From 873e9dedd0ee5d732294b7923e06c58d0e84a6ed Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 9 Jun 2025 13:44:26 +0530 Subject: [PATCH 1/4] arm: mach-k3: {am6/j7}*_hardware.h: Expose MCU R5 proc and device ids Currently the MCU R5 processor ids and device ids are only defined for R5 SPL Stage. Expose these ids always so that A72 SPL can utilize this information to shutdown MCU R5 Core 1 when booted in Split mode. Signed-off-by: Beleswar Padhi Reviewed-by: Neha Malcom Francis --- arch/arm/mach-k3/include/mach/am62_hardware.h | 4 ++-- arch/arm/mach-k3/include/mach/am62a_hardware.h | 4 ++-- arch/arm/mach-k3/include/mach/am62p_hardware.h | 4 ++-- arch/arm/mach-k3/include/mach/am64_hardware.h | 9 +++++---- arch/arm/mach-k3/include/mach/am6_hardware.h | 9 +++++---- arch/arm/mach-k3/include/mach/j721e_hardware.h | 9 +++++---- arch/arm/mach-k3/include/mach/j721s2_hardware.h | 9 +++++---- arch/arm/mach-k3/include/mach/j722s_hardware.h | 4 ++-- arch/arm/mach-k3/include/mach/j784s4_hardware.h | 9 +++++---- 9 files changed, 33 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index bcbc4821c82..d44342d43d4 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -158,8 +158,8 @@ static inline int k3_has_gpu(void) static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_AM62_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h index cd61abe0185..f3fd736f31b 100644 --- a/arch/arm/mach-k3/include/mach/am62a_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -90,8 +90,8 @@ static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_AM62A_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62p_hardware.h b/arch/arm/mach-k3/include/mach/am62p_hardware.h index 95af5c5c547..a310b52b45d 100644 --- a/arch/arm/mach-k3/include/mach/am62p_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62p_hardware.h @@ -141,8 +141,8 @@ static inline int k3_get_a53_max_frequency(void) static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_AM62P_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 44df887d5df..105b42986de 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -50,19 +50,20 @@ #define AM64X_DEV_RTI8 127 #define AM64X_DEV_RTI9 128 -#define AM64X_DEV_R5FSS0_CORE0 121 -#define AM64X_DEV_R5FSS0_CORE1 122 static const u32 put_device_ids[] = { AM64X_DEV_RTI9, AM64X_DEV_RTI8, }; +#endif + +#define AM64X_DEV_R5FSS0_CORE0 121 +#define AM64X_DEV_R5FSS0_CORE1 122 + static const u32 put_core_ids[] = { AM64X_DEV_R5FSS0_CORE1, AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 9913964c46b..8169584a372 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -43,19 +43,20 @@ #define AM6_DEV_MCU_RTI0 134 #define AM6_DEV_MCU_RTI1 135 -#define AM6_DEV_MCU_ARMSS0_CPU0 159 -#define AM6_DEV_MCU_ARMSS0_CPU1 245 static const u32 put_device_ids[] = { AM6_DEV_MCU_RTI0, AM6_DEV_MCU_RTI1, }; +#endif + +#define AM6_DEV_MCU_ARMSS0_CPU0 159 +#define AM6_DEV_MCU_ARMSS0_CPU1 245 + static const u32 put_core_ids[] = { AM6_DEV_MCU_ARMSS0_CPU1, AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_AM6_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index 2b5ec771e18..5bef309af0a 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -41,19 +41,20 @@ #define J721E_DEV_MCU_RTI0 262 #define J721E_DEV_MCU_RTI1 263 -#define J721E_DEV_MCU_ARMSS0_CPU0 250 -#define J721E_DEV_MCU_ARMSS0_CPU1 251 static const u32 put_device_ids[] = { J721E_DEV_MCU_RTI0, J721E_DEV_MCU_RTI1, }; +#endif + +#define J721E_DEV_MCU_ARMSS0_CPU0 250 +#define J721E_DEV_MCU_ARMSS0_CPU1 251 + static const u32 put_core_ids[] = { J721E_DEV_MCU_ARMSS0_CPU1, J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_J721E_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 8daea82a77e..82f076a45e0 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -41,19 +41,20 @@ #define J721S2_DEV_MCU_RTI0 295 #define J721S2_DEV_MCU_RTI1 296 -#define J721S2_DEV_MCU_ARMSS0_CPU0 284 -#define J721S2_DEV_MCU_ARMSS0_CPU1 285 static const u32 put_device_ids[] = { J721S2_DEV_MCU_RTI0, J721S2_DEV_MCU_RTI1, }; +#endif + +#define J721S2_DEV_MCU_ARMSS0_CPU0 284 +#define J721S2_DEV_MCU_ARMSS0_CPU1 285 + static const u32 put_core_ids[] = { J721S2_DEV_MCU_ARMSS0_CPU1, J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_J721S2_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h b/arch/arm/mach-k3/include/mach/j722s_hardware.h index 8d0bec22068..0c695134c28 100644 --- a/arch/arm/mach-k3/include/mach/j722s_hardware.h +++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h @@ -76,8 +76,8 @@ static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_J722S_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j784s4_hardware.h b/arch/arm/mach-k3/include/mach/j784s4_hardware.h index 0ffe238cdae..29a894baed3 100644 --- a/arch/arm/mach-k3/include/mach/j784s4_hardware.h +++ b/arch/arm/mach-k3/include/mach/j784s4_hardware.h @@ -41,19 +41,20 @@ #define J784S4_DEV_MCU_RTI0 367 #define J784S4_DEV_MCU_RTI1 368 -#define J784S4_DEV_MCU_ARMSS0_CPU0 346 -#define J784S4_DEV_MCU_ARMSS0_CPU1 347 static const u32 put_device_ids[] = { J784S4_DEV_MCU_RTI0, J784S4_DEV_MCU_RTI1, }; +#endif + +#define J784S4_DEV_MCU_ARMSS0_CPU0 346 +#define J784S4_DEV_MCU_ARMSS0_CPU1 347 + static const u32 put_core_ids[] = { J784S4_DEV_MCU_ARMSS0_CPU1, J784S4_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_J784S4_HARDWARE_H */ From 87a9c1f5a05a2eff0f2146bf9199145a00049a0e Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 9 Jun 2025 13:44:27 +0530 Subject: [PATCH 2/4] arch: mach-k3: common: Add support to shutdown MCU R5 Core 1 During boot, ROM can bring up the MCU R5F cores in either lockstep or split mode based on X509 certificate flags. If booted in split mode, core 0 will run DM firmware and second core sits in WFI. Add support to shut down core 1 so that other firmwares can later be loaded on them. The shutdown of MCU R5 Core 1 is invoked at A72 SPL init, as by that time Device Manager (DM) is up and running on R5 Core 0. The shutdown request of Core 1 is handled by Device Manager itself. Signed-off-by: Beleswar Padhi --- arch/arm/mach-k3/common.c | 69 +++++++++++++++++++++++++++ arch/arm/mach-k3/common.h | 1 + arch/arm/mach-k3/j721e/j721e_init.c | 9 +++- arch/arm/mach-k3/j721s2/j721s2_init.c | 7 +++ arch/arm/mach-k3/j784s4/j784s4_init.c | 7 +++ 5 files changed, 92 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index fc230f180d0..43ff114678a 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -31,6 +31,11 @@ #include #include +#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 +#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 +#define PROC_ID_MCU_R5FSS0_CORE1 0x02 +#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100 + #include struct ti_sci_handle *get_ti_sci_handle(void) @@ -328,3 +333,67 @@ void setup_qos(void) writel(qos_data[i].val, (uintptr_t)qos_data[i].reg); } #endif + +int __maybe_unused shutdown_mcu_r5_core1(void) +{ + struct ti_sci_handle *ti_sci = get_ti_sci_handle(); + struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops; + struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; + u32 dev_id_mcu_r5_core1 = put_core_ids[0]; + u64 boot_vector; + u32 cfg, ctrl, sts, halted; + int cluster_mode_lockstep, ret; + bool r_state = false, c_state = false; + + ret = proc_ops->proc_request(ti_sci, PROC_ID_MCU_R5FSS0_CORE1); + if (ret) { + printf("Unable to request processor control for MCU1_1 core, %d\n", + ret); + return ret; + } + + ret = dev_ops->is_on(ti_sci, dev_id_mcu_r5_core1, &r_state, &c_state); + if (ret) { + printf("Unable to get device status for MCU1_1 core, %d\n", ret); + return ret; + } + + ret = proc_ops->get_proc_boot_status(ti_sci, PROC_ID_MCU_R5FSS0_CORE1, + &boot_vector, &cfg, &ctrl, &sts); + if (ret) { + printf("Unable to get Processor boot status for MCU1_1 core, %d\n", + ret); + goto release_proc_ctrl; + } + + halted = !!(sts & PROC_BOOT_STATUS_FLAG_R5_WFI); + cluster_mode_lockstep = !!(cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP); + + /* + * Shutdown MCU R5F Core 1 only if: + * - cluster is booted in SplitMode + * - core is powered on + * - core is in WFI (halted) + */ + if (cluster_mode_lockstep || !c_state || !halted) { + ret = -EINVAL; + goto release_proc_ctrl; + } + + ret = proc_ops->set_proc_boot_ctrl(ti_sci, PROC_ID_MCU_R5FSS0_CORE1, + PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0); + if (ret) { + printf("Unable to Halt MCU1_1 core, %d\n", ret); + goto release_proc_ctrl; + } + + ret = dev_ops->put_device(ti_sci, dev_id_mcu_r5_core1); + if (ret) { + printf("Unable to assert reset on MCU1_1 core, %d\n", ret); + return ret; + } + +release_proc_ctrl: + proc_ops->proc_release(ti_sci, PROC_ID_MCU_R5FSS0_CORE1); + return ret; +} diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 02c74731fea..6e33f578151 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -49,6 +49,7 @@ enum k3_device_type get_device_type(void); struct ti_sci_handle *get_ti_sci_handle(void); void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); +int shutdown_mcu_r5_core1(void); #if (IS_ENABLED(CONFIG_K3_QOS)) void setup_qos(void); diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index f31c20f7ed6..edca2634fb9 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -296,9 +296,9 @@ void do_dt_magic(void) void board_init_f(ulong dummy) { + int ret; #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW) struct udevice *dev; - int ret; #endif /* * Cannot delay this further as there is a chance that @@ -371,6 +371,13 @@ void board_init_f(ulong dummy) preloader_console_init(); #endif + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */ + if (IS_ENABLED(CONFIG_ARM64)) { + ret = shutdown_mcu_r5_core1(); + if (ret) + printf("Unable to shutdown MCU R5 core 1, %d\n", ret); + } + /* Output System Firmware version info */ k3_sysfw_print_ver(); diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 5941fa26a95..6342161f830 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -230,6 +230,13 @@ void k3_spl_init(void) remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls)); } + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */ + if (IS_ENABLED(CONFIG_ARM64)) { + ret = shutdown_mcu_r5_core1(); + if (ret) + printf("Unable to shutdown MCU R5 core 1, %d\n", ret); + } + /* Output System Firmware version info */ k3_sysfw_print_ver(); } diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 787cf6261e4..2756accbe12 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -206,6 +206,13 @@ void k3_spl_init(void) writel(AUDIO_REFCLK1_DEFAULT, (uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL); + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */ + if (IS_ENABLED(CONFIG_ARM64)) { + ret = shutdown_mcu_r5_core1(); + if (ret) + printf("Unable to shutdown MCU R5 core 1, %d\n", ret); + } + /* Output System Firmware version info */ k3_sysfw_print_ver(); } From 92e77d3768ae968158a5b76e023b86cf6b7d72bd Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 9 Jun 2025 13:44:28 +0530 Subject: [PATCH 3/4] remoteproc: k3-r5: Acquire processor control before reset ops Acquire processor control before doing core reset operations in probe routine. Release the control afterwards, so that it can be acquired during core loading operations. Signed-off-by: Beleswar Padhi Reviewed-by: Neha Malcom Francis --- drivers/remoteproc/ti_k3_r5f_rproc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 57268e7f8ff..f4bab6868ee 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -834,8 +834,14 @@ static int k3_r5f_probe(struct udevice *dev) return 0; } + ret = k3_r5f_proc_request(core); + if (ret) + return ret; + /* Make sure Local reset is asserted. Redundant? */ reset_assert(&core->reset); + + ti_sci_proc_release(&core->tsp); } ret = k3_r5f_rproc_configure(core); From 574321414fa94f1f66e6ce34807a997ffb72ec55 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 9 Jun 2025 13:44:29 +0530 Subject: [PATCH 4/4] board: ti: j7*: Add firmware for MCU R5 core1 Link the default firmware in the environment variable for MCU R5 core1 for all J7 platforms. Signed-off-by: Beleswar Padhi Reviewed-by: Neha Malcom Francis --- board/ti/j7200/j7200.env | 2 +- board/ti/j721e/j721e.env | 2 +- board/ti/j721s2/j721s2.env | 2 +- board/ti/j784s4/j784s4.env | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env index 6cc92bf0d8d..292fc72fd58 100644 --- a/board/ti/j7200/j7200.env +++ b/board/ti/j7200/j7200.env @@ -36,5 +36,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J7200_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw +rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index e5b4225b3ce..ead7fbdb212 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -38,5 +38,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J721E_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw +rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index a6b22550809..abd4faea6ee 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -24,6 +24,6 @@ name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw #endif rd_spec=- -rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw +rproc_fw_binaries= 1 /lib/firmware/j721s2-mcu-r5f0_1-fw 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 9e1741be424..2f1a5f549d1 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -21,7 +21,7 @@ bootdir=/boot rd_spec=- #if CONFIG_TARGET_J784S4_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw +rproc_fw_binaries= 1 /lib/firmware/j784s4-mcu-r5f0_1-fw 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw #elif CONFIG_TARGET_J742S2_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw +rproc_fw_binaries= 1 /lib/firmware/j742s2-mcu-r5f0_1-fw 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw #endif