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https://source.denx.de/u-boot/u-boot.git
synced 2026-06-09 13:16:40 +03:00
ARM: dts: renesas: Drop R8A779H0 V4M DTs with OF_UPSTREAM counterparts
Remove R8A779H0 V4M DTs which are now replaced by OF_UPSTREAM counterparts. No functional change expected. This patch finalizes OF_UPSTREAM conversion of R8A779H0 V4M which DTs landed in Linux 6.9 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Marek Vasut
@@ -958,9 +958,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
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imxrt1020-evk.dtb \
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imxrt1170-evk.dtb \
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dtb-$(CONFIG_RCAR_GEN4) += \
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r8a779h0-gray-hawk.dtb
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dtb-$(CONFIG_TARGET_RZG2L) += \
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r9a07g044l2-smarc.dts
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@@ -1,166 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Gray Hawk CPU board
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "r8a779h0.dtsi"
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/ {
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model = "Renesas Gray Hawk CPU board";
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compatible = "renesas,grayhawk-cpu", "renesas,r8a779h0";
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aliases {
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ethernet0 = &avb0;
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serial0 = &hscif0;
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};
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chosen {
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bootargs = "ignore_loglevel";
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stdout-path = "serial0:921600n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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memory@480000000 {
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device_type = "memory";
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reg = <0x4 0x80000000 0x1 0x80000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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tx-internal-delay-ps = <2000>;
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status = "okay";
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio7>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&hscif0 {
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uart-has-rtscts;
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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eeprom@50 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "cpu-board";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&mmc0 {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-1 = <&mmc_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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bus-width = <8>;
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no-sd;
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no-sdio;
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non-removable;
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full-pwr-cycle-in-suspend;
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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avb0_pins: avb0 {
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mux {
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groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
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"avb0_txcrefclk";
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function = "avb0";
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};
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pins_mdio {
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groups = "avb0_mdio";
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drive-strength = <21>;
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};
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pins_mii {
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groups = "avb0_rgmii";
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drive-strength = <21>;
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};
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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mmc_pins: mmc {
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groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
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function = "mmc";
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power-source = <1800>;
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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};
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&scif_clk {
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clock-frequency = <24000000>;
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};
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@@ -1,15 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car V4M Gray Hawk CSI/DSI sub-board
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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&i2c0 {
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eeprom@52 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "csi-dsi-sub-board-id";
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reg = <0x52>;
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pagesize = <8>;
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};
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};
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@@ -1,15 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car V4M Gray Hawk Ethernet sub-board
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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&i2c0 {
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eeprom@53 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "ethernet-sub-board-id";
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reg = <0x53>;
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pagesize = <8>;
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};
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};
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@@ -1,41 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the Gray Hawk board
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include "r8a779h0-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &rpc;
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};
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};
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&pfc {
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qspi0_pins: qspi0 {
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groups = "qspi0_ctrl", "qspi0_data4";
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function = "qspi0";
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};
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};
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&rpc {
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pinctrl-0 = <&qspi0_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <40000000>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "s25fs512s", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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@@ -1,25 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Gray Hawk CPU and BreakOut boards
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a779h0-gray-hawk-cpu.dtsi"
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#include "r8a779h0-gray-hawk-csi-dsi.dtsi"
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#include "r8a779h0-gray-hawk-ethernet.dtsi"
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/ {
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model = "Renesas Gray Hawk CPU and Breakout boards based on r8a779h0";
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compatible = "renesas,gray-hawk-breakout", "renesas,gray-hawk-cpu", "renesas,r8a779h0";
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};
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&i2c0 {
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eeprom@51 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "breakout-board";
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reg = <0x51>;
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pagesize = <8>;
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};
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};
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@@ -1,27 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include "r8a779x-u-boot.dtsi"
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/ {
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soc {
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rpc: spi@ee200000 {
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compatible = "renesas,r8a779h0-rpc-if", "renesas,rcar-gen4-rpc-if";
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reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 629>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 629>;
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bank-width = <2>;
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num-cs = <1>;
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status = "disabled";
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};
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};
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};
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&extalr_clk {
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bootph-all;
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};
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@@ -1,460 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car V4M (R8A779H0) SoC
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/renesas,r8a779h0-sysc.h>
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/ {
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compatible = "renesas,r8a779h0";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a76_0: cpu@0 {
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compatible = "arm,cortex-a76";
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reg = <0>;
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device_type = "cpu";
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power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
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};
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};
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extal_clk: extal-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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pmu-a76 {
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compatible = "arm,cortex-a76-pmu";
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interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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pfc: pinctrl@e6050000 {
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compatible = "renesas,pfc-r8a779h0";
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reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
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<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
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<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
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<0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
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};
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gpio0: gpio@e6050180 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6050180 0 0x54>;
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interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 19>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 915>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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};
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gpio1: gpio@e6050980 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6050980 0 0x54>;
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interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 30>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 915>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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};
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gpio2: gpio@e6058180 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6058180 0 0x54>;
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interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 20>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 916>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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};
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gpio3: gpio@e6058980 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6058980 0 0x54>;
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interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 916>;
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power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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};
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||||
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gpio4: gpio@e6060180 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6060180 0 0x54>;
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interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
|
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#gpio-cells = <2>;
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gpio-controller;
|
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gpio-ranges = <&pfc 0 128 25>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
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clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
|
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};
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gpio5: gpio@e6060980 {
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compatible = "renesas,gpio-r8a779h0",
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"renesas,rcar-gen4-gpio";
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reg = <0 0xe6060980 0 0x54>;
|
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interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
|
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#gpio-cells = <2>;
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gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 21>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6061180 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6061180 0 0x54>;
|
||||
interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 21>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6061980 {
|
||||
compatible = "renesas,gpio-r8a779h0",
|
||||
"renesas,rcar-gen4-gpio";
|
||||
reg = <0 0xe6061980 0 0x54>;
|
||||
interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 224 21>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a779h0-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x4000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a779h0-rst";
|
||||
reg = <0 0xe6160000 0 0x4000>;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a779h0-sysc";
|
||||
reg = <0 0xe6180000 0 0x4000>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe6500000 0 0x40>;
|
||||
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 518>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 518>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@e6508000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 519>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 519>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@e6510000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe6510000 0 0x40>;
|
||||
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 520>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 520>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e66d0000 {
|
||||
compatible = "renesas,i2c-r8a779h0",
|
||||
"renesas,rcar-gen4-i2c";
|
||||
reg = <0 0xe66d0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 521>;
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 521>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e6540000 {
|
||||
compatible = "renesas,hscif-r8a779h0",
|
||||
"renesas,rcar-gen4-hscif", "renesas,hscif";
|
||||
reg = <0 0xe6540000 0 0x60>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>,
|
||||
<&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 514>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb0: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a779h0",
|
||||
"renesas,etheravb-rcar-gen4";
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 211>;
|
||||
power-domains = <&sysc R8A779H0_PD_C4>;
|
||||
resets = <&cpg 211>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb1: ethernet@e6810000 {
|
||||
compatible = "renesas,etheravb-r8a779h0",
|
||||
"renesas,etheravb-rcar-gen4";
|
||||
reg = <0 0xe6810000 0 0x800>;
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 212>;
|
||||
power-domains = <&sysc R8A779H0_PD_C4>;
|
||||
resets = <&cpg 212>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avb2: ethernet@e6820000 {
|
||||
compatible = "renesas,etheravb-r8a779h0",
|
||||
"renesas,etheravb-rcar-gen4";
|
||||
reg = <0 0xe6820000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 213>;
|
||||
power-domains = <&sysc R8A779H0_PD_C4>;
|
||||
resets = <&cpg 213>;
|
||||
phy-mode = "rgmii";
|
||||
rx-internal-delay-ps = <0>;
|
||||
tx-internal-delay-ps = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a779h0",
|
||||
"renesas,rcar-gen4-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 706>,
|
||||
<&cpg CPG_CORE R8A779H0_CLK_SD0H>;
|
||||
clock-names = "core", "clkh";
|
||||
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 706>;
|
||||
max-frequency = <200000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1000000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x110000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
||||
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user