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riscv: dts: th1520: Add DRAM controller

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Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
devicetree blob.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Yao Zi
2025-05-13 09:05:00 +00:00
committed by Leo Yu-Chi Liang
parent 17582da96c
commit 64735e56aa
1 changed files with 10 additions and 0 deletions
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10
arch/riscv/dts/th1520.dtsi
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@@ -371,6 +371,16 @@
status = "disabled"; status = "disabled";
}; };
ddrc: ddrc@fffd000000 {
compatible = "thead,th1520-ddrc";
reg = <0xff 0xfd000000 0x0 0x1000000>,
<0xff 0xfe000000 0x0 0x1000000>,
<0xff 0xff000000 0x0 0x4000>,
<0xff 0xff005000 0x0 0x1000>;
reg-names = "phy-0", "phy-1", "ctrl", "sys";
bootph-pre-ram;
};
timer4: timer@ffffc33000 { timer4: timer@ffffc33000 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33000 0x0 0x14>; reg = <0xff 0xffc33000 0x0 0x14>;