From db95933996603814ba648ac6bae4eca07b4061ef Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 18:44:36 +0100 Subject: [PATCH 1/7] sh: Assure end of U-Boot is at 8-byte aligned offset Make sure the end of U-Boot is at 8-byte aligned offset, not 4-byte aligned offset. This allows safely appending DT at the end of U-Boot with the guarantee that the DT will be at 8-byte aligned offset. This 8-byte alignment is now checked by newer libfdt 1.7.2 . Signed-off-by: Marek Vasut --- arch/sh/cpu/u-boot.lds | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index c31deecec65..81526f5bd23 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -72,6 +72,7 @@ SECTIONS __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); + . = ALIGN(8); } >ram PROVIDE (__init_end = .); @@ -83,7 +84,7 @@ SECTIONS .bss : { *(.bss) - . = ALIGN(4); + . = ALIGN(8); } >ram PROVIDE (bss_end = .); PROVIDE (__bss_end = .); From af96395a821c4c87e2026351b5d05de9726df1ef Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Oct 2025 17:33:07 +0100 Subject: [PATCH 2/7] clk: renesas: Introduce temporary compound clock for SCP compatibility The current state of SCP on Renesas R-Car Gen5 is not yet final and is still missing full clock control, the clock control is exposed as separate enable/disable and rate controls. Temporarily introduce custom local compound clock, which are used as an adaptation layer between U-Boot clock tree and current state of SCP, and which bind two SCP clock into a single compound clock, which provides both enable/disable and rate controls. This is mainly meant to be used by SD/eMMC controller, to allow the driver to both turn its clock on and off, and also obtain the current clock rate. This is going to be removed once the SCP clock protocol solidifies. Signed-off-by: Marek Vasut --- drivers/clk/renesas/Makefile | 4 ++ drivers/clk/renesas/compound-clock.c | 92 ++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 drivers/clk/renesas/compound-clock.c diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 6c742553091..354035baf2d 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -26,3 +26,7 @@ obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o + +# Temporary stub clock used for SCP compatibility. +# This is going to be removed once SCP solidifies. +obj-$(CONFIG_R8A78000) += compound-clock.o diff --git a/drivers/clk/renesas/compound-clock.c b/drivers/clk/renesas/compound-clock.c new file mode 100644 index 00000000000..499a2598833 --- /dev/null +++ b/drivers/clk/renesas/compound-clock.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Marek Vasut + */ + +#define LOG_CATEGORY UCLASS_CLK + +#include +#include +#include +#include +#include + +struct clk_compound_rate { + struct clk clk; /* This clock */ + struct clk mdlc; /* MDLC parent module clock */ + struct clk per; /* Peripheral parent clock */ +}; + +static struct clk_compound_rate *to_clk_compound_rate(struct clk *clk) +{ + return (struct clk_compound_rate *)dev_get_plat(clk->dev); +} + +static int clk_compound_rate_enable(struct clk *clk) +{ + struct clk_compound_rate *cc = to_clk_compound_rate(clk); + + return clk_enable(&cc->mdlc); +} + +static int clk_compound_rate_disable(struct clk *clk) +{ + struct clk_compound_rate *cc = to_clk_compound_rate(clk); + + return clk_disable(&cc->mdlc); +} + +static ulong clk_compound_rate_get_rate(struct clk *clk) +{ + struct clk_compound_rate *cc = to_clk_compound_rate(clk); + + return clk_get_rate(&cc->per); +} + +static ulong clk_compound_rate_set_rate(struct clk *clk, ulong rate) +{ + return 0; /* Set rate is not forwarded to SCP */ +} + +const struct clk_ops clk_compound_rate_ops = { + .enable = clk_compound_rate_enable, + .disable = clk_compound_rate_disable, + .get_rate = clk_compound_rate_get_rate, + .set_rate = clk_compound_rate_set_rate, +}; + +static int clk_compound_rate_of_to_plat(struct udevice *dev) +{ + struct clk_compound_rate *cc = (struct clk_compound_rate *)dev_get_plat(dev); + struct clk *clk = &cc->clk; + int ret; + + clk->dev = dev; + clk->id = CLK_ID(dev, 0); + clk->enable_count = 0; + + ret = clk_get_by_index(dev, 0, &cc->mdlc); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &cc->per); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id clk_compound_rate_match[] = { + { .compatible = "renesas,compound-clock", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_compound_clock) = { + .name = "compound-clock", + .id = UCLASS_CLK, + .of_match = clk_compound_rate_match, + .of_to_plat = clk_compound_rate_of_to_plat, + .plat_auto = sizeof(struct clk_compound_rate), + .ops = &clk_compound_rate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; From 5353fc464f00b2bf8e69ddbbcb4f1704566bcde2 Mon Sep 17 00:00:00 2001 From: Tuyen Dang Date: Mon, 27 Oct 2025 17:39:17 +0100 Subject: [PATCH 3/7] mailbox: renesas: Add Renesas MFIS Multifunctional Interface mailbox driver Add support for the Renesas MFIS mailbox, which provides an interface between the different CPU Cores, such as AP System Core domain and the Realtime Core domain, SCP Core domain and AP System Core domain or Realtime Core domain and AP System Core domain or Realtime Core domain. Signed-off-by: Tuyen Dang Signed-off-by: Marek Vasut # Update the driver [Marek: Rename the driver to renesas-mfis, simplify the driver. Always use only one TX channel and no RX channel, drop all unnecessary code. Perform 1ms delay in send callback which is perfectly fine to do in U-Boot which does RX polling] --- drivers/mailbox/Kconfig | 10 ++++++ drivers/mailbox/Makefile | 1 + drivers/mailbox/renesas-mfis.c | 59 ++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100644 drivers/mailbox/renesas-mfis.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index f9531c1627c..cfd2a3be3fd 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -66,6 +66,16 @@ config K3_SEC_PROXY Select this driver if your platform has support for this hardware block. +config RCAR_MFIS_MBOX + bool "Renesas MFIS Multifunctional Interface mailbox driver" + depends on DM_MAILBOX && ARCH_RENESAS + help + This enables support for the Renesas MFIS mailbox module, which + provides an interface between the different CPU Cores, such as AP + System Core domain and the Realtime Core domain, SCP Core domain + and AP System Core domain or Realtime Core domain and AP System + Core domain or Realtime Core domain. + config ZYNQMP_IPI bool "Xilinx ZynqMP IPI controller support" depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index b54fbdfff15..b3a36691497 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -12,4 +12,5 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o +obj-$(CONFIG_RCAR_MFIS_MBOX) += renesas-mfis.o obj-$(CONFIG_ZYNQMP_IPI) += zynqmp-ipi.o diff --git a/drivers/mailbox/renesas-mfis.c b/drivers/mailbox/renesas-mfis.c new file mode 100644 index 00000000000..1e9e8285974 --- /dev/null +++ b/drivers/mailbox/renesas-mfis.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. + */ + +#include +#include +#include +#include + +#define COM 0x0 +#define IIR BIT(0) + +struct mfis_priv { + void __iomem *tx_base; +}; + +static int mfis_send(struct mbox_chan *chan, const void *data) +{ + struct mfis_priv *mfis = dev_get_priv(chan->dev); + + writel(IIR, mfis->tx_base + COM); + + /* Give the remote side some time. */ + mdelay(1); + + writel(0, mfis->tx_base + COM); + + return 0; +} + +struct mbox_ops mfis_mbox_ops = { + .send = mfis_send, +}; + +static int mfis_mbox_probe(struct udevice *dev) +{ + struct mfis_priv *mbox = dev_get_priv(dev); + + mbox->tx_base = dev_read_addr_index_ptr(dev, 0); + if (!mbox->tx_base) + return -ENODEV; + + return 0; +} + +static const struct udevice_id mfis_mbox_of_match[] = { + { .compatible = "renesas,mfis-mbox", }, + {}, +}; + +U_BOOT_DRIVER(renesas_mfis) = { + .name = "renesas-mfis", + .id = UCLASS_MAILBOX, + .of_match = mfis_mbox_of_match, + .probe = mfis_mbox_probe, + .priv_auto = sizeof(struct mfis_priv), + .ops = &mfis_mbox_ops, +}; From e84a0bbefe19496b31b21c74133eedeefd1cc11c Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 2 Dec 2025 19:34:14 +0100 Subject: [PATCH 4/7] arm64: renesas: Add Renesas R-Car Gen5 infrastructure Add initial changes to support Renesas R-Car Gen5 SoC. Introduce Kconfig entries, architecture headers and PRR IDs for Renesas R-Car Gen5 and R-Car X5H R8A78000 SoC. Add Makefile change to produce u-boot-elf.srec with correct offset for installation tooling. Update MAINTAINERS entry to cover both r8a77nnn and r8a78nnn . Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- Makefile | 9 ++++ arch/arm/mach-renesas/Kconfig | 5 +++ arch/arm/mach-renesas/Kconfig.64 | 1 + arch/arm/mach-renesas/Kconfig.rcar5 | 12 +++++ arch/arm/mach-renesas/Makefile | 1 + arch/arm/mach-renesas/cpu_info-rcar.c | 8 +++- arch/arm/mach-renesas/cpu_info.c | 1 + .../include/mach/rcar-gen5-base.h | 44 +++++++++++++++++++ arch/arm/mach-renesas/include/mach/renesas.h | 3 ++ board/renesas/MAINTAINERS | 2 +- 10 files changed, 83 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-renesas/Kconfig.rcar5 create mode 100644 arch/arm/mach-renesas/include/mach/rcar-gen5-base.h diff --git a/Makefile b/Makefile index 375af33e5e7..1a613e70b27 100644 --- a/Makefile +++ b/Makefile @@ -1499,6 +1499,15 @@ ifeq ($(CONFIG_POSITION_INDEPENDENT)$(CONFIG_RCAR_GEN3),yy) OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x50000000 endif +ifeq ($(CONFIG_POSITION_INDEPENDENT)$(CONFIG_RCAR_GEN5),yy) +# The flash_writer tool and previous recovery tools +# require the SREC load address to be 0x8e30_0000 . +# The PIE U-Boot build sets the address to 0x0, so +# override the address back to make u-boot-elf.srec +# compatible with the recovery tools. +OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x8e300000 +endif + u-boot-elf.srec: u-boot.elf FORCE $(call if_changed,zobjcopy) diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig index 8f4fba4615c..fa4e312a4dd 100644 --- a/arch/arm/mach-renesas/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -46,6 +46,11 @@ config RCAR_GEN4 select RCAR_64 select PINCTRL_PFC +config RCAR_GEN5 + bool "Renesas ARM SoCs R-Car Gen5 (64bit)" + select RCAR_64 + select PINCTRL_PFC + config RZA1 prompt "Renesas ARM SoCs RZ/A1 (32bit)" select CPU_V7A diff --git a/arch/arm/mach-renesas/Kconfig.64 b/arch/arm/mach-renesas/Kconfig.64 index b5067d0a8f0..1b1ed88339b 100644 --- a/arch/arm/mach-renesas/Kconfig.64 +++ b/arch/arm/mach-renesas/Kconfig.64 @@ -8,5 +8,6 @@ config OF_LIBFDT_OVERLAY source "arch/arm/mach-renesas/Kconfig.rcar3" source "arch/arm/mach-renesas/Kconfig.rcar4" +source "arch/arm/mach-renesas/Kconfig.rcar5" endif diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 new file mode 100644 index 00000000000..34c0ae8772b --- /dev/null +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -0,0 +1,12 @@ +if RCAR_GEN5 + +menu "Select Target SoC" + +config R8A78000 + bool "Renesas SoC R8A78000" + select GICV3 + imply PINCTRL_PFC_R8A78000 + +endmenu + +endif diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 9165ceab4a3..c0454fffa48 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o +obj-$(CONFIG_RCAR_GEN5) += cpu_info-rcar.o memmap-gen3.o obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o diff --git a/arch/arm/mach-renesas/cpu_info-rcar.c b/arch/arm/mach-renesas/cpu_info-rcar.c index 74140fd38ab..a6e0b739e55 100644 --- a/arch/arm/mach-renesas/cpu_info-rcar.c +++ b/arch/arm/mach-renesas/cpu_info-rcar.c @@ -15,8 +15,12 @@ static u32 renesas_get_prr(void) { - if (IS_ENABLED(CONFIG_RCAR_64)) - return readl(0xFFF00044); + if (IS_ENABLED(CONFIG_RCAR_64)) { + if (IS_ENABLED(CONFIG_RCAR_GEN5)) + return readl(0x189E0044); + else + return readl(0xFFF00044); + } return readl(0xFF000044); } diff --git a/arch/arm/mach-renesas/cpu_info.c b/arch/arm/mach-renesas/cpu_info.c index 2f9a4374a96..f040d732a51 100644 --- a/arch/arm/mach-renesas/cpu_info.c +++ b/arch/arm/mach-renesas/cpu_info.c @@ -72,6 +72,7 @@ static const struct { { RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" }, { RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" }, { RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" }, + { RMOBILE_CPU_TYPE_R8A78000, "R8A78000" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h new file mode 100644 index 00000000000..f9af3ef885a --- /dev/null +++ b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __ASM_ARCH_RCAR_GEN5_BASE_H +#define __ASM_ARCH_RCAR_GEN5_BASE_H + +/* + * R-Car (R8A78000) I/O Addresses + */ +#define TMU_BASE 0x1C030000 + +/* Arm Generic Timer */ +#define CNTCR_BASE 0x1C000FFF /* Region 0 */ +#define CNTFID0 (CNTCR_BASE + 0x020) +#define CNTCR_EN BIT(0) + +/* Reset */ +#define RST_BASE 0xC1320000 /* Domain0 */ +#define RST_SWSRES1A (RST_BASE + 0x410) +#define RST_WDTRSTCR (RST_BASE + 0x420) +#define RST_RWDT_RSTMSK BIT(0) +#define RST_WWDT_RSTMSK BIT(2) +#define RST_RESKCPROT0 (RST_BASE + 0x4F0) +#define RST_KCPROT_DIS 0xA5A5A501 + +/* GICv4 */ +/* Distributor Registers */ +#define GICD_BASE 0x38000000 +#define GICR_BASE (GICR_LPI_BASE) + +/* ReDistributor Registers for Control and Physical LPIs */ +#define GICR_LPI_BASE 0x38080000 +#define GICR_WAKER 0x0014 +#define GICR_PWRR 0x0024 +#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER) +#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR) + +/* ReDistributor Registers for SGIs and PPIs */ +#define GICR_SGI_BASE 0x38090000 +#define GICR_IGROUPR0 0x0080 + +#endif /* __ASM_ARCH_RCAR_GEN5_BASE_H */ diff --git a/arch/arm/mach-renesas/include/mach/renesas.h b/arch/arm/mach-renesas/include/mach/renesas.h index c69c764adb8..deaeffedef9 100644 --- a/arch/arm/mach-renesas/include/mach/renesas.h +++ b/arch/arm/mach-renesas/include/mach/renesas.h @@ -16,6 +16,8 @@ #include #elif defined(CONFIG_RCAR_GEN4) #include +#elif defined(CONFIG_RCAR_GEN5) +#include #elif defined(CONFIG_R7S72100) #elif defined(CONFIG_RZG2L) #include @@ -42,6 +44,7 @@ #define RENESAS_CPU_TYPE_R8A779F0 0x5A #define RENESAS_CPU_TYPE_R8A779G0 0x5C #define RENESAS_CPU_TYPE_R8A779H0 0x5D +#define RMOBILE_CPU_TYPE_R8A78000 0x60 #define RENESAS_CPU_TYPE_R9A07G044L 0x9A070440 #ifndef __ASSEMBLY__ diff --git a/board/renesas/MAINTAINERS b/board/renesas/MAINTAINERS index 13551cdd2b4..8571bb02576 100644 --- a/board/renesas/MAINTAINERS +++ b/board/renesas/MAINTAINERS @@ -6,7 +6,7 @@ N: grpeach N: r2dplus N: r7s72100 N: r8a66597 -N: r8a77 +N: r8a7[78] N: r9a0[0-9]g N: rcar N: renesas From b546189a4b515ba5aaf542558e9778d7d2a05b4e Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 2 Dec 2025 19:34:15 +0100 Subject: [PATCH 5/7] arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 SoC DTs Add initial device trees for Renesas R-Car X5H R8A78000 SoC. Include very basic clock, reset, power domain headers which are used to control supported peripherals via SCMI / SCP. The headers are currently kept limited to avoid possible ABI break. A lot of clock are still stubbed via fixed-clock, this is going to be gradually removed over time, as more of the platform is upstreamed. Signed-off-by: Hai Pham Signed-off-by: Khanh Le Signed-off-by: Marek Vasut --- arch/arm/dts/r8a78000-u-boot.dtsi | 139 ++ arch/arm/dts/r8a78000.dtsi | 1164 +++++++++++++++++ .../dt-bindings/clock/r8a78000-clock-scmi.h | 46 + .../dt-bindings/power/r8a78000-power-scmi.h | 25 + .../dt-bindings/reset/r8a78000-reset-scmi.h | 33 + 5 files changed, 1407 insertions(+) create mode 100644 arch/arm/dts/r8a78000-u-boot.dtsi create mode 100644 arch/arm/dts/r8a78000.dtsi create mode 100644 include/dt-bindings/clock/r8a78000-clock-scmi.h create mode 100644 include/dt-bindings/power/r8a78000-power-scmi.h create mode 100644 include/dt-bindings/reset/r8a78000-reset-scmi.h diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi new file mode 100644 index 00000000000..1bc73252430 --- /dev/null +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot on R-Car R8A78000 SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/ { + soc { + bootph-all; + }; + + /* Placeholder clock until the clock provider is in place */ + clk_stub_gpio: clk-stub-gpio { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + clk_stub_i2c0: clk-stub-i2c0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; + + clk_stub_i2c1: clk-stub-i2c1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + clk_stub_mmc: clk-stub-mmc { + compatible = "renesas,compound-clock"; + #clock-cells = <0>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>, + <&scmi_clk 1691>; + clock-names = "mdlc", "per"; + }; +}; + +&cpg { + bootph-all; +}; + +&extal_clk { + bootph-all; +}; + +&extalr_clk { + bootph-all; +}; + +&gpio0 { + clocks = <&clk_stub_gpio>; +}; + +&gpio1 { + clocks = <&clk_stub_gpio>; +}; + +&gpio2 { + clocks = <&clk_stub_gpio>; +}; + +&gpio3 { + clocks = <&clk_stub_gpio>; +}; + +&gpio4 { + clocks = <&clk_stub_gpio>; +}; + +&gpio5 { + clocks = <&clk_stub_gpio>; +}; + +&gpio6 { + clocks = <&clk_stub_gpio>; +}; + +&gpio7 { + clocks = <&clk_stub_gpio>; +}; + +&gpio8 { + clocks = <&clk_stub_gpio>; +}; + +&gpio9 { + clocks = <&clk_stub_gpio>; +}; + +&gpio10 { + clocks = <&clk_stub_gpio>; +}; + +&i2c0 { + clocks = <&clk_stub_i2c0>; +}; + +&i2c1 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c2 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c3 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c4 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c5 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c6 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c7 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c8 { + clocks = <&clk_stub_i2c1>; +}; + +&mmc0 { + clocks = <&clk_stub_mmc>; +}; + +&prr { + bootph-all; +}; diff --git a/arch/arm/dts/r8a78000.dtsi b/arch/arm/dts/r8a78000.dtsi new file mode 100644 index 00000000000..0d0c24503e2 --- /dev/null +++ b/arch/arm/dts/r8a78000.dtsi @@ -0,0 +1,1164 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car X5H (R8A78000) SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a78000"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a720_0>; + }; + core1 { + cpu = <&a720_1>; + }; + core2 { + cpu = <&a720_2>; + }; + core3 { + cpu = <&a720_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a720_4>; + }; + core1 { + cpu = <&a720_5>; + }; + core2 { + cpu = <&a720_6>; + }; + core3 { + cpu = <&a720_7>; + }; + }; + + cluster2 { + core0 { + cpu = <&a720_8>; + }; + core1 { + cpu = <&a720_9>; + }; + core2 { + cpu = <&a720_10>; + }; + core3 { + cpu = <&a720_11>; + }; + }; + + cluster3 { + core0 { + cpu = <&a720_12>; + }; + core1 { + cpu = <&a720_13>; + }; + core2 { + cpu = <&a720_14>; + }; + core3 { + cpu = <&a720_15>; + }; + }; + + cluster4 { + core0 { + cpu = <&a720_16>; + }; + core1 { + cpu = <&a720_17>; + }; + core2 { + cpu = <&a720_18>; + }; + core3 { + cpu = <&a720_19>; + }; + }; + + cluster5 { + core0 { + cpu = <&a720_20>; + }; + core1 { + cpu = <&a720_21>; + }; + core2 { + cpu = <&a720_22>; + }; + core3 { + cpu = <&a720_23>; + }; + }; + + cluster6 { + core0 { + cpu = <&a720_24>; + }; + core1 { + cpu = <&a720_25>; + }; + core2 { + cpu = <&a720_26>; + }; + core3 { + cpu = <&a720_27>; + }; + }; + + cluster7 { + core0 { + cpu = <&a720_28>; + }; + core1 { + cpu = <&a720_29>; + }; + core2 { + cpu = <&a720_30>; + }; + core3 { + cpu = <&a720_31>; + }; + }; + }; + + a720_0: cpu@0 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x0>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_0>; + }; + + a720_1: cpu@100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_1>; + }; + + a720_2: cpu@200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_2>; + }; + + a720_3: cpu@300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_3>; + }; + + a720_4: cpu@10000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_4>; + }; + + a720_5: cpu@10100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_5>; + }; + + a720_6: cpu@10200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_6>; + }; + + a720_7: cpu@10300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_7>; + }; + + a720_8: cpu@20000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_8>; + }; + + a720_9: cpu@20100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_9>; + }; + + a720_10: cpu@20200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_10>; + }; + + a720_11: cpu@20300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_11>; + }; + + a720_12: cpu@30000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_12>; + }; + + a720_13: cpu@30100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_13>; + }; + + a720_14: cpu@30200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_14>; + }; + + a720_15: cpu@30300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_15>; + }; + + a720_16: cpu@40000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_16>; + }; + + a720_17: cpu@40100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_17>; + }; + + a720_18: cpu@40200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_18>; + }; + + a720_19: cpu@40300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_19>; + }; + + a720_20: cpu@50000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_20>; + }; + + a720_21: cpu@50100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_21>; + }; + + a720_22: cpu@50200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_22>; + }; + + a720_23: cpu@50300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_23>; + }; + + a720_24: cpu@60000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_24>; + }; + + a720_25: cpu@60100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_25>; + }; + + a720_26: cpu@60200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_26>; + }; + + a720_27: cpu@60300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_27>; + }; + + a720_28: cpu@70000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_28>; + }; + + a720_29: cpu@70100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_29>; + }; + + a720_30: cpu@70200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_30>; + }; + + a720_31: cpu@70300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_31>; + }; + + L2_CA720_0: cache-controller-200 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_1: cache-controller-201 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_2: cache-controller-202 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_3: cache-controller-203 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_4: cache-controller-204 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_5: cache-controller-205 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_6: cache-controller-206 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_7: cache-controller-207 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_8: cache-controller-208 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_9: cache-controller-209 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_10: cache-controller-210 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_11: cache-controller-211 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_12: cache-controller-212 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_13: cache-controller-213 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_14: cache-controller-214 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_15: cache-controller-215 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_16: cache-controller-216 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_17: cache-controller-217 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_18: cache-controller-218 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_19: cache-controller-219 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_20: cache-controller-220 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_21: cache-controller-221 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_22: cache-controller-222 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_23: cache-controller-223 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_24: cache-controller-224 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_25: cache-controller-225 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_26: cache-controller-226 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_27: cache-controller-227 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_28: cache-controller-228 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_29: cache-controller-229 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_30: cache-controller-230 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_31: cache-controller-231 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L3_CA720_0: cache-controller-30 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_1: cache-controller-31 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_2: cache-controller-32 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_3: cache-controller-33 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_4: cache-controller-34 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_5: cache-controller-35 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_6: cache-controller-36 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_7: cache-controller-37 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + }; + + /* + * In the early phase, there is no clock control support, + * so assume that the clocks are enabled by default. + * Therefore, dummy clocks are used. + */ + dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <66666000>; + }; + + dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266660000>; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* clock-frequency must be set on board */ + }; + + extalr_clk: extalr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* clock-frequency must be set on board */ + }; + + firmware { + scmi { + compatible = "arm,scmi"; + arm,poll-transport; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0>, <&mailbox 1>; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; /* optional */ + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mailbox: mfis_mbox@18842000 { + compatible = "renesas,mfis-mbox"; + #mbox-cells = <1>; + reg = <0 0x18842004 0 0x8>; + interrupts = ; + }; + + prr: chipid@189e0044 { + compatible = "renesas,prr"; + reg = <0 0x189e0044 0 4>; + }; + + /* Application Processors manage View-1 of a GIC-720AE */ + gic: interrupt-controller@39000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x39000000 0 0x10000>, + <0 0x39080000 0 0x800000>; + interrupts = ; + }; + + pfc: pinctrl@c0400000 { + compatible = "renesas,pfc-r8a78000"; + reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, + <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, + <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, + <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, + <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, + <0 0xc9b00800 0 0x104>; + }; + + scif0: serial@c0700000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0700000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + scif1: serial@c0704000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0704000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "okay"; + }; + + scif3: serial@c0708000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0708000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + scif4: serial@c070c000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc070c000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + mmc0: mmc@c0880000 { + compatible = "renesas,rcar-gen5-sdhi"; + reg = <0 0xc0880000 0 0x2000>; + clock-names = "core"; + max-frequency = <200000000>; + status = "disabled"; + }; + + ufs0: ufs@c0a80000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; + + ufs1: ufs@c0a90000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; + + scp: sram@c1000000 { + compatible = "arm,rcar-sram-ns", "mmio-sram"; + reg = <0x0 0xc1000000 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1000000 0x80000>; + + cpu_scp_lpri0: scp-shmem@60000 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61200 0x0100>; + }; + + cpu_scp_hpri0: scp-shmem@60300 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61300 0x100>; + }; + }; + + cpg: clock-controller@c64f0000 { + compatible = "renesas,r8a78000-cpg-mssr"; + reg = <0 0xc64f0000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + hscif0: serial@c0710000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0710000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif1: serial@c0714000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0714000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif2: serial@c0718000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0718000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif3: serial@c071c000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc071c000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + i2c0: i2c@c11d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc11d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@c06c0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@c06c8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@c06d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@c06d8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06d8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@c06e0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06e0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@c06e8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06e8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@c06f0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06f0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@c06f8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06f8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gpio0: gpio@c1080110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 28>; + }; + + gpio1: gpio@c1080910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 22>; + }; + + gpio2: gpio@c1081110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1081110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 29>; + }; + + gpio3: gpio@c0800110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + }; + + gpio4: gpio@c0800910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 16>; + }; + + gpio5: gpio@c0400110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 23>; + }; + + gpio6: gpio@c0400910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 31>; + }; + + gpio7: gpio@c0401110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 31>; + }; + + gpio8: gpio@c0401910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 32>; + gpio-reserved-ranges = <16 10>; + }; + + gpio9: gpio@c9b00110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + }; + + gpio10: gpio@c9b00910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 14>; + }; + + mp_phy: mp_phy@c9a00000 { + compatible = "renesas,r8a78000-multi-protocol-phy"; + reg = <0 0xc9a00000 0 0x100000>; + #phy-cells = <2>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; + clock-names = "mpphy01", "mpphy11", "mpphy21", + "mpphy31", "mpphy02"; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; + status = "disabled"; + }; + + rswitch3: ethernet@c9bc0000 { + compatible = "renesas,r8a78000-ether-switch3", + "renesas,etherswitch"; + reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; + reg-names = "base", "secure_base"; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; + clock-names = "rsw3", "rsw3tsn", "rsw3aes", + "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", + "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", + "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; + status = "disabled"; + }; + + eth_pcs: phy@c9c50000 { + compatible = "renesas,r8a78000-ether-pcs"; + reg = <0 0xc9c50000 0 0x4000>; + #phy-cells = <1>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; + clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; + reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/include/dt-bindings/clock/r8a78000-clock-scmi.h b/include/dt-bindings/clock/r8a78000-clock-scmi.h new file mode 100644 index 00000000000..455402ee8cc --- /dev/null +++ b/include/dt-bindings/clock/r8a78000-clock-scmi.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ +#define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ + +/* + * These definition indices match the Clock ID defined by SCP FW 4.27. + */ + +#define SCP_CLOCK_ID_MDLC_UFS0 202 +#define SCP_CLOCK_ID_MDLC_UFS1 203 +#define SCP_CLOCK_ID_MDLC_SDHI0 204 + +#define SCP_CLOCK_ID_MDLC_XPCS0 316 +#define SCP_CLOCK_ID_MDLC_XPCS1 317 +#define SCP_CLOCK_ID_MDLC_XPCS2 318 +#define SCP_CLOCK_ID_MDLC_XPCS3 319 +#define SCP_CLOCK_ID_MDLC_XPCS4 320 +#define SCP_CLOCK_ID_MDLC_XPCS5 321 +#define SCP_CLOCK_ID_MDLC_XPCS6 322 +#define SCP_CLOCK_ID_MDLC_XPCS7 323 +#define SCP_CLOCK_ID_MDLC_RSW3 324 +#define SCP_CLOCK_ID_MDLC_RSW3TSN 325 +#define SCP_CLOCK_ID_MDLC_RSW3AES 326 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES0 327 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES1 328 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES2 329 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES3 330 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES4 331 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES5 332 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES6 333 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES7 334 +#define SCP_CLOCK_ID_MDLC_RSW3MFWD 335 + +#define SCP_CLOCK_ID_MDLC_MPPHY01 344 +#define SCP_CLOCK_ID_MDLC_MPPHY11 345 +#define SCP_CLOCK_ID_MDLC_MPPHY21 346 +#define SCP_CLOCK_ID_MDLC_MPPHY31 347 +#define SCP_CLOCK_ID_MDLC_MPPHY02 348 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */ diff --git a/include/dt-bindings/power/r8a78000-power-scmi.h b/include/dt-bindings/power/r8a78000-power-scmi.h new file mode 100644 index 00000000000..2f1cb8e909c --- /dev/null +++ b/include/dt-bindings/power/r8a78000-power-scmi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_POWER_H__ +#define __DT_BINDINGS_R8A78000_SCMI_POWER_H__ + +/* + * These power domain indices match the Power Domain ID defined by SCP FW 4.27. + */ + +#define X5H_POWER_DOMAIN_ID_UFS0 12 +#define X5H_POWER_DOMAIN_ID_UFS1 13 + +#define X5H_POWER_DOMAIN_ID_RSW 15 + +#define X5H_POWER_DOMAIN_ID_MPP0 17 +#define X5H_POWER_DOMAIN_ID_MPP1 18 +#define X5H_POWER_DOMAIN_ID_MPP2 19 +#define X5H_POWER_DOMAIN_ID_MPP3 20 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_POWER_H__ */ diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h new file mode 100644 index 00000000000..e0d10caa589 --- /dev/null +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__ +#define __DT_BINDINGS_R8A78000_SCMI_RESET_H__ + +/* + * These definition indices match the Reset ID defined by SCP FW 4.27. + */ + +#define SCP_RESET_DOMAIN_ID_UFS0 202 +#define SCP_RESET_DOMAIN_ID_UFS1 203 + +#define SCP_RESET_DOMAIN_ID_XPCS0 316 +#define SCP_RESET_DOMAIN_ID_XPCS1 317 +#define SCP_RESET_DOMAIN_ID_XPCS2 318 +#define SCP_RESET_DOMAIN_ID_XPCS3 319 +#define SCP_RESET_DOMAIN_ID_XPCS4 320 +#define SCP_RESET_DOMAIN_ID_XPCS5 321 +#define SCP_RESET_DOMAIN_ID_XPCS6 322 +#define SCP_RESET_DOMAIN_ID_XPCS7 323 + +#define SCP_RESET_DOMAIN_ID_MPPHY01 344 +#define SCP_RESET_DOMAIN_ID_MPPHY11 345 +#define SCP_RESET_DOMAIN_ID_MPPHY21 346 +#define SCP_RESET_DOMAIN_ID_MPPHY31 347 +#define SCP_RESET_DOMAIN_ID_MPPHY02 348 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ From cf71963778ee1c1ac4b86c78acae138591b4169c Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 2 Dec 2025 19:34:16 +0100 Subject: [PATCH 6/7] arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 Ironhide board code Add initial support for Renesas R-Car X5H R8A78000 Ironhide board. This consists mainly of DTs, Makefile and Kconfig entries and board specific configuration files. The DTs will be gradually switched over to Linux DTs via OF_UPSTREAM once Linux DTs become available upstream, as upstreaming progresses. Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 7 + arch/arm/dts/r8a78000-ironhide-u-boot.dtsi | 8 + arch/arm/dts/r8a78000-ironhide.dts | 257 +++++++++++++++++++++ arch/arm/mach-renesas/Kconfig.rcar5 | 14 ++ board/renesas/common/Makefile | 4 + board/renesas/common/gen5-common.c | 75 ++++++ board/renesas/ironhide/Kconfig | 15 ++ configs/r8a78000_ironhide_defconfig | 43 ++++ configs/renesas_rcar5.config | 23 ++ include/configs/ironhide.h | 11 + include/configs/rcar-gen5-common.h | 24 ++ 11 files changed, 481 insertions(+) create mode 100644 arch/arm/dts/r8a78000-ironhide-u-boot.dtsi create mode 100644 arch/arm/dts/r8a78000-ironhide.dts create mode 100644 board/renesas/common/gen5-common.c create mode 100644 board/renesas/ironhide/Kconfig create mode 100644 configs/r8a78000_ironhide_defconfig create mode 100644 configs/renesas_rcar5.config create mode 100644 include/configs/ironhide.h create mode 100644 include/configs/rcar-gen5-common.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 865ceb65f9a..fcad6fb2fc7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -918,6 +918,13 @@ dtb-$(CONFIG_RZA1) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb +dtb-$(CONFIG_RCAR_GEN5) += \ + r8a78000-ironhide.dtb + +ifdef CONFIG_RCAR_GEN5 +DTC_FLAGS += -R 4 -p 0x1000 +endif + dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi new file mode 100644 index 00000000000..9c72f3e55f4 --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Ironhide board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include "r8a78000-u-boot.dtsi" diff --git a/arch/arm/dts/r8a78000-ironhide.dts b/arch/arm/dts/r8a78000-ironhide.dts new file mode 100644 index 00000000000..601f2740b54 --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide.dts @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a78000.dtsi" +#include + +/ { + model = "Renesas Ironhide board based on r8a78000"; + compatible = "renesas,ironhide", "renesas,r8a78000"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + mmc0 = &mmc0; + serial0 = &hscif0; + }; + + chosen { + stdout-path = "serial0:1843200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x80000000>; + }; + + memory@1080000000 { + device_type = "memory"; + reg = <0x10 0x80000000 0x0 0x80000000>; + }; + + memory@1200000000 { + device_type = "memory"; + reg = <0x12 0x00000000 0x1 0x00000000>; + }; + + memory@1400000000 { + device_type = "memory"; + reg = <0x14 0x00000000 0x1 0x00000000>; + }; + + memory@1600000000 { + device_type = "memory"; + reg = <0x16 0x00000000 0x1 0x00000000>; + }; + + memory@1800000000 { + device_type = "memory"; + reg = <0x18 0x00000000 0x1 0x00000000>; + }; + + memory@1a00000000 { + device_type = "memory"; + reg = <0x1a 0x00000000 0x1 0x00000000>; + }; + + memory@1c00000000 { + device_type = "memory"; + reg = <0x1c 0x00000000 0x1 0x00000000>; + }; + + memory@1e00000000 { + device_type = "memory"; + reg = <0x1e 0x00000000 0x1 0x00000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&extal_clk { + clock-frequency = <16666600>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +ð_pcs { + phys = <&mp_phy 2 1>; + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-1 = <&mmc0_pins>; + pinctrl-names = "default", "state_uhs"; + + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + + status = "okay"; +}; + +&ufs0 { + status = "okay"; +}; + +&ufs1 { + status = "okay"; +}; + +&mp_phy { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + eth25g2_pins: eth25g2 { + groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; + function = "eth25g2"; + drive-strength = <24>; + }; + + ethes0_pins: ethes0 { + groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; + function = "ethes0"; + drive-strength = <24>; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; + function = "mmc0"; + drive-strength = <24>; + }; + + rsw3_pins: rsw3 { + groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; + function = "rsw3"; + drive-strength = <24>; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rswitch3 { + pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * NOTE: Only port@4 is configured for R-Car X5H board. + * Other ports (0-3, 5-12) are currently unused or not + * connected. + */ + port@4 { + reg = <4>; + renesas,connect_to_xpcs; + phy-handle = <&dp83869_phy>; + phy-mode = "sgmii"; + phys = <ð_pcs 5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83869_phy: ethernet-phy@2 { + reg = <2>; + ti,sgmii-interface; + ti,max-output-impedance; + ti,refclk-output-enable; + ti,clk-output-sel = ; + }; + }; + }; + }; +}; + +&scif_clk { + clock-frequency = <26000000>; +}; diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index 34c0ae8772b..528fc5aecc9 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -9,4 +9,18 @@ config R8A78000 endmenu +choice + prompt "Renesas ARM64 SoCs board select" + optional + +config TARGET_IRONHIDE + bool "Ironhide board" + imply R8A78000 + help + Support for Renesas R-Car Gen5 Ironhide platform + +endchoice + +source "board/renesas/ironhide/Kconfig" + endif diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 1849c995aee..889de8ea9ac 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -43,6 +43,10 @@ else obj-y += gen4-common.o endif endif + +ifdef CONFIG_RCAR_GEN5 +obj-y += gen5-common.o +endif endif endif diff --git a/board/renesas/common/gen5-common.c b/board/renesas/common/gen5-common.c new file mode 100644 index 00000000000..a05a3e8abef --- /dev/null +++ b/board/renesas/common/gen5-common.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void init_generic_timer(void) +{ + const u32 freq = CONFIG_SYS_CLK_FREQ; + + /* Update memory mapped and register based freqency */ + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +static void init_gic_v3(void) +{ + /* GIC v3 power on */ + writel(BIT(1), GICR_LPI_PWRR); + + /* Wait till the WAKER_CA_BIT changes to 0 */ + clrbits_le32(GICR_LPI_WAKER, BIT(1)); + while (readl(GICR_LPI_WAKER) & BIT(2)) + ; + + writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); +} + +void s_init(void) +{ + if (current_el() == 3) + init_generic_timer(); +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* Allow WDT reset */ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK); + + if (current_el() != 3) + return 0; + init_gic_v3(); + + return 0; +} + +void __weak reset_cpu(void) +{ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + writel(0x1, RST_SWSRES1A); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} diff --git a/board/renesas/ironhide/Kconfig b/board/renesas/ironhide/Kconfig new file mode 100644 index 00000000000..34b596714f3 --- /dev/null +++ b/board/renesas/ironhide/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IRONHIDE + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "ironhide" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "ironhide" + +endif diff --git a/configs/r8a78000_ironhide_defconfig b/configs/r8a78000_ironhide_defconfig new file mode 100644 index 00000000000..180704e75af --- /dev/null +++ b/configs/r8a78000_ironhide_defconfig @@ -0,0 +1,43 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_RCAR_GEN5=y +CONFIG_TARGET_IRONHIDE=y + +# CONFIG_OF_UPSTREAM is not set +CONFIG_ARMV8_PSCI=y +CONFIG_ARM_SMCCC=y +CONFIG_BAUDRATE=1843200 +CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}" +CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide" +CONFIG_CLK_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SCMI=y +CONFIG_CMD_UFS=y +CONFIG_DM_MAILBOX=y +CONFIG_DM_RESET=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_MMC_DEVICE_INDEX=0 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 +CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_FIRMWARE=y +CONFIG_NR_DRAM_BANKS=16 +CONFIG_POWER_DOMAIN=y +CONFIG_RCAR_MFIS_MBOX=y +CONFIG_RESET_SCMI=y +CONFIG_SCMI_AGENT_MAILBOX=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_SCSI=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_CLK_FREQ=1066666667 +CONFIG_UFS=y +CONFIG_UFS_RENESAS_GEN5=y diff --git a/configs/renesas_rcar5.config b/configs/renesas_rcar5.config new file mode 100644 index 00000000000..fbf158dfdb3 --- /dev/null +++ b/configs/renesas_rcar5.config @@ -0,0 +1,23 @@ +#include + +CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_LOAD_ADDR=0x9E600000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y + +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_CMD_MMC=y +CONFIG_DM_ETH_PHY=y +# CONFIG_MMC_HS200_SUPPORT is not set +# CONFIG_MMC_IO_VOLTAGE is not set +# CONFIG_MMC_UHS_SUPPORT is not set +CONFIG_PHY_R8A78000_ETHERNET_PCS=y +CONFIG_PHY_R8A78000_MP_PHY=y +CONFIG_PHY_TI_DP83869=y +# CONFIG_PSCI_RESET is not set +CONFIG_RENESAS_ETHER_SWITCH=y +CONFIG_RENESAS_SDHI=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SYS_I2C_RCAR_I2C=y diff --git a/include/configs/ironhide.h b/include/configs/ironhide.h new file mode 100644 index 00000000000..703c1714052 --- /dev/null +++ b/include/configs/ironhide.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __IRONHIDE_H +#define __IRONHIDE_H + +#include "rcar-gen5-common.h" + +#endif /* __IRONHIDE_H */ diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h new file mode 100644 index 00000000000..dc28d07c7f9 --- /dev/null +++ b/include/configs/rcar-gen5-common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corporation + */ + +#ifndef __RCAR_GEN5_COMMON_H +#define __RCAR_GEN5_COMMON_H + +#include + +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } + +/* Memory */ +#define DRAM_RSV_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) + +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +#endif /* __RCAR_GEN5_COMMON_H */ From 186de8a8fa860b44c528711d295fe3f32952074b Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Mon, 27 Oct 2025 18:22:55 +0100 Subject: [PATCH 7/7] arm64: renesas: Extend stub PSCI implementation to R-Car Gen5 Extend the stub PSCI implementation with support for R-Car Gen5. R-Car Gen5 uses different register to perform reset, therefore add a compile-time conditional. This is __secure code, therefore the runtime SoC detection parts are not available to it, hence the compile time conditional. Signed-off-by: Hai Pham Signed-off-by: Marek Vasut # Tweak commit message --- arch/arm/mach-renesas/psci-rcar64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-renesas/psci-rcar64.c b/arch/arm/mach-renesas/psci-rcar64.c index 459dd55ff45..22c2ee045cc 100644 --- a/arch/arm/mach-renesas/psci-rcar64.c +++ b/arch/arm/mach-renesas/psci-rcar64.c @@ -32,7 +32,12 @@ u32 __secure psci_version(void) void __secure __noreturn psci_system_reset(void) { +#if defined(CONFIG_RCAR_GEN5) + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + writel(0x1, RST_SWSRES1A); +#else writel(RST_SPRES, RST_SRESCR0); +#endif while (1) ;