mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
i2c: Rename CONFIG_SYS_I2C to CONFIG_SYS_I2C_LEGACY
It is quite confusing that CONFIG_SYS_I2C selects the legacy I2C and CONFIG_DM_I2C selects the current I2C. The deadline to migrate I2C is less than a year away. Also we want to have a CONFIG_I2C for U-Boot proper just like we have CONFIG_SPL_I2C for SPL, so we can simplify the Makefile rules. Rename this symbol so it is clear it is going away. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
@@ -277,7 +277,7 @@ struct global_data {
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*/
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void *trace_buff;
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#endif
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#if defined(CONFIG_SYS_I2C)
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#if defined(CONFIG_SYS_I2C_LEGACY)
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/**
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* @cur_i2c_bus: currently used I2C bus
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*/
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@@ -47,8 +47,8 @@
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#endif
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#if CONFIG_IS_ENABLED(DM_I2C)
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# ifdef CONFIG_SYS_I2C
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# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
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# ifdef CONFIG_SYS_I2C_LEGACY
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# error "Cannot define CONFIG_SYS_I2C_LEGACY when CONFIG_DM_I2C is used"
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# endif
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#endif
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@@ -40,7 +40,7 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -49,7 +49,7 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_i2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -70,7 +70,7 @@
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#define CONFIG_HOSTNAME "M5253DEMO"
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -59,7 +59,7 @@
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -55,7 +55,7 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -49,7 +49,7 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -51,7 +51,7 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -165,7 +165,7 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -220,7 +220,7 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -203,7 +203,7 @@
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#define CONFIG_FSL_SERDES2 0xe3100
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -206,7 +206,7 @@
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -295,7 +295,7 @@ extern unsigned long get_clock_freq(void);
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* I2C
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*/
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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@@ -203,7 +203,7 @@
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -526,7 +526,7 @@ extern unsigned long get_sdram_size(void);
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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@@ -260,7 +260,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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@@ -423,7 +423,7 @@ unsigned long get_board_ddr_clk(void);
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
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@@ -453,7 +453,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C3_SPEED 400000
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@@ -371,7 +371,7 @@ unsigned long get_board_ddr_clk(void);
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* I2C
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*/
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
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@@ -323,7 +323,7 @@ unsigned long get_board_ddr_clk(void);
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* I2C
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*/
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
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@@ -155,7 +155,7 @@
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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@@ -310,7 +310,7 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -58,7 +58,7 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -20,7 +20,7 @@
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#define CONFIG_SYS_NS16550_COM1 0x44e09000
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#define CONFIG_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#endif /* CONFIG_DM */
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@@ -31,7 +31,7 @@
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#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
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/* I2C configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */
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#define CONFIG_SYS_I2C_SPEED 100000
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@@ -166,7 +166,7 @@
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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@@ -41,7 +41,7 @@
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*/
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/* I2C support */
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#ifdef CONFIG_SYS_I2C
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#ifdef CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_PXA
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#define CONFIG_PXA_STD_I2C
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#define CONFIG_PXA_PWR_I2C
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@@ -270,7 +270,7 @@
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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@@ -18,7 +18,7 @@
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#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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@@ -13,7 +13,7 @@
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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@@ -19,7 +19,7 @@
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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@@ -40,7 +40,7 @@
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_SPEED 100000
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/*
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@@ -21,7 +21,7 @@
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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@@ -194,7 +194,7 @@
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
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@@ -153,7 +153,7 @@
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* I2C related stuff
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*/
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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@@ -26,7 +26,7 @@
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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/* I2C config */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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@@ -21,7 +21,7 @@
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#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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@@ -97,7 +97,7 @@
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/* I2C */
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#define CONFIG_SYS_MAX_I2C_BUS 1
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SOFT_SPEED 100000
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0
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@@ -36,7 +36,7 @@
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/*
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* Hardware drivers
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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@@ -42,7 +42,7 @@
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#define CONFIG_SYS_BOOTM_LEN (64 << 20)
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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@@ -163,7 +163,7 @@
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/*
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* I2C setup
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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@@ -37,7 +37,7 @@
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PCA9450
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
#undef CONFIG_DM_PMIC
|
||||
#undef CONFIG_DM_PMIC_PFUZE100
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
@@ -41,7 +41,7 @@
|
||||
#undef CONFIG_DM_PMIC
|
||||
#undef CONFIG_DM_PMIC_PFUZE100
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
@@ -62,7 +62,7 @@
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_NUM_I2C_BUSES 4
|
||||
#define CONFIG_SYS_I2C_MAX_HOPS 1
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
|
||||
@@ -90,7 +90,7 @@
|
||||
* I2C related stuff
|
||||
*/
|
||||
#undef CONFIG_I2C_MVTWSI
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
|
||||
|
||||
@@ -191,7 +191,7 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
|
||||
@@ -83,7 +83,7 @@
|
||||
#define CONFIG_NFS_TIMEOUT 10000UL
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_SH
|
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
|
||||
#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
|
||||
|
||||
@@ -47,7 +47,7 @@
|
||||
/*
|
||||
* I2C Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
|
||||
|
||||
|
||||
@@ -56,7 +56,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#else
|
||||
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
|
||||
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
|
||||
|
||||
@@ -99,7 +99,7 @@
|
||||
*/
|
||||
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#else
|
||||
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
|
||||
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
|
||||
|
||||
@@ -331,7 +331,7 @@ unsigned long get_board_ddr_clk(void);
|
||||
* I2C
|
||||
*/
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#else
|
||||
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
|
||||
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
|
||||
|
||||
@@ -105,7 +105,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#else
|
||||
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
|
||||
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
|
||||
|
||||
@@ -209,7 +209,7 @@
|
||||
* I2C
|
||||
*/
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#else
|
||||
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
|
||||
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
|
||||
|
||||
@@ -45,7 +45,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#endif
|
||||
|
||||
/* Serial Port */
|
||||
|
||||
@@ -150,7 +150,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
@@ -134,7 +134,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
@@ -62,7 +62,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@@ -75,7 +75,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#endif
|
||||
|
||||
/* Serial Port */
|
||||
|
||||
@@ -88,7 +88,7 @@
|
||||
* I2C
|
||||
*/
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MVTWSI
|
||||
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
|
||||
@@ -36,7 +36,7 @@
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -51,7 +51,7 @@
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -38,7 +38,7 @@
|
||||
#endif
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -52,7 +52,7 @@
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -464,7 +464,7 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
|
||||
@@ -33,7 +33,7 @@
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PCA9450
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -126,7 +126,7 @@
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
#undef CONFIG_DM_MMC
|
||||
#undef CONFIG_DM_PMIC
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
@@ -74,7 +74,7 @@
|
||||
|
||||
/* I2C Configuration */
|
||||
#define CONFIG_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
|
||||
|
||||
@@ -73,7 +73,7 @@
|
||||
#endif
|
||||
|
||||
/* I2C - Bit-bashed */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
* I2C
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/*
|
||||
|
||||
@@ -199,7 +199,7 @@
|
||||
defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
|
||||
#define CONFIG_SYS_I2C_MVTWSI
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7f
|
||||
#endif
|
||||
|
||||
@@ -116,7 +116,7 @@
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
|
||||
@@ -56,7 +56,7 @@
|
||||
/* EHCI */
|
||||
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
*/
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MVTWSI
|
||||
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
||||
#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
|
||||
|
||||
@@ -89,7 +89,7 @@
|
||||
/* If DM_I2C, enable non-DM I2C support */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
||||
@@ -118,7 +118,7 @@
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
|
||||
#undef CONFIG_SYS_I2C
|
||||
#undef CONFIG_SYS_I2C_LEGACY
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_TI_OMAP4_COMMON_H */
|
||||
|
||||
@@ -30,6 +30,6 @@
|
||||
#define CONFIG_SYS_BOOTCOUNT_BE
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
|
||||
#endif /* __CONFIG_TQMA6_WRU4_H */
|
||||
|
||||
@@ -71,7 +71,7 @@
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
@@ -32,7 +32,7 @@
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -43,7 +43,7 @@
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
#define DFU_DEFAULT_POLL_TIMEOUT 300
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -47,7 +47,7 @@
|
||||
* I2C driver
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_SPEED 350000
|
||||
|
||||
/*
|
||||
|
||||
@@ -22,7 +22,7 @@
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_LEGACY
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
|
||||
/*
|
||||
* For now there are essentially two parts to this file - driver model
|
||||
* here at the top, and the older code below (with CONFIG_SYS_I2C being
|
||||
* here at the top, and the older code below (with CONFIG_SYS_I2C_LEGACY being
|
||||
* most recent). The plan is to migrate everything to driver model.
|
||||
* The driver model structures and API are separate as they are different
|
||||
* enough as to be incompatible for compilation purposes.
|
||||
@@ -748,7 +748,7 @@ void i2c_early_init_f(void);
|
||||
void i2c_init(int speed, int slaveaddr);
|
||||
void i2c_init_board(void);
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
#ifdef CONFIG_SYS_I2C_LEGACY
|
||||
/*
|
||||
* i2c_get_bus_num:
|
||||
*
|
||||
@@ -922,13 +922,13 @@ int i2c_set_bus_speed(unsigned int);
|
||||
*/
|
||||
|
||||
unsigned int i2c_get_bus_speed(void);
|
||||
#endif /* CONFIG_SYS_I2C */
|
||||
#endif /* CONFIG_SYS_I2C_LEGACY */
|
||||
|
||||
/*
|
||||
* only for backwardcompatibility, should go away if we switched
|
||||
* completely to new multibus support.
|
||||
*/
|
||||
#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
|
||||
#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS)
|
||||
# if !defined(CONFIG_SYS_MAX_I2C_BUS)
|
||||
# define CONFIG_SYS_MAX_I2C_BUS 2
|
||||
# endif
|
||||
|
||||
Reference in New Issue
Block a user