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Move MPC512x_FEC driver to drivers/net
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Ben Warren
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).a
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START = start.o
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COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o
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COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@@ -1,794 +0,0 @@
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/*
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* (C) Copyright 2003-2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Derived from the MPC8xx FEC driver.
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* Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
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*/
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#include <common.h>
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#include <mpc512x.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include "fec.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DEBUG 0
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
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defined(CONFIG_MPC512x_FEC)
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#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
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#error "CONFIG_MII has to be defined!"
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#endif
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#if (DEBUG & 0x40)
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static uint32 local_crc32(char *string, unsigned int crc_value, int len);
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#endif
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int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
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int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
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int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
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static uchar rx_buff[FEC_BUFFER_SIZE];
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static int rx_buff_idx = 0;
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/********************************************************************/
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#if (DEBUG & 0x2)
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static void mpc512x_fec_phydump (char *devname)
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{
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uint16 phyStatus, i;
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uint8 phyAddr = CONFIG_PHY_ADDR;
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uint8 reg_mask[] = {
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/* regs to print: 0...8, 21,27,31 */
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1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
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};
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for (i = 0; i < 32; i++) {
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if (reg_mask[i]) {
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miiphy_read (devname, phyAddr, i, &phyStatus);
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printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
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}
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}
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}
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#endif
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/********************************************************************/
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static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
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{
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int ix;
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/*
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* Receive BDs init
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*/
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for (ix = 0; ix < FEC_RBD_NUM; ix++) {
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fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix];
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fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
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fec->bdBase->rbd[ix].dataLength = 0;
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}
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/*
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* have the last RBD to close the ring
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*/
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fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
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fec->rbdIndex = 0;
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/*
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* Trasmit BDs init
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*/
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for (ix = 0; ix < FEC_TBD_NUM; ix++) {
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fec->bdBase->tbd[ix].status = 0;
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}
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/*
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* Have the last TBD to close the ring
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*/
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fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
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/*
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* Initialize some indices
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*/
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fec->tbdIndex = 0;
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fec->usedTbdIndex = 0;
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fec->cleanTbdNum = FEC_TBD_NUM;
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return 0;
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}
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/********************************************************************/
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static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
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{
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/*
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* Reset buffer descriptor as empty
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*/
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if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
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pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
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else
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pRbd->status = FEC_RBD_EMPTY;
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pRbd->dataLength = 0;
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/*
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* Increment BD count
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*/
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fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
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/*
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* Now, we have an empty RxBD, notify FEC
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*/
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fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
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}
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/********************************************************************/
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static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
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{
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volatile FEC_TBD *pUsedTbd;
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#if (DEBUG & 0x1)
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printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
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fec->cleanTbdNum, fec->usedTbdIndex);
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#endif
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/*
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* process all the consumed TBDs
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*/
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while (fec->cleanTbdNum < FEC_TBD_NUM) {
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pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
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if (pUsedTbd->status & FEC_TBD_READY) {
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#if (DEBUG & 0x20)
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printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
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#endif
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return;
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}
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/*
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* clean this buffer descriptor
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*/
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if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
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pUsedTbd->status = FEC_TBD_WRAP;
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else
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pUsedTbd->status = 0;
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/*
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* update some indeces for a correct handling of the TBD ring
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*/
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fec->cleanTbdNum++;
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fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
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}
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}
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/********************************************************************/
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static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
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{
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uint8 currByte; /* byte for which to compute the CRC */
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int byte; /* loop - counter */
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int bit; /* loop - counter */
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uint32 crc = 0xffffffff; /* initial value */
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/*
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* The algorithm used is the following:
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* we loop on each of the six bytes of the provided address,
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* and we compute the CRC by left-shifting the previous
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* value by one position, so that each bit in the current
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* byte of the address may contribute the calculation. If
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* the latter and the MSB in the CRC are different, then
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* the CRC value so computed is also ex-ored with the
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* "polynomium generator". The current byte of the address
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* is also shifted right by one bit at each iteration.
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* This is because the CRC generatore in hardware is implemented
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* as a shift-register with as many ex-ores as the radixes
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* in the polynomium. This suggests that we represent the
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* polynomiumm itself as a 32-bit constant.
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*/
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for (byte = 0; byte < 6; byte++) {
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currByte = mac[byte];
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for (bit = 0; bit < 8; bit++) {
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if ((currByte & 0x01) ^ (crc & 0x01)) {
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crc >>= 1;
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crc = crc ^ 0xedb88320;
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} else {
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crc >>= 1;
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}
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currByte >>= 1;
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}
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}
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crc = crc >> 26;
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/*
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* Set individual hash table register
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*/
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if (crc >= 32) {
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fec->eth->iaddr1 = (1 << (crc - 32));
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fec->eth->iaddr2 = 0;
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} else {
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fec->eth->iaddr1 = 0;
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fec->eth->iaddr2 = (1 << crc);
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}
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/*
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* Set physical address
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*/
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fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
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fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
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}
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/********************************************************************/
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static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
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{
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mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
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#if (DEBUG & 0x1)
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printf ("mpc512x_fec_init... Begin\n");
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#endif
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/* Set interrupt mask register */
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fec->eth->imask = 0x00000000;
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/* Clear FEC-Lite interrupt event register(IEVENT) */
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fec->eth->ievent = 0xffffffff;
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/* Set transmit fifo watermark register(X_WMRK), default = 64 */
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fec->eth->x_wmrk = 0x0;
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/* Set Opcode/Pause Duration Register */
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fec->eth->op_pause = 0x00010020;
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/* Frame length=1522; MII mode */
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fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
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/* Half-duplex, heartbeat disabled */
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fec->eth->x_cntrl = 0x00000000;
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/* Enable MIB counters */
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fec->eth->mib_control = 0x0;
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/* Setup recv fifo start and buff size */
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fec->eth->r_fstart = 0x500;
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fec->eth->r_buff_size = FEC_BUFFER_SIZE;
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/* Setup BD base addresses */
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fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
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fec->eth->x_des_start = (uint32)fec->bdBase->tbd;
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/* DMA Control */
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fec->eth->dma_control = 0xc0000000;
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/* Enable FEC */
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fec->eth->ecntrl |= 0x00000006;
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/* Initilize addresses and status words of BDs */
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mpc512x_fec_bd_init (fec);
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/* Descriptor polling active */
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fec->eth->r_des_active = 0x01000000;
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#if (DEBUG & 0x1)
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printf("mpc512x_fec_init... Done \n");
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#endif
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return 1;
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}
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/********************************************************************/
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int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
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{
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mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
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const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
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int timeout = 1;
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uint16 phyStatus;
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#if (DEBUG & 0x1)
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printf ("mpc512x_fec_init_phy... Begin\n");
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#endif
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/*
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* Clear FEC-Lite interrupt event register(IEVENT)
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*/
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fec->eth->ievent = 0xffffffff;
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/*
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* Set interrupt mask register
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*/
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fec->eth->imask = 0x00000000;
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if (fec->xcv_type != SEVENWIRE) {
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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fec->eth->mii_speed = (((gd->ips_clk / 1000000) / 5) + 1) << 1;
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/*
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* Reset PHY, then delay 300ns
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*/
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miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
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udelay (1000);
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if (fec->xcv_type == MII10) {
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/*
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* Force 10Base-T, FDX operation
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*/
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#if (DEBUG & 0x2)
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printf ("Forcing 10 Mbps ethernet link... ");
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#endif
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miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
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miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
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timeout = 20;
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do { /* wait for link status to go down */
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udelay (10000);
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if ((timeout--) == 0) {
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#if (DEBUG & 0x2)
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printf ("hmmm, should not have waited...");
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#endif
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break;
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}
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miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
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#if (DEBUG & 0x2)
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printf ("=");
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#endif
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} while ((phyStatus & 0x0004)); /* !link up */
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timeout = 1000;
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do { /* wait for link status to come back up */
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udelay (10000);
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if ((timeout--) == 0) {
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printf ("failed. Link is down.\n");
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break;
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}
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miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
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#if (DEBUG & 0x2)
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printf ("+");
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#endif
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} while (!(phyStatus & 0x0004)); /* !link up */
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#if (DEBUG & 0x2)
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printf ("done.\n");
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#endif
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} else { /* MII100 */
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
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/*
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* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
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*/
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miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
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/*
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* Wait for AN completion
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*/
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timeout = 50000;
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do {
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udelay (1000);
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if ((timeout--) == 0) {
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#if (DEBUG & 0x2)
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printf ("PHY auto neg 0 failed...\n");
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#endif
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return -1;
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}
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if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
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#if (DEBUG & 0x2)
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printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
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#endif
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return -1;
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}
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} while (!(phyStatus & 0x0004));
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#if (DEBUG & 0x2)
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printf ("PHY auto neg complete! \n");
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#endif
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}
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}
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#if (DEBUG & 0x2)
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if (fec->xcv_type != SEVENWIRE)
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mpc512x_fec_phydump (dev->name);
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#endif
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#if (DEBUG & 0x1)
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printf ("mpc512x_fec_init_phy... Done \n");
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#endif
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return 1;
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}
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/********************************************************************/
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static void mpc512x_fec_halt (struct eth_device *dev)
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{
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mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
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int counter = 0xffff;
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#if (DEBUG & 0x2)
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if (fec->xcv_type != SEVENWIRE)
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mpc512x_fec_phydump (dev->name);
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#endif
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/*
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* mask FEC chip interrupts
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*/
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fec->eth->imask = 0;
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/*
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* issue graceful stop command to the FEC transmitter if necessary
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*/
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fec->eth->x_cntrl |= 0x00000001;
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/*
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* wait for graceful stop to register
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*/
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while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
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/*
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* Disable the Ethernet Controller
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*/
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fec->eth->ecntrl &= 0xfffffffd;
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/*
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* Issue a reset command to the FEC chip
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*/
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fec->eth->ecntrl |= 0x1;
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/*
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* wait at least 16 clock cycles
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*/
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udelay (10);
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#if (DEBUG & 0x3)
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printf ("Ethernet task stopped\n");
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#endif
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}
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/********************************************************************/
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static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
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int data_length)
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{
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/*
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* This routine transmits one frame. This routine only accepts
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* 6-byte Ethernet addresses.
|
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*/
|
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mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
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volatile FEC_TBD *pTbd;
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#if (DEBUG & 0x20)
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printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
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#endif
|
||||
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/*
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* Clear Tx BD ring at first
|
||||
*/
|
||||
mpc512x_fec_tbd_scrub (fec);
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/*
|
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* Check for valid length of data.
|
||||
*/
|
||||
if ((data_length > 1500) || (data_length <= 0)) {
|
||||
return -1;
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||||
}
|
||||
|
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/*
|
||||
* Check the number of vacant TxBDs.
|
||||
*/
|
||||
if (fec->cleanTbdNum < 1) {
|
||||
#if (DEBUG & 0x20)
|
||||
printf ("No available TxBDs ...\n");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the first TxBD to send the mac header
|
||||
*/
|
||||
pTbd = &fec->bdBase->tbd[fec->tbdIndex];
|
||||
pTbd->dataLength = data_length;
|
||||
pTbd->dataPointer = (uint32)eth_data;
|
||||
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
|
||||
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
|
||||
|
||||
/* Activate transmit Buffer Descriptor polling */
|
||||
fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */
|
||||
|
||||
#if (DEBUG & 0x8)
|
||||
printf ( "+" );
|
||||
#endif
|
||||
|
||||
fec->cleanTbdNum -= 1;
|
||||
|
||||
/*
|
||||
* wait until frame is sent .
|
||||
*/
|
||||
while (pTbd->status & FEC_TBD_READY) {
|
||||
udelay (10);
|
||||
#if (DEBUG & 0x8)
|
||||
printf ("TDB status = %04x\n", pTbd->status);
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
static int mpc512x_fec_recv (struct eth_device *dev)
|
||||
{
|
||||
/*
|
||||
* This command pulls one frame from the card
|
||||
*/
|
||||
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
|
||||
volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
|
||||
unsigned long ievent;
|
||||
int frame_length = 0;
|
||||
|
||||
#if (DEBUG & 0x1)
|
||||
printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
|
||||
#endif
|
||||
#if (DEBUG & 0x8)
|
||||
printf( "-" );
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check if any critical events have happened
|
||||
*/
|
||||
ievent = fec->eth->ievent;
|
||||
fec->eth->ievent = ievent;
|
||||
if (ievent & 0x20060000) {
|
||||
/* BABT, Rx/Tx FIFO errors */
|
||||
mpc512x_fec_halt (dev);
|
||||
mpc512x_fec_init (dev, NULL);
|
||||
return 0;
|
||||
}
|
||||
if (ievent & 0x80000000) {
|
||||
/* Heartbeat error */
|
||||
fec->eth->x_cntrl |= 0x00000001;
|
||||
}
|
||||
if (ievent & 0x10000000) {
|
||||
/* Graceful stop complete */
|
||||
if (fec->eth->x_cntrl & 0x00000001) {
|
||||
mpc512x_fec_halt (dev);
|
||||
fec->eth->x_cntrl &= ~0x00000001;
|
||||
mpc512x_fec_init (dev, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
if (!(pRbd->status & FEC_RBD_EMPTY)) {
|
||||
if (!(pRbd->status & FEC_RBD_ERR) &&
|
||||
((pRbd->dataLength - 4) > 14)) {
|
||||
|
||||
/*
|
||||
* Get buffer size
|
||||
*/
|
||||
if (pRbd->status & FEC_RBD_LAST)
|
||||
frame_length = pRbd->dataLength - 4;
|
||||
else
|
||||
frame_length = pRbd->dataLength;
|
||||
#if (DEBUG & 0x20)
|
||||
{
|
||||
int i;
|
||||
printf ("recv data length 0x%08x data hdr: ",
|
||||
pRbd->dataLength);
|
||||
for (i = 0; i < 14; i++)
|
||||
printf ("%x ", *((uint8*)pRbd->dataPointer + i));
|
||||
printf("\n");
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Fill the buffer and pass it to upper layers
|
||||
*/
|
||||
memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
|
||||
frame_length - rx_buff_idx);
|
||||
rx_buff_idx = frame_length;
|
||||
|
||||
if (pRbd->status & FEC_RBD_LAST) {
|
||||
NetReceive ((uchar*)rx_buff, frame_length);
|
||||
rx_buff_idx = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset buffer descriptor as empty
|
||||
*/
|
||||
mpc512x_fec_rbd_clean (fec, pRbd);
|
||||
}
|
||||
|
||||
/* Try to fill Buffer Descriptors */
|
||||
fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
|
||||
return frame_length;
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
int mpc512x_fec_initialize (bd_t * bis)
|
||||
{
|
||||
mpc512x_fec_priv *fec;
|
||||
struct eth_device *dev;
|
||||
int i;
|
||||
char *tmp, *end, env_enetaddr[6];
|
||||
void * bd;
|
||||
|
||||
fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
|
||||
dev = (struct eth_device *) malloc (sizeof(*dev));
|
||||
memset (dev, 0, sizeof *dev);
|
||||
|
||||
fec->eth = (ethernet_regs *) MPC512X_FEC;
|
||||
|
||||
# ifndef CONFIG_FEC_10MBIT
|
||||
fec->xcv_type = MII100;
|
||||
# else
|
||||
fec->xcv_type = MII10;
|
||||
# endif
|
||||
dev->priv = (void *)fec;
|
||||
dev->iobase = MPC512X_FEC;
|
||||
dev->init = mpc512x_fec_init;
|
||||
dev->halt = mpc512x_fec_halt;
|
||||
dev->send = mpc512x_fec_send;
|
||||
dev->recv = mpc512x_fec_recv;
|
||||
|
||||
sprintf (dev->name, "FEC ETHERNET");
|
||||
eth_register (dev);
|
||||
|
||||
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
||||
miiphy_register (dev->name,
|
||||
fec512x_miiphy_read, fec512x_miiphy_write);
|
||||
#endif
|
||||
|
||||
/* Clean up space FEC's MIB and FIFO RAM ...*/
|
||||
memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
|
||||
|
||||
/*
|
||||
* Malloc space for BDs (must be quad word-aligned)
|
||||
* this pointer is lost, so cannot be freed
|
||||
*/
|
||||
bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
|
||||
fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
|
||||
memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
|
||||
|
||||
/*
|
||||
* Set interrupt mask register
|
||||
*/
|
||||
fec->eth->imask = 0x00000000;
|
||||
|
||||
/*
|
||||
* Clear FEC-Lite interrupt event register(IEVENT)
|
||||
*/
|
||||
fec->eth->ievent = 0xffffffff;
|
||||
|
||||
/*
|
||||
* Try to set the mac address now. The fec mac address is
|
||||
* a garbage after reset. When not using fec for booting
|
||||
* the Linux fec driver will try to work with this garbage.
|
||||
*/
|
||||
tmp = getenv ("ethaddr");
|
||||
if (tmp) {
|
||||
for (i=0; i<6; i++) {
|
||||
env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0;
|
||||
if (tmp)
|
||||
tmp = (*end) ? end+1 : end;
|
||||
}
|
||||
mpc512x_fec_set_hwaddr (fec, env_enetaddr);
|
||||
fec->eth->gaddr1 = 0x00000000;
|
||||
fec->eth->gaddr2 = 0x00000000;
|
||||
}
|
||||
|
||||
mpc512x_fec_init_phy (dev, bis);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* MII-interface related functions */
|
||||
/********************************************************************/
|
||||
int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
|
||||
{
|
||||
ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
|
||||
uint32 reg; /* convenient holder for the PHY register */
|
||||
uint32 phy; /* convenient holder for the PHY */
|
||||
int timeout = 0xffff;
|
||||
|
||||
/*
|
||||
* reading from any PHY's register is done by properly
|
||||
* programming the FEC's MII data register.
|
||||
*/
|
||||
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
|
||||
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
|
||||
|
||||
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
|
||||
|
||||
/*
|
||||
* wait for the related interrupt
|
||||
*/
|
||||
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
|
||||
|
||||
if (timeout == 0) {
|
||||
#if (DEBUG & 0x2)
|
||||
printf ("Read MDIO failed...\n");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* clear mii interrupt bit
|
||||
*/
|
||||
eth->ievent = 0x00800000;
|
||||
|
||||
/*
|
||||
* it's now safe to read the PHY's register
|
||||
*/
|
||||
*retVal = (uint16) eth->mii_data;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
|
||||
{
|
||||
ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
|
||||
uint32 reg; /* convenient holder for the PHY register */
|
||||
uint32 phy; /* convenient holder for the PHY */
|
||||
int timeout = 0xffff;
|
||||
|
||||
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
|
||||
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
|
||||
|
||||
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
|
||||
FEC_MII_DATA_TA | phy | reg | data);
|
||||
|
||||
/*
|
||||
* wait for the MII interrupt
|
||||
*/
|
||||
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
|
||||
|
||||
if (timeout == 0) {
|
||||
#if (DEBUG & 0x2)
|
||||
printf ("Write MDIO failed...\n");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* clear MII interrupt bit
|
||||
*/
|
||||
eth->ievent = 0x00800000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if (DEBUG & 0x40)
|
||||
static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
|
||||
{
|
||||
int i;
|
||||
char c;
|
||||
unsigned int crc, count;
|
||||
|
||||
/*
|
||||
* crc32 algorithm
|
||||
*/
|
||||
/*
|
||||
* crc = 0xffffffff; * The initialized value should be 0xffffffff
|
||||
*/
|
||||
crc = crc_value;
|
||||
|
||||
for (i = len; --i >= 0;) {
|
||||
c = *string++;
|
||||
for (count = 0; count < 8; count++) {
|
||||
if ((c & 0x01) ^ (crc & 0x01)) {
|
||||
crc >>= 1;
|
||||
crc = crc ^ 0xedb88320;
|
||||
} else {
|
||||
crc >>= 1;
|
||||
}
|
||||
c >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* In big endian system, do byte swaping for crc value
|
||||
*/
|
||||
/**/ return crc;
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
#endif /* CONFIG_MPC512x_FEC */
|
||||
@@ -1,227 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2003 - 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Derived from the MPC8xx driver's header file.
|
||||
*/
|
||||
|
||||
#ifndef __MPC512X_FEC_H
|
||||
#define __MPC512X_FEC_H
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc512x.h>
|
||||
|
||||
typedef unsigned long uint32;
|
||||
typedef unsigned short uint16;
|
||||
typedef unsigned char uint8;
|
||||
|
||||
typedef struct ethernet_register_set {
|
||||
|
||||
/* [10:2]addr = 00 */
|
||||
|
||||
/* Control and status Registers (offset 000-1FF) */
|
||||
|
||||
volatile uint32 fec_id; /* MBAR_ETH + 0x000 */
|
||||
volatile uint32 ievent; /* MBAR_ETH + 0x004 */
|
||||
volatile uint32 imask; /* MBAR_ETH + 0x008 */
|
||||
|
||||
volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
|
||||
volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
|
||||
volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
|
||||
|
||||
volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */
|
||||
volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
|
||||
|
||||
volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */
|
||||
volatile uint32 mii_data; /* MBAR_ETH + 0x040 */
|
||||
volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */
|
||||
|
||||
volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */
|
||||
volatile uint32 mib_control; /* MBAR_ETH + 0x064 */
|
||||
|
||||
volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */
|
||||
volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
|
||||
volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
|
||||
|
||||
volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
|
||||
volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
|
||||
|
||||
volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
|
||||
volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
|
||||
volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
|
||||
volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */
|
||||
|
||||
volatile uint32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */
|
||||
volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */
|
||||
volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */
|
||||
volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */
|
||||
volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */
|
||||
|
||||
volatile uint32 RES8[6]; /* MBAR_ETH + 0x128-13C */
|
||||
volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */
|
||||
volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */
|
||||
volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */
|
||||
volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
|
||||
volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
|
||||
|
||||
volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */
|
||||
volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */
|
||||
volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */
|
||||
volatile uint32 r_buff_size; /* MBAR_ETH + 0x188 */
|
||||
volatile uint32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */
|
||||
volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */
|
||||
volatile uint32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */
|
||||
|
||||
/* MIB COUNTERS (Offset 200-2FF) */
|
||||
|
||||
volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */
|
||||
volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */
|
||||
volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
|
||||
volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
|
||||
volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */
|
||||
volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */
|
||||
volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */
|
||||
volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */
|
||||
volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */
|
||||
volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */
|
||||
volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */
|
||||
volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */
|
||||
volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */
|
||||
volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */
|
||||
volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
|
||||
volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
|
||||
volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
|
||||
volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */
|
||||
volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */
|
||||
volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
|
||||
volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */
|
||||
volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */
|
||||
volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */
|
||||
volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */
|
||||
volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */
|
||||
volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */
|
||||
volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */
|
||||
volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */
|
||||
volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */
|
||||
volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
|
||||
|
||||
volatile uint32 RES13[2]; /* MBAR_ETH + 0x278-27C */
|
||||
volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */
|
||||
volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */
|
||||
volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
|
||||
volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
|
||||
volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */
|
||||
volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */
|
||||
volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */
|
||||
volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */
|
||||
volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */
|
||||
|
||||
volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
|
||||
|
||||
volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */
|
||||
volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
|
||||
volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
|
||||
volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
|
||||
volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
|
||||
volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
|
||||
volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
|
||||
volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */
|
||||
volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */
|
||||
volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
|
||||
volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */
|
||||
volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */
|
||||
volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */
|
||||
volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */
|
||||
volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
|
||||
|
||||
volatile uint32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */
|
||||
|
||||
volatile uint32 RES15[64]; /* MBAR_ETH + 0x300-3FF */
|
||||
} ethernet_regs;
|
||||
|
||||
/* Receive & Transmit Buffer Descriptor definitions */
|
||||
typedef struct BufferDescriptor {
|
||||
uint16 status;
|
||||
uint16 dataLength;
|
||||
uint32 dataPointer;
|
||||
} FEC_RBD;
|
||||
|
||||
typedef struct {
|
||||
uint16 status;
|
||||
uint16 dataLength;
|
||||
uint32 dataPointer;
|
||||
} FEC_TBD;
|
||||
|
||||
/* private structure */
|
||||
typedef enum {
|
||||
SEVENWIRE, /* 7-wire */
|
||||
MII10, /* MII 10Mbps */
|
||||
MII100 /* MII 100Mbps */
|
||||
} xceiver_type;
|
||||
|
||||
/* BD Numer definitions */
|
||||
#define FEC_TBD_NUM 48 /* The user can adjust this value */
|
||||
#define FEC_RBD_NUM 32 /* The user can adjust this value */
|
||||
|
||||
/* packet size limit */
|
||||
#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
|
||||
|
||||
/* Buffer size must be evenly divisible by 16 */
|
||||
#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
|
||||
|
||||
typedef struct {
|
||||
uint8 frame[FEC_BUFFER_SIZE];
|
||||
} mpc512x_frame;
|
||||
|
||||
typedef struct {
|
||||
FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
|
||||
FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
|
||||
mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
|
||||
} mpc512x_buff_descs;
|
||||
|
||||
typedef struct {
|
||||
ethernet_regs *eth;
|
||||
xceiver_type xcv_type; /* transceiver type */
|
||||
mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
|
||||
uint16 rbdIndex; /* next receive BD to read */
|
||||
uint16 tbdIndex; /* next transmit BD to send */
|
||||
uint16 usedTbdIndex; /* next transmit BD to clean */
|
||||
uint16 cleanTbdNum; /* the number of available transmit BDs */
|
||||
} mpc512x_fec_priv;
|
||||
|
||||
/* RBD bits definitions */
|
||||
#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
|
||||
#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
|
||||
#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
|
||||
#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
|
||||
#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
|
||||
#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
|
||||
#define FEC_RBD_LG 0x0020 /* Frame length violation */
|
||||
#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
|
||||
#define FEC_RBD_SH 0x0008 /* Short frame */
|
||||
#define FEC_RBD_CR 0x0004 /* CRC error */
|
||||
#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
|
||||
#define FEC_RBD_TR 0x0001 /* Frame is truncated */
|
||||
#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
|
||||
FEC_RBD_OV | FEC_RBD_TR)
|
||||
|
||||
/* TBD bits definitions */
|
||||
#define FEC_TBD_READY 0x8000 /* Buffer is ready */
|
||||
#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
|
||||
#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
|
||||
#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
|
||||
#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
|
||||
|
||||
/* MII-related definitios */
|
||||
#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
|
||||
#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
|
||||
#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
|
||||
#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
|
||||
#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
|
||||
#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
|
||||
#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
|
||||
|
||||
#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
|
||||
#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
|
||||
|
||||
#endif /* __MPC512X_FEC_H */
|
||||
Reference in New Issue
Block a user