diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 15520c4dafd..b3fd4ceef13 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -316,9 +316,20 @@ stages: fi export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH} export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci + python3 -m http.server 80 --directory "\${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 & + HTTP_PID=\$! + sleep 1 # Give the server a moment to start + if ps -p \${HTTP_PID} > /dev/null; then + export HTTP_PID + else + unset HTTP_PID + fi # "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_EXTRA} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml # the below corresponds to .gitlab-ci.yml "after_script" + if [[ -n "\${HTTP_PID}" ]]; then + kill \${HTTP_PID}; + fi rm -rf /tmp/uboot-test-hooks /tmp/venv EOF - task: CopyFiles@2 diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 49f3c588cfc..2dfeda9985d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -106,10 +106,21 @@ stages: # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH}; export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; + python3 -m http.server 80 --directory "${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 & + HTTP_PID=$!; + sleep 1; + if ps -p ${HTTP_PID} > /dev/null; then + export HTTP_PID; + else + unset HTTP_PID; + fi; ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_EXTRA} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir "$UBOOT_TRAVIS_BUILD_DIR" - --junitxml=/tmp/${TEST_PY_BD}/results.xml + --junitxml=/tmp/${TEST_PY_BD}/results.xml; + if [[ -n "${HTTP_PID}" ]]; then + kill ${HTTP_PID}; + fi artifacts: when: always paths: @@ -253,8 +264,8 @@ Check packing of Python tools: sandbox test.py: parallel: matrix: - - HOST: "fast arm64" - - HOST: "fast amd64" + - HOST: "arm64" + - HOST: "amd64" tags: - ${HOST} variables: @@ -265,8 +276,8 @@ sandbox test.py: sandbox with clang test.py: parallel: matrix: - - HOST: "fast arm64" - - HOST: "fast amd64" + - HOST: "arm64" + - HOST: "amd64" tags: - ${HOST} variables: @@ -277,8 +288,8 @@ sandbox with clang test.py: sandbox64 test.py: parallel: matrix: - - HOST: "fast arm64" - - HOST: "fast amd64" + - HOST: "arm64" + - HOST: "amd64" tags: - ${HOST} variables: @@ -288,8 +299,8 @@ sandbox64 test.py: sandbox64 with clang test.py: parallel: matrix: - - HOST: "fast arm64" - - HOST: "fast amd64" + - HOST: "arm64" + - HOST: "amd64" tags: - ${HOST} variables: @@ -300,8 +311,8 @@ sandbox64 with clang test.py: sandbox64_lwip test.py: parallel: matrix: - - HOST: "fast arm64" - - HOST: "fast amd64" + - HOST: "arm64" + - HOST: "amd64" tags: - ${HOST} variables: @@ -594,8 +605,10 @@ coreboot test.py: - export strategy="-s uboot -e off" - export USE_LABGRID_SJG=1 # export verbose="-v" - - ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}" - --capture=tee-sys -k "not bootstd ${TEST_PY_TEST_SPEC}" || ret=$? + - ${SRC}/test/py/test.py -ra --role ${ROLE} ${TEST_PY_EXTRA:-"--capture=tee-sys"} + --build-dir "${OUT}" + ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} + --junitxml=${OUT}/results.xml || ret=$? - U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true - if [[ $ret -ne 0 ]]; then exit $ret; @@ -605,6 +618,9 @@ coreboot test.py: paths: - "build/${BOARD}/test-log.html" - "build/${BOARD}/multiplexed_log.css" + - "build/${BOARD}/results.xml" + reports: + junit: "build/${BOARD}/results.xml" expire_in: 1 week rpi3: diff --git a/Kconfig b/Kconfig index 51358633762..05b7f410fa5 100644 --- a/Kconfig +++ b/Kconfig @@ -309,7 +309,7 @@ config SYS_MALLOC_F_LEN config SYS_MALLOC_LEN hex "Define memory for Dynamic allocation" default 0x4000000 if SANDBOX - default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON + default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON || ARCH_K3 default 0x200000 if ARCH_BMIPS || X86 default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256 default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64 diff --git a/MAINTAINERS b/MAINTAINERS index 893977ad1df..b4d5df77ff6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -468,7 +468,6 @@ F: drivers/memory/atmel-ebi.c F: drivers/misc/microchip_flexcom.c F: drivers/timer/atmel_tcb_timer.c F: include/dt-bindings/clk/at91.h -F: include/dt-bindings/clock/at91.h F: include/dt-bindings/dma/at91.h F: include/dt-bindings/mfd/at91-usart.h F: include/dt-bindings/mfd/atmel-flexcom.h @@ -718,7 +717,7 @@ F: drivers/power/regulator/stm32-vrefbuf.c F: drivers/power/regulator/stpmic1.c F: drivers/ram/stm32mp1/ F: drivers/remoteproc/stm32_copro.c -F: drivers/reset/stm32-reset.c +F: drivers/reset/stm32/ F: drivers/rng/optee_rng.c F: drivers/rng/stm32_rng.c F: drivers/rtc/stm32_rtc.c @@ -731,6 +730,7 @@ F: include/dt-bindings/clock/stm32fx-clock.h F: include/dt-bindings/clock/stm32mp* F: include/dt-bindings/pinctrl/stm32-pinfunc.h F: include/dt-bindings/reset/stm32mp* +F: include/stm32-reset-core.h F: include/stm32_rcc.h F: tools/logos/st.bmp F: tools/stm32image.c @@ -1073,6 +1073,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git F: cmd/dfu.c F: cmd/usb_*.c F: common/dfu.c +F: common/spl/spl_dfu.c F: common/update.c F: doc/api/dfu.rst F: doc/usage/dfu.rst @@ -1569,6 +1570,14 @@ F: drivers/clk/clk_k210.c F: drivers/pinctrl/pinctrl-k210.c F: include/k210/ +RISC-V T-HEAD TH1520 +M: Yao Zi +S: Maintained +F: arch/riscv/cpu/th1520/ +F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/pinctrl/pinctrl-th1520.c +F: drivers/ram/thead/th1520_ddr.c + RNG M: Sughosh Ganu R: Heinrich Schuchardt @@ -1628,6 +1637,13 @@ F: drivers/gpio/sl28cpld-gpio.c F: drivers/misc/sl28cpld.c F: drivers/watchdog/sl28cpld-wdt.c +SLRE +M: Rasmus Villemoes +S: Maintained +F: include/slre.h +F: lib/slre.c +F: test/lib/slre.c + SMCCC TRNG M: Etienne Carriere S: Maintained diff --git a/Makefile b/Makefile index 1a5c77d7caf..fa9ce756083 100644 --- a/Makefile +++ b/Makefile @@ -12,10 +12,6 @@ NAME = # Comments in this file are targeted only to the developer, do not # expect to learn how to build the kernel reading this file. -# Do not use make's built-in rules and variables -# (this increases performance and avoids hard-to-debug behaviour) -MAKEFLAGS += -rR - # Determine target architecture for the sandbox include include/host_arch.h ifeq ("", "$(CROSS_COMPILE)") @@ -39,15 +35,6 @@ else ifeq ("riscv64", $(MK_ARCH)) endif undefine MK_ARCH -# Avoid funny character set dependencies -unexport LC_ALL -LC_COLLATE=C -LC_NUMERIC=C -export LC_COLLATE LC_NUMERIC - -# Avoid interference with shell env settings -unexport GREP_OPTIONS - # We are using a recursive build, so we need to do a little thinking # to get the ordering right. # @@ -64,6 +51,21 @@ unexport GREP_OPTIONS # descending is started. They are now explicitly listed as the # prepare rule. +ifneq ($(sub_make_done),1) + +# Do not use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour) +MAKEFLAGS += -rR + +# Avoid funny character set dependencies +unexport LC_ALL +LC_COLLATE=C +LC_NUMERIC=C +export LC_COLLATE LC_NUMERIC + +# Avoid interference with shell env settings +unexport GREP_OPTIONS + # Beautify output # --------------------------------------------------------------------------- # @@ -137,7 +139,6 @@ export quiet Q KBUILD_VERBOSE # KBUILD_SRC is set on invocation of make in OBJ directory # KBUILD_SRC is not intended to be used by the regular user (for now) -ifeq ($(KBUILD_SRC),) # OK, Make called in directory where kernel src resides # Do we want to locate output files in a separate directory? @@ -168,22 +169,26 @@ $(if $(KBUILD_OUTPUT),, \ # 'sub-make' below. MAKEFLAGS += --include-dir=$(CURDIR) +else + +# Do not print "Entering directory ..." at all for in-tree build. +MAKEFLAGS += --no-print-directory + +endif # ifneq ($(KBUILD_OUTPUT),) + +export sub_make_done := 1 PHONY += $(MAKECMDGOALS) sub-make $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make @: sub-make: FORCE - $(Q)$(MAKE) -C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR) \ + $(Q)$(MAKE) \ + $(if $(KBUILD_OUTPUT),-C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR)) \ -f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS)) -# Leave processing to above invocation of make -skip-makefile := 1 -endif # ifneq ($(KBUILD_OUTPUT),) -endif # ifeq ($(KBUILD_SRC),) - +else # sub_make_done # We process the rest of the Makefile if this is the final invocation of make -ifeq ($(skip-makefile),) # Do not print "Entering directory ...", # but we want to display it when entering to the output directory @@ -225,6 +230,9 @@ ifeq ($(KBUILD_EXTMOD),) _all: all else _all: modules +PHONY += prepare +prepare: + $(cmd_crmodverdir) endif ifeq ($(KBUILD_SRC),) @@ -429,18 +437,20 @@ CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__ -KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ +KBUILD_CFLAGS := -Wall -Werror=strict-prototypes -Wno-trigraphs \ -Wno-format-security \ - -fno-builtin -ffreestanding $(CSTD_FLAG) + -fno-builtin -ffreestanding $(CSTD_FLAG) \ + -fno-PIE \ + -Werror=implicit-function-declaration -Werror=implicit-int KBUILD_CFLAGS += -fshort-wchar -fno-strict-aliasing -KBUILD_AFLAGS := -D__ASSEMBLY__ +KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE KBUILD_LDFLAGS := ifeq ($(cc-name),clang) ifneq ($(CROSS_COMPILE),) CLANG_TARGET := --target=$(notdir $(CROSS_COMPILE:%-=%)) LDPPFLAGS += $(CLANG_TARGET) -GCC_TOOLCHAIN_DIR := $(dir $(shell which $(LD))) +GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit)) CLANG_PREFIX := --prefix=$(GCC_TOOLCHAIN_DIR) GCC_TOOLCHAIN := $(realpath $(GCC_TOOLCHAIN_DIR)/..) endif @@ -453,10 +463,6 @@ KBUILD_CFLAGS += $(call cc-option, -no-integrated-as) KBUILD_AFLAGS += $(call cc-option, -no-integrated-as) endif -# Don't generate position independent code -KBUILD_CFLAGS += $(call cc-option,-fno-PIE) -KBUILD_AFLAGS += $(call cc-option,-fno-PIE) - # Read UBOOTRELEASE from include/config/uboot.release (if it exists) UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) @@ -511,10 +517,14 @@ PHONY += outputmakefile # outputmakefile generates a Makefile in the output directory, if using a # separate output directory. This allows convenient use of make in the # output directory. +# At the same time when output Makefile generated, generate .gitignore to +# ignore whole output directory outputmakefile: ifneq ($(KBUILD_SRC),) $(Q)ln -fsn $(srctree) source $(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile $(srctree) + $(Q)test -e .gitignore || \ + { echo "# this is build directory, ignore it"; echo "*"; } > .gitignore endif # To make sure we do not include .config for any of the *config targets @@ -795,7 +805,6 @@ ifdef CONFIG_CC_IS_CLANG KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,) KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier) KBUILD_CFLAGS += $(call cc-disable-warning, gnu) -KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) # Quiet clang warning: comparison of unsigned expression < 0 is always false KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare) # CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the @@ -1414,6 +1423,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ $(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \ $(foreach f,$(BINMAN_INDIRS),-I $(f)) \ + -a atf-bl1-path=${BL1} \ -a atf-bl31-path=${BL31} \ -a tee-os-path=${TEE} \ -a ti-dm-path=${TI_DM} \ @@ -1733,6 +1743,7 @@ u-boot.elf: u-boot.bin u-boot-elf.lds u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE $(call if_changed_dep,cpp_lds) +PHONY += prepare0 # MediaTek's ARM-based u-boot needs a header to contains its load address # which is parsed by the BootROM. # If the SPL build is enabled, the header will be added to the spl binary, @@ -1915,7 +1926,7 @@ $(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ; # Error messages still appears in the original language PHONY += $(u-boot-dirs) -$(u-boot-dirs): prepare scripts +$(u-boot-dirs): prepare $(Q)$(MAKE) $(build)=$@ tools: prepare @@ -1944,7 +1955,7 @@ include/config/uboot.release: include/config/auto.conf FORCE # version.h and scripts_basic is processed / created. # Listed in dependency order -PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3 +PHONY += prepare archprepare prepare1 prepare3 # prepare3 is used to check if we are building in a separate output directory, # and if so do: @@ -1959,23 +1970,20 @@ ifneq ($(KBUILD_SRC),) fi; endif -# prepare2 creates a makefile if using a separate output directory -prepare2: prepare3 outputmakefile cfg - -prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) $(env_h) \ +prepare1: prepare3 outputmakefile cfg $(version_h) $(timestamp_h) $(dt_h) $(env_h) \ include/config/auto.conf ifeq ($(wildcard $(LDSCRIPT)),) @echo >&2 " Could not find linker script." @/bin/false endif -ifeq ($(CONFIG_USE_DEFAULT_ENV_FILE),y) +ifeq ($(CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE),y) prepare1: $(defaultenv_h) envtools: $(defaultenv_h) endif -archprepare: prepare1 scripts_basic +archprepare: prepare1 scripts prepare0: archprepare FORCE $(Q)$(MAKE) $(build)=. @@ -2049,7 +2057,7 @@ $(timestamp_h): $(srctree)/Makefile FORCE $(dt_h): $(srctree)/Makefile FORCE $(call filechk,dt.h) -$(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE +$(defaultenv_h): $(CONFIG_ENV_DEFAULT_ENV_TEXT_FILE:"%"=%) FORCE $(call filechk,defaultenv.h) # --------------------------------------------------------------------------- @@ -2281,7 +2289,7 @@ mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS)) mrproper: rm-files := $(wildcard $(MRPROPER_FILES)) mrproper-dirs := $(addprefix _mrproper_,scripts) -PHONY += $(mrproper-dirs) mrproper archmrproper +PHONY += $(mrproper-dirs) mrproper $(mrproper-dirs): $(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@) @@ -2482,32 +2490,29 @@ else target-dir = $(if $(KBUILD_EXTMOD),$(dir $<),$(dir $@)) endif -%.s: %.c prepare scripts FORCE +%.s: %.c prepare FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) -%.i: %.c prepare scripts FORCE +%.i: %.c prepare FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) -%.o: %.c prepare scripts FORCE +%.o: %.c prepare FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) -%.lst: %.c prepare scripts FORCE +%.lst: %.c prepare FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) -%.s: %.S prepare scripts FORCE +%.s: %.S prepare FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) -%.o: %.S prepare scripts FORCE +%.o: %.S prepare FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) -%.symtypes: %.c prepare scripts FORCE +%.symtypes: %.c prepare FORCE $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@) # Modules -/: prepare scripts FORCE - $(cmd_crmodverdir) +/: prepare FORCE $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ $(build)=$(build-dir) -%/: prepare scripts FORCE - $(cmd_crmodverdir) +%/: prepare FORCE $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ $(build)=$(build-dir) -%.ko: prepare scripts FORCE - $(cmd_crmodverdir) +%.ko: prepare FORCE $(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \ $(build)=$(build-dir) $(@:.ko=.o) $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost @@ -2539,18 +2544,15 @@ quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs))) quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files))) cmd_rmfiles = rm -f $(rm-files) -# read all saved command lines - -cmd_files := $(wildcard .*.cmd) - -ifneq ($(cmd_files),) - $(cmd_files): ; # Do not try to update included dependency files - include $(cmd_files) -endif +# read saved command lines for existing targets +existing-targets := $(wildcard $(sort $(targets))) +cmd_files := $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd) +$(cmd_files): ; # Do not try to update included dependency files +-include $(cmd_files) endif #ifeq ($(config-targets),1) endif #ifeq ($(mixed-targets),1) -endif # skip-makefile +endif # sub_make_done PHONY += FORCE FORCE: diff --git a/README b/README index 88b6e6f2772..40326ef3547 100644 --- a/README +++ b/README @@ -950,15 +950,6 @@ The following options need to be configured: the environment like the "source" command or the boot command first. - CONFIG_DELAY_ENVIRONMENT - - Normally the environment is loaded when the board is - initialised so that it is available to U-Boot. This inhibits - that so that the environment is not available until - explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL - this is instead controlled by the value of - /config/load-environment. - - Automatic software updates via TFTP server CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP_CNT_MAX diff --git a/arch/Kconfig b/arch/Kconfig index ea33d07c086..7e05e0c2263 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -63,6 +63,13 @@ config SYS_CACHELINE_SIZE default 64 if RISCV default 32 if MIPS +config SYS_DTC_PAD_BYTES + int "Size in bytes to pad device tree blob" + default 32768 if X86 && EFI_APP + default 4096 if ARC || ARM64 || M68K || MICROBLAZE || NIOS2 \ + || RISCV || SANDBOX || X86 + default 0 + config LINKER_LIST_ALIGN int default 32 if SANDBOX @@ -213,6 +220,7 @@ config SANDBOX imply BITREVERSE select BLOBLIST imply LTO + imply CMD_BOOTEFI_SELFTEST imply CMD_DM imply CMD_EXCEPTION imply CMD_GETTIME diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index fe6ad7b849a..87c627c01c8 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -11,4 +11,4 @@ dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here -DTC_FLAGS += -R 4 -p 0x1000 +DTC_FLAGS += -R 4 diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index fd9b7fb5f8d..4c3a25996fc 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -20,6 +20,6 @@ struct arch_global_data { #include -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r25") #endif /* __ASM_ARC_GLOBAL_DATA_H */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6ff3f2750ea..1d096ad6554 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -108,6 +108,18 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE The value subtracted from CONFIG_TEXT_BASE to calculate the TEXT_OFFSET value written to the Linux kernel image header. +config KVM_VIRT_INS + bool "Emit virtualizable instructions" + help + Instructions in the ARM ISA that have multiple output registers, + can't be used if the instruction leads to an exception to the hypervisor. + These instructions cannot be emulated by KVM because they do not produce + syndrome information data that KVM can use to infer the destination + register, the faulting address, whether it was a load or store, + if it's a 32 or 64 bit general-purpose register amongst other things. + Use this to produce virtualizable instructions if you plan to run U-Boot + with KVM. + config NVIC bool @@ -820,6 +832,7 @@ config ARCH_K3 select FIT select REGEX select FIT_SIGNATURE if ARM64 + select LTO imply TI_SECURE_DEVICE config ARCH_OMAP2PLUS @@ -1067,7 +1080,7 @@ config ARCH_OWL select CLK select CLK_OWL select OF_CONTROL - select SYS_RELOC_GD_ENV_ADDR + select ENV_RELOC_GD_ENV_ADDR imply CMD_DM config ARCH_QEMU @@ -1125,6 +1138,7 @@ config ARCH_SNAPDRAGON select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK select SYSRESET select SYSRESET_PSCI + select ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR imply OF_UPSTREAM imply CMD_DM imply DM_USB_GADGET @@ -1207,7 +1221,7 @@ config ARCH_SUNXI select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST select SPL_USE_TINY_PRINTF if SPL select USE_PREBOOT - select SYS_RELOC_GD_ENV_ADDR + select ENV_RELOC_GD_ENV_ADDR imply BOARD_LATE_INIT imply CMD_DM imply CMD_GPT diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 4eb34b7b449..ab86d642eee 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -36,7 +36,8 @@ config ARMV7_SECURE_BASE hex "Base address for secure mode memory" depends on HAS_ARMV7_SECURE_BASE default 0xfff00000 if TEGRA124 - default 0x2ffc0000 if ARCH_STM32MP + default 0x2ffe0000 if STM32MP13X + default 0x2ffc0000 if STM32MP15X default 0x2f000000 if ARCH_MX7ULP default 0x10010000 if ARCH_LS1021A default 0x00900000 if ARCH_MX7 diff --git a/arch/arm/cpu/armv7m/start.S b/arch/arm/cpu/armv7m/start.S index 0c07f2140c7..a439404a248 100644 --- a/arch/arm/cpu/armv7m/start.S +++ b/arch/arm/cpu/armv7m/start.S @@ -4,13 +4,19 @@ * Kamil Lulko, */ +#include #include -.globl reset -.type reset, %function -reset: - W(b) _main +/* + * Startup code (reset vector) + */ +ENTRY(reset) + W(b) _main @ Jump to _main (C runtime crt0.S) +ENDPROC(reset) -.globl c_runtime_cpu_setup -c_runtime_cpu_setup: - mov pc, lr +/* + * Setup CPU for C runtime + */ +ENTRY(c_runtime_cpu_setup) + mov pc, lr @ Jump back to caller +ENDPROC(c_runtime_cpu_setup) diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index 044a7c16cc5..6a7ec9a7ec1 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -41,7 +41,7 @@ ENTRY(return_to_fel) str w2, [x1] ldr w0, =0xfa50392f // CPU hotplug magic -#ifdef CONFIG_MACH_SUN50I_H616 +#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) ldr w2, =(SUNXI_R_CPUCFG_BASE + 0x1c0) str w0, [x2], #0x4 #elif CONFIG_MACH_SUN50I_H6 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2d3e346a36..cfbaa475701 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -802,7 +802,7 @@ enum boot_src get_boot_src(void) int mmc_get_env_dev(void) { enum boot_src src = get_boot_src(); - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; switch (src) { case BOOT_SOURCE_SD_MMC: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index ca6be3626fb..e8d2339f1a3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/sysinfo.c b/arch/arm/cpu/armv8/sysinfo.c index 850142da37d..ff0abee4c6b 100644 --- a/arch/arm/cpu/armv8/sysinfo.c +++ b/arch/arm/cpu/armv8/sysinfo.c @@ -134,7 +134,7 @@ int sysinfo_get_cache_info(u8 level, struct cache_info *cinfo) /* Select cache level */ csselr_el1 = (level << 1); - asm volatile("msr csselr_el1, %0" : : "r" (csselr_el1)); + asm volatile("msr csselr_el1, %0" : : "r" ((u64)csselr_el1)); /* Read CCSIDR_EL1 */ asm volatile("mrs %0, ccsidr_el1" : "=r" (creg.data)); diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index eee463a1b1c..5aecb61ce90 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -53,13 +53,14 @@ SECTIONS __rel_dyn_end = .; } + . = ALIGN(8); _image_binary_end = .; _end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; *(.bss*) - . = ALIGN(4); + . = ALIGN(8); __bss_end = .; } __bss_size = __bss_end - __bss_start; diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 817e7a983ae..78aad093d3b 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -153,14 +153,14 @@ SECTIONS __efi_runtime_rel_stop = .; } - . = ALIGN(4); + . = ALIGN(8); __image_copy_end = .; /* * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start - * needs to be a multiple of 4 and we overlay .bss with .rel.dyn + * needs to be a multiple of 8 and we overlay .bss with .rel.dyn */ - .rel.dyn ALIGN(4) : { + .rel.dyn ALIGN(8) : { __rel_dyn_start = .; *(.rel*) __rel_dyn_end = .; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 976dbda48c3..10404ce076e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1111,7 +1111,9 @@ dtb-$(CONFIG_SOC_K3_AM62A7) += \ k3-am62a7-r5-sk.dtb \ k3-am62a7-r5-phycore-som-2gb.dtb -dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \ + k3-am62p5-verdin-r5.dtb \ + k3-am62p5-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ diff --git a/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi index dd4623311c9..9144387861e 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi +++ b/arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi @@ -95,3 +95,7 @@ &slow_xtal { bootph-all; }; + +&watchdog { + timeout-sec = <16>; +}; diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 1c7f0fa6a49..f165fdadb9e 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -336,3 +336,7 @@ &usb2 { status = "okay"; }; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi new file mode 100644 index 00000000000..94585ee0232 --- /dev/null +++ b/arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity-u-boot.dtsi - Device Tree file for SAM9X75 + * CURIOSITY board. + * + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + */ + +/ { + cpus { + cpu@0 { + clocks = <&pmc PMC_TYPE_CORE 25>, <&pmc PMC_TYPE_CORE 17>, <&main_xtal>; + clock-names = "cpu", "master", "xtal"; + }; + }; + + clocks { + slow_rc_osc: slow_rc_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <18500>; + }; + }; + + ahb { + bootph-all; + + apb { + bootph-all; + + pinctrl { + bootph-all; + }; + }; + }; + + chosen { + bootph-all; + }; +}; + +&clk32k { + bootph-all; + clocks = <&slow_rc_osc>, <&slow_xtal>; +}; + +&dbgu { + bootph-all; +}; + +&gmac { + compatible = "microchip,sam9x7-gem", "cdns,sama7g5-gem"; +}; + +&main_xtal { + bootph-all; +}; + +&pinctrl_dbgu_default { + bootph-all; +}; + +&pinctrl_sdmmc0_default { + bootph-all; +}; + +&pioA { + bootph-all; +}; + +&pioB { + bootph-all; +}; + +&pit64b0 { + bootph-all; +}; + +&pmc { + bootph-all; +}; + +&sdmmc0 { + bootph-all; +}; + +&slow_xtal { + bootph-all; +}; + +&slow_rc_osc { + bootph-all; +}; diff --git a/arch/arm/dts/exynos-pinctrl.h b/arch/arm/dts/exynos-pinctrl.h deleted file mode 100644 index 7dd94a9b365..00000000000 --- a/arch/arm/dts/exynos-pinctrl.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Samsung Exynos DTS pinctrl constants - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Linaro Ltd - * Author: Krzysztof Kozlowski - */ - -#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ -#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ - -#define EXYNOS_PIN_PULL_NONE 0 -#define EXYNOS_PIN_PULL_DOWN 1 -#define EXYNOS_PIN_PULL_UP 3 - -/* Pin function in power down mode */ -#define EXYNOS_PIN_PDN_OUT0 0 -#define EXYNOS_PIN_PDN_OUT1 1 -#define EXYNOS_PIN_PDN_INPUT 2 -#define EXYNOS_PIN_PDN_PREV 3 - -/* - * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850 - * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1) - */ -#define EXYNOS5420_PIN_DRV_LV1 0 -#define EXYNOS5420_PIN_DRV_LV2 1 -#define EXYNOS5420_PIN_DRV_LV3 2 -#define EXYNOS5420_PIN_DRV_LV4 3 - -/* Drive strengths for Exynos5433 */ -#define EXYNOS5433_PIN_DRV_FAST_SR1 0 -#define EXYNOS5433_PIN_DRV_FAST_SR2 1 -#define EXYNOS5433_PIN_DRV_FAST_SR3 2 -#define EXYNOS5433_PIN_DRV_FAST_SR4 3 -#define EXYNOS5433_PIN_DRV_FAST_SR5 4 -#define EXYNOS5433_PIN_DRV_FAST_SR6 5 -#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 -#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 -#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa -#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb -#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc -#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf - -/* Drive strengths for Exynos7 (except FSYS1) */ -#define EXYNOS7_PIN_DRV_LV1 0 -#define EXYNOS7_PIN_DRV_LV2 2 -#define EXYNOS7_PIN_DRV_LV3 1 -#define EXYNOS7_PIN_DRV_LV4 3 - -/* Drive strengths for Exynos7 FSYS1 block */ -#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 -#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 -#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 -#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 -#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 -#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 - -/* Drive strengths for Exynos850 GPIO_HSI block */ -#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ -#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ -#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ -#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ -#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ -#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ - -#define EXYNOS_PIN_FUNC_INPUT 0 -#define EXYNOS_PIN_FUNC_OUTPUT 1 -#define EXYNOS_PIN_FUNC_2 2 -#define EXYNOS_PIN_FUNC_3 3 -#define EXYNOS_PIN_FUNC_4 4 -#define EXYNOS_PIN_FUNC_5 5 -#define EXYNOS_PIN_FUNC_6 6 -#define EXYNOS_PIN_FUNC_EINT 0xf -#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT - -#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts index aa85caaff58..be94767fa94 100644 --- a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts +++ b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts @@ -130,29 +130,29 @@ pinctrl_lpuart0: lpuart0grp { fsl,pins = < - SC_P_UART0_RX_ADMA_UART0_RX 0X06000020 - SC_P_UART0_TX_ADMA_UART0_TX 0X06000020 + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 >; }; pinctrl_lpuart1: lpuart1grp { fsl,pins = < - SC_P_UART1_RX_ADMA_UART1_RX 0X06000020 - SC_P_UART1_TX_ADMA_UART1_TX 0X06000020 + SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 + SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 >; }; pinctrl_lpuart2: lpuart2grp { fsl,pins = < - SC_P_UART2_RX_ADMA_UART2_RX 0X06000020 - SC_P_UART2_TX_ADMA_UART2_TX 0X06000020 + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 >; }; pinctrl_lpuart3: lpuart3grp { fsl,pins = < - SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020 - SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020 + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 >; }; diff --git a/arch/arm/dts/hi3660.dtsi b/arch/arm/dts/hi3660.dtsi index 028f4db60d2..7cc1e1b6279 100644 --- a/arch/arm/dts/hi3660.dtsi +++ b/arch/arm/dts/hi3660.dtsi @@ -580,7 +580,7 @@ rtc0: rtc@fff04000 { compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0Xfff04000 0x0 0x1000>; + reg = <0x0 0xfff04000 0x0 0x1000>; interrupts = ; clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; diff --git a/arch/arm/dts/imx23-pinfunc.h b/arch/arm/dts/imx23-pinfunc.h deleted file mode 100644 index 468c079f3c2..00000000000 --- a/arch/arm/dts/imx23-pinfunc.h +++ /dev/null @@ -1,327 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Header providing constants for i.MX23 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - */ - -#ifndef __DT_BINDINGS_MX23_PINCTRL_H__ -#define __DT_BINDINGS_MX23_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -#define MX23_PAD_LCD_D00__LCD_D00 0x1000 -#define MX23_PAD_LCD_D01__LCD_D01 0x1010 -#define MX23_PAD_LCD_D02__LCD_D02 0x1020 -#define MX23_PAD_LCD_D03__LCD_D03 0x1030 -#define MX23_PAD_LCD_D04__LCD_D04 0x1040 -#define MX23_PAD_LCD_D05__LCD_D05 0x1050 -#define MX23_PAD_LCD_D06__LCD_D06 0x1060 -#define MX23_PAD_LCD_D07__LCD_D07 0x1070 -#define MX23_PAD_LCD_D08__LCD_D08 0x1080 -#define MX23_PAD_LCD_D09__LCD_D09 0x1090 -#define MX23_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX23_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX23_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX23_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX23_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX23_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX23_PAD_LCD_D16__LCD_D16 0x1100 -#define MX23_PAD_LCD_D17__LCD_D17 0x1110 -#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -#define MX23_PAD_LCD_RS__LCD_RS 0x1130 -#define MX23_PAD_LCD_WR__LCD_WR 0x1140 -#define MX23_PAD_LCD_CS__LCD_CS 0x1150 -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -#define MX23_PAD_PWM0__PWM0 0x11a0 -#define MX23_PAD_PWM1__PWM1 0x11b0 -#define MX23_PAD_PWM2__PWM2 0x11c0 -#define MX23_PAD_PWM3__PWM3 0x11d0 -#define MX23_PAD_PWM4__PWM4 0x11e0 -#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -#define MX23_PAD_ROTARYA__ROTARYA 0x2070 -#define MX23_PAD_ROTARYB__ROTARYB 0x2080 -#define MX23_PAD_EMI_A00__EMI_A00 0x2090 -#define MX23_PAD_EMI_A01__EMI_A01 0x20a0 -#define MX23_PAD_EMI_A02__EMI_A02 0x20b0 -#define MX23_PAD_EMI_A03__EMI_A03 0x20c0 -#define MX23_PAD_EMI_A04__EMI_A04 0x20d0 -#define MX23_PAD_EMI_A05__EMI_A05 0x20e0 -#define MX23_PAD_EMI_A06__EMI_A06 0x20f0 -#define MX23_PAD_EMI_A07__EMI_A07 0x2100 -#define MX23_PAD_EMI_A08__EMI_A08 0x2110 -#define MX23_PAD_EMI_A09__EMI_A09 0x2120 -#define MX23_PAD_EMI_A10__EMI_A10 0x2130 -#define MX23_PAD_EMI_A11__EMI_A11 0x2140 -#define MX23_PAD_EMI_A12__EMI_A12 0x2150 -#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -#define MX23_PAD_EMI_D00__EMI_D00 0x3000 -#define MX23_PAD_EMI_D01__EMI_D01 0x3010 -#define MX23_PAD_EMI_D02__EMI_D02 0x3020 -#define MX23_PAD_EMI_D03__EMI_D03 0x3030 -#define MX23_PAD_EMI_D04__EMI_D04 0x3040 -#define MX23_PAD_EMI_D05__EMI_D05 0x3050 -#define MX23_PAD_EMI_D06__EMI_D06 0x3060 -#define MX23_PAD_EMI_D07__EMI_D07 0x3070 -#define MX23_PAD_EMI_D08__EMI_D08 0x3080 -#define MX23_PAD_EMI_D09__EMI_D09 0x3090 -#define MX23_PAD_EMI_D10__EMI_D10 0x30a0 -#define MX23_PAD_EMI_D11__EMI_D11 0x30b0 -#define MX23_PAD_EMI_D12__EMI_D12 0x30c0 -#define MX23_PAD_EMI_D13__EMI_D13 0x30d0 -#define MX23_PAD_EMI_D14__EMI_D14 0x30e0 -#define MX23_PAD_EMI_D15__EMI_D15 0x30f0 -#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -#define MX23_PAD_GPMI_D00__LCD_D8 0x0001 -#define MX23_PAD_GPMI_D01__LCD_D9 0x0011 -#define MX23_PAD_GPMI_D02__LCD_D10 0x0021 -#define MX23_PAD_GPMI_D03__LCD_D11 0x0031 -#define MX23_PAD_GPMI_D04__LCD_D12 0x0041 -#define MX23_PAD_GPMI_D05__LCD_D13 0x0051 -#define MX23_PAD_GPMI_D06__LCD_D14 0x0061 -#define MX23_PAD_GPMI_D07__LCD_D15 0x0071 -#define MX23_PAD_GPMI_D08__LCD_D18 0x0081 -#define MX23_PAD_GPMI_D09__LCD_D19 0x0091 -#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -#define MX23_PAD_AUART1_RX__IR_RX 0x01c1 -#define MX23_PAD_AUART1_TX__IR_TX 0x01d1 -#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -#define MX23_PAD_LCD_D00__ETM_DA8 0x1001 -#define MX23_PAD_LCD_D01__ETM_DA9 0x1011 -#define MX23_PAD_LCD_D02__ETM_DA10 0x1021 -#define MX23_PAD_LCD_D03__ETM_DA11 0x1031 -#define MX23_PAD_LCD_D04__ETM_DA12 0x1041 -#define MX23_PAD_LCD_D05__ETM_DA13 0x1051 -#define MX23_PAD_LCD_D06__ETM_DA14 0x1061 -#define MX23_PAD_LCD_D07__ETM_DA15 0x1071 -#define MX23_PAD_LCD_D08__ETM_DA0 0x1081 -#define MX23_PAD_LCD_D09__ETM_DA1 0x1091 -#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -#define MX23_PAD_PWM0__ROTARYA 0x11a1 -#define MX23_PAD_PWM1__ROTARYB 0x11b1 -#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -#define MX23_PAD_PWM3__ETM_TCTL 0x11d1 -#define MX23_PAD_PWM4__ETM_TCLK 0x11e1 -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -#define MX23_PAD_PWM0__DUART_RX 0x11a2 -#define MX23_PAD_PWM1__DUART_TX 0x11b2 -#define MX23_PAD_PWM3__AUART1_CTS 0x11d2 -#define MX23_PAD_PWM4__AUART1_RTS 0x11e2 -#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -#define MX23_PAD_ROTARYA__SPDIF 0x2072 -#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -#define MX23_PAD_PWM0__GPIO_1_26 0x11a3 -#define MX23_PAD_PWM1__GPIO_1_27 0x11b3 -#define MX23_PAD_PWM2__GPIO_1_28 0x11c3 -#define MX23_PAD_PWM3__GPIO_1_29 0x11d3 -#define MX23_PAD_PWM4__GPIO_1_30 0x11e3 -#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 - -#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */ diff --git a/arch/arm/dts/imx28-btt3-0-u-boot.dtsi b/arch/arm/dts/imx28-btt3-0-u-boot.dtsi new file mode 100644 index 00000000000..b128eef9e17 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-0-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include "imx28-btt3-u-boot.dtsi" diff --git a/arch/arm/dts/imx28-btt3-1-u-boot.dtsi b/arch/arm/dts/imx28-btt3-1-u-boot.dtsi new file mode 100644 index 00000000000..b128eef9e17 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-1-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include "imx28-btt3-u-boot.dtsi" diff --git a/arch/arm/dts/imx28-btt3-2-u-boot.dtsi b/arch/arm/dts/imx28-btt3-2-u-boot.dtsi new file mode 100644 index 00000000000..b128eef9e17 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include "imx28-btt3-u-boot.dtsi" diff --git a/arch/arm/dts/imx28-btt3-u-boot.dtsi b/arch/arm/dts/imx28-btt3-u-boot.dtsi new file mode 100644 index 00000000000..3569d29a737 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-u-boot.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/* + * The minimal augmentation DTS U-Boot file to allow eMMC driver + * configuration in SPL for falcon boot. + */ +#include "imx28-u-boot.dtsi" +/ { + aliases { + /delete-property/ saif0; + /delete-property/ saif1; + /delete-property/ spi0; + /delete-property/ spi1; + /delete-property/ usbphy0; + /delete-property/ usbphy1; + }; + apb@80000000 { + bootph-pre-ram; + + apbh@80000000 { + bootph-pre-ram; + }; + + apbx@80040000 { + bootph-pre-ram; + }; + }; + + /delete-node/ keypad; + /delete-node/ panel; + /delete-node/ sdio-pwrseq; + /delete-node/ sound; +}; + +&clks { + bootph-pre-ram; + status = "disable"; +}; + +&duart { + /delete-property/ clocks; + bootph-pre-ram; + type = <1>; /* TYPE_PL011 */ +}; + +&gpio0 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&pinctrl { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + bootph-pre-ram; +}; + +&ssp0 { + bootph-pre-ram; +}; + +&ssp3 { + num-cs = <2>; + spi-max-frequency = <40000000>; + bootph-pre-ram; +}; + +/delete-node/ &hog_pins_a; +/delete-node/ &keypad_pins_bttc; +/delete-node/ &lcdif; +/delete-node/ &lcdif_sync_pins_bttc; +/delete-node/ &pwm; +/delete-node/ &saif0; +/delete-node/ &saif1; +/delete-node/ &ssp1; +/delete-node/ &ssp2; +/delete-node/ &usb0; +/delete-node/ &usb1; +/delete-node/ &usbphy0; +/delete-node/ &usbphy1; diff --git a/arch/arm/dts/imx28-pinfunc.h b/arch/arm/dts/imx28-pinfunc.h deleted file mode 100644 index d427e6c2fa7..00000000000 --- a/arch/arm/dts/imx28-pinfunc.h +++ /dev/null @@ -1,500 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - */ - -#ifndef __DT_BINDINGS_MX28_PINCTRL_H__ -#define __DT_BINDINGS_MX28_PINCTRL_H__ - -#include "mxs-pinfunc.h" - -#define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -#define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -#define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -#define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -#define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -#define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -#define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -#define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -#define MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -#define MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -#define MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -#define MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -#define MX28_PAD_LCD_D00__LCD_D0 0x1000 -#define MX28_PAD_LCD_D01__LCD_D1 0x1010 -#define MX28_PAD_LCD_D02__LCD_D2 0x1020 -#define MX28_PAD_LCD_D03__LCD_D3 0x1030 -#define MX28_PAD_LCD_D04__LCD_D4 0x1040 -#define MX28_PAD_LCD_D05__LCD_D5 0x1050 -#define MX28_PAD_LCD_D06__LCD_D6 0x1060 -#define MX28_PAD_LCD_D07__LCD_D7 0x1070 -#define MX28_PAD_LCD_D08__LCD_D8 0x1080 -#define MX28_PAD_LCD_D09__LCD_D9 0x1090 -#define MX28_PAD_LCD_D10__LCD_D10 0x10a0 -#define MX28_PAD_LCD_D11__LCD_D11 0x10b0 -#define MX28_PAD_LCD_D12__LCD_D12 0x10c0 -#define MX28_PAD_LCD_D13__LCD_D13 0x10d0 -#define MX28_PAD_LCD_D14__LCD_D14 0x10e0 -#define MX28_PAD_LCD_D15__LCD_D15 0x10f0 -#define MX28_PAD_LCD_D16__LCD_D16 0x1100 -#define MX28_PAD_LCD_D17__LCD_D17 0x1110 -#define MX28_PAD_LCD_D18__LCD_D18 0x1120 -#define MX28_PAD_LCD_D19__LCD_D19 0x1130 -#define MX28_PAD_LCD_D20__LCD_D20 0x1140 -#define MX28_PAD_LCD_D21__LCD_D21 0x1150 -#define MX28_PAD_LCD_D22__LCD_D22 0x1160 -#define MX28_PAD_LCD_D23__LCD_D23 0x1170 -#define MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -#define MX28_PAD_LCD_RS__LCD_RS 0x11a0 -#define MX28_PAD_LCD_CS__LCD_CS 0x11b0 -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -#define MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -#define MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -#define MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -#define MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -#define MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -#define MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -#define MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -#define MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -#define MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -#define MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -#define MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -#define MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -#define MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -#define MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -#define MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -#define MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -#define MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -#define MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -#define MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -#define MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -#define MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -#define MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -#define MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -#define MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -#define MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -#define MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -#define MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -#define MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -#define MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -#define MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -#define MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -#define MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -#define MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -#define MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -#define MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -#define MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -#define MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -#define MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -#define MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -#define MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -#define MX28_PAD_PWM0__PWM_0 0x3100 -#define MX28_PAD_PWM1__PWM_1 0x3110 -#define MX28_PAD_PWM2__PWM_2 0x3120 -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -#define MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -#define MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -#define MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -#define MX28_PAD_PWM3__PWM_3 0x31c0 -#define MX28_PAD_PWM4__PWM_4 0x31d0 -#define MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -#define MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -#define MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -#define MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -#define MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -#define MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -#define MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -#define MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -#define MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -#define MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -#define MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -#define MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -#define MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -#define MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -#define MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -#define MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -#define MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -#define MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -#define MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -#define MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -#define MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -#define MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -#define MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -#define MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -#define MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -#define MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -#define MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -#define MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -#define MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -#define MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -#define MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -#define MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -#define MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -#define MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -#define MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -#define MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -#define MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -#define MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -#define MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -#define MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -#define MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -#define MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -#define MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -#define MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -#define MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -#define MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -#define MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -#define MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -#define MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -#define MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -#define MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -#define MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -#define MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -#define MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -#define MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -#define MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -#define MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -#define MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -#define MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -#define MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -#define MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -#define MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -#define MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -#define MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -#define MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -#define MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -#define MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -#define MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -#define MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -#define MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -#define MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -#define MX28_PAD_LCD_D03__ETM_DA8 0x1031 -#define MX28_PAD_LCD_D04__ETM_DA9 0x1041 -#define MX28_PAD_LCD_D08__ETM_DA3 0x1081 -#define MX28_PAD_LCD_D09__ETM_DA4 0x1091 -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -#define MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -#define MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -#define MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -#define MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -#define MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -#define MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -#define MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -#define MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -#define MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -#define MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -#define MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -#define MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -#define MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -#define MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -#define MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -#define MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -#define MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -#define MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -#define MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -#define MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -#define MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -#define MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -#define MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -#define MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -#define MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -#define MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -#define MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -#define MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -#define MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -#define MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -#define MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -#define MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -#define MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -#define MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -#define MX28_PAD_PWM0__I2C1_SCL 0x3101 -#define MX28_PAD_PWM1__I2C1_SDA 0x3111 -#define MX28_PAD_PWM2__USB0_ID 0x3121 -#define MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -#define MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -#define MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -#define MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -#define MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -#define MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -#define MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -#define MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -#define MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -#define MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -#define MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -#define MX28_PAD_LCD_D00__ETM_DA0 0x1002 -#define MX28_PAD_LCD_D01__ETM_DA1 0x1012 -#define MX28_PAD_LCD_D02__ETM_DA2 0x1022 -#define MX28_PAD_LCD_D03__ETM_DA3 0x1032 -#define MX28_PAD_LCD_D04__ETM_DA4 0x1042 -#define MX28_PAD_LCD_D05__ETM_DA5 0x1052 -#define MX28_PAD_LCD_D06__ETM_DA6 0x1062 -#define MX28_PAD_LCD_D07__ETM_DA7 0x1072 -#define MX28_PAD_LCD_D08__ETM_DA8 0x1082 -#define MX28_PAD_LCD_D09__ETM_DA9 0x1092 -#define MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -#define MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -#define MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -#define MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -#define MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -#define MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -#define MX28_PAD_LCD_D16__ETM_DA7 0x1102 -#define MX28_PAD_LCD_D17__ETM_DA6 0x1112 -#define MX28_PAD_LCD_D18__ETM_DA5 0x1122 -#define MX28_PAD_LCD_D19__ETM_DA4 0x1132 -#define MX28_PAD_LCD_D20__ETM_DA3 0x1142 -#define MX28_PAD_LCD_D21__ETM_DA2 0x1152 -#define MX28_PAD_LCD_D22__ETM_DA1 0x1162 -#define MX28_PAD_LCD_D23__ETM_DA0 0x1172 -#define MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -#define MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -#define MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -#define MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -#define MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -#define MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -#define MX28_PAD_AUART1_RX__PWM_0 0x3042 -#define MX28_PAD_AUART1_TX__PWM_1 0x3052 -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -#define MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -#define MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -#define MX28_PAD_PWM0__DUART_RX 0x3102 -#define MX28_PAD_PWM1__DUART_TX 0x3112 -#define MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -#define MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -#define MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -#define MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -#define MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -#define MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -#define MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -#define MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -#define MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -#define MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -#define MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -#define MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -#define MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -#define MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -#define MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -#define MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -#define MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -#define MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -#define MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -#define MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -#define MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -#define MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -#define MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -#define MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -#define MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -#define MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -#define MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -#define MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -#define MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -#define MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -#define MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -#define MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -#define MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -#define MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -#define MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -#define MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -#define MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -#define MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -#define MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -#define MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -#define MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -#define MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -#define MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -#define MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -#define MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -#define MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -#define MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -#define MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -#define MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -#define MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -#define MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -#define MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -#define MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -#define MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -#define MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -#define MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -#define MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -#define MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -#define MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -#define MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -#define MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -#define MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -#define MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -#define MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -#define MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -#define MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -#define MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -#define MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -#define MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -#define MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -#define MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -#define MX28_PAD_PWM0__GPIO_3_16 0x3103 -#define MX28_PAD_PWM1__GPIO_3_17 0x3113 -#define MX28_PAD_PWM2__GPIO_3_18 0x3123 -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -#define MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -#define MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -#define MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -#define MX28_PAD_PWM3__GPIO_3_28 0x31c3 -#define MX28_PAD_PWM4__GPIO_3_29 0x31d3 -#define MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -#define MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -#define MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -#define MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -#define MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */ diff --git a/arch/arm/dts/imx51-pinfunc.h b/arch/arm/dts/imx51-pinfunc.h deleted file mode 100644 index 910e0ec50ef..00000000000 --- a/arch/arm/dts/imx51-pinfunc.h +++ /dev/null @@ -1,768 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX51_PINFUNC_H -#define __DTS_IMX51_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 -#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 -#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 -#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 -#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 -#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 -#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 -#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 -#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 -#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 -#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0 -#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0 -#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0 -#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0 -#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0 -#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0 -#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0 -#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1 -#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0 -#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 -#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0 -#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0 -#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0 -#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0 -#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1 -#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0 -#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 -#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0 -#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0 -#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0 -#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0 -#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 -#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0 -#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0 -#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0 -#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0 -#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 -#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0 -#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0 -#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0 -#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 -#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0 -#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 -#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0 -#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0 -#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0 -#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0 -#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0 -#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0 -#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0 -#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0 -#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0 -#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0 -#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0 -#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0 -#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3 -#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0 -#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0 -#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 -#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0 -#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0 -#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3 -#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0 -#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 -#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0 -#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0 -#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0 -#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0 -#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0 -#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0 -#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0 -#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0 -#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0 -#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0 -#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0 -#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0 -#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0 -#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0 -#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0 -#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0 -#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0 -#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0 -#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0 -#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0 -#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0 -#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0 -#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0 -#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0 -#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0 -#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0 -#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0 -#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0 -#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0 -#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0 -#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0 -#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0 -#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0 -#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0 -#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0 -#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0 -#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0 -#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0 -#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0 -#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0 -#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0 -#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0 -#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0 -#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0 -#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0 -#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0 -#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0 -#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0 -#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0 -#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0 -#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0 -#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0 -#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0 -#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0 -#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0 -#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0 -#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0 -#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0 -#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0 -#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1 -#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0 -#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1 -#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0 -#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1 -#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0 -#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0 -#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1 -#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0 -#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0 -#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0 -#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0 -#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0 -#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0 -#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0 -#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0 -#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0 -#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0 -#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0 -#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0 -#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0 -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0 -#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0 -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0 -#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0 -#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0 -#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0 -#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0 -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0 -#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0 -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0 -#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0 -#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0 -#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0 -#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0 -#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0 -#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0 -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0 -#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0 -#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0 -#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0 -#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0 -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0 -#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0 -#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0 -#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0 -#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0 -#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0 -#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0 -#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0 -#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0 -#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0 -#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0 -#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0 -#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0 -#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0 -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0 -#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0 -#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0 -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0 -#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1 -#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0 -#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0 -#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1 -#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1 -#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0 -#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1 -#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1 -#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0 -#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0 -#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0 -#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0 -#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0 -#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0 -#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0 -#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0 -#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0 -#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0 -#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0 -#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0 -#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1 -#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0 -#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0 -#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0 -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0 -#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0 -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0 -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0 -#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0 -#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0 -#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0 -#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0 -#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0 -#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0 -#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0 -#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0 -#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0 -#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0 -#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2 -#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0 -#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0 -#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0 -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1 -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1 -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1 -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1 -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0 -#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0 -#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1 -#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0 -#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0 -#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0 -#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0 -#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0 -#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0 -#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0 -#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0 -#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0 -#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0 -#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0 -#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2 -#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0 -#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0 -#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0 -#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0 -#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0 -#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4 -#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0 -#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0 -#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0 -#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0 -#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0 -#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0 -#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0 -#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0 -#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0 -#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0 -#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0 -#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1 -#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0 -#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4 -#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1 -#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0 -#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0 -#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1 -#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0 -#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2 -#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1 -#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2 -#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0 -#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0 -#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6 -#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0 -#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0 -#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0 -#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0 -#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4 -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5 -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0 -#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1 -#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0 -#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1 -#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0 -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0 -#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1 -#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1 -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0 -#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1 -#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0 -#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0 -#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1 -#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0 -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1 -#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1 -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0 -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0 -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1 -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0 -#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0 -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0 -#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0 -#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0 -#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0 -#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1 -#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1 -#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0 -#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1 -#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1 -#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0 -#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0 -#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1 -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 -#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1 -#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0 -#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1 -#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0 -#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1 -#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1 -#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8 -#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1 -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1 -#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1 -#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1 -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1 -#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1 -#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1 -#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1 -#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1 -#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1 -#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1 -#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1 -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1 -#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1 -#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1 -#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1 -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1 -#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0 -#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1 -#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1 -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1 -#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1 -#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1 -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1 -#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1 -#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1 -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1 -#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1 -#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1 -#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0 -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0 -#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0 -#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1 -#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1 -#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2 -#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0 -#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1 -#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2 -#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2 -#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1 -#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2 -#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2 -#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2 -#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1 -#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0 -#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2 -#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0 -#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0 -#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3 -#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2 -#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0 -#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3 -#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2 -#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3 -#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0 -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0 -#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1 -#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0 -#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0 -#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3 -#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1 -#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3 -#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1 -#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0 -#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1 -#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1 -#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0 -#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2 -#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0 -#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0 -#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0 -#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0 -#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0 -#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0 -#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0 - -#endif /* __DTS_IMX51_PINFUNC_H */ diff --git a/arch/arm/dts/imx53-pinfunc.h b/arch/arm/dts/imx53-pinfunc.h deleted file mode 100644 index 67bd06610fd..00000000000 --- a/arch/arm/dts/imx53-pinfunc.h +++ /dev/null @@ -1,1189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX53_PINFUNC_H -#define __DTS_IMX53_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 -#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 -#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 -#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 -#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 -#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 -#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 -#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 -#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 -#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 -#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 -#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 -#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 -#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 -#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 -#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 -#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 -#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 -#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 -#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 -#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 -#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 -#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 -#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 -#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 -#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 -#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 -#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 -#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 -#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 -#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 -#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 -#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 -#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 -#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 -#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 -#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 -#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 -#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 -#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 -#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 -#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 -#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 -#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 -#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 -#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 -#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 -#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 -#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 -#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 -#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 -#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 -#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 -#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 -#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 -#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 -#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 -#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 -#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 -#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 -#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 -#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 -#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 -#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 -#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 -#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 -#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 -#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 -#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 -#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 -#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 -#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 -#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 -#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 -#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 -#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 -#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 -#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 -#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 -#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 -#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 -#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 -#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 -#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 -#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 -#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 -#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 -#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 -#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 -#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 -#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 -#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 -#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 -#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 -#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 -#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 -#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 -#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 -#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 -#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 -#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 -#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 -#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 -#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 -#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 -#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 -#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 -#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 -#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 -#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 -#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 -#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 -#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 -#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 -#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 -#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 -#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 -#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 -#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 -#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 -#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 -#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 -#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 -#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 -#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 -#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 -#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 -#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 -#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 -#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 -#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 -#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 -#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 -#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 -#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 -#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 -#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 -#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 -#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 -#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 -#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 -#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 -#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 -#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 -#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 -#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 -#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 -#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 -#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 -#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 -#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 -#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 -#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 -#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 -#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 -#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 -#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 -#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 -#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 -#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 -#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 -#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 -#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 -#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 -#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 -#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 -#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 -#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 -#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 -#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 -#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 -#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 -#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 -#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 -#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 -#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 -#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 -#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 -#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 -#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 -#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 -#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 -#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 -#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 -#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 -#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 -#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 -#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 -#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 -#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 -#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 -#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 -#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 -#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 -#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 -#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 -#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 -#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 -#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 -#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 -#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 -#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 -#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 -#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 -#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 -#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 -#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 -#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 -#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 -#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 -#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 -#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 -#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 -#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 -#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 -#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 -#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 -#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 -#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 -#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 -#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 -#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 -#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 -#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 -#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 -#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 -#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 -#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 -#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 -#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 -#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 -#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 -#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 -#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 -#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 -#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 -#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 -#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 -#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 -#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 -#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 -#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 -#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 -#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 -#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 -#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 -#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 -#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 -#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 -#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 -#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 -#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 -#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 -#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 -#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 -#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 -#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 -#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 -#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 -#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 -#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 -#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 -#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 -#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 -#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 -#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 -#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 -#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 -#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 -#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 -#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 -#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 -#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 -#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 -#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 -#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 -#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 -#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 -#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 -#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 -#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 -#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 -#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 -#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 -#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 -#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 -#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 -#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 -#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 -#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 -#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 -#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 -#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 -#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 -#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 -#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 -#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 -#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 -#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 -#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 -#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 -#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 -#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 -#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 -#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 -#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 -#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 -#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 -#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 -#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 -#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 -#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 -#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 -#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 -#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 -#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 -#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 -#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 -#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 -#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 -#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 -#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 -#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 -#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 -#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 -#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 -#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 -#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 -#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 -#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 -#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 -#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 -#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 -#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 -#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 -#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 -#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 -#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 -#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 -#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 -#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 -#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 -#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 -#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 -#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 -#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 -#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 -#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 -#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 -#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 -#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 -#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 -#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 -#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 -#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 -#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 -#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 -#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 -#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 -#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 -#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 -#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 -#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 -#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 -#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 -#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 -#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 -#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 -#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 -#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 -#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 -#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 -#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 -#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 -#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 -#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 -#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 -#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 -#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 -#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 -#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 -#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 -#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 -#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 -#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 -#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 -#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 -#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 -#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 -#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 -#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 -#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 -#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 -#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 -#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 -#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 -#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 -#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 -#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 -#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 -#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 -#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 -#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 -#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 -#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 -#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 -#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 -#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 -#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 -#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 -#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 -#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 -#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 -#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 -#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 -#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 -#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 -#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 -#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 -#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 -#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 -#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 -#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 -#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 -#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 -#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 -#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 -#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 -#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 -#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 -#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 -#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 -#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 -#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 -#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 -#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 -#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 -#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 -#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 -#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 -#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 -#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 -#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 -#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 -#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 -#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 -#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 -#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 -#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 -#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 -#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 -#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 -#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 -#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 -#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 -#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 -#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 -#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 -#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 -#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 -#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 -#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 -#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 -#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 -#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 -#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 -#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 -#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 -#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 -#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 -#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 -#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 -#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 -#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 -#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 -#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 -#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 -#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 -#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 -#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 -#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 -#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 -#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 -#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 -#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 -#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 -#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 -#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 -#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 -#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 -#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 -#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 -#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 -#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 -#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 -#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 -#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 -#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 -#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 -#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 -#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 -#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 -#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 -#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 -#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 -#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 -#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 -#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 -#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 -#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 -#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 -#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 -#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 -#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 -#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 -#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 -#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 -#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 -#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 -#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 -#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 -#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 -#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 -#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 -#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 -#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 -#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 -#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 -#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 -#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 -#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 -#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 -#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 -#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 -#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 -#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 -#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 -#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 -#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 -#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 -#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 -#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 -#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 -#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 -#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 -#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 -#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 -#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 -#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 -#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 -#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 -#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 -#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 -#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 - -#endif /* __DTS_IMX53_PINFUNC_H */ diff --git a/arch/arm/dts/imx6dl-pinfunc.h b/arch/arm/dts/imx6dl-pinfunc.h deleted file mode 100644 index 9d88d09f9bf..00000000000 --- a/arch/arm/dts/imx6dl-pinfunc.h +++ /dev/null @@ -1,1088 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6DL_PINFUNC_H -#define __DTS_IMX6DL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 -#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 -#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 -#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 -#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1f8 0x5c8 0x000 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x2dc 0x6c4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6DL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6q-pinfunc.h b/arch/arm/dts/imx6q-pinfunc.h deleted file mode 100644 index e40409d04b9..00000000000 --- a/arch/arm/dts/imx6q-pinfunc.h +++ /dev/null @@ -1,1044 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6Q_PINFUNC_H -#define __DTS_IMX6Q_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 -#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 -#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 -#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 -#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 -#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 -#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 -#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 -#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 -#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 -#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 -#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 -#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 -#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 -#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 -#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 -#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 -#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 -#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 -#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 -#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 -#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 -#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 -#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 -#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 -#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 -#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 -#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 -#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 -#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 -#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 -#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 -#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 -#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 -#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 -#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 -#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 -#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 -#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 -#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 -#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 -#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 -#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 -#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 -#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 -#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 -#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 -#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 -#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1 -#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 -#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 -#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 -#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 -#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 -#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 -#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 -#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 -#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 -#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 -#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 -#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 -#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 -#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 -#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 -#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 -#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 -#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 -#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 -#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 -#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 -#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 -#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 -#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 -#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 -#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 -#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 -#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 -#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 -#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 -#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 -#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 -#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 -#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 -#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 -#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 -#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 -#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 -#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 -#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 -#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 -#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 -#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 -#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 -#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 -#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 -#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 -#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 -#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 -#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 -#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0 -#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 -#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 -#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 -#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 -#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 -#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 -#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 -#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 -#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 -#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 -#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 -#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 -#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 -#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 -#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 -#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 -#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 -#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 -#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 -#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 -#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 -#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 -#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 -#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 -#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 -#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 -#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 -#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 -#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 -#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 -#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 -#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 -#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 -#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 -#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 -#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 -#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 -#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 -#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 -#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 -#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 -#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 -#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 -#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 -#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 -#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 -#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 -#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 -#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 -#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 -#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 -#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 -#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 -#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 -#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 -#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 -#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 -#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 -#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 -#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 -#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 -#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 -#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 -#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 -#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 -#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 -#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 -#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 -#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 -#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 -#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 -#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 -#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 -#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 -#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 -#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 -#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 -#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 -#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 -#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 -#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 -#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 -#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 -#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 -#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 -#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 -#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 -#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 -#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 -#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 -#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 -#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 -#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 -#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 -#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 -#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 -#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 -#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 -#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 -#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 -#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 -#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 -#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 -#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 -#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 -#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 -#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 -#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 -#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 -#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 -#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 -#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 -#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 -#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 -#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 -#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 -#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 -#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 -#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 -#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 -#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 -#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 -#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 -#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 -#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 -#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 -#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 -#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 -#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 -#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 -#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 -#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 -#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 -#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 -#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 -#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 -#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 -#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 -#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 -#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 -#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 -#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 -#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 -#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 - -#endif /* __DTS_IMX6Q_PINFUNC_H */ diff --git a/arch/arm/dts/imx6sll-pinfunc.h b/arch/arm/dts/imx6sll-pinfunc.h deleted file mode 100644 index 713a346f4c8..00000000000 --- a/arch/arm/dts/imx6sll-pinfunc.h +++ /dev/null @@ -1,880 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP. - * - */ - -#ifndef __DTS_IMX6SLL_PINFUNC_H -#define __DTS_IMX6SLL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 -#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 -#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 -#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 -#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 -#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 -#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 -#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 -#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 -#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 -#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 -#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 -#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 -#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 -#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 -#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 -#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 -#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 -#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 -#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 -#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 -#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 -#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 -#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 -#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 -#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 -#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 -#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 -#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 -#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 -#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 -#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 -#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 -#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 -#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 -#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 -#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 -#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 -#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 -#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 -#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 -#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 -#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 -#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 -#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 -#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 -#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 -#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 -#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 -#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 -#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 -#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 -#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 -#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 -#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 -#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 -#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 -#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 -#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 -#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 -#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 -#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 -#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 -#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 -#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 -#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 -#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 -#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 -#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 -#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 -#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 -#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 -#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 -#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 -#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 -#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 -#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 -#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 -#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 -#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 -#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 -#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 -#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 -#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 -#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 -#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 -#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 -#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 -#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 -#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 -#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 -#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 -#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 -#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 -#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 -#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 -#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 -#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 -#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 -#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 -#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 -#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 -#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 -#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 -#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 -#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 -#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 -#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 -#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 -#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 -#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 -#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 -#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 -#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 -#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 -#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 -#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 -#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 -#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 -#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 -#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 -#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 -#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 -#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 -#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 -#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 -#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 -#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 -#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 -#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 -#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 -#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 -#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 -#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 -#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 -#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 -#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 -#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 -#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 -#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 -#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 -#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 -#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 -#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 -#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 -#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 -#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 -#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 -#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 -#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 -#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 -#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 -#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 -#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 -#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 -#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 -#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 -#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 -#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 -#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 -#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 -#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 -#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 -#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 -#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 -#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 -#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 -#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 -#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 -#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 -#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 -#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 -#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 -#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 -#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 -#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 -#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 -#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 -#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 -#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 -#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 -#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 -#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 -#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 -#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 -#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 -#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 -#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 -#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 -#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 -#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 -#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 -#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 -#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 -#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 -#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 -#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 -#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 -#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 -#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 -#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 -#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 -#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 -#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 -#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 -#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 -#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 -#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 -#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 -#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 -#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 -#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 -#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 -#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 -#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 -#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 -#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 -#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 -#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 -#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 -#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 -#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 -#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 -#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 -#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 -#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 -#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 -#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 -#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 -#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 -#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 -#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 -#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 -#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 -#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 -#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 -#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 -#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 -#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 -#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 -#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 -#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 -#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 -#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 -#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 -#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 -#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 -#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 -#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 -#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 -#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 -#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 -#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 -#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 -#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 -#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 -#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 -#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 -#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 - -#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6sx-pinfunc.h b/arch/arm/dts/imx6sx-pinfunc.h deleted file mode 100644 index f4dc4620795..00000000000 --- a/arch/arm/dts/imx6sx-pinfunc.h +++ /dev/null @@ -1,1668 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6SX_PINFUNC_H -#define __DTS_IMX6SX_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x0024 0x036C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX 0x0024 0x036C 0x0830 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x0028 0x0370 0x0830 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX 0x0028 0x0370 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x002C 0x0374 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX 0x002C 0x0374 0x0838 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x0030 0x0378 0x0838 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX 0x0030 0x0378 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 -#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 -#define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1 -#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2 -#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0 -#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0 -#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0 -#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0 -#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0 -#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0 -#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1 -#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0 -#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1 -#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0 -#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1 -#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1 -#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0 -#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1 -#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1 -#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0 -#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0 -#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0 -#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 -#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x005C 0x03A4 0x0858 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_DTE_TX 0x005C 0x03A4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0 -#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 -#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 -#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x0060 0x03A8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA05__UART6_DTE_RX 0x0060 0x03A8 0x0858 0x4 0x1 -#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0 -#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 -#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 -#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 -#define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0 -#define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0 -#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 -#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 -#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1 -#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 -#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 -#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 -#define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2 -#define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0 -#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 -#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 -#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_MCLK__UART4_DCE_RX 0x0070 0x03B8 0x0848 0x3 0x2 -#define MX6SX_PAD_CSI_MCLK__UART4_DTE_TX 0x0070 0x03B8 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0 -#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 -#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX 0x0074 0x03BC 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX 0x0074 0x03BC 0x0848 0x3 0x3 -#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2 -#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0 -#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 -#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 -#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 -#define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0 -#define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3 -#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 -#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 -#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 -#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0 -#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0 -#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1 -#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1 -#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1 -#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1 -#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1 -#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1 -#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2 -#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0 -#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1 -#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1 -#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 -/* - * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is - * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a - * PHY in RMII mode. This configuration is valid if: - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset - * It seems to be a silicon bug that in this configuration ENET1_TX reference - * clock isn't provided automatically. According to i.MX6SX reference manual - * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it - * should be the case. - * So this might have unwanted side effects for other hardware units that are - * also connected to that pin and using respective function as input (e.g. - * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). - */ -#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 -#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 -#define MX6SX_PAD_ENET2_COL__UART1_DCE_RX 0x0094 0x03DC 0x0830 0x3 0x2 -#define MX6SX_PAD_ENET2_COL__UART1_DTE_TX 0x0094 0x03DC 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 -#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 -#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 -#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 -#define MX6SX_PAD_ENET2_CRS__UART1_DCE_TX 0x0098 0x03E0 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_CRS__UART1_DTE_RX 0x0098 0x03E0 0x0830 0x3 0x3 -#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 -#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 -#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2 -#define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3 -#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0 -#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 -#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2 -#define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 -#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 -#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1 -#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0 -#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL1__UART6_DCE_TX 0x00A8 0x03F0 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL1__UART6_DTE_RX 0x00A8 0x03F0 0x0858 0x2 0x2 -#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 -#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 -#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 -#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 -#define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2 -#define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x00B0 0x03F8 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_COL3__UART5_DTE_RX 0x00B0 0x03F8 0x0850 0x2 0x2 -#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 -#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2 -#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0 -#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3 -#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 -#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 -#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1 -#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW1__UART6_DCE_RX 0x00BC 0x0404 0x0858 0x2 0x3 -#define MX6SX_PAD_KEY_ROW1__UART6_DTE_TX 0x00BC 0x0404 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 -#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 -#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0 -#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 -#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 -#define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3 -#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 -#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 -#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x00C4 0x040C 0x0850 0x2 0x3 -#define MX6SX_PAD_KEY_ROW3__UART5_DTE_TX 0x00C4 0x040C 0x0000 0x2 0x0 -#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 -#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 -#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0 -#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0 -#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3 -#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2 -#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0 -#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0 -#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0 -#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0 -#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1 -#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0 -#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0 -#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1 -#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0 -#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0 -#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0 -#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1 -#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0 -#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0 -#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0 -#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1 -#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0 -#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0 -#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0 -#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1 -#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0 -#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0 -#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0 -#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1 -#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1 -#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0 -#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0 -#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0 -#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0 -#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0 -#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0 -#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0 -#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0 -#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0 -#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0 -#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0 -#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0 -#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0 -#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0 -#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0 -#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0 -#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0 -#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0 -#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0 -#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0 -#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0 -#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0 -#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0 -#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0 -#define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 -#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1 -#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 -#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_DCE_RX 0x0168 0x04B0 0x0840 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_DTE_TX 0x0168 0x04B0 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA07__UART3_DCE_TX 0x016C 0x04B4 0x0000 0x3 0x0 -#define MX6SX_PAD_NAND_DATA07__UART3_DTE_RX 0x016C 0x04B4 0x0840 0x3 0x1 -#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 -#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0 -#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0 -#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0 -#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0 -#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0 -#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0 -#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0 -#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0 -#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0 -#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0 -#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0 -#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0 -#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0 -#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0 -#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0 -#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2 -#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1 -#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1 -#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2 -#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2 -#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1 -#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4 -#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5 -#define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2 -#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0 -#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1 -#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1 -#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 -#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x01B8 0x0500 0x0000 0x1 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX 0x01B8 0x0500 0x0840 0x1 0x5 -#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 -#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2 -#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1 -#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0 -#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1 -#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1 -#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1 -#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1 -#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1 -#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0 -#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1 -#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0 -#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0 -#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0 -#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0 -#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0 -#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0 -#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0 -#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA0__UART2_DCE_RX 0x0228 0x0570 0x0838 0x4 0x2 -#define MX6SX_PAD_SD1_DATA0__UART2_DTE_TX 0x0228 0x0570 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 -#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA1__UART2_DCE_TX 0x022C 0x0574 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA1__UART2_DTE_RX 0x022C 0x0574 0x0838 0x4 0x3 -#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0 -#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 -#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 -#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2 -#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 -#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0 -#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 -#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 -#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3 -#define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0 -#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 -#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2 -#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1 -#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1 -#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2 -#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2 -#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1 -#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1 -#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2 -#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2 -#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 -#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA0__UART4_DCE_RX 0x0240 0x0588 0x0848 0x7 0x4 -#define MX6SX_PAD_SD2_DATA0__UART4_DTE_TX 0x0240 0x0588 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2 -#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1 -#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 -#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA1__UART4_DCE_TX 0x0244 0x058C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA1__UART4_DTE_RX 0x0244 0x058C 0x0848 0x7 0x5 -#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2 -#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1 -#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1 -#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 -#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA2__UART6_DCE_RX 0x0248 0x0590 0x0858 0x7 0x4 -#define MX6SX_PAD_SD2_DATA2__UART6_DTE_TX 0x0248 0x0590 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 -#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 -#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2 -#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1 -#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1 -#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 -#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 -#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 -#define MX6SX_PAD_SD2_DATA3__UART6_DCE_TX 0x024C 0x0594 0x0000 0x7 0x0 -#define MX6SX_PAD_SD2_DATA3__UART6_DTE_RX 0x024C 0x0594 0x0858 0x7 0x5 -#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 -#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0 -#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 -#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0 -#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_DCE_TX 0x0254 0x059C 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_DTE_RX 0x0254 0x059C 0x0848 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 -#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 -#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0 -#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0 -#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0 -#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0 -#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1 -#define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 -#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA3__UART4_DCE_RX 0x0264 0x05AC 0x0848 0x1 0x1 -#define MX6SX_PAD_SD3_DATA3__UART4_DTE_TX 0x0264 0x05AC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 -#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 -#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 -#define MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x0268 0x05B0 0x0840 0x3 0x2 -#define MX6SX_PAD_SD3_DATA4__UART3_DTE_TX 0x0268 0x05B0 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x026C 0x05B4 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA5__UART3_DTE_RX 0x026C 0x05B4 0x0840 0x3 0x3 -#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2 -#define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 -#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 -#define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0 -#define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3 -#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1 -#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0 -#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1 -#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0 -#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1 -#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1 -#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0 -#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0 -#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0 -#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0 -#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x0290 0x05D8 0x0850 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_DTE_TX 0x0290 0x05D8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 -#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x0294 0x05DC 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX 0x0294 0x05DC 0x0850 0x2 0x1 -#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 -#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0 -#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0 -#define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 -#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0 -#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1 -#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 -#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0 -#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0 -#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0 -#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0 -#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0 -#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0 -#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0 -#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1 -#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0 -#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0 -#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0 -#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0 -#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1 -#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 -#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 - -/* these are not supposed to be used any more and remove them after some time */ -#define MX6SX_PAD_GPIO1_IO04__UART1_RX MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX -#define MX6SX_PAD_GPIO1_IO04__UART1_TX MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX -#define MX6SX_PAD_GPIO1_IO05__UART1_RX MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX -#define MX6SX_PAD_GPIO1_IO05__UART1_TX MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX -#define MX6SX_PAD_GPIO1_IO06__UART2_RX MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX -#define MX6SX_PAD_GPIO1_IO06__UART2_TX MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX -#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS -#define MX6SX_PAD_GPIO1_IO07__UART2_RX MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX -#define MX6SX_PAD_GPIO1_IO07__UART2_TX MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX -#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS -#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS -#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS -#define MX6SX_PAD_CSI_DATA04__UART6_RX MX6SX_PAD_CSI_DATA04__UART6_DCE_RX -#define MX6SX_PAD_CSI_DATA04__UART6_TX MX6SX_PAD_CSI_DATA04__UART6_DTE_TX -#define MX6SX_PAD_CSI_DATA05__UART6_RX MX6SX_PAD_CSI_DATA05__UART6_DTE_RX -#define MX6SX_PAD_CSI_DATA05__UART6_TX MX6SX_PAD_CSI_DATA05__UART6_DCE_TX -#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS -#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS -#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS -#define MX6SX_PAD_CSI_MCLK__UART4_RX MX6SX_PAD_CSI_MCLK__UART4_DCE_RX -#define MX6SX_PAD_CSI_MCLK__UART4_TX MX6SX_PAD_CSI_MCLK__UART4_DTE_TX -#define MX6SX_PAD_CSI_PIXCLK__UART4_RX MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX -#define MX6SX_PAD_CSI_PIXCLK__UART4_TX MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX -#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS -#define MX6SX_PAD_ENET2_COL__UART1_RX MX6SX_PAD_ENET2_COL__UART1_DCE_RX -#define MX6SX_PAD_ENET2_COL__UART1_TX MX6SX_PAD_ENET2_COL__UART1_DTE_TX -#define MX6SX_PAD_ENET2_CRS__UART1_RX MX6SX_PAD_ENET2_CRS__UART1_DTE_RX -#define MX6SX_PAD_ENET2_CRS__UART1_TX MX6SX_PAD_ENET2_CRS__UART1_DCE_TX -#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS -#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS -#define MX6SX_PAD_KEY_COL0__UART6_RTS_B MX6SX_PAD_KEY_COL0__UART6_DCE_RTS -#define MX6SX_PAD_KEY_COL1__UART6_RX MX6SX_PAD_KEY_COL1__UART6_DTE_RX -#define MX6SX_PAD_KEY_COL1__UART6_TX MX6SX_PAD_KEY_COL1__UART6_DCE_TX -#define MX6SX_PAD_KEY_COL2__UART5_RTS_B MX6SX_PAD_KEY_COL2__UART5_DCE_RTS -#define MX6SX_PAD_KEY_COL3__UART5_RX MX6SX_PAD_KEY_COL3__UART5_DTE_RX -#define MX6SX_PAD_KEY_COL3__UART5_TX MX6SX_PAD_KEY_COL3__UART5_DCE_TX -#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS -#define MX6SX_PAD_KEY_ROW1__UART6_RX MX6SX_PAD_KEY_ROW1__UART6_DCE_RX -#define MX6SX_PAD_KEY_ROW1__UART6_TX MX6SX_PAD_KEY_ROW1__UART6_DTE_TX -#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS -#define MX6SX_PAD_KEY_ROW3__UART5_RX MX6SX_PAD_KEY_ROW3__UART5_DCE_RX -#define MX6SX_PAD_KEY_ROW3__UART5_TX MX6SX_PAD_KEY_ROW3__UART5_DTE_TX -#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS -#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS -#define MX6SX_PAD_NAND_DATA06__UART3_RX MX6SX_PAD_NAND_DATA06__UART3_DCE_RX -#define MX6SX_PAD_NAND_DATA06__UART3_TX MX6SX_PAD_NAND_DATA06__UART3_DTE_TX -#define MX6SX_PAD_NAND_DATA07__UART3_RX MX6SX_PAD_NAND_DATA07__UART3_DTE_RX -#define MX6SX_PAD_NAND_DATA07__UART3_TX MX6SX_PAD_NAND_DATA07__UART3_DCE_TX -#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS -#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS -#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX -#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX -#define MX6SX_PAD_SD1_DATA0__UART2_RX MX6SX_PAD_SD1_DATA0__UART2_DCE_RX -#define MX6SX_PAD_SD1_DATA0__UART2_TX MX6SX_PAD_SD1_DATA0__UART2_DTE_TX -#define MX6SX_PAD_SD1_DATA1__UART2_RX MX6SX_PAD_SD1_DATA1__UART2_DTE_RX -#define MX6SX_PAD_SD1_DATA1__UART2_TX MX6SX_PAD_SD1_DATA1__UART2_DCE_TX -#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS -#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS -#define MX6SX_PAD_SD2_DATA0__UART4_RX MX6SX_PAD_SD2_DATA0__UART4_DCE_RX -#define MX6SX_PAD_SD2_DATA0__UART4_TX MX6SX_PAD_SD2_DATA0__UART4_DTE_TX -#define MX6SX_PAD_SD2_DATA1__UART4_RX MX6SX_PAD_SD2_DATA1__UART4_DTE_RX -#define MX6SX_PAD_SD2_DATA1__UART4_TX MX6SX_PAD_SD2_DATA1__UART4_DCE_TX -#define MX6SX_PAD_SD2_DATA2__UART6_RX MX6SX_PAD_SD2_DATA2__UART6_DCE_RX -#define MX6SX_PAD_SD2_DATA2__UART6_TX MX6SX_PAD_SD2_DATA2__UART6_DTE_TX -#define MX6SX_PAD_SD2_DATA3__UART6_RX MX6SX_PAD_SD2_DATA3__UART6_DTE_RX -#define MX6SX_PAD_SD2_DATA3__UART6_TX MX6SX_PAD_SD2_DATA3__UART6_DCE_TX -#define MX6SX_PAD_SD3_CLK__UART4_CTS_B MX6SX_PAD_SD3_CLK__UART4_DCE_CTS -#define MX6SX_PAD_SD3_CMD__UART4_RX MX6SX_PAD_SD3_CMD__UART4_DTE_RX -#define MX6SX_PAD_SD3_CMD__UART4_TX MX6SX_PAD_SD3_CMD__UART4_DCE_TX -#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS -#define MX6SX_PAD_SD3_DATA3__UART4_RX MX6SX_PAD_SD3_DATA3__UART4_DCE_RX -#define MX6SX_PAD_SD3_DATA3__UART4_TX MX6SX_PAD_SD3_DATA3__UART4_DTE_TX -#define MX6SX_PAD_SD3_DATA4__UART3_RX MX6SX_PAD_SD3_DATA4__UART3_DCE_RX -#define MX6SX_PAD_SD3_DATA4__UART3_TX MX6SX_PAD_SD3_DATA4__UART3_DTE_TX -#define MX6SX_PAD_SD3_DATA5__UART3_RX MX6SX_PAD_SD3_DATA5__UART3_DTE_RX -#define MX6SX_PAD_SD3_DATA5__UART3_TX MX6SX_PAD_SD3_DATA5__UART3_DCE_TX -#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS -#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS -#define MX6SX_PAD_SD4_DATA4__UART5_RX MX6SX_PAD_SD4_DATA4__UART5_DCE_RX -#define MX6SX_PAD_SD4_DATA4__UART5_TX MX6SX_PAD_SD4_DATA4__UART5_DTE_TX -#define MX6SX_PAD_SD4_DATA5__UART5_RX MX6SX_PAD_SD4_DATA5__UART5_DTE_RX -#define MX6SX_PAD_SD4_DATA5__UART5_TX MX6SX_PAD_SD4_DATA5__UART5_DCE_TX -#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS -#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS - -#endif /* __DTS_IMX6SX_PINFUNC_H */ diff --git a/arch/arm/dts/imx6ul-pinfunc.h b/arch/arm/dts/imx6ul-pinfunc.h deleted file mode 100644 index 380d2db13a9..00000000000 --- a/arch/arm/dts/imx6ul-pinfunc.h +++ /dev/null @@ -1,959 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2014 - 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6UL_PINFUNC_H -#define __DTS_IMX6UL_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 -#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 - -#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 -#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 - -#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 -#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 -#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 -#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 -#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 -#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0610 6 0 -#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x05f0 2 0 -#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 -#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0614 6 0 -#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 -#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 -#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 -#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 -#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 -#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 -#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 -#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 -#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 -#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 -#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 -#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 -#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 -#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 -#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 -#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 -#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x0054 0x02e0 0x0000 6 0 -#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 -#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 -#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 -#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 -#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 -#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 -#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M 0x0058 0x02e4 0x0000 6 0 -#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 -#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 -#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 -#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 -#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 -#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 -#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 -#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 -#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0610 6 1 -#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 -#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 -#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 -#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 -#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02f4 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 -#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 -#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M 0x006c 0x02f8 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 -#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 -#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 -#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 -#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 -#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 -#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 -#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 -#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 -#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 -#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 -#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 -#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 -#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 -#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 -#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 -#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 -#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 -#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 -#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 -#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 -#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 -#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 -#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 -#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 -#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 -#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 -#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 -#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 -#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 -#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 -#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 -#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 -#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 -#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 -#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 -#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 -#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 -#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 -#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 -#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 -#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 -#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 -#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 -#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 -#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 -#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 -#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 -#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 -#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 -#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 -#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 -#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 -#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 -#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 -#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 -#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 -#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0560 8 0 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 -#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 -#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 -#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 -#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 -#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 -#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 -#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 -#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 -#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 -#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 -#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 -#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 -#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 -#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 -#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 -#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 -#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 -#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 -#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 -#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 -#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 -#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 -#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 -#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 -#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 -#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 -#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 -#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x04d4 3 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 -#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 -#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 -#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 -#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 -#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 -#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 -#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x04d0 3 0 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 -#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 -#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 -#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 -#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 -#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 -#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x04ec 3 0 -#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 -#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 -#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 -#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 -#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 -#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 -#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x04f0 3 0 -#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 -#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 -#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 -#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 -#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 -#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x04f4 3 0 -#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 -#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 -#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 -#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 -#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 -#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x04f8 3 0 -#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 -#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0550 8 1 -#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 -#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 -#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 -#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x04fc 3 0 -#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 -#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 -#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 -#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0500 3 0 -#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 -#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 -#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 -#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0504 3 0 -#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x05d0 6 0 -#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 -#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0508 3 0 -#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 -#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x05c4 6 0 -#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 -#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 -#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x00cc 0x0358 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x050c 3 0 -#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x05d4 6 0 -#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 -#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M 0x00d0 0x035c 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0510 3 0 -#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 -#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x05c8 6 0 -#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 -#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0514 3 0 -#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 -#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x05d8 6 0 -#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 -#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0518 3 0 -#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 -#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x05cc 6 0 -#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 -#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x051c 3 0 -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 -#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 -#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 -#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 -#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 -#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 -#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0520 3 0 -#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 -#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 -#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 -#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 -#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 -#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 -#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00e8 0x0374 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 -#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 -#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 -#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 -#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 -#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M 0x00f0 0x037c 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 -#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 -#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 -#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 -#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00f8 0x0384 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 -#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 -#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 -#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 -#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 -#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 -#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 -#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 -#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 -#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 -#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0570 3 0 -#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 -#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 -#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 -#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 -#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 -#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 -#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0600 3 0 -#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 -#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 -#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 -#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 -#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 -#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 -#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 -#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 -#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 -#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 -#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 -#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 -#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 -#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 -#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 -#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 -#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 -#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 -#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0604 3 0 -#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 -#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 -#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 -#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 -#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 -#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 -#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 -#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 -#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 0x0118 0x03a4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 -#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x05e0 8 1 -#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 0x011c 0x03a8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 -#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 -#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 0x0120 0x03ac 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 -#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 -#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 0x0124 0x03b0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 -#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x05e4 8 0 -#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 -#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 0x0128 0x03b4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 -#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 0x012c 0x03b8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 -#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 0x0130 0x03bc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 -#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 0x0134 0x03c0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 -#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 -#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 -#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 0x0138 0x03c4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0504 3 1 -#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0600 1 1 -#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 0x013c 0x03c8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0508 3 1 -#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 -#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 0x0140 0x03cc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x050c 3 1 -#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 0x0144 0x03d0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0510 3 1 -#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 -#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 -#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 0x0148 0x03d4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0514 3 1 -#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 -#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 0x014c 0x03d8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0518 3 1 -#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 -#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0604 1 1 -#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 0x0150 0x03dc 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x051c 3 1 -#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 -#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 0x0154 0x03e0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0520 3 1 -#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 -#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 -#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK 0x0158 0x03e4 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x04d4 3 1 -#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 -#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 -#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL 0x015c 0x03e8 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x04d0 3 1 -#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 -#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x04ec 3 1 -#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 -#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 -#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x04f0 3 1 -#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 -#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 -#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x04f4 3 1 -#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 -#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0540 2 0 -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x04f8 3 1 -#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 -#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x04fc 3 1 -#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 -#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 -#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 -#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0500 3 1 -#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 -#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 -#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 -#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 -#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 -#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 -#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x05d0 3 1 -#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 -#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 -#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 -#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 -#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 -#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 -#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x05c4 3 1 -#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 -#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 -#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 -#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x05d4 3 1 -#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 -#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x05c8 3 1 -#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 -#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x05d8 3 1 -#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 -#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x05cc 3 1 -#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 -#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 -#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 -#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 -#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 -#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 -#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 -#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 -#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 -#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 -#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 -#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 -#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0570 3 1 -#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 -#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 -#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 -#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 -#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 -#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 -#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 -#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 -#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 -#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 -#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 -#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 -#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 -#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 -#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 -#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 -#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 -#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 -#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 -#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0560 3 1 -#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 -#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 -#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 -#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 -#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 -#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 -#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 -#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 -#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 -#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 -#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 -#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 -#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 -#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 -#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 -#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 -#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 -#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 -#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 -#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 -#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 -#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 -#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 -#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 -#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 -#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 -#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 -#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 -#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 -#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 -#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0614 6 1 -#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 -#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 -#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 -#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 -#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 -#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 -#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0610 6 2 -#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 -#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 -#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x05f0 2 1 -#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 -#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 -#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 -#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 -#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 -#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 -#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 -#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 -#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 -#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 -#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 -#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 -#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 -#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 -#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 -#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 -#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 -#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 -#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 -#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 -#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 -#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 -#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 -#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 -#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 -#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 -#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 -#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 -#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 -#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 -#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 -#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 -#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 -#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 -#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 -#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 -#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 -#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 -#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 -#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 -#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 -#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 -#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 -#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 -#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 -#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 -#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 -#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 -#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 -#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 -#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 -#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 -#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 -#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 -#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 -#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 -#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 -#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 -#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 -#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 -#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0550 3 0 -#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x05e0 6 0 -#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 -#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 -#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 -#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 -#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 -#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 -#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 -#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 -#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 -#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 -#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 -#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 -#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 -#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 -#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 -#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 -#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0540 3 1 -#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 -#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 -#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 -#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 -#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 -#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x05e4 6 1 -#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 -#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 -#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 -#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 -#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 -#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 -#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 -#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 -#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 - -#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6ull-pinfunc-snvs.h b/arch/arm/dts/imx6ull-pinfunc-snvs.h deleted file mode 100644 index 54cfe72295a..00000000000 --- a/arch/arm/dts/imx6ull-pinfunc-snvs.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright (C) 2017 NXP - */ - -#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H -#define __DTS_IMX6ULL_PINFUNC_SNVS_H -/* - * The pin function ID is a tuple of - * - */ -#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 -#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 -#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 - -#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ diff --git a/arch/arm/dts/imx6ull-pinfunc.h b/arch/arm/dts/imx6ull-pinfunc.h deleted file mode 100644 index 7328d4ef855..00000000000 --- a/arch/arm/dts/imx6ull-pinfunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX6ULL_PINFUNC_H -#define __DTS_IMX6ULL_PINFUNC_H - -#include "imx6ul-pinfunc.h" -/* - * The pin function ID is a tuple of - * - */ -/* signals common for i.MX6UL and i.MX6ULL */ -#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX -#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 -#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX -#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 -#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 -#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 -#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 - -/* signals for i.MX6ULL only */ -#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 -#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 -#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3 -#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4 -#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0 -#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 -#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0 -#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 -#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0 - -#endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/arch/arm/dts/imx7-colibri.dtsi b/arch/arm/dts/imx7-colibri.dtsi index a8c31ee6562..4c0b5ec6c61 100644 --- a/arch/arm/dts/imx7-colibri.dtsi +++ b/arch/arm/dts/imx7-colibri.dtsi @@ -669,7 +669,7 @@ pinctrl_can_int: canintgrp { fsl,pins = < - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x14 /* SODIMM 73 */ >; }; diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h deleted file mode 100644 index 69f2c1ec825..00000000000 --- a/arch/arm/dts/imx7d-pinfunc.h +++ /dev/null @@ -1,1154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_IMX7D_PINFUNC_H -#define __DTS_IMX7D_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 -#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 -#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 -#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 -#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 -#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 -#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0 -#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0 -#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1 -#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0 -#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0 -#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0 -#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1 -#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0 -#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0 -#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0 -#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0 -#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0 -#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0 -#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0 -#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0 -#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1 -#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0 -#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0 -#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0 -#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0 -#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0 -#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0 -#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0 -#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0 -#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0 -#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 -#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 -#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 -#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 -#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 -#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 -#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 -#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 -#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 -#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 -#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 -#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 -#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 -#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 -#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 -#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 -#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 -#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 -#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 -#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 -#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 -#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 -#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 -#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 -#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 -#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 -#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 -#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 -#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 -#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 -#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 -#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 -#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 -#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 -#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 -#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 -#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 -#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 -#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 -#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 -#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 -#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 -#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 -#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 -#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 -#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 -#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 -#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 -#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 -#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 -#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 -#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 -#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 -#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 -#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 -#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 -#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 -#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 -#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 -#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 -#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 -#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 -#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 -#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 -#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 -#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 -#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 -#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 -#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 -#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 -#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 -#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 -#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 -#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 -#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 -#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 -#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 -#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 -#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 -#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 -#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 -#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 -#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 -#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 -#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 -#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 -#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 -#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 -#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 -#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 -#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 -#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 -#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 -#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 -#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 -#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 -#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 -#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 -#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 -#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 -#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 -#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 -#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 -#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 -#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 -#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 -#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 -#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 -#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 -#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 -#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 -#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 -#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 -#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 -#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 -#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 -#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 -#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 -#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 -#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 -#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 -#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 -#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 -#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 -#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 -#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 -#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 -#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 -#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 -#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 -#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 -#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 -#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 -#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 -#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 -#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 -#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 -#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 -#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 -#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 -#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 -#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 -#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 -#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 -#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 -#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1 -#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 -#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 -#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 -#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 -#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 -#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 -#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 -#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 -#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 -#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 -#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 -#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 -#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2 -#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 -#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 -#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 -#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 -#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 -#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 -#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 -#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 -#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 -#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 -#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 -#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 -#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 -#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 -#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 -#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 -#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 -#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 -#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 -#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 -#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 -#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 -#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 -#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 -#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 -#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 -#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 -#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 -#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 -#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 -#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 -#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 -#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 -#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 -#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 -#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 -#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 -#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 -#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 -#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 -#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 -#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 -#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 -#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 -#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 -#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 -#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 -#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 -#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 -#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 -#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 -#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 -#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 -#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 -#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 -#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 -#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 -#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 -#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 -#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 -#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 -#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 -#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 -#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 -#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 -#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 -#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 -#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 -#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 -#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 -#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 -#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 -#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 -#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 -#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 -#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 -#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 -#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 -#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 -#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 -#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 -#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 -#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 -#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 -#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 -#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 -#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 -#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 -#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 -#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 -#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 -#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 -#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 -#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 -#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 -#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 -#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 -#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 -#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 -#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 -#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 -#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 -#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 -#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 -#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 -#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 -#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 -#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 -#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 -#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 -#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 -#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 -#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 -#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 -#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 -#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 -#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 -#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 -#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 -#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 -#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 -#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 -#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 -#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 -#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 -#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 -#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 -#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 -#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 -#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 -#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 -#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 -#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 -#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 -#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 -#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 -#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 -#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 -#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 -#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 -#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 -#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 -#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 -#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 -#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 -#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 -#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 -#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 -#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 -#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 -#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 -#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 -#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 -#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 -#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 -#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 -#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 -#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 -#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 -#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 -#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 -#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 -#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 -#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 -#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 -#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 -#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 -#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 -#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 -#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 -#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 -#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 -#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 -#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 -#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 -#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 -#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 -#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 -#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 -#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 -#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 -#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 -#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 -#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 -#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 -#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 -#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 -#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 -#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 -#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 -#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 -#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 -#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 -#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 -#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 -#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 -#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 -#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 -#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 -#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 -#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 -#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 -#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 -#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 -#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 -#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 -#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 -#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 -#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 -#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 -#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 -#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 - -#endif /* __DTS_IMX7D_PINFUNC_H */ diff --git a/arch/arm/dts/imx7ulp-pinfunc.h b/arch/arm/dts/imx7ulp-pinfunc.h deleted file mode 100644 index c0148d79b62..00000000000 --- a/arch/arm/dts/imx7ulp-pinfunc.h +++ /dev/null @@ -1,478 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DTS_IMX7ULP_PINFUNC_H -#define __DTS_IMX7ULP_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 -#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 -#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 -#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 -#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 -#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 -#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 -#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 -#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 -#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 -#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 -#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 -#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 -#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 -#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 -#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 -#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 -#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 -#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 -#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 -#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 -#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 -#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 -#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 -#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 -#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 -#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 -#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 -#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 -#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 -#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 -#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 -#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 -#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 -#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 -#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 -#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 -#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 -#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 -#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 -#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 -#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 -#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 -#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 -#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 -#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 -#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 -#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 -#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 -#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 -#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 -#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 -#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 -#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 -#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 -#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 -#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 -#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 -#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 -#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 -#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 -#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 -#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 -#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 -#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 -#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 -#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 -#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 -#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 -#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 -#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 -#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 -#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 -#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 -#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1 -#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 -#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 -#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 -#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3 -#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3 -#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 -#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 -#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 -#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 -#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 -#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 -#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 -#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 -#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 -#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 -#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 -#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 -#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 -#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 -#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 -#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 -#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 -#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 -#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 -#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 -#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 -#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2 -#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 -#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 -#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 -#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 -#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 -#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 -#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 -#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 -#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 -#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 -#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 -#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 -#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 -#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 -#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 -#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 -#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 -#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 -#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 -#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 -#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 -#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 -#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 -#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 -#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 -#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 -#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 -#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 -#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 -#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 -#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 -#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 -#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 -#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 -#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 -#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 -#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 -#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 -#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 -#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 -#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 -#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0 -#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 -#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 -#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 -#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 -#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 -#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 -#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 -#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 -#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 -#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 -#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 -#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 -#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 -#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 -#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 -#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 -#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 -#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 -#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 -#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 -#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 -#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 -#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 -#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 -#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 -#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 -#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 -#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 -#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 -#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 -#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 -#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 -#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 -#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 -#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 -#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 -#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 -#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 -#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 -#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 -#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 -#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 -#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 -#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 -#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 -#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 -#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 -#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 -#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 -#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 -#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 -#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 -#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 -#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 -#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 -#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 -#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 -#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 -#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 -#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 -#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 -#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 -#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 -#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 -#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 -#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 -#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 -#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 -#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 -#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 -#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 -#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 -#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 -#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 -#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 - -#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h deleted file mode 100644 index 83c8f715cd9..00000000000 --- a/arch/arm/dts/imx8mm-pinfunc.h +++ /dev/null @@ -1,646 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __DTS_IMX8MM_PINFUNC_H -#define __DTS_IMX8MM_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53C 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 -#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 -#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 -#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 -#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 -#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 -#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 -#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 - -#endif /* __DTS_IMX8MM_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mn-pinfunc.h b/arch/arm/dts/imx8mn-pinfunc.h deleted file mode 100644 index faf1e69e742..00000000000 --- a/arch/arm/dts/imx8mn-pinfunc.h +++ /dev/null @@ -1,646 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __DTS_IMX8MN_PINFUNC_H -#define __DTS_IMX8MN_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 -#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 -#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x4BC 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x4C0 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x048 0x2B0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x04C 0x2B4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x050 0x2B8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x068 0x2D0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x068 0x2D0 0x540 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0 -#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x068 0x2D0 0x59C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x06C 0x2D4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x06C 0x2D4 0x53C 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x06C 0x2D4 0x550 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x070 0x2D8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x070 0x2D8 0x538 0x3 0x1 -#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1 -#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x070 0x2D8 0x584 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x074 0x2DC 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x074 0x2DC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x074 0x2DC 0x540 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x074 0x2DC 0x54C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x078 0x2E0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x078 0x2E0 0x53C 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x078 0x2E0 0x598 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x07C 0x2E4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x07C 0x2E4 0x538 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x07C 0x2E4 0x5B8 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x080 0x2E8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x080 0x2E8 0x5B4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x084 0x2EC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x084 0x2EC 0x5B0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x574 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x088 0x2F0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x088 0x2F0 0x540 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x088 0x2F0 0x5E4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x5C8 0x1 0x0 -#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x08C 0x2F4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x08C 0x2F4 0x53C 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x08C 0x2F4 0x5E0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x57C 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x090 0x2F8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x090 0x2F8 0x538 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x090 0x2F8 0x558 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x554 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x094 0x2FC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x094 0x2FC 0x534 0x3 0x1 -#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x094 0x2FC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x098 0x300 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x098 0x300 0x000 0x3 0x0 -#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x098 0x300 0x5A0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x09C 0x304 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x09C 0x304 0x5CC 0x3 0x5 -#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x09C 0x304 0x5DC 0x6 0x1 -#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x0A0 0x308 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4 -#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x0A4 0x30C 0x4C0 0x1 0x3 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x0A4 0x30C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x0A8 0x310 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x0A8 0x310 0x4F0 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x0A8 0x310 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x0AC 0x314 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x0AC 0x314 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x0AC 0x314 0x4F0 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x0B0 0x318 0x57C 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x0B0 0x318 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x0B0 0x318 0x4FC 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x0B4 0x31C 0x554 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x0B4 0x31C 0x4FC 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x0B4 0x31C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x0B8 0x320 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x0B8 0x320 0x55C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x0B8 0x320 0x4F8 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x0B8 0x320 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x0BC 0x324 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x0BC 0x324 0x56C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x0BC 0x324 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x0BC 0x324 0x4F8 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x0C0 0x328 0x574 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x0C0 0x328 0x5D0 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x0C0 0x328 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x0C0 0x328 0x504 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x0C4 0x32C 0x5C8 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x0C4 0x32C 0x560 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x0C4 0x32C 0x504 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x0C4 0x32C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x0C8 0x330 0x5A4 0x1 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0C8 0x330 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x0C8 0x330 0x588 0x3 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x0C8 0x330 0x500 0x4 0x2 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x0C8 0x330 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x0CC 0x334 0x5BC 0x3 0x1 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x0CC 0x334 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x0CC 0x334 0x500 0x4 0x3 -#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x0D0 0x338 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x0D4 0x33C 0x4E4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x0D4 0x33C 0x580 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x0D4 0x33C 0x50C 0x3 0x4 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x0D4 0x33C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x0D4 0x33C 0x594 0x4 0x1 -#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x0D8 0x340 0x4D0 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x0D8 0x340 0x590 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x0D8 0x340 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x0D8 0x340 0x50C 0x3 0x5 -#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x0D8 0x340 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x0DC 0x344 0x4D4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x0DC 0x344 0x58C 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x0DC 0x344 0x4FC 0x3 0x6 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x0DC 0x344 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x0DC 0x344 0x534 0x4 0x2 -#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x0E0 0x348 0x4EC 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x0E0 0x348 0x5D4 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x0E0 0x348 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x0E0 0x348 0x4FC 0x3 0x7 -#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x0E0 0x348 0x538 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x0E4 0x34C 0x4E8 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x0E4 0x34C 0x570 0x2 0x2 -#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x0E4 0x34C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x0E4 0x34C 0x53C 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x0E8 0x350 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x0E8 0x350 0x578 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x0E8 0x350 0x5CC 0x3 0x2 -#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x0E8 0x350 0x540 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x0F0 0x358 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x0F4 0x35C 0x534 0x3 0x3 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x0F4 0x35C 0x504 0x4 0x6 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x0F4 0x35C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x0F4 0x35C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x0F8 0x360 0x538 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x0F8 0x360 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x0F8 0x360 0x504 0x4 0x7 -#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x0F8 0x360 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x59C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x0FC 0x364 0x534 0x3 0x4 -#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x0FC 0x364 0x5D4 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x0FC 0x364 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6 -#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x584 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x104 0x36C 0x53C 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x104 0x36C 0x5BC 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x104 0x36C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x54C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x108 0x370 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x10C 0x374 0x53C 0x3 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x10C 0x374 0x50C 0x4 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x10C 0x374 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x10C 0x374 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x110 0x378 0x540 0x3 0x5 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x110 0x378 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x110 0x378 0x50C 0x4 0x7 -#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x110 0x378 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x114 0x37C 0x598 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x114 0x37C 0x58C 0x4 0x3 -#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x114 0x37C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x118 0x380 0x5B8 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x118 0x380 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x5B4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x11C 0x384 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x5B0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x120 0x388 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x5E4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x124 0x38C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x12C 0x394 0x000 0x3 0x0 -#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x12C 0x394 0x588 0x4 0x2 -#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x12C 0x394 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x558 0x2 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x130 0x398 0x538 0x3 0x7 -#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x130 0x398 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6 -#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3 -#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x5A0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x138 0x3A0 0x5BC 0x4 0x3 -#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x138 0x3A0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x5DC 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x13C 0x3A4 0x58C 0x4 0x4 -#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x13C 0x3A4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x148 0x3B0 0x534 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x14C 0x3B4 0x538 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x150 0x3B8 0x53C 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x154 0x3BC 0x540 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x594 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x1B0 0x418 0x000 0x2 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x1B0 0x418 0x5AC 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x1B0 0x418 0x53C 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x1B4 0x41C 0x538 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x1B8 0x420 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x1B8 0x420 0x540 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x1BC 0x424 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x1BC 0x424 0x53C 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x1C0 0x428 0x538 0x6 0x9 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x1C4 0x42C 0x540 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x594 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x1C8 0x430 0x5C0 0x6 0x1 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x5F0 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x1CC 0x434 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x1CC 0x434 0x5CC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x1CC 0x434 0x534 0x6 0x5 -#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x5E8 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x1D0 0x438 0x5AC 0x3 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x1D0 0x438 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x1D4 0x43C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x1D8 0x440 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x1D8 0x440 0x540 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x1DC 0x444 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x1DC 0x444 0x53C 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x1E0 0x448 0x568 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x1E0 0x448 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x5C0 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x594 0x2 0x3 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x1E4 0x44C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x1E4 0x44C 0x5CC 0x6 0x4 -#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x5CC 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x568 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x5D8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x1F4 0x45C 0x55C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x1F4 0x45C 0x4DC 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x5A8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x1F8 0x460 0x56C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x1F8 0x460 0x4D0 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x5C4 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x1FC 0x464 0x5D0 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x1FC 0x464 0x4D4 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x564 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x200 0x468 0x560 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x200 0x468 0x4D8 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x200 0x468 0x4EC 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x580 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x204 0x46C 0x588 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x204 0x46C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x204 0x46C 0x4E8 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x590 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x208 0x470 0x5BC 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x208 0x470 0x4E0 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x208 0x470 0x000 0x4 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x578 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x20C 0x474 0x5D4 0x2 0x3 -#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x20C 0x474 0x594 0x3 0x4 -#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x570 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x210 0x478 0x58C 0x2 0x5 -#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x55C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x214 0x47C 0x5D8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x56C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x218 0x480 0x5A8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x5D0 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x21C 0x484 0x598 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x21C 0x484 0x5C4 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x560 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x220 0x488 0x5B8 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x220 0x488 0x564 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x5BC 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x228 0x490 0x590 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x5D4 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x22C 0x494 0x578 0x3 0x2 -#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x58C 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x230 0x498 0x570 0x3 0x1 -#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1 -#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x23C 0x4A4 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x240 0x4A8 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x244 0x4AC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x244 0x4AC 0x5EC 0x3 0x1 -#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1 -#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x24C 0x4B4 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1 -#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 - -#endif /* __DTS_IMX8MN_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mp-pinfunc.h b/arch/arm/dts/imx8mp-pinfunc.h deleted file mode 100644 index 0fef066471b..00000000000 --- a/arch/arm/dts/imx8mp-pinfunc.h +++ /dev/null @@ -1,799 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef __DTS_IMX8MP_PINFUNC_H -#define __DTS_IMX8MP_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 -#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 -#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 -#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 0x058 0x2B8 0x4CC 0x3 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 0x05C 0x2BC 0x4C8 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 0x060 0x2C0 0x4C4 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 0x064 0x2C4 0x4C0 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 -#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK 0x068 0x2C8 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 -#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT 0x06C 0x2CC 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK 0x084 0x2E4 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN 0x088 0x2E8 0x544 0x3 0x0 -#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 -#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 -#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 -#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 -#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 -#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 -#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 -#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 -#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 -#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 -#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 -#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 0x0C4 0x324 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 -#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 -#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 -#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 -#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT 0x0D0 0x330 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 -#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x0E0 0x340 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 -#define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 -#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 -#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 -#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 -#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 -#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 -#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 -#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x0F4 0x354 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 -#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 -#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 -#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x100 0x360 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 -#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 -#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x104 0x364 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 -#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 -#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 -#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x108 0x368 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 -#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x110 0x370 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x114 0x374 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 0x118 0x378 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 -#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 -#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 -#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x120 0x380 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 -#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x124 0x384 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 -#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 -#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 -#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 -#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0x130 0x390 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 -#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0x14C 0x3AC 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 -#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 -#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 -#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 -#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 -#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 -#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 -#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK 0x194 0x3F4 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 -#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 -#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 -#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 -#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 -#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 -#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 -#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 -#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 -#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 -#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 -#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN 0x1B8 0x418 0x544 0x4 0x2 -#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 -#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x1BC 0x41C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 -#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 -#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 -#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 -#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT 0x1D0 0x430 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN 0x1D0 0x430 0x544 0x6 0x3 -#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0x1D4 0x434 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 -#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0x1D8 0x438 0x544 0x0 0x4 -#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 -#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 -#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 -#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 -#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 -#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 -#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 -#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 -#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 -#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 -#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 -#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 -#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 0x1F8 0x458 0x000 0x4 0x0 -#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 -#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 -#define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 -#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 -#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 -#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 -#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 -#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 -#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 -#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 -#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 -#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 -#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 -#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 -#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 -#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 -#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 -#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 -#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 -#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 -#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 -#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 -#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 -#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 -#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 -#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 -#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 -#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 -#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 -#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 -#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 -#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 -#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 -#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 -#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 -#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 -#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 -#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 -#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 -#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 -#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 -#define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 -#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 -#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 -#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 -#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 -#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 -#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 -#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x240 0x4A0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x244 0x4A4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x248 0x4A8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x24C 0x4AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 -#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 - -#endif /* __DTS_IMX8MP_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi index a90794d8108..95f5f15e742 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -98,6 +98,13 @@ gpios = <6 GPIO_ACTIVE_HIGH>; line-name = "m2_rst"; }; + + m2_wdis2 { + gpio-hog; + output-high; + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "m2_wdis2#"; + }; }; &gpio4 { @@ -110,11 +117,11 @@ line-name = "m2_off#"; }; - m2_wdis { + m2_wdis1 { gpio-hog; output-high; gpios = <18 GPIO_ACTIVE_HIGH>; - line-name = "m2_wdis#"; + line-name = "m2_wdis1#"; }; rs485_en { diff --git a/arch/arm/dts/imx8mp-venice-gw82xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw82xx-2x-u-boot.dtsi new file mode 100644 index 00000000000..2d58b3b8ab7 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw82xx-2x-u-boot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Gateworks Corporation + */ +#include "imx8mp-venice-gw702x-u-boot.dtsi" + +&gpio4 { + dio_1 { + gpio-hog; + input; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "dio0#"; + }; + + usb1mux { + gpio-hog; + output-high; + gpios = <17 GPIO_ACTIVE_HIGH>; + line-name = "usb1_mux"; + }; + + rs485_en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en"; + }; + + rs485_term { + gpio-hog; + output-low; + gpios = <23 GPIO_ACTIVE_HIGH>; + line-name = "rs485_term"; + }; + + rs485_half { + gpio-hog; + output-low; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "rs485_hd"; + }; +}; diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h deleted file mode 100644 index 68e8fa17297..00000000000 --- a/arch/arm/dts/imx8mq-pinfunc.h +++ /dev/null @@ -1,623 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DTS_IMX8MQ_PINFUNC_H -#define __DTS_IMX8MQ_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 - -#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index f67fe166d31..845fe205925 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -28,7 +28,6 @@ &iomuxc1 { bootph-pre-ram; - fsl,mux_mask = <0xf00>; }; &pinctrl_lpuart5 { diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h deleted file mode 100644 index b204ac79b44..00000000000 --- a/arch/arm/dts/imx8ulp-pinfunc.h +++ /dev/null @@ -1,978 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2021 NXP - */ - -#ifndef __DTS_IMX8ULP_PINFUNC_H -#define __DTS_IMX8ULP_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 -#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 -#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 -#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 -#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 -#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 -#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 -#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1 -#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 -#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1 -#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1 -#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1 -#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1 -#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1 -#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1 -#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1 -#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1 -#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1 -#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1 -#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1 -#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1 -#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1 -#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1 -#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1 -#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2 -#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1 -#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1 -#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1 -#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1 -#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1 -#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1 -#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1 -#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1 -#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1 -#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1 -#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1 -#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1 -#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1 -#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1 -#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1 -#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1 -#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1 -#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 -#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1 -#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1 -#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1 -#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1 -#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1 -#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 -#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2 -#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1 -#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1 -#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1 -#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1 -#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 -#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 -#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2 -#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1 -#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1 -#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1 -#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2 -#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1 -#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1 -#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1 -#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 -#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2 -#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1 -#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1 -#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1 -#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 -#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1 -#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2 -#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1 -#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1 -#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 -#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1 -#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2 -#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1 -#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1 -#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 -#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1 -#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2 -#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1 -#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1 -#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 -#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1 -#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1 -#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 -#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1 -#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2 -#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2 -#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1 -#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1 -#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1 -#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3 -#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1 -#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2 -#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2 -#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1 -#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1 -#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2 -#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1 -#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1 -#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3 -#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4 -#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2 -#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2 -#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1 -#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1 -#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3 -#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2 -#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2 -#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1 -#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1 -#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1 -#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1 -#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3 -#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2 -#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2 -#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2 -#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1 -#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2 -#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1 -#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3 -#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2 -#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2 -#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1 -#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1 -#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1 -#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3 -#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2 -#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1 -#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2 -#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1 -#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1 -#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2 -#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1 -#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1 -#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1 -#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2 -#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1 -#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2 -#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1 -#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1 -#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2 -#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1 -#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1 -#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1 -#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2 -#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1 -#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2 -#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1 -#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1 -#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2 -#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1 -#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1 -#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2 -#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1 -#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2 -#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1 -#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1 -#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2 -#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1 -#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1 -#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1 -#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2 -#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1 -#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2 -#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1 -#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1 -#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1 -#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1 -#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1 -#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2 -#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1 -#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1 -#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2 -#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1 -#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1 -#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1 -#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1 -#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1 -#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2 -#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1 -#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1 -#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2 -#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1 -#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1 -#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2 -#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1 -#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1 -#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1 -#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2 -#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1 -#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1 -#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2 -#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1 -#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1 -#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1 -#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1 -#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2 -#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2 -#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1 -#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2 -#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1 -#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1 -#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2 -#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1 -#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1 -#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1 -#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2 -#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2 -#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2 -#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2 -#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1 -#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1 -#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2 -#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2 -#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0 -#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2 -#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1 -#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1 -#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1 -#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2 -#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2 -#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2 -#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1 -#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1 -#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1 -#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2 -#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1 -#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2 -#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1 -#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1 -#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1 -#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2 -#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2 -#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1 -#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5 -#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1 -#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1 -#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2 -#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2 -#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1 -#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1 -#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2 -#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2 -#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2 -#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2 -#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2 -#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2 -#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3 -#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2 -#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2 -#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2 -#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2 -#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2 -#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2 -#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2 -#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2 -#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2 -#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2 -#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3 -#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2 -#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2 -#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2 -#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2 -#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2 -#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2 -#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3 -#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2 -#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2 -#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1 -#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2 -#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2 -#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3 -#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2 -#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3 -#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2 -#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1 -#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2 -#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2 -#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2 -#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0 -#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2 -#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3 -#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2 -#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3 -#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1 -#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2 -#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2 -#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3 -#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2 -#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2 -#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3 -#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1 -#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2 -#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2 -#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2 -#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3 -#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3 -#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3 -#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1 -#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2 -#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2 -#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2 -#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3 -#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3 -#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1 -#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2 -#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2 -#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0 -#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2 -#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3 -#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3 -#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3 -#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1 -#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2 -#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2 -#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2 -#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3 -#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3 -#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2 -#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2 -#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2 -#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2 -#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3 -#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3 -#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2 -#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1 -#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2 -#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2 -#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2 -#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3 -#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2 -#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1 -#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2 -#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2 -#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2 -#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3 -#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3 -#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2 -#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2 -#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2 -#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3 -#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2 -#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3 -#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2 -#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2 -#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2 -#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3 -#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3 -#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2 -#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3 -#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2 -#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2 -#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2 -#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3 -#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2 -#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3 -#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2 -#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0 -#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2 -#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2 -#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3 -#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3 -#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2 -#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3 -#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2 -#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2 -#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3 -#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2 -#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3 -#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2 -#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3 -#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3 -#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2 -#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3 -#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2 -#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2 -#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0 -#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3 -#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2 -#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2 -#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2 -#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2 -#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3 -#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3 -#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3 -#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2 -#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2 -#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2 -#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2 -#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3 -#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0 -#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2 -#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2 -#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0 -#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2 -#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3 -#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4 -#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2 -#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0 -#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2 -#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4 -#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2 -#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2 -#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3 -#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2 -#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3 -#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2 -#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2 -#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2 -#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2 -#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0 -#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2 -#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3 -#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2 -#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2 -#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2 -#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0 -#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2 -#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2 -#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2 -#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0 -#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0 -#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2 -#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2 -#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0 -#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0 -#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0 -#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0 -#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0 -#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0 -#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0 - -#endif /* __DTS_IMX8ULP_PINFUNC_H */ diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h deleted file mode 100644 index 4298a145f8a..00000000000 --- a/arch/arm/dts/imx93-pinfunc.h +++ /dev/null @@ -1,623 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright 2022 NXP - */ - -#ifndef __DTS_IMX93_PINFUNC_H -#define __DTS_IMX93_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 -#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 -#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 -#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 -#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 -#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 -#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 -#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 -#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 -#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 -#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 -#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 -#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 -#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 -#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 -#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 -#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 -#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 -#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 -#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 -#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 -#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 -#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 -#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 -#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 -#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 -#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 -#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 -#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 -#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 -#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 -#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 -#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 -#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 -#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 -#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 -#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 -#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 -#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 -#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 -#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 -#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 -#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 -#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 -#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 -#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 -#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 -#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 -#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 -#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 -#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 -#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 -#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 -#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 -#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 -#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 -#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 -#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 -#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 -#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 -#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 -#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 -#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 -#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 -#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 -#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 -#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 -#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 -#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 -#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 -#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 -#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 -#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 -#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 -#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 -#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 -#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 -#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 -#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 -#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 -#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 -#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 -#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 -#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 -#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 -#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 -#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 -#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 -#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 -#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 -#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 -#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 -#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 -#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 -#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 -#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 -#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 -#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 -#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 -#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 -#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 -#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 -#define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 -#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 -#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 -#define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 -#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 -#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 -#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 -#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 -#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 -#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 -#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 -#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 -#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 -#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 -#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 -#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 -#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 -#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 -#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 -#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 -#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 -#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 -#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 -#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 -#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 -#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 -#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 -#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 -#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 -#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 -#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 -#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 -#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 -#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 -#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 -#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 -#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 -#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 -#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 -#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 -#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 -#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 -#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 -#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 -#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 -#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 -#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 -#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 -#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 -#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 -#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 -#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 -#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 -#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 -#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 -#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 -#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 -#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 -#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 -#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 -#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 -#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 -#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 -#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 -#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 -#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 -#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 -#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 -#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 -#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 -#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 -#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 -#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 -#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 -#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 -#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 -#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 -#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 -#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 -#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 -#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 -#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 -#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 -#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 -#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 -#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 -#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 -#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 -#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 -#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 -#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 -#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 -#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 -#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 -#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 -#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 -#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 -#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 -#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 -#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 -#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 -#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 -#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 -#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 -#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 -#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 -#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 -#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 -#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 -#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 -#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 -#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 -#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 -#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 -#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 -#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 -#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 -#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 -#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 -#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 -#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 -#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 -#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 -#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 -#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 -#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 -#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 -#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 -#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 -#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 -#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 -#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 -#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 -#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 -#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 -#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 -#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 -#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 -#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 -#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 -#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 -#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 -#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 -#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 -#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 -#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 -#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 -#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 -#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 -#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 -#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 -#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 -#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 -#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 -#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 -#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 -#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 -#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 -#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 -#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 -#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 -#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 -#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 -#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 -#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 -#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 -#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 -#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 -#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 -#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 -#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 -#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 -#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 -#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 -#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 -#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 -#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 -#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 -#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 -#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 -#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 -#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 -#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 -#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 -#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 -#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 -#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 -#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 -#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 -#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 -#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 -#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 -#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 -#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 -#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 -#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 -#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 -#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 -#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 -#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 -#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 -#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 -#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 -#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 -#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 -#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 -#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 -#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 -#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 -#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 -#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 -#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 -#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 -#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 -#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 -#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 -#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 -#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 -#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 -#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 -#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 - -#endif /* __DTS_IMX93_PINFUNC_H */ diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi index 13511ebb18e..336aeedb2ce 100644 --- a/arch/arm/dts/imxrt1020.dtsi +++ b/arch/arm/dts/imxrt1020.dtsi @@ -64,7 +64,6 @@ iomuxc: iomuxc@401f8000 { compatible = "fsl,imxrt-iomuxc"; reg = <0x401f8000 0x4000>; - fsl,mux_mask = <0x7>; }; anatop: anatop@400d8000 { diff --git a/arch/arm/dts/imxrt1170-pinfunc.h b/arch/arm/dts/imxrt1170-pinfunc.h deleted file mode 100644 index fba5483a084..00000000000 --- a/arch/arm/dts/imxrt1170-pinfunc.h +++ /dev/null @@ -1,1561 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2021 - * Author(s): Jesse Taube - */ - -#ifndef _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H -#define _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H - -#define IMX_PAD_SION 0x40000000 - -/* - * The pin function ID is a tuple of - * - */ - -#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 -#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 -#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x004 0x044 0x0B4 0x1 0x0 -#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x004 0x044 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x004 0x044 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x004 0x044 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x004 0x044 0x0AC 0x6 0x0 -#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x004 0x044 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x008 0x048 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x008 0x048 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x008 0x048 0x098 0x1 0x0 -#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x008 0x048 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x008 0x048 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x008 0x048 0x0 0x5 0x0 - -#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x00C 0x04C 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x00C 0x04C 0x094 0x1 0x0 -#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x00C 0x04C 0x0DC 0x2 0x0 -#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x00C 0x04C 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x00C 0x04C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x00C 0x04C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x010 0x050 0x088 0x0 0x0 -#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x010 0x050 0x0A0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x010 0x050 0x0D8 0x2 0x0 -#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x010 0x050 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x010 0x050 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x010 0x050 0x0A8 0x6 0x0 -#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x010 0x050 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x014 0x054 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x014 0x054 0x084 0x0 0x0 -#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x014 0x054 0x09C 0x1 0x0 -#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x014 0x054 0x0C8 0x2 0x1 -#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x014 0x054 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x014 0x054 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x014 0x054 0x0A4 0x6 0x0 -#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x014 0x054 0x0C4 0x7 0x0 - -#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x018 0x058 0x090 0x0 0x0 -#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x018 0x058 0x0D0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x018 0x058 0x0B0 0x3 0x1 -#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x018 0x058 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x018 0x058 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x018 0x058 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x018 0x058 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x018 0x058 0x0 0x8 0x0 -#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x018 0x058 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x01C 0x05C 0x08C 0x0 0x0 -#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x01C 0x05C 0x0CC 0x2 0x0 -#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x01C 0x05C 0x0AC 0x3 0x1 -#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x01C 0x05C 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x01C 0x05C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x01C 0x05C 0x080 0x6 0x1 -#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x01C 0x05C 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x01C 0x05C 0x0 0x8 0x0 -#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x01C 0x05C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x020 0x060 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x020 0x060 0x0A8 0x0 0x1 -#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x020 0x060 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x020 0x060 0x0D4 0x2 0x0 -#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x020 0x060 0x0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x020 0x060 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x020 0x060 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x020 0x060 0x088 0x6 0x1 -#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x020 0x060 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x020 0x060 0x0 0x8 0x0 - -#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x024 0x064 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x024 0x064 0x0A4 0x0 0x1 -#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x024 0x064 0x080 0x1 0x2 -#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x024 0x064 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x024 0x064 0x0B4 0x3 0x1 -#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x024 0x064 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x024 0x064 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x024 0x064 0x084 0x6 0x1 -#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x024 0x064 0x0 0x7 0x0 - -#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x028 0x068 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x028 0x068 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x028 0x068 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x028 0x068 0x090 0x2 0x1 -#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x028 0x068 0x0B8 0x3 0x0 -#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x028 0x068 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x028 0x068 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x028 0x068 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x028 0x068 0x0DC 0x7 0x1 -#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x028 0x068 0x0B0 0x8 0x2 - -#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x02C 0x06C 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x02C 0x06C 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x02C 0x06C 0x08C 0x2 0x1 -#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x02C 0x06C 0x0BC 0x3 0x0 -#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x02C 0x06C 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x02C 0x06C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x02C 0x06C 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x02C 0x06C 0x0 0x7 0x0 -#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x02C 0x06C 0x0AC 0x8 0x2 -#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x02C 0x06C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x030 0x070 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x030 0x070 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x030 0x070 0x0 0x1 0x0 -#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x030 0x070 0x0C0 0x3 0x0 -#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x030 0x070 0x0 0x4 0x0 -#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x030 0x070 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x030 0x070 0x0 0x6 0x0 -#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x030 0x070 0x0D8 0x7 0x1 -#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x030 0x070 0x098 0x8 0x1 - -#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x034 0x074 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x034 0x074 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x034 0x074 0x0B8 0x1 0x1 -#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x034 0x074 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x034 0x074 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x034 0x074 0x0D0 0x7 0x1 -#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x034 0x074 0x094 0x8 0x1 - -#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x038 0x078 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x038 0x078 0x0BC 0x1 0x1 -#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x038 0x078 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x038 0x078 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x038 0x078 0x0CC 0x7 0x1 -#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x038 0x078 0x0A0 0x8 0x1 -#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x038 0x078 0x0 0xA 0x0 - -#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x03C 0x07C 0x0 0xA 0x0 -#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x03C 0x07C 0x0 0x0 0x0 -#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x03C 0x07C 0x0C0 0x1 0x1 -#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x03C 0x07C 0x0 0x2 0x0 -#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x03C 0x07C 0x0 0x5 0x0 -#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x03C 0x07C 0x0D4 0x7 0x1 -#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x03C 0x07C 0x09C 0x8 0x1 - -#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000 0x40C94040 0x0 0x5 0x0 -#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000 0x40C94040 0x0C4 0x7 0x1 - -#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004 0x40C94044 0x0 0x0 0x0 -#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004 0x40C94044 0x0 0x5 0x0 - -#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008 0x40C94048 0x0 0x0 0x0 -#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008 0x40C94048 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400C 0x40C9404C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400C 0x40C9404C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010 0x40C94050 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010 0x40C94050 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014 0x40C94054 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014 0x40C94054 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018 0x40C94058 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018 0x40C94058 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401C 0x40C9405C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401C 0x40C9405C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020 0x40C94060 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020 0x40C94060 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024 0x40C94064 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024 0x40C94064 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028 0x40C94068 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028 0x40C94068 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402C 0x40C9406C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402C 0x40C9406C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030 0x40C94070 0x0 0x0 0x0 -#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030 0x40C94070 0x0 0x5 0x0 - -#define IOMUXC_TEST_MODE_DIG 0x0 0x40C94034 0x0 0x0 0x0 - -#define IOMUXC_POR_B_DIG 0x0 0x40C94038 0x0 0x0 0x0 - -#define IOMUXC_ONOFF_DIG 0x0 0x40C9403C 0x0 0x0 0x0 - -#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x010 0x254 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x010 0x254 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x010 0x254 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x010 0x254 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x010 0x254 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x014 0x258 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x014 0x258 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x014 0x258 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x014 0x258 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x014 0x258 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x018 0x25C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x018 0x25C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x018 0x25C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x018 0x25C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x018 0x25C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x01C 0x260 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x01C 0x260 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x01C 0x260 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x01C 0x260 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x01C 0x260 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x020 0x264 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x020 0x264 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x020 0x264 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x020 0x264 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x020 0x264 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x024 0x268 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x024 0x268 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x024 0x268 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x024 0x268 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x024 0x268 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x028 0x26C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x028 0x26C 0x518 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x028 0x26C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x028 0x26C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x028 0x26C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x02C 0x270 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x02C 0x270 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x02C 0x270 0x524 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x02C 0x270 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x02C 0x270 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x030 0x274 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x030 0x274 0x51C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x030 0x274 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x030 0x274 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x030 0x274 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x034 0x278 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x034 0x278 0x528 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x034 0x278 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x034 0x278 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x034 0x278 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x034 0x278 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x038 0x27C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x038 0x27C 0x520 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x038 0x27C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x038 0x27C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x038 0x27C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x038 0x27C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x03C 0x280 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x03C 0x280 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x03C 0x280 0x52C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x03C 0x280 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x03C 0x280 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x03C 0x280 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x040 0x284 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x040 0x284 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x040 0x284 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x040 0x284 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x040 0x284 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x040 0x284 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x044 0x288 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x044 0x288 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x044 0x288 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x044 0x288 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x044 0x288 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x044 0x288 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x048 0x28C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x048 0x28C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x048 0x28C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x048 0x28C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x048 0x28C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x048 0x28C 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x04C 0x290 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x04C 0x290 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x04C 0x290 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x04C 0x290 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x04C 0x290 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x050 0x294 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x050 0x294 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x050 0x294 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x050 0x294 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x050 0x294 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x054 0x298 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x054 0x298 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x054 0x298 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x054 0x298 0x63C 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x054 0x298 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x054 0x298 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x058 0x29C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x058 0x29C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x058 0x29C 0x648 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x058 0x29C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x058 0x29C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x058 0x29C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x05C 0x2A0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x05C 0x2A0 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x05C 0x2A0 0x654 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x05C 0x2A0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x05C 0x2A0 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x05C 0x2A0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x060 0x2A4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x060 0x2A4 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x060 0x2A4 0x660 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x060 0x2A4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x060 0x2A4 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x060 0x2A4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x064 0x2A8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x064 0x2A8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x064 0x2A8 0x53C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x064 0x2A8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x064 0x2A8 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x068 0x2AC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x068 0x2AC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x068 0x2AC 0x54C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x068 0x2AC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x068 0x2AC 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x06C 0x2B0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x06C 0x2B0 0x500 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x06C 0x2B0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x06C 0x2B0 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x06C 0x2B0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x070 0x2B4 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x070 0x2B4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x070 0x2B4 0x50C 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x070 0x2B4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x070 0x2B4 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x074 0x2B8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x074 0x2B8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x074 0x2B8 0x504 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x074 0x2B8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x074 0x2B8 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x078 0x2BC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x078 0x2BC 0x510 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x078 0x2BC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x078 0x2BC 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x078 0x2BC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x07C 0x2C0 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x07C 0x2C0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x07C 0x2C0 0x508 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x07C 0x2C0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x07C 0x2C0 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x080 0x2C4 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x080 0x2C4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x080 0x2C4 0x514 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x080 0x2C4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x080 0x2C4 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x084 0x2C8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x084 0x2C8 0x530 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x084 0x2C8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x084 0x2C8 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x084 0x2C8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x088 0x2CC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x088 0x2CC 0x540 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x088 0x2CC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x088 0x2CC 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x088 0x2CC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x08C 0x2D0 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x08C 0x2D0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x08C 0x2D0 0x534 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x08C 0x2D0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x08C 0x2D0 0x0 0x8 0x0 - -#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x090 0x2D4 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x090 0x2D4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x090 0x2D4 0x544 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x090 0x2D4 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x094 0x2D8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x094 0x2D8 0x538 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x094 0x2D8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x094 0x2D8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x098 0x2DC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x098 0x2DC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x098 0x2DC 0x548 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x098 0x2DC 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x09C 0x2E0 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x09C 0x2E0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x09C 0x2E0 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x09C 0x2E0 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x0A0 0x2E4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x0A0 0x2E4 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x0A0 0x2E4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x0A0 0x2E4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x0A4 0x2E8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x0A4 0x2E8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x0A4 0x2E8 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x0A4 0x2E8 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x0A8 0x2EC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x0A8 0x2EC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x0A8 0x2EC 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x0A8 0x2EC 0x640 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x0A8 0x2EC 0x0 0x5 0x0 - -#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x0AC 0x2F0 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x0AC 0x2F0 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x0AC 0x2F0 0x64C 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x0AC 0x2F0 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x0AC 0x2F0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x0B0 0x2F4 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x0B0 0x2F4 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x0B0 0x2F4 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x0B0 0x2F4 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x0B0 0x2F4 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x0B0 0x2F4 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x0B0 0x2F4 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x0B0 0x2F4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x0B4 0x2F8 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x0B4 0x2F8 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x0B4 0x2F8 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x0B4 0x2F8 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x0B4 0x2F8 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x0B4 0x2F8 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x0B4 0x2F8 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x0B4 0x2F8 0x4C8 0x7 0x0 -#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x0B4 0x2F8 0x0 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x0B8 0x2FC 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x0B8 0x2FC 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x0B8 0x2FC 0x658 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x0B8 0x2FC 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x0B8 0x2FC 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x0B8 0x2FC 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x0B8 0x2FC 0x6D8 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x0B8 0x2FC 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x0B8 0x2FC 0x5D0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x0B8 0x2FC 0x5B4 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x0B8 0x2FC 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x0B8 0x2FC 0x530 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x0BC 0x300 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x0BC 0x300 0x6D0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x0BC 0x300 0x664 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x0BC 0x300 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x0BC 0x300 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x0BC 0x300 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x0BC 0x300 0x6DC 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x0BC 0x300 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x0BC 0x300 0x5CC 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x0BC 0x300 0x5B8 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x0BC 0x300 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x0BC 0x300 0x540 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x0C0 0x304 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x0C0 0x304 0x6D4 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x0C0 0x304 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x0C0 0x304 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x0C0 0x304 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x0C0 0x304 0x6E0 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x0C0 0x304 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x0C0 0x304 0x5D8 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x0C0 0x304 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x0C0 0x304 0x534 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x0C4 0x308 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x0C4 0x308 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x0C4 0x308 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x0C4 0x308 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x0C4 0x308 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x0C4 0x308 0x6E4 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x0C4 0x308 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x0C4 0x308 0x5D4 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x0C4 0x308 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x0C4 0x308 0x544 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x0C8 0x30C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x0C8 0x30C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x0C8 0x30C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x0C8 0x30C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x0C8 0x30C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x0C8 0x30C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x0C8 0x30C 0x6E8 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x0C8 0x30C 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x0C8 0x30C 0x600 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x0C8 0x30C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x0C8 0x30C 0x538 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x0CC 0x310 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x0CC 0x310 0x598 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x0CC 0x310 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x0CC 0x310 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x0CC 0x310 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x0CC 0x310 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x0CC 0x310 0x6EC 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x0CC 0x310 0x4CC 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x0CC 0x310 0x5F0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x0CC 0x310 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x0CC 0x310 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x0CC 0x310 0x548 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x0D0 0x314 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x0D0 0x314 0x590 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x0D0 0x314 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x0D0 0x314 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x0D0 0x314 0x53C 0xB 0x1 -#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x0D0 0x314 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x0D0 0x314 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x0D0 0x314 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x0D0 0x314 0x6F0 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x0D0 0x314 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x0D0 0x314 0x608 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x0D0 0x314 0x0 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x0D4 0x318 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x0D4 0x318 0x594 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x0D4 0x318 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x0D4 0x318 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x0D4 0x318 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x0D4 0x318 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x0D4 0x318 0x6F4 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x0D4 0x318 0x4DC 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x0D4 0x318 0x604 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x0D4 0x318 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x0D4 0x318 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x0D4 0x318 0x54C 0xB 0x1 - -#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x0D8 0x31C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x0D8 0x31C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x0D8 0x31C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x0D8 0x31C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x0D8 0x31C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x0D8 0x31C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x0D8 0x31C 0x6F8 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x0D8 0x31C 0x4D8 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x0D8 0x31C 0x5F4 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x0D8 0x31C 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x0D8 0x31C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x0DC 0x320 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x0DC 0x320 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x0DC 0x320 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x0DC 0x320 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x0DC 0x320 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x0DC 0x320 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x0DC 0x320 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x0DC 0x320 0x6FC 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x0DC 0x320 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x0DC 0x320 0x5F8 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x0DC 0x320 0x63C 0x9 0x1 - -#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x0E0 0x324 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x0E0 0x324 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x0E0 0x324 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x0E0 0x324 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x0E0 0x324 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x0E0 0x324 0x58C 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x0E0 0x324 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x0E0 0x324 0x700 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x0E0 0x324 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x0E0 0x324 0x5FC 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x0E0 0x324 0x640 0x9 0x1 - -#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x0E4 0x328 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x0E4 0x328 0x6B4 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x0E4 0x328 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x0E4 0x328 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x0E4 0x328 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x0E4 0x328 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x0E4 0x328 0x704 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x0E4 0x328 0x69C 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x0E4 0x328 0x644 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x0E4 0x328 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x0E8 0x32C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x0E8 0x32C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x0E8 0x32C 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x0E8 0x32C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x0E8 0x32C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x0E8 0x32C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x0E8 0x32C 0x708 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x0E8 0x32C 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x0E8 0x32C 0x0 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x0E8 0x32C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x0EC 0x330 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x0EC 0x330 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x0EC 0x330 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x0EC 0x330 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x0EC 0x330 0x57C 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x0EC 0x330 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x0EC 0x330 0x70C 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x0EC 0x330 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x0EC 0x330 0x648 0x9 0x1 - -#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x0F0 0x334 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x0F0 0x334 0x4E8 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x0F0 0x334 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x0F0 0x334 0x580 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x0F0 0x334 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x0F0 0x334 0x710 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x0F0 0x334 0x0 0x7 0x0 -#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x0F0 0x334 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x0F0 0x334 0x64C 0x9 0x1 -#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x0F0 0x334 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x0F4 0x338 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x0F4 0x338 0x4D0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x0F4 0x338 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x0F4 0x338 0x584 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x0F4 0x338 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x0F4 0x338 0x714 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x0F4 0x338 0x6A0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x0F4 0x338 0x650 0x9 0x0 -#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x0F4 0x338 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x0F8 0x33C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x0F8 0x33C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x0F8 0x33C 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x0F8 0x33C 0x4D4 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x0F8 0x33C 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x0F8 0x33C 0x588 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x0F8 0x33C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x0F8 0x33C 0x6A4 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x0F8 0x33C 0x0 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x0FC 0x340 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x0FC 0x340 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x0FC 0x340 0x4E0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x0FC 0x340 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x0FC 0x340 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x0FC 0x340 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x0FC 0x340 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x0FC 0x340 0x654 0x9 0x1 -#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x0FC 0x340 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x100 0x344 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x100 0x344 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x100 0x344 0x4E4 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x100 0x344 0x0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x100 0x344 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x100 0x344 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x100 0x344 0x550 0x6 0x0 -#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x100 0x344 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x100 0x344 0x658 0x9 0x1 -#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x100 0x344 0x0 0xA 0x0 - -#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x104 0x348 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x104 0x348 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x104 0x348 0x0 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x104 0x348 0x0 0x2 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x104 0x348 0x4C4 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x104 0x348 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x104 0x348 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x104 0x348 0x0 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x104 0x348 0x65C 0x9 0x0 - -#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x108 0x34C 0x0 0xA 0x0 -#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x108 0x34C 0x0 0x0 0x0 -#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x108 0x34C 0x4AC 0x1 0x0 -#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x108 0x34C 0x4C8 0x2 0x1 -#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x108 0x34C 0x4A0 0x3 0x0 -#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x108 0x34C 0x0 0x4 0x0 -#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x108 0x34C 0x0 0x5 0x0 -#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x108 0x34C 0x4EC 0x8 0x0 -#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x108 0x34C 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x10C 0x350 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x10C 0x350 0x69C 0x0 0x1 -#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x10C 0x350 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x10C 0x350 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x10C 0x350 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x10C 0x350 0x500 0x4 0x1 -#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x10C 0x350 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x10C 0x350 0x630 0x6 0x0 -#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x10C 0x350 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x10C 0x350 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x110 0x354 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x110 0x354 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x110 0x354 0x49C 0x1 0x0 -#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x110 0x354 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x110 0x354 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x110 0x354 0x50C 0x4 0x1 -#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x110 0x354 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x110 0x354 0x62C 0x6 0x0 -#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x110 0x354 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x110 0x354 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x114 0x358 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x114 0x358 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x114 0x358 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x114 0x358 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x114 0x358 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x114 0x358 0x504 0x4 0x1 -#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x114 0x358 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x114 0x358 0x638 0x6 0x0 -#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x114 0x358 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x114 0x358 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x118 0x35C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x118 0x35C 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x118 0x35C 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x118 0x35C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x118 0x35C 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x118 0x35C 0x510 0x4 0x1 -#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x118 0x35C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x118 0x35C 0x634 0x6 0x0 -#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x118 0x35C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x118 0x35C 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x11C 0x360 0x6A0 0x0 0x1 -#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x11C 0x360 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x11C 0x360 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x11C 0x360 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x11C 0x360 0x508 0x4 0x1 -#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x11C 0x360 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_04_WDOG1_B 0x11C 0x360 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x11C 0x360 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x11C 0x360 0x660 0x9 0x1 -#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x11C 0x360 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x120 0x364 0x6A4 0x0 0x1 -#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x120 0x364 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x120 0x364 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x120 0x364 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x120 0x364 0x514 0x4 0x1 -#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x120 0x364 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_05_WDOG2_B 0x120 0x364 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x120 0x364 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x120 0x364 0x664 0x9 0x1 -#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x120 0x364 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x124 0x368 0x6B8 0x0 0x0 -#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x124 0x368 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x124 0x368 0x6A8 0x2 0x0 -#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x124 0x368 0x590 0x3 0x1 -#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x124 0x368 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x124 0x368 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x124 0x368 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x124 0x368 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x124 0x368 0x668 0x9 0x0 -#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x124 0x368 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x124 0x368 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x128 0x36C 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x128 0x36C 0x498 0x1 0x0 -#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x128 0x36C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x128 0x36C 0x594 0x3 0x1 -#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x128 0x36C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x128 0x36C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x128 0x36C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x128 0x36C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x128 0x36C 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x128 0x36C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x128 0x36C 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x12C 0x370 0x6C4 0x0 0x0 -#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x12C 0x370 0x5AC 0x1 0x0 -#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x12C 0x370 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x12C 0x370 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x12C 0x370 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x12C 0x370 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x12C 0x370 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x12C 0x370 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x12C 0x370 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x12C 0x370 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x130 0x374 0x6C0 0x0 0x0 -#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x130 0x374 0x5B0 0x1 0x0 -#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x130 0x374 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x130 0x374 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x130 0x374 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x130 0x374 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x130 0x374 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x130 0x374 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x130 0x374 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x130 0x374 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x134 0x378 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x134 0x378 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x134 0x378 0x6AC 0x2 0x0 -#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x134 0x378 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x134 0x378 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x134 0x378 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x134 0x378 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x134 0x378 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x134 0x378 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x134 0x378 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x138 0x37C 0x6BC 0x0 0x0 -#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x138 0x37C 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x138 0x37C 0x6B0 0x2 0x0 -#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x138 0x37C 0x598 0x3 0x1 -#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x138 0x37C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x138 0x37C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x138 0x37C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x138 0x37C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x138 0x37C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x138 0x37C 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x13C 0x380 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x13C 0x380 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x13C 0x380 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x13C 0x380 0x570 0x3 0x0 -#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x13C 0x380 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x13C 0x380 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x13C 0x380 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x13C 0x380 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x13C 0x380 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x13C 0x380 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x13C 0x380 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x140 0x384 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x140 0x384 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x140 0x384 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x140 0x384 0x56C 0x3 0x0 -#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x140 0x384 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x140 0x384 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x140 0x384 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x140 0x384 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x140 0x384 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x140 0x384 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x140 0x384 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x144 0x388 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x144 0x388 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x144 0x388 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x144 0x388 0x568 0x3 0x0 -#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x144 0x388 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x144 0x388 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x144 0x388 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x144 0x388 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x144 0x388 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x144 0x388 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x144 0x388 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x148 0x38C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x148 0x38C 0x0 0xB 0x0 -#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x148 0x38C 0x6B4 0x0 0x1 -#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x148 0x38C 0x628 0x1 0x0 -#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x148 0x38C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x148 0x38C 0x564 0x3 0x0 -#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x148 0x38C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x148 0x38C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x148 0x38C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x148 0x38C 0x0 0x8 0x0 - -#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x14C 0x390 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x14C 0x390 0x624 0x1 0x0 -#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x14C 0x390 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x14C 0x390 0x578 0x3 0x0 -#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x14C 0x390 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x14C 0x390 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x14C 0x390 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x14C 0x390 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x14C 0x390 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x14C 0x390 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x14C 0x390 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x150 0x394 0x66C 0x0 0x0 -#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x150 0x394 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x150 0x394 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x150 0x394 0x550 0x3 0x1 -#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x150 0x394 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x150 0x394 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x150 0x394 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x150 0x394 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x150 0x394 0x4C8 0x9 0x2 -#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x150 0x394 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x150 0x394 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x154 0x398 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x154 0x398 0x0 0xB 0x0 -#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x154 0x398 0x678 0x0 0x0 -#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x154 0x398 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x154 0x398 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x154 0x398 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x154 0x398 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x154 0x398 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_18_ENET_CRS 0x154 0x398 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x154 0x398 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x154 0x398 0x5B4 0x9 0x1 - -#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x158 0x39C 0x670 0x0 0x0 -#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x158 0x39C 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x158 0x39C 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x158 0x39C 0x574 0x3 0x0 -#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x158 0x39C 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x158 0x39C 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_19_ENET_COL 0x158 0x39C 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x158 0x39C 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x158 0x39C 0x5B8 0x9 0x1 -#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x158 0x39C 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x158 0x39C 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x15C 0x3A0 0x674 0x0 0x0 -#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x15C 0x3A0 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x15C 0x3A0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x15C 0x3A0 0x554 0x3 0x0 -#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x15C 0x3A0 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x15C 0x3A0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x15C 0x3A0 0x5A8 0x6 0x0 -#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x15C 0x3A0 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x15C 0x3A0 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x15C 0x3A0 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x15C 0x3A0 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x160 0x3A4 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x160 0x3A4 0x5E0 0x2 0x0 -#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x160 0x3A4 0x558 0x3 0x0 -#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x160 0x3A4 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x160 0x3A4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_21_KPP_COL07 0x160 0x3A4 0x5A0 0x6 0x0 -#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x160 0x3A4 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x160 0x3A4 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x160 0x3A4 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x160 0x3A4 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x164 0x3A8 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x164 0x3A8 0x67C 0x0 0x0 -#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x164 0x3A8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x164 0x3A8 0x55C 0x3 0x0 -#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x164 0x3A8 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x164 0x3A8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x164 0x3A8 0x5A4 0x6 0x0 -#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x164 0x3A8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x164 0x3A8 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x168 0x3AC 0x680 0x0 0x0 -#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x168 0x3AC 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x168 0x3AC 0x560 0x3 0x0 -#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x168 0x3AC 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x168 0x3AC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_23_KPP_COL06 0x168 0x3AC 0x59C 0x6 0x0 -#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x168 0x3AC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x168 0x3AC 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x168 0x3AC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x16C 0x3B0 0x620 0x0 0x0 -#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x16C 0x3B0 0x5E4 0x1 0x0 -#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x16C 0x3B0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x16C 0x3B0 0x4B8 0x3 0x0 -#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x16C 0x3B0 0x518 0x4 0x1 -#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x16C 0x3B0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x16C 0x3B0 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x16C 0x3B0 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x16C 0x3B0 0x5C4 0x9 0x0 -#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x16C 0x3B0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x170 0x3B4 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x170 0x3B4 0x61C 0x0 0x0 -#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x170 0x3B4 0x5DC 0x1 0x0 -#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x170 0x3B4 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x170 0x3B4 0x4BC 0x3 0x0 -#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x170 0x3B4 0x524 0x4 0x1 -#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x170 0x3B4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_25_KPP_COL05 0x170 0x3B4 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x170 0x3B4 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x170 0x3B4 0x5C8 0x9 0x0 - -#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x174 0x3B8 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x174 0x3B8 0x5EC 0x1 0x0 -#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x174 0x3B8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x174 0x3B8 0x4B0 0x3 0x0 -#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x174 0x3B8 0x51C 0x4 0x1 -#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x174 0x3B8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x174 0x3B8 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x174 0x3B8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x174 0x3B8 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x174 0x3B8 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x174 0x3B8 0x6D0 0xB 0x1 - -#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x178 0x3BC 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x178 0x3BC 0x5E8 0x1 0x0 -#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x178 0x3BC 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x178 0x3BC 0x4B4 0x3 0x0 -#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x178 0x3BC 0x528 0x4 0x1 -#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x178 0x3BC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_27_KPP_COL04 0x178 0x3BC 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x178 0x3BC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x178 0x3BC 0x4EC 0x9 0x1 -#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x178 0x3BC 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x178 0x3BC 0x6D4 0xB 0x1 - -#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x17C 0x3C0 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x17C 0x3C0 0x0 0xB 0x0 -#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x17C 0x3C0 0x5D0 0x0 0x1 -#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x17C 0x3C0 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x17C 0x3C0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x17C 0x3C0 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x17C 0x3C0 0x520 0x4 0x1 -#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x17C 0x3C0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x17C 0x3C0 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x17C 0x3C0 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x17C 0x3C0 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x180 0x3C4 0x5CC 0x0 0x1 -#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x180 0x3C4 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x180 0x3C4 0x4A8 0x2 0x0 -#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x180 0x3C4 0x4C0 0x3 0x0 -#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x180 0x3C4 0x52C 0x4 0x1 -#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x180 0x3C4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_29_KPP_COL03 0x180 0x3C4 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x180 0x3C4 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x180 0x3C4 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x180 0x3C4 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x180 0x3C4 0x0 0xB 0x0 - -#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x184 0x3C8 0x5D8 0x0 0x1 -#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x184 0x3C8 0x6B8 0x1 0x1 -#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x184 0x3C8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x184 0x3C8 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x184 0x3C8 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x184 0x3C8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x184 0x3C8 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x184 0x3C8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x184 0x3C8 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x184 0x3C8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x188 0x3CC 0x5D4 0x0 0x1 -#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x188 0x3CC 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x188 0x3CC 0x49C 0x2 0x1 -#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x188 0x3CC 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x188 0x3CC 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x188 0x3CC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_31_KPP_COL02 0x188 0x3CC 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x188 0x3CC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x188 0x3CC 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x188 0x3CC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x18C 0x3D0 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x18C 0x3D0 0x5AC 0x0 0x1 -#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x18C 0x3D0 0x6C4 0x1 0x1 -#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x18C 0x3D0 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_32_ENET_MDC 0x18C 0x3D0 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x18C 0x3D0 0x6C8 0x4 0x0 -#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x18C 0x3D0 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x18C 0x3D0 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x18C 0x3D0 0x628 0x8 0x1 -#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x18C 0x3D0 0x0 0x9 0x0 - -#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x190 0x3D4 0x5B0 0x0 0x1 -#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x190 0x3D4 0x6C0 0x1 0x1 -#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x190 0x3D4 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x190 0x3D4 0x4AC 0x3 0x1 -#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x190 0x3D4 0x6CC 0x4 0x0 -#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x190 0x3D4 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_33_KPP_COL01 0x190 0x3D4 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x190 0x3D4 0x624 0x8 0x1 -#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x190 0x3D4 0x4C8 0x9 0x3 -#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x190 0x3D4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x194 0x3D8 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x194 0x3D8 0x0 0x1 0x0 -#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x194 0x3D8 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x194 0x3D8 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x194 0x3D8 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x194 0x3D8 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x194 0x3D8 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x194 0x3D8 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x194 0x3D8 0x0 0x9 0x0 -#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x194 0x3D8 0x0 0xA 0x0 - -#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x198 0x3DC 0x0 0xA 0x0 -#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x0 0x0 -#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x198 0x3DC 0x6BC 0x1 0x1 -#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x198 0x3DC 0x0 0x2 0x0 -#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x198 0x3DC 0x0 0x3 0x0 -#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x198 0x3DC 0x0 0x4 0x0 -#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x198 0x3DC 0x0 0x5 0x0 -#define IOMUXC_GPIO_AD_35_KPP_COL00 0x198 0x3DC 0x0 0x6 0x0 -#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x198 0x3DC 0x0 0x8 0x0 -#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x198 0x3DC 0x0 0x9 0x0 - -#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x19C 0x3E0 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x19C 0x3E0 0x6D8 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x19C 0x3E0 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x19C 0x3E0 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x19C 0x3E0 0x0 0x6 0x0 -#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x19C 0x3E0 0x5A8 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x19C 0x3E0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x1A0 0x3E4 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x1A0 0x3E4 0x6DC 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x1A0 0x3E4 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x1A0 0x3E4 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x1A0 0x3E4 0x58C 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x1A0 0x3E4 0x5A0 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x1A0 0x3E4 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x1A4 0x3E8 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x1A4 0x3E8 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x1A4 0x3E8 0x6E0 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x1A4 0x3E8 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x1A4 0x3E8 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x1A4 0x3E8 0x57C 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x1A4 0x3E8 0x5A4 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x1A4 0x3E8 0x0 0x9 0x0 - -#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x1A8 0x3EC 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x1A8 0x3EC 0x6E4 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x1A8 0x3EC 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x1A8 0x3EC 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x1A8 0x3EC 0x580 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x1A8 0x3EC 0x59C 0x8 0x1 -#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x1A8 0x3EC 0x0 0x9 0x0 -#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x1A8 0x3EC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x1AC 0x3F0 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x1AC 0x3F0 0x6E8 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x1AC 0x3F0 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x1AC 0x3F0 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x1AC 0x3F0 0x584 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x1AC 0x3F0 0x0 0x8 0x0 -#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x1AC 0x3F0 0x0 0x9 0x0 -#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x1AC 0x3F0 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x1B0 0x3F4 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x1B0 0x3F4 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x1B0 0x3F4 0x6EC 0x2 0x1 -#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x1B0 0x3F4 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x1B0 0x3F4 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x1B0 0x3F4 0x588 0x6 0x1 -#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x1B0 0x3F4 0x0 0x8 0x0 -#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x1B0 0x3F4 0x0 0x9 0x0 - -#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x1B4 0x3F8 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x1B4 0x3F8 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x1B4 0x3F8 0x570 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x1B4 0x3F8 0x4E0 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x1B4 0x3F8 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x1B4 0x3F8 0x610 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x1B4 0x3F8 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x1B8 0x3FC 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x1B8 0x3FC 0x56C 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x1B8 0x3FC 0x4CC 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x1B8 0x3FC 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x1B8 0x3FC 0x60C 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x1B8 0x3FC 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x1B8 0x3FC 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x1BC 0x400 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x1BC 0x400 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x1BC 0x400 0x568 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x1BC 0x400 0x4D0 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x1BC 0x400 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x1BC 0x400 0x618 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x1BC 0x400 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x1C0 0x404 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x1C0 0x404 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x1C0 0x404 0x564 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x1C0 0x404 0x4D4 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x1C0 0x404 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x1C0 0x404 0x614 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x1C0 0x404 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x1C4 0x408 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x1C4 0x408 0x578 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x1C4 0x408 0x4D8 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x1C4 0x408 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x1C4 0x408 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x1C4 0x408 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x1C4 0x408 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x1C8 0x40C 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x1C8 0x40C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x1C8 0x40C 0x550 0x1 0x2 -#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x1C8 0x40C 0x4DC 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x1C8 0x40C 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x1C8 0x40C 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x1C8 0x40C 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x1CC 0x410 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x1CC 0x410 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x1CC 0x410 0x0 0x1 0x0 -#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x1CC 0x410 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x1CC 0x410 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x1CC 0x410 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x1CC 0x410 0x0 0x5 0x0 - -#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x1D0 0x414 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x1D0 0x414 0x574 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x1D0 0x414 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x1D0 0x414 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x1D0 0x414 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x1D0 0x414 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x1D0 0x414 0x5E4 0x6 0x1 -#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x1D0 0x414 0x0 0x8 0x0 -#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x1D0 0x414 0x4A0 0x9 0x1 -#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x1D0 0x414 0x0 0xA 0x0 - -#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x1D4 0x418 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x1D4 0x418 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x1D4 0x418 0x554 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x1D4 0x418 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x1D4 0x418 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x1D4 0x418 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x1D4 0x418 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x1D4 0x418 0x5DC 0x6 0x1 - -#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x1D8 0x41C 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x1D8 0x41C 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x1D8 0x41C 0x558 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x1D8 0x41C 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x1D8 0x41C 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x1D8 0x41C 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x1D8 0x41C 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x1D8 0x41C 0x5EC 0x6 0x1 - -#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x1DC 0x420 0x0 0xA 0x0 -#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x1DC 0x420 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x1DC 0x420 0x55C 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x1DC 0x420 0x0 0x2 0x0 -#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x1DC 0x420 0x0 0x3 0x0 -#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x1DC 0x420 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x1DC 0x420 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x1DC 0x420 0x5E8 0x6 0x1 - -#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x1E0 0x424 0x0 0x0 0x0 -#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x1E0 0x424 0x560 0x1 0x1 -#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x1E0 0x424 0x4E8 0x2 0x1 -#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x1E0 0x424 0x4C4 0x3 0x1 -#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x1E0 0x424 0x0 0x4 0x0 -#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x1E0 0x424 0x0 0x5 0x0 -#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x1E0 0x424 0x5E0 0x6 0x1 -#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x1E0 0x424 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x1E4 0x428 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x1E4 0x428 0x4E0 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x1E4 0x428 0x63C 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x1E4 0x428 0x6F0 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x1E4 0x428 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x1E4 0x428 0x4F8 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x1E4 0x428 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x1E8 0x42C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x1E8 0x42C 0x4CC 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x1E8 0x42C 0x4E4 0x2 0x1 -#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x1E8 0x42C 0x640 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x1E8 0x42C 0x6F4 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x1E8 0x42C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x1E8 0x42C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x1E8 0x42C 0x4FC 0x9 0x0 -#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x1E8 0x42C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x1EC 0x430 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x1EC 0x430 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x1EC 0x430 0x4D0 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x1EC 0x430 0x5BC 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x1EC 0x430 0x644 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x1EC 0x430 0x6F8 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x1EC 0x430 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x1EC 0x430 0x4F0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x1EC 0x430 0x620 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x1F0 0x434 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x1F0 0x434 0x4D4 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x1F0 0x434 0x5C0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x1F0 0x434 0x648 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x1F0 0x434 0x6FC 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x1F0 0x434 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x1F0 0x434 0x4F4 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x1F0 0x434 0x61C 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x1F0 0x434 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x1F4 0x438 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x1F4 0x438 0x4D8 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x1F4 0x438 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x1F4 0x438 0x64C 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x1F4 0x438 0x700 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x1F4 0x438 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x1F4 0x438 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x1F4 0x438 0x600 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x1F4 0x438 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x1F8 0x43C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x1F8 0x43C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x1F8 0x43C 0x4DC 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x1F8 0x43C 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x1F8 0x43C 0x650 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x1F8 0x43C 0x704 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x1F8 0x43C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x1F8 0x43C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x1F8 0x43C 0x604 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x1FC 0x440 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x1FC 0x440 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x1FC 0x440 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x1FC 0x440 0x654 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x1FC 0x440 0x708 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x1FC 0x440 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x1FC 0x440 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x1FC 0x440 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x1FC 0x440 0x608 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x1FC 0x440 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x200 0x444 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x200 0x444 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x200 0x444 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x200 0x444 0x658 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x200 0x444 0x70C 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x200 0x444 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x200 0x444 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x200 0x444 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x200 0x444 0x5F0 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x200 0x444 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x204 0x448 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x204 0x448 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x204 0x448 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x204 0x448 0x6C8 0x2 0x1 -#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x204 0x448 0x65C 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x204 0x448 0x710 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x204 0x448 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x204 0x448 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x204 0x448 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x204 0x448 0x5F4 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x208 0x44C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x208 0x44C 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x208 0x44C 0x6CC 0x2 0x1 -#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x208 0x44C 0x660 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x208 0x44C 0x714 0x4 0x1 -#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x208 0x44C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x208 0x44C 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x208 0x44C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x208 0x44C 0x5F8 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x208 0x44C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x20C 0x450 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x20C 0x450 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x20C 0x450 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x20C 0x450 0x664 0x3 0x2 -#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x20C 0x450 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x20C 0x450 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x20C 0x450 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x20C 0x450 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x20C 0x450 0x5FC 0x9 0x1 -#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x20C 0x450 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x210 0x454 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x210 0x454 0x4E8 0x1 0x2 -#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x210 0x454 0x4C4 0x2 0x2 -#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x210 0x454 0x668 0x3 0x1 -#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x210 0x454 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x210 0x454 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x210 0x454 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x210 0x454 0x4A4 0x8 0x0 -#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x210 0x454 0x4A0 0x9 0x2 -#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x210 0x454 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x214 0x458 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x214 0x458 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x214 0x458 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x214 0x458 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x214 0x458 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x214 0x458 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x214 0x458 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x214 0x458 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x214 0x458 0x0 0x8 0x0 - -#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x218 0x45C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x218 0x45C 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x218 0x45C 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x218 0x45C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x218 0x45C 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x218 0x45C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x218 0x45C 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x218 0x45C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x218 0x45C 0x0 0x9 0x0 -#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x218 0x45C 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x21C 0x460 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x21C 0x460 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x21C 0x460 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x21C 0x460 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x21C 0x460 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x21C 0x460 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x21C 0x460 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x21C 0x460 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x21C 0x460 0x0 0x8 0x0 - -#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x220 0x464 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x220 0x464 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x220 0x464 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x220 0x464 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x220 0x464 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x220 0x464 0x66C 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x220 0x464 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x220 0x464 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x220 0x464 0x0 0x8 0x0 - -#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x224 0x468 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x224 0x468 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x224 0x468 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x224 0x468 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x224 0x468 0x678 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x224 0x468 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x224 0x468 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x224 0x468 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x224 0x468 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x228 0x46C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x228 0x46C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x228 0x46C 0x4C0 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x228 0x46C 0x4A8 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x228 0x46C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x228 0x46C 0x670 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x228 0x46C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x228 0x46C 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x228 0x46C 0x4A4 0x8 0x1 - -#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x22C 0x470 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x22C 0x470 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x22C 0x470 0x4B0 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x22C 0x470 0x630 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x22C 0x470 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x22C 0x470 0x674 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x22C 0x470 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x22C 0x470 0x4F0 0x8 0x1 - -#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x230 0x474 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x230 0x474 0x4B4 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x230 0x474 0x62C 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x230 0x474 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x230 0x474 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x230 0x474 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x230 0x474 0x4F4 0x8 0x1 -#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x230 0x474 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x234 0x478 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x234 0x478 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x234 0x478 0x4B8 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x234 0x478 0x638 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x234 0x478 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x234 0x478 0x67C 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x234 0x478 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x234 0x478 0x4F8 0x8 0x1 -#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x234 0x478 0x620 0x9 0x2 - -#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x238 0x47C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x238 0x47C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x238 0x47C 0x4BC 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x238 0x47C 0x634 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x238 0x47C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x238 0x47C 0x680 0x4 0x1 -#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x238 0x47C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x238 0x47C 0x4FC 0x8 0x1 -#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x238 0x47C 0x61C 0x9 0x2 - -#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x23C 0x480 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x23C 0x480 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x23C 0x480 0x6A8 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x23C 0x480 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x23C 0x480 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x23C 0x480 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x23C 0x480 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x23C 0x480 0x5BC 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x23C 0x480 0x4FC 0x8 0x2 -#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x23C 0x480 0x6B4 0x9 0x2 - -#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x240 0x484 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x240 0x484 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x240 0x484 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x240 0x484 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x240 0x484 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x240 0x484 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x240 0x484 0x5C0 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x240 0x484 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x240 0x484 0x0 0x9 0x0 -#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x240 0x484 0x0 0xA 0x0 - -#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x244 0x488 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x244 0x488 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x244 0x488 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x244 0x488 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x244 0x488 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x244 0x488 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x244 0x488 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x244 0x488 0x5C4 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x244 0x488 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x244 0x488 0x610 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x248 0x48C 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x248 0x48C 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x248 0x48C 0x0 0x1 0x0 -#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x248 0x48C 0x498 0x2 0x1 -#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x248 0x48C 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x248 0x48C 0x4A8 0x4 0x2 -#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x248 0x48C 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x248 0x48C 0x5C8 0x6 0x1 -#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x248 0x48C 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x248 0x48C 0x614 0x9 0x1 - -#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x24C 0x490 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x24C 0x490 0x0 0x6 0x0 -#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x24C 0x490 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x24C 0x490 0x618 0x9 0x1 -#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x24C 0x490 0x0 0xA 0x0 -#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x24C 0x490 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x24C 0x490 0x6AC 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x24C 0x490 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x24C 0x490 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x24C 0x490 0x4C4 0x4 0x3 - -#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x250 0x494 0x0 0x0 0x0 -#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x250 0x494 0x6B0 0x1 0x1 -#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x250 0x494 0x0 0x2 0x0 -#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x250 0x494 0x0 0x3 0x0 -#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x250 0x494 0x0 0x4 0x0 -#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x250 0x494 0x0 0x5 0x0 -#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x250 0x494 0x498 0x6 0x2 -#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x250 0x494 0x0 0x8 0x0 -#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x250 0x494 0x60C 0x9 0x1 -#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x250 0x494 0x0 0xA 0x0 - -#endif /* _DT_BINDINGS_PINCTRL_IMXRT1170_PINFUNC_H */ diff --git a/arch/arm/dts/imxrt1170.dtsi b/arch/arm/dts/imxrt1170.dtsi index 08665eaf06a..7566402353a 100644 --- a/arch/arm/dts/imxrt1170.dtsi +++ b/arch/arm/dts/imxrt1170.dtsi @@ -77,7 +77,6 @@ iomuxc: iomuxc@400e8000 { compatible = "fsl,imxrt-iomuxc"; reg = <0x400e8000 0x4000>; - fsl,mux_mask = <0x7>; }; anatop: anatop@40c84000 { diff --git a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi new file mode 100644 index 00000000000..9e4af4d9f72 --- /dev/null +++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IPQ5424 RDP466 board device tree source + * + * Copyright (c) 2025 The Linux Foundation. All rights reserved. + */ + +/ { + /* Will be removed when SMEM parsing is updated */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x20000000>; + }; + +}; + + &sdhc { + sdhci-caps-mask = <0x0 0x04000000>; + sdhci-caps = <0x0 0x04000000>; /* SDHCI_CAN_VDD_180 */ + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <192000000>; + bus-width = <4>; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + non-removable; + + /* + * This reset is needed to clear out the settings done by + * previous boot loader. Without this the SDHCI_RESET_ALL + * reset done sdhci_init() times out. + */ + resets = <&gcc GCC_SDCC_BCR>; + + status = "okay"; + }; + diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index 01b6a8e417c..2a4f0e45365 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -9,10 +9,6 @@ #include "k3-binman.dtsi" / { - chosen { - tick-timer = &main_timer0; - }; - /* Keep the LEDs on by default to indicate life */ leds { led-0 { @@ -37,10 +33,6 @@ }; }; -&main_timer0 { - clock-frequency = <25000000>; -}; - &sd_pins_default { /* Force to use SDCD card detect pin */ pinctrl-single,pins = < diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index c001e2c96e8..ee273563e83 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -13,7 +13,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - tick-timer = &main_timer0; }; aliases { @@ -96,10 +95,6 @@ bootph-all; }; -&main_timer0 { - clock-frequency = <25000000>; -}; - &main_uart0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index 9b536d679af..6deebdadf09 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -36,7 +36,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -45,7 +44,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -82,7 +80,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -91,7 +88,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -125,7 +121,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -405,11 +400,105 @@ }; &binman { + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x40000>; + sw-rev = ; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = ; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + ti-spl_unsigned { insert-template = <&ti_spl_unsigned_template>; fit { images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { ti-dm { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 9e0a6ed6784..f4b2cd8904e 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -46,6 +46,14 @@ }; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; + &dmsc { mboxes= <&secure_proxy_main 0>, <&secure_proxy_main 1>, @@ -103,7 +111,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts index 70154409b12..7132fae36fa 100644 --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts @@ -54,6 +54,14 @@ }; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; + &secure_proxy_sa3 { /* We require this for boot handshake */ status = "okay"; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index cc619f5920e..6822a5dac89 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -34,7 +34,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -43,7 +42,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -80,7 +78,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -89,7 +86,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -123,7 +119,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -263,7 +258,6 @@ }; dm: ti-dm { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; @@ -391,7 +385,6 @@ dm { ti-dm { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 2b333e70f5c..39e8ab8158e 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -69,6 +69,14 @@ ti,secure-host; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; + &secure_proxy_sa3 { /* We require this for boot handshake */ status = "okay"; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 5a8788b227b..bfbba28269c 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -34,7 +34,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -43,7 +42,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -80,7 +78,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -89,7 +86,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -123,7 +119,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi index b3d237c8697..8487ea14800 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi @@ -12,10 +12,6 @@ eeprom2 = &eeprom_display_adapter; }; - chosen { - tick-timer = &main_timer0; - }; - memory@80000000 { bootph-all; }; @@ -25,10 +21,6 @@ }; }; -&main_timer0 { - clock-frequency = <25000000>; -}; - &main_bcdma { reg = <0x00 0x485c0100 0x00 0x100>, <0x00 0x4c000000 0x00 0x20000>, diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index 1871926c207..fd340101532 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -41,7 +41,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -50,7 +49,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -87,7 +85,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -96,7 +93,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -130,7 +126,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -269,7 +264,6 @@ }; dm: ti-dm { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; @@ -456,7 +450,6 @@ dm { ti-dm { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index ed973541fff..877a513a241 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -38,7 +38,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -47,7 +46,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -84,7 +82,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -93,7 +90,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -127,7 +123,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -253,7 +248,6 @@ }; dm: ti-dm { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; @@ -379,7 +373,6 @@ dm { ti-dm { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi index f922f4b4781..73255a18e9b 100644 --- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi @@ -13,7 +13,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - tick-timer = &main_timer0; }; aliases { @@ -157,10 +156,6 @@ bootph-all; }; -&main_timer0 { - bootph-all; -}; - &main_uart0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts index 0060c7a6934..63b7864a469 100644 --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -88,6 +88,15 @@ ti,secure-host; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; + bootph-pre-ram; +}; + &main_bcdma { ti,sci = <&dm_tifs>; }; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 8216add3498..d65e5c4d4e1 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -38,7 +38,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -49,7 +48,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -87,7 +85,6 @@ ti_fs_enc_hs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_hs: combined-tifs-cfg.bin { @@ -98,7 +95,6 @@ sysfw_inner_cert_hs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_hs: combined-dm-cfg.bin { @@ -203,7 +199,6 @@ dm: ti-dm { filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-am62p-verdin-dev.dtsi b/arch/arm/dts/k3-am62p-verdin-dev.dtsi new file mode 100644 index 00000000000..4cf38226077 --- /dev/null +++ b/arch/arm/dts/k3-am62p-verdin-dev.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM on Development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + carrier_eth_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&carrier_eth_phy>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + #sound-dai-cells = <0>; + }; + + carrier_gpio_expander: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&main_uart1 { + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am62p-verdin-wifi.dtsi b/arch/arm/dts/k3-am62p-verdin-wifi.dtsi new file mode 100644 index 00000000000..04d3124b5e0 --- /dev/null +++ b/arch/arm/dts/k3-am62p-verdin-wifi.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + */ + +/* On-module Bluetooth */ +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci2>; + keep-power-in-suspend; + non-removable; + ti,fails-without-test-cd; + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am62p-verdin.dtsi b/arch/arm/dts/k3-am62p-verdin.dtsi new file mode 100644 index 00000000000..b78b2ac76f3 --- /dev/null +++ b/arch/arm/dts/k3-am62p-verdin.dtsi @@ -0,0 +1,1399 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + */ + +#include +#include +#include +#include +#include + +/ { + aliases { + can0 = &main_mcan0; + can1 = &mcu_mcan0; + eeprom0 = &som_eeprom; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + i2c0 = &wkup_i2c0; + i2c1 = &main_i2c0; + i2c2 = &main_i2c1; + i2c3 = &mcu_i2c0; + i2c4 = &main_i2c3; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &som_rtc_i2c; + rtc1 = &wkup_rtc0; + serial0 = &main_uart1; + serial1 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &mcu_uart0; + serial4 = &main_uart6; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb0_ep>; + }; + }; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + status = "disabled"; + + key-wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&main_gpio0 1 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + memory@80000000 { + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + + /* Verdin SD_1 Power Supply */ + reg_sd1_vmmc: regulator-sdhci1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpios = <&main_gpio0 47 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reg_sd1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd_vsel>; + /* PMIC_VSEL_SD */ + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-name = "LDO1-VSEL-SD (PMIC)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, + <3300000 0x1>; + vin-supply = <®_sd_3v3_1v8>; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en>; + /* Verdin USB_1_EN (SODIMM 155) */ + gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + + /* Module Power Supply */ + reg_vsodimm: regulator-vsodimm { + compatible = "regulator-fixed"; + regulator-name = "+V_SODIMM"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + /* Verdin PWM_3_DSI */ + pinctrl_epwm0_b: main-epwm0b-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ /* SODIMM 19 */ + >; + }; + + /* Verdin PWM_2 */ + pinctrl_epwm2_a: main-epwm2a-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0124, PIN_OUTPUT, 4) /* (J25) MMC2_SDCD.EHRPWM2_A */ /* SODIMM 16 */ + >; + }; + + /* Verdin PWM_1 */ + pinctrl_epwm2_b: main-epwm2b-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0128, PIN_OUTPUT, 4) /* (K25) MMC2_SDWP.EHRPWM2_B */ /* SODIMM 15 */ + >; + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_INPUT, 7) /* (P23) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ + >; + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: main-gpio0-1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0004, PIN_INPUT, 7) /* (N23) OSPI0_LBCLKO.GPIO0_1 */ /* SODIMM 252 */ + >; + }; + + /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_dqs_gpio: main-gpio0-2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0008, PIN_INPUT, 7) /* (P22) OSPI0_DQS.GPIO0_2 */ /* SODIMM 66 */ + >; + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x000c, PIN_INPUT, 7) /* (L25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ + >; + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0010, PIN_INPUT, 7) /* (N24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ + >; + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0014, PIN_INPUT, 7) /* (N25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ + >; + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0018, PIN_INPUT, 7) /* (M24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ + >; + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x002c, PIN_INPUT, 7) /* (M25) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0030, PIN_INPUT, 7) /* (L24) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ + >; + }; + + /* Verdin MSP_37 as GPIO */ + pinctrl_msp37_gpio: main-gpio0-13-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0034, PIN_INPUT, 7) /* (L22) OSPI0_CSn2.GPIO0_13 */ /* SODIMM 174 - WiFi_W_WKUP_HOST# */ + >; + }; + + /* Verdin PCIE_1_RESET# */ + pinctrl_pcie_1_reset: main-gpio0-14-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0038, PIN_INPUT, 7) /* (L23) OSPI0_CSn3.GPIO0_14 */ /* SODIMM 244 */ + >; + }; + + pinctrl_sd_vsel: main-gpio0-21-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0054, PIN_INPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ /* PMIC_SD_VSEL */ + >; + }; + + pinctrl_tpm_extint: main-gpio0-25-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0064, PIN_INPUT, 7) /* (AA25) GPMC0_AD10.GPIO0_25 */ /* TPM_EXTINT# */ + >; + }; + + pinctrl_wifi_wkup_bt: main-gpio0-29-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0074, PIN_INPUT, 7) /* (AB24) GPMC0_AD14.GPIO0_29 */ /* WiFi_WKUP_BT# */ + >; + }; + + pinctrl_wifi_wkup_wlan: main-gpio0-30-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0078, PIN_INPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ /* WiFi_WKUP_WLAN# */ + >; + }; + + /* Verdin USB_1_ID */ + pinctrl_usb0_id: main-gpio0-31-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 161 */ + >; + }; + + /* Verdin USB_1_OC# */ + pinctrl_usb1_oc: main-gpio0-32-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0084, PIN_INPUT, 7) /* (R25) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 157 */ + >; + }; + + /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_in_gpio: main-gpio0-33-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + >; + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x008c, PIN_INPUT, 7) /* (T25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + >; + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 7) /* (U24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ + >; + }; + + pinctrl_eth_int: main-gpio0-36-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0094, PIN_INPUT, 7) /* (T24) GPMC0_BE1n.GPIO0_36 */ /* ETH_INT# */ + >; + }; + + /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_sync_gpio: main-gpio0-37-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0098, PIN_INPUT, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + >; + }; + + /* Verdin DSI_1_INT# */ + pinctrl_dsi1_int: main-gpio0-38-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x009c, PIN_INPUT, 7) /* (AD24) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 17 */ + >; + }; + + /* Verdin DSI_1_BLK_EN# */ + pinctrl_dsi1_bkl_en: main-gpio0-39-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00a0, PIN_INPUT, 7) /* (P24) GPMC0_WPn.GPIO0_39 */ /* SODIMM 21 */ + >; + }; + + /* Verdin USB_2_OC# */ + pinctrl_usb2_oc: main-gpio0-41-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00a8, PIN_INPUT, 7) /* (T23) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 187 */ + >; + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: main-gpio0-42-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00ac, PIN_INPUT, 7) /* (U23) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 189 */ + >; + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-47-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c0, PIN_INPUT, 7) /* (AA23) VOUT0_DATA2.GPIO0_47 */ /* SODIMM 76 */ + >; + }; + + /* Verdin GPIO_5 */ + pinctrl_gpio_5: main-gpio0-49-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c8, PIN_INPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ /* SODIMM 216 */ + >; + }; + + /* Verdin GPIO_6 */ + pinctrl_gpio_6: main-gpio0-50-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00cc, PIN_INPUT, 7) /* (AD23) VOUT0_DATA5.GPIO0_50 */ /* SODIMM 218 */ + >; + }; + + /* Verdin GPIO_7 */ + pinctrl_gpio_7: main-gpio0-51-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d0, PIN_INPUT, 7) /* (AC23) VOUT0_DATA6.GPIO0_51 */ /* SODIMM 220 */ + >; + }; + + /* Verdin GPIO_8 */ + pinctrl_gpio_8: main-gpio0-52-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d4, PIN_INPUT, 7) /* (AE23) VOUT0_DATA7.GPIO0_52 */ /* SODIMM 222 */ + >; + }; + + /* Verdin MSP_36 as GPIO */ + pinctrl_msp36_gpio: main-gpio0-57-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00e8, PIN_INPUT, 7) /* (AD21) VOUT0_DATA12.GPIO0_57 */ /* SODIMM 172 - WiFi_BT_WKUP_HOST# */ + >; + }; + + pinctrl_wifi_sd_int: main-gpio0-59-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f0, PIN_INPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 */ /* WIFI_SD_INT */ + >; + }; + + pinctrl_wifi_spi_cs: main-gpio0-60-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f4, PIN_INPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 */ /* WIFI_SPI_CS# */ + >; + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: main-gpio1-16-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */ /* SODIMM 19 */ + >; + }; + + /* Verdin SD_1_CD# */ + pinctrl_sd1_cd: main-gpio1-48-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0240, PIN_INPUT, 7) /* (D23) MMC1_SDCD.GPIO1_48 */ /* SODIMM 84 */ + >; + }; + + /* Verdin MSP_29 as GPIO */ + pinctl_msp29_gpio: main-gpio1-49-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */ /* SODIMM 154 */ + >; + }; + + /* Verdin USB_1_EN */ + pinctrl_usb0_en: main-gpio1-50-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0254, PIN_INPUT, 7) /* (G22) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_main_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ /* SODIMM 14 */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ /* SODIMM 12 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_main_i2c1: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ /* SODIMM 55 */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_main_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ + >; + }; + + /* Verdin CAN_1 */ + pinctrl_main_mcan0: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ /* SODIMM 22 */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* Verdin MSP_3/MSP_8 as CAN */ + pinctrl_main_mcan1: main-mcan1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */ /* SODIMM 92 */ + AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */ /* SODIMM 104 */ + >; + }; + + /* Verdin SD_1 */ + pinctrl_sdhci1: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ /* SODIMM 74 */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ /* SODIMM 78 */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ /* SODIMM 80 */ + AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ /* SODIMM 82 */ + AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ /* SODIMM 70 */ + AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ /* SODIMM 72 */ + >; + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_sdhci2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */ + AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */ + AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT, 0) /* (L21) MMC2_DAT3 */ /* SODIMM 168, WiFi_SDIO_DATA3 */ + >; + }; + + /* Verdin QSPI_1 */ + pinctrl_ospi0: main-ospi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ /* SODIMM 52 */ + AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ /* SODIMM 54 */ + AM62PX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (L24) OSPI0_CSn1 */ /* SODIMM 64 */ + AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ /* SODIMM 56 */ + AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ /* SODIMM 58 */ + AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ /* SODIMM 60 */ + AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ /* SODIMM 62 */ + AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ /* SODIMM 66 */ + >; + }; + + /* Verdin ETH_1 RGMII (On-module PHY) */ + pinctrl_rgmii1: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ /* RGMII_RXD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ /* RGMII_RXD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ /* RGMII_RXD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ /* RGMII_RXD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ /* RGMII_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ /* RGMII_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ /* RGMII_TXD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ /* RGMII_TXD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ /* RGMII_TXD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ /* RGMII_TXD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ /* RGMII_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ /* RGMII_TX_CTL */ + >; + }; + + /* Verdin ETH_2 RGMII */ + pinctrl_rgmii2: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ /* SODIMM 201 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ /* SODIMM 203 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ /* SODIMM 205 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ /* SODIMM 207 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ /* SODIMM 197 */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ /* SODIMM 199 */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ /* SODIMM 221 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ /* SODIMM 219 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ /* SODIMM 217 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ /* SODIMM 215 */ + AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */ /* SODIMM 213 */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ /* SODIMM 211 */ + >; + }; + + /* TPM SPI, Optional Module Specific SPI */ + pinctrl_main_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_INPUT, 0) /* (B21) SPI0_CLK */ /* TPM_SPI_CLK - SODIMM 148 */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ /* TPM_SPI_MOSI - SODIMM 150 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ /* TPM_SPI_MISO - SODIMM 152 */ + AM62PX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D20) SPI0_CS0 */ /* TPM_SPI_CS */ + >; + }; + + /* Verdin SPI_1 */ + pinctrl_main_spi1: main-spi1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0020, PIN_INPUT, 1) /* (N22) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ + AM62PX_IOPAD(0x0024, PIN_OUTPUT, 1) /* (P21) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ + AM62PX_IOPAD(0x0028, PIN_INPUT, 1) /* (N20) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ + >; + }; + + /* Verdin SPI_1_CS */ + pinctrl_main_spi1_cs0: main-spi1-cs0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x001c, PIN_OUTPUT, 1) /* (N21) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ + >; + }; + + /* Verdin I2S_1 MCLK */ + pinctrl_i2s1_mclk: main-system-audio-ext-reflock0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 5) /* (Y23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ /* SODIMM 38 */ + >; + }; + + pinctrl_eth_clock: main-system-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (C25) EXT_REFCLK1.CLKOUT0 */ /* ETH_25MHz_CLK */ + >; + }; + + pinctrl_pmic_extint: main-system-extint-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f4, PIN_INPUT, 0) /* (C23) EXTINTn */ /* PMIC_EXTINT# */ + >; + }; + + /* Verdin UART_3, used as the Linux console */ + pinctrl_uart0: main-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ /* SODIMM 147 */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ /* SODIMM 149 */ + >; + }; + + /* Verdin UART_1 */ + pinctrl_uart1: main-uart1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ + AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ + AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ + AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ + >; + }; + + /* Verdin MSP 41, 42, 44 and 45 as UART */ + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b8, PIN_INPUT, 4) /* (AE24) VOUT0_DATA0.UART2_RXD */ /* SODIMM 192 */ + AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 4) /* (W23) VOUT0_DATA1.UART2_TXD */ /* SODIMM 190 */ + AM62PX_IOPAD(0x0104, PIN_INPUT, 4) /* (Y21) VOUT0_PCLK.UART2_CTSn */ /* SODIMM 184 */ + AM62PX_IOPAD(0x0100, PIN_OUTPUT, 4) /* (W20) VOUT0_VSYNC.UART2_RTSn */ /* SODIMM 186 */ + >; + }; + + /* Bluetooth on WB SKUs */ + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d8, PIN_INPUT, 4) /* (AE22) VOUT0_DATA8.UART6_RXD */ /* WiFi_UART_RXD */ + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (AC22) VOUT0_DATA9.UART6_TXD */ /* WiFi_UART_TXD */ + AM62PX_IOPAD(0x00e4, PIN_INPUT, 4) /* (AE21) VOUT0_DATA11.UART6_CTSn */ /* WiFi_UART_CTS */ + AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (W22) VOUT0_DATA10.UART6_RTSn */ /* WiFi_UART_RTS */ + >; + }; + + /* Verdin USB_2_EN */ + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ /* SODIMM 185 */ + >; + }; + + /* Verdin I2S_1 */ + pinctrl_mcasp0: mcasp0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_INPUT, 0) /* (F24) MCASP0_ACLKX */ /* SODIMM 30 */ + AM62PX_IOPAD(0x01a8, PIN_INPUT, 0) /* (F25) MCASP0_AFSX */ /* SODIMM 32 */ + AM62PX_IOPAD(0x01a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ /* SODIMM 34 */ + AM62PX_IOPAD(0x019c, PIN_INPUT, 0) /* (E24) MCASP0_AXR1 */ /* SODIMM 36 */ + >; + }; + + /* Verdin I2S_2 */ + pinctrl_mcasp1: mcasp1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ + AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ + AM62PX_IOPAD(0x0088, PIN_INPUT, 2) /* (R24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ + >; + }; + + /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ + pinctrl_mdio: mdio0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ /* SODIMM 193 */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ /* SODIMM 191 */ + >; + }; +}; + +&mcu_pmx0 { + /* Verdin GPIO_1 */ + pinctrl_gpio_1: mcu-gpio0-1-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (E10) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ + >; + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio_2: mcu-gpio0-2-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (C10) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ + >; + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio_3: mcu-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (B11) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ + >; + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio_4: mcu-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (D10) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ + >; + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (E11) MCU_I2C0_SCL */ /* SODIMM 59 */ + AM62PX_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D11) MCU_I2C0_SDA */ /* SODIMM 57 */ + >; + }; + + /* Verdin CAN_2 */ + pinctrl_mcu_mcan0: mcu-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */ /* SODIMM 22 */ + AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* Verdin MSP_13/MSP_18 as CAN */ + pinctrl_mcu_mcan1: mcu-mcan1-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */ /* SODIMM 116 */ + AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */ /* SODIMM 128 */ + >; + }; + + /* Verdin UART_4 */ + pinctrl_mcu_uart0: mcu-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0014, PIN_INPUT, 0) /* (B6) MCU_UART0_RXD */ /* SODIMM 151 */ + AM62PX_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (C8) MCU_UART0_TXD */ /* SODIMM 153 */ + >; + }; + + /* On-module I2C - PMIC_I2C */ + pinctrl_wkup_i2c0: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x004c, PIN_INPUT, 0) /* (A13) WKUP_I2C0_SCL */ /* PMIC_I2C_SCL */ + AM62PX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (C11) WKUP_I2C0_SDA */ /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_wkup_clkout0: wkup-system-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ /* SODIMM 91 */ + >; + }; + + /* Verdin UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ /* SODIMM 143 */ + AM62PX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ /* SODIMM 141 */ + AM62PX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ /* SODIMM 137 */ + AM62PX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ /* SODIMM 139 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "disabled"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>, <&pinctrl_eth_clock>; + assigned-clocks = <&k3_clks 157 36>; + assigned-clock-parents = <&k3_clks 157 38>; + assigned-clock-rates = <25000000>; + status = "disabled"; + + som_eth_phy: ethernet-phy@0 { + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <36 IRQ_TYPE_EDGE_FALLING>; + ti,clk-output-sel = ; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + phy-handle = <&som_eth_phy>; + phy-mode = "rgmii-rxid"; + status = "disabled"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + status = "disabled"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm0_b>; + status = "disabled"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm2_a>, <&pinctrl_epwm2_b>; + status = "disabled"; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&main_gpio0 { + gpio-line-names = + "SODIMM_52", + "SODIMM_252", + "SODIMM_66", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", /* 10 */ + "SODIMM_54", + "SODIMM_64", + "SODIMM_174", + "SODIMM_244", + "", + "", + "", + "", + "", + "", /* 20 */ + "PMIC_SD_VSEL", + "", + "", + "", + "TPM_EXTINT#", + "", + "", + "", + "WiFi_WKUP_BT#", + "WiFi_WKUP_WLAN#", /* 30 */ + "SODIMM_161", + "SODIMM_157", + "", + "", + "", + "ETH_INT#", + "", + "SODIMM_17", + "SODIMM_21", + "", /* 40 */ + "SODIMM_187", + "SODIMM_189", + "", + "", + "", + "", + "SODIMM_76", + "", + "SODIMM_216", + "SODIMM_218", /* 50 */ + "SODIMM_220", + "SODIMM_222", + "", + "", + "", + "", + "SODIMM_172", + "", + "WIFI_SD_INT", + "WIFI_SPI_CS#", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 90 */ + ""; + + verdin_pcie_1_reset_hog: pcie-1-reset-hog { + gpio-hog; + /* Verdin PCIE_1_RESET# (SODIMM 244) */ + gpios = <14 GPIO_ACTIVE_LOW>; + line-name = "PCIE_1_RESET#"; + output-low; + status = "disabled"; + }; +}; + +&main_gpio1 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "SODIMM_84", + "SODIMM_154", + "SODIMM_155", /* 50 */ + ""; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c0>; + status = "disabled"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c1>; + status = "disabled"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c3>; + status = "disabled"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mcan0>; + status = "disabled"; +}; + +/* TPM SPI, optional SPI on module specific pins */ +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi0>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm_extint>; + interrupt-parent = <&main_gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi1>, <&pinctrl_main_spi1_cs0>; + ti,pindir-d0-out-d1-in; + status = "disabled"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp0>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <0>; + tx-num-evt = <0>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2S_2 */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <0>; + tx-num-evt = <0>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&mcu_gpio0 { + gpio-line-names = + "", + "SODIMM_206", + "SODIMM_208", + "SODIMM_210", + "SODIMM_212", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + ""; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c0>; + status = "disabled"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan0>; + status = "disabled"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_uart0>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ospi0>; + status = "disabled"; +}; + +/* On-module eMMC */ +&sdhci0 { + no-mmc-hs400; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>, <&pinctrl_sd1_cd>; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_sd1_vmmc>; + vqmmc-supply = <®_sd1_vqmmc>; + ti,fails-without-test-cd; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbss0 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb0 { + adp-disable; + usb-role-switch; + status = "disabled"; + + port { + usb0_ep: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Verdin USB_2 */ +&usbss1 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "disabled"; +}; + +/* On-module I2C - PMIC_I2C */ +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + som_gpio_expander: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "SODIMM_256"; + }; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_extint>; + interrupt-parent = <&gic500>; + interrupts = ; + + buck1-supply = <®_vsodimm>; + buck2-supply = <®_vsodimm>; + buck3-supply = <®_vsodimm>; + ldo1-supply = <®_3v3>; + ldo2-supply = <®_1v8>; + ldo3-supply = <®_3v3>; + ldo4-supply = <®_3v3>; + system-power-controller; + ti,power-button; + + regulators { + reg_3v3: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3 (PMIC BUCK1)"; + }; + + reg_1v8: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ + }; + + buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR (PMIC BUCK3)"; + }; + + reg_sd_3v3_1v8: ldo1 { + regulator-allow-bypass; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; + }; + + ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+V_PMIC_LDO2 (PMIC LDO4)"; // +VDDR_CORE + }; + + ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "+V2.5_ETH (PMIC LDO4)"; + }; + }; + }; + + som_rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* Verdin (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + uart-has-rtscts; + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi b/arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi new file mode 100644 index 00000000000..4534b0ae44b --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi @@ -0,0 +1,2801 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.30 + * Sun Mar 09 2025 17:28:17 GMT+0100 (Central European Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1600MHz + * Density (per channel): 8Gb + * Number of Ranks: 1 +*/ + + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 +#define DDRSS_SDRAM_IDX 15 +#define DDRSS_REGION_IDX 17 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000C80 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004040 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00000E38 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00000E38 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000A00 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x006B0014 +#define DDRSS_CTL_51_DATA 0x09110048 +#define DDRSS_CTL_52_DATA 0x00004220 +#define DDRSS_CTL_53_DATA 0x006B0014 +#define DDRSS_CTL_54_DATA 0x09110048 +#define DDRSS_CTL_55_DATA 0x09004220 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040001B6 +#define DDRSS_CTL_58_DATA 0x090D2005 +#define DDRSS_CTL_59_DATA 0x00001710 +#define DDRSS_CTL_60_DATA 0x0C0036D8 +#define DDRSS_CTL_61_DATA 0x090D200D +#define DDRSS_CTL_62_DATA 0x00001710 +#define DDRSS_CTL_63_DATA 0x0C0036D8 +#define DDRSS_CTL_64_DATA 0x0304200D +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x1F211F21 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x043F3F07 +#define DDRSS_CTL_69_DATA 0x03252503 +#define DDRSS_CTL_70_DATA 0x00002525 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x000E0803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x000001C0 +#define DDRSS_CTL_77_DATA 0x0000185E +#define DDRSS_CTL_78_DATA 0x000001C0 +#define DDRSS_CTL_79_DATA 0x0000185E +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x00000007 +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x000000E0 +#define DDRSS_CTL_84_DATA 0x00000304 +#define DDRSS_CTL_85_DATA 0x000000E0 +#define DDRSS_CTL_86_DATA 0x00000304 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000C0005 +#define DDRSS_CTL_90_DATA 0x2408000C +#define DDRSS_CTL_91_DATA 0x0A050524 +#define DDRSS_CTL_92_DATA 0x170C0803 +#define DDRSS_CTL_93_DATA 0x170C0803 +#define DDRSS_CTL_94_DATA 0x03010103 +#define DDRSS_CTL_95_DATA 0x00010301 +#define DDRSS_CTL_96_DATA 0x000F000F +#define DDRSS_CTL_97_DATA 0x01CC01CC +#define DDRSS_CTL_98_DATA 0x01CC01CC +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x03031804 +#define DDRSS_CTL_103_DATA 0x0C080C08 +#define DDRSS_CTL_104_DATA 0x08030318 +#define DDRSS_CTL_105_DATA 0x030C080C +#define DDRSS_CTL_106_DATA 0x00000303 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00061780 +#define DDRSS_CTL_127_DATA 0x00061780 +#define DDRSS_CTL_128_DATA 0x00061780 +#define DDRSS_CTL_129_DATA 0x00061780 +#define DDRSS_CTL_130_DATA 0x00061780 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000AA92 +#define DDRSS_CTL_133_DATA 0x00061780 +#define DDRSS_CTL_134_DATA 0x00061780 +#define DDRSS_CTL_135_DATA 0x00061780 +#define DDRSS_CTL_136_DATA 0x00061780 +#define DDRSS_CTL_137_DATA 0x00061780 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000AA92 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x03080308 +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00A00140 +#define DDRSS_CTL_199_DATA 0x0C0C0190 +#define DDRSS_CTL_200_DATA 0x00000190 +#define DDRSS_CTL_201_DATA 0x00A00140 +#define DDRSS_CTL_202_DATA 0x0C0C0190 +#define DDRSS_CTL_203_DATA 0x00000190 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000054 +#define DDRSS_CTL_212_DATA 0x0000002D +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000054 +#define DDRSS_CTL_215_DATA 0x0000002D +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000054 +#define DDRSS_CTL_221_DATA 0x0000002D +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000054 +#define DDRSS_CTL_224_DATA 0x0000002D +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000029 +#define DDRSS_CTL_228_DATA 0x000000A9 +#define DDRSS_CTL_229_DATA 0x000000A9 +#define DDRSS_CTL_230_DATA 0x00000029 +#define DDRSS_CTL_231_DATA 0x000000A9 +#define DDRSS_CTL_232_DATA 0x000000A9 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x35003535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000015 +#define DDRSS_CTL_278_DATA 0x00000015 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x06400040 +#define DDRSS_CTL_316_DATA 0x00020030 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x00300640 +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x00500050 +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0xFFFFFFFF +#define DDRSS_CTL_327_DATA 0x00FFFF00 +#define DDRSS_CTL_328_DATA 0x0B000000 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C01 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x7FFFFFFF +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0xFFFFFFFF +#define DDRSS_CTL_361_DATA 0xFFFF0000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0xFFFFFFFF +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00FFFFFF +#define DDRSS_CTL_366_DATA 0xFFFF00FF +#define DDRSS_CTL_367_DATA 0x0000FFFF +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01080803 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0C081818 +#define DDRSS_CTL_389_DATA 0x0008040C +#define DDRSS_CTL_390_DATA 0x0B100406 +#define DDRSS_CTL_391_DATA 0x0B100406 +#define DDRSS_CTL_392_DATA 0x10100806 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x06030601 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x33200404 +#define DDRSS_CTL_406_DATA 0x000030BC +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000DB4E +#define DDRSS_CTL_412_DATA 0x0001E758 +#define DDRSS_CTL_413_DATA 0x0F160402 +#define DDRSS_CTL_414_DATA 0x33200A07 +#define DDRSS_CTL_415_DATA 0x000030BC +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000DB4E +#define DDRSS_CTL_421_DATA 0x0001E758 +#define DDRSS_CTL_422_DATA 0x0F160402 +#define DDRSS_CTL_423_DATA 0x00200A07 +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00001E1E +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00050001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x05000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x00050500 +#define DDRSS_PI_49_DATA 0x00000019 +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00001705 +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010500 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x00F000F0 +#define DDRSS_PI_178_DATA 0x00202001 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x00000058 +#define DDRSS_PI_181_DATA 0x00020058 +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x00000E0C +#define DDRSS_PI_185_DATA 0x000E3800 +#define DDRSS_PI_186_DATA 0x00380000 +#define DDRSS_PI_187_DATA 0x0000000E +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x000001C0 +#define DDRSS_PI_190_DATA 0x0000185E +#define DDRSS_PI_191_DATA 0x000001C0 +#define DDRSS_PI_192_DATA 0x0400185E +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00250025 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05080803 +#define DDRSS_PI_200_DATA 0x01011818 +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0A021010 +#define DDRSS_PI_207_DATA 0x0404020A +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x00190041 +#define DDRSS_PI_210_DATA 0x00190041 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x00030190 +#define DDRSS_PI_214_DATA 0x01000190 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01910100 +#define DDRSS_PI_217_DATA 0x01000191 +#define DDRSS_PI_218_DATA 0x01910191 +#define DDRSS_PI_219_DATA 0x301B3200 +#define DDRSS_PI_220_DATA 0x0101301B +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x180F090D +#define DDRSS_PI_223_DATA 0x180F0911 +#define DDRSS_PI_224_DATA 0x000C0011 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x001E000D +#define DDRSS_PI_231_DATA 0x001E0190 +#define DDRSS_PI_232_DATA 0x00000190 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00230204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x13000101 +#define DDRSS_PI_239_DATA 0x00230A10 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x13000101 +#define DDRSS_PI_242_DATA 0x00000A10 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000018A +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x250D0000 +#define DDRSS_PI_249_DATA 0x1F090021 +#define DDRSS_PI_250_DATA 0x0000315C +#define DDRSS_PI_251_DATA 0x20060048 +#define DDRSS_PI_252_DATA 0x17101718 +#define DDRSS_PI_253_DATA 0x250D0000 +#define DDRSS_PI_254_DATA 0x1F090021 +#define DDRSS_PI_255_DATA 0x0000315C +#define DDRSS_PI_256_DATA 0x20060048 +#define DDRSS_PI_257_DATA 0x17101718 +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000030BC +#define DDRSS_PI_262_DATA 0x0001E758 +#define DDRSS_PI_263_DATA 0x000030BC +#define DDRSS_PI_264_DATA 0x0001E758 +#define DDRSS_PI_265_DATA 0x01CC000F +#define DDRSS_PI_266_DATA 0x030301CC +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x08030503 +#define DDRSS_PI_270_DATA 0x00000803 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x0000000F +#define DDRSS_PI_276_DATA 0x0004E200 +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000C80 +#define DDRSS_PI_280_DATA 0x000001CC +#define DDRSS_PI_281_DATA 0x0004E200 +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000C80 +#define DDRSS_PI_285_DATA 0x010001CC +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x06400040 +#define DDRSS_PI_289_DATA 0x00010030 +#define DDRSS_PI_290_DATA 0x06400040 +#define DDRSS_PI_291_DATA 0x00000330 +#define DDRSS_PI_292_DATA 0x00280050 +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000029 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000054 +#define DDRSS_PI_338_DATA 0x0000002D +#define DDRSS_PI_339_DATA 0x000000A9 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20152B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000054 +#define DDRSS_PI_346_DATA 0x0000002D +#define DDRSS_PI_347_DATA 0x000000A9 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20152B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000029 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000054 +#define DDRSS_PI_362_DATA 0x0000002D +#define DDRSS_PI_363_DATA 0x000000A9 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20152B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000054 +#define DDRSS_PI_370_DATA 0x0000002D +#define DDRSS_PI_371_DATA 0x000000A9 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20152B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000029 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000054 +#define DDRSS_PI_386_DATA 0x0000002D +#define DDRSS_PI_387_DATA 0x000000A9 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20152B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000054 +#define DDRSS_PI_394_DATA 0x0000002D +#define DDRSS_PI_395_DATA 0x000000A9 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20152B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000029 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000054 +#define DDRSS_PI_410_DATA 0x0000002D +#define DDRSS_PI_411_DATA 0x000000A9 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20152B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000054 +#define DDRSS_PI_418_DATA 0x0000002D +#define DDRSS_PI_419_DATA 0x000000A9 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20152B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000104 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0B01 +#define DDRSS_PHY_80_DATA 0x1003CC0B +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00031000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000004 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0B000000 +#define DDRSS_PHY_99_DATA 0x000B0A0A +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C2D +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x00F50120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x00000299 +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000B2010 +#define DDRSS_PHY_111_DATA 0x43180276 +#define DDRSS_PHY_112_DATA 0x00000005 +#define DDRSS_PHY_113_DATA 0x04190419 +#define DDRSS_PHY_114_DATA 0x04190419 +#define DDRSS_PHY_115_DATA 0x04190419 +#define DDRSS_PHY_116_DATA 0x04190419 +#define DDRSS_PHY_117_DATA 0x00000419 +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x01E600A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000104 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0B01 +#define DDRSS_PHY_336_DATA 0x1003CC0B +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00031000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000004 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0B000000 +#define DDRSS_PHY_355_DATA 0x000B0A0A +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C2D +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x00F50120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x00000299 +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000B2010 +#define DDRSS_PHY_367_DATA 0x65328017 +#define DDRSS_PHY_368_DATA 0x00000004 +#define DDRSS_PHY_369_DATA 0x04190419 +#define DDRSS_PHY_370_DATA 0x04190419 +#define DDRSS_PHY_371_DATA 0x04190419 +#define DDRSS_PHY_372_DATA 0x04190419 +#define DDRSS_PHY_373_DATA 0x00000419 +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x01E600A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000104 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0B01 +#define DDRSS_PHY_592_DATA 0x1003CC0B +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00031000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000004 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0B000000 +#define DDRSS_PHY_611_DATA 0x000B0A0A +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C2D +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x00F50120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x00000299 +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000B2010 +#define DDRSS_PHY_623_DATA 0x78610245 +#define DDRSS_PHY_624_DATA 0x00000003 +#define DDRSS_PHY_625_DATA 0x04190419 +#define DDRSS_PHY_626_DATA 0x04190419 +#define DDRSS_PHY_627_DATA 0x04190419 +#define DDRSS_PHY_628_DATA 0x04190419 +#define DDRSS_PHY_629_DATA 0x00000419 +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x01E600A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000001 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000104 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0B01 +#define DDRSS_PHY_848_DATA 0x1003CC0B +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00031000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000004 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0B000000 +#define DDRSS_PHY_867_DATA 0x000B0A0A +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C2D +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x00F50120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x00000299 +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000B2010 +#define DDRSS_PHY_879_DATA 0x01462358 +#define DDRSS_PHY_880_DATA 0x00000007 +#define DDRSS_PHY_881_DATA 0x04190419 +#define DDRSS_PHY_882_DATA 0x04190419 +#define DDRSS_PHY_883_DATA 0x04190419 +#define DDRSS_PHY_884_DATA 0x04190419 +#define DDRSS_PHY_885_DATA 0x00000419 +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x01E600A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000304CC +#define DDRSS_PHY_1062_DATA 0x03000003 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000304CC +#define DDRSS_PHY_1318_DATA 0x03000003 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000304CC +#define DDRSS_PHY_1574_DATA 0x03000003 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76542310 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C3 +#define DDRSS_PHY_1889_DATA 0x03000003 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000004 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F91 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040005 diff --git a/arch/arm/dts/k3-am62p5-verdin-r5.dts b/arch/arm/dts/k3-am62p5-verdin-r5.dts new file mode 100644 index 00000000000..983a3bfe670 --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-r5.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Toradex Verdin AM62P dts file for R5 SPL + * Copyright 2025 Toradex - https://www.toradex.com/ + */ + +#include "k3-am62p5-verdin-wifi-dev.dts" +#include "k3-am62p5-verdin-lpddr4-1600.dtsi" +#include "k3-am62a-ddr.dtsi" + +#include "k3-am62p5-verdin-wifi-dev-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 36>; + assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 38>; + assigned-clock-rates = <200000000>, <1200000000>, <25000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-all; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 20>, + <&secure_proxy_main 21>; + bootph-all; + }; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + reg-names = "rt", "scfg", "target_data"; + bootph-all; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-all; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi new file mode 100644 index 00000000000..13fac18d7aa --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + */ + +#include "k3-binman.dtsi" + +#if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_R5) + +&binman { + tiboot3-am62px-hs-fs-verdin.bin { + filename = "tiboot3-am62px-hs-fs-verdin.bin"; + symlink = "tiboot3.bin"; + + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; + + tiboot3-am62px-hs-verdin.bin { + filename = "tiboot3-am62px-hs-verdin.bin"; + + ti-secure-rom { + content = <&u_boot_spl_hs>, <&ti_fs_enc_hs>, <&combined_tifs_cfg_hs>, + <&combined_dm_cfg_hs>, <&sysfw_inner_cert_hs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_hs>; + content-sysfw = <&ti_fs_enc_hs>; + content-sysfw-data = <&combined_tifs_cfg_hs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_hs>; + content-dm-data = <&combined_dm_cfg_hs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + + u_boot_spl_hs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_hs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_hs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_hs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_hs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif /* CONFIG_TARGET_VERDIN_AM62P_R5 */ + +#if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_A53) + +#define SPL_VERDIN_AM62P_DTB "spl/dts/k3-am62p5-verdin-wifi-dev.dtb" +#define VERDIN_AM62P_DTB "u-boot.dtb" + +&binman { + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x60000>; + sw-rev = ; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + dm { + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + + dm: ti-dm { + filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + fdt-0 { + description = "k3-am62p5-verdin-wifi-dev"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&spl_verdin_am62p_dtb>; + keyfile = "custMpk.pem"; + }; + + spl_verdin_am62p_dtb: blob-ext { + filename = SPL_VERDIN_AM62P_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62p5-verdin-wifi-dev"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for Verdin AM62P5 Boards"; + }; + + fdt-0 { + description = "k3-am62p5-verdin-wifi-dev"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&verdin_am62p_dtb>; + keyfile = "custMpk.pem"; + }; + + verdin_am62p_dtb: blob-ext { + filename = VERDIN_AM62P_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62p5-verdin-wifi-dev"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; + +&binman { + firmware-verdin-am62px-hs.bin { + filename = "firmware-verdin-am62px-hs.bin"; + + blob-ext@1 { + filename = "tiboot3-am62px-hs-verdin.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-verdin-am62px-hs-fs.bin { + filename = "firmware-verdin-am62px-hs-fs.bin"; + + blob-ext@1 { + filename = "tiboot3-am62px-hs-fs-verdin.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; +}; + +#endif /* CONFIG_TARGET_VERDIN_AM62P_A53 */ diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi new file mode 100644 index 00000000000..366867d1e6a --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + */ + +#include "k3-am62p5-verdin-wifi-dev-binman.dtsi" + +/ { + chosen { + tick-timer = &main_timer0; + }; + + memory@80000000 { + bootph-pre-ram; + }; + + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&carrier_eth_phy { + bootph-all; +}; + +&cpsw3g { + ethernet-ports { + bootph-all; + }; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + bootph-all; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + bootph-all; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + bootph-all; +}; + +&dmsc { + bootph-all; +}; + +&k3_clks { + bootph-all; +}; + +&k3_pds { + bootph-all; +}; + +&k3_reset { + bootph-all; +}; + +&main_gpio0 { + bootph-all; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + bootph-all; +}; + +&main_pktdma { + bootph-all; +}; + +&mcu_pmx0 { + bootph-all; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + bootph-all; +}; + +&main_pmx0 { + bootph-all; +}; + +&pinctrl_main_i2c0 { + bootph-all; +}; + +&pinctrl_mdio { + bootph-all; +}; + +&pinctrl_rgmii1 { + bootph-all; +}; + +&pinctrl_rgmii2 { + bootph-all; +}; + +&pinctrl_uart0 { + bootph-all; +}; + +&pinctrl_wkup_i2c0 { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + +&sdhci0 { + bootph-all; +}; + +&sdhci2 { + status = "disabled"; +}; + +&som_eth_phy { + bootph-all; +}; + +&som_gpio_expander { + bootph-all; + + ctrl-sleep-moci-hog { + bootph-all; + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; +}; + +/* Required for USB DFU Boot */ +&usb0 { + /* Enable peripheral mode only during bootup + * to support DFU while allowing Linux to stay + * in OTG mode + */ + dr_mode = "peripheral"; + bootph-all; +}; + +/* Required for USB DFU Boot */ +&usb0_phy_ctrl { + bootph-all; +}; + +/* Required for USB DFU Boot */ +&usbss0 { + bootph-all; +}; + +/* On-module I2C - PMIC_I2C */ +&wkup_i2c0 { + bootph-all; +}; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts b/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts new file mode 100644 index 00000000000..bbc2770d5f5 --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Verdin Development Board"; + compatible = "toradex,verdin-am62p-wifi-dev", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi index 5228eed19bf..966905bd64d 100644 --- a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi @@ -33,7 +33,6 @@ ti_sci_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -42,7 +41,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -73,7 +71,6 @@ ti_sci_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_fs: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -82,7 +79,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -109,7 +105,6 @@ ti_sci_gp: ti-sci-gp.bin { filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin { filename = "combined-sysfw-cfg.bin"; diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi index f768c4d946d..32e47a3f688 100644 --- a/arch/arm/dts/k3-am64x-binman.dtsi +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -29,7 +29,6 @@ ti_sci_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -38,7 +37,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -69,7 +67,6 @@ ti_sci_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_fs: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -78,7 +75,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -105,7 +101,6 @@ ti_sci_gp: ti-sci-gp.bin { filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin { filename = "combined-sysfw-cfg.bin"; diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi index 350775e42c2..cc82c8b5768 100644 --- a/arch/arm/dts/k3-am65x-binman.dtsi +++ b/arch/arm/dts/k3-am65x-binman.dtsi @@ -32,12 +32,10 @@ ti_sci_cert: ti-sci-cert.bin { filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; ti-sci-firmware-am65x-hs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; }; itb { @@ -73,7 +71,6 @@ ti_sci: ti-sci.bin { filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-gp.bin"; type = "blob-ext"; - optional; }; }; itb_gp { diff --git a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi index ba05d410357..2a0023fb7c3 100644 --- a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi +++ b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi @@ -88,7 +88,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { @@ -99,7 +98,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { @@ -140,7 +138,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -151,7 +148,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -181,7 +177,6 @@ dm: ti-dm { filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 47a4cde6b85..b74bd1657f9 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -35,7 +35,6 @@ ti_fs_enc_sr1: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_sr1: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -44,7 +43,6 @@ sysfw_inner_cert_sr1: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_sr1: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -80,7 +78,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -89,7 +86,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -127,7 +123,6 @@ ti_fs_enc_fs_sr1: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -136,7 +131,6 @@ sysfw_inner_cert_fs_sr1: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs_sr1: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -172,7 +166,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -181,7 +174,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -216,7 +208,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-j7200-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -339,7 +330,6 @@ }; dm: ti-dm { filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; @@ -425,7 +415,6 @@ dm { ti-dm { filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 6adfab164ee..9522a956506 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -46,12 +46,10 @@ ti_fs_cert: ti-fs-cert.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e_sr1_1-hs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-enc.bin"; type = "blob-ext"; - optional; }; }; @@ -67,12 +65,10 @@ ti_fs_cert_sr2: ti-fs-cert.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e_sr2-hs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; }; @@ -148,12 +144,10 @@ ti-fs-cert-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e-hs-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; }; itb_fs_sr1_1 { @@ -235,12 +229,10 @@ ti-fs-cert-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e-hs-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; }; itb_fs { @@ -276,7 +268,6 @@ ti_fs: ti-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin"; type = "blob-ext"; - optional; }; }; itb_gp { @@ -461,7 +452,6 @@ }; dm: ti-dm { filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; @@ -546,7 +536,6 @@ dm { ti-dm { filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts index 586ddb6e7c8..5f0dfe9c2fa 100644 --- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts +++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts @@ -47,7 +47,6 @@ ti_fs: ti-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin"; type = "blob-ext"; - optional; }; }; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 73af184d27e..4f524e58ceb 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -34,7 +34,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -43,7 +42,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -79,7 +77,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -88,7 +85,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -123,7 +119,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-j721s2-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -280,7 +275,6 @@ }; dm: ti-dm { filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; @@ -366,7 +360,6 @@ dm { ti-dm { filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi index 8f1471371e5..57e966ea666 100644 --- a/arch/arm/dts/k3-j722s-binman.dtsi +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -36,7 +36,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { @@ -47,7 +46,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { @@ -88,7 +86,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -99,7 +96,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -129,7 +125,6 @@ dm: ti-dm { filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; }; }; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index cb1fbc65923..a7ce1ee2b03 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -39,7 +39,6 @@ ti_fs_enc: ti-fs-enc.bin { type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { @@ -49,7 +48,6 @@ sysfw_inner_cert: sysfw-inner-cert { type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { @@ -88,7 +86,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -98,7 +95,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -135,7 +131,6 @@ ti_fs_gp: ti-fs-gp.bin { type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { @@ -166,7 +161,6 @@ }; dm: ti-dm { - optional; }; }; @@ -255,7 +249,6 @@ images { dm { ti-dm { - optional; }; }; diff --git a/arch/arm/dts/k3-pinctrl.h b/arch/arm/dts/k3-pinctrl.h deleted file mode 100644 index 2a4e0e084d6..00000000000 --- a/arch/arm/dts/k3-pinctrl.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for pinctrl bindings for TI's K3 SoC - * family. - * - * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ - */ -#ifndef DTS_ARM64_TI_K3_PINCTRL_H -#define DTS_ARM64_TI_K3_PINCTRL_H - -#define PULLUDEN_SHIFT (16) -#define PULLTYPESEL_SHIFT (17) -#define RXACTIVE_SHIFT (18) -#define DEBOUNCE_SHIFT (11) - -#define PULL_DISABLE (1 << PULLUDEN_SHIFT) -#define PULL_ENABLE (0 << PULLUDEN_SHIFT) - -#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) -#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) - -#define INPUT_EN (1 << RXACTIVE_SHIFT) -#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) - -/* Only these macros are expected be used directly in device tree files */ -#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) - -#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) -#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) -#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) -#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) -#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) -#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) -#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) - -#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#endif diff --git a/arch/arm/dts/k3-serdes.h b/arch/arm/dts/k3-serdes.h deleted file mode 100644 index 21b4886c47b..00000000000 --- a/arch/arm/dts/k3-serdes.h +++ /dev/null @@ -1,204 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for SERDES MUX for TI SoCs - * - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef DTS_ARM64_TI_K3_SERDES_H -#define DTS_ARM64_TI_K3_SERDES_H - -/* J721E */ - -#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 -#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 -#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 -#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 -#define J721E_SERDES0_LANE1_USB3_0 0x2 -#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 -#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 -#define J721E_SERDES1_LANE1_USB3_1 0x2 -#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 -#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 -#define J721E_SERDES2_LANE1_USB3_1 0x2 -#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 -#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 -#define J721E_SERDES3_LANE1_USB3_0 0x2 -#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 -#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 -#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 -#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 -#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 -#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 -#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 -#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 -#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 - -/* J7200 */ - -#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 -#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 -#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 -#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 -#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J7200_SERDES0_LANE3_USB 0x2 -#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* AM64 */ - -#define AM64_SERDES0_LANE0_PCIE0 0x0 -#define AM64_SERDES0_LANE0_USB 0x1 - -/* J721S2 */ - -#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 -#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 -#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J721S2_SERDES0_LANE1_USB 0x2 -#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 -#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_USB_SWAP 0x2 -#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 -#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J721S2_SERDES0_LANE3_USB 0x2 -#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* J784S4 */ - -#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 -#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 -#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J784S4_SERDES0_LANE3_USB 0x2 -#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 -#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 -#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 -#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 -#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 -#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 -#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 -#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 -#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 -#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 -#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 -#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 -#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 -#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 -#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES4_LANE0_EDP_LANE0 0x0 -#define J784S4_SERDES4_LANE0_QSGMII_LANE5 0x1 -#define J784S4_SERDES4_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES4_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES4_LANE1_EDP_LANE1 0x0 -#define J784S4_SERDES4_LANE1_QSGMII_LANE6 0x1 -#define J784S4_SERDES4_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES4_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES4_LANE2_EDP_LANE2 0x0 -#define J784S4_SERDES4_LANE2_QSGMII_LANE7 0x1 -#define J784S4_SERDES4_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES4_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES4_LANE3_EDP_LANE3 0x0 -#define J784S4_SERDES4_LANE3_QSGMII_LANE8 0x1 -#define J784S4_SERDES4_LANE3_USB 0x2 -#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 - -#endif /* DTS_ARM64_TI_K3_SERDES_H */ diff --git a/arch/arm/dts/mxs-pinfunc.h b/arch/arm/dts/mxs-pinfunc.h deleted file mode 100644 index 31297abcbc7..00000000000 --- a/arch/arm/dts/mxs-pinfunc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Header providing constants for i.MX28 pinctrl bindings. - * - * Copyright (C) 2013 Lothar Waßmann - */ - -#ifndef __DT_BINDINGS_MXS_PINCTRL_H__ -#define __DT_BINDINGS_MXS_PINCTRL_H__ - -/* fsl,drive-strength property */ -#define MXS_DRIVE_4mA 0 -#define MXS_DRIVE_8mA 1 -#define MXS_DRIVE_12mA 2 -#define MXS_DRIVE_16mA 3 - -/* fsl,voltage property */ -#define MXS_VOLTAGE_LOW 0 -#define MXS_VOLTAGE_HIGH 1 - -/* fsl,pull-up property */ -#define MXS_PULL_DISABLE 0 -#define MXS_PULL_ENABLE 1 - -#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */ diff --git a/arch/arm/dts/qcs615-ride-u-boot.dtsi b/arch/arm/dts/qcs615-ride-u-boot.dtsi new file mode 100644 index 00000000000..68fffc70fcb --- /dev/null +++ b/arch/arm/dts/qcs615-ride-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x7a00000>, + <0x0 0x89600000 0x0 0x30100000>, + <0x0 0xc0000000 0x0 0xc0000000>, + <0x1 0x80000000 0x1 0x00000000>; + }; +}; diff --git a/arch/arm/dts/qcs8300-ride-u-boot.dtsi b/arch/arm/dts/qcs8300-ride-u-boot.dtsi new file mode 100644 index 00000000000..8c353ace71e --- /dev/null +++ b/arch/arm/dts/qcs8300-ride-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x11a80000>, + <0x0 0xc0000000 0x0 0x10000000>, + <0x0 0xd3100000 0x0 0x26b00000>, + <0xe 0x80000000 0x1 0x00000000>, + <0xa 0x80000000 0x1 0x80000000>, + <0x0 0xb0800000 0x0 0x0f200000>, + <0x0 0xd0100000 0x0 0x01800000>, + <0x0 0x91b00000 0x0 0x1e500000>; + }; +}; + diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi deleted file mode 100644 index dd5a208cc1b..00000000000 --- a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board - * - * Copyright (C) 2021-2024 Renesas Electronics Corporation - */ - -#include "r8a774a1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi deleted file mode 100644 index bd91a963cd6..00000000000 --- a/arch/arm/dts/r8a774a1-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on RZ/G2 R8A774A1 SoC - * - * Copyright (C) 2021 Renesas Electronics Corporation - */ - -#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi deleted file mode 100644 index b378cabb22c..00000000000 --- a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board - * - * Copyright (C) 2021-2024 Renesas Electronics Corp. - */ - -#include "r8a774b1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi deleted file mode 100644 index 38a82f065c0..00000000000 --- a/arch/arm/dts/r8a774b1-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774c0-u-boot.dtsi b/arch/arm/dts/r8a774c0-u-boot.dtsi index 4572c22f6c1..17b863d23c9 100644 --- a/arch/arm/dts/r8a774c0-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-u-boot.dtsi @@ -6,8 +6,6 @@ * */ -#include "r8a779x-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi deleted file mode 100644 index 560bea46ad7..00000000000 --- a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board - * - * Copyright (C) 2020-2024 Renesas Electronics Corp. - */ - -#include "r8a774e1-u-boot.dtsi" diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi deleted file mode 100644 index f314b2b0cf8..00000000000 --- a/arch/arm/dts/r8a774e1-u-boot.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a779x-rcar64-u-boot.dtsi" diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dtsi b/arch/arm/dts/r8a7790-lager-u-boot.dtsi index ed1891706ce..2b18e2e6af4 100644 --- a/arch/arm/dts/r8a7790-lager-u-boot.dtsi +++ b/arch/arm/dts/r8a7790-lager-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a7790-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dtsi b/arch/arm/dts/r8a7790-stout-u-boot.dtsi index 3b393045e36..788432bc590 100644 --- a/arch/arm/dts/r8a7790-stout-u-boot.dtsi +++ b/arch/arm/dts/r8a7790-stout-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a7790-u-boot.dtsi" - -&scifa0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7790-u-boot.dtsi b/arch/arm/dts/r8a7790-u-boot.dtsi deleted file mode 100644 index 2a7d76bd7b1..00000000000 --- a/arch/arm/dts/r8a7790-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7790 SoC - * - * Copyright (C) 2018 Marek Vasut - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi index 541c4191d69..ed258d55e58 100644 --- a/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi +++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a7791-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dtsi b/arch/arm/dts/r8a7791-porter-u-boot.dtsi index cbf2c5265d8..cb80842f326 100644 --- a/arch/arm/dts/r8a7791-porter-u-boot.dtsi +++ b/arch/arm/dts/r8a7791-porter-u-boot.dtsi @@ -5,20 +5,13 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a7791-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - -&i2c6 { - status = "okay"; - clock-frequency = <400000>; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; + +&i2c6 { + clock-frequency = <400000>; +}; diff --git a/arch/arm/dts/r8a7791-u-boot.dtsi b/arch/arm/dts/r8a7791-u-boot.dtsi deleted file mode 100644 index bb0e2fd106c..00000000000 --- a/arch/arm/dts/r8a7791-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7791 SoC - * - * Copyright (C) 2018 Marek Vasut - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7792-blanche-u-boot.dtsi b/arch/arm/dts/r8a7792-blanche-u-boot.dtsi deleted file mode 100644 index 8c36a3e5850..00000000000 --- a/arch/arm/dts/r8a7792-blanche-u-boot.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot for the Blanche board - * - * Copyright (C) 2018 Marek Vasut - */ - -#include "r8a7792-u-boot.dtsi" - -&iic3 { - status = "okay"; -}; - -&scif0 { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7792-u-boot.dtsi b/arch/arm/dts/r8a7792-u-boot.dtsi deleted file mode 100644 index ebbdcb7efd5..00000000000 --- a/arch/arm/dts/r8a7792-u-boot.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7792 SoC - * - * Copyright (C) 2018 Marek Vasut - */ - -#include "r8a779x-u-boot.dtsi" - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7793-gose-u-boot.dtsi b/arch/arm/dts/r8a7793-gose-u-boot.dtsi index 41c4361c6e1..fd99e0ffe76 100644 --- a/arch/arm/dts/r8a7793-gose-u-boot.dtsi +++ b/arch/arm/dts/r8a7793-gose-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a7793-u-boot.dtsi" - -&scif0 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7793-u-boot.dtsi b/arch/arm/dts/r8a7793-u-boot.dtsi deleted file mode 100644 index 08f2248e1f3..00000000000 --- a/arch/arm/dts/r8a7793-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7793 SoC - * - * Copyright (C) 2018 Marek Vasut - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dtsi b/arch/arm/dts/r8a7794-alt-u-boot.dtsi index e156b4c93c7..fea7138a1c1 100644 --- a/arch/arm/dts/r8a7794-alt-u-boot.dtsi +++ b/arch/arm/dts/r8a7794-alt-u-boot.dtsi @@ -5,48 +5,9 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a7794-u-boot.dtsi" - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&pfc { - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&scif2 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dtsi b/arch/arm/dts/r8a7794-silk-u-boot.dtsi index e448ea7e146..f87d04b0ae0 100644 --- a/arch/arm/dts/r8a7794-silk-u-boot.dtsi +++ b/arch/arm/dts/r8a7794-silk-u-boot.dtsi @@ -5,12 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a7794-u-boot.dtsi" - -&scif2 { - bootph-all; -}; - &qspi { flash@0 { spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a7794-u-boot.dtsi b/arch/arm/dts/r8a7794-u-boot.dtsi deleted file mode 100644 index 303afaeb4ce..00000000000 --- a/arch/arm/dts/r8a7794-u-boot.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A7794 SoC - * - * Copyright (C) 2018 Marek Vasut - */ - -#include "r8a779x-u-boot.dtsi" - -&usb_extal_clk { - bootph-all; -}; - -&pfc { - bootph-all; -}; - -&rst { - bootph-all; -}; diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 768d633ded0..13760f3d5d4 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index db062f8e8c7..9cc0d52f634 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index d67e94e318b..3cf32d84ca0 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index 8dfa56c2f13..d00ef2f3105 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi index 088839907c2..df862978cba 100644 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2019 Marek Vasut */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index b701f68db81..d9dcce00e90 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a779x-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi index f4bafb6d088..85fccbabfb3 100644 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include "r8a779x-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi index f506a666518..a4e75a67dc3 100644 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a779f0-u-boot.dtsi b/arch/arm/dts/r8a779f0-u-boot.dtsi index 08d32fef2b9..a7ff4eb708a 100644 --- a/arch/arm/dts/r8a779f0-u-boot.dtsi +++ b/arch/arm/dts/r8a779f0-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { soc { rpc: spi@ee200000 { diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index cc9d99b0f34..5aa61314834 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include "r8a779x-rcar64-u-boot.dtsi" - / { binman: binman { multiple-images; @@ -135,14 +133,6 @@ }; }; -&cpg { - bootph-all; -}; - -&hscif0 { - bootph-all; -}; - &hscif0_pins { bootph-all; }; @@ -151,19 +141,11 @@ bootph-all; }; -&pfc { - bootph-all; -}; - &rpc { bank-width = <2>; num-cs = <1>; }; -&rst { - bootph-all; -}; - &soc { apmu@e6170000 { /* Remoteproc */ compatible = "renesas,r8a779g0-cr52"; diff --git a/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi b/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi deleted file mode 100644 index b59cc7deca7..00000000000 --- a/arch/arm/dts/r8a779x-rcar64-u-boot.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car 64bit SoC - * - * Copyright (C) 2024 Marek Vasut - */ - -#include "r8a779x-u-boot.dtsi" - -&extalr_clk { - bootph-all; -}; diff --git a/arch/arm/dts/r8a779x-u-boot.dtsi b/arch/arm/dts/r8a779x-u-boot.dtsi deleted file mode 100644 index d1441f1f9df..00000000000 --- a/arch/arm/dts/r8a779x-u-boot.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car Gen3 - * - * Copyright (C) 2018 Marek Vasut - */ - -/ { - soc { - bootph-all; - }; -}; - -&cpg { - bootph-all; -}; - -&extal_clk { - bootph-all; -}; - -&prr { - bootph-all; -}; diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 7631dfaa07f..79449042c24 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -311,6 +311,14 @@ clocks = <&slow_rc_osc>, <&slow_xtal>; #clock-cells = <1>; }; + + watchdog: watchdog@ffffff80 { + compatible = "microchip,sam9x60-wdt"; + reg = <0xffffff80 0x24>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32 0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/sama5d2-pinfunc.h b/arch/arm/dts/sama5d2-pinfunc.h deleted file mode 100644 index b0c912feaa2..00000000000 --- a/arch/arm/dts/sama5d2-pinfunc.h +++ /dev/null @@ -1,880 +0,0 @@ -#define PINMUX_PIN(no, func, ioset) \ -(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) - -#define PIN_PA0 0 -#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) -#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) -#define PIN_PA1 1 -#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) -#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) -#define PIN_PA2 2 -#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) -#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) -#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) -#define PIN_PA3 3 -#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) -#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) -#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) -#define PIN_PA4 4 -#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) -#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) -#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) -#define PIN_PA5 5 -#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) -#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) -#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) -#define PIN_PA6 6 -#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) -#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) -#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) -#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) -#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) -#define PIN_PA7 7 -#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) -#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) -#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) -#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) -#define PIN_PA8 8 -#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) -#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) -#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) -#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) -#define PIN_PA9 9 -#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) -#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) -#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) -#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) -#define PIN_PA10 10 -#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) -#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) -#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) -#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) -#define PIN_PA11 11 -#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) -#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) -#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) -#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) -#define PIN_PA12 12 -#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) -#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) -#define PIN_PA13 13 -#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) -#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) -#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) -#define PIN_PA14 14 -#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) -#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) -#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) -#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) -#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) -#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) -#define PIN_PA15 15 -#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) -#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) -#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) -#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) -#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) -#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) -#define PIN_PA16 16 -#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) -#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) -#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) -#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) -#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) -#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) -#define PIN_PA17 17 -#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) -#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) -#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) -#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) -#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) -#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) -#define PIN_PA18 18 -#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) -#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) -#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) -#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) -#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) -#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) -#define PIN_PA19 19 -#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) -#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) -#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) -#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) -#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) -#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) -#define PIN_PA20 20 -#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) -#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) -#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) -#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) -#define PIN_PA21 21 -#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) -#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) -#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) -#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) -#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) -#define PIN_PA22 22 -#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) -#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) -#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) -#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) -#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) -#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) -#define PIN_PA23 23 -#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) -#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) -#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) -#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) -#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) -#define PIN_PA24 24 -#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) -#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) -#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) -#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) -#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) -#define PIN_PA25 25 -#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) -#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) -#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) -#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) -#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) -#define PIN_PA26 26 -#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) -#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) -#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) -#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) -#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) -#define PIN_PA27 27 -#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) -#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) -#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) -#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) -#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) -#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) -#define PIN_PA28 28 -#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) -#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) -#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) -#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) -#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) -#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) -#define PIN_PA29 29 -#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) -#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) -#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) -#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) -#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) -#define PIN_PA30 30 -#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) -#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) -#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) -#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) -#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) -#define PIN_PA31 31 -#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) -#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) -#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) -#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) -#define PIN_PB0 32 -#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) -#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) -#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) -#define PIN_PB1 33 -#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) -#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) -#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) -#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) -#define PIN_PB2 34 -#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) -#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) -#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) -#define PIN_PB3 35 -#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) -#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) -#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) -#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) -#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) -#define PIN_PB4 36 -#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) -#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) -#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) -#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) -#define PIN_PB5 37 -#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) -#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) -#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) -#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) -#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) -#define PIN_PB6 38 -#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) -#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) -#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) -#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) -#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) -#define PIN_PB7 39 -#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) -#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) -#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) -#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) -#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) -#define PIN_PB8 40 -#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) -#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) -#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) -#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) -#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) -#define PIN_PB9 41 -#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) -#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) -#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) -#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) -#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) -#define PIN_PB10 42 -#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) -#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) -#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) -#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) -#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) -#define PIN_PB11 43 -#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) -#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) -#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) -#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) -#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) -#define PIN_PB12 44 -#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) -#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) -#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) -#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) -#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) -#define PIN_PB13 45 -#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) -#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) -#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) -#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) -#define PIN_PB14 46 -#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) -#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) -#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) -#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) -#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) -#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) -#define PIN_PB15 47 -#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) -#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) -#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) -#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) -#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) -#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) -#define PIN_PB16 48 -#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) -#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) -#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) -#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) -#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) -#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) -#define PIN_PB17 49 -#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) -#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) -#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) -#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) -#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) -#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) -#define PIN_PB18 50 -#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) -#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) -#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) -#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) -#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) -#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) -#define PIN_PB19 51 -#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) -#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) -#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) -#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) -#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) -#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) -#define PIN_PB20 52 -#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) -#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) -#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) -#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) -#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) -#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) -#define PIN_PB21 53 -#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) -#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) -#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) -#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) -#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) -#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) -#define PIN_PB22 54 -#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) -#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__TDO PINMUX_PIN(PIN_PB22, 3, 1) -#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) -#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) -#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) -#define PIN_PB23 55 -#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) -#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) -#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) -#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) -#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) -#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) -#define PIN_PB24 56 -#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) -#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) -#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) -#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) -#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) -#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) -#define PIN_PB25 57 -#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) -#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) -#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) -#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) -#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) -#define PIN_PB26 58 -#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) -#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) -#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) -#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) -#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) -#define PIN_PB27 59 -#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) -#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) -#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) -#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) -#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) -#define PIN_PB28 60 -#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) -#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) -#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) -#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) -#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) -#define PIN_PB29 61 -#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) -#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) -#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) -#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) -#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) -#define PIN_PB30 62 -#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) -#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) -#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) -#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) -#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) -#define PIN_PB31 63 -#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) -#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) -#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) -#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) -#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) -#define PIN_PC0 64 -#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) -#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) -#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) -#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) -#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) -#define PIN_PC1 65 -#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) -#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) -#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) -#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) -#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) -#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) -#define PIN_PC2 66 -#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) -#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) -#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) -#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) -#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) -#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) -#define PIN_PC3 67 -#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) -#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) -#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) -#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) -#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) -#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) -#define PIN_PC4 68 -#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) -#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) -#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) -#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) -#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) -#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) -#define PIN_PC5 69 -#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) -#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) -#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) -#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) -#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) -#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) -#define PIN_PC6 70 -#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) -#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) -#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) -#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) -#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) -#define PIN_PC7 71 -#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) -#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) -#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) -#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) -#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) -#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) -#define PIN_PC8 72 -#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) -#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) -#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) -#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) -#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) -#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) -#define PIN_PC9 73 -#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) -#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) -#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 2, 1) -#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) -#define PIN_PC10 74 -#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) -#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) -#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) -#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) -#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) -#define PIN_PC11 75 -#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) -#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) -#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) -#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) -#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) -#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) -#define PIN_PC12 76 -#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) -#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) -#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) -#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) -#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) -#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) -#define PIN_PC13 77 -#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) -#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) -#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) -#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) -#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) -#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) -#define PIN_PC14 78 -#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) -#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) -#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) -#define PIN_PC14__TDO PINMUX_PIN(PIN_PC14, 5, 2) -#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) -#define PIN_PC15 79 -#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) -#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) -#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) -#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) -#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) -#define PIN_PC16 80 -#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) -#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) -#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) -#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) -#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) -#define PIN_PC17 81 -#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) -#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) -#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) -#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) -#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) -#define PIN_PC18 82 -#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) -#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) -#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) -#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) -#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) -#define PIN_PC19 83 -#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) -#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) -#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) -#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) -#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) -#define PIN_PC20 84 -#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) -#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) -#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) -#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) -#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) -#define PIN_PC21 85 -#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) -#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) -#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) -#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) -#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) -#define PIN_PC22 86 -#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) -#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) -#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) -#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) -#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) -#define PIN_PC23 87 -#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) -#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) -#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) -#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) -#define PIN_PC24 88 -#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) -#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) -#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) -#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) -#define PIN_PC25 89 -#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) -#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) -#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) -#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) -#define PIN_PC26 90 -#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) -#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) -#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) -#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) -#define PIN_PC27 91 -#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) -#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) -#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) -#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) -#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) -#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) -#define PIN_PC28 92 -#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) -#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) -#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) -#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) -#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) -#define PIN_PC29 93 -#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) -#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) -#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) -#define PIN_PC30 94 -#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) -#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) -#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) -#define PIN_PC31 95 -#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) -#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) -#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) -#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) -#define PIN_PD0 96 -#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) -#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) -#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) -#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) -#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) -#define PIN_PD1 97 -#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) -#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) -#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) -#define PIN_PD2 98 -#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) -#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) -#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) -#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) -#define PIN_PD3 99 -#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) -#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) -#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) -#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) -#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) -#define PIN_PD4 100 -#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) -#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) -#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) -#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) -#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) -#define PIN_PD5 101 -#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) -#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) -#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) -#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) -#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) -#define PIN_PD6 102 -#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) -#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) -#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) -#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) -#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) -#define PIN_PD7 103 -#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) -#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) -#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) -#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) -#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) -#define PIN_PD8 104 -#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) -#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) -#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) -#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) -#define PIN_PD9 105 -#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) -#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) -#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) -#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) -#define PIN_PD10 106 -#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) -#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) -#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) -#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) -#define PIN_PD11 107 -#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) -#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) -#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) -#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) -#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) -#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) -#define PIN_PD12 108 -#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) -#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) -#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) -#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) -#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) -#define PIN_PD13 109 -#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) -#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) -#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) -#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) -#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) -#define PIN_PD14 110 -#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) -#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) -#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) -#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) -#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) -#define PIN_PD15 111 -#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) -#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) -#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) -#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) -#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) -#define PIN_PD16 112 -#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) -#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) -#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) -#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) -#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) -#define PIN_PD17 113 -#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) -#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) -#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) -#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) -#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) -#define PIN_PD18 114 -#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) -#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) -#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) -#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) -#define PIN_PD19 115 -#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) -#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) -#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) -#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) -#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) -#define PIN_PD20 116 -#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) -#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) -#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) -#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) -#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) -#define PIN_PD21 117 -#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) -#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) -#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) -#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) -#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) -#define PIN_PD22 118 -#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) -#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) -#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) -#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) -#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) -#define PIN_PD23 119 -#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) -#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) -#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) -#define PIN_PD24 120 -#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD23, 3, 3) -#define PIN_PD25 121 -#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) -#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) -#define PIN_PD26 122 -#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) -#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) -#define PIN_PD27 123 -#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) -#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) -#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) -#define PIN_PD28 124 -#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) -#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) -#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) -#define PIN_PD29 125 -#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) -#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) -#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) -#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) -#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) -#define PIN_PD30 126 -#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) -#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) -#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) -#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) -#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) -#define PIN_PD31 127 -#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) -#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) -#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) -#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) -#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) diff --git a/arch/arm/dts/sama7g5-pinfunc.h b/arch/arm/dts/sama7g5-pinfunc.h deleted file mode 100644 index a17707ba60a..00000000000 --- a/arch/arm/dts/sama7g5-pinfunc.h +++ /dev/null @@ -1,923 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define PINMUX_PIN(no, func, ioset) \ -(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) - -#define PIN_PA0 0 -#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) -#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) -#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) -#define PIN_PA1 1 -#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) -#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) -#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) -#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) -#define PIN_PA2 2 -#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) -#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) -#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) -#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) -#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) -#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) -#define PIN_PA3 3 -#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) -#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) -#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) -#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) -#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) -#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) -#define PIN_PA4 4 -#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) -#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) -#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) -#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) -#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) -#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) -#define PIN_PA5 5 -#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) -#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) -#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) -#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) -#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) -#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) -#define PIN_PA6 6 -#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) -#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) -#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) -#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) -#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) -#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) -#define PIN_PA7 7 -#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) -#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) -#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) -#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) -#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) -#define PIN_PA8 8 -#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) -#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) -#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) -#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) -#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) -#define PIN_PA9 9 -#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) -#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) -#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) -#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) -#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) -#define PIN_PA10 10 -#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) -#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) -#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) -#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) -#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) -#define PIN_PA11 11 -#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) -#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) -#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) -#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) -#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) -#define PIN_PA12 12 -#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) -#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) -#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) -#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) -#define PIN_PA13 13 -#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) -#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) -#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) -#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) -#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) -#define PIN_PA14 14 -#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) -#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) -#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) -#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) -#define PIN_PA15 15 -#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) -#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) -#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) -#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) -#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) -#define PIN_PA16 16 -#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) -#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) -#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) -#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) -#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) -#define PIN_PA17 17 -#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) -#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) -#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) -#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) -#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) -#define PIN_PA18 18 -#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) -#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) -#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) -#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) -#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) -#define PIN_PA19 19 -#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) -#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) -#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) -#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) -#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) -#define PIN_PA20 20 -#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) -#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) -#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) -#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) -#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) -#define PIN_PA21 21 -#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) -#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) -#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) -#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) -#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) -#define PIN_PA22 22 -#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) -#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) -#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) -#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) -#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) -#define PIN_PA23 23 -#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) -#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) -#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) -#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) -#define PIN_PA24 24 -#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) -#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) -#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) -#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) -#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) -#define PIN_PA25 25 -#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) -#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) -#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) -#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) -#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) -#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) -#define PIN_PA26 26 -#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) -#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) -#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) -#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) -#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) -#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) -#define PIN_PA27 27 -#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) -#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) -#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) -#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) -#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) -#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) -#define PIN_PA28 28 -#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) -#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) -#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) -#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) -#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) -#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) -#define PIN_PA29 29 -#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) -#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) -#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) -#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) -#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) -#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) -#define PIN_PA30 30 -#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) -#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) -#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) -#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) -#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) -#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) -#define PIN_PA31 31 -#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) -#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) -#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) -#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) -#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) -#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) -#define PIN_PB0 32 -#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) -#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) -#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) -#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) -#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) -#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) -#define PIN_PB1 33 -#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) -#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) -#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) -#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) -#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) -#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) -#define PIN_PB2 34 -#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) -#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) -#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) -#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) -#define PIN_PB2__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB2, 6, 3) -#define PIN_PB3 35 -#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) -#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) -#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) -#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) -#define PIN_PB4 36 -#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) -#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) -#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) -#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) -#define PIN_PB5 37 -#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) -#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) -#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) -#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) -#define PIN_PB6 38 -#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) -#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) -#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) -#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) -#define PIN_PB7 39 -#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) -#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) -#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) -#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) -#define PIN_PB8 40 -#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) -#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) -#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) -#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) -#define PIN_PB9 41 -#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) -#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) -#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) -#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) -#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) -#define PIN_PB10 42 -#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) -#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) -#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) -#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) -#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) -#define PIN_PB11 43 -#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) -#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) -#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) -#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) -#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) -#define PIN_PB12 44 -#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) -#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) -#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) -#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) -#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) -#define PIN_PB13 45 -#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) -#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) -#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) -#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) -#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) -#define PIN_PB14 46 -#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) -#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) -#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) -#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) -#define PIN_PB15 47 -#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) -#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) -#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) -#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) -#define PIN_PB16 48 -#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) -#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) -#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) -#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) -#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) -#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) -#define PIN_PB17 49 -#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) -#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) -#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) -#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) -#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) -#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) -#define PIN_PB18 50 -#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) -#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) -#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) -#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) -#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) -#define PIN_PB19 51 -#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) -#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) -#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) -#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) -#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) -#define PIN_PB20 52 -#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) -#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) -#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) -#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) -#define PIN_PB21 53 -#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) -#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) -#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) -#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) -#define PIN_PB22 54 -#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) -#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) -#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) -#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) -#define PIN_PB23 55 -#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) -#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) -#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) -#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) -#define PIN_PB24 56 -#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) -#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) -#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) -#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) -#define PIN_PB25 57 -#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) -#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) -#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) -#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) -#define PIN_PB26 58 -#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) -#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) -#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) -#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) -#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) -#define PIN_PB27 59 -#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) -#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) -#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) -#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) -#define PIN_PB28 60 -#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) -#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) -#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) -#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) -#define PIN_PB29 61 -#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) -#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) -#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) -#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) -#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) -#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) -#define PIN_PB30 62 -#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) -#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) -#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) -#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) -#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) -#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) -#define PIN_PB31 63 -#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) -#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) -#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) -#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) -#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) -#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) -#define PIN_PC0 64 -#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) -#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) -#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) -#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) -#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) -#define PIN_PC1 65 -#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) -#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) -#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) -#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) -#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) -#define PIN_PC2 66 -#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) -#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) -#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) -#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) -#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) -#define PIN_PC3 67 -#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) -#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) -#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) -#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) -#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) -#define PIN_PC4 68 -#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) -#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) -#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) -#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) -#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) -#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) -#define PIN_PC5 69 -#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) -#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) -#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) -#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) -#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) -#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) -#define PIN_PC6 70 -#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) -#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) -#define PIN_PC7 71 -#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) -#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) -#define PIN_PC8 72 -#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) -#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) -#define PIN_PC9 73 -#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) -#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) -#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) -#define PIN_PC10 74 -#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) -#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) -#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) -#define PIN_PC11 75 -#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) -#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) -#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) -#define PIN_PC12 76 -#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) -#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) -#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) -#define PIN_PC13 77 -#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) -#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) -#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) -#define PIN_PC14 78 -#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) -#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) -#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) -#define PIN_PC15 79 -#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) -#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) -#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) -#define PIN_PC16 80 -#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -#define PIN_PC16__I2SMCC_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) -#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) -#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) -#define PIN_PC17 81 -#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) -#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) -#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) -#define PIN_PC18 82 -#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) -#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) -#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) -#define PIN_PC19 83 -#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) -#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) -#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) -#define PIN_PC20 84 -#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) -#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) -#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) -#define PIN_PC21 85 -#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) -#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) -#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) -#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) -#define PIN_PC22 86 -#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) -#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) -#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) -#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) -#define PIN_PC23 87 -#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) -#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) -#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) -#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) -#define PIN_PC24 88 -#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) -#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) -#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) -#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) -#define PIN_PC25 89 -#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) -#define PIN_PC26 90 -#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) -#define PIN_PC27 91 -#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) -#define PIN_PC28 92 -#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) -#define PIN_PC29 93 -#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) -#define PIN_PC30 94 -#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) -#define PIN_PC31 95 -#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) -#define PIN_PD0 96 -#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) -#define PIN_PD1 97 -#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) -#define PIN_PD2 98 -#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) -#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) -#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) -#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) -#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) -#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) -#define PIN_PD3 99 -#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) -#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) -#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) -#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) -#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) -#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) -#define PIN_PD4 100 -#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) -#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) -#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) -#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) -#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) -#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) -#define PIN_PD5 101 -#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) -#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) -#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) -#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) -#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) -#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) -#define PIN_PD6 102 -#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) -#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) -#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) -#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) -#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) -#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) -#define PIN_PD7 103 -#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) -#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) -#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) -#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) -#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) -#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) -#define PIN_PD8 104 -#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) -#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__A22_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) -#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) -#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) -#define PIN_PD9 105 -#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) -#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) -#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) -#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) -#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) -#define PIN_PD10 106 -#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) -#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) -#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) -#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) -#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) -#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) -#define PIN_PD11 107 -#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) -#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) -#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) -#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) -#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) -#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) -#define PIN_PD12 108 -#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) -#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) -#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) -#define PIN_PD13 109 -#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) -#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) -#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) -#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) -#define PIN_PD14 110 -#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) -#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) -#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) -#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) -#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) -#define PIN_PD15 111 -#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) -#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) -#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) -#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) -#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) -#define PIN_PD16 112 -#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) -#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) -#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) -#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) -#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) -#define PIN_PD17 113 -#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) -#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) -#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) -#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) -#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) -#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) -#define PIN_PD18 114 -#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) -#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) -#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) -#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) -#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) -#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) -#define PIN_PD19 115 -#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) -#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) -#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) -#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) -#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) -#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) -#define PIN_PD20 116 -#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) -#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) -#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 4, 2) -#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) -#define PIN_PD21 117 -#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) -#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) -#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) -#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) -#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) -#define PIN_PD22 118 -#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) -#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) -#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) -#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) -#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) -#define PIN_PD23 119 -#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) -#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) -#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) -#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) -#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) -#define PIN_PD24 120 -#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) -#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) -#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) -#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) -#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) -#define PIN_PD25 121 -#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) -#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) -#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) -#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) -#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) -#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) -#define PIN_PD26 122 -#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) -#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) -#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) -#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) -#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) -#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) -#define PIN_PD27 123 -#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) -#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) -#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) -#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) -#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) -#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) -#define PIN_PD28 124 -#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) -#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) -#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) -#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) -#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) -#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) -#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) -#define PIN_PD29 125 -#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) -#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) -#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) -#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) -#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) -#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) -#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) -#define PIN_PD30 126 -#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) -#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) -#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) -#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) -#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) -#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) -#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) -#define PIN_PD31 127 -#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) -#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) -#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) -#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) -#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) -#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) -#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) -#define PIN_PE0 128 -#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) -#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) -#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) -#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) -#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) -#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) -#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) -#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) -#define PIN_PE1 129 -#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) -#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) -#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) -#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) -#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) -#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) -#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) -#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) -#define PIN_PE2 130 -#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) -#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) -#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) -#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) -#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) -#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) -#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) -#define PIN_PE3 131 -#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) -#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) -#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) -#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) -#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) -#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) -#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) -#define PIN_PE4 132 -#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) -#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) -#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) -#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) -#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) -#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) -#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) -#define PIN_PE5 133 -#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) -#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) -#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) -#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) -#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) -#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) -#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) -#define PIN_PE6 134 -#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) -#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) -#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) -#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) -#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) -#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) -#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) -#define PIN_PE7 135 -#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) -#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) -#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) -#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) -#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) -#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) diff --git a/arch/arm/dts/stm32h747i-disco-u-boot.dtsi b/arch/arm/dts/stm32h747i-disco-u-boot.dtsi new file mode 100644 index 00000000000..ff297cc91fa --- /dev/null +++ b/arch/arm/dts/stm32h747i-disco-u-boot.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + */ + +#include + +&fmc { + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * first bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@1 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; +}; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + ; + + slew-rate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp25-u-boot.dtsi b/arch/arm/dts/stm32mp25-u-boot.dtsi index 0c8e95b3416..d9aeeb6d510 100644 --- a/arch/arm/dts/stm32mp25-u-boot.dtsi +++ b/arch/arm/dts/stm32mp25-u-boot.dtsi @@ -25,6 +25,10 @@ optee { bootph-all; }; + + scmi { + bootph-all; + }; }; /* need PSCI for sysreset during board_f */ @@ -93,6 +97,10 @@ bootph-all; }; +&rcc { + bootph-all; +}; + &rifsc { bootph-all; }; diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi index d778b8d8d05..9a566e18d3f 100644 --- a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -10,84 +10,10 @@ u-boot,boot-led = "led-blue"; u-boot,mmc-env-partition = "u-boot-env"; }; - - clocks { - ck_flexgen_08: ck-flexgen-08 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - ck_flexgen_51: ck-flexgen-51 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_ls_mcu: ck-icn-ls-mcu { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; -}; - -&gpioa { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpiob { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpioc { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpiod { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpioe { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpiof { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpiog { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpioh { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpioi { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpioj { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpiok { - clocks = <&ck_icn_ls_mcu>; -}; - -&gpioz { - clocks = <&ck_icn_ls_mcu>; -}; - -&sdmmc1 { - clocks = <&ck_flexgen_51>; - /delete-property/resets; }; &usart2 { bootph-all; - clocks = <&ck_flexgen_08>; }; &usart2_pins_a { diff --git a/arch/arm/dts/vf610-pcm052.dtsi b/arch/arm/dts/vf610-pcm052.dtsi index ccdc0f57e2b..2b82b7313dd 100644 --- a/arch/arm/dts/vf610-pcm052.dtsi +++ b/arch/arm/dts/vf610-pcm052.dtsi @@ -244,7 +244,7 @@ qflash0: spi_flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <108000000>; reg = <0>; }; @@ -252,7 +252,7 @@ qflash1: spi_flash@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <66000000>; reg = <1>; }; diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h deleted file mode 100644 index 6775e4e3371..00000000000 --- a/arch/arm/dts/vf610-pinfunc.h +++ /dev/null @@ -1,855 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DTS_VF610_PINFUNC_H -#define __DTS_VF610_PINFUNC_H - -/* - * The pin function ID for VF610 is a tuple of: - * - */ - -#define ALT0 0x0 -#define ALT1 0x1 -#define ALT2 0x2 -#define ALT3 0x3 -#define ALT4 0x4 -#define ALT5 0x5 -#define ALT6 0x6 -#define ALT7 0x7 - -#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 -#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 -#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 -#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 -#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 -#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 -#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 -#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 -#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 -#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 -#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 -#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 -#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 -#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 -#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 -#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 -#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 -#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 -#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 -#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 -#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 -#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 -#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 -#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 -#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 -#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 -#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 -#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 -#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 -#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 -#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 -#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 -#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 -#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 -#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 -#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 -#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 -#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 -#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 -#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 -#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 -#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 -#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 -#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 -#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 -#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 -#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 -#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 -#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 -#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 -#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 -#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 -#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 -#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 -#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 -#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 -#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 -#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 -#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 -#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 -#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 -#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 -#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 -#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 -#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 -#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 -#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 -#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 -#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 -#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 -#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 -#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 -#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 -#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 -#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 -#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 -#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 -#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 -#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 -#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 -#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 -#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 -#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 -#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 -#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 -#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 -#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 -#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 -#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 -#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 -#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 -#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 -#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 -#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 -#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 -#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 -#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 -#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 -#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 -#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 -#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 -#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 -#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 -#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 -#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 -#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 -#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 -#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 -#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 -#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 -#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 -#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 -#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 -#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 -#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 -#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 -#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 -#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 -#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 -#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 -#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 -#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 -#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 -#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 -#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 -#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 -#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 -#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 -#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 -#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 -#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 -#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 -#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 -#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 -#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 -#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 -#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 -#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 -#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 -#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 -#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 -#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 -#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 -#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 -#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 -#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 -#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 -#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 -#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 -#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 -#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 -#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 -#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 -#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 -#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 -#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 -#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 -#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 -#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 -#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 -#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 -#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 -#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 -#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 -#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 -#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 -#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 -#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 -#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 -#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 -#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 -#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 -#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 -#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 -#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 -#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 -#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 -#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 -#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 -#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 -#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 -#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 -#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 -#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 -#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 -#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 -#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 -#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 -#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 -#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 -#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 -#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 -#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 -#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 -#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 -#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 -#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 -#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 -#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 -#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 -#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 -#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 -#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 -#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 -#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 -#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 -#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 -#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 -#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 -#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 -#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 -#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 -#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 -#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 -#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 -#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 -#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 -#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 -#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 -#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 -#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 -#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 -#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 -#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 -#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 -#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 -#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 -#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 -#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 -#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 -#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 -#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 -#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 -#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 -#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 -#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 -#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 -#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 -#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 -#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 -#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 -#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 -#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 -#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 -#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 -#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 -#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 -#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 -#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 -#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 -#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 -#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 -#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 -#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 -#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 -#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 -#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 -#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 -#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 -#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 -#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 -#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 -#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 -#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 -#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 -#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 -#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 -#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 -#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 -#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 -#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 -#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 -#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 -#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 -#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 -#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 -#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 -#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 -#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 -#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 -#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 -#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 -#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 -#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 -#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 -#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 -#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 -#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 -#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 -#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 -#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 -#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 -#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 -#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 -#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 -#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 -#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 -#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 -#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 -#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 -#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 -#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 -#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 -#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 -#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 -#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 -#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 -#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 -#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 -#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 -#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 -#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 -#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 -#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 -#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 -#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 -#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 -#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 -#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 -#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 -#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 -#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 -#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 -#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 -#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 -#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 -#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 -#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 -#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 -#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 -#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 -#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 -#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 -#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 -#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 -#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 -#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 -#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 -#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 -#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 -#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 -#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 -#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 -#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0 -#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 -#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 -#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 -#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 -#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 -#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 -#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 -#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 -#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 -#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 -#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 -#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 -#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 -#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 -#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 -#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 -#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 -#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 -#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 -#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 -#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 -#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 -#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 -#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 -#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 -#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 -#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 -#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 -#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 -#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 -#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 -#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 -#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 -#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 -#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 -#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 -#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 -#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 -#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 -#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 -#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 -#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 -#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 -#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 -#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 -#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 -#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 -#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 -#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 -#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 -#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 -#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 -#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 -#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 -#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 -#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 -#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 -#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 -#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 -#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 -#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 -#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 -#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 -#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 -#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 -#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 -#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 -#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 -#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 -#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 -#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 -#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 -#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 -#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 -#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 -#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 -#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 -#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 -#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 -#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 -#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 -#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 -#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 -#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 -#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 -#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 -#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 -#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 -#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 -#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 -#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 -#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 -#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 -#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 -#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 -#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 -#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 -#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 -#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 -#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 -#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 -#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 -#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 -#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 -#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 -#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 -#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 -#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 -#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 -#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 -#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 -#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 -#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 -#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 -#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 -#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 -#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 -#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 -#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 -#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 -#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 -#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 -#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 -#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 -#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 -#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 -#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 -#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 -#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 -#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 -#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 -#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 -#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 -#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 -#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 -#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 -#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 -#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 -#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 -#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 -#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 -#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 -#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 -#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 -#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 -#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 -#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 -#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 -#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 -#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 -#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 -#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 -#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 -#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 -#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 -#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 -#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 -#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 -#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 -#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 -#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 -#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 -#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 -#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 -#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 -#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 -#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 -#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 -#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 -#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 -#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 -#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 -#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 -#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 -#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 -#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 -#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 -#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 -#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 -#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 -#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 -#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 -#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 -#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 -#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 -#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 -#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 -#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 -#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 -#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 -#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 -#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 -#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 -#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 -#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 -#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 -#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 -#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 -#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 -#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 -#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 -#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 -#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 -#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 -#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 -#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 -#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 -#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 -#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 -#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 -#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 -#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 -#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 -#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 -#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 -#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 -#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 -#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 -#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 -#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 -#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 -#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 -#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 -#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 -#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 -#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 -#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 -#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 -#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 -#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 -#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 -#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 -#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 -#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 -#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 -#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 -#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 -#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 -#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 -#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 -#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 -#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 -#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 -#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 -#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 -#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 -#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 -#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 -#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 -#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 -#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 -#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 -#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 -#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 -#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 -#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 -#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 -#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 -#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 -#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 -#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 -#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 -#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 -#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 -#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 -#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 -#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 -#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 -#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 -#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 -#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 -#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 -#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 -#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 -#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 -#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 -#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 -#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 -#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 -#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 -#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 -#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 -#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 -#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 -#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 -#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 -#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 -#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 -#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 -#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 -#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 -#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 -#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 -#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 -#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 -#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 -#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 -#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 -#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 -#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 -#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 -#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 -#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 -#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 -#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 -#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 -#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 -#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 -#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 -#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 -#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 -#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 -#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 -#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 -#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 -#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 -#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 -#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 -#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 -#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 -#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 -#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 -#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 -#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 -#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 -#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 -#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 -#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 -#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 -#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 -#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 -#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 -#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 -#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 -#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 -#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 -#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 -#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 -#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 -#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 -#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 -#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 -#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 -#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 -#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 -#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 -#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 -#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 -#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 -#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 -#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 -#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 -#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 -#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 -#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 -#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 -#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 -#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 -#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 -#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 -#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 -#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 -#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 -#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 -#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 -#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 -#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 -#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 -#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 -#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 -#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 -#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 -#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 -#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 -#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 -#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 -#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 -#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 -#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 -#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 -#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 -#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 -#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 -#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 -#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 -#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 -#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 -#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 -#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 -#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 -#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 -#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 -#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 -#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 -#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 -#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 -#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 -#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 -#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 -#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 -#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 -#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 -#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 -#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 -#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 -#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 -#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 -#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 -#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 -#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 -#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 -#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 -#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 -#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 -#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 -#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 -#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 -#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 -#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 -#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 -#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 -#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 -#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 -#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 -#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 -#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 -#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 -#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 -#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 -#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 -#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 -#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 -#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 -#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 -#define VF610_PAD_DDR_RESETB 0x21c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A15__DDR_A_15 0x220 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A14__DDR_A_14 0x224 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A13__DDR_A_13 0x228 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A12__DDR_A_12 0x22c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A11__DDR_A_11 0x230 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A10__DDR_A_10 0x234 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A9__DDR_A_9 0x238 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A8__DDR_A_8 0x23c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A7__DDR_A_7 0x240 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A6__DDR_A_6 0x244 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A5__DDR_A_5 0x248 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A4__DDR_A_4 0x24c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A3__DDR_A_3 0x250 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A2__DDR_A_2 0x254 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A1__DDR_A_1 0x258 0x000 ALT0 0x0 -#define VF610_PAD_DDR_A0__DDR_A_0 0x25c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_BA2__DDR_BA_2 0x260 0x000 ALT0 0x0 -#define VF610_PAD_DDR_BA1__DDR_BA_1 0x264 0x000 ALT0 0x0 -#define VF610_PAD_DDR_BA0__DDR_BA_0 0x268 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CAS__DDR_CAS_B 0x26c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CKE__DDR_CKE_0 0x270 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CLK__DDR_CLK_0 0x274 0x000 ALT0 0x0 -#define VF610_PAD_DDR_CS__DDR_CS_B_0 0x278 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D15__DDR_D_15 0x27c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D14__DDR_D_14 0x280 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D13__DDR_D_13 0x284 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D12__DDR_D_12 0x288 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D11__DDR_D_11 0x28c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D10__DDR_D_10 0x290 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D9__DDR_D_9 0x294 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D8__DDR_D_8 0x298 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D7__DDR_D_7 0x29c 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D6__DDR_D_6 0x2a0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D5__DDR_D_5 0x2a4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D4__DDR_D_4 0x2a8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D3__DDR_D_3 0x2ac 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D2__DDR_D_2 0x2b0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D1__DDR_D_1 0x2b4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_D0__DDR_D_0 0x2b8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQM1__DDR_DQM_1 0x2bc 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQM0__DDR_DQM_0 0x2c0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQS1__DDR_DQS_1 0x2c4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DQS0__DDR_DQS_0 0x2c8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_RAS__DDR_RAS_B 0x2cc 0x000 ALT0 0x0 -#define VF610_PAD_DDR_WE__DDR_WE_B 0x2d0 0x000 ALT0 0x0 -#define VF610_PAD_DDR_ODT1__DDR_ODT_0 0x2d4 0x000 ALT0 0x0 -#define VF610_PAD_DDR_ODT0__DDR_ODT_1 0x2d8 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 0x2dc 0x000 ALT0 0x0 -#define VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 0x2e0 0x000 ALT0 0x0 - -#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 306f797f7a8..86d295c1a8d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -241,7 +241,7 @@ #define DCFG_RCWSR15 0x138 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 -#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_BASE 0x700100000ULL #define DCFG_DCSR_PORCR1 0x000 /* Interrupt Sampling Control */ diff --git a/arch/arm/include/asm/arch-imxrt/gpio.h b/arch/arm/include/asm/arch-imxrt/gpio.h index da31a7438aa..be130e00652 100644 --- a/arch/arm/include/asm/arch-imxrt/gpio.h +++ b/arch/arm/include/asm/arch-imxrt/gpio.h @@ -7,13 +7,6 @@ #ifndef __ASM_ARCH_GPIO_H__ #define __ASM_ARCH_GPIO_H__ -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; /* data */ - u32 gpio_dir; /* direction */ - u32 gpio_psr; /* pad satus */ -}; -#endif +#include #endif /* __ASM_ARCH_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 01b14d73dc9..699c951b1b9 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -31,10 +31,10 @@ enum { MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), - MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0), - MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0), - MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0), - MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0), + MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0), MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h index 504459bd93d..408fdd66635 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_px30.h +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -299,9 +299,9 @@ enum { /* CRU_CLK_SEL30_CON */ CLK_I2S1_DIV_CON_MASK = 0x7f, - CLK_I2S1_PLL_SEL_MASK = 0X1 << 8, - CLK_I2S1_PLL_SEL_GPLL = 0X0 << 8, - CLK_I2S1_PLL_SEL_NPLL = 0X1 << 8, + CLK_I2S1_PLL_SEL_MASK = 0x1 << 8, + CLK_I2S1_PLL_SEL_GPLL = 0x0 << 8, + CLK_I2S1_PLL_SEL_NPLL = 0x1 << 8, CLK_I2S1_SEL_MASK = 0x3 << 10, CLK_I2S1_SEL_I2S1 = 0x0 << 10, CLK_I2S1_SEL_FRAC = 0x1 << 10, diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h index e9c7f793391..9abb3b16c42 100644 --- a/arch/arm/include/asm/arch-rockchip/f_rockusb.h +++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h @@ -65,7 +65,7 @@ K_FW_SPI_READ_10 = 0x21, K_FW_SPI_WRITE_10 = 0x22, K_FW_LBA_ERASE_10 = 0x25, -K_FW_SESSION = 0X30, +K_FW_SESSION = 0x30, K_FW_RESET = 0xff, }; diff --git a/arch/arm/include/asm/arch-rockchip/sdram_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_px30.h index 2ab8e97ae1d..bf0cd01e7cc 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_px30.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_px30.h @@ -20,7 +20,7 @@ /* DDR GRF */ #define DDR_GRF_CON(n) (0 + (n) * 4) -#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS_BASE (0x100) #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) #define DDR_GRF_LP_CON (0x20) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h index 10923505d6e..454f9ca8878 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h @@ -32,7 +32,7 @@ /* DDR GRF */ #define DDR_GRF_CON(n) (0 + (n) * 4) -#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS_BASE (0x100) #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) /* CRU_SOFTRESET_CON5 */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h index 6a07436059c..9b65bad2581 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h @@ -185,7 +185,7 @@ /* DDR GRF */ #define DDR_GRF_CON(n) (0 + (n) * 4) -#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS_BASE (0x100) #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) #define DDR_GRF_LP_CON (0x20) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index ccacc99d018..575dff68804 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -90,6 +90,13 @@ #define CCM_PLL6_DEFAULT 0xe8216300 #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 #define CCM_APB1_DEFAULT 0x03000102 + +#elif CONFIG_MACH_SUN50I_A133 /* A133 */ + +#define CCM_PLL6_DEFAULT 0xb8003100 +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 +#define CCM_AHB3_DEFAULT 0x03000002 +#define CCM_APB1_DEFAULT 0x03000102 #endif /* apb2 bit field */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 8a3f465545a..2a9b086991c 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -29,6 +29,10 @@ #define SUNXI_DRAM_COM_BASE 0x047FA000 #define SUNXI_DRAM_CTL0_BASE 0x047FB000 #define SUNXI_DRAM_PHY0_BASE 0x04800000 +#elif CONFIG_MACH_SUN50I_A133 +#define SUNXI_DRAM_COM_BASE 0x04810000 +#define SUNXI_DRAM_CTL0_BASE 0x04820000 +#define SUNXI_DRAM_PHY0_BASE 0x04830000 #endif #define SUNXI_TWI0_BASE 0x05002000 diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 9d21b492418..0708ae3ee3b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -31,6 +31,8 @@ #include #elif defined(CONFIG_MACH_SUN50I_H616) #include +#elif defined(CONFIG_DRAM_SUN50I_A133) +#include #elif defined(CONFIG_MACH_SUNIV) #include #else diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h new file mode 100644 index 00000000000..a5fc6ad3656 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * A133 dram controller register and constant defines + * + * (C) Copyright 2024 MasterR3C0RD + */ + +#ifndef _SUNXI_DRAM_SUN50I_A133_H +#define _SUNXI_DRAM_SUN50I_A133_H + +#include + +enum sunxi_dram_type { + SUNXI_DRAM_TYPE_DDR3 = 3, + SUNXI_DRAM_TYPE_DDR4, + SUNXI_DRAM_TYPE_LPDDR3 = 7, + SUNXI_DRAM_TYPE_LPDDR4 +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +/* MBUS part is largely the same as in H6, except for one special register */ +#define MCTL_COM_UNK_008 0x008 +/* NOTE: This register has the same importance as mctl_ctl->clken in H616 */ +#define MCTL_COM_MAER0 0x020 + +/* + * Controller registers seems to be the same or at least very similar + * to those in H6. + */ +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x000 */ + u32 statr; /* 0x004 unused */ + u32 mstr1; /* 0x008 unused */ + u32 clken; /* 0x00c */ + u32 mrctrl0; /* 0x010 unused */ + u32 mrctrl1; /* 0x014 unused */ + u32 mrstatr; /* 0x018 unused */ + u32 mrctrl2; /* 0x01c unused */ + u32 derateen; /* 0x020 unused */ + u32 derateint; /* 0x024 unused */ + u8 reserved_0x028[8]; /* 0x028 */ + u32 pwrctl; /* 0x030 unused */ + u32 pwrtmg; /* 0x034 unused */ + u32 hwlpctl; /* 0x038 unused */ + u8 reserved_0x03c[20]; /* 0x03c */ + u32 rfshctl0; /* 0x050 unused */ + u32 rfshctl1; /* 0x054 unused */ + u8 reserved_0x058[8]; /* 0x05c */ + u32 rfshctl3; /* 0x060 */ + u32 rfshtmg; /* 0x064 */ + u8 reserved_0x068[104]; /* 0x068 */ + u32 init[8]; /* 0x0d0 */ + u32 dimmctl; /* 0x0f0 unused */ + u32 rankctl; /* 0x0f4 */ + u8 reserved_0x0f8[8]; /* 0x0f8 */ + u32 dramtmg[17]; /* 0x100 */ + u8 reserved_0x144[60]; /* 0x144 */ + u32 zqctl[3]; /* 0x180 */ + u32 zqstat; /* 0x18c unused */ + u32 dfitmg0; /* 0x190 */ + u32 dfitmg1; /* 0x194 */ + u32 dfilpcfg[2]; /* 0x198 unused */ + u32 dfiupd[3]; /* 0x1a0 */ + u32 reserved_0x1ac; /* 0x1ac */ + u32 dfimisc; /* 0x1b0 */ + u32 dfitmg2; /* 0x1b4 unused */ + u32 dfitmg3; /* 0x1b8 unused */ + u32 dfistat; /* 0x1bc */ + u32 dbictl; /* 0x1c0 */ + u8 reserved_0x1c4[60]; /* 0x1c4 */ + u32 addrmap[12]; /* 0x200 */ + u8 reserved_0x230[16]; /* 0x230 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 reserved_0x248[8]; /* 0x248 */ + u32 sched[2]; /* 0x250 */ + u8 reserved_0x258[180]; /* 0x258 */ + u32 dbgcmd; /* 0x30c unused */ + u32 dbgstat; /* 0x310 unused */ + u8 reserved_0x314[12]; /* 0x314 */ + u32 swctl; /* 0x320 */ + u32 swstat; /* 0x324 */ + u8 reserved_0x328[7768]; /* 0x328 */ + u32 unk_0x2180; /* 0x2180 */ + u8 reserved_0x2184[188]; /* 0x2184 */ + u32 unk_0x2240; /* 0x2240 */ + u8 reserved_0x2244[3900]; /* 0x2244 */ + u32 unk_0x3180; /* 0x3180 */ + u8 reserved_0x3184[188]; /* 0x3184 */ + u32 unk_0x3240; /* 0x3240 */ + u8 reserved_0x3244[3900]; /* 0x3244 */ + u32 unk_0x4180; /* 0x4180 */ + u8 reserved_0x4184[188]; /* 0x4184 */ + u32 unk_0x4240; /* 0x4240 */ +}; + +check_member(sunxi_mctl_ctl_reg, swstat, 0x324); +check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240); + +#define MSTR_DEVICETYPE_DDR3 BIT(0) +#define MSTR_DEVICETYPE_LPDDR2 BIT(2) +#define MSTR_DEVICETYPE_LPDDR3 BIT(3) +#define MSTR_DEVICETYPE_DDR4 BIT(4) +#define MSTR_DEVICETYPE_LPDDR4 BIT(5) +#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) +#define MSTR_GEARDOWNMODE BIT(0) /* Same as MSTR_DEVICETYPE_DDR3, only used for DDR4 */ +#define MSTR_2TMODE BIT(10) +#define MSTR_BUSWIDTH_FULL (0 << 12) +#define MSTR_BUSWIDTH_HALF (1 << 12) +#define MSTR_ACTIVE_RANKS(x) (((x == 1) ? 3 : 1) << 24) +#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) +#define MSTR_DEVICECONFIG_X32 (3 << 30) + +#define TPR10_CA_BIT_DELAY BIT(16) +#define TPR10_DX_BIT_DELAY0 BIT(17) +#define TPR10_DX_BIT_DELAY1 BIT(18) +#define TPR10_WRITE_LEVELING BIT(20) +#define TPR10_READ_CALIBRATION BIT(21) +#define TPR10_READ_TRAINING BIT(22) +#define TPR10_WRITE_TRAINING BIT(23) + +/* MRCTRL constants */ +#define MRCTRL0_MR_RANKS_ALL (3 << 4) +#define MRCTRL0_MR_ADDR(x) (x << 12) +#define MRCTRL0_MR_WR BIT(31) + +#define MRCTRL1_MR_ADDR(x) (x << 8) +#define MRCTRL1_MR_DATA(x) (x) + +/* ADDRMAP constants */ +#define ADDRMAP_DISABLED_3F_B(b) (0x3f + b) +#define ADDRMAP_DISABLED_1F_B(b) (0x1f + b) +#define ADDRMAP_DISABLED_0F_B(b) (0x0f + b) + +#define _ADDRMAP_VALUE(a,x,b) (((a) - b) << (x * 8)) + +/* + * Bx = internal base + * The selected HIF address bit for each address bit is determined + * by adding the internal base to the value of each field + * */ + +#define ADDRMAP0_CS0_B6(v) _ADDRMAP_VALUE(v, 0, 6) + +#define ADDRMAP1_BANK0_B2(v) _ADDRMAP_VALUE(v, 0, 2) +#define ADDRMAP1_BANK1_B3(v) _ADDRMAP_VALUE(v, 1, 3) +#define ADDRMAP1_BANK2_B4(v) _ADDRMAP_VALUE(v, 2, 4) + +#define ADDRMAP2_COL2_B2(v) _ADDRMAP_VALUE(v, 0, 2) +#define ADDRMAP2_COL3_B3(v) _ADDRMAP_VALUE(v, 1, 3) +#define ADDRMAP2_COL4_B4(v) _ADDRMAP_VALUE(v, 2, 4) +#define ADDRMAP2_COL5_B5(v) _ADDRMAP_VALUE(v, 3, 5) + +#define ADDRMAP3_COL6_B6(v) _ADDRMAP_VALUE(v, 0, 6) +#define ADDRMAP3_COL7_B7(v) _ADDRMAP_VALUE(v, 1, 7) +#define ADDRMAP3_COL8_B8(v) _ADDRMAP_VALUE(v, 2, 8) +#define ADDRMAP3_COL9_B9(v) _ADDRMAP_VALUE(v, 3, 9) + +#define ADDRMAP4_COL10_B10(v) _ADDRMAP_VALUE(v, 0, 10) +#define ADDRMAP4_COL11_B11(v) _ADDRMAP_VALUE(v, 1, 11) + +#define ADDRMAP5_ROW0_B6(v) _ADDRMAP_VALUE(v, 0, 6) +#define ADDRMAP5_ROW1_B7(v) _ADDRMAP_VALUE(v, 1, 7) +#define ADDRMAP5_ROW2_10_B8(v) _ADDRMAP_VALUE(v, 2, 8) +#define ADDRMAP5_ROW11_B17(v) _ADDRMAP_VALUE(v, 3, 17) + +#define ADDRMAP6_ROW12_B18(v) _ADDRMAP_VALUE(v, 0, 18) +#define ADDRMAP6_ROW13_B19(v) _ADDRMAP_VALUE(v, 1, 19) +#define ADDRMAP6_ROW14_B20(v) _ADDRMAP_VALUE(v, 2, 20) +#define ADDRMAP6_ROW15_B21(v) _ADDRMAP_VALUE(v, 3, 21) + +#define ADDRMAP7_ROW16_B22(v) _ADDRMAP_VALUE(v, 0, 22) +#define ADDRMAP7_ROW17_B23(v) _ADDRMAP_VALUE(v, 1, 23) + +#define ADDRMAP8_BG0_B2(v) _ADDRMAP_VALUE(v, 0, 2) +#define ADDRMAP8_BG1_B3(v) _ADDRMAP_VALUE(v, 1, 3) + +/* These are only used if ADDRMAP5_ROW_BITS_2_10 = ADDRMAP_DISABLED_0F */ +#define ADDRMAP9_ROW2_B8(v) _ADDRMAP_VALUE(v, 0, 8) +#define ADDRMAP9_ROW3_B9(v) _ADDRMAP_VALUE(v, 1, 9) +#define ADDRMAP9_ROW4_B10(v) _ADDRMAP_VALUE(v, 2, 10) +#define ADDRMAP9_ROW5_B11(v) _ADDRMAP_VALUE(v, 3, 11) + +#define ADDRMAP10_ROW6_B12(v) _ADDRMAP_VALUE(v, 0, 12) +#define ADDRMAP10_ROW7_B13(v) _ADDRMAP_VALUE(v, 1, 13) +#define ADDRMAP10_ROW8_B14(v) _ADDRMAP_VALUE(v, 2, 14) +#define ADDRMAP10_ROW9_B15(v) _ADDRMAP_VALUE(v, 3, 15) + +#define ADDRMAP11_ROW10_B16(v) _ADDRMAP_VALUE(v, 0, 16) + +struct dram_para { + uint32_t clk; + enum sunxi_dram_type type; + uint32_t dx_odt; + uint32_t dx_dri; + uint32_t ca_dri; + uint32_t para0; + uint32_t mr11; + uint32_t mr12; + uint32_t mr13; + uint32_t mr14; + uint32_t tpr1; + uint32_t tpr2; + uint32_t tpr3; + uint32_t tpr6; + uint32_t tpr10; + uint32_t tpr11; + uint32_t tpr12; + uint32_t tpr13; + uint32_t tpr14; +}; + +void mctl_set_timing_params(const struct dram_para *para); + +struct dram_config { + u8 cols; /* Column bits */ + u8 rows; /* Row bits */ + u8 ranks; /* Rank bits (different from H616!) */ + u8 banks; /* Bank bits */ + u8 bankgrps; /* Bank group bits */ + u8 bus_full_width; /* 1 = x32, 0 = x16 */ +}; + +#endif /* _SUNXI_DRAM_SUN50I_A133_H */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 45401d5e3c8..b2ec450f900 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -133,13 +133,13 @@ static inline gd_t *get_gd(void) #else #ifdef CONFIG_ARM64 -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("x18") #else -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r9") #endif #endif -static inline void set_gd(volatile gd_t *gd_ptr) +static inline void set_gd(gd_t *gd_ptr) { #ifdef CONFIG_ARM64 __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr)); diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 89b1015bc4d..85ec0e6937e 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -20,23 +20,108 @@ static inline void sync(void) { } -/* Generic virtual read/write. */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) -#define __arch_getq(a) (*(volatile unsigned long long *)(a)) +#ifdef CONFIG_ARM64 +#define __W "w" +#else +#define __W +#endif -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v)) +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) +#define __R "l" +#define __RM "=l" +#else +#define __R "r" +#define __RM "=r" +#endif + +#ifdef CONFIG_KVM_VIRT_INS +/* + * The __raw_writeX/__raw_readX below should be converted to static inline + * functions. However doing so produces a lot of compilation warnings when + * called with a raw address. Convert these once the callers have been fixed. + */ +#define __raw_writeb(val, addr) \ + do { \ + asm volatile("strb %" __W "0, [%1]" \ + : \ + : __R ((u8)(val)), __R (addr)); \ + } while (0) + +#define __raw_readb(addr) \ + ({ \ + u32 __val; \ + asm volatile("ldrb %" __W "0, [%1]" \ + : __RM (__val) \ + : __R (addr)); \ + __val; \ + }) + +#define __raw_writew(val, addr) \ + do { \ + asm volatile("strh %" __W "0, [%1]" \ + : \ + : __R ((u16)(val)), __R (addr)); \ + } while (0) + +#define __raw_readw(addr) \ + ({ \ + u32 __val; \ + asm volatile("ldrh %" __W "0, [%1]" \ + : __RM (__val) \ + : __R (addr)); \ + __val; \ + }) + +#define __raw_writel(val, addr) \ + do { \ + asm volatile("str %" __W "0, [%1]" \ + : \ + : __R ((u32)(val)), __R (addr)); \ + } while (0) + +#define __raw_readl(addr) \ + ({ \ + u32 __val; \ + asm volatile("ldr %" __W "0, [%1]" \ + : __RM (__val) \ + : __R (addr)); \ + __val; \ + }) + +#define __raw_writeq(val, addr) \ + do { \ + asm volatile("str %0, [%1]" \ + : \ + : __R ((u64)(val)), __R (addr)); \ + } while (0) + +#define __raw_readq(addr) \ + ({ \ + u64 __val; \ + asm volatile("ldr %0, [%1]" \ + : __RM (__val) \ + : __R (addr)); \ + __val; \ + }) +#else +/* Generic virtual read/write. */ +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_readq(a) (*(volatile unsigned long long *)(a)) + +#define __raw_writeb(v, a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_writeq(v, a) (*(volatile unsigned long long *)(a) = (v)) +#endif static inline void __raw_writesb(unsigned long addr, const void *data, int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) - __arch_putb(*buf++, addr); + __raw_writeb(*buf++, addr); } static inline void __raw_writesw(unsigned long addr, const void *data, @@ -44,7 +129,7 @@ static inline void __raw_writesw(unsigned long addr, const void *data, { uint16_t *buf = (uint16_t *)data; while(wordlen--) - __arch_putw(*buf++, addr); + __raw_writew(*buf++, addr); } static inline void __raw_writesl(unsigned long addr, const void *data, @@ -52,40 +137,30 @@ static inline void __raw_writesl(unsigned long addr, const void *data, { uint32_t *buf = (uint32_t *)data; while(longlen--) - __arch_putl(*buf++, addr); + __raw_writel(*buf++, addr); } static inline void __raw_readsb(unsigned long addr, void *data, int bytelen) { uint8_t *buf = (uint8_t *)data; while(bytelen--) - *buf++ = __arch_getb(addr); + *buf++ = __raw_readb(addr); } static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) { uint16_t *buf = (uint16_t *)data; while(wordlen--) - *buf++ = __arch_getw(addr); + *buf++ = __raw_readw(addr); } static inline void __raw_readsl(unsigned long addr, void *data, int longlen) { uint32_t *buf = (uint32_t *)data; while(longlen--) - *buf++ = __arch_getl(addr); + *buf++ = __raw_readl(addr); } -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) -#define __raw_writeq(v,a) __arch_putq(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) -#define __raw_readq(a) __arch_getq(a) - /* * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. @@ -98,15 +173,15 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define smp_processor_id() 0 -#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) -#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; }) +#define writeb(v, c) ({ u8 __v = v; __iowmb(); writeb_relaxed(__v, c); __v; }) +#define writew(v, c) ({ u16 __v = v; __iowmb(); writew_relaxed(__v, c); __v; }) +#define writel(v, c) ({ u32 __v = v; __iowmb(); writel_relaxed(__v, c); __v; }) +#define writeq(v, c) ({ u64 __v = v; __iowmb(); writeq_relaxed(__v, c); __v; }) -#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) -#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) +#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) +#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) +#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; }) /* * Relaxed I/O memory access primitives. These follow the Device memory @@ -121,13 +196,10 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ __raw_readq(c)); __r; }) -#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c))) -#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \ - cpu_to_le16(v), (c))) -#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ - cpu_to_le32(v), (c))) -#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \ - cpu_to_le64(v), (c))) +#define writeb_relaxed(v, c) __raw_writeb((v), (c)) +#define writew_relaxed(v, c) __raw_writew((__force u16)cpu_to_le16(v), (c)) +#define writel_relaxed(v, c) __raw_writel((__force u32)cpu_to_le32(v), (c)) +#define writeq_relaxed(v, c) __raw_writeq((__force u64)cpu_to_le64(v), (c)) /* * The compiler seems to be incapable of optimising constants diff --git a/arch/arm/include/asm/iproc-common/sysmap.h b/arch/arm/include/asm/iproc-common/sysmap.h index efd2f35f212..c071e9ea53f 100644 --- a/arch/arm/include/asm/iproc-common/sysmap.h +++ b/arch/arm/include/asm/iproc-common/sysmap.h @@ -6,17 +6,17 @@ #ifndef __SYSMAP_H #define __SYSMAP_H -#define IHOST_PROC_CLK_PLLARMA 0X19000C00 -#define IHOST_PROC_CLK_PLLARMB 0X19000C04 +#define IHOST_PROC_CLK_PLLARMA 0x19000C00 +#define IHOST_PROC_CLK_PLLARMB 0x19000C04 #define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R 24 -#define IHOST_PROC_CLK_WR_ACCESS 0X19000000 -#define IHOST_PROC_CLK_POLICY_FREQ 0X19000008 +#define IHOST_PROC_CLK_WR_ACCESS 0x19000000 +#define IHOST_PROC_CLK_POLICY_FREQ 0x19000008 #define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE 31 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R 24 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R 16 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R 8 -#define IHOST_PROC_CLK_POLICY_CTL 0X1900000C +#define IHOST_PROC_CLK_POLICY_CTL 0x1900000C #define IHOST_PROC_CLK_POLICY_CTL__GO 0 #define IHOST_PROC_CLK_POLICY_CTL__GO_AC 1 #define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0 @@ -26,11 +26,11 @@ #define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R 8 #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB 1 #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0 -#define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200 -#define IHOST_PROC_CLK_CORE1_CLKGATE 0X19000204 -#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0X19000210 -#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0X19000300 -#define IHOST_PROC_CLK_APB0_CLKGATE 0X19000400 +#define IHOST_PROC_CLK_CORE0_CLKGATE 0x19000200 +#define IHOST_PROC_CLK_CORE1_CLKGATE 0x19000204 +#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0x19000210 +#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0x19000300 +#define IHOST_PROC_CLK_APB0_CLKGATE 0x19000400 #define IPROC_CLKCT_HDELAY_SW_EN 0x00000303 #define IPROC_REG_WRITE_ACCESS 0x00a5a501 diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a50dde60e8b..3e11fadafc6 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -145,7 +145,7 @@ ENTRY(_main) ldr r1, =CONFIG_TEXT_BASE sub r1, r0 add lr, r1 -#if defined(CONFIG_SYS_RELOC_GD_ENV_ADDR) +#if defined(CONFIG_ENV_RELOC_GD_ENV_ADDR) ldr r0, [r9, #GD_ENV_ADDR] /* r0 = gd->env_addr */ add r0, r0, r1 str r0, [r9, #GD_ENV_ADDR] diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 30950ddaf9b..f3f279f2c39 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -119,7 +119,7 @@ ENTRY(_main) ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */ sub x9, x9, x0 /* x9 <- Run-vs-link offset */ add lr, lr, x9 -#if defined(CONFIG_SYS_RELOC_GD_ENV_ADDR) +#if defined(CONFIG_ENV_RELOC_GD_ENV_ADDR) ldr x0, [x18, #GD_ENV_ADDR] /* x0 <- gd->env_addr */ add x0, x0, x9 str x0, [x18, #GD_ENV_ADDR] diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 2644a04a622..4cd8979bdc2 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -772,22 +773,31 @@ u64 get_page_table_size(void) #define KERNEL_COMP_SIZE SZ_128M +#define lmb_alloc(size, addr) lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, addr, size, LMB_NONE) + int board_late_init(void) { u32 status = 0; + phys_addr_t addr; /* somewhat based on the Linux Kernel boot requirements: * align by 2M and maximal FDT size 2M */ - status |= env_set_hex("loadaddr", lmb_alloc(SZ_1G, SZ_2M)); - status |= env_set_hex("fdt_addr_r", lmb_alloc(SZ_2M, SZ_2M)); - status |= env_set_hex("kernel_addr_r", lmb_alloc(SZ_128M, SZ_2M)); - status |= env_set_hex("ramdisk_addr_r", lmb_alloc(SZ_1G, SZ_2M)); - status |= env_set_hex("kernel_comp_addr_r", - lmb_alloc(KERNEL_COMP_SIZE, SZ_2M)); - status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); - status |= env_set_hex("scriptaddr", lmb_alloc(SZ_4M, SZ_2M)); - status |= env_set_hex("pxefile_addr_r", lmb_alloc(SZ_4M, SZ_2M)); + status |= !lmb_alloc(SZ_1G, &addr) ? env_set_hex("loadaddr", addr) : 1; + status |= !lmb_alloc(SZ_2M, &addr) ? + env_set_hex("fdt_addr_r", addr) : 1; + status |= !lmb_alloc(SZ_128M, &addr) ? + env_set_hex("kernel_addr_r", addr) : 1; + status |= !lmb_alloc(SZ_1G, &addr) ? + env_set_hex("ramdisk_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_size", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("scriptaddr", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("pxefile_addr_r", addr) : 1; if (status) log_warning("late_init: Failed to set run time variables\n"); diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c index f3561543a35..251c6056cbd 100644 --- a/arch/arm/mach-apple/rtkit.c +++ b/arch/arm/mach-apple/rtkit.c @@ -9,7 +9,9 @@ #include #include +#include #include +#include #include #include #include diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7c4ccc427c8..d21534ce883 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -43,6 +43,10 @@ config SAM9X60 bool select CPU_ARM926EJS +config SAM9X7 + bool + select CPU_ARM926EJS + config SAMA7G5 bool select CPU_V7A @@ -154,6 +158,13 @@ config TARGET_SAM9X60_CURIOSITY select BOARD_EARLY_INIT_F select BOARD_LATE_INIT +config TARGET_SAM9X75_CURIOSITY + bool "SAM9X75 CURIOSITY board" + select SAM9X7 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply OF_UPSTREAM + config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" select BOARD_EARLY_INIT_F @@ -351,6 +362,7 @@ source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sam9x60ek/Kconfig" source "board/atmel/sam9x60_curiosity/Kconfig" +source "board/atmel/sam9x75_curiosity/Kconfig" source "board/atmel/sama7g5ek/Kconfig" source "board/atmel/sama7g54_curiosity/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 62c44b997e4..8a9464cdfba 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o obj-$(CONFIG_SAM9X60) += sam9x60_devices.o +obj-$(CONFIG_SAM9X7) += sam9x7_devices.o obj-y += clock.o obj-y += cpu.o ifndef CONFIG_$(PHASE_)SYSRESET diff --git a/arch/arm/mach-at91/arm926ejs/sam9x7_devices.c b/arch/arm/mach-at91/arm926ejs/sam9x7_devices.c new file mode 100644 index 00000000000..c65764a3de4 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/sam9x7_devices.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + */ + +#include +#include +#include +#include + +unsigned int get_chip_id(void) +{ + /* The 0x40 is the offset of cidr in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x40); +} + +unsigned int get_extension_chip_id(void) +{ + /* The 0x44 is the offset of exid in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x44); +} + +char *get_cpu_name(void) +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sam9x7()) { + switch (extension_id) { + case ARCH_EXID_SAM9X70: + return "SAM9X70"; + case ARCH_EXID_SAM9X72: + return "SAM9X72"; + case ARCH_EXID_SAM9X75: + return "SAM9X75"; + case ARCH_EXID_SAM9X75_D1M: + return "SAM9X75 16MB DDR2 SiP"; + case ARCH_EXID_SAM9X75_D5M: + return "SAM9X75 64MB DDR2 SiP"; + case ARCH_EXID_SAM9X75_D1G: + return "SAM9X75 125MB DDR3L SiP"; + case ARCH_EXID_SAM9X75_D2G: + return "SAM9X75 250MB DDR3L SiP"; + default: + return "Unknown CPU type"; + } + } else { + return "Unknown CPU type"; + } +} diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index 8ef8e007d77..3780f0bfe40 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -19,15 +19,16 @@ #else -typedef struct at91_wdt { - u32 cr; - u32 mr; - u32 sr; -} at91_wdt_t; +enum { + AT91_WDT_MODE_SAM9260 = 0, + AT91_WDT_MODE_SAM9X60 = 1 +}; struct at91_wdt_priv { void __iomem *regs; - u32 regval; + u32 mr; + u32 wddis; + u8 mode; }; #endif @@ -38,15 +39,23 @@ struct at91_wdt_priv { #define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ /* Watchdog Mode Register*/ -#define AT91_WDT_MR 0X04 -#define AT91_WDT_MR_WDV(x) (x & 0xfff) +#define AT91_WDT_MR 0x04 +#define AT91_WDT_MR_WDV(x) ((x) & 0xfff) +#define AT91_SAM9X60_MR_PERIODRST 0x00000010 #define AT91_WDT_MR_WDFIEN 0x00001000 +#define AT91_SAM9X60_MR_WDDIS 0x00001000 #define AT91_WDT_MR_WDRSTEN 0x00002000 #define AT91_WDT_MR_WDRPROC 0x00004000 #define AT91_WDT_MR_WDDIS 0x00008000 -#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) +#define AT91_WDT_MR_WDD(x) (((x) & 0xfff) << 16) #define AT91_WDT_MR_WDDBGHLT 0x10000000 +#define AT91_SAM9X60_MR_WDIDLEHLT 0x10000000 #define AT91_WDT_MR_WDIDLEHLT 0x20000000 +#define AT91_SAM9X60_MR_WDDBGHLT 0x20000000 + +/* Watchdog Window Level Register */ +#define AT91_SAM9X60_WLR 0x0c +#define AT91_SAM9X60_WLR_COUNTER(x) ((x) & 0xfff) /* Hardware timeout in seconds */ #define WDT_MAX_TIMEOUT 16 diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 988ef492b62..de89714b097 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -23,6 +23,8 @@ # include #elif defined(CONFIG_SAM9X60) # include +#elif defined(CONFIG_SAM9X7) +# include #elif defined(CONFIG_SAMA7G5) # include #elif defined(CONFIG_SAMA5D2) diff --git a/arch/arm/mach-at91/include/mach/sam9x7.h b/arch/arm/mach-at91/include/mach/sam9x7.h new file mode 100644 index 00000000000..998fa786f90 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sam9x7.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAM9X7 SoC. + * + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + */ + +#ifndef __SAM9X7_H__ +#define __SAM9X7_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller - FIQ */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ +#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ +#define ATMEL_ID_FLEXCOM0 5 /* FLEXCOM 0 */ +#define ATMEL_ID_FLEXCOM1 6 /* FLEXCOM 1 */ +#define ATMEL_ID_FLEXCOM2 7 /* FLEXCOM 2 */ +#define ATMEL_ID_FLEXCOM3 8 /* FLEXCOM 3 */ +#define ATMEL_ID_FLEXCOM6 9 /* FLEXCOM 6 */ +#define ATMEL_ID_FLEXCOM7 10 /* FLEXCOM 7 */ +#define ATMEL_ID_FLEXCOM8 11 /* FLEXCOM 8 */ +#define ATMEL_ID_SDMMC0 12 /* SDMMC 0 */ +#define ATMEL_ID_FLEXCOM4 13 /* FLEXCOM 4 */ +#define ATMEL_ID_FLEXCOM5 14 /* FLEXCOM 5 */ +#define ATMEL_ID_FLEXCOM9 15 /* FLEXCOM 9 */ +#define ATMEL_ID_FLEXCOM10 16 /* FLEXCOM 10 */ +#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_ADC 19 /* ADC Controller */ +#define ATMEL_ID_XDMAC0 20 /* XDMA Controller 0 */ +#define ATMEL_ID_MATRIX 21 /* BUS Matrix */ +#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ +#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ +#define ATMEL_ID_GMAC 24 /* GMAC */ +#define ATMEL_ID_LCDC 25 /* LCD Controller */ +#define ATMEL_ID_SDMMC1 26 /* SDMMC 1 */ +#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ +#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller - IRQ */ +#define ATMEL_ID_TRNG 38 /* True Random Number Generator */ +#define ATMEL_ID_PIOD 44 /* Parallel I/O Controller D */ +#define ATMEL_ID_DBGU 47 /* Debug unit */ + +/* + * User Peripheral physical base addresses. + */ +#define ATMEL_BASE_FLEXCOM4 0xf0000000 +#define ATMEL_BASE_FLEXCOM5 0xf0004000 +#define ATMEL_BASE_XDMA0 0xf0008000 +#define ATMEL_BASE_SSC 0xf0010000 +#define ATMEL_BASE_QSPI 0xf0014000 +#define ATMEL_BASE_CAN0 0xf8000000 +#define ATMEL_BASE_CAN1 0xf8004000 +#define ATMEL_BASE_TC0 0xf8008000 +#define ATMEL_BASE_TC1 0xf800c000 +#define ATMEL_BASE_FLEXCOM6 0xf8010000 +#define ATMEL_BASE_FLEXCOM7 0xf8014000 +#define ATMEL_BASE_FLEXCOM8 0xf8018000 +#define ATMEL_BASE_FLEXCOM0 0xf801c000 +#define ATMEL_BASE_FLEXCOM1 0xf8020000 +#define ATMEL_BASE_FLEXCOM2 0xf8024000 +#define ATMEL_BASE_FLEXCOM3 0xf8028000 +#define ATMEL_BASE_GMAC 0xf802c000 +#define ATMEL_BASE_PWM 0xf8034000 +#define ATMEL_BASE_LCDC 0xf8038000 +#define ATMEL_BASE_UDPHS 0xf803c000 +#define ATMEL_BASE_FLEXCOM9 0xf8040000 +#define ATMEL_BASE_FLEXCOM10 0xf8044000 +#define ATMEL_BASE_ISC 0xf8048000 +#define ATMEL_BASE_ADC 0xf804c000 +#define ATMEL_BASE_SFR 0xf8050000 +#define ATMEL_BASE_SYS 0xffffc000 + +/* + * System Peripherals + */ +#define ATMEL_BASE_MATRIX 0xffffde00 +#define ATMEL_BASE_PMECC 0xffffe000 +#define ATMEL_BASE_PMERRLOC 0xffffe600 +#define ATMEL_BASE_MPDDRC 0xffffe800 +#define ATMEL_BASE_SMC 0xffffea00 +#define ATMEL_BASE_SDRAMC 0xffffec00 +#define ATMEL_BASE_AIC 0xfffff100 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PIOD 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffe00 +#define ATMEL_BASE_SHDWC 0xfffffe10 +#define ATMEL_BASE_PIT 0xfffffe40 +#define ATMEL_BASE_GPBR 0xfffffe60 +#define ATMEL_BASE_RTC 0xfffffea8 +#define ATMEL_BASE_WDT 0xffffff80 + +/* + * Internal Memory. + */ +#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ +#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ + +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_SDMMC0 0x80000000 +#define ATMEL_BASE_SDMMC1 0x90000000 + +/* + * SAM9x7 series chip id definitions + */ +#define ARCH_ID_SAM9X7 0x89750030 +#define ARCH_EXID_SAM9X70 0x00000005 +#define ARCH_EXID_SAM9X72 0x00000004 +#define ARCH_EXID_SAM9X75 0x00000000 +#define ARCH_EXID_SAM9X75_D1G 0x00000018 +#define ARCH_EXID_SAM9X75_D2G 0x00000020 +#define ARCH_EXID_SAM9X75_D1M 0x00000003 +#define ARCH_EXID_SAM9X75_D5M 0x00000010 + +#define cpu_is_sam9x7() (get_chip_id() == ARCH_ID_SAM9X7) + +/* + * Cpu Name + */ +#define ATMEL_CPU_NAME get_cpu_name() + +/* + * Timer + */ +#define CFG_SYS_TIMER_COUNTER 0xf0028000 + +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 4 +#define CPU_HAS_PCR +#define CPU_NO_PLLB +#define PLL_ID_PLLA 0 +#define PLL_ID_UPLL 1 +#define PLL_ID_AUDIOPLL 2 +#define PLL_ID_LVDSPLL 3 +#define PLL_ID_PLLA_DIV_2 4 + +/* + * PMECC table in ROM + */ +#define ATMEL_PMECC_INDEX_OFFSET_512 0x0000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x8000 + +/* + * SAM9X7 specific prototypes + */ +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +char *get_cpu_name(void); +#endif + +#endif diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 5feb8f73551..a814973242a 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -14,9 +14,7 @@ #if !defined(CONFIG_WDT_AT91) void at91_disable_wdt(void) { - struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; - - writel(AT91_WDT_MR_WDDIS, &wdt->mr); + writel(AT91_WDT_MR_WDDIS, ATMEL_BASE_WDT + AT91_WDT_MR); } #endif diff --git a/arch/arm/mach-exynos/include/mach/dsim.h b/arch/arm/mach-exynos/include/mach/dsim.h index 15671b603c3..de6c2d29871 100644 --- a/arch/arm/mach-exynos/include/mach/dsim.h +++ b/arch/arm/mach-exynos/include/mach/dsim.h @@ -101,7 +101,7 @@ struct exynos_mipi_dsim { /* EXYNOS_DSIM_MDRESOL */ #define DSIM_MAIN_STAND_BY (1 << 31) #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) -#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) +#define DSIM_MAIN_HRESOL(x) (((x) & 0x7ff) << 0) /* EXYNOS_DSIM_MVPORCH */ #define DSIM_CMD_ALLOW_SHIFT (28) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 600092389a3..ab5861578e5 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -74,7 +74,7 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr) #define FSL_SIP_HAB_REPORT_STATUS 0x04 #define FSL_SIP_HAB_FAILSAFE 0x05 #define FSL_SIP_HAB_CHECK_TARGET 0x06 -static volatile gd_t *gd_save; +static gd_t *gd_save; #endif static inline void save_gd(void) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 37a5473ac7c..0e112af661c 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -451,7 +451,7 @@ void get_board_serial(struct tag_serialnr *serialnr) #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } int mmc_get_env_dev(void) @@ -473,7 +473,7 @@ int mmc_get_env_dev(void) break; default: /* If not boot from sd/mmc, use default value */ - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } return board_mmc_get_env_dev(devno); diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b5dc45296d1..8fe70e2424f 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -56,7 +56,7 @@ int mmc_get_env_dev(void) if (ret != ROM_API_OKAY) { puts("ROMAPI: failure at query_boot_info\n"); - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } boot_type = boot >> 16; @@ -64,7 +64,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC) - return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + return env_get_ulong("mmcdev", 10, CONFIG_ENV_MMC_DEVICE_INDEX); return board_mmc_get_env_dev(boot_instance); } @@ -806,7 +806,7 @@ int imx8ulp_dm_post_init(void) EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init); #if defined(CONFIG_XPL_BUILD) -__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +__weak void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index d2b0455bff9..13f13ca7d10 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -67,7 +67,7 @@ int mmc_get_env_dev(void) u16 boot_type; u8 boot_instance; - volatile gd_t *pgd = gd; + gd_t *pgd = gd; rom_passover_t *rdata; #if IS_ENABLED(CONFIG_XPL_BUILD) @@ -84,7 +84,7 @@ int mmc_get_env_dev(void) ret = scmi_get_rom_data(rdata); if (ret != 0) { puts("SCMI: failure at rom_boot_info\n"); - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } } boot_type = rdata->boot_dev_type; @@ -95,7 +95,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC) - return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + return env_get_ulong("mmcdev", 10, CONFIG_ENV_MMC_DEVICE_INDEX); return board_mmc_get_env_dev(boot_instance); } @@ -675,7 +675,7 @@ enum imx9_soc_voltage_mode soc_target_voltage_mode(void) #if IS_ENABLED(CONFIG_SCMI_FIRMWARE) enum boot_device get_boot_device(void) { - volatile gd_t *pgd = gd; + gd_t *pgd = gd; int ret; u16 boot_type; u8 boot_instance; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index bb13ca742e3..02db7cc97ba 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -48,8 +48,8 @@ __weak int board_mmc_get_env_dev(int devno) return devno; } -#ifdef CONFIG_SYS_MMC_ENV_DEV -#define IMX9_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_DEV +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX +#define IMX9_MMC_ENV_DEV CONFIG_ENV_MMC_DEVICE_INDEX #else #define IMX9_MMC_ENV_DEV 0 #endif diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c index c134e95ed78..22ffbcaffd9 100644 --- a/arch/arm/mach-imx/iomux-v3.c +++ b/arch/arm/mach-imx/iomux-v3.c @@ -142,6 +142,6 @@ void imx_iomux_gpio_set_direction(unsigned int gpio, void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state) { *gpio_state = readl(base + (gpio << 2)) & - ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE); + ((0x07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE); } #endif diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 34a7d1706f3..2ec8ddf4d59 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -10,7 +10,7 @@ __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } int mmc_get_env_dev(void) @@ -22,7 +22,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; return board_mmc_get_env_dev(devno); } diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 41116e2c6a2..9901f8a7b56 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index d4a61731a67..50521490b35 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -502,7 +502,7 @@ int arch_cpu_init(void) #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } static int mmc_get_boot_dev(void) @@ -535,15 +535,15 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (devno < 0) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; return board_mmc_get_env_dev(devno); } -#ifdef CONFIG_SYS_MMC_ENV_PART +#ifdef CONFIG_ENV_MMC_EMMC_HW_PARTITION __weak int board_mmc_get_env_part(int devno) { - return CONFIG_SYS_MMC_ENV_PART; + return CONFIG_ENV_MMC_EMMC_HW_PARTITION; } uint mmc_get_env_part(struct mmc *mmc) @@ -552,7 +552,7 @@ uint mmc_get_env_part(struct mmc *mmc) /* If not boot from sd/mmc, use default value */ if (devno < 0) - return CONFIG_SYS_MMC_ENV_PART; + return CONFIG_ENV_MMC_EMMC_HW_PARTITION; return board_mmc_get_env_part(devno); } diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 61d331e0181..5306e76223f 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -362,7 +362,7 @@ static char *get_reset_cause(char *ret) #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } int mmc_get_env_dev(void) @@ -372,7 +372,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (get_boot_mode() == LOW_POWER_BOOT) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; bt1_cfg = readl(CMC1_RBASE + 0x40); devno = (bt1_cfg >> 9) & 0x7; diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index d2e4205c5ce..b134d04b210 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -38,6 +38,11 @@ choice prompt "MX28 board select" optional +config TARGET_BTT + bool "Support BTT" + select PL01X_SERIAL + imply OF_UPSTREAM + config TARGET_MX28EVK bool "Support mx28evk" select PL01X_SERIAL @@ -70,6 +75,7 @@ config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR from VDD5V) - so the VDD4P2 power source is operational. source "board/freescale/mx28evk/Kconfig" +source "board/liebherr/btt/Kconfig" source "board/liebherr/xea/Kconfig" endif diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c index ff0522c2d11..c6fe4d8858e 100644 --- a/arch/arm/mach-imx/romapi.c +++ b/arch/arm/mach-imx/romapi.c @@ -9,7 +9,7 @@ DECLARE_GLOBAL_DATA_PTR; u32 rom_api_download_image(u8 *dest, u32 offset, u32 size) { u32 xor = (uintptr_t)dest ^ offset ^ size; - volatile gd_t *sgd = gd; + gd_t *sgd = gd; u32 ret; ret = g_rom_api->download_image(dest, offset, size, xor); @@ -21,7 +21,7 @@ u32 rom_api_download_image(u8 *dest, u32 offset, u32 size) u32 rom_api_query_boot_infor(u32 info_type, u32 *info) { u32 xor = info_type ^ (uintptr_t)info; - volatile gd_t *sgd = gd; + gd_t *sgd = gd; u32 ret; ret = g_rom_api->query_boot_infor(info_type, info, xor); @@ -34,7 +34,7 @@ extern struct rom_api *g_rom_api; enum boot_device get_boot_device(void) { - volatile gd_t *pgd = gd; + gd_t *pgd = gd; int ret; u32 boot; u16 boot_type; diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index bc291dcd129..518d9cb1262 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -276,7 +276,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) * +------------+ + CSF_PAD_SIZE */ -__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +__weak void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); uint32_t offset; diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index edd43a1d78d..00173e6836b 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -57,7 +57,6 @@ static void ctrl_mmr_unlock(void) mmr_unlock(CTRL_MMR0_BASE, 1); mmr_unlock(CTRL_MMR0_BASE, 2); mmr_unlock(CTRL_MMR0_BASE, 4); - mmr_unlock(CTRL_MMR0_BASE, 5); mmr_unlock(CTRL_MMR0_BASE, 6); /* Unlock all MCU_CTRL_MMR0 module registers */ @@ -172,6 +171,10 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + /* Output DM Firmware version info */ + if (IS_ENABLED(CONFIG_ARM64)) + k3_dm_print_ver(); + if (IS_ENABLED(CONFIG_ESM_K3)) { /* Probe/configure ESM0 */ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); diff --git a/arch/arm/mach-k3/am62px/Kconfig b/arch/arm/mach-k3/am62px/Kconfig index 76ae86b6622..0f1fcfab5fc 100644 --- a/arch/arm/mach-k3/am62px/Kconfig +++ b/arch/arm/mach-k3/am62px/Kconfig @@ -29,5 +29,6 @@ config TARGET_AM62P5_R5_EVM endchoice source "board/ti/am62px/Kconfig" +source "board/toradex/verdin-am62p/Kconfig" endif diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 6e3c66e5107..44a2d445d24 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -224,6 +224,10 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + /* Output DM Firmware version info */ + if (IS_ENABLED(CONFIG_ARM64)) + k3_dm_print_ver(); + if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) { ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-k3/am62x/boot.c b/arch/arm/mach-k3/am62x/boot.c index 132b42f7edb..a3a6cda6bdb 100644 --- a/arch/arm/mach-k3/am62x/boot.c +++ b/arch/arm/mach-k3/am62x/boot.c @@ -101,3 +101,43 @@ u32 get_boot_device(void) return bootmedia; } + +const char *get_reset_reason(void) +{ + u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC); + + /* After reading reset source register, software must clear it */ + if (reset_reason) + writel(reset_reason, CTRLMMR_MCU_RST_SRC); + + if (reset_reason == 0 || + (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN | + RST_SRC_SW_MAIN_POR_FROM_MCU | + RST_SRC_DS_MAIN_PORZ))) + return "POR"; + + if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR)) + return "ESM"; + + if (reset_reason & RST_SRC_DM_WDT_RST) + return "WDOG"; + + if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN | + RST_SRC_SW_MAIN_WARM_FROM_MCU | + RST_SRC_SW_MCU_WARM_RST)) + return "RST"; + + if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST)) + return "DMSC"; + + if (reset_reason & RST_SRC_DEBUG_RST) + return "JTAG"; + + if (reset_reason & RST_SRC_THERMAL_RST) + return "THERMAL"; + + if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN)) + return "PIN"; + + return "UNKNOWN"; +} diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index fc230f180d0..f8c53b286eb 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -31,6 +31,11 @@ #include #include +#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 +#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 +#define PROC_ID_MCU_R5FSS0_CORE1 0x02 +#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100 + #include struct ti_sci_handle *get_ti_sci_handle(void) @@ -68,6 +73,35 @@ void k3_sysfw_print_ver(void) ti_sci->version.firmware_revision, fw_desc); } +void __maybe_unused k3_dm_print_ver(void) +{ + struct ti_sci_handle *ti_sci = get_ti_sci_handle(); + struct ti_sci_firmware_ops *fw_ops = &ti_sci->ops.fw_ops; + struct ti_sci_dm_version_info dm_info = {0}; + u64 fw_caps; + int ret; + + ret = fw_ops->query_dm_cap(ti_sci, &fw_caps); + if (ret) { + printf("Failed to query DM firmware capability %d\n", ret); + return; + } + + if (!(fw_caps & TI_SCI_MSG_FLAG_FW_CAP_DM)) + return; + + ret = fw_ops->get_dm_version(ti_sci, &dm_info); + if (ret) { + printf("Failed to fetch DM firmware version %d\n", ret); + return; + } + + printf("DM ABI: %d.%d (firmware ver 0x%04x '%s--%s' " + "patch_ver: %d)\n", dm_info.abi_major, dm_info.abi_minor, + dm_info.dm_ver, dm_info.sci_server_version, + dm_info.rm_pm_hal_version, dm_info.patch_ver); +} + void mmr_unlock(uintptr_t base, u32 partition) { /* Translate the base address */ @@ -175,11 +209,17 @@ static const char *get_device_type_name(void) } } +__weak const char *get_reset_reason(void) +{ + return NULL; +} + int print_cpuinfo(void) { struct udevice *soc; char name[64]; int ret; + const char *reset_reason; printf("SoC: "); @@ -201,6 +241,10 @@ int print_cpuinfo(void) printf("%s\n", get_device_type_name()); + reset_reason = get_reset_reason(); + if (reset_reason) + printf("Reset reason: %s\n", reset_reason); + return 0; } #endif @@ -328,3 +372,67 @@ void setup_qos(void) writel(qos_data[i].val, (uintptr_t)qos_data[i].reg); } #endif + +int __maybe_unused shutdown_mcu_r5_core1(void) +{ + struct ti_sci_handle *ti_sci = get_ti_sci_handle(); + struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops; + struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops; + u32 dev_id_mcu_r5_core1 = put_core_ids[0]; + u64 boot_vector; + u32 cfg, ctrl, sts, halted; + int cluster_mode_lockstep, ret; + bool r_state = false, c_state = false; + + ret = proc_ops->proc_request(ti_sci, PROC_ID_MCU_R5FSS0_CORE1); + if (ret) { + printf("Unable to request processor control for MCU1_1 core, %d\n", + ret); + return ret; + } + + ret = dev_ops->is_on(ti_sci, dev_id_mcu_r5_core1, &r_state, &c_state); + if (ret) { + printf("Unable to get device status for MCU1_1 core, %d\n", ret); + return ret; + } + + ret = proc_ops->get_proc_boot_status(ti_sci, PROC_ID_MCU_R5FSS0_CORE1, + &boot_vector, &cfg, &ctrl, &sts); + if (ret) { + printf("Unable to get Processor boot status for MCU1_1 core, %d\n", + ret); + goto release_proc_ctrl; + } + + halted = !!(sts & PROC_BOOT_STATUS_FLAG_R5_WFI); + cluster_mode_lockstep = !!(cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP); + + /* + * Shutdown MCU R5F Core 1 only if: + * - cluster is booted in SplitMode + * - core is powered on + * - core is in WFI (halted) + */ + if (cluster_mode_lockstep || !c_state || !halted) { + ret = -EINVAL; + goto release_proc_ctrl; + } + + ret = proc_ops->set_proc_boot_ctrl(ti_sci, PROC_ID_MCU_R5FSS0_CORE1, + PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0); + if (ret) { + printf("Unable to Halt MCU1_1 core, %d\n", ret); + goto release_proc_ctrl; + } + + ret = dev_ops->put_device(ti_sci, dev_id_mcu_r5_core1); + if (ret) { + printf("Unable to assert reset on MCU1_1 core, %d\n", ret); + return ret; + } + +release_proc_ctrl: + proc_ops->proc_release(ti_sci, PROC_ID_MCU_R5FSS0_CORE1); + return ret; +} diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 02c74731fea..52d3faaab5c 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -42,6 +42,7 @@ int remove_fwl_region(struct fwl_data *fwl); void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr); void k3_sysfw_print_ver(void); +void k3_dm_print_ver(void); void spl_enable_cache(void); void mmr_unlock(uintptr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); @@ -49,6 +50,7 @@ enum k3_device_type get_device_type(void); struct ti_sci_handle *get_ti_sci_handle(void); void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); +int shutdown_mcu_r5_core1(void); #if (IS_ENABLED(CONFIG_K3_QOS)) void setup_qos(void); diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index bcbc4821c82..2f5655bf24a 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -79,6 +79,25 @@ #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) +/* Reset Reason Detection */ +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) + +#define RST_SRC_SAFETY_ERR BIT(31) +#define RST_SRC_MAIN_ESM_ERR BIT(30) +#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25) +#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24) +#define RST_SRC_DS_MAIN_PORZ BIT(23) +#define RST_SRC_DM_WDT_RST BIT(22) +#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21) +#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20) +#define RST_SRC_SW_MCU_WARM_RST BIT(16) +#define RST_SRC_SMS_WARM_RST BIT(13) +#define RST_SRC_SMS_COLD_RST BIT(12) +#define RST_SRC_DEBUG_RST BIT(8) +#define RST_SRC_THERMAL_RST BIT(4) +#define RST_SRC_MAIN_RESET_PIN BIT(2) +#define RST_SRC_MCU_RESET_PIN BIT(0) + /* Debounce register configuration */ #define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4)) @@ -158,8 +177,8 @@ static inline int k3_has_gpu(void) static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_AM62_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h index cd61abe0185..f3fd736f31b 100644 --- a/arch/arm/mach-k3/include/mach/am62a_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -90,8 +90,8 @@ static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_AM62A_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62p_hardware.h b/arch/arm/mach-k3/include/mach/am62p_hardware.h index 95af5c5c547..a310b52b45d 100644 --- a/arch/arm/mach-k3/include/mach/am62p_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62p_hardware.h @@ -141,8 +141,8 @@ static inline int k3_get_a53_max_frequency(void) static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_AM62P_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 44df887d5df..105b42986de 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -50,19 +50,20 @@ #define AM64X_DEV_RTI8 127 #define AM64X_DEV_RTI9 128 -#define AM64X_DEV_R5FSS0_CORE0 121 -#define AM64X_DEV_R5FSS0_CORE1 122 static const u32 put_device_ids[] = { AM64X_DEV_RTI9, AM64X_DEV_RTI8, }; +#endif + +#define AM64X_DEV_R5FSS0_CORE0 121 +#define AM64X_DEV_R5FSS0_CORE1 122 + static const u32 put_core_ids[] = { AM64X_DEV_R5FSS0_CORE1, AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 9913964c46b..8169584a372 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -43,19 +43,20 @@ #define AM6_DEV_MCU_RTI0 134 #define AM6_DEV_MCU_RTI1 135 -#define AM6_DEV_MCU_ARMSS0_CPU0 159 -#define AM6_DEV_MCU_ARMSS0_CPU1 245 static const u32 put_device_ids[] = { AM6_DEV_MCU_RTI0, AM6_DEV_MCU_RTI1, }; +#endif + +#define AM6_DEV_MCU_ARMSS0_CPU0 159 +#define AM6_DEV_MCU_ARMSS0_CPU1 245 + static const u32 put_core_ids[] = { AM6_DEV_MCU_ARMSS0_CPU1, AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_AM6_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index fc7bee4d00b..81b5f1fa45e 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -125,4 +125,5 @@ struct rom_extended_boot_data { }; u32 get_boot_device(void); +const char *get_reset_reason(void); #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index 2b5ec771e18..5bef309af0a 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -41,19 +41,20 @@ #define J721E_DEV_MCU_RTI0 262 #define J721E_DEV_MCU_RTI1 263 -#define J721E_DEV_MCU_ARMSS0_CPU0 250 -#define J721E_DEV_MCU_ARMSS0_CPU1 251 static const u32 put_device_ids[] = { J721E_DEV_MCU_RTI0, J721E_DEV_MCU_RTI1, }; +#endif + +#define J721E_DEV_MCU_ARMSS0_CPU0 250 +#define J721E_DEV_MCU_ARMSS0_CPU1 251 + static const u32 put_core_ids[] = { J721E_DEV_MCU_ARMSS0_CPU1, J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_J721E_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 8daea82a77e..82f076a45e0 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -41,19 +41,20 @@ #define J721S2_DEV_MCU_RTI0 295 #define J721S2_DEV_MCU_RTI1 296 -#define J721S2_DEV_MCU_ARMSS0_CPU0 284 -#define J721S2_DEV_MCU_ARMSS0_CPU1 285 static const u32 put_device_ids[] = { J721S2_DEV_MCU_RTI0, J721S2_DEV_MCU_RTI1, }; +#endif + +#define J721S2_DEV_MCU_ARMSS0_CPU0 284 +#define J721S2_DEV_MCU_ARMSS0_CPU1 285 + static const u32 put_core_ids[] = { J721S2_DEV_MCU_ARMSS0_CPU1, J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_J721S2_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j722s_hardware.h b/arch/arm/mach-k3/include/mach/j722s_hardware.h index 8d0bec22068..0c695134c28 100644 --- a/arch/arm/mach-k3/include/mach/j722s_hardware.h +++ b/arch/arm/mach-k3/include/mach/j722s_hardware.h @@ -76,8 +76,8 @@ static const u32 put_device_ids[] = {}; -static const u32 put_core_ids[] = {}; - #endif +static const u32 put_core_ids[] = {}; + #endif /* __ASM_ARCH_J722S_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j784s4_hardware.h b/arch/arm/mach-k3/include/mach/j784s4_hardware.h index 0ffe238cdae..29a894baed3 100644 --- a/arch/arm/mach-k3/include/mach/j784s4_hardware.h +++ b/arch/arm/mach-k3/include/mach/j784s4_hardware.h @@ -41,19 +41,20 @@ #define J784S4_DEV_MCU_RTI0 367 #define J784S4_DEV_MCU_RTI1 368 -#define J784S4_DEV_MCU_ARMSS0_CPU0 346 -#define J784S4_DEV_MCU_ARMSS0_CPU1 347 static const u32 put_device_ids[] = { J784S4_DEV_MCU_RTI0, J784S4_DEV_MCU_RTI1, }; +#endif + +#define J784S4_DEV_MCU_ARMSS0_CPU0 346 +#define J784S4_DEV_MCU_ARMSS0_CPU1 347 + static const u32 put_core_ids[] = { J784S4_DEV_MCU_ARMSS0_CPU1, J784S4_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ }; -#endif - #endif /* __ASM_ARCH_J784S4_HARDWARE_H */ diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index f31c20f7ed6..f9af0288cf6 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -296,9 +296,9 @@ void do_dt_magic(void) void board_init_f(ulong dummy) { + int ret; #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW) struct udevice *dev; - int ret; #endif /* * Cannot delay this further as there is a chance that @@ -371,9 +371,20 @@ void board_init_f(ulong dummy) preloader_console_init(); #endif + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */ + if (IS_ENABLED(CONFIG_ARM64)) { + ret = shutdown_mcu_r5_core1(); + if (ret) + printf("Unable to shutdown MCU R5 core 1, %d\n", ret); + } + /* Output System Firmware version info */ k3_sysfw_print_ver(); + /* Output DM Firmware version info */ + if (IS_ENABLED(CONFIG_ARM64)) + k3_dm_print_ver(); + /* Perform board detection */ do_board_detect(); diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 5941fa26a95..eee3d0440ac 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -230,8 +230,19 @@ void k3_spl_init(void) remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls)); } + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */ + if (IS_ENABLED(CONFIG_ARM64)) { + ret = shutdown_mcu_r5_core1(); + if (ret) + printf("Unable to shutdown MCU R5 core 1, %d\n", ret); + } + /* Output System Firmware version info */ k3_sysfw_print_ver(); + + /* Output DM Firmware version info */ + if (IS_ENABLED(CONFIG_ARM64)) + k3_dm_print_ver(); } bool check_rom_loaded_sysfw(void) diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c index af211377e7c..1180c75f551 100644 --- a/arch/arm/mach-k3/j722s/j722s_init.c +++ b/arch/arm/mach-k3/j722s/j722s_init.c @@ -150,6 +150,10 @@ static void k3_spl_init(void) /* Output System Firmware version info */ k3_sysfw_print_ver(); + + /* Output DM Firmware version info */ + if (IS_ENABLED(CONFIG_ARM64)) + k3_dm_print_ver(); } static void k3_mem_init(void) @@ -162,6 +166,8 @@ static void k3_mem_init(void) if (ret) panic("DRAM init failed: %d\n", ret); } + + spl_enable_cache(); } static __maybe_unused void enable_mcu_esm_reset(void) diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 787cf6261e4..0f11511bda0 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -206,8 +206,19 @@ void k3_spl_init(void) writel(AUDIO_REFCLK1_DEFAULT, (uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL); + /* Shutdown MCU_R5 Core 1 in Split mode at A72 SPL Stage */ + if (IS_ENABLED(CONFIG_ARM64)) { + ret = shutdown_mcu_r5_core1(); + if (ret) + printf("Unable to shutdown MCU R5 core 1, %d\n", ret); + } + /* Output System Firmware version info */ k3_sysfw_print_ver(); + + /* Output DM Firmware version info */ + if (IS_ENABLED(CONFIG_ARM64)) + k3_dm_print_ver(); } void k3_mem_init(void) @@ -242,6 +253,10 @@ void board_init_f(ulong dummy) int ret; k3_spl_init(); + + /* Perform board detection */ + do_board_detect(); + k3_mem_init(); if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_AVS0)) { diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 0b6604039f3..6ac2973bd67 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -5,6 +5,7 @@ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include @@ -136,7 +137,7 @@ void release_resources_for_core_shutdown(void) } } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); struct ti_sci_handle *ti_sci = get_ti_sci_handle(); diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c index e9ecc05953a..7b94a80b725 100644 --- a/arch/arm/mach-keystone/cmd_clock.c +++ b/arch/arm/mach-keystone/cmd_clock.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index 971c081bb3c..482995fc8ba 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -67,8 +67,8 @@ /* NETCP */ #define KS2_NETCP_BASE 0x04000000 -#define K2G_GPIO0_BASE 0X02603000 -#define K2G_GPIO1_BASE 0X0260a000 +#define K2G_GPIO0_BASE 0x02603000 +#define K2G_GPIO1_BASE 0x0260a000 #define K2G_GPIO0_BANK0_BASE K2G_GPIO0_BASE + 0x10 #define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38 #define K2G_GPIO_DIR_OFFSET 0x0 diff --git a/arch/arm/mach-kirkwood/include/mach/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h index e2757942590..f50156b3357 100644 --- a/arch/arm/mach-kirkwood/include/mach/mpp.h +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h @@ -89,7 +89,7 @@ #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0x3, 0, 1, 1, 1, 1, 1 ) #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 2efc8c6a88f..8bdd3848d26 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -6,14 +6,13 @@ #include #include +#include #include #include #include DECLARE_GLOBAL_DATA_PTR; -#define SZ_8G _AC(0x200000000, ULL) - int dram_init(void) { int ret; diff --git a/arch/arm/mach-mediatek/tzcfg.c b/arch/arm/mach-mediatek/tzcfg.c index 71982ba4d20..c8fe8ac0e9b 100644 --- a/arch/arm/mach-mediatek/tzcfg.c +++ b/arch/arm/mach-mediatek/tzcfg.c @@ -173,6 +173,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) int arch_misc_init(void) { + phys_addr_t addr; struct arm_smccc_res res; /* @@ -180,11 +181,14 @@ int arch_misc_init(void) * there's no need to check the result */ arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); - lmb_reserve(res.a1, res.a2, LMB_NOMAP); + addr = (phys_addr_t)res.a1; + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, res.a2, LMB_NOMAP); arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + addr = (phys_addr_t)res.a1; if (!res.a0 && res.a1 && res.a2) - lmb_reserve(res.a1, res.a2, LMB_NOMAP); + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, res.a2, + LMB_NOMAP); #if IS_ENABLED(CONFIG_CMD_PSTORE) char cmd[64]; diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 7908f75809c..3eb93c82387 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -109,5 +109,5 @@ int mmc_get_env_dev(void) return 1; } - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index ddd7eeaf052..95b44c8b1e5 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -291,7 +291,7 @@ void spl_soc_init(void) spl_boot_ipu(); } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(u32 *); image_entry_noargs_t image_entry = diff --git a/arch/arm/mach-omap2/lowlevel_init.S b/arch/arm/mach-omap2/lowlevel_init.S index 1a55295f9de..e977805bd03 100644 --- a/arch/arm/mach-omap2/lowlevel_init.S +++ b/arch/arm/mach-omap2/lowlevel_init.S @@ -39,7 +39,7 @@ restore_from_hyp: adr r0, save_sp ldr sp, [r0] MRC p15, 4, R0, c1, c0, 0 - ldr r1, =0X1004 @Set cache enable bits for hypervisor mode + ldr r1, =0x1004 @Set cache enable bits for hypervisor mode orr r0, r0, r1 MCR p15, 4, R0, c1, c0, 0 b switch_to_hypervisor_ret diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d3ed870b169..342933ca509 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -362,7 +362,7 @@ config ROCKCHIP_RK3528 imply SPL_REGMAP imply SPL_SERIAL imply SPL_SYSCON - imply SYS_RELOC_GD_ENV_ADDR + imply ENV_RELOC_GD_ENV_ADDR imply SYSRESET imply SYSRESET_PSCI if SPL_ATF help @@ -446,7 +446,7 @@ config ROCKCHIP_RK3576 imply SPL_REGMAP imply SPL_SERIAL imply SPL_SYSCON - imply SYS_RELOC_GD_ENV_ADDR + imply ENV_RELOC_GD_ENV_ADDR imply SYSRESET help The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72 and diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 75d6693e28a..2e6bb38b923 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -512,8 +512,8 @@ int mmc_get_env_dev(void) const char *boot_device; struct udevice *dev; -#ifdef CONFIG_SYS_MMC_ENV_DEV - devnum = CONFIG_SYS_MMC_ENV_DEV; +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX + devnum = CONFIG_ENV_MMC_DEVICE_INDEX; #else devnum = 0; #endif diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c index e375b5c9dfa..30b77aee459 100644 --- a/arch/arm/mach-sc5xx/init/dmcinit.c +++ b/arch/arm/mach-sc5xx/init/dmcinit.c @@ -367,7 +367,7 @@ static inline void calibration_legacy(void) */ if (dmc.ddr_mode == DDR3_MODE || dmc.ddr_mode == DDR2_MODE) { - writel(0XFC000000, dmc.reg + REG_DMC_PHY_CTL2); + writel(0xFC000000, dmc.reg + REG_DMC_PHY_CTL2); writel(0x0000000f, dmc.reg + REG_DMC_PHY_CTL0); } diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 5547d6d054f..ec51ebbbe7f 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -37,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; +enum qcom_boot_source qcom_boot_source __section(".data") = 0; + static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; struct mm_region *mem_map = rbx_mem_map; @@ -238,6 +240,12 @@ int board_fdt_blob_setup(void **fdtp) if (ret < 0) panic("No valid memory ranges found!\n"); + /* If we have an external FDT, it can only have come from the Android bootloader. */ + if (external_valid) + qcom_boot_source = QCOM_BOOT_SOURCE_ANDROID; + else + qcom_boot_source = QCOM_BOOT_SOURCE_XBL; + debug("ram_base = %#011lx, ram_size = %#011llx\n", gd->ram_base, gd->ram_size); @@ -481,6 +489,23 @@ static void configure_env(void) qcom_set_serialno(); } +void qcom_show_boot_source(void) +{ + const char *name = "UNKNOWN"; + + switch (qcom_boot_source) { + case QCOM_BOOT_SOURCE_ANDROID: + name = "ABL"; + break; + case QCOM_BOOT_SOURCE_XBL: + name = "XBL"; + break; + } + + log_info("U-Boot loaded from %s\n", name); + env_set("boot_source", name); +} + void __weak qcom_late_init(void) { } @@ -492,38 +517,56 @@ void __weak qcom_late_init(void) #define FASTBOOT_BUF_SIZE 0 #endif -#define addr_alloc(size) lmb_alloc(size, SZ_2M) +#define lmb_alloc(size, addr) lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, addr, size, LMB_NONE) /* Stolen from arch/arm/mach-apple/board.c */ int board_late_init(void) { - u32 status = 0; + u32 status = 0, fdt_status = 0; phys_addr_t addr; struct fdt_header *fdt_blob = (struct fdt_header *)gd->fdt_blob; /* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */ - addr = addr_alloc(SZ_128M); + status |= !lmb_alloc(SZ_128M, &addr) ? + env_set_hex("loadaddr", addr) : 1; status |= env_set_hex("kernel_addr_r", addr); - status |= env_set_hex("loadaddr", addr); - status |= env_set_hex("ramdisk_addr_r", addr_alloc(SZ_128M)); - status |= env_set_hex("kernel_comp_addr_r", addr_alloc(KERNEL_COMP_SIZE)); - status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); - if (IS_ENABLED(CONFIG_FASTBOOT)) - status |= env_set_hex("fastboot_addr_r", addr_alloc(FASTBOOT_BUF_SIZE)); - status |= env_set_hex("scriptaddr", addr_alloc(SZ_4M)); - status |= env_set_hex("pxefile_addr_r", addr_alloc(SZ_4M)); - addr = addr_alloc(SZ_2M); - status |= env_set_hex("fdt_addr_r", addr); + status |= !lmb_alloc(SZ_128M, &addr) ? + env_set_hex("ramdisk_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_size", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("scriptaddr", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("pxefile_addr_r", addr) : 1; - if (status) + if (IS_ENABLED(CONFIG_FASTBOOT)) { + status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ? + env_set_hex("fastboot_addr_r", addr) : 1; + /* override loadaddr for memory rich soc */ + status |= !lmb_alloc(SZ_128M, &addr) ? + env_set_hex("loadaddr", addr) : 1; + } + + fdt_status |= !lmb_alloc(SZ_2M, &addr) ? + env_set_hex("fdt_addr_r", addr) : 1; + + if (status || fdt_status) log_warning("%s: Failed to set run time variables\n", __func__); /* By default copy U-Boots FDT, it will be used as a fallback */ - memcpy((void *)addr, (void *)gd->fdt_blob, fdt32_to_cpu(fdt_blob->totalsize)); + if (fdt_status) + log_warning("%s: Failed to reserve memory for copying FDT\n", + __func__); + else + memcpy((void *)addr, (void *)gd->fdt_blob, + fdt32_to_cpu(fdt_blob->totalsize)); configure_env(); qcom_late_init(); + qcom_show_boot_source(); /* Configure the dfu_string for capsule updates */ qcom_configure_capsule_updates(); diff --git a/arch/arm/mach-snapdragon/capsule_update.c b/arch/arm/mach-snapdragon/capsule_update.c index bf75a9a1b24..4dced4961b6 100644 --- a/arch/arm/mach-snapdragon/capsule_update.c +++ b/arch/arm/mach-snapdragon/capsule_update.c @@ -20,22 +20,19 @@ #include "qcom-priv.h" /* - * NOTE: for now this implementation only supports the rb3gen2. Supporting other - * boards that boot in different ways (e.g. chainloaded from ABL) will require - * additional complexity to properly create the dfu string and fw_images array. - */ - -/* - * To handle different variants like chainloaded U-Boot here we'll need to - * build the fw_images array dynamically at runtime. It looks like - * mach-rockchip is a good example for how to do this. - * Detecting which image types a board uses is TBD, hence for now we only - * support the one new board that runs U-Boot as its primary bootloader. + * To handle different variants like chainloaded U-Boot here we need to + * build the fw_images array dynamically at runtime. These are the possible + * implementations: + * + * - Devices with U-Boot on the uefi_a/b partition + * - Devices with U-Boot on the boot (a/b) partition + * - Devices with U-Boot on the xbl (a/b) partition + * + * Which partition actually has U-Boot on it is determined based on the + * qcom_boot_source variable and additional logic in find_target_partition(). */ struct efi_fw_image fw_images[] = { { - /* U-Boot flashed to the uefi_X partition (e.g. rb3gen2) */ - .fw_name = u"UBOOT_UEFI_PARTITION", .image_index = 1, }, }; @@ -47,6 +44,12 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +enum target_part_type { + TARGET_PART_UEFI = 1, + TARGET_PART_XBL, + TARGET_PART_BOOT, +}; + /* LSB first */ struct part_slot_status { u16: 2; @@ -57,35 +60,202 @@ struct part_slot_status { u16 tries_remaining : 4; }; -static int find_boot_partition(const char *partname, struct blk_desc *blk_dev, char *name) +enum ab_slot { + SLOT_NONE, + SLOT_A, + SLOT_B, +}; + +static enum ab_slot get_part_slot(const char *partname) +{ + int len = strlen(partname); + + if (partname[len - 2] != '_') + return SLOT_NONE; + if (partname[len - 1] == 'a') + return SLOT_A; + if (partname[len - 1] == 'b') + return SLOT_B; + + return SLOT_NONE; +} + +/* + * Determine which partition U-Boot is flashed to based on the boot source (ABL/XBL), + * the slot status, and prioritizing the uefi partition over xbl if found. + */ +static int find_target_partition(int *devnum, enum uclass_id *uclass, + enum target_part_type *target_part_type) { int ret; - int partnum; + int partnum, uefi_partnum = -1, xbl_partnum = -1; struct disk_partition info; struct part_slot_status *slot_status; + struct udevice *dev = NULL; + struct blk_desc *desc = NULL, *xbl_desc = NULL; + uchar ptn_name[32] = { 0 }; + bool have_ufs = false; - for (partnum = 1;; partnum++) { - ret = part_get_info(blk_dev, partnum, &info); - if (ret) - return ret; + /* + * Check to see if we have UFS storage, if so U-Boot MUST be on it and we can skip + * all non-UFS block devices + */ + uclass_foreach_dev_probe(UCLASS_UFS, dev) { + have_ufs = true; + break; + } - slot_status = (struct part_slot_status *)&info.type_flags; - log_io("%16s: Active: %1d, Successful: %1d, Unbootable: %1d, Tries left: %1d\n", - info.name, slot_status->active, - slot_status->successful, slot_status->unbootable, - slot_status->tries_remaining); + uclass_foreach_dev_probe(UCLASS_BLK, dev) { + if (device_get_uclass_id(dev) != UCLASS_BLK) + continue; + + /* If we have a UFS then don't look at any other block devices */ + if (have_ufs) { + if (device_get_uclass_id(dev->parent->parent) != UCLASS_UFS) + continue; /* - * FIXME: eventually we'll want to find the active/inactive variant of the partition - * but on the rb3gen2 these values might all be 0 + * If we don't have UFS, then U-Boot must be on the eMMC which is always the first + * MMC device. */ - if (!strncmp(info.name, partname, strlen(partname))) { - log_debug("Found active %s partition: '%s'!\n", partname, info.name); - strlcpy(name, info.name, sizeof(info.name)); - return partnum; + } else if (dev->parent->seq_ > 0) { + continue; + } + + desc = dev_get_uclass_plat(dev); + if (!desc || desc->part_type == PART_TYPE_UNKNOWN) + continue; + for (partnum = 1;; partnum++) { + ret = part_get_info(desc, partnum, &info); + if (ret) + break; + + slot_status = (struct part_slot_status *)&info.type_flags; + + /* + * Qualcomm Linux devices have a "uefi" partition, it's A/B but the + * flags might not be set so we assume the A partition unless the B + * partition is active. + */ + if (!strncmp(info.name, "uefi", strlen("uefi"))) { + /* + * If U-Boot was chainloaded somehow we can't be flashed to + * the uefi partition + */ + if (qcom_boot_source != QCOM_BOOT_SOURCE_XBL) + continue; + + *target_part_type = TARGET_PART_UEFI; + /* + * Found an active UEFI partition, this is where U-Boot is + * flashed. + */ + if (slot_status->active) + goto found; + + /* Prefer A slot if it's not marked active */ + if (get_part_slot(info.name) == SLOT_A) { + /* + * If we found the A slot after the B slot (both + * inactive) then we assume U-Boot is on the A slot. + */ + if (uefi_partnum >= 0) + goto found; + + /* Didn't find the B slot yet */ + uefi_partnum = partnum; + strlcpy(ptn_name, info.name, 32); + } else { + /* + * Found inactive B slot after inactive A slot, return + * the A slot + */ + if (uefi_partnum >= 0) { + partnum = uefi_partnum; + goto found; + } + + /* + * Didn't find the A slot yet. Record that we found the + * B slot + */ + uefi_partnum = partnum; + strlcpy(ptn_name, info.name, 32); + } + /* xbl and aboot are effectively the same */ + } else if ((!strncmp(info.name, "xbl", strlen("xbl")) && + strlen(info.name) == 5) || + !strncmp(info.name, "aboot", strlen("aboot"))) { + /* + * If U-Boot was booted via ABL, we can't be flashed to the + * XBL partition + */ + if (qcom_boot_source != QCOM_BOOT_SOURCE_XBL) + continue; + + /* + * ignore xbl partition if we have uefi partitions, U-Boot will + * always be on the UEFI partition in this case. + */ + if (*target_part_type == TARGET_PART_UEFI) + continue; + + /* Either non-A/B or find the active XBL partition */ + if (slot_status->active || !get_part_slot(info.name)) { + /* + * No quick return since we might find a uefi partition + * later + */ + xbl_partnum = partnum; + *target_part_type = TARGET_PART_XBL; + xbl_desc = desc; + strlcpy(ptn_name, info.name, 32); + } + + /* + * No fast return since we might also have a uefi partition which + * will take priority. + */ + } else if (!strncmp(info.name, "boot", strlen("boot"))) { + /* We can only be flashed to boot if we were chainloaded */ + if (qcom_boot_source != QCOM_BOOT_SOURCE_ANDROID) + continue; + + /* + * Either non-A/B or find the active partition. We can return + * immediately here since we've narrowed it down to a single option + */ + if (slot_status->active || !get_part_slot(info.name)) { + *target_part_type = TARGET_PART_BOOT; + goto found; + } + } } } + /* + * Now we've exhausted all options, if we didn't find a uefi partition + * then we are indeed flashed to the xbl partition. + */ + if (*target_part_type == TARGET_PART_XBL) { + partnum = xbl_partnum; + desc = xbl_desc; + goto found; + } + + /* Found no candidate partitions */ return -1; + +found: + if (desc) { + *devnum = desc->devnum; + *uclass = desc->uclass_id; + } + + /* info won't match for XBL hence the copy. */ + log_info("Capsule update target: %s (disk %d:%d)\n", + *target_part_type == TARGET_PART_BOOT ? info.name : ptn_name, + *devnum, partnum); + return partnum; } /** @@ -101,12 +271,10 @@ static int find_boot_partition(const char *partname, struct blk_desc *blk_dev, c */ void qcom_configure_capsule_updates(void) { - struct blk_desc *desc; int ret = 0, partnum = -1, devnum; static char dfu_string[32] = { 0 }; - char name[32]; /* GPT partition name */ - char *partname = "uefi_a"; - struct udevice *dev = NULL; + enum target_part_type target_part_type = 0; + enum uclass_id dev_uclass; if (IS_ENABLED(CONFIG_SCSI)) { /* Scan for SCSI devices */ @@ -117,26 +285,30 @@ void qcom_configure_capsule_updates(void) } } - uclass_foreach_dev_probe(UCLASS_BLK, dev) { - if (device_get_uclass_id(dev) != UCLASS_BLK) - continue; - - desc = dev_get_uclass_plat(dev); - if (!desc || desc->part_type == PART_TYPE_UNKNOWN) - continue; - devnum = desc->devnum; - partnum = find_boot_partition(partname, desc, - name); - if (partnum >= 0) - break; - } - + partnum = find_target_partition(&devnum, &dev_uclass, &target_part_type); if (partnum < 0) { log_err("Failed to find boot partition\n"); return; } - switch (desc->uclass_id) { + /* + * Set the fw_name based on the partition type. This causes the GUID to be different + * so we will never accidentally flash a U-Boot image intended for XBL to the boot + * partition. + */ + switch (target_part_type) { + case TARGET_PART_UEFI: + fw_images[0].fw_name = u"UBOOT_UEFI_PARTITION"; + break; + case TARGET_PART_XBL: + fw_images[0].fw_name = u"UBOOT_XBL_PARTITION"; + break; + case TARGET_PART_BOOT: + fw_images[0].fw_name = u"UBOOT_BOOT_PARTITION"; + break; + } + + switch (dev_uclass) { case UCLASS_SCSI: snprintf(dfu_string, 32, "scsi %d=u-boot.bin part %d", devnum, partnum); break; @@ -144,10 +316,10 @@ void qcom_configure_capsule_updates(void) snprintf(dfu_string, 32, "mmc 0=u-boot.bin part %d %d", devnum, partnum); break; default: - debug("Unsupported storage uclass: %d\n", desc->uclass_id); + debug("Unsupported storage uclass: %d\n", dev_uclass); return; } - log_debug("boot partition is %s, DFU string: '%s'\n", name, dfu_string); + log_debug("DFU string: '%s'\n", dfu_string); update_info.dfu_string = dfu_string; } diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index b398c6b7b9f..328c7812f30 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -99,19 +99,6 @@ static int fixup_qcom_dwc3(struct device_node *root, struct device_node *glue_np return ret; } - /* - * The RB1/2 boards only have a single USB controller and it's muxed between the type-C port - * and a USB hub. Since we can't do OTG in U-Boot properly we prefer to put it into host mode. - */ - if (of_device_is_compatible(root, "qcom,qrb4210-rb2", NULL, NULL) || - of_device_is_compatible(root, "qcom,qrb2210-rb1", NULL, NULL)) { - ret = of_write_prop(dwc3, "dr_mode", sizeof("host"), "host"); - if (ret) { - log_err("Failed to set 'dr_mode' property: %d\n", ret); - return ret; - } - } - return 0; } diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h index 4f398e2ba37..b8bf574e8bb 100644 --- a/arch/arm/mach-snapdragon/qcom-priv.h +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -3,6 +3,20 @@ #ifndef __QCOM_PRIV_H__ #define __QCOM_PRIV_H__ +/** + * enum qcom_boot_source - Track where we got loaded from. + * Used for capsule update logic. + * + * @QCOM_BOOT_SOURCE_ANDROID: chainloaded (typically from ABL) + * @QCOM_BOOT_SOURCE_XBL: flashed to the XBL or UEFI partition + */ +enum qcom_boot_source { + QCOM_BOOT_SOURCE_ANDROID = 1, + QCOM_BOOT_SOURCE_XBL, +}; + +extern enum qcom_boot_source qcom_boot_source; + #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) void qcom_configure_capsule_updates(void); #else diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 8506d510413..bda12324803 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index 18921169a6d..5dcbda9473e 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -120,12 +120,12 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_PLLGLOB_PD_MASK 0x00000001 #define CLKMGR_PLLGLOB_RST_MASK 0x00000002 -#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0x3 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 #define CLKMGR_VCO_PSRC_EOSC1 0 #define CLKMGR_VCO_PSRC_INTOSC 1 #define CLKMGR_VCO_PSRC_F2S 2 -#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0x3f #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 #define CLKMGR_CLKSRC_MASK 0x7 @@ -152,7 +152,7 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 -#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3 +#define CLKMGR_NOCDIV_L4SPCLK_MASK 0x3 #define CLKMGR_NOCDIV_DIV1 0 #define CLKMGR_NOCDIV_DIV2 1 #define CLKMGR_NOCDIV_DIV4 2 diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig index 70233a4b23c..72f20c477d0 100644 --- a/arch/arm/mach-stm32/stm32h7/Kconfig +++ b/arch/arm/mach-stm32/stm32h7/Kconfig @@ -6,11 +6,15 @@ config TARGET_STM32H743_DISCO config TARGET_STM32H743_EVAL bool "STM32H743 Evaluation board" +config TARGET_STM32H747_DISCO + bool "STM32H747 Discovery board" + config TARGET_STM32H750_ART_PI bool "STM32H750 ART Pi board" source "board/st/stm32h743-eval/Kconfig" source "board/st/stm32h743-disco/Kconfig" +source "board/st/stm32h747-disco/Kconfig" source "board/st/stm32h750-art-pi/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 58250901101..09b7d5123ae 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -139,6 +139,15 @@ config STM32_ECDSA_VERIFY ROM API provided on STM32MP. The ROM API is only available during SPL for now. +config STM32MP_TAMP_NVMEM + bool "STM32 TAMP backup registers via NVMEM API" + select NVMEM + default y + help + Say y to enable the uclass driver for TAMP Backup registers using the + NVMEM API. It allows to access to boot mode or others shared information + between software components/execution levels. + config CMD_STM32KEY bool "command stm32key to fuse public key hash" depends on CMDLINE diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 103e3410ad9..ecd49fe668d 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -13,6 +13,8 @@ obj-$(CONFIG_STM32MP13X) += stm32mp1/ obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_MFD_STM32_TIMERS) += timers.o +obj-$(CONFIG_STM32MP_TAMP_NVMEM) += tamp_nvram.o + obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o ifndef CONFIG_XPL_BUILD obj-y += cmd_stm32prog/ diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 04640e476e6..506ecac2ef0 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 5b027fad048..9acbc0689a9 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index a9ac49bc5d2..dfba57e7dc4 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -78,9 +78,7 @@ enum forced_boot_mode { #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 -#ifdef CONFIG_STM32MP15X #define STM32_DBGMCU_BASE 0x50081000 -#endif #define STM32_FMC2_BASE 0x58002000 #define STM32_IWDG2_BASE 0x5A002000 #define STM32_DDRCTRL_BASE 0x5A003000 @@ -110,6 +108,11 @@ enum forced_boot_mode { #define STM32_SDMMC2_BASE 0x58007000 #define STM32_SDMMC3_BASE 0x48004000 +#ifdef CONFIG_STM32MP13X +#define STM32_SYSRAM_BASE 0x2FFE0000 +#define STM32_SYSRAM_SIZE SZ_128K +#endif + #ifdef CONFIG_STM32MP15X #define STM32_SYSRAM_BASE 0x2FFC0000 #define STM32_SYSRAM_SIZE SZ_256K diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 18175fd12cc..8c09d91de05 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -330,8 +330,7 @@ static uintptr_t nt_fw_dtb __section(".data"); void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, unsigned long r3) { - if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY)) - rom_api_table = r0; + rom_api_table = r0; if (IS_ENABLED(CONFIG_TFABOOT)) nt_fw_dtb = r2; @@ -350,7 +349,7 @@ uintptr_t get_stm32mp_bl2_dtb(void) } #ifdef CONFIG_XPL_BUILD -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); uintptr_t romapi = get_stm32mp_rom_api_table(); diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index 4f1d783649b..07d99034861 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -64,10 +64,9 @@ * - boot instance = bit 31:16 * - boot device = bit 15:0 */ -#define BOOTROM_PARAM_ADDR 0x2FFC0078 #define BOOTROM_MODE_MASK GENMASK(15, 0) #define BOOTROM_MODE_SHIFT 0 -#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) #define BOOTROM_INSTANCE_SHIFT 16 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ @@ -189,7 +188,7 @@ void spl_board_init(void) static void update_bootmode(void) { u32 boot_mode; - u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); + u32 bootrom_itf = readl(get_stm32mp_rom_api_table()); u32 bootrom_device, bootrom_instance; /* enable TAMP clock = RTCAPBEN */ diff --git a/arch/arm/mach-stm32mp/tamp_nvram.c b/arch/arm/mach-stm32mp/tamp_nvram.c new file mode 100644 index 00000000000..17a4f4ff44b --- /dev/null +++ b/arch/arm/mach-stm32mp/tamp_nvram.c @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ +#define LOG_CATEGORY UCLASS_MISC + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RIF_CID1 0x1 +#define CURRENT_CID RIF_CID1 +#define NB_ZONES_STM32MP1 3 +#define NB_ZONES_STM32MP2 7 + +#define _TAMP_SECCFGR 0x20U +#define _TAMP_BKPRIFR(x) (0x70U + 0x4U * ((x) - 1)) +#define _TAMP_RXCIDCFGR(x) (0x80U + 0x4U * ((x))) + +#define BKPREG_PROTECTION_ZONE_1 0 +#define BKPREG_PROTECTION_ZONE_2 1 +#define BKPREG_PROTECTION_ZONE_3 2 + +#define BKPREG_PROTECTION_ZONE_1_RIF1 0 +#define BKPREG_PROTECTION_ZONE_1_RIF2 1 +#define BKPREG_PROTECTION_ZONE_2_RIF1 2 +#define BKPREG_PROTECTION_ZONE_2_RIF2 3 +#define BKPREG_PROTECTION_ZONE_3_RIF1 4 +#define BKPREG_PROTECTION_ZONE_3_RIF0 5 +#define BKPREG_PROTECTION_ZONE_3_RIF2 6 +#define NB_COMPARTMENT_STM32MP2 3 + +enum stm32_tamp_bkpreg_access { + BKP_READ_WRITE, + BKP_READ, + BKP_NO +}; + +struct stm32_tamp_nvram_plat { + void __iomem *base; + void __iomem *parent_base; + fdt_size_t size; + fdt_size_t parent_size; + unsigned int nb_total_regs; +}; + +struct stm32_tamp_nvram_priv { + int *idx_bkpreg_zones_end; + struct regmap *config_regmap; + struct regmap *bkpregs_regmap; + const enum stm32_tamp_bkpreg_access *bkpreg_access; +}; + +struct stm32_tamp_nvram_drvdata { + const unsigned int nb_zones; + const struct reg_field *reg_fields; + const enum stm32_tamp_bkpreg_access *(*get_access)(struct udevice *dev); +}; + +static const struct reg_field stm32mp1_tamp_nvram_zone_cfg_fields[NB_ZONES_STM32MP1 - 1] = { + [BKPREG_PROTECTION_ZONE_1] = REG_FIELD(_TAMP_SECCFGR, 0, 7), + [BKPREG_PROTECTION_ZONE_2] = REG_FIELD(_TAMP_SECCFGR, 16, 23), +}; + +static const struct reg_field stm32mp2_tamp_nvram_zone_cfg_fields[NB_ZONES_STM32MP2 - 1] = { + [BKPREG_PROTECTION_ZONE_1_RIF1] = REG_FIELD(_TAMP_BKPRIFR(1), 0, 7), + [BKPREG_PROTECTION_ZONE_1_RIF2] = REG_FIELD(_TAMP_SECCFGR, 0, 7), + [BKPREG_PROTECTION_ZONE_2_RIF1] = REG_FIELD(_TAMP_BKPRIFR(2), 0, 7), + [BKPREG_PROTECTION_ZONE_2_RIF2] = REG_FIELD(_TAMP_SECCFGR, 16, 23), + [BKPREG_PROTECTION_ZONE_3_RIF1] = REG_FIELD(_TAMP_BKPRIFR(3), 0, 7), + [BKPREG_PROTECTION_ZONE_3_RIF0] = REG_FIELD(_TAMP_BKPRIFR(3), 16, 23), +}; + +static const struct reg_field stm32mp2_tamp_nvram_rxcidcfg_cfen_fields[NB_COMPARTMENT_STM32MP2] = { + REG_FIELD(_TAMP_RXCIDCFGR(0), 0, 0), + REG_FIELD(_TAMP_RXCIDCFGR(1), 0, 0), + REG_FIELD(_TAMP_RXCIDCFGR(2), 0, 0), +}; + +static const struct reg_field stm32mp2_tamp_nvram_rxcidcfg_fields[NB_COMPARTMENT_STM32MP2] = { + REG_FIELD(_TAMP_RXCIDCFGR(0), 4, 6), + REG_FIELD(_TAMP_RXCIDCFGR(1), 4, 6), + REG_FIELD(_TAMP_RXCIDCFGR(2), 4, 6), +}; + +static const enum stm32_tamp_bkpreg_access stm32mp1_tamp_bkpreg_access[NB_ZONES_STM32MP1] = { + [BKPREG_PROTECTION_ZONE_1] = BKP_NO, + [BKPREG_PROTECTION_ZONE_2] = BKP_READ, + [BKPREG_PROTECTION_ZONE_3] = BKP_READ_WRITE, +}; + +static const enum stm32_tamp_bkpreg_access *stm32mp1_tamp_get_access_rights(struct udevice *dev) +{ + return stm32mp1_tamp_bkpreg_access; +} + +static int stm32mp2_tamp_is_compartment_isolation_enabled(struct udevice *dev) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + int nb_compartment_enabled = 0; + u32 cfen; + struct regmap_field *cfen_field; + + for (int i = 0; i < NB_COMPARTMENT_STM32MP2; i++) { + cfen_field = devm_regmap_field_alloc(dev, + priv->config_regmap, + stm32mp2_tamp_nvram_rxcidcfg_cfen_fields[i]); + if (IS_ERR_OR_NULL(cfen_field)) { + dev_err(dev, "Can't allocate field for reading configuration\n"); + return -ENOMEM; + } + if (regmap_field_read(cfen_field, &cfen) != 0) { + dev_err(dev, "Can't read field for registers zones\n"); + devm_regmap_field_free(dev, cfen_field); + return -EINVAL; + } + nb_compartment_enabled += cfen; + devm_regmap_field_free(dev, cfen_field); + } + + if (nb_compartment_enabled == 0) + return 0; + else if (nb_compartment_enabled == NB_COMPARTMENT_STM32MP2) + return 1; + else + return -EINVAL; +} + +static bool *stm32mp2_tamp_get_compartment_owner(struct udevice *dev) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + struct regmap_field *cid_field; + u32 cid_per_zone; + int isolation_enabled; + bool *compartment_owner; + + isolation_enabled = stm32mp2_tamp_is_compartment_isolation_enabled(dev); + if (isolation_enabled < 0) + return NULL; + + compartment_owner = devm_kcalloc(dev, + NB_COMPARTMENT_STM32MP2, + sizeof(*compartment_owner), + GFP_KERNEL); + if (!compartment_owner) + return ERR_PTR(-ENOMEM); + + for (int i = 0; i < NB_COMPARTMENT_STM32MP2; i++) { + if (isolation_enabled) { + cid_field = devm_regmap_field_alloc(dev, + priv->config_regmap, + stm32mp2_tamp_nvram_rxcidcfg_fields[i] + ); + + if (regmap_field_read(cid_field, &cid_per_zone) != 0) { + dev_err(dev, "Can't read field for registers zones\n"); + devm_regmap_field_free(dev, cid_field); + devm_kfree(dev, compartment_owner); + return ERR_PTR(-EINVAL); + } + if (cid_per_zone == CURRENT_CID) + compartment_owner[i] = true; + else + compartment_owner[i] = false; + + devm_regmap_field_free(dev, cid_field); + } else { + compartment_owner[i] = true; + } + } + + return compartment_owner; +} + +static const enum stm32_tamp_bkpreg_access *stm32mp2_tamp_get_access_rights(struct udevice *dev) +{ + struct stm32_tamp_nvram_drvdata *drvdata = + (struct stm32_tamp_nvram_drvdata *)dev_get_driver_data(dev); + unsigned int nb_zones = drvdata->nb_zones; + bool *compartment_owner; + enum stm32_tamp_bkpreg_access *bkpreg_access; + + compartment_owner = stm32mp2_tamp_get_compartment_owner(dev); + if (IS_ERR(compartment_owner)) + return ERR_PTR(-ENODEV); + + bkpreg_access = devm_kcalloc(dev, + NB_ZONES_STM32MP2, + sizeof(*bkpreg_access), + GFP_KERNEL); + + for (int protection_zone_idx = 0; protection_zone_idx < nb_zones; + protection_zone_idx++) { + switch (protection_zone_idx) { + case BKPREG_PROTECTION_ZONE_1_RIF1: + bkpreg_access[protection_zone_idx] = BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_1_RIF2: + bkpreg_access[protection_zone_idx] = BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_2_RIF1: + if (compartment_owner[1] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] = BKP_READ; + else + bkpreg_access[protection_zone_idx] = BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_2_RIF2: + if (compartment_owner[1] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] = BKP_READ; + else + bkpreg_access[protection_zone_idx] = BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_3_RIF1: + if (compartment_owner[1]) + bkpreg_access[protection_zone_idx] = BKP_READ_WRITE; + else if (compartment_owner[0] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] = BKP_READ; + else + bkpreg_access[protection_zone_idx] = BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_3_RIF0: + if (compartment_owner[0]) + bkpreg_access[protection_zone_idx] = BKP_READ_WRITE; + else if (compartment_owner[1] || compartment_owner[2]) + bkpreg_access[protection_zone_idx] = BKP_READ; + else + bkpreg_access[protection_zone_idx] = BKP_NO; + break; + case BKPREG_PROTECTION_ZONE_3_RIF2: + if (compartment_owner[2]) + bkpreg_access[protection_zone_idx] = BKP_READ_WRITE; + else if (compartment_owner[0] || compartment_owner[1]) + bkpreg_access[protection_zone_idx] = BKP_READ; + else + bkpreg_access[protection_zone_idx] = BKP_NO; + break; + default: + devm_kfree(dev, bkpreg_access); + return ERR_PTR(-ENODEV); + } + } + + return bkpreg_access; +} + +static const struct stm32_tamp_nvram_drvdata stm32mp1_tamp_nvram = { + .nb_zones = NB_ZONES_STM32MP1, + .reg_fields = stm32mp1_tamp_nvram_zone_cfg_fields, + .get_access = stm32mp1_tamp_get_access_rights, +}; + +static const struct stm32_tamp_nvram_drvdata stm32mp2_tamp_nvram = { + .nb_zones = NB_ZONES_STM32MP2, + .reg_fields = stm32mp2_tamp_nvram_zone_cfg_fields, + .get_access = stm32mp2_tamp_get_access_rights, +}; + +static int stm32_tamp_nvram_bkpreg_get_zone_idx(struct udevice *dev, int reg) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + struct stm32_tamp_nvram_drvdata *drvdata = + (struct stm32_tamp_nvram_drvdata *)dev_get_driver_data(dev); + int *idx_bkpreg_zones_end = priv->idx_bkpreg_zones_end; + int nb_zones = drvdata->nb_zones; + int protection_zone_idx; + + if (reg < 0) + return -1; // negative reg is the boundary of an empty zone + + for (protection_zone_idx = 0; protection_zone_idx < nb_zones; protection_zone_idx++) { + if (reg <= idx_bkpreg_zones_end[protection_zone_idx]) + break; + } + + if (protection_zone_idx >= nb_zones) + return -1; // the reg is not a part of any zone + + return protection_zone_idx; +} + +static bool stm32_tamp_nvram_rights(struct udevice *dev, int reg, bool read_only) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + int protection_zone_idx = stm32_tamp_nvram_bkpreg_get_zone_idx(dev, reg); + + if (protection_zone_idx < 0) + return false; + + switch (priv->bkpreg_access[protection_zone_idx]) { + case BKP_READ_WRITE: + return true; + case BKP_READ: + return read_only; + case BKP_NO: + return false; + default: + dev_err(dev, "Can't get access rights for the zone\n"); + return false; + } + + return false; +} + +static int stm32_tamp_nvram_write_byte(struct udevice *dev, u32 offset, u8 byte) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + int offset_aligned = ALIGN_DOWN(offset, sizeof(u32)); + int byte_in_word = offset - offset_aligned; + u32 read_value, to_be_writen_value; + u32 reg_idx = offset_aligned / sizeof(u32); + + if (!stm32_tamp_nvram_rights(dev, reg_idx, false)) + return -EIO; + + regmap_read(priv->bkpregs_regmap, offset_aligned, &read_value); + to_be_writen_value = read_value & ~(0xFFUL << byte_in_word * 8); + to_be_writen_value |= (u32)byte << (byte_in_word * 8); + + return regmap_write(priv->bkpregs_regmap, offset_aligned, to_be_writen_value); +} + +static int stm32_tamp_nvram_read_byte(struct udevice *dev, unsigned int offset, u8 *byte) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + int offset_aligned = ALIGN_DOWN(offset, sizeof(u32)); + int byte_in_word = offset - offset_aligned; + u32 read_value; + u32 reg_idx = offset_aligned / sizeof(u32); + + if (!stm32_tamp_nvram_rights(dev, reg_idx, true)) + return -EIO; + + regmap_read(priv->bkpregs_regmap, offset_aligned, &read_value); + *byte = (read_value >> (byte_in_word * 8)) & 0xFF; + + return 0; +} + +static int stm32_tamp_nvram_read(struct udevice *dev, int offset, void *buf, int size) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + u8 byte; + u8 *buf_u8 = buf; + u32 temp_u32; + int i, ret; + int total = offset + size; + u32 reg_idx; + + i = offset; + while (i < total) { + reg_idx = i / sizeof(u32); + if (i + sizeof(u32) <= total && IS_ALIGNED(i, sizeof(u32))) { + if (!stm32_tamp_nvram_rights(dev, reg_idx, true)) { + dev_dbg(dev, "Backup register %u is not allowed to be read\n", + reg_idx); + temp_u32 = 0; + } else { + regmap_read(priv->bkpregs_regmap, i, &temp_u32); + } + memcpy(buf_u8, &temp_u32, sizeof(u32)); + buf_u8 += sizeof(u32); + i += sizeof(u32); + } else { + ret = stm32_tamp_nvram_read_byte(dev, i, &byte); + if (ret != 0) { + dev_dbg(dev, "Backup register %u is not allowed to be read\n", + reg_idx); + byte = 0; + } + *buf_u8 = byte; + i++; + buf_u8++; + } + } + + return size; +} + +static int stm32_tamp_nvram_write(struct udevice *dev, int offset, const void *buf, int size) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + u8 *buf_u8 = (u8 *)buf; + u32 temp_u32; + size_t total = offset + size; + int i, ret; + u32 reg_idx; + + i = offset; + while (i < total) { + reg_idx = i / sizeof(u32); + if (i + sizeof(u32) <= total && IS_ALIGNED(i, sizeof(u32))) { + if (stm32_tamp_nvram_rights(dev, reg_idx, false)) { + memcpy(&temp_u32, buf_u8, sizeof(u32)); + regmap_write(priv->bkpregs_regmap, i, temp_u32); + } else { + dev_dbg(dev, "Backup register %u is not allowed to be written", + reg_idx); + } + buf_u8 += sizeof(u32); + i += sizeof(u32); + } else { + ret = stm32_tamp_nvram_write_byte(dev, i, *buf_u8); + if (ret != 0) + dev_dbg(dev, "Backup register %u is not allowed to be written", + reg_idx); + i++; + buf_u8++; + } + } + + return size; +} + +static const struct misc_ops stm32_tamp_nvram_ops = { + .read = stm32_tamp_nvram_read, + .write = stm32_tamp_nvram_write, +}; + +static u32 *stm32_tamp_nvram_get_backup_zones(struct udevice *dev) +{ + struct stm32_tamp_nvram_plat *plat = dev_get_plat(dev); + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + const struct stm32_tamp_nvram_drvdata *drvdata = + (struct stm32_tamp_nvram_drvdata *)dev_get_driver_data(dev); + int nb_zones = drvdata->nb_zones; + int zone_idx; + int *idx_bkpreg_zones_end; + struct regmap *tamp_regmap = priv->config_regmap; + u32 offset_field; + + idx_bkpreg_zones_end = devm_kcalloc(dev, + sizeof(*idx_bkpreg_zones_end), + nb_zones, + GFP_KERNEL); + if (IS_ERR_OR_NULL(idx_bkpreg_zones_end)) { + dev_err(dev, "Can't allocate registers zones\n"); + return ERR_PTR(-ENOMEM); + } + + //Get the n-1 frontiers of zone within the tamp configuration registers + for (zone_idx = 0; zone_idx < nb_zones - 1; zone_idx++) { + const struct reg_field reg_field = drvdata->reg_fields[zone_idx]; + struct regmap_field *field = devm_regmap_field_alloc(dev, + tamp_regmap, + reg_field); + + if (IS_ERR_OR_NULL(field)) { + dev_err(dev, "Can't allocate registers zones\n"); + devm_kfree(dev, idx_bkpreg_zones_end); + return ERR_PTR(-ENOMEM); + } + if (regmap_field_read(field, &offset_field) != 0) { + dev_err(dev, "Can't read field for registers zones\n"); + devm_kfree(dev, idx_bkpreg_zones_end); + return ERR_PTR(-EIO); + } + + idx_bkpreg_zones_end[zone_idx] = offset_field - 1; + } + + //The last zone end is defined by the number of registers in TAMP + idx_bkpreg_zones_end[zone_idx] = plat->nb_total_regs - 1; + + return idx_bkpreg_zones_end; +} + +static void stm32_tamp_nvram_print_zones(struct udevice *dev) +{ + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + int *zones_end = priv->idx_bkpreg_zones_end; + + if (device_is_compatible(dev, "st,stm32mp25-tamp-nvram")) { + dev_dbg(dev, + "\n" + "Zone 1-RIF1 %3d - %3d %c%c\n" + "Zone 1-RIF2 %3d - %3d %c%c\n" + "Zone 2-RIF1 %3d - %3d %c%c\n" + "Zone 2-RIF2 %3d - %3d %c%c\n" + "Zone 3-RIF1 %3d - %3d %c%c\n" + "Zone 3-RIF0 %3d - %3d %c%c\n" + "Zone 3-RIF2 %3d - %3d %c%c\n", + 0, zones_end[BKPREG_PROTECTION_ZONE_1_RIF1], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_1_RIF1], + true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_1_RIF1], + false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_1_RIF1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_1_RIF2], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_1_RIF2], + true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_1_RIF2], + false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_1_RIF2] + 1, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF1], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_2_RIF1], + true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_2_RIF1], + false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_2_RIF1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_2_RIF2], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_2_RIF2], + true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_2_RIF2], + false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_2_RIF2] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF1], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3_RIF1], + true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3_RIF1], + false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_3_RIF1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF0], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3_RIF0], + true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3_RIF0], + false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_3_RIF0] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3_RIF2], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3_RIF2], + true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3_RIF2], + false) ? + 'W' : + '-'); + } else if (device_is_compatible(dev, "st,stm32mp15-tamp-nvram")) { + dev_dbg(dev, + "\n" + "Zone 1 %3d - %3d %c%c\n" + "Zone 2 %3d - %3d %c%c\n" + "Zone 3 %3d - %3d %c%c\n", + 0, zones_end[BKPREG_PROTECTION_ZONE_1], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_1], true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_1], false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_1] + 1, + zones_end[BKPREG_PROTECTION_ZONE_2], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_2], true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_2], false) ? + 'W' : + '-', + zones_end[BKPREG_PROTECTION_ZONE_2] + 1, + zones_end[BKPREG_PROTECTION_ZONE_3], + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3], true) ? + 'R' : + '-', + stm32_tamp_nvram_rights(dev, zones_end[BKPREG_PROTECTION_ZONE_3], false) ? + 'W' : + '-'); + } +} + +static int stm32_tamp_nvram_of_to_plat(struct udevice *dev) +{ + struct stm32_tamp_nvram_plat *plat = dev_get_plat(dev); + fdt_addr_t addr = dev_read_addr_size_index(dev, 0, &plat->size); + fdt_addr_t parent_addr = dev_read_addr_size_index(dev->parent, 0, &plat->parent_size); + + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->base = (void __iomem *)addr; + + if (parent_addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->parent_base = (void __iomem *)parent_addr; + + if (plat->size == FDT_ADDR_T_NONE) + return -EOPNOTSUPP; + + plat->nb_total_regs = plat->size / sizeof(uint32_t); + + return 0; +} + +static int stm32_tamp_nvram_probe(struct udevice *dev) +{ + struct stm32_tamp_nvram_plat *plat = dev_get_plat(dev); + struct stm32_tamp_nvram_priv *priv = dev_get_priv(dev); + struct regmap_config config_regmap; + struct regmap_config bckreg_regmap; + const struct stm32_tamp_nvram_drvdata *drvdata = + (struct stm32_tamp_nvram_drvdata *)dev_get_driver_data(dev); + + config_regmap.r_start = (ulong)(plat->parent_base); + config_regmap.r_size = plat->parent_size; + config_regmap.reg_offset_shift = 0; + config_regmap.width = REGMAP_SIZE_32; + priv->config_regmap = devm_regmap_init(dev, NULL, NULL, &config_regmap); + + bckreg_regmap.r_start = (ulong)(plat->base); + bckreg_regmap.r_size = plat->size; + bckreg_regmap.reg_offset_shift = 0; + bckreg_regmap.width = REGMAP_SIZE_32; + priv->bkpregs_regmap = devm_regmap_init(dev, NULL, NULL, &bckreg_regmap); + + priv->idx_bkpreg_zones_end = stm32_tamp_nvram_get_backup_zones(dev); + if (IS_ERR_OR_NULL(priv->idx_bkpreg_zones_end)) { + dev_err(dev, "Failed to get the backup zone from tamp regs\n\n"); + return -ENODEV; + } + + priv->bkpreg_access = drvdata->get_access(dev); + stm32_tamp_nvram_print_zones(dev); + + return 0; +} + +static int stm32_tamp_nvram_remove(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id stm32_tamp_nvram_ids[] = { + { .compatible = "st,stm32mp15-tamp-nvram", .data = (ulong)&stm32mp1_tamp_nvram }, + { .compatible = "st,stm32mp25-tamp-nvram", .data = (ulong)&stm32mp2_tamp_nvram }, + {}, +}; + +U_BOOT_DRIVER(stm32_tamp_nvram) = { + .name = "stm32_tamp_nvram", + .id = UCLASS_MISC, + .of_match = stm32_tamp_nvram_ids, + .priv_auto = sizeof(struct stm32_tamp_nvram_priv), + .plat_auto = sizeof(struct stm32_tamp_nvram_plat), + .ops = &stm32_tamp_nvram_ops, + .of_to_plat = of_match_ptr(stm32_tamp_nvram_of_to_plat), + .probe = stm32_tamp_nvram_probe, + .remove = stm32_tamp_nvram_remove, +}; diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 17179593913..0a7c029b15a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -51,7 +51,13 @@ config DRAM_SUN50I_H616 Select this dram controller driver for some sun50i platforms, like H616. -if DRAM_SUN50I_H616 +config DRAM_SUN50I_A133 + bool + help + Select this dram controller driver for some sun50i platforms, + like A133. + +if DRAM_SUN50I_H616 || DRAM_SUN50I_A133 config DRAM_SUNXI_DX_ODT hex "DRAM DX ODT parameter" help @@ -73,18 +79,64 @@ config DRAM_SUNXI_ODT_EN help ODT EN value from vendor DRAM settings. +config DRAM_SUNXI_PARA0 + hex "DRAM PARA0 parameter" + depends on DRAM_SUN50I_A133 + help + PARA0 value from vendor DRAM settings. + +config DRAM_SUNXI_MR11 + hex "DRAM MR11 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + MR11 value from vendor DRAM settings. + +config DRAM_SUNXI_MR12 + hex "DRAM MR12 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + MR12 value from vendor DRAM settings. + +config DRAM_SUNXI_MR13 + hex "DRAM MR13 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + MR13 value from vendor DRAM settings. + +config DRAM_SUNXI_MR14 + hex "DRAM MR14 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + MR14 value from vendor DRAM settings. + config DRAM_SUNXI_TPR0 hex "DRAM TPR0 parameter" default 0x0 help TPR0 value from vendor DRAM settings. +config DRAM_SUNXI_TPR1 + hex "DRAM TPR1 parameter" + default 0x0 + help + TPR1 value from vendor DRAM settings. + config DRAM_SUNXI_TPR2 hex "DRAM TPR2 parameter" default 0x0 help TPR2 value from vendor DRAM settings. +config DRAM_SUNXI_TPR3 + hex "DRAM TPR3 parameter" + default 0x0 + help + TPR3 value from vendor DRAM settings. + config DRAM_SUNXI_TPR6 hex "DRAM TPR6 parameter" default 0x3300c080 @@ -109,6 +161,20 @@ config DRAM_SUNXI_TPR12 help TPR12 value from vendor DRAM settings. +config DRAM_SUNXI_TPR13 + hex "DRAM TPR13 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + TPR13 value from vendor DRAM settings. + +config DRAM_SUNXI_TPR14 + hex "DRAM TPR14 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + TPR14 value from vendor DRAM settings. + choice prompt "DRAM PHY pin mapping selection" default DRAM_SUNXI_PHY_ADDR_MAP_0 @@ -116,7 +182,8 @@ choice config DRAM_SUNXI_PHY_ADDR_MAP_0 bool "DRAM PHY address map 0" help - This pin mapping selection should be used by the H313, H616, H618. + This pin mapping selection should be used by the H313, H616, H618, + and A133, R818 SoCs. config DRAM_SUNXI_PHY_ADDR_MAP_1 bool "DRAM PHY address map 1" @@ -153,6 +220,7 @@ config SUNXI_SRAM_ADDRESS config SUNXI_RVBAR_ADDRESS hex depends on ARM64 + default 0x08100040 if MACH_SUN50I_A133 default 0x09010040 if SUN50I_GEN_H6 default 0x017000a0 ---help--- @@ -179,8 +247,8 @@ config SUNXI_RVBAR_ALTERNATIVE config SUNXI_BL31_BASE hex default 0x00044000 if MACH_SUN50I || MACH_SUN50I_H5 - default 0x00104000 if MACH_SUN50I_H6 default 0x40000000 if MACH_SUN50I_H616 + default 0x00104000 if SUN50I_GEN_H6 default 0x0 help Address where BL31 (TF-A) is loaded, or zero if BL31 is not used. @@ -262,7 +330,7 @@ config MACH_SUNXI_H3_H5 # TODO: try out A80's 8GiB DRAM space config SUNXI_DRAM_MAX_SIZE hex - default 0x100000000 if MACH_SUN50I_H616 + default 0x100000000 if MACH_SUN50I_H616 || MACH_SUN50I_A133 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 default 0x80000000 @@ -459,6 +527,10 @@ config MACH_SUN50I_H616 config MACH_SUN50I_A133 bool "sun50i (Allwinner A133)" + select ARM64 + select DRAM_SUN50I_A133 + select SUN50I_GEN_H6 + imply OF_UPSTREAM endchoice @@ -497,7 +569,7 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed. -if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616 +if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616 || DRAM_SUN50I_A133 config SUNXI_DRAM_DDR3 bool @@ -510,6 +582,9 @@ config SUNXI_DRAM_LPDDR3 config SUNXI_DRAM_LPDDR4 bool +config SUNXI_DRAM_DDR4 + bool + choice prompt "DRAM Type and Timing" default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S @@ -518,6 +593,7 @@ choice config SUNXI_DRAM_DDR3_1333 bool "DDR3 1333" select SUNXI_DRAM_DDR3 + depends on !DRAM_SUN50I_A133 ---help--- This option is the original only supported memory type, which suits many H3/H5/A64 boards available now. @@ -525,6 +601,7 @@ config SUNXI_DRAM_DDR3_1333 config SUNXI_DRAM_LPDDR3_STOCK bool "LPDDR3 with Allwinner stock configuration" select SUNXI_DRAM_LPDDR3 + depends on !DRAM_SUN50I_A133 ---help--- This option is the LPDDR3 timing used by the stock boot0 by Allwinner. @@ -548,7 +625,7 @@ config SUNXI_DRAM_H6_DDR3_1333 config SUNXI_DRAM_H616_LPDDR3 bool "LPDDR3 DRAM chips on the H616 DRAM controller" select SUNXI_DRAM_LPDDR3 - depends on DRAM_SUN50I_H616 + depends on DRAM_SUN50I_H616 || DRAM_SUN50I_A133 help This option is the LPDDR3 timing used by the stock boot0 by Allwinner. @@ -556,7 +633,7 @@ config SUNXI_DRAM_H616_LPDDR3 config SUNXI_DRAM_H616_LPDDR4 bool "LPDDR4 DRAM chips on the H616 DRAM controller" select SUNXI_DRAM_LPDDR4 - depends on DRAM_SUN50I_H616 + depends on DRAM_SUN50I_H616 || DRAM_SUN50I_A133 help This option is the LPDDR4 timing used by the stock boot0 by Allwinner. @@ -564,11 +641,27 @@ config SUNXI_DRAM_H616_LPDDR4 config SUNXI_DRAM_H616_DDR3_1333 bool "DDR3-1333 boot0 timings on the H616 DRAM controller" select SUNXI_DRAM_DDR3 - depends on DRAM_SUN50I_H616 + depends on DRAM_SUN50I_H616 || DRAM_SUN50I_A133 help This option is the DDR3 timing used by the boot0 on H616 TV boxes which use a DDR3-1333 timing. +config SUNXI_DRAM_A133_DDR4 + bool "DDR4 boot0 timings on the A133 DRAM controller" + select SUNXI_DRAM_DDR4 + depends on DRAM_SUN50I_A133 + help + This option is the DDR4 timing used by the boot0 on A133 devices + which use a DDR4 timing. + +config SUNXI_DRAM_A133_LPDDR4 + bool "LPDDR4 boot0 timings on the A133 DRAM controller" + select SUNXI_DRAM_LPDDR4 + depends on DRAM_SUN50I_A133 + help + This option is the LPDDR4 timing used by the boot0 on A133 devices + which use an LPDDR4 timing. + config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 @@ -596,7 +689,7 @@ config DRAM_CLK MACH_SUN8I_V3S default 672 if MACH_SUN50I default 744 if MACH_SUN50I_H6 - default 720 if MACH_SUN50I_H616 + default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133 ---help--- Set the dram clock speed, valid range 240 - 480 (prior to sun9i), must be a multiple of 24. For the sun9i (A80), the tested values @@ -613,7 +706,7 @@ endif config DRAM_ZQ int "sunxi dram zq value" - depends on !MACH_SUN50I_H616 + depends on !MACH_SUN50I_H616 && !MACH_SUN50I_A133 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T default 127 if MACH_SUN7I @@ -733,6 +826,7 @@ config SYS_CONFIG_NAME default "sun50i" if MACH_SUN50I default "sun50i" if MACH_SUN50I_H6 default "sun50i" if MACH_SUN50I_H616 + default "sun50i" if MACH_SUN50I_A133 config SYS_BOARD default "sunxi" diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index a33cd5b0f07..8eff20b77bf 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -45,4 +45,6 @@ obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/ obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/ +obj-$(CONFIG_DRAM_SUN50I_A133) += dram_sun50i_a133.o +obj-$(CONFIG_DRAM_SUN50I_A133) += dram_timings/ endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index b1bf51f40c5..08d55b3a0e3 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -137,6 +137,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_A133) + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN50I_H616_GPH_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 4c522f60810..3f375a51965 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -87,7 +87,8 @@ void clock_set_pll1(unsigned int clk) /* clk = 24*n/p, p is ignored if clock is >288MHz */ val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2; val |= CCM_PLL1_CTRL_N(clk / 24000000); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || + IS_ENABLED(CONFIG_MACH_SUN50I_A133)) val |= CCM_PLL1_OUT_EN; if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN; diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 310dca06e57..3f4735d4717 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -104,6 +104,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner H6 (SUN50I)\n"); #elif defined CONFIG_MACH_SUN50I_H616 puts("CPU: Allwinner H616 (SUN50I)\n"); +#elif defined CONFIG_MACH_SUN50I_A133 + puts("CPU: Allwinner A133 (SUN50I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c new file mode 100644 index 00000000000..a0fca3738f4 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c @@ -0,0 +1,1204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * sun50i A133 platform dram controller driver + * + * Controller and PHY appear to be quite similar to that of the H616; + * however certain offsets, timings, and other details are different enough that + * the original code does not work as expected. Some device flags and + * calibrations are not yet implemented, and configuration aside from DDR4 + * have not been tested. + * + * (C) Copyright 2024 MasterR3C0RD + * + * Uses code from H616 driver, which is + * (C) Copyright 2020 Jernej Skrabec + * + */ + +//#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1 +static const u8 phy_init[] = { +#ifdef CONFIG_SUNXI_DRAM_DDR3 + 0x0c, 0x08, 0x19, 0x18, 0x10, 0x06, 0x0a, 0x03, 0x0e, + 0x00, 0x0b, 0x05, 0x09, 0x1a, 0x04, 0x13, 0x16, 0x11, + 0x01, 0x15, 0x0d, 0x07, 0x12, 0x17, 0x14, 0x02, 0x0f +#elif CONFIG_SUNXI_DRAM_DDR4 + 0x19, 0x1a, 0x04, 0x12, 0x09, 0x06, 0x08, 0x0a, 0x16, + 0x17, 0x18, 0x0f, 0x0c, 0x13, 0x02, 0x05, 0x01, 0x11, + 0x0e, 0x00, 0x0b, 0x07, 0x03, 0x14, 0x15, 0x0d, 0x10 +#elif CONFIG_SUNXI_DRAM_LPDDR3 + 0x08, 0x03, 0x02, 0x00, 0x18, 0x19, 0x09, 0x01, 0x06, + 0x17, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, + 0x12, 0x13, 0x14, 0x15, 0x16, 0x04, 0x05, 0x07, 0x1a +#elif CONFIG_SUNXI_DRAM_LPDDR4 + 0x01, 0x05, 0x02, 0x00, 0x19, 0x03, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, + 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x04, 0x1a +#endif +}; +#else +static const u8 phy_init[] = { +#ifdef CONFIG_SUNXI_DRAM_DDR3 + 0x03, 0x19, 0x18, 0x02, 0x10, 0x15, 0x16, 0x07, 0x06, + 0x0e, 0x05, 0x08, 0x0d, 0x04, 0x17, 0x1a, 0x13, 0x11, + 0x12, 0x14, 0x00, 0x01, 0x0c, 0x0a, 0x09, 0x0b, 0x0f +#elif CONFIG_SUNXI_DRAM_DDR4 + 0x13, 0x17, 0x0e, 0x01, 0x06, 0x12, 0x14, 0x07, 0x09, + 0x02, 0x0f, 0x00, 0x0d, 0x05, 0x16, 0x0c, 0x0a, 0x11, + 0x04, 0x03, 0x18, 0x15, 0x08, 0x10, 0x0b, 0x19, 0x1a +#elif CONFIG_SUNXI_DRAM_LPDDR3 + 0x05, 0x06, 0x17, 0x02, 0x19, 0x18, 0x04, 0x07, 0x03, + 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, + 0x12, 0x13, 0x14, 0x15, 0x16, 0x08, 0x09, 0x00, 0x1a +#elif CONFIG_SUNXI_DRAM_LPDDR4 + 0x01, 0x03, 0x02, 0x19, 0x17, 0x00, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, + 0x12, 0x13, 0x14, 0x15, 0x16, 0x04, 0x18, 0x05, 0x1a +#endif +}; +#endif + +static void mctl_clk_init(u32 clk) +{ + void * const ccm = (void *)SUNXI_CCM_BASE; + + /* Place all DRAM blocks into reset */ + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT)); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); + udelay(5); + + /* Set up PLL5 clock, used for DRAM */ + clrsetbits_le32(ccm + CCU_H6_PLL5_CFG, 0xff03, + CCM_PLL5_CTRL_N((clk * 2) / 24) | CCM_PLL5_CTRL_EN); + setbits_le32(ccm + CCU_H6_PLL5_CFG, BIT(24)); + clrsetbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3, + CCM_PLL5_LOCK_EN | CCM_PLL5_CTRL_EN | BIT(30)); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3 | BIT(30)); + mctl_await_completion(ccm + CCU_H6_PLL5_CFG, + CCM_PLL5_LOCK, CCM_PLL5_LOCK); + + /* Enable DRAM clock and gate*/ + clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, BIT(24) | BIT(25)); + clrsetbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, 0x1f, BIT(1) | BIT(0)); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_CLK_UPDATE); + setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT)); + setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); + + /* Re-enable MBUS and reset the DRAM module */ + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); + udelay(5); +} + +static void mctl_set_odtmap(const struct dram_para *para, + const struct dram_config *config) +{ + struct sunxi_mctl_ctl_reg *mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u32 val, temp1, temp2; + + /* Set ODT/rank mappings*/ + if (config->bus_full_width) + writel_relaxed(0x0201, &mctl_ctl->odtmap); + else + writel_relaxed(0x0303, &mctl_ctl->odtmap); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = 0x06000400; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + /* TODO: What's the purpose of these values? */ + temp1 = para->clk * 7 / 2000; + if (para->clk < 400) + temp2 = 0x3; + else + temp2 = 0x4; + + val = 0x400 | (temp2 - temp1) << 16 | temp1 << 24; + break; + case SUNXI_DRAM_TYPE_DDR4: + /* MR4: CS to CMD / ADDR Latency and write preamble */ + val = 0x400 | (0x000 << 10 & 0x70000) | + (((0x0000 >> 12) & 1) + 6) << 24; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + val = 0x4000400; + break; + } + + writel_relaxed(val, &mctl_ctl->odtcfg); + /* Documented as ODTCFG_SHADOW */ + writel_relaxed(val, &mctl_ctl->unk_0x2240); + /* Offset's interesting; additional undocumented shadows? */ + writel_relaxed(val, &mctl_ctl->unk_0x3240); + writel_relaxed(val, &mctl_ctl->unk_0x4240); +} + +/* + * This function produces address mapping parameters, used internally by the + * controller to map address lines to HIF addresses. HIF addresses are word + * addresses, not byte addresses; + * In other words, DDR address 0x400 maps to HIF address 0x100. + * + * This implementation sets up a reasonable mapping where HIF address + * ordering (LSB->MSB) is as such: + * - Bank Groups + * - Columns + * - Banks + * - Rows + * - Ranks + * + * TODO: Handle 1.5GB + 3GB configurations. Info about these is stored in + * upper bits of TPR13 after autoscan in boot0, and then some extra logic + * happens in the address mapping + */ +#define INITIAL_HIF_OFFSET 3 + +static void mctl_set_addrmap(const struct dram_config *config) +{ + struct sunxi_mctl_ctl_reg *mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 bankgrp_bits = config->bankgrps; + u8 col_bits = config->cols; + u8 bank_bits = config->banks; + u8 row_bits = config->rows; + u8 rank_bits = config->ranks; + + unsigned int i, hif_offset, hif_bits[6]; + + /* + * When the bus is half width, we need to adjust address mapping, + * as COL[0] will be reallocated as part of the byte address, + * offsetting the column address mapping values by 1 + */ + if (!config->bus_full_width) + col_bits--; + + /* Match boot0's DRAM requirements */ + if (bankgrp_bits > 2) + panic("invalid dram configuration (bankgrps_bits = %d)", + bankgrp_bits); + if (col_bits < 8 || col_bits > 12) + panic("invalid dram configuration (col_bits = %d)", col_bits); + + if (bank_bits < 2 || bank_bits > 3) + panic("invalid dram configuration (bank_bits = %d)", bank_bits); + + if (row_bits < 14 || row_bits > 18) + panic("invalid dram configuration (row_bits = %d)", row_bits); + + if (rank_bits > 1) + panic("invalid dram configuration (rank_bits = %d)", rank_bits); + + /* + * Col[0:1] + HIF[0:1] (hardwired), Col[2] = HIF[2] (required) + * Thus, we start allocating from HIF[3] onwards + */ + hif_offset = INITIAL_HIF_OFFSET; + + /* BG[bankgrp_bits:0] = HIF[3 + bankgrp_bits:3]*/ + switch (bankgrp_bits) { + case 0: + writel_relaxed(ADDRMAP8_BG0_B2(ADDRMAP_DISABLED_1F_B(2)) | + ADDRMAP8_BG1_B3(ADDRMAP_DISABLED_1F_B(3)), + &mctl_ctl->addrmap[8]); + break; + case 1: + writel_relaxed(ADDRMAP8_BG0_B2(hif_offset) | + ADDRMAP8_BG1_B3(ADDRMAP_DISABLED_1F_B(3)), + &mctl_ctl->addrmap[8]); + break; + case 2: + writel_relaxed(ADDRMAP8_BG0_B2(hif_offset) | + ADDRMAP8_BG1_B3(hif_offset + 1), + &mctl_ctl->addrmap[8]); + break; + default: + panic("invalid dram configuration (bankgrp_bits = %d)", + bankgrp_bits); + } + + hif_offset += bankgrp_bits; + + /* Col[2] = HIF[2], Col[5:3] = HIF[offset + 2:offset] */ + writel_relaxed(ADDRMAP2_COL2_B2(2) | ADDRMAP2_COL3_B3(hif_offset) | + ADDRMAP2_COL4_B4(hif_offset + 1) | + ADDRMAP2_COL5_B5(hif_offset + 2), + &mctl_ctl->addrmap[2]); + + /* Col[col_bits:6] = HIF[col_bits + offset - 3:offset - 3] */ + for (i = 6; i < 12; i++) { + if (i < col_bits) + hif_bits[i - 6] = hif_offset + (i - INITIAL_HIF_OFFSET); + else + hif_bits[i - 6] = ADDRMAP_DISABLED_1F_B(i); + } + + writel_relaxed(ADDRMAP3_COL6_B6(hif_bits[0]) | + ADDRMAP3_COL7_B7(hif_bits[1]) | + ADDRMAP3_COL8_B8(hif_bits[2]) | + ADDRMAP3_COL9_B9(hif_bits[3]), + &mctl_ctl->addrmap[3]); + + writel_relaxed(ADDRMAP4_COL10_B10(hif_bits[4]) | + ADDRMAP4_COL11_B11(hif_bits[5]), + &mctl_ctl->addrmap[4]); + + hif_offset = bankgrp_bits + col_bits; + + /* Bank[bank_bits:0] = HIF[bank_bits + offset:offset] */ + if (bank_bits == 3) + writel_relaxed(ADDRMAP1_BANK0_B2(hif_offset) | + ADDRMAP1_BANK1_B3(hif_offset + 1) | + ADDRMAP1_BANK2_B4(hif_offset + 2), + &mctl_ctl->addrmap[1]); + else + writel_relaxed(ADDRMAP1_BANK0_B2(hif_offset) | + ADDRMAP1_BANK1_B3(hif_offset + 1) | + ADDRMAP1_BANK2_B4(ADDRMAP_DISABLED_1F_B(4)), + &mctl_ctl->addrmap[1]); + + hif_offset += bank_bits; + + /* Row[11:0] = HIF[11 + offset:offset] */ + writel_relaxed(ADDRMAP5_ROW0_B6(hif_offset) | + ADDRMAP5_ROW1_B7(hif_offset + 1) | + ADDRMAP5_ROW2_10_B8(hif_offset + 2) | + ADDRMAP5_ROW11_B17(hif_offset + 11), + &mctl_ctl->addrmap[5]); + + /* + * There's some complexity here because of a special case + * in boot0 code that appears to work around a hardware bug. + * For (col_bits, row_bits, rank_bits) = (10, 16, 1), we have to + * place CS[0] in the position we would normally place ROW[14], + * and shift ROW[14] and ROW[15] over by one. Using the bit following + * ROW[15], as would be standard here, seems to cause nonsensical + * aliasing patterns. + * + * Aside from this case, mapping is simple: + * Row[row_bits:12] = HIF[offset + row_bits:offset + 12] + */ + for (i = 12; i < 18; i++) { + if (i >= row_bits) + hif_bits[i - 12] = ADDRMAP_DISABLED_0F_B(6 + i); + else if (rank_bits != 1 || col_bits != 10 || row_bits != 16 || + i < 14) + hif_bits[i - 12] = hif_offset + i; + else + hif_bits[i - 12] = hif_offset + i + 1; + } + + writel_relaxed(ADDRMAP6_ROW12_B18(hif_bits[0]) | + ADDRMAP6_ROW13_B19(hif_bits[1]) | + ADDRMAP6_ROW14_B20(hif_bits[2]) | + ADDRMAP6_ROW15_B21(hif_bits[3]), + &mctl_ctl->addrmap[6]); + + writel_relaxed(ADDRMAP7_ROW16_B22(hif_bits[4]) | + ADDRMAP7_ROW17_B23(hif_bits[5]), + &mctl_ctl->addrmap[7]); + + hif_offset += row_bits; + + /* + * Ranks + * Most cases: CS[0] = HIF[offset] + * Special case (see above): CS[0] = HIF[offset - 2] + */ + if (rank_bits == 0) + writel_relaxed(ADDRMAP0_CS0_B6(ADDRMAP_DISABLED_1F_B(6)), + &mctl_ctl->addrmap[0]); + else if (col_bits == 10 && row_bits == 16) + writel_relaxed(ADDRMAP0_CS0_B6(hif_offset - 2), + &mctl_ctl->addrmap[0]); + else + writel_relaxed(ADDRMAP0_CS0_B6(hif_offset), + &mctl_ctl->addrmap[0]); +} + +static void mctl_com_init(const struct dram_para *para, + const struct dram_config *config) +{ + void *const mctl_com = (void *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg *mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + /* Might control power/reset of DDR-related blocks */ + clrsetbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(24), BIT(25) | BIT(9)); + + /* Unlock mctl_ctl registers */ + setbits_le32(mctl_com + MCTL_COM_MAER0, BIT(15)); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + setbits_le32(0x03102ea8, BIT(0)); + + clrsetbits_le32(&mctl_ctl->sched[0], 0xff << 8, 0x30 << 8); + if (!(para->tpr13 & BIT(28))) + clrsetbits_le32(&mctl_ctl->sched[0], 0xf, BIT(0)); + + writel_relaxed(0, &mctl_ctl->hwlpctl); + + /* Master settings */ + u32 mstr_value = MSTR_DEVICECONFIG_X32 | + MSTR_ACTIVE_RANKS(config->ranks); + + if (config->bus_full_width) + mstr_value |= MSTR_BUSWIDTH_FULL; + else + mstr_value |= MSTR_BUSWIDTH_HALF; + + /* + * Geardown and 2T mode are always enabled here, but is controlled by a flag in boot0; + * it has not been a problem so far, but may be suspect if a particular board isn't booting. + */ + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + mstr_value |= MSTR_DEVICETYPE_DDR3 | MSTR_BURST_LENGTH(8) | + MSTR_2TMODE; + break; + case SUNXI_DRAM_TYPE_DDR4: + mstr_value |= MSTR_DEVICETYPE_DDR4 | MSTR_BURST_LENGTH(8) | + MSTR_GEARDOWNMODE | MSTR_2TMODE; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + mstr_value |= MSTR_DEVICETYPE_LPDDR3 | MSTR_BURST_LENGTH(8); + break; + case SUNXI_DRAM_TYPE_LPDDR4: + mstr_value |= MSTR_DEVICETYPE_LPDDR4 | MSTR_BURST_LENGTH(16); + break; + } + + writel_relaxed(mstr_value, &mctl_ctl->mstr); + + mctl_set_odtmap(para, config); + mctl_set_addrmap(config); + mctl_set_timing_params(para); + + dsb(); + writel(0, &mctl_ctl->pwrctl); + + /* Disable automatic controller updates + automatic controller update requests */ + setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->unk_0x2180, BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30)); + + /* + * Data bus inversion + * Controlled by a flag in boot0, enabled by default here. + */ + if (para->type == SUNXI_DRAM_TYPE_DDR4 || + para->type == SUNXI_DRAM_TYPE_LPDDR4) + setbits_le32(&mctl_ctl->dbictl, BIT(2)); +} + +static void mctl_drive_odt_config(const struct dram_para *para) +{ + u32 val; + u64 base; + u32 i; + + /* DX drive */ + for (i = 0; i < 4; i++) { + base = SUNXI_DRAM_PHY0_BASE + 0x388 + 0x40 * i; + val = (para->dx_dri >> (i * 8)) & 0x1f; + + writel_relaxed(val, base); + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + if (para->tpr3 & 0x1f1f1f1f) + val = (para->tpr3 >> (i * 8)) & 0x1f; + else + val = 4; + } + writel_relaxed(val, base + 4); + } + + /* CA drive */ + for (i = 0; i < 2; i++) { + base = SUNXI_DRAM_PHY0_BASE + 0x340 + 0x8 * i; + val = (para->ca_dri >> (i * 8)) & 0x1f; + + writel_relaxed(val, base); + writel_relaxed(val, base + 4); + } + + /* DX ODT */ + for (i = 0; i < 4; i++) { + base = SUNXI_DRAM_PHY0_BASE + 0x380 + 0x40 * i; + val = (para->dx_odt >> (i * 8)) & 0x1f; + + if (para->type == SUNXI_DRAM_TYPE_DDR4 || + para->type == SUNXI_DRAM_TYPE_LPDDR3) + writel_relaxed(0, base); + else + writel_relaxed(val, base); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + writel_relaxed(0, base + 4); + else + writel_relaxed(val, base + 4); + } + dsb(); +} + +static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para) +{ + u32 val, i; + u32 *ptr; + + if (para->tpr10 & BIT(31)) { + val = para->tpr2; + } else { + val = ((para->tpr10 << 1) & 0x1e) | + ((para->tpr10 << 5) & 0x1e00) | + ((para->tpr10 << 9) & 0x1e0000) | + ((para->tpr10 << 13) & 0x1e000000); + + if (para->tpr10 >> 29 != 0) + val <<= 1; + } + + ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780); + for (i = 0; i < 32; i++) + writel_relaxed((val >> 8) & 0x3f, &ptr[i]); + + writel_relaxed(val & 0x3f, SUNXI_DRAM_PHY0_BASE + 0x7dc); + writel_relaxed(val & 0x3f, SUNXI_DRAM_PHY0_BASE + 0x7e0); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + writel_relaxed((val >> 16) & 0x3f, + SUNXI_DRAM_PHY0_BASE + 0x7b8); + writel_relaxed((val >> 24) & 0x3f, + SUNXI_DRAM_PHY0_BASE + 0x784); + break; + case SUNXI_DRAM_TYPE_DDR4: + writel_relaxed((val >> 16) & 0x3f, + SUNXI_DRAM_PHY0_BASE + 0x784); + break; + case SUNXI_DRAM_TYPE_LPDDR3: + writel_relaxed((val >> 16) & 0x3f, + SUNXI_DRAM_PHY0_BASE + 0x788); + writel_relaxed((val >> 24) & 0x3f, + SUNXI_DRAM_PHY0_BASE + 0x790); + break; + case SUNXI_DRAM_TYPE_LPDDR4: + writel_relaxed((val >> 16) & 0x3f, + SUNXI_DRAM_PHY0_BASE + 0x790); + writel_relaxed((val >> 24) & 0x3f, + SUNXI_DRAM_PHY0_BASE + 0x78c); + break; + } + + dsb(); +} + +static void mctl_phy_init(const struct dram_para *para, + const struct dram_config *config) +{ + struct sunxi_mctl_ctl_reg *mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; + void *const mctl_com = (void *)SUNXI_DRAM_COM_BASE; + + u32 val, val2, i; + u32 *ptr; + + /* Disable auto refresh. */ + setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); + + /* Set "phy_dbi_mode" to mark the DFI as implementing DBI functionality */ + writel_relaxed(0, &mctl_ctl->pwrctl); + clrbits_le32(&mctl_ctl->dfimisc, 1); + writel_relaxed(0x20, &mctl_ctl->pwrctl); + + /* PHY cold reset */ + clrsetbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(24), BIT(9)); + udelay(1); + setbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(24)); + + /* Not sure what this gates the power of. */ + clrbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, BIT(4)); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, BIT(7)); + + /* Note: Similar enumeration of values is used during read training */ + if (config->bus_full_width) + val = 0xf; + else + val = 0x3; + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = 13; + val2 = 9; + break; + case SUNXI_DRAM_TYPE_DDR4: + val = 13; + val2 = 10; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + val = 14; + val2 = 8; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + if (para->tpr13 & BIT(28)) + val = 22; + else + val = 20; + + val2 = 10; + break; + } + + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x14); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x35c); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x368); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x374); + writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x18); + writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x360); + writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x36c); + writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x378); + writel_relaxed(val2, SUNXI_DRAM_PHY0_BASE + 0x1c); + writel_relaxed(val2, SUNXI_DRAM_PHY0_BASE + 0x364); + writel_relaxed(val2, SUNXI_DRAM_PHY0_BASE + 0x370); + writel_relaxed(val2, SUNXI_DRAM_PHY0_BASE + 0x37c); + + /* Set up SDQ swizzle */ + ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xc0); + for (i = 0; i < ARRAY_SIZE(phy_init); i++) + writel_relaxed(phy_init[i], &ptr[i]); + + /* Set VREF */ + val = 0; + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = para->tpr6 & 0xff; + if (val == 0) + val = 0x80; + break; + case SUNXI_DRAM_TYPE_DDR4: + val = (para->tpr6 >> 8) & 0xff; + if (val == 0) + val = 0x80; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + val = (para->tpr6 >> 16) & 0xff; + if (val == 0) + val = 0x80; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + val = (para->tpr6 >> 24) & 0xff; + if (val == 0) + val = 0x33; + break; + } + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3dc); + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x45c); + + mctl_drive_odt_config(para); + + if (para->tpr10 & TPR10_CA_BIT_DELAY) + mctl_phy_ca_bit_delay_compensation(para); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = 2; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + val = 3; + break; + case SUNXI_DRAM_TYPE_DDR4: + val = 4; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + val = 5; + break; + } + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, 0x7, val | 8); + + if (para->clk <= 672) + writel_relaxed(0xf, SUNXI_DRAM_PHY0_BASE + 0x20); + + if (para->clk > 500) { + val = 0; + val2 = 0; + } else { + val = 0x80; + val2 = 0x20; + } + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x144, 0x80, val); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, val2); + + dsb(); + clrbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(9)); + udelay(1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, BIT(3)); + + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), BIT(2), + BIT(2)); + + /* + * This delay is controlled by a tpr13 flag in boot0; doesn't hurt + * to always do it though. + */ + udelay(1000); + writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58); + + setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, BIT(4)); +} + +/* Helpers for updating mode registers */ +static inline void mctl_mr_write(u32 mrctrl0, u32 mrctrl1) +{ + struct sunxi_mctl_ctl_reg *mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + writel(mrctrl1, &mctl_ctl->mrctrl1); + writel(mrctrl0 | MRCTRL0_MR_WR | MRCTRL0_MR_RANKS_ALL, + &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, MRCTRL0_MR_WR, 0); +} + +static inline void mctl_mr_write_lpddr4(u8 addr, u8 value) +{ + mctl_mr_write(0, MRCTRL1_MR_ADDR(addr) | MRCTRL1_MR_DATA(value)); +} + +static inline void mctl_mr_write_lpddr3(u8 addr, u8 value) +{ + /* Bit [7:6] are set by boot0, but undocumented */ + mctl_mr_write(BIT(6) | BIT(7), + MRCTRL1_MR_ADDR(addr) | MRCTRL1_MR_DATA(value)); +} + +static void mctl_dfi_init(const struct dram_para *para) +{ + void *const mctl_com = (void *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg *mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + /* Unlock DFI registers? */ + setbits_le32(mctl_com + MCTL_COM_MAER0, BIT(8)); + + /* Enable dfi_init_complete signal and trigger PHY init start request */ + writel_relaxed(0, &mctl_ctl->swctl); + setbits_le32(&mctl_ctl->dfimisc, BIT(0)); + setbits_le32(&mctl_ctl->dfimisc, BIT(5)); + writel_relaxed(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, BIT(0), BIT(0)); + + /* Stop sending init request and wait for DFI initialization to complete. */ + writel_relaxed(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->dfimisc, BIT(5)); + writel_relaxed(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, BIT(0), BIT(0)); + mctl_await_completion(&mctl_ctl->dfistat, BIT(0), BIT(0)); + + /* Enter Software Exit from Self Refresh */ + writel_relaxed(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->pwrctl, BIT(5)); + writel_relaxed(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, BIT(0), BIT(0)); + mctl_await_completion(&mctl_ctl->statr, 0x3, 1); + + udelay(200); + + /* Disable dfi_init_complete signal */ + writel_relaxed(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); + writel_relaxed(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, BIT(0), BIT(0)); + + /* Write mode registers, fixed in the JEDEC spec */ + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + mctl_mr_write(MRCTRL0_MR_ADDR(0), 0x1c70); /* MR0 */ + /* + * outbuf en, TDQs dis, write leveling dis, out drv 40 Ohms, + * DLL en, Rtt_nom 120 Ohms + */ + mctl_mr_write(MRCTRL0_MR_ADDR(1), 0x40); /* MR1 */ + /* + * full array self-ref, CAS: 8 cyc, SRT w/ norm temp range, + * dynamic ODT off + */ + mctl_mr_write(MRCTRL0_MR_ADDR(2), 0x18); /* MR2 */ + /* predef MPR pattern */ + mctl_mr_write(MRCTRL0_MR_ADDR(3), 0); /* MR3 */ + break; + case SUNXI_DRAM_TYPE_DDR4: + mctl_mr_write(MRCTRL0_MR_ADDR(0), 0x840); + mctl_mr_write(MRCTRL0_MR_ADDR(1), 0x601); + mctl_mr_write(MRCTRL0_MR_ADDR(2), 0x8); + mctl_mr_write(MRCTRL0_MR_ADDR(3), 0); + mctl_mr_write(MRCTRL0_MR_ADDR(4), 0); + mctl_mr_write(MRCTRL0_MR_ADDR(5), 0x400); + + mctl_mr_write(MRCTRL0_MR_ADDR(6), 0x862 | BIT(7)); + mctl_mr_write(MRCTRL0_MR_ADDR(6), 0x862 | BIT(7)); + mctl_mr_write(MRCTRL0_MR_ADDR(6), 0x862 & (~BIT(7))); + break; + case SUNXI_DRAM_TYPE_LPDDR3: + mctl_mr_write_lpddr3(1, 0xc3); /* MR1: nWR=8, BL8 */ + mctl_mr_write_lpddr3(2, 0xa); /* MR2: RL=12, WL=6 */ + mctl_mr_write_lpddr3(3, 0x2); /* MR3: 40 0hms PD/PU */ + mctl_mr_write_lpddr3(11, para->mr11); + break; + case SUNXI_DRAM_TYPE_LPDDR4: + mctl_mr_write_lpddr4(0, 0); /* MR0 */ + mctl_mr_write_lpddr4(1, 0x34); /* MR1 */ + mctl_mr_write_lpddr4(2, 0x1b); /* MR2 */ + mctl_mr_write_lpddr4(3, 0x33); /* MR3 */ + mctl_mr_write_lpddr4(4, 0x3); /* MR4 */ + mctl_mr_write_lpddr4(11, para->mr11); + mctl_mr_write_lpddr4(12, para->mr12); + mctl_mr_write_lpddr4(13, para->mr13); + mctl_mr_write_lpddr4(14, para->mr14); + mctl_mr_write_lpddr4(22, para->tpr1); + break; + } + + writel(0, SUNXI_DRAM_PHY0_BASE + 0x54); + + /* Re-enable controller refresh */ + writel(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->rfshctl3, BIT(0)); + writel(1, &mctl_ctl->swctl); +} + +/* Slightly modified from H616 driver */ +static bool mctl_phy_read_calibration(const struct dram_config *config) +{ + bool result = true; + u32 val, tmp; + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30, 0x20); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + + if (config->bus_full_width) + val = 0xf; + else + val = 3; + + while ((readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x184) & val) != val) { + if (readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x184) & 0x20) { + result = false; + break; + } + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30); + + if (config->ranks == 1) { + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30, 0x10); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + + while ((readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x184) & val) != + val) { + if (readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x184) & + 0x20) { + result = false; + break; + } + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30); + + val = readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x274) & 7; + tmp = readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x26c) & 7; + if (val < tmp) + val = tmp; + tmp = readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x32c) & 7; + if (val < tmp) + val = tmp; + tmp = readl_relaxed(SUNXI_DRAM_PHY0_BASE + 0x334) & 7; + if (val < tmp) + val = tmp; + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x38, 0x7, (val + 2) & 7); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x20); + + return result; +} + +static inline void mctl_phy_dx_delay1_inner(u32 *base, u32 val1, u32 val2) +{ + u32 *ptr = base; + + for (int i = 0; i < 9; i++) { + writel_relaxed(val1, ptr); + writel_relaxed(val1, ptr + 0x30); + ptr += 2; + } + + writel_relaxed(val2, ptr + 1); + writel_relaxed(val2, ptr + 49); + writel_relaxed(val2, ptr); + writel_relaxed(val2, ptr + 48); +} + +static inline void mctl_phy_dx_delay0_inner(u32 *base1, u32 *base2, u32 val1, + u32 val2) +{ + u32 *ptr = base1; + + for (int i = 0; i < 9; i++) { + writel_relaxed(val1, ptr); + writel_relaxed(val1, ptr + 0x30); + ptr += 2; + } + + writel_relaxed(val2, base2); + writel_relaxed(val2, base2 + 48); + writel_relaxed(val2, ptr); + writel_relaxed(val2, base2 + 44); +} + +/* + * This might be somewhat transferable to H616; whether or not people like + * the design is another question + */ +static void mctl_phy_dx_delay_compensation(const struct dram_para *para) +{ + if (para->tpr10 & TPR10_DX_BIT_DELAY1) { + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, BIT(3)); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, BIT(4)); + + if (para->type == SUNXI_DRAM_TYPE_DDR4) + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, BIT(7)); + + mctl_phy_dx_delay1_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484), + para->tpr11 & 0x3f, + para->para0 & 0x3f); + mctl_phy_dx_delay1_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8), + (para->tpr11 >> 8) & 0x3f, + (para->para0 >> 8) & 0x3f); + mctl_phy_dx_delay1_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x604), + (para->tpr11 >> 16) & 0x3f, + (para->para0 >> 16) & 0x3f); + mctl_phy_dx_delay1_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x658), + (para->tpr11 >> 24) & 0x3f, + (para->para0 >> 24) & 0x3f); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); + } + + if (para->tpr10 & TPR10_DX_BIT_DELAY0) { + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, BIT(7)); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, BIT(2)); + + mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), + para->tpr12 & 0x3f, + para->tpr14 & 0x3f); + + mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x52c), + (para->tpr12 >> 8) & 0x3f, + (para->tpr14 >> 8) & 0x3f); + + mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6a8), + (para->tpr12 >> 16) & 0x3f, + (para->tpr14 >> 16) & 0x3f); + + mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6ac), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), + (para->tpr12 >> 24) & 0x3f, + (para->tpr14 >> 24) & 0x3f); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, BIT(7)); + } +} + +static bool mctl_calibrate_phy(const struct dram_para *para, + const struct dram_config *config) +{ + struct sunxi_mctl_ctl_reg *mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + int i; + + /* TODO: Implement write levelling */ + if (para->tpr10 & TPR10_READ_CALIBRATION) { + for (i = 0; i < 5; i++) + if (mctl_phy_read_calibration(config)) + break; + if (i == 5) { + debug("read calibration failed\n"); + return false; + } + } + + /* TODO: Implement read training */ + /* TODO: Implement write training */ + + mctl_phy_dx_delay_compensation(para); + /* TODO: Implement DFS */ + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, BIT(0)); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 7); + + /* Q: Does self-refresh get disabled by a calibration? */ + writel_relaxed(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->rfshctl3, BIT(1)); + writel_relaxed(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, BIT(0), BIT(0)); + + return true; +} + +static bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config) +{ + mctl_clk_init(para->clk); + mctl_com_init(para, config); + mctl_phy_init(para, config); + mctl_dfi_init(para); + + return mctl_calibrate_phy(para, config); +} + +/* Heavily inspired from H616 driver. */ +static void auto_detect_ranks(const struct dram_para *para, + struct dram_config *config) +{ + int i; + + config->cols = 9; + config->rows = 14; + config->banks = 2; + config->bankgrps = 0; + + /* Test ranks */ + for (i = 1; i >= 0; i--) { + config->ranks = i; + config->bus_full_width = true; + debug("Testing ranks = %d, 32-bit bus: ", i); + if (mctl_core_init(para, config)) { + debug("OK\n"); + break; + } + + config->bus_full_width = false; + debug("Testing ranks = %d, 16-bit bus: ", i); + if (mctl_core_init(para, config)) { + debug("OK\n"); + break; + } + } + + if (i < 0) + debug("rank testing failed\n"); +} + +static void mctl_write_pattern(void) +{ + unsigned int i; + u32 *ptr, val; + + ptr = (u32 *)CFG_SYS_SDRAM_BASE; + for (i = 0; i < 16; ptr++, i++) { + if (i & 1) + val = ~(ulong)ptr; + else + val = (ulong)ptr; + writel(val, ptr); + } +} + +static bool mctl_check_pattern(ulong offset) +{ + unsigned int i; + u32 *ptr, val; + + ptr = (u32 *)CFG_SYS_SDRAM_BASE; + for (i = 0; i < 16; ptr++, i++) { + if (i & 1) + val = ~(ulong)ptr; + else + val = (ulong)ptr; + if (val != *(ptr + offset / 4)) + return false; + } + + return true; +} + +static void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config) +{ + unsigned int shift; + u32 buffer[16]; + + /* max config for bankgrps on DDR4, minimum for everything else */ + config->cols = 8; + config->banks = 2; + config->rows = 14; + + shift = 1 + config->bus_full_width; + if (para->type == SUNXI_DRAM_TYPE_DDR4) { + config->bankgrps = 2; + mctl_core_init(para, config); + + /* store content so it can be restored later. */ + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + mctl_write_pattern(); + + if (mctl_check_pattern(1ULL << (shift + 4))) + config->bankgrps = 1; + + /* restore data */ + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); + } else { + /* No bank groups in (LP)DDR3/LPDDR4 */ + config->bankgrps = 0; + } + + /* reconfigure to make sure all active columns are accessible */ + config->cols = 12; + mctl_core_init(para, config); + + /* store data again as it might be moved */ + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + mctl_write_pattern(); + + /* + * Detect column address bits. The last number of columns checked + * is 11, if that doesn't match, is must be 12, no more checks needed. + */ + shift = 1 + config->bus_full_width + config->bankgrps; + for (config->cols = 8; config->cols < 12; config->cols++) { + if (mctl_check_pattern(1ULL << (config->cols + shift))) + break; + } + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); + + /* reconfigure to make sure that all active banks are accessible */ + config->banks = 3; + mctl_core_init(para, config); + + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + mctl_write_pattern(); + + /* detect bank bits */ + shift += config->cols; + for (config->banks = 2; config->banks < 3; config->banks++) { + if (mctl_check_pattern(1ULL << (config->banks + shift))) + break; + } + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); + + /* reconfigure to make sure that all active rows are accessible */ + config->rows = 18; + mctl_core_init(para, config); + + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + mctl_write_pattern(); + + /* detect row address bits */ + shift += config->banks; + for (config->rows = 14; config->rows < 18; config->rows++) { + if (mctl_check_pattern(1ULL << (config->rows + shift))) + break; + } + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); +} + +/* Modified from H616 driver to add banks and bank groups */ +static unsigned long calculate_dram_size(const struct dram_config *config) +{ + /* Bootrom only uses x32 or x16 bus widths */ + u8 width = config->bus_full_width ? 4 : 2; + + return (1ULL << (config->cols + config->rows + config->banks + + config->bankgrps)) * + width * (1ULL << config->ranks); +} + +static const struct dram_para para = { + .clk = CONFIG_DRAM_CLK, +#ifdef CONFIG_SUNXI_DRAM_DDR3 + .type = SUNXI_DRAM_TYPE_DDR3, +#elif defined(CONFIG_SUNXI_DRAM_DDR4) + .type = SUNXI_DRAM_TYPE_DDR4, +#elif defined(CONFIG_SUNXI_DRAM_LPDDR3) + .type = SUNXI_DRAM_TYPE_LPDDR3, +#elif defined(CONFIG_SUNXI_DRAM_LPDDR4) + .type = SUNXI_DRAM_TYPE_LPDDR4, +#endif + /* TODO: Populate from config */ + .dx_odt = CONFIG_DRAM_SUNXI_DX_ODT, + .dx_dri = CONFIG_DRAM_SUNXI_DX_DRI, + .ca_dri = CONFIG_DRAM_SUNXI_CA_DRI, + .para0 = CONFIG_DRAM_SUNXI_PARA0, + .mr11 = CONFIG_DRAM_SUNXI_MR11, + .mr12 = CONFIG_DRAM_SUNXI_MR12, + .mr13 = CONFIG_DRAM_SUNXI_MR13, + .mr14 = CONFIG_DRAM_SUNXI_MR14, + .tpr1 = CONFIG_DRAM_SUNXI_TPR1, + .tpr2 = CONFIG_DRAM_SUNXI_TPR2, + .tpr3 = CONFIG_DRAM_SUNXI_TPR3, + .tpr6 = CONFIG_DRAM_SUNXI_TPR6, + .tpr10 = CONFIG_DRAM_SUNXI_TPR10, + .tpr11 = CONFIG_DRAM_SUNXI_TPR11, + .tpr12 = CONFIG_DRAM_SUNXI_TPR12, + .tpr13 = CONFIG_DRAM_SUNXI_TPR13, + .tpr14 = CONFIG_DRAM_SUNXI_TPR14, +}; + +unsigned long sunxi_dram_init(void) +{ + struct dram_config config; + + /* Writing to undocumented SYS_CFG area, according to user manual. */ + setbits_le32(0x03000160, BIT(8)); + clrbits_le32(0x03000168, 0x3f); + + auto_detect_ranks(¶, &config); + mctl_auto_detect_dram_size(¶, &config); + + if (!mctl_core_init(¶, &config)) + return 0; + + debug("cols = 2^%d, rows = 2^%d, banks = %d, bank groups = %d, ranks = %d, width = %d\n", + config.cols, config.rows, 1U << config.banks, + 1U << config.bankgrps, 1U << config.ranks, + 16U << config.bus_full_width); + + return calculate_dram_size(&config); +} diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 5f203419240..4dc1f29fc08 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -6,3 +6,5 @@ obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333) += h616_ddr3_1333.o obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR3) += h616_lpddr3.o obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR4) += h616_lpddr4_2133.o +obj-$(CONFIG_SUNXI_DRAM_A133_DDR4) += a133_ddr4.o +obj-$(CONFIG_SUNXI_DRAM_A133_LPDDR4) += a133_lpddr4.o diff --git a/arch/arm/mach-sunxi/dram_timings/a133_ddr4.c b/arch/arm/mach-sunxi/dram_timings/a133_ddr4.c new file mode 100644 index 00000000000..dec208e22df --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/a133_ddr4.c @@ -0,0 +1,80 @@ +#include +#include + +void mctl_set_timing_params(const struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg *const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 txsr = 4; + u8 tccd = 3; + u8 rd2wr = 5; + u8 tmrd = 4; + u8 tmrw = 0; + u8 wrlat = 5; + u8 rdlat = 7; + u8 wr2pre = 14; + u8 dfi_tphy_wrlat = 6; + u8 dfi_trddata_en = 10; + + u8 tfaw = ns_to_t(35); + u8 trrd = max(ns_to_t(8), 2); + u8 txp = max(ns_to_t(6), 2); + u8 tmrd_pda = max(ns_to_t(10), 8); + u8 trp = ns_to_t(15); + u8 trc = ns_to_t(49); + u8 wr2rd_s = max(ns_to_t(3), 1) + 7; + u8 tras_min = ns_to_t(34); + u16 trefi_x32 = ns_to_t(7800) / 32; + u16 trfc_min = ns_to_t(350); + u16 txs_x32 = ns_to_t(360) / 32; + u16 tmod = max(ns_to_t(15), 12); + u8 tcke = max(ns_to_t(5), 2); + u8 tcksrx = max(ns_to_t(10), 3); + u8 txs_abort_x32 = ns_to_t(170) / 32; + u8 tras_max = ns_to_t(70200) / 1024; + + u8 rd2pre = (trp < 5 ? 9 - trp : 4); + u8 wr2rd = trrd + 7; + u8 tckesr = tcke + 1; + u8 trcd = trp; + u8 trrd_s = txp; + u8 tcksre = tcksrx; + + writel(tras_min | tras_max << 8 | tfaw << 16 | wr2pre << 24, + &mctl_ctl->dramtmg[0]); + writel(trc | rd2pre << 8 | txp << 16, &mctl_ctl->dramtmg[1]); + writel(wr2rd | rd2wr << 8 | rdlat << 16 | wrlat << 24, + &mctl_ctl->dramtmg[2]); + writel(tmod | tmrd << 12 | tmrw << 20, &mctl_ctl->dramtmg[3]); + writel(trp | trrd << 8 | tccd << 16 | trcd << 24, + &mctl_ctl->dramtmg[4]); + writel(tcke | tckesr << 8 | tcksre << 16 | tcksrx << 24, + &mctl_ctl->dramtmg[5]); + writel((txp + 2) | 0x20 << 16 | 0x20 << 24, + &mctl_ctl->dramtmg[6]); + writel(txs_x32 | 0x10 << 8 | txs_abort_x32 << 16 | txs_abort_x32 << 24, + &mctl_ctl->dramtmg[8]); + writel(wr2rd_s | trrd_s << 8 | 0x2 << 16, &mctl_ctl->dramtmg[9]); + writel(0xe0c05, &mctl_ctl->dramtmg[10]); + writel(0x440c021c, &mctl_ctl->dramtmg[11]); + writel(tmrd_pda, &mctl_ctl->dramtmg[12]); + writel(0xa100002, &mctl_ctl->dramtmg[13]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + clrsetbits_le32(&mctl_ctl->init[0], 0xc0000fff, 1008); + writel(0x1f20000, &mctl_ctl->init[1]); + clrsetbits_le32(&mctl_ctl->init[2], 0xff0f, 0xd05); + writel(0, &mctl_ctl->dfimisc); + + writel(0x840 << 16 | 0x601, &mctl_ctl->init[3]); /* MR0 / MR1 */ + writel(0x8 << 16 | 0x0, &mctl_ctl->init[4]); /* MR2 / MR3 */ + writel(0x0 << 16 | 0x400, &mctl_ctl->init[6]); /* MR4 / MR5 */ + writel(0x826, &mctl_ctl->init[7]); /* MR6 */ + + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + writel((dfi_tphy_wrlat - 1) | 0x2000000 | (dfi_trddata_en - 1) << 16 | + 0x808000, &mctl_ctl->dfitmg0); + writel(0x100202, &mctl_ctl->dfitmg1); + writel(trfc_min | trefi_x32 << 16, &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-sunxi/dram_timings/a133_lpddr4.c b/arch/arm/mach-sunxi/dram_timings/a133_lpddr4.c new file mode 100644 index 00000000000..1e607381023 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/a133_lpddr4.c @@ -0,0 +1,102 @@ +#include +#include + +void mctl_set_timing_params(const struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg *const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + bool tpr13_flag1 = para->tpr13 & BIT(28); + bool tpr13_flag2 = para->tpr13 & BIT(3); + bool tpr13_flag3 = para->tpr13 & BIT(5); + + u8 tccd = 4; + u8 tfaw = ns_to_t(40); + u8 trrd = max(ns_to_t(10), 2); + u8 trcd = max(ns_to_t(18), 2); + u8 trc = ns_to_t(65); + u8 txp = max(ns_to_t(8), 2); + + u8 trp = ns_to_t(21); + u8 tras_min = ns_to_t(42); + u16 trefi_x32 = ns_to_t(3904) / 32; + u16 trfc_min = ns_to_t(180); + u16 txsr = ns_to_t(190); + + u8 tmrw = max(ns_to_t(14), 5); + u8 tmrd = max(ns_to_t(14), 5); + u8 tmod = 12; + u8 tcke = max(ns_to_t(15), 2); + u8 tcksrx = max(ns_to_t(2), 2); + u8 tcksre = max(ns_to_t(5), 2); + u8 tckesr = max(ns_to_t(15), 2); + u8 tras_max = (trefi_x32 * 9) / 32; + u8 txs_x32 = 4; + u8 txsabort_x32 = 4; + + u8 wrlat = 5; + u8 wr2rd_s = 8; + u8 trrd_s = 2; + u8 tmrd_pda = 8; + + u8 wr2pre = 24; + u8 rd2pre = 4; + u8 wr2rd = 14 + max(ns_to_t(tpr13_flag1 ? 10 : 12), 4); + u8 rd2wr = 17 + ns_to_t(4) - ns_to_t(1); + u8 tphy_wrlat = 5; + + u8 rdlat = 10; + u8 trddata_en = 17; + + if (tpr13_flag1) { + rdlat = 11; + trddata_en = 19; + } + + writel(tras_min | tras_max << 8 | tfaw << 16 | wr2pre << 24, + &mctl_ctl->dramtmg[0]); + writel(trc | rd2pre << 8 | txp << 16, &mctl_ctl->dramtmg[1]); + writel(wr2rd | rd2wr << 8 | rdlat << 16 | wrlat << 24, + &mctl_ctl->dramtmg[2]); + writel(tmod | tmrd << 12 | tmrw << 20, &mctl_ctl->dramtmg[3]); + writel(trp | trrd << 8 | tccd << 16 | trcd << 24, + &mctl_ctl->dramtmg[4]); + writel(tcke | tckesr << 8 | tcksre << 16 | tcksrx << 24, + &mctl_ctl->dramtmg[5]); + writel((txp + 2) | 0x20 << 16 | 0x20 << 24, &mctl_ctl->dramtmg[6]); + writel(txs_x32 | 0x10 << 8 | txsabort_x32 << 16 | txsabort_x32 << 24, + &mctl_ctl->dramtmg[8]); + writel(wr2rd_s | trrd_s << 8 | 0x2 << 16, &mctl_ctl->dramtmg[9]); + writel(0xe0c05, &mctl_ctl->dramtmg[10]); + writel(0x440c021c, &mctl_ctl->dramtmg[11]); + writel(tmrd_pda, &mctl_ctl->dramtmg[12]); + writel(0xa100002, &mctl_ctl->dramtmg[13]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + clrsetbits_le32(&mctl_ctl->init[0], 0xc0000fff, 1008); + + if (tpr13_flag2) + writel(0x420000, &mctl_ctl->init[1]); + else + writel(0x1f20000, &mctl_ctl->init[1]); + + clrsetbits_le32(&mctl_ctl->init[2], 0xff0f, 0xd05); + writel(0, &mctl_ctl->dfimisc); + + writel(0x34 << 16 | 0x1b, &mctl_ctl->init[3]); /* MR1/MR2 */ + writel(0x33 << 16, &mctl_ctl->init[4]); /* MR3 */ + writel(para->mr11 << 16 | para->mr12, &mctl_ctl->init[6]); + writel(para->tpr1 << 16 | para->mr14, &mctl_ctl->init[7]); + + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + if (!tpr13_flag3) { + tphy_wrlat -= 1; + trddata_en -= 1; + } + + writel(tphy_wrlat | trddata_en << 16 | 0x808000 | 0x2000000, + &mctl_ctl->dfitmg0); + writel(0x100202, &mctl_ctl->dfitmg1); + + writel(trfc_min | trefi_x32 << 16, &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index f4ae602d523..a74d59205d4 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -3,8 +3,10 @@ * Copyright (c) 2010-2016, NVIDIA CORPORATION. */ +#include #include #include +#include #include #include diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 5df0eb28c96..b3a039217c2 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -43,7 +43,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lX\n", spl_image->entry_point); diff --git a/arch/arm/mach-tegra/tegra124/bct.c b/arch/arm/mach-tegra/tegra124/bct.c index a71aa87fce1..4dc4b7138ab 100644 --- a/arch/arm/mach-tegra/tegra124/bct.c +++ b/arch/arm/mach-tegra/tegra124/bct.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index b647b6b26d2..253cb243676 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index 250009ea8d8..398ba1de386 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-uniphier/bcu/bcu-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ld4.c index ea6088ba1cb..08c41fa6d4d 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ld4.c @@ -20,7 +20,7 @@ void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd) writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR5); /* 0xe0000000-0xffffffff: IPPC/IPPD-bus */ /* Specify DDR channel */ shift = bd->dram_ch[0].size / 0x04000000 * 4; diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c index 629f8b90c9d..be4ce3265bb 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "../soc-info.h" #include "ddrmphy-regs.h" diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index ca519d1c7e0..3ccafe20638 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "../soc-info.h" #include "ddrphy-regs.h" diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 3c372bd6dcf..02bbc54ff0f 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -19,7 +19,7 @@ #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 -#define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800 +#define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0xFFA50800 #define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \ + 0x00000114) #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210 diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index b288c65e7fd..8ade6f7b9d1 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -155,10 +155,6 @@ config TARGET_M5282EVB bool "Support M5282EVB" select M5282 -config TARGET_ASTRO_MCF5373L - bool "Support astro_mcf5373l" - select M5373 - config TARGET_M53017EVB bool "Support M53017EVB" select M53015 @@ -183,7 +179,6 @@ config TARGET_STMARK2 endchoice source "board/BuS/eb_cpu5282/Kconfig" -source "board/astro/mcf5373l/Kconfig" source "board/cobra5272/Kconfig" source "board/freescale/m5208evbe/Kconfig" source "board/freescale/m5235evb/Kconfig" diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 8b354b9c570..c89559be309 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -11,7 +11,6 @@ dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb -dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb @@ -21,4 +20,4 @@ dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here -DTC_FLAGS += -R 4 -p 0x1000 +DTC_FLAGS += -R 4 diff --git a/arch/m68k/dts/astro_mcf5373l.dts b/arch/m68k/dts/astro_mcf5373l.dts deleted file mode 100644 index 40f84dd64b6..00000000000 --- a/arch/m68k/dts/astro_mcf5373l.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello - */ - -/dts-v1/; -/include/ "mcf537x.dtsi" - -/ { - model = "Astro mcf5373l"; - compatible = "astro,mcf5373l"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - bootph-all; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <80000>; - u-boot,i2c-slave-addr = <0x7f>; - status = "okay"; -}; diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 4ac886933c6..aea2ccabe08 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -32,11 +32,6 @@ struct arch_global_data { #include -#if 0 -extern gd_t *global_data; -#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data -#else -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7") -#endif +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("d7") #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 9be902d3bb1..0f3a7472a67 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -5,4 +5,4 @@ dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here -DTC_FLAGS += -R 4 -p 0x1000 +DTC_FLAGS += -R 4 diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index bb4112f22a3..f7922fac41c 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -18,7 +18,7 @@ struct arch_global_data { #include -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r31") #define gd_cpuinfo() ((struct microblaze_cpuinfo *)&gd->arch.cpuinfo) diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 147a95ecea8..265dd2a3ec4 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -44,6 +44,6 @@ struct arch_global_data { #include -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("k0") #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 39a4f435a84..4c6322ed1c7 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -118,20 +118,4 @@ struct task_struct; */ #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define ARCH_HAS_PREFETCH - -static inline void prefetch(const void *addr) -{ - __asm__ __volatile__( - " .set mips4 \n" - " pref %0, (%1) \n" - " .set mips0 \n" - : - : "i" (Pref_Load), "r" (addr)); -} - -#endif - #endif /* _ASM_PROCESSOR_H */ diff --git a/arch/mips/lib/spl.c b/arch/mips/lib/spl.c index b4087546dd1..4949b17bd59 100644 --- a/arch/mips/lib/spl.c +++ b/arch/mips/lib/spl.c @@ -7,7 +7,7 @@ #include #include -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); image_entry_noargs_t image_entry = diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c index 8ef00f99a10..0ff717b4595 100644 --- a/arch/mips/mach-jz47xx/jz4780/pll.c +++ b/arch/mips/mach-jz47xx/jz4780/pll.c @@ -327,7 +327,7 @@ /* BCH clock divider register */ #define CPM_BCHCDR_BPCS_BIT 30 #define CPM_BCHCDR_BPCS_MASK (0x3 << CPM_BCHCDR_BPCS_BIT) -#define CPM_BCHCDR_BPCS_STOP (0X0 << CPM_BCHCDR_BPCS_BIT) +#define CPM_BCHCDR_BPCS_STOP (0x0 << CPM_BCHCDR_BPCS_BIT) #define CPM_BCHCDR_BPCS_SRC_CLK (0x1 << CPM_BCHCDR_BPCS_BIT) #define CPM_BCHCDR_BPCS_MPLL (0x2 << CPM_BCHCDR_BPCS_BIT) #define CPM_BCHCDR_BPCS_EPLL (0x3 << CPM_BCHCDR_BPCS_BIT) diff --git a/arch/nios2/dts/Makefile b/arch/nios2/dts/Makefile index d77db9762a1..75951164978 100644 --- a/arch/nios2/dts/Makefile +++ b/arch/nios2/dts/Makefile @@ -5,4 +5,4 @@ dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here -DTC_FLAGS += -R 4 -p 0x1000 +DTC_FLAGS += -R 4 diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index b2c0c517e7a..143b7c624d2 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 8918a401fac..bee6758dc9a 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -410,9 +410,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) void cpu_mp_lmb_reserve(void) { - u32 bootpg = determine_mp_bootpg(NULL); + phys_addr_t bootpg = determine_mp_bootpg(NULL); - lmb_reserve(bootpg, 4096, LMB_NONE); + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &bootpg, 4096, LMB_NONE); } void setup_mp(void) diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index f61f4e1ea6e..7e53dcf8af5 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -39,12 +39,14 @@ /* The FMAN driver uses the PHYLIB infrastructure */ -#if CONFIG_IS_ENABLED(DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX) +#if !defined(CONFIG_CLK_MPC83XX) /* * TODO: Convert this to a clock driver exists that can give us the UART * clock here. */ -#define CFG_SYS_NS16550_CLK get_serial_clock() +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK get_bus_freq(0) +#endif #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index cc2ce617350..26cbc7854d9 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -93,7 +93,7 @@ struct arch_global_data { #include -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r2") #include diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7293720fb3c..3565a287154 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2027,8 +2027,8 @@ typedef struct ccsr_gur { #endif #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #if defined(CONFIG_ARCH_BSC9131) -#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 -#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0x40000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0x80000000 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 @@ -2727,7 +2727,7 @@ struct ccsr_cluster_l2 { (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ -#define CFG_SYS_DCSR_DCFG_OFFSET 0X20000 +#define CFG_SYS_DCSR_DCFG_OFFSET 0x20000 struct dcsr_dcfg_regs { u8 res_0[0x520]; u32 ecccr1; diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index f7e1a807746..2357734a5be 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1053,7 +1053,7 @@ #define SVR_P4080 0x820000 #define SVR_P5010 0x822100 #define SVR_P5020 0x822000 -#define SVR_P5021 0X820500 +#define SVR_P5021 0x820500 #define SVR_P5040 0x820400 #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 @@ -1062,7 +1062,7 @@ #define SVR_C291 0x850000 #define SVR_C292 0x850020 #define SVR_C293 0x850030 -#define SVR_B4860 0X868000 +#define SVR_B4860 0x868000 #define SVR_G4860 0x868001 #define SVR_B4460 0x868003 #define SVR_B4440 0x868100 diff --git a/arch/powerpc/lib/misc.c b/arch/powerpc/lib/misc.c index 7e303419624..fc10ae50cf8 100644 --- a/arch/powerpc/lib/misc.c +++ b/arch/powerpc/lib/misc.c @@ -36,11 +36,12 @@ int arch_misc_init(void) size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE); if (size < bootm_size) { - ulong base = bootmap_base + size; + phys_addr_t base = bootmap_base + size; printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n", size, (unsigned long long)bootm_size); - lmb_reserve(base, bootm_size - size, LMB_NONE); + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &base, + bootm_size - size, LMB_NONE); } #ifdef CONFIG_MP diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index 9f16dda92a0..eddd6a3b9a2 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -10,19 +10,29 @@ # Rick Chen, Andes Technology Corporation # -32bit-emul := elf32lriscv -64bit-emul := elf64lriscv +ifdef CONFIG_SYS_BIG_ENDIAN +small-endian := b +large-endian := big +PLATFORM_CPPFLAGS += -mbig-endian +KBUILD_LDFLAGS += -mbig-endian +else +small-endian := l +large-endian := little +endif + +32bit-emul := elf32$(small-endian)riscv +64bit-emul := elf64$(small-endian)riscv ifdef CONFIG_32BIT KBUILD_LDFLAGS += -m $(32bit-emul) EFI_LDS := elf_riscv32_efi.lds -PLATFORM_ELFFLAGS += -B riscv -O elf32-littleriscv +PLATFORM_ELFFLAGS += -B riscv -O elf32-$(large-endian)riscv endif ifdef CONFIG_64BIT KBUILD_LDFLAGS += -m $(64bit-emul) EFI_LDS := elf_riscv64_efi.lds -PLATFORM_ELFFLAGS += -B riscv -O elf64-littleriscv +PLATFORM_ELFFLAGS += -B riscv -O elf64-$(large-endian)riscv endif PLATFORM_CPPFLAGS += -ffixed-x3 -fpic diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index 4d44191bd22..c73462c04b8 100644 --- a/arch/riscv/cpu/th1520/Kconfig +++ b/arch/riscv/cpu/th1520/Kconfig @@ -11,6 +11,7 @@ config THEAD_TH1520 select BINMAN if SPL select SYS_CACHE_THEAD_CMO select CLK_THEAD + select PINCTRL_TH1520 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile index 5d806c06e2e..d971ea7390d 100644 --- a/arch/riscv/cpu/th1520/Makefile +++ b/arch/riscv/cpu/th1520/Makefile @@ -5,4 +5,4 @@ obj-y += cache.o obj-y += cpu.o obj-y += dram.o -obj-y += spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c index 08aa1f789fd..b2fec229363 100644 --- a/arch/riscv/cpu/th1520/cache.c +++ b/arch/riscv/cpu/th1520/cache.c @@ -11,6 +11,7 @@ #define CSR_MHCR_IE BIT(0) #define CSR_MHCR_DE BIT(1) +#if CONFIG_IS_ENABLED(RISCV_MMODE) void icache_enable(void) { csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE); @@ -30,3 +31,4 @@ int dcache_status(void) { return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0; } +#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */ diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c index b83f1272c67..f60446fd772 100644 --- a/arch/riscv/cpu/th1520/cpu.c +++ b/arch/riscv/cpu/th1520/cpu.c @@ -9,8 +9,35 @@ #include #include +#include -#define TH1520_PMP_BASE (void *)0xffdc020000 +#define TH1520_C910_RST (void __iomem *)(0xffef014000 + 0x004) +#define TH1520_C910_CORE_RST_N(n) BIT((n) + 1) +#define TH1520_SYSCFG_AP_BASE (void __iomem *)(0xffef018000) +#define TH1520_SYSCFG_CORE_START_L(n) (TH1520_SYSCFG_AP_BASE + 0x50 + 8 * (n)) +#define TH1520_SYSCFG_CORE_START_H(n) (TH1520_SYSCFG_AP_BASE + 0x54 + 8 * (n)) +#define TH1520_PMP_BASE (void *)0xffdc020000 + +void th1520_kick_secondary_cores(void) +{ + int i; + + /* + * On coldboot, only HART 0 is brought up by hardware, and resets for + * secondary cores are asserted. Set reset address of secondary cores + * to the entry of SPL, then deassert the resets to bring them up. + */ + for (i = 1; i < 4; i++) { + writel(CONFIG_SPL_TEXT_BASE & 0xffffffff, + TH1520_SYSCFG_CORE_START_L(i)); + writel(CONFIG_SPL_TEXT_BASE >> 32, + TH1520_SYSCFG_CORE_START_H(i)); + } + + setbits_le32(TH1520_C910_RST, TH1520_C910_CORE_RST_N(1) | + TH1520_C910_CORE_RST_N(2) | + TH1520_C910_CORE_RST_N(3)); +} void th1520_invalidate_pmp(void) { diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c index 362fe895f86..b95470485f6 100644 --- a/arch/riscv/cpu/th1520/spl.c +++ b/arch/riscv/cpu/th1520/spl.c @@ -4,6 +4,7 @@ */ #include #include +#include #include #include #include @@ -21,6 +22,52 @@ DECLARE_GLOBAL_DATA_PTR; #define TH1520_SUBSYS_RST_VI_N BIT(1) #define TH1520_SUBSYS_RST_DSP_N BIT(0) +#define CSR_MXSTATUS 0x7c0 +#define CSR_MXSTATUS_THEADISAEE BIT(22) +#define CSR_MXSTATUS_MAEE BIT(21) +#define CSR_MXSTATUS_CLINTEE BIT(17) +#define CSR_MXSTATUS_UCME BIT(16) +#define CSR_MXSTATUS_MM BIT(15) +#define CSR_MHCR 0x7c1 +#define CSR_MHCR_WBR BIT(8) +#define CSR_MHCR_BTB BIT(6) +#define CSR_MHCR_BPE BIT(5) +#define CSR_MHCR_RS BIT(4) +#define CSR_MHCR_WB BIT(3) +#define CSR_MHCR_WA BIT(2) +#define CSR_MHCR_DE BIT(1) +#define CSR_MHCR_IE BIT(0) +#define CSR_MCOR 0x7c2 +#define CSR_MCOR_IBP_INV BIT(18) +#define CSR_MCOR_BTB_INV BIT(17) +#define CSR_MCOR_BHT_INV BIT(16) +#define CSR_MCOR_CACHE_INV BIT(4) +#define CSR_MCCR2 0x7c3 +#define CSR_MCCR2_TPRF BIT(31) +#define CSR_MCCR2_IPRF(n) ((n) << 29) +#define CSR_MCCR2_TSETUP BIT(25) +#define CSR_MCCR2_TLNTCY(n) ((n) << 22) +#define CSR_MCCR2_DSETUP BIT(19) +#define CSR_MCCR2_DLNTCY(n) ((n) << 16) +#define CSR_MCCR2_L2EN BIT(3) +#define CSR_MCCR2_RFE BIT(0) +#define CSR_MHINT 0x7c5 +#define CSR_MHINT_FENCERW_BROAD_DIS BIT(22) +#define CSR_MHINT_TLB_BRAOD_DIS BIT(21) +#define CSR_MHINT_NSFE BIT(18) +#define CSR_MHINT_L2_PREF_DIST(n) ((n) << 16) +#define CSR_MHINT_L2PLD BIT(15) +#define CSR_MHINT_DCACHE_PREF_DIST(n) ((n) << 13) +#define CSR_MHINT_LPE BIT(9) +#define CSR_MHINT_ICACHE_PREF BIT(8) +#define CSR_MHINT_AMR BIT(3) +#define CSR_MHINT_DCACHE_PREF BIT(2) +#define CSR_MHINT2 0x7cc +#define CSR_MHINT2_LOCAL_ICG_EN(n) BIT((n) + 14) +#define CSR_MHINT4 0x7ce +#define CSR_MSMPR 0x7f3 +#define CSR_MSMPR_SMPEN BIT(0) + int spl_dram_init(void) { int ret; @@ -77,6 +124,42 @@ void harts_early_init(void) { int i; + /* Invalidate cache and buffer entries */ + csr_write(CSR_MCOR, CSR_MCOR_IBP_INV | CSR_MCOR_BTB_INV | + CSR_MCOR_BHT_INV | CSR_MCOR_CACHE_INV | 0x3); + + /* Enable cache snooping */ + csr_write(CSR_MSMPR, CSR_MSMPR_SMPEN); + + /* + * Configure and enable L2 cache, + * Enable tag/data RAM prefetch, both cost 2 cycles + * Prefetch 3 cache lines of instructions + * Enable read allocation + */ + csr_write(CSR_MCCR2, CSR_MCCR2_TPRF | CSR_MCCR2_IPRF(3) | + CSR_MCCR2_TSETUP | CSR_MCCR2_TLNTCY(1) | + CSR_MCCR2_DSETUP | CSR_MCCR2_DLNTCY(1) | + CSR_MCCR2_L2EN | CSR_MCCR2_RFE); + csr_write(CSR_MXSTATUS, CSR_MXSTATUS_THEADISAEE | CSR_MXSTATUS_MAEE | + CSR_MXSTATUS_CLINTEE | CSR_MXSTATUS_UCME | + CSR_MXSTATUS_MM); + csr_write(CSR_MHINT, CSR_MHINT_FENCERW_BROAD_DIS | + CSR_MHINT_TLB_BRAOD_DIS | + CSR_MHINT_NSFE | + CSR_MHINT_L2_PREF_DIST(2) | + CSR_MHINT_L2PLD | + CSR_MHINT_DCACHE_PREF_DIST(3) | + CSR_MHINT_LPE | + CSR_MHINT_ICACHE_PREF | + CSR_MHINT_AMR | + CSR_MHINT_DCACHE_PREF); + csr_write(CSR_MHCR, CSR_MHCR_WBR | CSR_MHCR_BTB | CSR_MHCR_BPE | + CSR_MHCR_RS | CSR_MHCR_WB | CSR_MHCR_WA | 0x3); + csr_write(CSR_MHINT2, CSR_MHINT2_LOCAL_ICG_EN(8) | + CSR_MHINT2_LOCAL_ICG_EN(3)); + csr_write(CSR_MHINT4, 0x410); + /* * Set IOPMPs to the default attribute, allowing the application * processor to access various peripherals. Subsystem clocks should be diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index cf1872f3fdc..2b10c2d6c01 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -19,4 +19,4 @@ dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here -DTC_FLAGS += -R 4 -p 0x1000 +DTC_FLAGS += -R 4 diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index 28107a9f354..8306eda5521 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -128,6 +128,13 @@ #clock-cells = <0>; }; + aonsys_clk: clock-73728000 { + compatible = "fixed-clock"; + clock-frequency = <73728000>; + clock-output-names = "aonsys_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -151,6 +158,7 @@ clint: timer@ffdc000000 { compatible = "thead,th1520-clint", "thead,c900-clint"; reg = <0xff 0xdc000000 0x0 0x00010000>; + bootph-pre-ram; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, @@ -258,6 +266,13 @@ }; }; + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xe7f3c000 0x0 0x1000>; + clocks = <&clk CLK_PADCTRL1>; + thead,pad-group = <2>; + }; + gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; @@ -298,6 +313,13 @@ }; }; + padctrl0_apsys: pinctrl@ffec007000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xec007000 0x0 0x1000>; + clocks = <&clk CLK_PADCTRL0>; + thead,pad-group = <3>; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -438,6 +460,13 @@ }; }; + padctrl_aosys: pinctrl@fffff4a000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; + clocks = <&aonsys_clk>; + thead,pad-group = <1>; + }; + ao_gpio1: gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; diff --git a/arch/riscv/dts/thead-th1520-binman.dtsi b/arch/riscv/dts/thead-th1520-binman.dtsi index f060639e1c6..7b535e8402c 100644 --- a/arch/riscv/dts/thead-th1520-binman.dtsi +++ b/arch/riscv/dts/thead-th1520-binman.dtsi @@ -30,24 +30,48 @@ fit,fdt-list = "of-list"; images { + opensbi { + description = "OpenSBI fw_dynamic Firmware"; + type = "firmware"; + os = "opensbi"; + arch = "riscv"; + load = /bits/ 64 ; + entry = /bits/ 64 ; + + opensbi_blob: opensbi { + filename = "fw_dynamic.bin"; + missing-msg = "opensbi"; + }; + }; + uboot { description = "U-Boot"; type = "standalone"; + firmware = "opensbi"; os = "U-boot"; arch = "riscv"; compression = "none"; load = /bits/ 64 ; - uboot_blob: u-boot { + uboot_nodtb_blob: u-boot-nodtb { }; }; + + @fdt-SEQ { + fit,operation = "gen-fdt-nodes"; + description = "NAME"; + type = "flat_dt"; + compression = "none"; + }; }; configurations { - default = "conf-th1520-lichee-pi-4a"; + default = "@conf-DEFAULT-SEQ"; - conf-th1520-lichee-pi-4a { - description = "th1520-lichee-pi-4a"; + @conf-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "opensbi"; loadables = "uboot"; }; }; diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h b/arch/riscv/include/asm/arch-th1520/cpu.h index 837f0b8d06b..e164e9ab979 100644 --- a/arch/riscv/include/asm/arch-th1520/cpu.h +++ b/arch/riscv/include/asm/arch-th1520/cpu.h @@ -5,5 +5,6 @@ #ifndef _ASM_TH1520_CPU_H_ #define _ASM_TH1520_CPU_H_ +void th1520_kick_secondary_cores(void); void th1520_invalidate_pmp(void); #endif /* _ASM_TH1520_CPU_H_ */ diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h index d26ac5688fa..3140c1f585e 100644 --- a/arch/riscv/include/asm/byteorder.h +++ b/arch/riscv/include/asm/byteorder.h @@ -26,7 +26,7 @@ # define __SWAB_64_THRU_32__ #endif -#ifdef __RISCVEB__ +#if defined(__RISCVEB__) || (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) #include #else #include diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 47b5e2cfc8f..33f2b5ec5c8 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -68,7 +68,7 @@ static inline gd_t *get_gd(void) #endif -static inline void set_gd(volatile gd_t *gd_ptr) +static inline void set_gd(gd_t *gd_ptr) { #ifdef CONFIG_64BIT asm volatile("ld gp, %0\n" : : "m"(gd_ptr)); diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c index dcd7e5e6b34..1c9a2d70301 100644 --- a/arch/riscv/lib/aclint_ipi.c +++ b/arch/riscv/lib/aclint_ipi.c @@ -29,6 +29,10 @@ int riscv_init_ipi(void) ret = uclass_get_device_by_driver(UCLASS_TIMER, DM_DRIVER_GET(riscv_aclint_timer), &dev); + if (ret == -ENODEV) + ret = uclass_get_device_by_driver(UCLASS_SYSCON, + DM_DRIVER_GET(riscv_aclint_swi), &dev); + if (ret) return ret; @@ -66,6 +70,7 @@ int riscv_get_ipi(int hart, int *pending) static const struct udevice_id riscv_aclint_swi_ids[] = { { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_ACLINT }, + { .compatible = "thead,c900-clint", .data = RISCV_SYSCON_ACLINT }, { } }; diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 9a7a4f6ac8d..38a5ab27dd8 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -36,7 +36,7 @@ __weak void board_init_f(ulong dummy) panic("spl_board_init_f() failed: %d\n", ret); } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb); void *fdt_blob; diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index ecc03785463..7ee4975523e 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -74,7 +74,7 @@ static int spl_board_load_file(struct spl_image_info *spl_image, } /* - * Set up spl_image to boot from jump_to_image_no_args(). Allocate this + * Set up spl_image to boot from jump_to_image(). Allocate this * outsdide the RAM buffer (i.e. don't use strdup()). */ spl_image->arg = os_malloc(strlen(fname) + 1); @@ -112,7 +112,7 @@ static int load_from_image(struct spl_image_info *spl_image, log_info("Reading from pos %lx size %lx\n", pos, size); /* - * Set up spl_image to boot from jump_to_image_no_args(). Allocate this + * Set up spl_image to boot from jump_to_image(). Allocate this * outside the RAM buffer (i.e. don't use strdup()). */ fname = state->prog_fname ? state->prog_fname : state->argv[0]; @@ -159,7 +159,7 @@ void spl_board_init(void) } } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { switch (spl_image->flags) { case SPL_SANDBOXF_ARG_IS_FNAME: { diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 49236db99c2..6a15c8b0a18 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -480,7 +480,9 @@ int state_init(void) state = &main_state; state->ram_size = CFG_SYS_SDRAM_SIZE; - state->ram_buf = os_malloc(state->ram_size); + state->mmap_addr = os_malloc(state->ram_size + SB_SDRAM_ALIGN); + state->ram_buf = (uint8_t *)ALIGN((uintptr_t)state->mmap_addr, + SB_SDRAM_ALIGN); if (!state->ram_buf) { printf("Out of memory\n"); os_exit(1); @@ -533,7 +535,7 @@ int state_uninit(void) trace_set_enabled(0); os_free(state->state_fdt); - os_free(state->ram_buf); + os_free(state->mmap_addr); memset(state, '\0', sizeof(*state)); return 0; diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index 1c9fb4a4566..0d7b0b80e21 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -11,4 +11,4 @@ dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here -DTC_FLAGS += -R 4 -p 0x1000 +DTC_FLAGS += -R 4 diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index dc21a623106..9dea0980bfc 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -75,6 +75,7 @@ struct sandbox_state { char **argv; /* Command line arguments */ const char *jumped_fname; /* Jumped from previous U-Boot */ const char *prog_fname; /* U-Boot executable filename */ + uint8_t *mmap_addr; /* Memory allocated via mmap */ uint8_t *ram_buf; /* Emulated RAM buffer */ unsigned long ram_size; /* Size of RAM buffer */ const char *ram_buf_fname; /* Filename to use for RAM buffer */ diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index 93040e7bb37..f32a10daedd 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -20,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c index 982149b394e..8688232ec34 100644 --- a/arch/x86/cpu/intel_common/acpi.c +++ b/arch/x86/cpu/intel_common/acpi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c index 4a2717b3584..78caff0dc12 100644 --- a/arch/x86/cpu/intel_common/intel_opregion.c +++ b/arch/x86/cpu/intel_common/intel_opregion.c @@ -31,7 +31,6 @@ static int locate_vbt(char **vbtp, int *sizep) size = vbt.size; if (size > sizeof(vbt_data)) return log_msg_ret("vbt", -E2BIG); - vbt.image_pos += CONFIG_ROM_SIZE; ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data); if (ret) return log_msg_ret("read", ret); diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 9a46726e026..725991e2629 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -24,4 +24,4 @@ dtb-y += bayleybay.dtb \ include $(srctree)/scripts/Makefile.dts -DTC_FLAGS += -R 4 -p $(if $(CONFIG_EFI_APP),0x8000,0x1000) +DTC_FLAGS += -R 4 diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h index ef8eb228dbe..639d8f2de78 100644 --- a/arch/x86/include/asm/arch-apollolake/global_nvs.h +++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h @@ -10,6 +10,6 @@ #ifndef _GLOBAL_NVS_H_ #define _GLOBAL_NVS_H_ -#include +#include #endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index de4578666fb..77a8117d158 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index 0be892b14dc..4b5f9889655 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -140,7 +140,7 @@ int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry, if (ret) return log_msg_ret("binman entry", ret); if (!use_spi_flash) - rom_offset = map_base + CONFIG_ROM_SIZE; + rom_offset = map_base; } else { ret = -ENOENT; if (false) diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 6a6cad310bc..01ff034d665 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -277,7 +277,7 @@ int spl_spi_load_image(void) } #ifdef CONFIG_X86_RUN_64BIT -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { int ret; diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index f7df7e03621..06c9e4d02c1 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -101,7 +101,7 @@ int spl_spi_load_image(void) return -EPERM; } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("Jumping to %s at %lx\n", xpl_name(xpl_next_phase()), (ulong)spl_image->entry_point); diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c index c0a163251b4..de206bdf1bc 100644 --- a/board/BuR/brppt2/board.c +++ b/board/BuR/brppt2/board.c @@ -7,6 +7,7 @@ * */ #include +#include #include #include #include diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index b7588fa4eec..baee5afa46d 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include "../drivers/ddr/marvell/a38x/ddr3_init.h" diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index df3fb6d2164..e44b713f96d 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Synology/common/legacy.h b/board/Synology/common/legacy.h index 0a814324d09..f7ba225bd2b 100644 --- a/board/Synology/common/legacy.h +++ b/board/Synology/common/legacy.h @@ -8,6 +8,8 @@ #ifndef __SYNO_LEGACY_H #define __SYNO_LEGACY_H +#include + /* Marvell uboot parameters */ #define ATAG_MV_UBOOT 0x41000403 #define VER_NUM 0x03040400 /* 3.4.4 */ diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index 1a4cea87e1a..02d6a4a1ea8 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Phil Sutter */ +#include #include #include #include diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index b9f47006d61..8c9e9830876 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env index 0c9f9c4178a..90861e622ed 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env @@ -6,7 +6,7 @@ earlycon=lpuart32,0x5a060000 fdt_addr=0x83000000 boot_fdt=try fdt_file=imx8qm-dmsse20-a1.dtb -mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV) +mmcdev= __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index 50b35db5f6c..accd300df04 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -4,6 +4,7 @@ * Copyright 2019-2023 Kococonnector GmbH */ +#include #include #include #include diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index b770a1f8c53..9e87fb9f9d7 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/board/andestech/ae350/ae350.c b/board/andestech/ae350/ae350.c index 1d9d4a929c2..9bdd2ab1780 100644 --- a/board/andestech/ae350/ae350.c +++ b/board/andestech/ae350/ae350.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/board/astro/mcf5373l/Kconfig b/board/astro/mcf5373l/Kconfig deleted file mode 100644 index a7c04cef83d..00000000000 --- a/board/astro/mcf5373l/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASTRO_MCF5373L - -config SYS_CPU - default "mcf532x" - -config SYS_BOARD - default "mcf5373l" - -config SYS_VENDOR - default "astro" - -config SYS_CONFIG_NAME - default "astro_mcf5373l" - -endif diff --git a/board/astro/mcf5373l/MAINTAINERS b/board/astro/mcf5373l/MAINTAINERS deleted file mode 100644 index 6c23da71968..00000000000 --- a/board/astro/mcf5373l/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MCF5373L BOARD -M: Wolfgang Wegner -S: Maintained -F: board/astro/mcf5373l/ -F: include/configs/astro_mcf5373l.h -F: configs/astro_mcf5373l_defconfig diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile deleted file mode 100644 index d3ea0d06a8d..00000000000 --- a/board/astro/mcf5373l/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = mcf5373l.o fpga.o diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h deleted file mode 100644 index b55a6f785ce..00000000000 --- a/board/astro/mcf5373l/astro.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __ASTRO_H__ -#define __ASTRO_H__ - -/* in mcf5373l.c */ -int rs_serial_init(int port, int baud); -void astro_put_char(char ch); -int astro_is_char(void); -int astro_get_char(void); - -/* in fpga.c */ -int astro5373l_altera_load(void); -int astro5373l_xilinx_load(void); - -/* data structures used for communication (update.c) */ -typedef struct card_id { - char card_type; - char hardware_version; - char software_version; - char software_subversion; /* " ","a".."z" */ - char fpga_version_altera; - char fpga_version_xilinx; -} card_id_t; - -typedef struct { - unsigned char mode; - unsigned char deviation; - unsigned short freq; -} __attribute__ ((packed)) output_params_t; - -typedef struct { - unsigned short satfreq; - unsigned char satdatallg; - unsigned short symbolrate; - unsigned char viterbirate; - unsigned char symbolrate_l; - output_params_t output_params; - unsigned char reserve; - unsigned char card_error; - unsigned short dummy_ts_id; - unsigned char dummy_pat_ver; - unsigned char dummy_sdt_ver; -} __attribute__ ((packed)) parameters_t; - -#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c deleted file mode 100644 index 6e505c630d1..00000000000 --- a/board/astro/mcf5373l/fpga.c +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, - * w.wegner@astro-kom.de - * - * based on the files by - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * and - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - */ - -/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" - -int altera_pre_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - - /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ - writeb(0xFE, &gpiop->pclrr_timer); - writeb(0xDF, &gpiop->pclrr_qspi); - return FPGA_SUCCESS; -} - -/* Set the state of CONFIG Pin */ -int altera_config_fn(int assert_config, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_config) - writeb(0x04, &gpiop->ppd_uart); - else - writeb(0xFB, &gpiop->pclrr_uart); - return FPGA_SUCCESS; -} - -/* Returns the state of STATUS Pin */ -int altera_status_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x08) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* Returns the state of CONF_DONE Pin */ -int altera_done_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x20) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* - * writes the complete buffer to the FPGA - * writing the complete buffer in one function is much faster, - * then calling it for every bit - */ -int altera_write_fn(const void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - while (bytecount < len) { - val = data[bytecount++]; - i = 8; - do { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x01) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val >>= 1; - i--; - } while (i > 0); - - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* called, when programming is aborted */ -int altera_abort_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - writeb(0x20, &gpiop->ppd_qspi); - writeb(0x08, &gpiop->ppd_uart); - return FPGA_SUCCESS; -} - -/* called, when programming was succesful */ -int altera_post_fn(int cookie) -{ - return altera_abort_fn(cookie); -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -Altera_CYC2_Passive_Serial_fns altera_fns = { - altera_pre_fn, - altera_config_fn, - altera_status_fn, - altera_done_fn, - altera_write_fn, - altera_abort_fn, - altera_post_fn -}; - -#define FPGA_COUNT 1 -Altera_desc altera_fpga[FPGA_COUNT] = { - {Altera_CYC2, - passive_serial, - 85903, - (void *)&altera_fns, - NULL, - 0} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_altera_load(void) -{ - int i; - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - altera_fns.pre = altera_pre_fn; - altera_fns.config = altera_config_fn; - altera_fns.status = altera_status_fn; - altera_fns.done = altera_done_fn; - altera_fns.write = altera_write_fn; - altera_fns.abort = altera_abort_fn; - altera_fns.post = altera_post_fn; - altera_fpga[i].iface_fns = (void *)&altera_fns; - fpga_add(fpga_altera, &altera_fpga[i]); - } - return 1; -} - -/* Set the FPGA's PROG_B line to the specified level */ -int xilinx_pgm_config_fn(int assert, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert) - writeb(0xFB, &gpiop->pclrr_uart); - else - writeb(0x04, &gpiop->ppd_uart); - return assert; -} - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int xilinx_init_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x08) == 0; -} - -/* Test the state of the active-high FPGA DONE pin */ -int xilinx_done_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; -} - -/* Abort an FPGA operation */ -int xilinx_abort_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - /* ensure all SPI peripherals and FPGAs are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x01, &gpiop->ppd_timer); - writeb(0x38, &gpiop->ppd_qspi); - return FPGA_FAIL; -} - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int xilinx_pre_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - writeb(0x01, &gpiop->ppd_timer); - - /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ - writeb(0xF7, &gpiop->pclrr_uart); - writeb(0xDF, &gpiop->pclrr_qspi); - return 0; -} - -/* - * FPGA post configuration function. Should perform a test if FPGA is running. - */ -int xilinx_post_config_fn(int cookie) -{ - int rc = 0; - - /* - * no test yet - */ - return rc; -} - -int xilinx_clk_config_fn(int assert_clk, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_clk) - writeb(0x04, &gpiop->ppd_qspi); - else - writeb(0xFB, &gpiop->pclrr_qspi); - return assert_clk; -} - -int xilinx_wr_config_fn(int assert_write, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_write) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - return assert_write; -} - -int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - for (bytecount = 0; bytecount < len; bytecount++) { - val = *(data++); - for (i = 8; i > 0; i--) { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x80) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val <<= 1; - } - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -xilinx_spartan3_slave_serial_fns xilinx_fns = { - xilinx_pre_config_fn, - xilinx_pgm_config_fn, - xilinx_clk_config_fn, - xilinx_init_config_fn, - xilinx_done_config_fn, - xilinx_wr_config_fn, - 0, - xilinx_fastwr_config_fn -}; - -xilinx_desc xilinx_fpga[FPGA_COUNT] = { - {xilinx_spartan3, - slave_serial, - XILINX_XC3S4000_SIZE, - (void *)&xilinx_fns, - 0, - &spartan3_op} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_xilinx_load(void) -{ - int i; - - fpga_init(); - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - xilinx_fns.pre = xilinx_pre_config_fn; - xilinx_fns.pgm = xilinx_pgm_config_fn; - xilinx_fns.clk = xilinx_clk_config_fn; - xilinx_fns.init = xilinx_init_config_fn; - xilinx_fns.done = xilinx_done_config_fn; - xilinx_fns.wr = xilinx_wr_config_fn; - xilinx_fns.bwr = xilinx_fastwr_config_fn; - xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; - fpga_add(fpga_xilinx, &xilinx_fpga[i]); - } - return 1; -} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c deleted file mode 100644 index 43fcbc65513..00000000000 --- a/board/astro/mcf5373l/mcf5373l.c +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * modified by Wolfgang Wegner for ASTRO 5373l - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* needed for astro bus: */ -#include -#include "astro.h" - -DECLARE_GLOBAL_DATA_PTR; -extern void uart_port_conf(void); - -int checkboard(void) -{ - puts("Board: "); - puts("ASTRO MCF5373L (Urmel) Board\n"); - return 0; -} - -int dram_init(void) -{ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); - - /* - * GPIO configuration for bus should be set correctly from reset, - * so we do not care! First, set up address space: at this point, - * we should be running from internal SRAM; - * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM, - * and do not care where it is - */ - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, - &sdp->cs0); - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, - &sdp->cs1); - /* - * I am not sure from the data sheet, but it seems burst length - * has to be 8 for the 16 bit data bus we use; - * so these values are for BL = 8 - */ - __raw_writel(0x33211530, &sdp->cfg1); - __raw_writel(0x56570000, &sdp->cfg2); - /* send PrechargeALL, REF and IREF remain cleared! */ - __raw_writel(0xE1462C02, &sdp->ctrl); - udelay(1); - /* refresh SDRAM twice */ - __raw_writel(0xE1462C04, &sdp->ctrl); - udelay(1); - __raw_writel(0xE1462C04, &sdp->ctrl); - /* init MR */ - __raw_writel(0x008D0000, &sdp->mode); - /* initialize EMR */ - __raw_writel(0x80010000, &sdp->mode); - /* wait until DLL is locked */ - udelay(1); - /* - * enable automatic refresh, lock mode register, - * clear iref and ipall - */ - __raw_writel(0x71462C00, &sdp->ctrl); - /* Dummy write to start SDRAM */ - writel(0, CFG_SYS_SDRAM_BASE); -#endif - - /* - * for get_ram_size() to work, both CS areas have to be - * configured, i.e. CS1 has to be explicitely disabled, else - * probing for memory will cause the SDRAM bus to hang! - * (Do not rely on the SDCS register(s) being set to 0x00000000 - * during reset as stated in the data sheet.) - */ - gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, - 0x80000000 - CFG_SYS_SDRAM_BASE); - - return 0; -} - -#define UART_BASE MMAP_UART0 -int rs_serial_init(int port, int baud) -{ - uart_t *uart; - u32 counter; - - switch (port) { - case 0: - uart = (uart_t *)(MMAP_UART0); - break; - case 1: - uart = (uart_t *)(MMAP_UART1); - break; - case 2: - uart = (uart_t *)(MMAP_UART2); - break; - default: - uart = (uart_t *)(MMAP_UART0); - } - - uart_port_conf(); - - /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ - writeb(UART_UCR_RESET_RX, &uart->ucr); - writeb(UART_UCR_RESET_TX, &uart->ucr); - writeb(UART_UCR_RESET_ERROR, &uart->ucr); - writeb(UART_UCR_RESET_MR, &uart->ucr); - __asm__ ("nop"); - - writeb(0, &uart->uimr); - - /* write to CSR: RX/TX baud rate from timers */ - writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); - - writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); - writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); - - /* Setting up BaudRate */ - counter = (u32) (gd->bus_clk / (baud)); - counter >>= 5; - - /* write to CTUR: divide counter upper byte */ - writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); - /* write to CTLR: divide counter lower byte */ - writeb((u8) (counter & 0x00ff), &uart->ubg2); - - writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); - - return 0; -} - -void astro_put_char(char ch) -{ - uart_t *uart; - unsigned long timer; - - uart = (uart_t *)(MMAP_UART0); - /* - * Wait for last character to go. Timeout of 6ms should - * be enough for our lowest baud rate of 2400. - */ - timer = get_timer(0); - while (get_timer(timer) < 6) { - if (readb(&uart->usr) & UART_USR_TXRDY) - break; - } - writeb(ch, &uart->utb); - - return; -} - -int astro_is_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - return readb(&uart->usr) & UART_USR_RXRDY; -} - -int astro_get_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; - return readb(&uart->urb); -} - -int misc_init_r(void) -{ - int retval = 0; - - puts("Configure Xilinx FPGA..."); - retval = astro5373l_xilinx_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - puts("Configure Altera FPGA..."); - retval = astro5373l_altera_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - return retval; -} diff --git a/board/atmel/sam9x75_curiosity/Kconfig b/board/atmel/sam9x75_curiosity/Kconfig new file mode 100644 index 00000000000..8ea93a21aa3 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAM9X75_CURIOSITY + +config SYS_BOARD + default "sam9x75_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sam9x75_curiosity" + +endif diff --git a/board/atmel/sam9x75_curiosity/MAINTAINERS b/board/atmel/sam9x75_curiosity/MAINTAINERS new file mode 100644 index 00000000000..f0dfdbe8d5c --- /dev/null +++ b/board/atmel/sam9x75_curiosity/MAINTAINERS @@ -0,0 +1,7 @@ +SAM9X75 CURIOSITY BOARD +M: Manikandan Muralidharan +S: Maintained +F: board/atmel/sam9x75_curiosity/ +F: include/configs/sam9x75_curiosity.h +F: arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi +F: configs/sam9x75_curiosity_mmc_defconfig diff --git a/board/atmel/sam9x75_curiosity/Makefile b/board/atmel/sam9x75_curiosity/Makefile new file mode 100644 index 00000000000..1f36d613229 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# +# Author: Manikandan Muralidharan + +obj-y += sam9x75_curiosity.o diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c new file mode 100644 index 00000000000..4e7c5667e21 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void at91_prepare_cpu_var(void); + +int board_late_init(void) +{ + at91_prepare_cpu_var(); + + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_dbgu0_hw_init(void) +{ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 1); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 1); /* DTXD */ + + at91_periph_clk_enable(ATMEL_ID_DBGU); +} + +void board_debug_uart_init(void) +{ + board_dbgu0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 04de1257eca..897fab58eba 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; rgb_leds_init(); @@ -82,11 +82,14 @@ int misc_init_r(void) } #endif +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + int dram_init(void) { - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CFG_SYS_SDRAM_SIZE); - return 0; + return fdtdec_setup_mem_size_base(); } /* SPL */ diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 33ba7a7751c..ebbae27c0f9 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h index a5e58186c9c..8ff68f5a64b 100644 --- a/board/bosch/shc/board.h +++ b/board/bosch/shc/board.h @@ -14,6 +14,8 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include + /* Definition to control the GPIOs (for LEDs and Reset) */ #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) @@ -146,7 +148,6 @@ static inline int board_is_series(void) #define RESET_MASK (0x1 << 29) #define HDR_MAGIC 0x43485342 -#define HDR_ETH_ALEN 6 #define HDR_NAME_LEN 8 #define HDR_REV_LEN 8 #define HDR_SER_LEN 16 @@ -176,7 +177,7 @@ struct shc_eeprom { u32 magic; u16 version; u16 lenght; - uint8_t mac_addr[HDR_ETH_ALEN]; + uint8_t mac_addr[ETH_ALEN]; }; void enable_uart0_pin_mux(void); diff --git a/board/bsh/imx6ulz_smm_m2/Kconfig b/board/bsh/imx6ulz_smm_m2/Kconfig index e38df7ce5cb..20971aa4fe1 100644 --- a/board/bsh/imx6ulz_smm_m2/Kconfig +++ b/board/bsh/imx6ulz_smm_m2/Kconfig @@ -9,4 +9,25 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6ulz_smm_m2" +choice + prompt "Memory Type (M2/M2B) board" + default BSH_M2_MEMORY + help + Memory type setup. + Please choose correct memory model here. + +config BSH_M2_MEMORY + bool "Enable for bsh m2 variant" + help + If this option is enabled, U-Boot will be configured to support + imx6ulz bsh m2 revision memories. + +config BSH_M2B_MEMORY + bool "Enable for bsh m2b variant" + help + If this option is enabled, U-Boot will be configured to support + imx6ulz bsh m2b revision memories. + +endchoice + endif diff --git a/board/bsh/imx6ulz_smm_m2/MAINTAINERS b/board/bsh/imx6ulz_smm_m2/MAINTAINERS index 77a033c6cbb..a75cddd72f8 100644 --- a/board/bsh/imx6ulz_smm_m2/MAINTAINERS +++ b/board/bsh/imx6ulz_smm_m2/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/bsh/imx6ulz_smm_m2/ F: include/configs/imx6ulz_smm_m2.h F: configs/imx6ulz_smm_m2_defconfig +F: configs/imx6ulz_smm_m2b_defconfig diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile index 4f4d67f659d..233bbff4c16 100644 --- a/board/bsh/imx6ulz_smm_m2/Makefile +++ b/board/bsh/imx6ulz_smm_m2/Makefile @@ -2,4 +2,6 @@ # (C) Copyright 2021 Amarula Solutions B.V. obj-y := imx6ulz_smm_m2.o -obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_BSH_M2_MEMORY) += ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o +obj-$(CONFIG_BSH_M2B_MEMORY) += ddr3l_timing_256m_m2b.o ddr3l_timing_128m_m2b.o diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c index 66c3483adbf..f11654a8ceb 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c @@ -166,4 +166,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { struct dram_timing_info bsh_dram_timing_128mb = { .ddrc_cfg = ddr_ddrc_cfg_128mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), + .dram_size = SZ_128M, }; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c new file mode 100644 index 00000000000..f989e24f567 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ + + /* Address: */ + {0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured + * using Group Control Register IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ + {0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ + {0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:WINBOND + * Device Part Number:W631GU6RB-11 + * Clock Freq.: 400MHz + * Density per CS in Gb: 1 + * Chip Selects used:1 + * Total DRAM density (Gb)1 + * Number of Banks:8 + * Row address: 13 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit + * during MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune + * these settings. + */ + {0x021b080c, 0x00060002}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x414c0150}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x4040363e}, /* MPRDDLCTL PHY0 */ + + /* Write calibration */ + {0x021b0850, 0x40402a28}, /* MPWRDLCTL PHY0 */ + + /* + * Read data bit delay: 3 is the recommended default value, although out of reset + * value is 0. + */ + {0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + /* Write data bit delay: */ + {0x021b082c, 0xf3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021b0830, 0xf3333333}, /* MMDC_MPWRDQBY1DL */ + + /* DQS&CLK Duty Cycle */ + {0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */ + + /* Complete calibration by forced measurement: */ + {0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* MMDC init: */ + {0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + {0x021b0018, 0x00201740}, /* MMDC0_MDMISC */ + {0x021b002C, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x002F1023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000043}, /* CS0_END */ + {0x021b0000, 0x82180000}, /* MMDC0_MDCTL */ + + /* Mode register writes for CS0 */ + {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */ + {0x021B001C, 0x04008040}, /* + * MMDC0_MDSCR, ZQ calibration + * command sent to device on CS0 + */ + + /* final DDR setup, before operation start: */ + {0x021b0020, 0x00000800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + + {0x021b0004, 0x0002556D}, /* MMDC0_MDPDC now SDCTL power down enabled */ + + {0x021b0404, 0x00011006}, /* + * MMDC0_MAPSR ADOPT power down enabled, + * MMDC will enter automatically to self-refresh + * while the number of idle cycle reached. + */ + + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially the + * configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_128mb = { + .ddrc_cfg = ddr_ddrc_cfg_128mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), + .dram_size = SZ_128M, +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c index 0fe5b90a673..5dfc9f5c70d 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c @@ -165,4 +165,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = { struct dram_timing_info bsh_dram_timing_256mb = { .ddrc_cfg = ddr_ddrc_cfg_256mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb), + .dram_size = SZ_256M, }; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c new file mode 100644 index 00000000000..c44f632b928 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */ + + /* Address: */ + {0x020e0250, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be + * configured using Group Control Register: + * IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */ + {0x020e0264, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */ + {0x020e0284, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:WINBOND + * Device Part Number:W632GU6RB-11 + * Clock Freq.: 400MHz + * Density per CS in Gb: 2 + * Chip Selects used:1 + * Total DRAM density (Gb)2 + * Number of Banks:8 + * Row address: 14 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit + * during MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune + * these settings. + */ + {0x021b080c, 0x00070005}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x414c0150}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x4040383e}, /* MMDC_MPRDDLCTL */ + + /* Write calibration */ + {0x021b0850, 0x40402e2a}, /* MMDC_MPWRDLCTL */ + + {0x021B081C, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021B0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + {0x021B082C, 0xf3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021B0830, 0xf3333333}, /* MMDC_MPWRDQBY1DL */ + + {0x021B08C0, 0x00944009}, /* MMDC_MPDCCR */ + + /* Complete calibration by forced measurement: */ + {0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* MMDC init: */ + {0x021b0004, 0x00020024}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x3F4352D3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + {0x021b0018, 0x00201740}, /* MMDC0_MDMISC */ + {0x021b002C, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x00431023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000047}, /* CS0_END */ + {0x021b0000, 0x83180000}, /* MMDC0_MDCTL */ + + /* Mode register writes for CS0 */ + {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */ + {0x021B001C, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration */ + + /* final DDR setup, before operation start: */ + {0x021b0020, 0x00000800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + {0x021b0004, 0x00025564}, /* MMDC0_MDPDC now SDCTL power down enabled */ + {0x021b0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */ + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially + * the configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_256mb = { + .ddrc_cfg = ddr_ddrc_cfg_256mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb), + .dram_size = SZ_256M, +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c index f5989382f5a..4c2ffcd429d 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c @@ -165,4 +165,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { struct dram_timing_info bsh_dram_timing_512mb = { .ddrc_cfg = ddr_ddrc_cfg_512mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb), + .dram_size = SZ_512M, }; diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index c330e4d6d39..7aea73f0f5d 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -52,28 +52,31 @@ static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info) } } +static const struct dram_timing_info *board_dram_timing[] = { +#if defined(CONFIG_M2_MEMORY) + &bsh_dram_timing_512mb, +#endif + &bsh_dram_timing_256mb, + &bsh_dram_timing_128mb, +}; + static void spl_dram_init(void) { /* Configure memory to maximum supported size for detection */ - ddr_cfg_write(&bsh_dram_timing_512mb); + ddr_cfg_write(board_dram_timing[0]); /* Detect memory physically present */ - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, board_dram_timing[0]->dram_size); - /* Reconfigure memory for actual detected size */ - switch (gd->ram_size) { - case SZ_512M: - /* Already configured, nothing to do */ - break; - case SZ_256M: - udelay(1); - ddr_cfg_write(&bsh_dram_timing_256mb); - break; - case SZ_128M: - default: - udelay(1); - ddr_cfg_write(&bsh_dram_timing_128mb); - break; + if (board_dram_timing[0]->dram_size == gd->ram_size) + return; + + for (size_t index = 1; index < ARRAY_SIZE(board_dram_timing); index++) { + if (board_dram_timing[index]->dram_size == gd->ram_size) { + udelay(1); + ddr_cfg_write(board_dram_timing[index]); + break; + } } } diff --git a/board/bsh/imx6ulz_smm_m2/spl_mtypes.h b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h index 8da59881c83..06d6f2d76d8 100644 --- a/board/bsh/imx6ulz_smm_m2/spl_mtypes.h +++ b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h @@ -18,6 +18,7 @@ struct dram_cfg_param { struct dram_timing_info { const struct dram_cfg_param *ddrc_cfg; unsigned int ddrc_cfg_num; + size_t dram_size; }; extern struct dram_timing_info bsh_dram_timing_128mb; diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index 054e4e10867..03be02a2884 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -4,6 +4,7 @@ * Copyright (C) 2019 Oliver Graute */ #include +#include #include #include #include diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index 9e35dc5d6cb..7d344792937 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 71010803f55..8c052c45007 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d30171f1fbe..f7347bbb826 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c index 393fcaeb742..8a59f5ade13 100644 --- a/board/emulation/common/qemu_dfu.c +++ b/board/emulation/common/qemu_dfu.c @@ -7,6 +7,7 @@ #include #include #include +#include #define DFU_ALT_BUF_LEN SZ_1K diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 194a0907e72..3d44357caf7 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -134,7 +134,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) /* Override weak funtion defined in SPL framework to enable validation * of main u-boot image before jumping to u-boot image. */ -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); uint32_t hdr_addr; diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 7815ba2dbce..04cad48f033 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "qixis.h" diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 784046ac4e0..0a0df6f34f8 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -136,8 +136,8 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 -#define QIXIS_DAT5_6_7 0X02 -#define QIXIS_DAT4 0X01 +#define QIXIS_DAT5_6_7 0x02 +#define QIXIS_DAT4 0x01 #define QIXIS_EVDD_BY_SDHC_VS 0x0c diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index d41db8d31d8..ecc20768cb5 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -3,6 +3,8 @@ * Copyright 2018 NXP */ +#include +#include #include #include #include @@ -15,6 +17,26 @@ DECLARE_GLOBAL_DATA_PTR; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \ + 0xa2, 0x82, 0xeb, 0x85, 0x8b, 0x6b) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MM-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.env b/board/freescale/imx8mm_evk/imx8mm_evk.env index 29690e75b15..299b8472c74 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.env +++ b/board/freescale/imx8mm_evk/imx8mm_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index c62d7a47e21..9d3f29f2253 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -5,9 +5,31 @@ #include #include +#include +#include #include #include +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xcbabf44d, 0x12cc, 0x45dd, 0xb0, 0xc5, \ + 0x29, 0xc5, 0xb7, 0x42, 0x2d, 0x34) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MN-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_mmc_get_env_dev(int devno) { return devno; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.env b/board/freescale/imx8mn_evk/imx8mn_evk.env index 16a6543ffc6..487893f9287 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.env +++ b/board/freescale/imx8mn_evk/imx8mn_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 2ff067bc675..2a9ba7df2bb 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -4,8 +4,31 @@ */ #include +#include +#include #include +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x928b33bc, 0xe58b, 0x4247, 0x9f, 0x1d, \ + 0x3b, 0xf1, 0xee, 0x1c, 0xda, 0xff) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MP-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + + int board_init(void) { return 0; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.env b/board/freescale/imx8mp_evk/imx8mp_evk.env index f70e18fa9d9..18cdf3da056 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.env +++ b/board/freescale/imx8mp_evk/imx8mp_evk.env @@ -10,7 +10,7 @@ fdt_addr=0x43000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image ip_dyn=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index 18e83d90a08..e90c56c33ff 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) @@ -22,6 +23,26 @@ static iomux_v3_cfg_t const uart_pads[] = { IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x296119cf, 0xdd70, 0x43de, 0x8a, 0xc8, \ + 0xa7, 0x05, 0x1f, 0x31, 0x25, 0x77) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MQ-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.env b/board/freescale/imx8mq_evk/imx8mq_evk.env index dcfe1c2f2d4..cab8c6b70bf 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.env +++ b/board/freescale/imx8mq_evk/imx8mq_evk.env @@ -12,7 +12,7 @@ ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted; diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 0af61067263..4bf77a488cc 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include #include #include diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx91_evk/imx91_evk.env +++ b/board/freescale/imx91_evk/imx91_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index c9171df330e..d84d56be5e1 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -28,6 +29,26 @@ static iomux_v3_cfg_t const uart_pads[] = { MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); diff --git a/board/freescale/imx93_evk/imx93_evk.env b/board/freescale/imx93_evk/imx93_evk.env index 8c3aef6b557..d5ed216f54b 100644 --- a/board/freescale/imx93_evk/imx93_evk.env +++ b/board/freescale/imx93_evk/imx93_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_qsb/imx93_qsb.env b/board/freescale/imx93_qsb/imx93_qsb.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.env +++ b/board/freescale/imx93_qsb/imx93_qsb.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx95_evk/imx95_19x19_evk.env b/board/freescale/imx95_evk/imx95_19x19_evk.env index a002767e874..a7309d734b0 100644 --- a/board/freescale/imx95_evk/imx95_19x19_evk.env +++ b/board/freescale/imx95_evk/imx95_19x19_evk.env @@ -14,7 +14,7 @@ cntr_file=os_cntr_signed.bin boot_fit=no fdtfile=CONFIG_DEFAULT_FDT_FILE bootm_size=0x10000000 -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index bda2f3ac3a6..39b6c6449cf 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -7,6 +7,7 @@ #include #include +#include #include #include "cpld.h" diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 7f8ca2e857f..26a5962bd6e 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -7,6 +7,7 @@ #include #include +#include #include #include "cpld.h" diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 446a79e6723..50c5320b55c 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -93,6 +93,7 @@ int testdram(void) #ifdef CONFIG_IDE #include +#include void ide_set_reset(int idereset) { atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 3db167c0dad..bef4f901ff7 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c index 915a8b994d5..2bba377d4d4 100644 --- a/board/freescale/p2041rdb/cpld.c +++ b/board/freescale/p2041rdb/cpld.c @@ -12,6 +12,7 @@ */ #include +#include #include #include "cpld.h" diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index cc933ccd544..00ea9d8f503 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -9,6 +9,7 @@ #include #include +#include #include #include "cpld.h" diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index c2d526ae15a..038e40e2fae 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -12,6 +12,7 @@ #include #include +#include #include #include "cpld.h" diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index d2226af6278..838d88d977e 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -7,6 +7,7 @@ #include #include +#include #include #include "cpld.h" diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index f076350c1c5..258581eee96 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -16,6 +16,7 @@ #include #include +#include #include #include "cpld.h" diff --git a/board/gateworks/fsa.c b/board/gateworks/fsa.c new file mode 100644 index 00000000000..1af8021057c --- /dev/null +++ b/board/gateworks/fsa.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Gateworks Corporation + */ + +#include +#include +#include +#include +#include +#include +#include // device_remove/device_unbind +#include +#include +#include + +#include "fsa.h" + +static int fsa; +static struct udevice *fsa_gpiodevs[FSA_MAX] = { NULL }; + +/* find the ofnode of the FSA i2c bus */ +static ofnode fsa_get_ofnode(int fsa) +{ + char str[32]; + + /* by alias */ + snprintf(str, sizeof(str), "fsa%d", fsa); + return ofnode_get_aliases_node(str); +} + +static int fsa_get_dtnode(void *fdt, int fsa) +{ + char str[32]; + + /* by alias */ + snprintf(str, sizeof(str), "fsa%d", fsa); + return fdt_path_offset(fdt, fdt_get_alias(fdt, str)); +} + +static const char * const fsa_gpio_config_names[] = { "NC", "", "input", "output-low", + "output-high" }; + +static const char *fsa_gpio_config_name(struct fsa_gpio_desc *desc) +{ + if (desc->config < ARRAY_SIZE(fsa_gpio_config_names)) + return fsa_gpio_config_names[desc->config]; + return NULL; +}; + +static char *fsa_get_gpio_desc(struct fsa_gpio_desc *desc, char *str, int sz) +{ + str[0] = 0; + if (desc->source == 0xff) { + snprintf(str, sz, "fsa_gpio%d : %s %s", + desc->offset + 1, + desc->name, + fsa_gpio_config_name(desc)); + } else if (desc->config) { + snprintf(str, sz, "gpio@%02x_%02d: %s %s", + desc->source, + desc->offset, + desc->name, + fsa_gpio_config_name(desc)); + } + return str; +} + +static void fsa_show_gpio_descs(const char *prefix, int fsa, struct fsa_board_info *board_info, + struct fsa_user_info *user_info) +{ + char str[128]; + int i; + + /* display slot specific gpios */ + for (i = 0; i < board_info->sockgpios; i++) { + fsa_get_gpio_desc(&user_info->gpios[i], str, sizeof(str)); + printf("%s%-2d: %s\n", prefix, i, str); + } + /* display io-expander specific gpios */ + if (fsa_gpiodevs[fsa]) { + for (i = board_info->sockgpios; + i < (board_info->sockgpios + board_info->ioexpgpios); + i++) { + fsa_get_gpio_desc(&user_info->gpios[i], str, sizeof(str)); + printf("%s%-2d: %s\n", prefix, i, str); + } + } +} + +/* detect gpio expander by address and deal with enabling/disabling/adding gpio expander to dt */ +static int fsa_get_gpiodev(int fsa, int addr, struct udevice **devp) +{ + struct udevice *bus, *dev; + char gpio_name[32]; + int ret; + + ret = device_get_global_by_ofnode(fsa_get_ofnode(fsa), &bus); + if (ret) + return ret; + + sprintf(gpio_name, "gpio@%02x", addr); + + /* probe device on i2c bus */ + ret = dm_i2c_probe(bus, addr, 0, &dev); + switch (ret) { + case -EREMOTEIO: /* chip is not present on i2c bus */ + /* if device is in dt remove/unbind/disable it */ + ret = device_find_child_by_name(bus, gpio_name, &dev); + if (ret) + return ret; + ret = ofnode_set_enabled(dev_ofnode(dev), false); + if (ret) + return ret; + ret = device_unbind(dev); + if (ret) + return ret; + ret = device_remove(dev, DM_REMOVE_NORMAL); + if (ret) + return ret; + return ret; + case -ENOSYS: /* chip found but driver invalid */ + /* if device is in not in dt add/bind it */ + return ret; + case 0: /* chip responded and driver bound */ + break; + } + + if (devp) + *devp = dev; + return 0; +} + +/* add gpio's to gpio device: GPIO device must be probed before you can manipulate it */ +static int fsa_config_gpios(int fsa, struct fsa_user_info *info, int gpios, struct udevice *dev) +{ + struct fsa_gpio_desc *desc; + struct gpio_desc gdesc; + struct udevice *gdev; + int i, ret, flags; + char name[32]; + + /* configure GPIO's */ + for (i = 0; i < gpios; i++) { + desc = &info->gpios[i]; + if (desc->config < FSA_GPIO_INPUT) + continue; + memset(&gdesc, 0, sizeof(gdesc)); + + if (desc->source == 0xff) { + /* Board specific IMX8M GPIO's: find dev of controller by line-name */ + sprintf(name, "fsa%d_gpio%d", fsa, desc->offset + 1); + uclass_foreach_dev_probe(UCLASS_GPIO, gdev) { + ret = dev_read_stringlist_search(gdev, "gpio-line-names", name); + if (ret >= 0) { + gdesc.dev = gdev; + gdesc.offset = ret; + break; + } + } + } else { + /* port expander GPIOs */ + gdesc.dev = dev; + gdesc.offset = desc->offset; + } + + if (!gdesc.dev) + continue; + + sprintf(name, "fsa%d_%s", fsa, desc->name); + switch (desc->config) { + case FSA_GPIO_INPUT: + flags = GPIOD_IS_IN; + break; + case FSA_GPIO_OUTPUT_LOW: + flags = GPIOD_IS_OUT; + break; + case FSA_GPIO_OUTPUT_HIGH: + flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; + break; + } + if (!dm_gpio_request(&gdesc, name)) + dm_gpio_clrset_flags(&gdesc, GPIOD_MASK_DIR, flags); + } + + return 0; +} + +static int fsa_read_board_config(int fsa, struct fsa_board_info *info) +{ + struct udevice *dev; + int chksum; + int i, ret; + ofnode node; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@54"); + if (!ofnode_valid(node)) + return -EINVAL; + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + + /* read eeprom */ + ret = dm_i2c_read(dev, 0, (uint8_t *)info, sizeof(*info)); + if (ret) { + dev_err(dev, "read failed: %d\n", ret); + return ret; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + dev_err(dev, "FSA%d EEPROM: Invalid User Config Checksum\n", fsa); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, info, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + +static int fsa_read_user_config(int fsa, struct fsa_user_info *info) +{ + struct udevice *dev; + int chksum; + int i, ret; + ofnode node; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@55"); + if (!ofnode_valid(node)) + return -EINVAL; + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + + /* read eeprom */ + ret = dm_i2c_read(dev, 0, (uint8_t *)info, sizeof(*info)); + if (ret) { + dev_err(dev, "read failed: %d\n", ret); + return ret; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + dev_err(dev, "FSA%d EEPROM: Invalid User Config Checksum\n", fsa); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, info, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + +static int fsa_write_user_config(int fsa, struct fsa_user_info *info) +{ + struct udevice *bus, *dev; + int i, n, chunk, slave, base, ret; + ofnode node; + int chksum; + + /* create checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + info->chksum[0] = chksum >> 8; + info->chksum[1] = chksum & 0xff; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@55"); + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + bus = dev->parent; + base = dev_read_addr(dev); + + /* write in 16byte chunks (multi-byte writes fail larger than that) */ + chunk = 16; + slave = -1; + for (i = 0; i < sizeof(*info); i += chunk) { + /* select device based on offset */ + if ((base + (i / 256)) != slave) { + slave = base + (i / 256); + ret = i2c_get_chip(bus, slave, 1, &dev); + if (ret) { + dev_err(bus, "failed to get eeprom@0x%02x: %d\n", slave, ret); + return ret; + } + } + /* select byte count */ + n = sizeof(*info) - i; + if (n > chunk) + n = chunk; + ret = dm_i2c_write(dev, i % 256, (uint8_t *)info + i, n); + if (ret) { + dev_err(dev, "write failed: %d\n", ret); + return ret; + } + mdelay(11); + } + + return ret; +} + +static int fsa_detect(int fsa, struct fsa_board_info *board_info, struct fsa_user_info *user_info, + bool gpio) +{ + int ret; + + ret = fsa_read_board_config(fsa, board_info); + if (ret) + return ret; + if (user_info) { + ret = fsa_read_user_config(fsa, user_info); + if (ret) + return ret; + /* detect port expander */ + if (gpio && !fsa_get_gpiodev(fsa, 0x20, &fsa_gpiodevs[fsa])) + fsa_config_gpios(fsa, user_info, + board_info->sockgpios + board_info->ioexpgpios, + fsa_gpiodevs[fsa]); + } + + return ret; +} + +static int ft_fixup_stringlist_elem(void *fdt, int offset, const char *prop, int elem, + const char *val) +{ + const char *list, *end; + char *new, *buf; + int length; + int sz = 0; + int i = 0; + int ret; + + if (offset < 0 || elem < 0 || !val) { + printf("%s -EINVAL\n", __func__); + return -EINVAL; + } + + list = fdt_getprop(fdt, offset, prop, &length); + + /* no property or invalid params */ + if (!list || length < 0) { + printf("%s failed - no property\n", __func__); + return -EINVAL; + } + + /* create new buffer with enough space */ + buf = calloc(1, length + strlen(val)); + new = buf; + + /* iterate over current stringlist and build new list into buf */ + end = list + length; + while (list < end) { + length = strnlen(list, end - list) + 1; + sz += length; + /* insert new value into buf */ + if (elem == i) { + strcpy(new, val); + new += strlen(val) + 1; + } else { + strcpy(new, list); + new += length; + } + list += length; + i++; + } + length = new - buf; + ret = fdt_setprop(fdt, offset, prop, buf, length); + free(buf); + if (ret) + printf("%s failed %d\n", __func__, ret); + + return ret; +} + +static int ft_fixup_fsa_gpio_name(void *fdt, int offset, int fsa, int gpio, const char *name) +{ + const char *prop = "gpio-line-names"; + char str[32]; + + sprintf(str, "fsa%d_%s", fsa, name); + + if (!fdt_getprop(fdt, offset, prop, NULL)) { + char buf[16] = { 0 }; + + fdt_setprop(fdt, offset, prop, &buf, sizeof(buf)); + } + + return ft_fixup_stringlist_elem(fdt, offset, prop, gpio, str); +} + +static void fsa_show_details(int fsa, struct fsa_board_info *board, struct fsa_user_info *user) +{ + printf("FSA%d: %s\n", fsa, board->model); + printf("description: %s\n", user->desc); + printf("overlay: %s\n", user->overlay); + fsa_show_gpio_descs("\t", fsa, board, user); +} + +int fsa_init(void) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int fsa, ret; + + for (fsa = 1; fsa < FSA_MAX; fsa++) { + ret = fsa_detect(fsa, &board_info, &user_info, true); + if (!ret) + printf("FSA%d: %s %s\n", fsa, board_info.model, user_info.desc); + } + + return 0; +} + +int fsa_show(void) +{ + struct fsa_board_info board_info; + int fsa, ret; + + for (fsa = 1; fsa < FSA_MAX; fsa++) { + ret = fsa_detect(fsa, &board_info, NULL, false); + if (!ret) { + printf("FSA%d : %s %d %02x-%02x-%02x%02x\n", fsa, + board_info.model, board_info.serial, + board_info.mfgdate[0], board_info.mfgdate[1], + board_info.mfgdate[2], board_info.mfgdate[3]); + } + } + return 0; +} + +/* fixup gpio line names for fsa gpios */ +int fsa_ft_fixup(void *fdt) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int fsa, i, ret; + char path[128]; + char str[32]; + ofnode node; + int off; + + /* iterate over FSA's and rename gpio's */ + for (fsa = 1; fsa < FSA_MAX; fsa++) { + /* disable FSA ioexp node if disabled in controlling dt */ + off = fdt_subnode_offset(fdt, fsa_get_dtnode(fdt, fsa), "gpio@20"); + if (off >= 0) { + if (!fdt_get_path(fdt, off, path, sizeof(path))) { + node = ofnode_path(path); + if (ofnode_valid(node) && !ofnode_is_enabled(node)) + fdt_setprop_string(fdt, off, "status", "disabled"); + } + } + + /* detect FSA eeprom */ + if (fsa_detect(fsa, &board_info, &user_info, false)) + continue; + + /* configure GPIO's */ + for (i = 0; i < board_info.sockgpios + board_info.ioexpgpios; i++) { + if (user_info.gpios[i].config < FSA_GPIO_INPUT) + continue; + + if (user_info.gpios[i].source == 0xff) { + /* Board specific IMX8M GPIO's */ + for (off = fdt_node_offset_by_prop_value(fdt, 0, + "gpio-controller", NULL, + 0); + off >= 0; + off = fdt_node_offset_by_prop_value(fdt, off, + "gpio-controller", NULL, + 0) + ) { + sprintf(str, "fsa%d_gpio%d", fsa, + user_info.gpios[i].offset + 1); + ret = fdt_stringlist_search(fdt, off, "gpio-line-names", + str); + if (ret >= 0) { + ft_fixup_fsa_gpio_name(fdt, off, fsa, ret, + user_info.gpios[i].name); + break; + } + } + } else { + /* port expander GPIOs */ + off = fdt_subnode_offset(fdt, fsa_get_dtnode(fdt, fsa), "gpio@20"); + ft_fixup_fsa_gpio_name(fdt, off, fsa, user_info.gpios[i].offset, + user_info.gpios[i].name); + } + } + } + + return 0; +} + +static int do_fsa_dev(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int i; + + if (argc < 2) { + /* list FSAs */ + printf("detecting FSA Adapters:\n"); + for (i = 1; i < FSA_MAX; i++) { + if (!fsa_read_board_config(i, &board_info) && + !fsa_read_user_config(i, &user_info)) + printf("FSA%d : %s %s\n", i, board_info.model, user_info.desc); + } + } else { + /* select FSA */ + fsa = simple_strtoul(argv[1], NULL, 10); + } + + if (fsa) { + /* read FSA */ + if (!fsa_read_board_config(fsa, &board_info) && + !fsa_read_user_config(fsa, &user_info)) { + printf("selected:\n"); + fsa_show_details(fsa, &board_info, &user_info); + } else { + printf("FSA%d not detected\n", fsa); + fsa = 0; + } + } else { + printf("no FSA currently selected\n"); + } + + return 0; +} + +static int do_fsa_desc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + /* set */ + if (argc) { + strlcpy(user_info.desc, argv[0], sizeof(user_info.desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + } + + /* show */ + fsa_show_details(fsa, &board_info, &user_info); + + return CMD_RET_SUCCESS; +} + +static int do_fsa_overlay(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + /* set */ + if (argc) { + strlcpy(user_info.overlay, argv[0], sizeof(user_info.overlay)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + } + + /* show */ + fsa_show_details(fsa, &board_info, &user_info); + + return CMD_RET_SUCCESS; +} + +static int do_fsa_gpio(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + struct fsa_gpio_desc desc; + char str[64]; + int i, j; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + if (!argc) { + /* show all gpios */ + fsa_show_gpio_descs("\t", fsa, &board_info, &user_info); + return CMD_RET_SUCCESS; + } + + if (!isdigit(argv[0][0])) { + printf("invalid gpio offset: %s\n", argv[0]); + return CMD_RET_USAGE; + } + + memset(&desc, 0, sizeof(desc)); + i = simple_strtoul(argv[0], NULL, 10); + + if (i >= 0 && i < board_info.sockgpios) { + desc.offset = i; + desc.source = 0xff; + } else if (i >= board_info.sockgpios && + i < (board_info.sockgpios + board_info.ioexpgpios) && + fsa_gpiodevs[fsa]) { + desc.offset = i - board_info.sockgpios; + desc.source = 0x20; + } else { + printf("invalid index %d", i); + return CMD_RET_FAILURE; + } + + if (argc > 1) { + if (user_info.gpios[i].config == FSA_GPIO_NC) { + printf("can not alter NC gpio\n"); + return CMD_RET_FAILURE; + } + strlcpy(desc.name, argv[1], sizeof(desc.name)); + if (!*desc.name) { + printf("FSA%d %s erasing gpio %d\n", fsa, board_info.model, i); + memset(&user_info.gpios[i], 0, sizeof(desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + } + if (argc > 2) { + if (user_info.gpios[i].config == FSA_GPIO_NC) { + printf("can not alter NC gpio\n"); + return CMD_RET_FAILURE; + } + for (j = 1; j < ARRAY_SIZE(fsa_gpio_config_names); j++) { + if (!strcasecmp(argv[2], fsa_gpio_config_names[j])) { + desc.config = j; + break; + } + }; + if (j >= ARRAY_SIZE(fsa_gpio_config_names)) { + printf("invalid config type '%s\n", argv[2]); + return CMD_RET_FAILURE; + } + } + + /* show a specific gpio */ + if (argc == 1) { + printf("FSA%d %s showing gpio %d\n", fsa, board_info.model, i); + printf("%s\n", fsa_get_gpio_desc(&user_info.gpios[i], str, sizeof(str))); + return CMD_RET_SUCCESS; + } + + /* set a specific gpio */ + else if (argc == 3) { + printf("FSA%d %s updating gpio %d\n", fsa, board_info.model, i); + memcpy(&user_info.gpios[i], &desc, sizeof(desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + + return CMD_RET_USAGE; +} + +static struct cmd_tbl cmd_fsa_sub[] = { + U_BOOT_CMD_MKENT(dev, 1, 1, do_fsa_dev, "", ""), + U_BOOT_CMD_MKENT(gpio, 4, 1, do_fsa_gpio, "", ""), + U_BOOT_CMD_MKENT(description, 1, 1, do_fsa_desc, "", ""), + U_BOOT_CMD_MKENT(overlay, 1, 1, do_fsa_overlay, "", ""), +}; + +static int do_fsa(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct cmd_tbl *c; + + /* strip off leading fsa arg */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_fsa_sub, ARRAY_SIZE(cmd_fsa_sub)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + return CMD_RET_USAGE; +} + +U_BOOT_LONGHELP(fsa, + "dev [dev] - show or set current FSA adapter\n" + "fsa gpio - show current gpio descriptors\n" + "fsa gpio []|[ ] - show a specific gpio descriptor\n" + "fsa gpio [ [source]] - set a gpio descriptor\n" + "fsa description [description] - show or set the FSA user description string\n" + "fsa overlay [overlay] - show or set the FSA overlay string\n" +); + +U_BOOT_CMD(fsa, 6, 1, do_fsa, + "Flexible Socket Adapter", + fsa_help_text +); diff --git a/board/gateworks/fsa.h b/board/gateworks/fsa.h new file mode 100644 index 00000000000..ddb64499d78 --- /dev/null +++ b/board/gateworks/fsa.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 Gateworks Corporation + */ + +#ifndef _FSA_H_ +#define _FSA_H_ + +#define FSA_MAX 5 + +enum fsa_gpio_cfg { + FSA_GPIO_NC, + FSA_GPIO_UNCONFIGURED, + FSA_GPIO_INPUT, + FSA_GPIO_OUTPUT_LOW, + FSA_GPIO_OUTPUT_HIGH, +}; + +struct fsa_gpio_desc { + u8 offset; + u8 config; + u8 source; + char name[13]; +}; + +struct fsa_board_info { + char model[16]; /* 0x00: model string */ + u8 mac[6]; /* 0x10: MAC base */ + u8 macno; /* 0x16: number of mac addrs */ + u8 resv1; /* 0x17: reserved */ + u32 serial; /* 0x18: Serial Number */ + u8 mfgdate[4]; /* 0x1c: MFG date */ + u8 sockgpios; /* 0x20: number of socket gpio descriptors */ + u8 ioexpgpios; /* 0x21: number of io expander gpio descriptors */ + u8 resv2[220]; /* 0x22: reserved */ + u8 chksum[2]; /* 0xfe: */ +}; + +struct fsa_user_info { + char desc[32]; /* 0x000: user description */ + char overlay[16]; /* 0x020: dt-overlay suffice */ + struct fsa_gpio_desc gpios[20]; /* 0x030: gpio descriptors */ + u8 reserved[398]; /* 0x170: reserved */ + u8 chksum[2]; /* 0x2fe: */ +}; + +int fsa_init(void); +int fsa_show(void); +int fsa_ft_fixup(void *fdt); + +#endif // _FSA_H_ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 21a908c20dd..457d8281a66 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 3de4727b2ed..4385732a617 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -366,34 +366,34 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00480047, - .p0_mpwldectrl1 = 0X003D003F, + .p0_mpwldectrl0 = 0x00480047, + .p0_mpwldectrl1 = 0x003D003F, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0X423E0241, - .p0_mpdgctrl1 = 0X022B022C, + .p0_mpdgctrl0 = 0x423E0241, + .p0_mpdgctrl1 = 0x022B022C, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X49454A4A, + .p0_mprddlctl = 0x49454A4A, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X2E372C32, + .p0_mpwrdlctl = 0x2E372C32, }; static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00220021, - .p0_mpwldectrl1 = 0X00200030, - .p1_mpwldectrl0 = 0X002D0027, - .p1_mpwldectrl1 = 0X00150026, + .p0_mpwldectrl0 = 0x00220021, + .p0_mpwldectrl1 = 0x00200030, + .p1_mpwldectrl0 = 0x002D0027, + .p1_mpwldectrl1 = 0x00150026, /* Read DQS Gating calibration */ .p0_mpdgctrl0 = 0x43330342, .p0_mpdgctrl1 = 0x0339034A, .p1_mpdgctrl0 = 0x032F0325, .p1_mpdgctrl1 = 0x032F022E, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X3A2E3437, - .p1_mprddlctl = 0X35312F3F, + .p0_mprddlctl = 0x3A2E3437, + .p1_mprddlctl = 0x35312F3F, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X33363B37, - .p1_mpwrdlctl = 0X40304239, + .p0_mpwrdlctl = 0x33363B37, + .p1_mpwrdlctl = 0x40304239, }; static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile index ab69e07ba7b..1aaf0295d5c 100644 --- a/board/gateworks/venice/Makefile +++ b/board/gateworks/venice/Makefile @@ -5,6 +5,7 @@ # obj-y += venice.o eeprom.o +obj-y += ../fsa.o ifdef CONFIG_XPL_BUILD obj-y += spl.o diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index afaabf34879..d9a87193434 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -6,9 +6,11 @@ #include #include #include +#include #include #include "eeprom.h" +#include "../fsa.h" /* I2C */ #define SOM_EEPROM_BUSNO 0 @@ -18,7 +20,8 @@ struct venice_board_info som_info; struct venice_board_info base_info; -char venice_model[32]; +char venice_model[64]; +char venice_som_model[32]; char venice_baseboard_model[32]; u32 venice_serial; @@ -107,7 +110,7 @@ static int eeprom_read(int busno, int slave, int alen, struct venice_board_info /* validate checksum */ for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) chksum += buf[i]; - if ((info->chksum[0] != chksum >> 8) || + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || (info->chksum[1] != (chksum & 0xff))) { printf("EEPROM: I2C%d@0x%02x: Invalid Checksum\n", busno, slave); print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info)); @@ -126,6 +129,54 @@ static int eeprom_read(int busno, int slave, int alen, struct venice_board_info return 0; } +static int fsa_eeprom_read(const char *base, int fsa, struct fsa_board_info *info) +{ + int i; + int chksum; + unsigned char *buf = (unsigned char *)info; + struct udevice *dev, *bus; + int ret; + u8 reg; + + /* probe mux */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 2, &bus); + if (!ret) + ret = dm_i2c_probe(bus, 0x70, 0, &dev); + if (ret) + return ret; + /* steer mux */ + if (!strncmp(base, "GW82", 4)) { + if (fsa < 3) + reg = (fsa == 1) ? BIT(1) : BIT(0); + else + return -EINVAL; + } + dm_i2c_write(dev, 0x00, ®, 1); + + /* get eeprom */ + ret = dm_i2c_probe(bus, 0x54, 0, &dev); + if (ret) + return ret; + + /* read eeprom config section */ + ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info)); + if (ret) + return ret; + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += buf[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + printf("FSA%d EEPROM (board): %s: Invalid Checksum\n", fsa, dev->name); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + /* determine BOM revision from model */ int get_bom_rev(const char *str) { @@ -299,6 +350,8 @@ static int eeprom_info(bool verbose) base_info.mfgdate[0], base_info.mfgdate[1], base_info.mfgdate[2], base_info.mfgdate[3]); } + if (verbose) + fsa_show(); return 0; } @@ -315,6 +368,7 @@ int venice_eeprom_init(int quiet) memset(&som_info, 0, sizeof(som_info)); return 0; } + strlcpy(venice_som_model, som_info.model, sizeof(venice_som_model)); /* read optional baseboard EEPROM */ eeprom_read(BASEBOARD_EEPROM_BUSNO, BASEBOARD_EEPROM_ADDR, 2, &base_info); @@ -322,7 +376,7 @@ int venice_eeprom_init(int quiet) /* create model strings */ if (base_info.model[0]) { sprintf(venice_model, "GW%c%c%c%c-%c%c-", - som_info.model[2], /* family */ + base_info.model[2], /* family */ base_info.model[3], /* baseboard */ base_info.model[4], base_info.model[5], /* subload of baseboard */ som_info.model[4], som_info.model[5]); /* last 2digits of SOM */ @@ -347,9 +401,74 @@ int venice_eeprom_init(int quiet) } venice_serial = som_info.serial; + /* GW8xxx product family naming scheme */ + if (venice_model[2] == '8') { + struct fsa_board_info fsa_info; + int i = 0; + int fsa; + + /* baseboard */ + if (base_info.model[0]) { + rev_pcb = get_pcb_rev(base_info.model); + rev_bom = get_bom_rev(base_info.model); + venice_model[i++] = 'G'; + venice_model[i++] = 'W'; + venice_model[i++] = base_info.model[2]; /* baseboard */ + venice_model[i++] = base_info.model[3]; + venice_model[i++] = base_info.model[4]; /* subload */ + venice_model[i++] = base_info.model[5]; + venice_model[i++] = rev_pcb; + if (rev_bom) + venice_model[i++] = rev_bom; + venice_model[i++] = '-'; + venice_model[i++] = 'S'; + } else { + venice_model[i++] = 'G'; + venice_model[i++] = 'W'; + } + + /* som */ + rev_pcb = get_pcb_rev(som_info.model); + rev_bom = get_bom_rev(som_info.model); + venice_model[i++] = som_info.model[4]; + venice_model[i++] = som_info.model[5]; + venice_model[i++] = rev_pcb; + if (rev_bom) + venice_model[i++] = rev_bom; + + /* fsa */ + for (fsa = 1; fsa < FSA_MAX; fsa++) { + if (!fsa_eeprom_read(venice_model, fsa, &fsa_info)) { + venice_model[i++] = '-'; + venice_model[i++] = 'F'; + venice_model[i++] = '0' + fsa; + venice_model[i++] = fsa_info.model[5]; + venice_model[i++] = fsa_info.model[6]; + venice_model[i++] = fsa_info.model[8]; + if (fsa_info.model[9]) + venice_model[i++] = fsa_info.model[9]; + } + } + + /* append extra model info */ + if (som_info.config[0] >= 32 && som_info.config[0] < 0x7f) { + venice_model[i++] = '-'; + strlcpy(venice_model + i, som_info.config, (sizeof(venice_model) - i) - 1); + i += strlen(som_info.config); + if (i >= sizeof(venice_model)) + i = sizeof(venice_model) - 1; + } + venice_model[i++] = 0; + } + if (!quiet) eeprom_info(false); + if (!strncmp(venice_model, "GW7901-SP486", 12) && + strcmp(venice_model, "GW7901-SP486-C")) { + return 2048; + } + return (16 << som_info.sdram_size); } @@ -363,6 +482,11 @@ const char *eeprom_get_model(void) return venice_model; } +const char *eeprom_get_som_model(void) +{ + return venice_som_model; +} + const char *eeprom_get_baseboard_model(void) { return venice_baseboard_model; diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h index bb7a5fa9ad1..a0f449299aa 100644 --- a/board/gateworks/venice/eeprom.h +++ b/board/gateworks/venice/eeprom.h @@ -20,12 +20,13 @@ struct venice_board_info { u8 sdram_width; /* 0x2D: (8 << n) bit */ u8 res3[2]; /* 0x2E */ char model[16]; /* 0x30: model string */ - u8 res4[14]; /* 0x40 */ + u8 config[14]; /* 0x40: model config */ u8 chksum[2]; /* 0x4E */ }; int venice_eeprom_init(int quiet); const char *eeprom_get_model(void); +const char *eeprom_get_som_model(void); const char *eeprom_get_baseboard_model(void); const char *eeprom_get_dtb_name(int level, char *buf, int len); int eeprom_getmac(int index, uint8_t *enetaddr); diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index d19902f10ec..21997f6fb2a 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -6,18 +6,6 @@ #ifndef __LPDDR4_TIMING_H__ #define __LPDDR4_TIMING_H__ -#ifdef CONFIG_IMX8MM -extern struct dram_timing_info dram_timing_512mb; -extern struct dram_timing_info dram_timing_1gb; -extern struct dram_timing_info dram_timing_2gb; -extern struct dram_timing_info dram_timing_4gb; -#elif CONFIG_IMX8MN -extern struct dram_timing_info dram_timing_1gb_single_die; -extern struct dram_timing_info dram_timing_2gb_single_die; -extern struct dram_timing_info dram_timing_2gb_dual_die; -#elif CONFIG_IMX8MP -extern struct dram_timing_info dram_timing_1gb_single_die; -extern struct dram_timing_info dram_timing_4gb_dual_die; -#endif +extern struct dram_timing_info *spl_dram_init(const char *model, int sizemb); #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c index 3f2c090a94f..956071c5125 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mm.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c @@ -6,6 +6,7 @@ */ #include +#include #include #include @@ -1333,7 +1334,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x203 }, + { 0x3d400020, 0x223 }, { 0x3d400024, 0x3a980 }, { 0x3d400064, 0x5b0062 }, { 0x3d4000d0, 0xc00305ba }, @@ -1385,7 +1386,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1 }, + { 0x3d402020, 0x21 }, { 0x3d402024, 0x7d00 }, { 0x3d402050, 0x20d040 }, { 0x3d402064, 0xc000d }, @@ -1410,7 +1411,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1 }, + { 0x3d403020, 0x21 }, { 0x3d403024, 0x1f40 }, { 0x3d403050, 0x20d040 }, { 0x3d403064, 0x30004 }, @@ -1459,9 +1460,9 @@ static struct dram_cfg_param ddr_ddrphy_cfg_512mb[] = { { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, { 0x120a2, 0x3 }, - { 0x120a3, 0x4 }, + { 0x120a3, 0x2 }, { 0x120a4, 0x5 }, - { 0x120a5, 0x2 }, + { 0x120a5, 0x4 }, { 0x120a6, 0x7 }, { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, @@ -1830,7 +1831,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_512mb[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_512mb = { +static struct dram_timing_info dram_timing_512mb = { .ddrc_cfg = ddr_ddrc_cfg_512mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb), .ddrphy_cfg = ddr_ddrphy_cfg_512mb, @@ -2489,7 +2490,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_1gb = { +static struct dram_timing_info dram_timing_1gb = { .ddrc_cfg = lpddr4_ddrc_cfg_1gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_1gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_1gb, @@ -3005,7 +3006,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_4gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_4gb = { +static struct dram_timing_info dram_timing_4gb = { .ddrc_cfg = lpddr4_ddrc_cfg_4gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_4gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_4gb, @@ -3140,12 +3141,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, { 0x120a2, 0x3 }, @@ -3156,12 +3157,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x5 }, - { 0x130a3, 0x2 }, - { 0x130a4, 0x3 }, - { 0x130a5, 0x4 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -3521,7 +3522,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_2gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_2gb = { +static struct dram_timing_info dram_timing_2gb = { .ddrc_cfg = lpddr4_ddrc_cfg_2gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_2gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_2gb, @@ -3534,3 +3535,63 @@ struct dram_timing_info dram_timing_2gb = { .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz, + struct dram_cfg_param *patch, int patch_sz) +{ + int i, j; + + for (i = 0; i < cfg_sz; i++) + for (j = 0; j < patch_sz; j++) + if (cfg[i].reg == patch[j].reg) + cfg[i].val = patch[j].val; +} + +static struct dram_cfg_param ddr_ddrc_cfg_alt_patch[] = { + { 0x3d400020, 0x203}, + { 0x3d402020, 0x1}, + { 0x3d403020, 0x1} +}; + +static struct dram_cfg_param ddr_ddrphy_cfg_alt_patch[] = { + { 0x120a3, 0x4 }, + { 0x120a5, 0x2 }, +}; + +struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +{ + struct dram_timing_info *dram_timing; + + switch (sizemb) { + case 512: + dram_timing = &dram_timing_512mb; + break; + case 1024: + dram_timing = &dram_timing_1gb; + break; + case 2048: + dram_timing = &dram_timing_2gb; + break; + case 4096: + dram_timing = &dram_timing_4gb; + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_1gb; + } + + /* apply ddrc/phy register changes for alternate dram bus layout */ + if (!strncmp(model, "GW7902", 6) || + !strncmp(model, "GW7903", 6) || + !strncmp(model, "GW7904", 6)) { + apply_cfg_patch(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num, + ddr_ddrc_cfg_alt_patch, + ARRAY_SIZE(ddr_ddrc_cfg_alt_patch)); + + apply_cfg_patch(dram_timing->ddrphy_cfg, dram_timing->ddrphy_cfg_num, + ddr_ddrphy_cfg_alt_patch, + ARRAY_SIZE(ddr_ddrphy_cfg_alt_patch)); + } + + return dram_timing; +} diff --git a/board/gateworks/venice/lpddr4_timing_imx8mn.c b/board/gateworks/venice/lpddr4_timing_imx8mn.c index 9ba2d2571ce..e7d04822c9c 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mn.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mn.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include +#include #include /* @@ -1425,7 +1426,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_1gb_single_die = { +static struct dram_timing_info dram_timing_1gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, @@ -1890,7 +1891,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2gb_single_die = { +static struct dram_timing_info dram_timing_2gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_2gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_2gb_single_die, @@ -2354,7 +2355,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_dual_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2gb_dual_die = { +static struct dram_timing_info dram_timing_2gb_dual_die = { .ddrc_cfg = ddr_ddrc_cfg_2gb_dual_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_dual_die), .ddrphy_cfg = ddr_ddrphy_cfg_2gb_dual_die, @@ -2367,3 +2368,27 @@ struct dram_timing_info dram_timing_2gb_dual_die = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 400, 100, }, }; + +struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +{ + struct dram_timing_info *dram_timing; + + switch (sizemb) { + case 1024: + dram_timing = &dram_timing_1gb_single_die; + break; + case 2048: + if (!strcmp(model, "GW7902-SP466-A") || + !strcmp(model, "GW7902-SP466-B")) { + dram_timing = &dram_timing_2gb_dual_die; + } else { + dram_timing = &dram_timing_2gb_single_die; + } + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_2gb_dual_die; + } + + return dram_timing; +} diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 56c6e2b5cff..36c4cb147e8 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1832,7 +1832,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_1gb_single_die = { +static struct dram_timing_info dram_timing_1gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, @@ -2364,7 +2364,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_4gb_dual_die = { +static struct dram_timing_info dram_timing_4gb_dual_die = { .ddrc_cfg = ddr_ddrc_cfg_4gb_dual_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_4gb_dual_die), .ddrphy_cfg = ddr_ddrphy_cfg_4gb_dual_die, @@ -2377,3 +2377,22 @@ struct dram_timing_info dram_timing_4gb_dual_die = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 4000, 400, 100, }, }; + +struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +{ + struct dram_timing_info *dram_timing; + + switch (sizemb) { + case 1024: + dram_timing = &dram_timing_1gb_single_die; + break; + case 4096: + dram_timing = &dram_timing_4gb_dual_die; + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_4gb_dual_die; + } + + return dram_timing; +} diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index bcdc1a2a468..e813f3e763e 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -32,69 +32,6 @@ #define PCIE_RSTN IMX_GPIO_NR(4, 6) -static void spl_dram_init(int size) -{ - struct dram_timing_info *dram_timing; - - switch (size) { -#ifdef CONFIG_IMX8MM - case 512: - dram_timing = &dram_timing_512mb; - break; - case 1024: - dram_timing = &dram_timing_1gb; - break; - case 2048: - dram_timing = &dram_timing_2gb; - break; - case 4096: - dram_timing = &dram_timing_4gb; - break; - default: - printf("Unknown DDR configuration: %d MiB\n", size); - dram_timing = &dram_timing_1gb; - size = 1024; -#elif CONFIG_IMX8MN - case 1024: - dram_timing = &dram_timing_1gb_single_die; - break; - case 2048: - if (!strcmp(eeprom_get_model(), "GW7902-SP466-A") || - !strcmp(eeprom_get_model(), "GW7902-SP466-B")) { - dram_timing = &dram_timing_2gb_dual_die; - } else { - dram_timing = &dram_timing_2gb_single_die; - } - break; - default: - printf("Unknown DDR configuration: %d MiB\n", size); - dram_timing = &dram_timing_2gb_dual_die; - size = 2048; -#elif CONFIG_IMX8MP - case 1024: - dram_timing = &dram_timing_1gb_single_die; - break; - case 4096: - dram_timing = &dram_timing_4gb_dual_die; - break; - default: - printf("Unknown DDR configuration: %d GiB\n", size); - dram_timing = &dram_timing_4gb_dual_die; - size = 4096; -#endif - } - - printf("DRAM : LPDDR4 "); - if (size > 512) - printf("%d GiB", size / 1024); - else - printf("%d MiB", size); - printf(" %dMT/s %dMHz\n", - dram_timing->fsp_msg[0].drate, - dram_timing->fsp_msg[0].drate / 2); - ddr_init(dram_timing); -} - /* * Model specific PMIC adjustments necessary prior to DRAM init * @@ -118,21 +55,23 @@ static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) return dm_i2c_write(dev, reg, &val, 1); } -static int power_init_board(struct udevice *gsc) +static int power_init_board(const char *model, struct udevice *gsc) { - const char *model = eeprom_get_model(); + const char *som = eeprom_get_som_model(); struct udevice *bus; struct udevice *dev; int ret; - /* Enable GSC voltage supervisor for new board models */ - if ((!strncmp(model, "GW7100", 6) && model[10] > 'D') || - (!strncmp(model, "GW7101", 6) && model[10] > 'D') || - (!strncmp(model, "GW7200", 6) && model[10] > 'E') || - (!strncmp(model, "GW7201", 6) && model[10] > 'E') || - (!strncmp(model, "GW7300", 6) && model[10] > 'E') || - (!strncmp(model, "GW7301", 6) && model[10] > 'E') || - (!strncmp(model, "GW740", 5) && model[7] > 'B')) { + /* Enable GSC voltage supervisor only for newew board models */ + if ((!strncmp(model, "GW7100", 6) && model[10] < 'E') || + (!strncmp(model, "GW7101", 6) && model[10] < 'E') || + (!strncmp(model, "GW7200", 6) && model[10] < 'F') || + (!strncmp(model, "GW7201", 6) && model[10] < 'F') || + (!strncmp(model, "GW7300", 6) && model[10] < 'F') || + (!strncmp(model, "GW7301", 6) && model[10] < 'F') || + (!strncmp(model, "GW740", 5) && model[7] < 'C')) { + printf("GSC : voltage supervisor disabled\n"); + } else { u8 ver; if (!dm_i2c_read(gsc, 14, &ver, 1) && ver > 62) { @@ -141,10 +80,7 @@ static int power_init_board(struct udevice *gsc) } } - if ((!strncmp(model, "GW71", 4)) || - (!strncmp(model, "GW72", 4)) || - (!strncmp(model, "GW73", 4)) || - (!strncmp(model, "GW75", 4))) { + if (!strncmp(som, "GW70", 4)) { ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); @@ -251,9 +187,11 @@ static int power_init_board(struct udevice *gsc) void board_init_f(ulong dummy) { + struct dram_timing_info *dram_timing; struct udevice *bus, *dev; + const char *model; + int dram_szmb; int i, ret; - int dram_sz; arch_cpu_init(); @@ -311,13 +249,23 @@ void board_init_f(ulong dummy) break; mdelay(1); } - dram_sz = venice_eeprom_init(0); + dram_szmb = venice_eeprom_init(0); + model = eeprom_get_model(); /* PMIC */ - power_init_board(dev); + power_init_board(model, dev); /* DDR initialization */ - spl_dram_init(dram_sz); + printf("DRAM : LPDDR4 "); + if (dram_szmb > 512) + printf("%d GiB", dram_szmb / 1024); + else + printf("%d MiB", dram_szmb); + dram_timing = spl_dram_init(model, dram_szmb); + printf(" %dMT/s %dMHz\n", + dram_timing->fsp_msg[0].drate, + dram_timing->fsp_msg[0].drate / 2); + ddr_init(dram_timing); board_init_r(NULL, 0); } diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 98b33624f04..6a24f618ae2 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -3,6 +3,7 @@ * Copyright 2021 Gateworks Corporation */ +#include #include #include #include @@ -14,6 +15,7 @@ #include #include "eeprom.h" +#include "../fsa.h" int board_phys_sdram_size(phys_size_t *size) { @@ -75,6 +77,9 @@ int board_init(void) { venice_eeprom_init(1); + /* detect and configure FSA adapters */ + fsa_init(); + return 0; } @@ -221,6 +226,9 @@ int ft_board_setup(void *fdt, struct bd_info *bd) /* set board model dt prop */ fdt_setprop_string(fdt, 0, "board", eeprom_get_model()); + /* fixups for FSA adapters */ + fsa_ft_fixup(fdt); + if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); path = fdt_get_alias(fdt, "ethernet1"); diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index c1aacd1458b..ddb7304d493 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c index 4d3049689d3..d8ffdd25b38 100644 --- a/board/google/chameleonv3/board.c +++ b/board/google/chameleonv3/board.c @@ -2,6 +2,8 @@ /* * Copyright 2022 Google LLC */ + +#include #include #include #include "mercury_aa1.h" diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index db96534857c..b4053fa097d 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -11,13 +11,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index c2a44b4aa2d..492d1dc1d8c 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -84,7 +84,7 @@ static int mmc_get_env_devno(void) /* If not boot from sd/mmc, use default value */ if (bootsel != 1) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; /* BOOT_CFG2[3] and BOOT_CFG2[4] */ dev_no = (soc_sbmr & 0x00001800) >> 11; diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 4a72ab5ceca..0ffa964178f 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index a35a7cd3b1f..c21b083b62a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 783853d5c6f..0f43ebfec4d 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -6,6 +6,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index b1758858705..33e5337bcbc 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -204,7 +204,7 @@ static struct mx6_ddr3_cfg mem_512M_ddr = { static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = { .p0_mpwldectrl0 = 0x00000000, - .p0_mpdgctrl0 = 0X01440144, + .p0_mpdgctrl0 = 0x01440144, .p0_mprddlctl = 0x40405454, .p0_mpwrdlctl = 0x40404E4C, }; diff --git a/board/liebherr/btt/Kconfig b/board/liebherr/btt/Kconfig new file mode 100644 index 00000000000..ff35dd04532 --- /dev/null +++ b/board/liebherr/btt/Kconfig @@ -0,0 +1,24 @@ +if TARGET_BTT + +config SYS_BOARD + default "btt" + +config SYS_VENDOR + default "liebherr" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "btt" + +config ENV_SIZE + default 0x2000 + +config ENV_SECT_SIZE + default 0x10000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x80000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/liebherr/btt/MAINTAINERS b/board/liebherr/btt/MAINTAINERS new file mode 100644 index 00000000000..b4afed5aaeb --- /dev/null +++ b/board/liebherr/btt/MAINTAINERS @@ -0,0 +1,6 @@ +BTT BOARD +M: Lukasz Majewski +S: Maintained +F: board/liebherr/btt/ +F: include/configs/btt.h +F: configs/imx28_btt3_defconfig diff --git a/board/liebherr/btt/Makefile b/board/liebherr/btt/Makefile new file mode 100644 index 00000000000..a8ab657a9e0 --- /dev/null +++ b/board/liebherr/btt/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2025 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := btt.o +obj-$(CONFIG_XPL_BUILD) += spl_btt.o diff --git a/board/liebherr/btt/boot_img_scr.h b/board/liebherr/btt/boot_img_scr.h new file mode 100644 index 00000000000..baa3072b49c --- /dev/null +++ b/board/liebherr/btt/boot_img_scr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Struct for boot image source description for placing in last + * two SPI NOR flash sectors on legcom. + */ + +struct boot_img_src { + u8 magic; /* Must be 'B' = 0x42 */ + u8 flags; /* flags to specify mmcblk[0|1] boot[0|1] */ + u8 crc8; /* CRC-8 over above two bytes */ +} __packed; + +/* + * Bit definition in boot_img_src.flags: + * Bit 0: mmcblk device 0 or 1 (1 - if this bit set) + * Bit 1: mmcblk boot partition 0 or 1. + * for eMMC: boot0 if this bit is cleared, boot1 - if set + * for SD-card the boot partition value will always be 0 + * (independent of the value of this bit) + * + */ +#define BOOT_SRC_MMC1 BIT(0) +#define BOOT_SRC_PART1 BIT(1) + +/* Offset of the first boot image source descriptor in SPI NOR */ +#define SPI_FLASH_BOOT_SRC_OFFS 0xFE0000 +#define SPI_FLASH_SECTOR_SIZE 0x10000 diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c new file mode 100644 index 00000000000..e05e333ac7e --- /dev/null +++ b/board/liebherr/btt/btt.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * BTT[3C] iMX28 board + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "boot_img_scr.h" + +#include +#include + +#ifdef CONFIG_XPL_BUILD +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ + +static void init_clocks(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + /* SSP3 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK3, 96000, 0); +} + +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +void board_init_f(ulong arg) +{ + init_clocks(); + spl_early_init(); + preloader_console_init(); +} + +static struct boot_img_src img_src[2]; +static int spi_load_boot_info(void) +{ + struct spi_flash *flash; + int err; + + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!flash) { + printf("%s: SPI probe err\n", __func__); + return -ENODEV; + } + + /* + * Load both boot info structs from SPI flash + */ + err = spi_flash_read(flash, SPI_FLASH_BOOT_SRC_OFFS, + sizeof(img_src[0]), + (void *)&img_src[0]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + err = spi_flash_read(flash, + SPI_FLASH_BOOT_SRC_OFFS + SPI_FLASH_SECTOR_SIZE, + sizeof(img_src[0]), + (void *)&img_src[1]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + debug("%s: BI0 0x%x 0x%x 0x%x\n", __func__, + img_src[0].magic, img_src[0].flags, img_src[0].crc8); + + debug("%s: BI1 0x%x 0x%x 0x%x\n", __func__, + img_src[1].magic, img_src[1].flags, img_src[1].crc8); + + return 0; +} + +#define BTT_MONITORING_DEVICE_TIMEOUT 100 +static int rescue_val; + +void spl_board_init(void) +{ + struct gpio_desc phy_rst, boot, rescue, wifi_en, bt_en; + int ret, i; + + /* + * On the new HW version of BTTC/3 (with LAN8720ai PHY) the !RST pin + * (15) is pulled LOW by external resistor. As a result it needs to be + * set HIGH as soon as possible to allow correct generation of RESET + * pulse. + * + * In the old BTTC (with TLK105 PHY) the RC circuit was used instead + * to set the RESET pin to HIGH after 100us, so there was no need to + * set it explicitly. + */ + ret = dm_gpio_lookup_name("GPIO4_12", &phy_rst); + if (ret) + printf("Cannot get GPIO4_12\n"); + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) + printf("Cannot request GPIO4_12\n"); + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls WL_EN (wifi) to LOW. On the BTT3 + * it is directly connected to Jody module without any externa pull up + * down register. + */ + ret = dm_gpio_lookup_name("GPIO0_27", &wifi_en); + if (ret) + printf("Cannot get GPIO0_27\n"); + + ret = dm_gpio_request(&wifi_en, "wifi-en"); + if (ret) + printf("Cannot request GPIO0_27\n"); + + dm_gpio_set_dir_flags(&wifi_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls BT_EN (Bluetooth) to LOW. On the + * BTT3 it is connected to Jody module via RC circuit (after some R*C + * time this pin is set to HIGH). However, the manual recommends setting + * it high from LOW state. + */ + ret = dm_gpio_lookup_name("GPIO3_27", &bt_en); + if (ret) + printf("Cannot get GPIO3_27\n"); + + ret = dm_gpio_request(&bt_en, "bt-en"); + if (ret) + printf("Cannot request GPIO3_27\n"); + + dm_gpio_set_dir_flags(&bt_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* 'boot' and 'rescue' pins */ + ret = dm_gpio_lookup_name("GPIO4_9", &boot); + if (ret) + printf("Cannot get GPIO4_9\n"); + + ret = dm_gpio_request(&boot, "boot"); + if (ret) + printf("Cannot request GPIO4_9\n"); + + dm_gpio_set_dir_flags(&boot, GPIOD_IS_IN); + + ret = dm_gpio_lookup_name("GPIO4_11", &rescue); + if (ret) + printf("Cannot get GPIO4_11\n"); + + ret = dm_gpio_request(&rescue, "rescue"); + if (ret) + printf("Cannot request GPIO4_11\n"); + + dm_gpio_set_dir_flags(&rescue, GPIOD_IS_IN); + + /* Wait for ready signal from system "monitoring" device */ + for (i = 0; i < BTT_MONITORING_DEVICE_TIMEOUT; i++) { + if (dm_gpio_get_value(&boot)) + break; + mdelay(10); + } + + rescue_val = dm_gpio_get_value(&rescue); +} + +int spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int i, src_idx = -1, ret; + + ret = spi_load_boot_info(); + if (ret) { + printf("%s: Cannot read BTT boot info! [%d]\n", __func__, ret); + /* To avoid bricking board - by default boot from boot0 eMMC */ + return 1; + } + + for (i = 0; i < 2; i++) { + if (img_src[i].magic == 'B' && + img_src[i].crc8 == crc8(0, &img_src[i].magic, 2)) { + src_idx = i; + break; + } + } + + debug("%s: src idx: %d\n", __func__, src_idx); + + if (src_idx < 0) + /* + * Always use eMMC (mmcblkX) boot0 if no + * valid image source description found + */ + return 1; + + if (img_src[src_idx].flags & BOOT_SRC_PART1) + return 2; + + return 1; +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_SPI; + spl_boot_list[2] = BOOT_DEVICE_UART; +} + +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + debug("%s: rescue: %d\n", __func__, rescue_val); + return rescue_val; +} +#else + +/* + * Providing proper board name - i.e. 'bttc' vs 'btt3' + * The distinction is made on the size of DRAM memory - i.e. + * bttc has only 128 MiB, whereas btt3 has 256 MiB. + */ +#define STR_BTTC "bttc" +#define STR_BTT3 "btt3" + +static const char *get_board_name(void) +{ + if (gd->bd->bi_dram[0].size == SZ_128M) + return STR_BTTC; + + return STR_BTT3; +} + +/* + * Reading the HW ID number for BTT3 device + * + * GPIOs from Port 4: + * E0: GPIO4_10 + * E1: GPIO4_5 + * E2: GPIO4_14 + * E3: GPIO4_15 + * are used on BTT3 to store HW revision information. + * + * From rev 1+ the REV GPIOs are properly connected on the PCB, so PULL UPs + * shall be disabled (as they are by default on pins' SPL configuration) + *. + * Rev 0: - read all '1' (first production version without HW rev set) + * Rev 1: - read 0x1 (E0 set) + * Rev 2: - read 0x2 (E1 set) + * + */ +#define BTT3_HW_ID_GPIO_PORT (MXS_PINCTRL_BASE + (0x0900 + ((4) * 0x10))) +#define BTT3_HW_ID_E0 BIT(10) +#define BTT3_HW_ID_E1 BIT(5) +#define BTT3_HW_ID_E2 BIT(14) +#define BTT3_HW_ID_E3 BIT(15) + +static u8 get_som_rev(void) +{ + struct mxs_register_32 *reg = + (struct mxs_register_32 *)BTT3_HW_ID_GPIO_PORT; + u32 tmp = ~readl(®->reg); + u8 id = 0; + + if (tmp & BTT3_HW_ID_E0) + id += 1; + + if (tmp & BTT3_HW_ID_E1) + id += 2; + + if (tmp & BTT3_HW_ID_E2) + id += 4; + + if (tmp & BTT3_HW_ID_E3) + id += 8; + + /* + * Special case for first production BTT3 version, without HW + * revision support (so it reads 0x0s as pullups are disabled + * and hence 0xF is set for ID) + */ + if (id == 0xF) + id = 0; + + return id; +} + +int board_early_init_f(void) +{ + init_clocks(); + + return 0; +} + +int board_init(void) +{ + struct gpio_desc phy_rst; + int ret; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + cpu_eth_init(NULL); + + /* PHY INT#/PWDN# */ + ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst); + if (ret) { + printf("Cannot get GPIO4_13\n"); + return ret; + } + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) { + printf("Cannot request GPIO4_13\n"); + return ret; + } + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN); + udelay(1000); + + return 0; +} + +#if defined(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + int ret = env_set_ulong("board_som_rev", get_som_rev()); + + if (ret) + printf("Cannot set BTT's SoM revision env variable!\n"); + + ret = env_set("arch", get_board_name()); + if (ret) + printf("Cannot set SoM 'arch' env variable!\n"); + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO) +int checkboard(void) +{ + printf("Board: LWE BTT SoM HW rev %d\n", get_som_rev()); + + return 0; +} +#endif + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#if defined(CONFIG_OF_BOARD) +int board_fdt_blob_setup(void **fdtp) +{ + /* + * The only purpose of this function is the specific BTT's DTB + * setup in u-boot proper. To be more specific - the SPL + * cannot support DTB selection due to size constraints + * (SPL < 50 KiB). + * + * Hence, the DTB selection is done in u-boot, which due to + * board's partition sizes (and backward compatibility) has also + * size constrain (~448 KiB). + * + * To support multiple DTBs appended, the compression has been used + * for them. Unfortunately, the initf_malloc() is called + * after the DTB needs to be selected. To fix this problem for this + * particular setup (i.e. BTT board) the initf_malloc() is called here. + */ + initf_malloc(); + + return -EEXIST; +} +#endif + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + u8 rev_id = get_som_rev(); + char board[12]; + + sprintf(board, "imx28-btt3-%d", rev_id); + + if (!strncmp(name, board, sizeof(board))) + return 0; + + return -EINVAL; +} +#endif + +/* + * NOTE: + * + * IMX28 clock "stub" DM driver! + * + * Only used for SPL stage, which is NOT using DM; serial and + * eMMC configuration. + * + * It is required for SPL_OF_PLATDATA proper code generation as, + * this device has hard constrain on the size of the SPL binary + * (u-boot.sb). + */ +static const struct udevice_id imx28_clk_ids[] = { + { .compatible = "fsl,imx28-clkctrl", }, + { } +}; + +U_BOOT_DRIVER(fsl_imx28_clkctrl) = { + .name = "fsl_imx28_clkctrl", + .id = UCLASS_CLK, + .of_match = imx28_clk_ids, +}; +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/liebherr/btt/btt.env b/board/liebherr/btt/btt.env new file mode 100644 index 00000000000..aaf0b8415d1 --- /dev/null +++ b/board/liebherr/btt/btt.env @@ -0,0 +1,139 @@ +bootmode=update +bootpri=mmc_mmc +bootsec=sf_swu +consdev=ttyAMA0 +baudrate=115200 +dtbfile=imx28-btt3-1.dtb +rootdev=/dev/mmcblk0p2 +netdev=eth0 +swufile=swupdate-image-btt3-upd.itb +sf_kernel_offset=0xA0000 +sf_swu_size=0xF40000 +ethact=FEC +arch=btt3 +lwe_env= + if dhcp ${loadaddr} ${hostname}/${lwe_uenv} ; then + source ${loadaddr}; + fi +lwe_uenv=env_uboot_btt3.bin +do_update_mmc= + if mmc rescan ; then + mmc dev 0 ${update_mmc_part} ; + if dhcp ${hostname}/${update_filename} ; then + setexpr fw_sz ${filesize} / 0x200 ; + setexpr fw_sz ${fw_sz} + 1 ; + mmc write ${loadaddr} ${update_offset} ${fw_sz} ; + fi ; + fi +do_update_sf= + if sf probe ; then + if dhcp ${hostname}/${update_filename} ; then + sf erase ${update_offset} +${filesize} ; + sf write ${loadaddr} ${update_offset} ${filesize} ; + fi ; + fi +factory_reset= + if sf probe ; then + run update_swu ; + setenv bootmode update ; + saveenv ; + fi +update_spl_filename=u-boot.sb +update_spl= + setenv update_filename ${update_spl_filename} ; + setenv update_offset 0 ; + run do_update_sf +update_uboot_filename=u-boot.img +update_uboot= + setenv update_filename ${update_uboot_filename} ; + setenv update_offset 0x10000 ; + run do_update_sf ; + setenv update_mmc_part 1 ; + setenv update_offset 0 ; + run do_update_mmc ; + setenv update_mmc_part 2 ; + run do_update_mmc +update_kernel_filename=uImage +update_kernel= + setenv update_mmc_part 1 ; + setenv update_filename ${update_kernel_filename} ; + setenv update_offset 0x800 ; + run do_update_mmc ; + setenv update_filename ${dtbfile} ; + setenv update_offset 0x400 ; + run do_update_mmc +update_swu= + setenv update_filename ${swufile} ; + setenv update_offset ${sf_kernel_offset} ; + run do_update_sf +addcons= + setenv bootargs ${bootargs} + console=${consdev},${baudrate} +addip= + setenv bootargs ${bootargs} + ip=${ipaddr}:${serverip}:${gatewayip}: + ${netmask}:${hostname}:${netdev}:off +addmisc= + setenv bootargs ${bootargs} ${miscargs} +addargs=run addcons addmisc +mmcload= + mmc rescan ; + mmc dev 0 1 ; + mmc read ${loadaddr} 0x800 0x2000 ; + mmc read ${dtbaddr} 0x400 0x80 +netload= + dhcp ${loadaddr} ${hostname}/${bootfile} ; + tftp ${dtbaddr} ${hostname}/${dtbfile} +usbload= + usb start ; + load usb 0:1 ${loadaddr} ${bootfile} +miscargs=panic=1 +mmcargs=setenv bootargs root=${rootdev} rw rootwait +nfsargs= + setenv bootargs root=/dev/nfs rw + nfsroot=${serverip}:${rootpath},v3,tcp +mmc_mmc= + if run mmcload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +mmc_nfs= + if run mmcload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_mmc= + if run sfload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_swu= + if sf probe ; then + sf read ${loadaddr} ${sf_kernel_offset} ${sf_swu_size} ; + setenv bootargs root=/dev/ram0 rw ; + run addargs ; + bootm ${loadaddr}#conf-imx28-${arch}-${board_som_rev}.dtb ; + fi +net_mmc= + if run netload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +net_nfs= + if run netload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +prebootcmd= + if test ${envsaved} != y ; then ; + setenv envsaved y ; + saveenv ; + fi ; + if test ${bootmode} = normal ; then + setenv bootdelay 0 ; + setenv bootpri mmc_mmc ; + elif test ${bootmode} = devel ; then + setenv bootdelay 3 ; + setenv bootpri net_mmc ; + else + if test ${bootmode} != update ; then + echo Warning: unknown bootmode ${bootmode} ; + fi ; + setenv bootdelay 1 ; + setenv bootpri sf_swu ; + fi diff --git a/board/liebherr/btt/spl_btt.c b/board/liebherr/btt/spl_btt.c new file mode 100644 index 00000000000..da17e186b06 --- /dev/null +++ b/board/liebherr/btt/spl_btt.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DENX M28 Boot setup + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include +#include +#include +#include +#include + +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_BOOT (MXS_PAD_3V3) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +/* HW_PINCTRL_EMI_DS_CTRL */ +#define EMI_DS_CTRL_CLR 0x3FFF +#define EMI_DS_CTRL_SLICE0_SHIFT 0 +#define EMI_DS_CTRL_SLICE1_SHIFT 2 +#define EMI_DS_CTRL_SLICE2_SHIFT 4 +#define EMI_DS_CTRL_SLICE3_SHIFT 6 +#define EMI_DS_CTRL_DUALPAD_SHIFT 8 +#define EMI_DS_CTRL_CONTROL_SHIFT 10 +#define EMI_DS_CTRL_ADDRESS_SHIFT 12 +#define EMI_DS_CTRL_MA_20 0x10 + +/* + * The BTT devide can be boot in several ways; U-Boot's 'falcon' mode, + * normal boot (through U-Boot proper) and also via recovery system. + * + * To fix some HW issues on the device, as well as providing all the + * above boot method's the same "start" state when kernel starts it + * has been decided to configure PINMUXes for all relevant IP blocks + * (and GPIOs during early SPI state). + * + * It also shall be mentioned, that during early SPL stage, the BTT + * device needs to cooperate with uC based co-processor - this + * requires correct pins configuration. + */ +static const iomux_cfg_t iomux_setup[] = { + /* AUART0 IRDA */ + MX28_PAD_AUART0_RX__AUART0_RX, + MX28_PAD_AUART0_TX__AUART0_TX, + + /* AUART 4 RS422 */ + MX28_PAD_AUART0_CTS__AUART4_RX, + MX28_PAD_AUART0_RTS__AUART4_TX, + + /* USB0 */ + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT, + MX28_PAD_AUART1_RTS__USB0_ID, + MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */ + + /* USB1 */ + MX28_PAD_PWM2__USB1_OVERCURRENT, + + /* eMMC */ + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */ + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* DIG Keys */ + MX28_PAD_GPMI_D00__GPIO_0_0, + MX28_PAD_GPMI_D01__GPIO_0_1, + MX28_PAD_GPMI_D02__GPIO_0_2, + MX28_PAD_GPMI_D03__GPIO_0_3, + MX28_PAD_GPMI_D04__GPIO_0_4, + MX28_PAD_GPMI_D05__GPIO_0_5, + MX28_PAD_GPMI_D06__GPIO_0_6, + MX28_PAD_GPMI_D07__GPIO_0_7, + + /* ADR_0-2 */ + MX28_PAD_GPMI_CE1N__GPIO_0_17, + MX28_PAD_GPMI_CE2N__GPIO_0_18, + MX28_PAD_GPMI_CE3N__GPIO_0_19, + + /* Read Keys */ + MX28_PAD_GPMI_RDY0__GPIO_0_20, + + /* LATCH_EN */ + MX28_PAD_GPMI_RDY1__GPIO_0_21, + + /* Power off */ + MX28_PAD_GPMI_RDN__GPIO_0_24, + + /* WIFI EN */ + MX28_PAD_GPMI_CLE__GPIO_0_27, + + /* I2C1 Touch */ + MX28_PAD_AUART2_CTS__GPIO_3_10, + MX28_PAD_AUART2_RTS__GPIO_3_11, + MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */ + MX28_PAD_GPMI_RDY3__GPIO_0_23, /* Touch INT */ + + /* TIVA */ + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT, + MX28_PAD_SSP2_MISO__SSP2_D0, + MX28_PAD_SSP2_MOSI__SSP2_CMD, + MX28_PAD_SSP2_SCK__SSP2_SCK, + MX28_PAD_SSP2_SS0__SSP2_D3, + MX28_PAD_SSP2_SS1__GPIO_2_20, + MX28_PAD_SSP2_SS2__GPIO_2_21, + + /* SPI3 NOR-Flash */ + MX28_PAD_AUART1_TX__SSP3_CARD_DETECT, + MX28_PAD_AUART2_RX__SSP3_D1, + MX28_PAD_AUART2_TX__SSP3_D2, + MX28_PAD_SSP3_MISO__SSP3_D0, + MX28_PAD_SSP3_MOSI__SSP3_CMD, + MX28_PAD_SSP3_SCK__SSP3_SCK, + MX28_PAD_SSP3_SS0__SSP3_D3, + + /* NOR-Flash CMD */ + MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */ + MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */ + + /* I2C0 Codec */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* I2S Codec */ + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK, + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK, + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK, + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0, + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0, + + /* BT_EN */ + MX28_PAD_SPDIF__GPIO_3_27, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* Uart3 Bluetooth-Interface */ + MX28_PAD_AUART3_CTS__AUART3_CTS, + MX28_PAD_AUART3_RTS__AUART3_RTS, + MX28_PAD_AUART3_RX__AUART3_RX, + MX28_PAD_AUART3_TX__AUART3_TX, + + /* framebuffer */ + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + + /* DUART RS232 */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* Backlight */ + MX28_PAD_PWM3__PWM_3, + + /* FEC Ethernet */ + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */ + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */ + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__GPIO_4_12, /* PHY reset */ + + /* boot/rescue pins */ + MX28_PAD_ENET0_RXD2__GPIO_4_9, + MX28_PAD_ENET0_TXD2__GPIO_4_11, + + /* HW revision setup pins - by default pullup DISABLED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, + MX28_PAD_ENET0_COL__GPIO_4_14, + MX28_PAD_ENET0_CRS__GPIO_4_15, +}; + +u32 mxs_dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x07080403, 0x07005303, 0x0b0000c8, + 0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322, + 0x02040203, 0x00c8002b, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000102, + 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + 0x07400300, 0x07400300, 0x07400300, 0x00000005, + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000001, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00030404, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040101, 0x21002103, 0x00061200, + 0x06120612, 0x00000642, 0x00000000, 0x00000004, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, + 0x00000000, 0xffffffff +}; + +#ifndef CONFIG_SPL_FRAMEWORK +void board_init_ll(const u32 arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#else +void lowlevel_init(void) +{ + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set EMI drive strength - the HW_PINCTRL_EMI_DS_CTRL */ + writel(EMI_DS_CTRL_CLR, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr); + writel(EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE0_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE1_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE2_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE3_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_DUALPAD_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_CONTROL_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_ADDRESS_SHIFT, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#endif diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c index b1f6881275d..e612d9e9ce0 100644 --- a/board/liebherr/mccmon6/spl.c +++ b/board/liebherr/mccmon6/spl.c @@ -5,6 +5,7 @@ * Richard Hu */ +#include #include #include #include diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 1d4f165fd13..9630e7f576b 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -13,6 +13,7 @@ * */ +#include #include #include #include diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 4d7d843dfa3..6b6984eae3f 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -9,6 +9,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,68 @@ static void read_device_serial_number(u8 *response, u8 response_size) response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx); } +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + const void *fdt; + int list_len; + + /* + * If there's not a HSS provided dtb, there's no point re-selecting + * since we'd just end up re-selecting the same dtb again. + */ + if (!gd->arch.firmware_fdt_addr) + return -EINVAL; + + fdt = (void *)gd->arch.firmware_fdt_addr; + + list_len = fdt_stringlist_count(fdt, 0, "compatible"); + if (list_len < 1) + return -EINVAL; + + for (int i = 0; i < list_len; i++) { + int len, match; + const char *compat; + char *devendored; + + compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); + if (!compat) + return -EINVAL; + + strtok((char *)compat, ","); + + devendored = strtok(NULL, ","); + if (!devendored) + return -EINVAL; + + match = strcmp(devendored, name); + if (!match) + return 0; + } + + return -EINVAL; +} +#endif + +int board_fdt_blob_setup(void **fdtp) +{ + fdtp = (void *)_end; + + /* + * The devicetree provided by the previous stage is very minimal due to + * severe space constraints. The firmware performs no fixups etc. + * U-Boot, if providing a devicetree, almost certainly has a better + * more complete one than the firmware so that provided by the firmware + * is ignored for OF_SEPARATE. + */ + if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (gd->arch.firmware_fdt_addr) + fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; + } + + return 0; +} + int board_init(void) { /* For now nothing to do here. */ diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 828973a8e28..7f34d71d530 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -94,7 +94,7 @@ int mmc_get_env_dev(void) return 1; }; - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } #endif @@ -121,24 +121,37 @@ enum env_location env_get_location(enum env_operation op, int prio) } #if IS_ENABLED(CONFIG_BOARD_LATE_INIT) -int board_late_init(void) +/** + * Ensure the boot order favors the device we just booted from. + * If boot_targets is still at its default value, move the current + * boot device to the front of the list. Otherwise, leave any customized + * order untouched. + */ +static void boot_targets_setup(void) { u32 boot_device = get_boot_device(); + const char *boot_targets = NULL; + char boot_targets_default[100]; + int ret; switch (boot_device) { case BOOT_DEVICE_MMC1: env_set_ulong("mmcdev", 0); env_set("boot", "mmc"); + boot_targets = "mmc0 mmc1 spi_flash dhcp"; break; case BOOT_DEVICE_MMC2: env_set_ulong("mmcdev", 1); env_set("boot", "mmc"); + boot_targets = "mmc1 mmc0 spi_flash dhcp"; break; case BOOT_DEVICE_SPI: env_set("boot", "spi"); + boot_targets = "spi_flash mmc0 mmc1 dhcp"; break; case BOOT_DEVICE_ETHERNET: env_set("boot", "net"); + boot_targets = "dhcp mmc0 mmc1 spi_flash"; break; case BOOT_DEVICE_UART: env_set("boot", "uart"); @@ -148,26 +161,49 @@ int board_late_init(void) break; }; - if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { - struct phytec_api3_element *block_element; - struct phytec_eeprom_data data; - int ret; + if (!boot_targets) + return; - ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); - if (ret || !data.valid) - return 0; + ret = env_get_default_into("boot_targets", boot_targets_default, sizeof(boot_targets_default)); + if (ret < 0) + boot_targets_default[0] = '\0'; - PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { - switch (block_element->block_type) { - case PHYTEC_API3_BLOCK_MAC: - phytec_blocks_add_mac_to_env(block_element); - break; - default: - debug("%s: Unknown block type %i\n", __func__, - block_element->block_type); - } + if (strcmp(boot_targets_default, env_get("boot_targets"))) { + debug("boot_targets not default, don't change it\n"); + return; + } + + env_set("boot_targets", boot_targets); +} + +static void setup_mac_from_eeprom(void) +{ + struct phytec_api3_element *block_element; + struct phytec_eeprom_data data; + int ret; + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return; + + PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { + switch (block_element->block_type) { + case PHYTEC_API3_BLOCK_MAC: + phytec_blocks_add_mac_to_env(block_element); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + block_element->block_type); } } +} + +int board_late_init(void) +{ + boot_targets_setup(); + + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) + setup_mac_from_eeprom(); #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) configure_capsule_updates(); diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c index 5f3c27ef0c2..b44ff85972f 100644 --- a/board/phytec/common/phytec_som_detection_blocks.c +++ b/board/phytec/common/phytec_som_detection_blocks.c @@ -4,6 +4,7 @@ * Author: Daniel Schultz */ +#include #include #include #include diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 40787b0cbcb..797904013dc 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -24,3 +24,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 5c48e856685..797904013dc 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -10,6 +10,7 @@ fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 +fit_addr_r=0x90000000 fdtfile=CONFIG_DEFAULT_FDT_FILE mmcdev=1 @@ -23,3 +24,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index d69dfe75674..36ab16e2f7a 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -9,6 +9,7 @@ fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 +fit_addr_r=0x90000000 fdtfile=CONFIG_DEFAULT_FDT_FILE mmcdev=1 @@ -22,3 +23,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index a7d14e774a0..402d967ab7d 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -34,7 +34,7 @@ mmcboot= echo WARN: Cannot load the DT; fi; fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 netargs= diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index 2c12fc65432..69690aa92e4 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -51,7 +51,7 @@ mmcboot= else echo WARN: Cannot load the DT; fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 netargs= diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env index 3b2f30118e7..7b0a90e6447 100644 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ b/board/phytec/phycore_imx93/phycore_imx93.env @@ -23,7 +23,7 @@ bootenv_addr_r=0x90500000 fdtfile=CONFIG_DEFAULT_FDT_FILE ip_dyn=yes prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 mmcautodetect=yes diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 8ca8792fa42..5178ee6929d 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/board/qualcomm/MAINTAINERS b/board/qualcomm/MAINTAINERS new file mode 100644 index 00000000000..3767a2a7949 --- /dev/null +++ b/board/qualcomm/MAINTAINERS @@ -0,0 +1,24 @@ +# This MAINTAINERS file is for folks with an interest in a particular platform +# or board under ARM SNAPDRAGON + +QUALCOMM DRAGONWING QCS615 +M: Aswin Murugan +S: Maintained +N: qcs615 + +# RB3 Gen 2 and similar boards +QUALCOMM DRAGONWING QCS6490 +M: Casey Connolly +S: Maintained +N: qcs6490 +N: sc7280 + +QUALCOMM DRAGONWING QCS8300 +M: Balaji Selvanathan +S: Maintained +N: qcs8300 + +QUALCOMM DRAGONWING QCS9100 +M: Varadarajan Narayanan +S: Maintained +N: qcs9100 diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config index 913c91757c1..d24094eefdd 100644 --- a/board/qualcomm/qcom-phone.config +++ b/board/qualcomm/qcom-phone.config @@ -1,5 +1,5 @@ # Settings for phones -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/qcom-phone.env" +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/qcom-phone.env" # Hang on panic so the error message can be read CONFIG_PANIC_HANG=y # We use pause in various places to allow text to be read diff --git a/board/renesas/common/rcar64-spl.c b/board/renesas/common/rcar64-spl.c index 76f2bde924e..d8f05d2ffbe 100644 --- a/board/renesas/common/rcar64-spl.c +++ b/board/renesas/common/rcar64-spl.c @@ -6,7 +6,7 @@ #include #include -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index fbee2c39771..602216854ba 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index d97945e58fc..43f4edc39e9 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -101,7 +101,6 @@ enum env_location env_get_location(enum env_operation op, int prio) int dram_init(void) { - gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c index daf0bb930ec..939ff81797d 100644 --- a/board/siemens/common/board_am335x.c +++ b/board/siemens/common/board_am335x.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index d827f728a08..161210c60a9 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c index a8b111477ef..5d2f40f241c 100644 --- a/board/socionext/developerbox/fwu_plat.c +++ b/board/socionext/developerbox/fwu_plat.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/board/st/stm32h747-disco/Kconfig b/board/st/stm32h747-disco/Kconfig new file mode 100644 index 00000000000..a7b2c09a327 --- /dev/null +++ b/board/st/stm32h747-disco/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STM32H747_DISCO + +config SYS_BOARD + default "stm32h747-disco" + +config SYS_VENDOR + default "st" + +config SYS_SOC + default "stm32h7" + +config SYS_CONFIG_NAME + default "stm32h747-disco" + +endif diff --git a/board/st/stm32h747-disco/MAINTAINERS b/board/st/stm32h747-disco/MAINTAINERS new file mode 100644 index 00000000000..d48649f773f --- /dev/null +++ b/board/st/stm32h747-disco/MAINTAINERS @@ -0,0 +1,7 @@ +STM32H747 DISCOVERY BOARD +M: Dario Binacchi +S: Maintained +F: board/st/stm32h747-disco +F: include/configs/stm32h747-disco.h +F: configs/stm32h747-disco_defconfig +F: arch/arm/dts/stm32h747* diff --git a/board/st/stm32h747-disco/Makefile b/board/st/stm32h747-disco/Makefile new file mode 100644 index 00000000000..e11f052cc88 --- /dev/null +++ b/board/st/stm32h747-disco/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2025 Dario Binacchi +# + +obj-y := stm32h747-disco.o diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c new file mode 100644 index 00000000000..be0884bdeb4 --- /dev/null +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * stm32h747i-disco support + * + * Copyright (C) 2025 Dario Binacchi + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + if (fdtdec_setup_mem_size_base() != 0) + ret = -EINVAL; + + return ret; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int board_init(void) +{ + return 0; +} diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 15fb9e4b062..ab7af69d472 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -828,7 +828,7 @@ const char *env_ext4_get_dev_part(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 2547f2e4bb7..a72056e12d6 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -183,7 +183,7 @@ int mmc_get_boot(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 84799879e85..1b4b7d87163 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -296,6 +296,11 @@ M: Adam Sampson S: Maintained F: configs/Linksprite_pcDuino3_Nano_defconfig +LIONTRON H-A133L BOARD +M: Andre Przywara +S: Maintained +F: configs/liontron-h-a133l_defconfig + MARSBOARD-A10 BOARD M: Aleksei Mamlin S: Maintained @@ -596,6 +601,11 @@ M: Peter Korsgaard S: Maintained F: configs/Yones_Toptech_BS1078_V2_defconfig +YUZUKIHD CHAMELEON BOARD +M: Andre Przywara +S: Maintained +F: configs/yuzukihd-chameleon_defconfig + ZEROPI BOARD M: Yu-Tung Chang S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ac9cefc6eac..943b6221b8a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -114,7 +114,7 @@ void i2c_init_board(void) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); -#elif CONFIG_MACH_SUN50I_H616 +#elif defined(CONFIG_MACH_SUN50I_H616) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); @@ -435,7 +435,7 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } -#elif defined(CONFIG_MACH_SUN50I_H616) +#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) @@ -516,7 +516,7 @@ int board_mmc_init(struct bd_info *bis) return 0; } -#ifdef CONFIG_SYS_MMC_ENV_DEV +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX int mmc_get_env_dev(void) { switch (sunxi_get_boot_device()) { @@ -525,7 +525,7 @@ int mmc_get_env_dev(void) case BOOT_DEVICE_MMC2: return 1; default: - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } } #endif diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index d0f739c624a..cf6b7fcbd95 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 NXP Semiconductors */ +#include #include #include #include diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c index 25dfa387c36..d75fa6f3eff 100644 --- a/board/thead/th1520_lpi4a/spl.c +++ b/board/thead/th1520_lpi4a/spl.c @@ -39,6 +39,9 @@ void board_init_f(ulong dummy) if (ret) panic("failed to bind CPU: %d\n", ret); + riscv_cpu_setup(); + th1520_kick_secondary_cores(); + spl_dram_init(); icache_enable(); diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 960de15398f..d416d88c1a1 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -274,6 +274,47 @@ static struct module_pin_mux uart3_icev2_pin_mux[] = { {-1}, }; +#if (IS_ENABLED(CONFIG_AM335X_LCD)) +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0))}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0))}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0))}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0))}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0))}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0))}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0))}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0))}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0))}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0))}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0))}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0))}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0))}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0))}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0))}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0))}, /* LCD-Data(15) */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD-Data(23) */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD-CLK */ + {-1}, +}; +#endif + +#if (IS_ENABLED(CONFIG_PWM_TI_ECAP)) +static struct module_pin_mux ecap_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, /* ecap0_in_pwm0_out */ + {-1}, +}; +#endif + #if defined(CONFIG_NOR_BOOT) void enable_norboot_pin_mux(void) { @@ -389,6 +430,13 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } + #if IS_ENABLED(CONFIG_AM335X_LCD) + configure_module_pin_mux(lcd_pin_mux); + #endif + + #if IS_ENABLED(CONFIG_PWM_TI_ECAP) + configure_module_pin_mux(ecap_pin_mux); + #endif } else if (board_is_idk()) { /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h index ca1aa80f2f0..b057f3b2269 100644 --- a/board/ti/common/board_detect.h +++ b/board/ti/common/board_detect.h @@ -10,6 +10,8 @@ /* TI EEPROM MAGIC Header identifier */ #include +#include + #define TI_EEPROM_HEADER_MAGIC 0xEE3355AA #define TI_DEAD_EEPROM_MAGIC 0xADEAD12C @@ -18,7 +20,7 @@ #define TI_EEPROM_HDR_SERIAL_LEN 12 #define TI_EEPROM_HDR_CONFIG_LEN 32 #define TI_EEPROM_HDR_NO_OF_MAC_ADDR 3 -#define TI_EEPROM_HDR_ETH_ALEN 6 +#define TI_EEPROM_HDR_ETH_ALEN ETH_ALEN /** * struct ti_am_eeprom - This structure holds data read in from the diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env index 6cc92bf0d8d..292fc72fd58 100644 --- a/board/ti/j7200/j7200.env +++ b/board/ti/j7200/j7200.env @@ -36,5 +36,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J7200_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw +rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 0525f6e6f97..b1ed29af001 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index e5b4225b3ce..ead7fbdb212 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -38,5 +38,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J721E_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw +rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index a6b22550809..abd4faea6ee 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -24,6 +24,6 @@ name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw #endif rd_spec=- -rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw +rproc_fw_binaries= 1 /lib/firmware/j721s2-mcu-r5f0_1-fw 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 9e1741be424..2f1a5f549d1 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -21,7 +21,7 @@ bootdir=/boot rd_spec=- #if CONFIG_TARGET_J784S4_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw +rproc_fw_binaries= 1 /lib/firmware/j784s4-mcu-r5f0_1-fw 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw #elif CONFIG_TARGET_J742S2_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw +rproc_fw_binaries= 1 /lib/firmware/j742s2-mcu-r5f0_1-fw 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw #endif diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index 698b05bc5ad..8721276bed8 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -11,6 +11,7 @@ #include #include #include +#include static int mfgr_fuse(void) { diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index 698b05bc5ad..8721276bed8 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -11,6 +11,7 @@ #include #include #include +#include static int mfgr_fuse(void) { diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 7de29e3abfb..69a8a18d3a7 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 6c1cea77c8c..a89c5bf2c19 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -166,6 +166,23 @@ const struct toradex_som toradex_modules[] = { { APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, { SMARC_IMX95_HEXA_8GB_WB_IT, "SMARC iMX95 Hexa 8GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, { SMARC_IMX8MPQ_4GB_WB_IT, "SMARC iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { AQUILA_IMX95_HEXA_16GB_WB_IT, "Aquila iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(AQUILA_IMX95) }, + { VERDIN_AM62PQ_2G_WIFI_BT_IT, "Verdin AM62P Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62P_A53) }, + { SMARC_IMX95_HEXA_8GB_IT, "SMARC iMX95 Hexa 8GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_4GB_WB_IT, "SMARC iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_4GB_ET, "SMARC iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_2GB_WB_IT, "SMARC iMX95 Hexa 2GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_2GB_ET, "SMARC iMX95 Hexa 2GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX8MPQ_4GB_IT, "SMARC iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQ_2GB_WB_IT, "SMARC iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQ_2GB_IT, "SMARC iMX8M Plus Quad 2GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQL_1GB_WB_ET, "SMARC iMX8M Plus Quadlite 1GB WB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQL_1GB_ET, "SMARC iMX8M Plus Quadlite 1GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { AQUILA_AM69O_32GB_IT, "Aquila AM69 Octa 32GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_16GB_WB_IT, "Aquila AM69 Octa 16GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_16GB_IT, "Aquila AM69 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_8GB_WB_IT, "Aquila AM69 Octa 8GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_8GB_IT, "Aquila AM69 Octa 8GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index f4dd853306b..db612811c5c 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -124,6 +124,23 @@ enum { APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, /* 95 */ SMARC_IMX95_HEXA_8GB_WB_IT, SMARC_IMX8MPQ_4GB_WB_IT, + AQUILA_IMX95_HEXA_16GB_WB_IT, + VERDIN_AM62PQ_2G_WIFI_BT_IT, /* 99 */ + SMARC_IMX95_HEXA_8GB_IT = 201, + SMARC_IMX95_HEXA_4GB_WB_IT, + SMARC_IMX95_HEXA_4GB_ET, + SMARC_IMX95_HEXA_2GB_WB_IT, + SMARC_IMX95_HEXA_2GB_ET, /* 205 */ + SMARC_IMX8MPQ_4GB_IT, + SMARC_IMX8MPQ_2GB_WB_IT, + SMARC_IMX8MPQ_2GB_IT, + SMARC_IMX8MPQL_1GB_WB_ET, + SMARC_IMX8MPQL_1GB_ET, /* 210 */ + AQUILA_AM69O_32GB_IT, + AQUILA_AM69O_16GB_WB_IT, + AQUILA_AM69O_16GB_IT, + AQUILA_AM69O_8GB_WB_IT, + AQUILA_AM69O_8GB_IT, /* 215 */ }; enum { diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 7b2eecbf659..eca2cc8bc7f 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "../common/tdx-cfg-block.h" diff --git a/board/toradex/verdin-am62p/Kconfig b/board/toradex/verdin-am62p/Kconfig new file mode 100644 index 00000000000..7bf0133b669 --- /dev/null +++ b/board/toradex/verdin-am62p/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +choice + prompt "Toradex Verdin AM62P based boards" + optional + +config TARGET_VERDIN_AM62P_A53 + bool "Toradex Verdin AM62P running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + +config TARGET_VERDIN_AM62P_R5 + bool "Toradex Verdin AM62P running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_VERDIN_AM62P_A53 + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_EXTRA + default y + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif + +if TARGET_VERDIN_AM62P_R5 + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +endif diff --git a/board/toradex/verdin-am62p/MAINTAINERS b/board/toradex/verdin-am62p/MAINTAINERS new file mode 100644 index 00000000000..97094e0e756 --- /dev/null +++ b/board/toradex/verdin-am62p/MAINTAINERS @@ -0,0 +1,17 @@ +Verdin AM62P +M: Francesco Dolcini +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p +S: Maintained +F: arch/arm/dts/k3-am62p-verdin-dev.dtsi +F: arch/arm/dts/k3-am62p-verdin-wifi.dtsi +F: arch/arm/dts/k3-am62p-verdin.dtsi +F: arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi +F: arch/arm/dts/k3-am62p5-verdin-r5.dts +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts +F: board/toradex/verdin-am62p/ +F: configs/verdin-am62p_a53_defconfig +F: configs/verdin-am62p_r5_defconfig +F: doc/board/toradex/verdin-am62p.rst +F: include/configs/verdin-am62p.h diff --git a/board/toradex/verdin-am62p/Makefile b/board/toradex/verdin-am62p/Makefile new file mode 100644 index 00000000000..2eef6f4f592 --- /dev/null +++ b/board/toradex/verdin-am62p/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +obj-y += verdin-am62p.o diff --git a/board/toradex/verdin-am62p/board-cfg.yaml b/board/toradex/verdin-am62p/board-cfg.yaml new file mode 100644 index 00000000000..d539011aff9 --- /dev/null +++ b/board/toradex/verdin-am62p/board-cfg.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62Px SoCs +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/toradex/verdin-am62p/pm-cfg.yaml b/board/toradex/verdin-am62p/pm-cfg.yaml new file mode 100644 index 00000000000..3ff27ce702c --- /dev/null +++ b/board/toradex/verdin-am62p/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62Px +# +# +--- +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/toradex/verdin-am62p/rm-cfg.yaml b/board/toradex/verdin-am62p/rm-cfg.yaml new file mode 100644 index 00000000000..73da85eeade --- /dev/null +++ b/board/toradex/verdin-am62p/rm-cfg.yaml @@ -0,0 +1,1083 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 1112 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 16 + type: 192 + host_id: 12 + reserved: 0 + - + start_resource: 34 + num_resource: 2 + type: 192 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 320 + host_id: 12 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 + - + start_resource: 4 + num_resource: 4 + type: 320 + host_id: 30 + reserved: 0 + - + start_resource: 0 + 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12813 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/verdin-am62p/sec-cfg.yaml b/board/toradex/verdin-am62p/sec-cfg.yaml new file mode 100644 index 00000000000..bfd6a4e5dbd --- /dev/null +++ b/board/toradex/verdin-am62p/sec-cfg.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM62Px +# +--- +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - # 1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - # 1 + host_id: 0 + supervisor_host_id: 0 + - # 2 + host_id: 0 + supervisor_host_id: 0 + - # 3 + host_id: 0 + supervisor_host_id: 0 + - # 4 + host_id: 0 + supervisor_host_id: 0 + - # 5 + host_id: 0 + supervisor_host_id: 0 + - # 6 + host_id: 0 + supervisor_host_id: 0 + - # 7 + host_id: 0 + supervisor_host_id: 0 + - # 8 + host_id: 0 + supervisor_host_id: 0 + - # 9 + host_id: 0 + supervisor_host_id: 0 + - # 10 + host_id: 0 + supervisor_host_id: 0 + - # 11 + host_id: 0 + supervisor_host_id: 0 + - # 12 + host_id: 0 + supervisor_host_id: 0 + - # 13 + host_id: 0 + supervisor_host_id: 0 + - # 14 + host_id: 0 + supervisor_host_id: 0 + - # 15 + host_id: 0 + supervisor_host_id: 0 + - # 16 + host_id: 0 + supervisor_host_id: 0 + - # 17 + host_id: 0 + supervisor_host_id: 0 + - # 18 + host_id: 0 + supervisor_host_id: 0 + - # 19 + host_id: 0 + supervisor_host_id: 0 + - # 20 + host_id: 0 + supervisor_host_id: 0 + - # 21 + host_id: 0 + supervisor_host_id: 0 + - # 22 + host_id: 0 + supervisor_host_id: 0 + - # 23 + host_id: 0 + supervisor_host_id: 0 + - # 24 + host_id: 0 + supervisor_host_id: 0 + - # 25 + host_id: 0 + supervisor_host_id: 0 + - # 26 + host_id: 0 + supervisor_host_id: 0 + - # 27 + host_id: 0 + supervisor_host_id: 0 + - # 28 + host_id: 0 + supervisor_host_id: 0 + - # 29 + host_id: 0 + supervisor_host_id: 0 + - # 30 + host_id: 0 + supervisor_host_id: 0 + - # 31 + host_id: 0 + supervisor_host_id: 0 + - # 32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + otp_entry: + - # 1 + host_id: 0 + host_perms: 0 + - # 2 + host_id: 0 + host_perms: 0 + - # 3 + host_id: 0 + host_perms: 0 + - # 4 + host_id: 0 + host_perms: 0 + - # 5 + host_id: 0 + host_perms: 0 + - # 6 + host_id: 0 + host_perms: 0 + - # 7 + host_id: 0 + host_perms: 0 + - # 8 + host_id: 0 + host_perms: 0 + - # 9 + host_id: 0 + host_perms: 0 + - # 10 + host_id: 0 + host_perms: 0 + - # 11 + host_id: 0 + host_perms: 0 + - # 12 + host_id: 0 + host_perms: 0 + - # 13 + host_id: 0 + host_perms: 0 + - # 14 + host_id: 0 + host_perms: 0 + - # 15 + host_id: 0 + host_perms: 0 + - # 16 + host_id: 0 + host_perms: 0 + - # 17 + host_id: 0 + host_perms: 0 + - # 18 + host_id: 0 + host_perms: 0 + - # 19 + host_id: 0 + host_perms: 0 + - # 20 + host_id: 0 + host_perms: 0 + - # 21 + host_id: 0 + host_perms: 0 + - # 22 + host_id: 0 + host_perms: 0 + - # 23 + host_id: 0 + host_perms: 0 + - # 24 + host_id: 0 + host_perms: 0 + - # 25 + host_id: 0 + host_perms: 0 + - # 26 + host_id: 0 + host_perms: 0 + - # 27 + host_id: 0 + host_perms: 0 + - # 28 + host_id: 0 + host_perms: 0 + - # 29 + host_id: 0 + host_perms: 0 + - # 30 + host_id: 0 + host_perms: 0 + - # 31 + host_id: 0 + host_perms: 0 + - # 32 + host_id: 0 + host_perms: 0 + write_host_id: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..80269748057 --- /dev/null +++ b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml @@ -0,0 +1,927 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 904 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + 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host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c new file mode 100644 index 00000000000..8b246e9d304 --- /dev/null +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Board specific initialization for Verdin AM62P SoM + * + * Copyright 2025 Toradex - https://www.toradex.com/ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; +static u8 hw_cfg; + +static void read_hw_cfg(void) +{ + struct gpio_desc gpio_hw_cfg; + static const int gpios[] = { 58, 61, 62 }; /* HW_CFG0, HW_CFG1, HW_CFG2 */ + char gpio_name[20]; + int i; + + printf("HW CFG: "); + + for (i = 0; i < ARRAY_SIZE(gpios); i++) { + snprintf(gpio_name, sizeof(gpio_name), "gpio@600000_%d", gpios[i]); + + if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) { + printf("Lookup error: GPIO %d\n", gpios[i]); + continue; + } + + if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) { + printf("GPIO request error: %d\n", gpios[i]); + continue; + } + + if (dm_gpio_get_value(&gpio_hw_cfg) == 1) + hw_cfg |= BIT(i); + + dm_gpio_free(NULL, &gpio_hw_cfg); + } + + printf("0x%02x\n", hw_cfg); +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); + + if (gd->ram_size < SZ_1G) + puts("## WARNING: Less than 1GB RAM detected\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + /* Use the detected RAM size, we only support 1 bank right now. */ + gd->bd->bi_dram[0].size = gd->ram_size; + + return ret; +} + +#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + int is_wifi = 0; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a module with + * Wi-Fi/Bluetooth make sure we use the -wifi device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62PQ_2G_WIFI_BT_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + return 0; +} + +#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4) + +void spl_board_init(void) +{ + u32 val; + + /* + * We use the 32k FOUT from the Epson RX8130CE RTC chip, + * configure LFXOSC accordingly, see AM62P datasheet, + * Table 6-23, LFXOSC Modes of Operation. + */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL; + val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL; + writel(val, MCU_CTRL_LFXOSC_CTRL); + /* Make sure to mux up to take the SoC 32k from the LFOSC input */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + + read_hw_cfg(); +} diff --git a/board/toradex/verdin-am62p/verdin-am62p.env b/board/toradex/verdin-am62p/verdin-am62p.env new file mode 100644 index 00000000000..f8b7363dcf5 --- /dev/null +++ b/board/toradex/verdin-am62p/verdin-am62p.env @@ -0,0 +1,41 @@ +#define CFG_RAMDISK_ADDR_R 0x90300000 +#define CFG_SCRIPTADDR 0x90280000 + +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyS2 +fdt_addr_r=0x90200000 +fdt_board=dev +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80200000 +kernel_comp_size=0x08000000 +ramdisk_addr_r=CFG_RAMDISK_ADDR_R +scriptaddr=CFG_SCRIPTADDR + +dfu_alt_info_ram= + tispl.bin ram 0x80080000 0x200000; + u-boot.img ram 0x81000000 0x400000; + loadaddr ram CONFIG_SYS_LOAD_ADDR 0x80000; + scriptaddr ram CFG_SCRIPTADDR 0x80000; + ramdisk_addr_r ram CFG_RAMDISK_ADDR_R 0x8000000 + +update_tiboot3= + askenv confirm Did you load tiboot3.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; + fi + +update_tispl= + askenv confirm Did you load tispl.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; + fi + +update_uboot= + askenv confirm Did you load u-boot.img (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; + fi diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 9359e0ac6bf..066e8db678f 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -3,7 +3,7 @@ * Copyright 2020-2021 Toradex */ -#include +#include #include #include #include diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 735ef3cd1be..789b945d462 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/boot/Kconfig b/boot/Kconfig index 30eb5b328d7..a671d78e570 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -11,6 +11,17 @@ config ANDROID_BOOT_IMAGE This enables support for booting images which use the Android image format header. +config ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR + bool "Android Boot Image ignore addr" + default n + help + This ignore kernel/ramdisk load addr specified in androidboot header. + + There is a concern on exposing the whole memory to image loading is + dangerous. Also, since it's not always possible to change the load + addr by repacking the boot.img (mainly due to AVB signature mismatch), + we need a way to use kernel_addr_r and ramdisk_addr_r. + config TIMESTAMP bool "Show image date and time when displaying image information" default y if CMD_DATE @@ -855,6 +866,56 @@ config EXPO The expo can be presented in graphics form using a vidconsole, or in text form on a serial console. +config BOOTMETH_RAUC + bool "Bootdev support for RAUC A/B systems" + depends on CMDLINE + select BOOTMETH_GLOBAL + select HUSH_PARSER + help + Enables support for booting RAUC A/B systems from MMC devices. This + makes the bootdevs look for a 'boot.scr.uimg' or 'boot.scr' in the + respective boot partitions, describing how to boot the distro. + +if BOOTMETH_RAUC + +config BOOTMETH_RAUC_BOOT_ORDER + string "RAUC boot order" + default "A B" + help + Sets the default boot order. This must be list of space-separated + strings naming the individual boot slots. Each entry in this string + should correspond to an existing slot on the target's flash device. + +config BOOTMETH_RAUC_PARTITIONS + string "RAUC boot and root partitions indexes" + default "1,2 3,4" + help + Sets the partition indexes of boot and root slots. This must be a list + of comma-separated pair values, which in turn are separated by spaces. + The first value in pair is for the boot partition and second for the + root partition. + +config BOOTMETH_RAUC_DEFAULT_TRIES + int "RAUC slot default tries" + default 3 + help + Sets how many times a slot should be tried booting, before considering + it to be bad. + +config BOOTMETH_RAUC_RESET_ALL_ZERO_TRIES + bool "Reset slot tries when all RAUC slots have zero tries left" + default y + help + When all slots have zero tries left or no valid slot was found, reset + to the default boot order set by BOOTMETH_RAUC_BOOT_ORDER and set the + slot tries to their default value specified by + BOOTMETH_RAUC_DEFAULT_TRIES. + + This prevents a system from remaining in an unbootable state, after + all slot tries were decremented to zero. + +endif # BOOTMETH_RAUC + config BOOTMETH_SANDBOX def_bool y depends on SANDBOX @@ -1845,7 +1906,7 @@ config USE_BOOTARGS config BOOTARGS string "Boot arguments" - depends on USE_BOOTARGS && !USE_DEFAULT_ENV_FILE + depends on USE_BOOTARGS && !ENV_USE_DEFAULT_ENV_TEXT_FILE help This can be used to pass arguments to the bootm command. The value of CONFIG_BOOTARGS goes into the environment value "bootargs". Note that @@ -1880,7 +1941,7 @@ config USE_BOOTCOMMAND config BOOTCOMMAND string "bootcmd value" - depends on USE_BOOTCOMMAND && !USE_DEFAULT_ENV_FILE + depends on USE_BOOTCOMMAND && !ENV_USE_DEFAULT_ENV_TEXT_FILE default "bootflow scan -lb" if BOOTSTD_DEFAULTS && CMD_BOOTFLOW_FULL default "bootflow scan" if BOOTSTD_DEFAULTS && !CMD_BOOTFLOW_FULL default "run distro_bootcmd" if !BOOTSTD_BOOTCOMMAND && DISTRO_DEFAULTS @@ -1903,7 +1964,7 @@ config USE_PREBOOT config PREBOOT string "preboot default value" - depends on USE_PREBOOT && !USE_DEFAULT_ENV_FILE + depends on USE_PREBOOT && !ENV_USE_DEFAULT_ENV_TEXT_FILE default "usb start" if USB_KEYBOARD default "" help diff --git a/boot/Makefile b/boot/Makefile index 71dafaefa76..3da6f7a0914 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_$(PHASE_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o obj-$(CONFIG_$(PHASE_)BOOTMETH_EFILOADER) += bootmeth_efi.o obj-$(CONFIG_$(PHASE_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o obj-$(CONFIG_$(PHASE_)BOOTMETH_QFW) += bootmeth_qfw.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_RAUC) += bootmeth_rauc.o obj-$(CONFIG_$(PHASE_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o obj-$(CONFIG_$(PHASE_)BOOTMETH_SCRIPT) += bootmeth_script.o obj-$(CONFIG_$(PHASE_)CEDIT) += cedit.o @@ -58,7 +59,7 @@ obj-$(CONFIG_CMD_ADTIMG) += image-android-dt.o obj-$(CONFIG_$(PHASE_)LOAD_FIT) += common_fit.o obj-$(CONFIG_$(PHASE_)EXPO) += expo.o scene.o expo_build.o -obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o +obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o scene_textedit.o ifdef CONFIG_COREBOOT_SYSINFO obj-$(CONFIG_$(PHASE_)EXPO) += expo_build_cb.o endif diff --git a/boot/bootflow_internal.h b/boot/bootflow_internal.h index 38cf02a55b5..4cdb6966a7b 100644 --- a/boot/bootflow_internal.h +++ b/boot/bootflow_internal.h @@ -14,7 +14,10 @@ enum { START, /* strings */ - STR_PROMPT, + STR_PROMPT1A, + STR_PROMPT1B, + STR_PROMPT2, + STR_AUTOBOOT, STR_MENU_TITLE, STR_POINTER, @@ -23,10 +26,14 @@ enum { /* objects */ OBJ_U_BOOT_LOGO, + OBJ_BOX, OBJ_MENU, - OBJ_PROMPT, + OBJ_PROMPT1A, + OBJ_PROMPT1B, + OBJ_PROMPT2, OBJ_MENU_TITLE, OBJ_POINTER, + OBJ_AUTOBOOT, /* strings for menu items */ STR_LABEL = 100, diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 9d0dc352f97..4a442e16850 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -25,21 +25,22 @@ * struct menu_priv - information about the menu * * @num_bootflows: Number of bootflows in the menu + * @last_bootdev: bootdev of the last bootflow added to the menu, NULL if none */ struct menu_priv { int num_bootflows; + struct udevice *last_bootdev; }; int bootflow_menu_new(struct expo **expp) { - struct udevice *last_bootdev; struct scene_obj_menu *menu; struct menu_priv *priv; - struct bootflow *bflow; struct scene *scn; struct expo *exp; + bool use_font; void *logo; - int ret, i; + int ret; priv = calloc(1, sizeof(*priv)); if (!priv) @@ -53,34 +54,150 @@ int bootflow_menu_new(struct expo **expp) if (ret < 0) return log_msg_ret("scn", ret); - ret |= scene_txt_str(scn, "prompt", OBJ_PROMPT, STR_PROMPT, - "UP and DOWN to choose, ENTER to select", NULL); + ret = scene_box(scn, "box", OBJ_BOX, 2, NULL); + if (ret < 0) + return log_msg_ret("bmb", ret); + ret |= scene_obj_set_bbox(scn, OBJ_BOX, 30, 90, 1366 - 30, 720); ret = scene_menu(scn, "main", OBJ_MENU, &menu); ret |= scene_obj_set_pos(scn, OBJ_MENU, MARGIN_LEFT, 100); ret |= scene_txt_str(scn, "title", OBJ_MENU_TITLE, STR_MENU_TITLE, "U-Boot - Boot Menu", NULL); - ret |= scene_menu_set_title(scn, OBJ_MENU, OBJ_PROMPT); + ret |= scene_obj_set_bbox(scn, OBJ_MENU_TITLE, 0, 32, + SCENEOB_DISPLAY_MAX, 30); + ret |= scene_obj_set_halign(scn, OBJ_MENU_TITLE, SCENEOA_CENTRE); logo = video_get_u_boot_logo(); if (logo) { ret |= scene_img(scn, "ulogo", OBJ_U_BOOT_LOGO, logo, NULL); - ret |= scene_obj_set_pos(scn, OBJ_U_BOOT_LOGO, -4, 4); + ret |= scene_obj_set_pos(scn, OBJ_U_BOOT_LOGO, 1165, 100); } + ret |= scene_txt_str(scn, "prompt1a", OBJ_PROMPT1A, STR_PROMPT1A, + "Use the \x18 and \x19 keys to select which entry is highlighted.", + NULL); + ret |= scene_txt_str(scn, "prompt1b", OBJ_PROMPT1B, STR_PROMPT1B, + "Use the UP and DOWN keys to select which entry is highlighted.", + NULL); + ret |= scene_txt_str(scn, "prompt2", OBJ_PROMPT2, STR_PROMPT2, + "Press enter to boot the selected OS, 'e' to edit the commands " + "before booting or 'c' for a command-line. ESC to return to " + "previous menu", NULL); + ret |= scene_txt_str(scn, "autoboot", OBJ_AUTOBOOT, STR_AUTOBOOT, + "The highlighted entry will be executed automatically in %ds.", + NULL); + ret |= scene_obj_set_bbox(scn, OBJ_PROMPT1A, 0, 590, + SCENEOB_DISPLAY_MAX, 30); + ret |= scene_obj_set_bbox(scn, OBJ_PROMPT1B, 0, 620, + SCENEOB_DISPLAY_MAX, 30); + ret |= scene_obj_set_bbox(scn, OBJ_PROMPT2, 100, 650, + 1366 - 100, 700); + ret |= scene_obj_set_bbox(scn, OBJ_AUTOBOOT, 0, 720, + SCENEOB_DISPLAY_MAX, 750); + ret |= scene_obj_set_halign(scn, OBJ_PROMPT1A, SCENEOA_CENTRE); + ret |= scene_obj_set_halign(scn, OBJ_PROMPT1B, SCENEOA_CENTRE); + ret |= scene_obj_set_halign(scn, OBJ_PROMPT2, SCENEOA_CENTRE); + ret |= scene_obj_set_valign(scn, OBJ_PROMPT2, SCENEOA_CENTRE); + ret |= scene_obj_set_halign(scn, OBJ_AUTOBOOT, SCENEOA_CENTRE); + + use_font = IS_ENABLED(CONFIG_CONSOLE_TRUETYPE); + scene_obj_set_hide(scn, OBJ_PROMPT1A, use_font); + scene_obj_set_hide(scn, OBJ_PROMPT1B, !use_font); + scene_obj_set_hide(scn, OBJ_AUTOBOOT, use_font); + ret |= scene_txt_str(scn, "cur_item", OBJ_POINTER, STR_POINTER, ">", NULL); ret |= scene_menu_set_pointer(scn, OBJ_MENU, OBJ_POINTER); if (ret < 0) return log_msg_ret("new", -EINVAL); - last_bootdev = NULL; + exp->show_highlight = true; + + *expp = exp; + + return 0; +} + +int bootflow_menu_add(struct expo *exp, struct bootflow *bflow, int seq, + struct scene **scnp) +{ + struct menu_priv *priv = exp->priv; + char str[2], *label, *key; + struct udevice *media; + struct scene *scn; + const char *name; + uint preview_id; + uint scene_id; + bool add_gap; + int ret; + + ret = expo_first_scene_id(exp); + if (ret < 0) + return log_msg_ret("scn", ret); + scene_id = ret; + scn = expo_lookup_scene_id(exp, scene_id); + + *str = seq < 10 ? '0' + seq : 'A' + seq - 10; + str[1] = '\0'; + key = strdup(str); + if (!key) + return log_msg_ret("key", -ENOMEM); + + media = dev_get_parent(bflow->dev); + if (device_get_uclass_id(media) == UCLASS_MASS_STORAGE) + name = "usb"; + else + name = media->name; + label = strdup(name); + + if (!label) { + free(key); + return log_msg_ret("nam", -ENOMEM); + } + + add_gap = priv->last_bootdev != bflow->dev; + + /* disable this gap for now, since it looks a little ugly */ + add_gap = false; + priv->last_bootdev = bflow->dev; + + ret = expo_str(exp, "prompt", STR_POINTER, ">"); + ret |= scene_txt_str(scn, "label", ITEM_LABEL + seq, + STR_LABEL + seq, label, NULL); + ret |= scene_txt_str(scn, "desc", ITEM_DESC + seq, STR_DESC + seq, + bflow->os_name ? bflow->os_name : + bflow->name, NULL); + ret |= scene_txt_str(scn, "key", ITEM_KEY + seq, STR_KEY + seq, key, + NULL); + preview_id = 0; + if (bflow->logo) { + preview_id = ITEM_PREVIEW + seq; + ret |= scene_img(scn, "preview", preview_id, + bflow->logo, NULL); + } + ret |= scene_menuitem(scn, OBJ_MENU, "item", ITEM + seq, + ITEM_KEY + seq, ITEM_LABEL + seq, + ITEM_DESC + seq, preview_id, + add_gap ? SCENEMIF_GAP_BEFORE : 0, + NULL); + + if (ret < 0) + return log_msg_ret("itm", -EINVAL); + priv->num_bootflows++; + *scnp = scn; + + return 0; +} + +int bootflow_menu_add_all(struct expo *exp) +{ + struct bootflow *bflow; + struct scene *scn; + int ret, i; + for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36; ret = bootflow_next_glob(&bflow), i++) { struct bootmeth_uc_plat *ucp; - char str[2], *label, *key; - uint preview_id; - bool add_gap; if (bflow->state != BOOTFLOWST_READY) continue; @@ -90,116 +207,24 @@ int bootflow_menu_new(struct expo **expp) if (ucp->flags & BOOTMETHF_GLOBAL) continue; - *str = i < 10 ? '0' + i : 'A' + i - 10; - str[1] = '\0'; - key = strdup(str); - if (!key) - return log_msg_ret("key", -ENOMEM); - label = strdup(dev_get_parent(bflow->dev)->name); - if (!label) { - free(key); - return log_msg_ret("nam", -ENOMEM); - } - - add_gap = last_bootdev != bflow->dev; - last_bootdev = bflow->dev; - - ret = expo_str(exp, "prompt", STR_POINTER, ">"); - ret |= scene_txt_str(scn, "label", ITEM_LABEL + i, - STR_LABEL + i, label, NULL); - ret |= scene_txt_str(scn, "desc", ITEM_DESC + i, STR_DESC + i, - bflow->os_name ? bflow->os_name : - bflow->name, NULL); - ret |= scene_txt_str(scn, "key", ITEM_KEY + i, STR_KEY + i, key, - NULL); - preview_id = 0; - if (bflow->logo) { - preview_id = ITEM_PREVIEW + i; - ret |= scene_img(scn, "preview", preview_id, - bflow->logo, NULL); - } - ret |= scene_menuitem(scn, OBJ_MENU, "item", ITEM + i, - ITEM_KEY + i, ITEM_LABEL + i, - ITEM_DESC + i, preview_id, - add_gap ? SCENEMIF_GAP_BEFORE : 0, - NULL); - - if (ret < 0) - return log_msg_ret("itm", -EINVAL); - priv->num_bootflows++; + ret = bootflow_menu_add(exp, bflow, i, &scn); + if (ret) + return log_msg_ret("bao", ret); } - ret = scene_arrange(scn); - if (ret) - return log_msg_ret("arr", ret); - - *expp = exp; - return 0; } -int bootflow_menu_apply_theme(struct expo *exp, ofnode node) +int bootflow_menu_setup(struct bootstd_priv *std, bool text_mode, + struct expo **expp) { - struct menu_priv *priv = exp->priv; - struct scene *scn; - u32 font_size; - int ret; - - log_debug("Applying theme %s\n", ofnode_get_name(node)); - scn = expo_lookup_scene_id(exp, MAIN); - if (!scn) - return log_msg_ret("scn", -ENOENT); - - /* Avoid error-checking optional items */ - if (!ofnode_read_u32(node, "font-size", &font_size)) { - int i; - - log_debug("font size %d\n", font_size); - scene_txt_set_font(scn, OBJ_PROMPT, NULL, font_size); - scene_txt_set_font(scn, OBJ_POINTER, NULL, font_size); - for (i = 0; i < priv->num_bootflows; i++) { - ret = scene_txt_set_font(scn, ITEM_DESC + i, NULL, - font_size); - if (ret) - return log_msg_ret("des", ret); - scene_txt_set_font(scn, ITEM_KEY + i, NULL, font_size); - scene_txt_set_font(scn, ITEM_LABEL + i, NULL, - font_size); - } - } - - ret = scene_arrange(scn); - if (ret) - return log_msg_ret("arr", ret); - - return 0; -} - -int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, - struct bootflow **bflowp) -{ - struct cli_ch_state s_cch, *cch = &s_cch; - struct bootflow *sel_bflow; struct udevice *dev; struct expo *exp; - uint sel_id; - bool done; int ret; - cli_ch_init(cch); - - sel_bflow = NULL; - *bflowp = NULL; - ret = bootflow_menu_new(&exp); if (ret) - return log_msg_ret("exp", ret); - - if (ofnode_valid(std->theme)) { - ret = bootflow_menu_apply_theme(exp, std->theme); - if (ret) - return log_msg_ret("thm", ret); - } + return log_msg_ret("bmn", ret); /* For now we only support a video console */ ret = uclass_first_device_err(UCLASS_VIDEO, &dev); @@ -216,78 +241,91 @@ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, if (text_mode) expo_set_text_mode(exp, text_mode); - done = false; - do { - struct expo_action act; - int ichar, key; - - ret = expo_render(exp); - if (ret) - break; - - ichar = cli_ch_process(cch, 0); - if (!ichar) { - while (!ichar && !tstc()) { - schedule(); - mdelay(2); - ichar = cli_ch_process(cch, -ETIMEDOUT); - } - if (!ichar) { - ichar = getchar(); - ichar = cli_ch_process(cch, ichar); - } - } - - key = 0; - if (ichar) { - key = bootmenu_conv_key(ichar); - if (key == BKEY_NONE) - key = ichar; - } - if (!key) - continue; - - ret = expo_send_key(exp, key); - if (ret) - break; - - ret = expo_action_get(exp, &act); - if (!ret) { - switch (act.type) { - case EXPOACT_SELECT: - sel_id = act.select.id; - done = true; - break; - case EXPOACT_QUIT: - done = true; - break; - default: - break; - } - } - } while (!done); - - if (ret) - return log_msg_ret("end", ret); - - if (sel_id) { - struct bootflow *bflow; - int i; - - for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36; - ret = bootflow_next_glob(&bflow), i++) { - if (i == sel_id - ITEM) { - sel_bflow = bflow; - break; - } - } - } - - expo_destroy(exp); - - if (!sel_bflow) - return -EAGAIN; - *bflowp = sel_bflow; + *expp = exp; + + return 0; +} + +int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, + struct expo **expp) +{ + struct scene *scn; + struct expo *exp; + uint scene_id; + int ret; + + ret = bootflow_menu_setup(std, text_mode, &exp); + if (ret) + return log_msg_ret("bmd", ret); + + ret = bootflow_menu_add_all(exp); + if (ret) + return log_msg_ret("bma", ret); + + if (ofnode_valid(std->theme)) { + ret = expo_apply_theme(exp, std->theme); + if (ret) + return log_msg_ret("thm", ret); + } + + ret = expo_calc_dims(exp); + if (ret) + return log_msg_ret("bmd", ret); + + ret = expo_first_scene_id(exp); + if (ret < 0) + return log_msg_ret("scn", ret); + scene_id = ret; + scn = expo_lookup_scene_id(exp, scene_id); + + scene_set_highlight_id(scn, OBJ_MENU); + + ret = scene_arrange(scn); + if (ret) + return log_msg_ret("arr", ret); + + *expp = exp; + + return 0; +} + +int bootflow_menu_poll(struct expo *exp, int *seqp) +{ + struct bootflow *sel_bflow; + struct expo_action act; + struct scene *scn; + int item, ret; + + sel_bflow = NULL; + + scn = expo_lookup_scene_id(exp, exp->scene_id); + + item = scene_menu_get_cur_item(scn, OBJ_MENU); + *seqp = item > 0 ? item - ITEM : -1; + + ret = expo_poll(exp, &act); + if (ret) + return log_msg_ret("bmp", ret); + + switch (act.type) { + case EXPOACT_SELECT: + *seqp = act.select.id - ITEM; + break; + case EXPOACT_POINT_ITEM: { + struct scene *scn = expo_lookup_scene_id(exp, MAIN); + + if (!scn) + return log_msg_ret("bms", -ENOENT); + ret = scene_menu_select_item(scn, OBJ_MENU, act.select.id); + if (ret) + return log_msg_ret("bmp", ret); + return -ERESTART; + } + case EXPOACT_QUIT: + return -EPIPE; + default: + return -EAGAIN; + } return 0; } diff --git a/boot/bootm.c b/boot/bootm.c index 108ca7fb472..4bdca22ea8c 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -623,12 +623,16 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) */ if (os.type == IH_TYPE_KERNEL_NOLOAD && os.comp != IH_COMP_NONE) { ulong req_size = ALIGN(image_len * 4, SZ_1M); + phys_addr_t addr; - load = lmb_alloc(req_size, SZ_2M); - if (!load) + err = lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, &addr, + req_size, LMB_NONE); + if (err) return 1; - os.load = load; - images->ep = load; + + load = (ulong)addr; + os.load = (ulong)addr; + images->ep = (ulong)addr; debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n", req_size, load, image_len); } @@ -698,9 +702,18 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) images->os.end = relocated_addr + image_size; } - if (CONFIG_IS_ENABLED(LMB)) - lmb_reserve(images->os.load, (load_end - images->os.load), - LMB_NONE); + if (CONFIG_IS_ENABLED(LMB)) { + phys_addr_t load; + + load = (phys_addr_t)images->os.load; + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &load, + (load_end - images->os.load), LMB_NONE); + if (err) { + log_err("Unable to allocate memory %#lx for loading OS\n", + images->os.load); + return 1; + } + } return 0; } diff --git a/boot/bootm_os.c b/boot/bootm_os.c index a3c7cb5332e..88f7c183867 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -402,6 +402,17 @@ static int do_bootm_elf(int flag, struct bootm_info *bmi) if (flag != BOOTM_STATE_OS_GO) return 0; + /* + * Required per RISC-V boot protocol: + * a0(argc) = hartid of the current core + * a1(argv) = address of the devicetree in memory + * https://www.kernel.org/doc/html/latest/arch/riscv/boot.html#register-state + */ +#if defined(CONFIG_RISCV) + bmi->argc = gd->arch.boot_hart; + bmi->argv = (char **)bmi->images->ft_addr; +#endif + bootelf(bmi->images->ep, flags, bmi->argc, bmi->argv); return 1; diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c index 014b7588e8d..188f6ea1895 100644 --- a/boot/bootmeth-uclass.c +++ b/boot/bootmeth-uclass.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -135,10 +136,12 @@ int bootmeth_setup_iter_order(struct bootflow_iter *iter, bool include_global) * We don't support skipping global bootmeths. Instead, the user * should omit them from the ordering */ - if (!include_global) - return log_msg_ret("glob", -EPERM); + if (!include_global) { + ret = log_msg_ret("glob", -EPERM); + goto err_order; + } memcpy(order, std->bootmeth_order, - count * sizeof(struct bootmeth *)); + count * sizeof(struct udevice *)); if (IS_ENABLED(CONFIG_BOOTMETH_GLOBAL)) { for (i = 0; i < count; i++) { @@ -146,6 +149,12 @@ int bootmeth_setup_iter_order(struct bootflow_iter *iter, bool include_global) struct bootmeth_uc_plat *ucp; bool is_global; + ret = device_probe(dev); + if (ret) { + ret = log_msg_ret("probe", ret); + goto err_order; + } + ucp = dev_get_uclass_plat(dev); is_global = ucp->flags & BOOTMETHF_GLOBAL; @@ -190,8 +199,10 @@ int bootmeth_setup_iter_order(struct bootflow_iter *iter, bool include_global) } count = upto; } - if (!count) - return log_msg_ret("count2", -ENOENT); + if (!count) { + ret = log_msg_ret("count2", -ENOENT); + goto err_order; + } if (IS_ENABLED(CONFIG_BOOTMETH_GLOBAL) && include_global && iter->first_glob_method != -1 && iter->first_glob_method != count) { @@ -202,6 +213,10 @@ int bootmeth_setup_iter_order(struct bootflow_iter *iter, bool include_global) iter->num_methods = count; return 0; + +err_order: + free(order); + return ret; } int bootmeth_set_order(const char *order_str) diff --git a/boot/bootmeth_android.c b/boot/bootmeth_android.c index 654ebfdf1fc..8c2bde10e17 100644 --- a/boot/bootmeth_android.c +++ b/boot/bootmeth_android.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index 0c9b4c3d59d..0af23df3a4a 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c index 6e5e0f99ea4..faa8d729b15 100644 --- a/boot/bootmeth_pxe.c +++ b/boot/bootmeth_pxe.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/boot/bootmeth_rauc.c b/boot/bootmeth_rauc.c new file mode 100644 index 00000000000..fc60e6e355d --- /dev/null +++ b/boot/bootmeth_rauc.c @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Bootmethod for distro boot with RAUC + * + * Copyright 2025 PHYTEC Messtechnik GmbH + * Written by Martin Schwan + */ + +#define LOG_CATEGORY UCLASS_BOOTSTD + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Length of env var "BOOT_*_LEFT" */ +#define BOOT_LEFT_LEN (5 + 32 + 5) + +static const char * const script_names[] = { "boot.scr", "boot.scr.uimg", NULL }; + +/** + * struct distro_rauc_slot - Slot information + * + * A slot describes the unit of a bootable system consisting of one or multiple + * partitions. This usually includes a root filesystem, kernel and potentially other + * files, like device trees and boot scripts for that particular distribution. + * + * @name The slot name + * @boot_part The boot partition number on disk + * @root_part The root partition number on disk + */ +struct distro_rauc_slot { + char *name; + int boot_part; + int root_part; +}; + +/** + * struct distro_rauc_priv - Private data + * + * @slots All slots of the device in default order + * @boot_order String of the current boot order containing the active slot names + */ +struct distro_rauc_priv { + struct distro_rauc_slot **slots; +}; + +static struct distro_rauc_slot *get_slot(struct distro_rauc_priv *priv, + const char *slot_name) +{ + int i; + + for (i = 0; priv->slots[i]->name; i++) { + if (!strcmp(priv->slots[i]->name, slot_name)) + return priv->slots[i]; + } + + return NULL; +} + +static int distro_rauc_check(struct udevice *dev, struct bootflow_iter *iter) +{ + /* + * This distro only works on whole MMC devices, as multiple partitions + * are needed for an A/B system. + */ + if (bootflow_iter_check_mmc(iter)) + return log_msg_ret("mmc", -EOPNOTSUPP); + if (iter->part) + return log_msg_ret("part", -EOPNOTSUPP); + + return 0; +} + +static int distro_rauc_scan_boot_part(struct bootflow *bflow) +{ + struct blk_desc *desc; + struct distro_rauc_priv *priv; + char *boot_order; + const char **boot_order_list; + bool exists; + int ret; + int i; + int j; + + desc = dev_get_uclass_plat(bflow->blk); + + priv = bflow->bootmeth_priv; + if (!priv || !priv->slots) + return log_msg_ret("priv", -EINVAL); + + boot_order = env_get("BOOT_ORDER"); + boot_order_list = str_to_list(boot_order); + for (i = 0; boot_order_list[i]; i++) { + exists = false; + for (j = 0; script_names[j]; j++) { + const struct distro_rauc_slot *slot; + + slot = get_slot(priv, boot_order_list[i]); + if (!slot) + return log_msg_ret("env", -ENOENT); + ret = fs_set_blk_dev_with_part(desc, slot->boot_part); + if (ret) + return log_msg_ret("blk", ret); + exists |= fs_exists(script_names[j]); + } + if (!exists) + return log_msg_ret("fs", -ENOENT); + } + str_free_list(boot_order_list); + + return 0; +} + +static int distro_rauc_read_bootflow(struct udevice *dev, struct bootflow *bflow) +{ + struct distro_rauc_priv *priv; + int ret; + char *slot; + int i; + char *partitions; + char *boot_order; + const char *default_boot_order; + const char **default_boot_order_list; + char *boot_order_copy; + char boot_left[BOOT_LEFT_LEN]; + char *parts; + + /* Get RAUC variables or set their default values */ + boot_order = env_get("BOOT_ORDER"); + if (!boot_order) { + log_debug("BOOT_ORDER did not exist yet, setting default value\n"); + if (env_set("BOOT_ORDER", CONFIG_BOOTMETH_RAUC_BOOT_ORDER)) + return log_msg_ret("env", -EPERM); + boot_order = CONFIG_BOOTMETH_RAUC_BOOT_ORDER; + } + default_boot_order = CONFIG_BOOTMETH_RAUC_BOOT_ORDER; + default_boot_order_list = str_to_list(default_boot_order); + for (i = 0; default_boot_order_list[i]; i++) { + sprintf(boot_left, "BOOT_%s_LEFT", default_boot_order_list[i]); + if (!env_get(boot_left)) { + log_debug("%s did not exist yet, setting default value\n", + boot_left); + if (env_set_ulong(boot_left, CONFIG_BOOTMETH_RAUC_DEFAULT_TRIES)) + return log_msg_ret("env", -EPERM); + } + } + str_free_list(default_boot_order_list); + + priv = calloc(1, sizeof(struct distro_rauc_priv)); + if (!priv) + return log_msg_ret("buf", -ENOMEM); + priv->slots = calloc(1, sizeof(struct distro_rauc_slot)); + + /* Copy default boot_order, so we can leave the original unmodified */ + boot_order_copy = strdup(default_boot_order); + partitions = strdup(CONFIG_BOOTMETH_RAUC_PARTITIONS); + + for (i = 1; + (parts = strsep(&partitions, " ")) && + (slot = strsep(&boot_order_copy, " ")); + i++) { + struct distro_rauc_slot *s; + + s = calloc(1, sizeof(struct distro_rauc_slot)); + s->name = strdup(slot); + s->boot_part = simple_strtoul(strsep(&parts, ","), NULL, 10); + s->root_part = simple_strtoul(strsep(&parts, ","), NULL, 10); + priv->slots = realloc(priv->slots, (i + 1) * + sizeof(struct distro_rauc_slot)); + priv->slots[i - 1] = s; + priv->slots[i]->name = NULL; + } + + bflow->bootmeth_priv = priv; + + ret = distro_rauc_scan_boot_part(bflow); + if (ret < 0) { + for (i = 0; priv->slots[i]->name; i++) { + free(priv->slots[i]->name); + free(priv->slots[i]); + } + free(priv); + free(boot_order_copy); + bflow->bootmeth_priv = NULL; + return ret; + } + + bflow->state = BOOTFLOWST_READY; + + return 0; +} + +static int distro_rauc_read_file(struct udevice *dev, struct bootflow *bflow, + const char *file_path, ulong addr, + enum bootflow_img_t type, ulong *sizep) +{ + /* + * Reading individual files is not supported since we only operate on + * whole MMC devices (because we require multiple partitions). + */ + return log_msg_ret("Unsupported", -ENOSYS); +} + +static int distro_rauc_load_boot_script(struct bootflow *bflow, + const struct distro_rauc_slot *slot) +{ + struct blk_desc *desc; + struct distro_rauc_priv *priv; + struct udevice *bootstd; + const char *const *prefixes; + int ret; + int i; + int j; + + ret = uclass_first_device_err(UCLASS_BOOTSTD, &bootstd); + if (ret) + return log_msg_ret("std", ret); + prefixes = bootstd_get_prefixes(bootstd); + + desc = dev_get_uclass_plat(bflow->blk); + priv = bflow->bootmeth_priv; + if (!priv || !priv->slots) + return log_msg_ret("priv", -EINVAL); + + bflow->part = slot->boot_part; + if (!bflow->part) + return log_msg_ret("part", -ENOENT); + + ret = bootmeth_setup_fs(bflow, desc); + if (ret) + return log_msg_ret("set", ret); + + for (i = 0; prefixes[i] && bflow->state != BOOTFLOWST_FILE; i++) { + for (j = 0; script_names[j] && bflow->state != BOOTFLOWST_FILE; j++) { + if (!bootmeth_try_file(bflow, desc, prefixes[i], script_names[j])) { + log_debug("Found file '%s%s' in %s.part_%x\n", + prefixes[i], script_names[j], + bflow->dev->name, bflow->part); + bflow->subdir = strdup(prefixes[i]); + } + } + } + if (bflow->state != BOOTFLOWST_FILE) + return log_msg_ret("file", -ENOENT); + + ret = bootmeth_alloc_file(bflow, 0x10000, ARCH_DMA_MINALIGN, + (enum bootflow_img_t)IH_TYPE_SCRIPT); + if (ret) + return log_msg_ret("read", ret); + + return 0; +} + +static int find_active_slot(char **slot_name, ulong *slot_tries) +{ + ulong tries; + char boot_left[BOOT_LEFT_LEN]; + char *boot_order; + const char **boot_order_list; + bool slot_found = false; + int ret; + int i; + + boot_order = env_get("BOOT_ORDER"); + if (!boot_order) + return log_msg_ret("env", -ENOENT); + boot_order_list = str_to_list(boot_order); + for (i = 0; boot_order_list[i] && !slot_found; i++) { + sprintf(boot_left, "BOOT_%s_LEFT", boot_order_list[i]); + tries = env_get_ulong(boot_left, 10, ULONG_MAX); + if (tries == ULONG_MAX) + return log_msg_ret("env", -ENOENT); + + if (tries) { + ret = env_set_ulong(boot_left, tries - 1); + if (ret) + return log_msg_ret("env", ret); + *slot_name = strdup(boot_order_list[i]); + *slot_tries = tries; + slot_found = true; + } + } + str_free_list(boot_order_list); + + if (!slot_found) { + if (IS_ENABLED(CONFIG_BOOTMETH_RAUC_RESET_ALL_ZERO_TRIES)) { + log_warning("WARNING: No valid slot found\n"); + log_info("INFO: Resetting boot order and all slot tries\n"); + boot_order_list = str_to_list(CONFIG_BOOTMETH_RAUC_BOOT_ORDER); + for (i = 0; boot_order_list[i]; i++) { + sprintf(boot_left, "BOOT_%s_LEFT", boot_order_list[i]); + ret = env_set_ulong(boot_left, CONFIG_BOOTMETH_RAUC_DEFAULT_TRIES); + if (ret) + return log_msg_ret("env", ret); + } + str_free_list(boot_order_list); + ret = env_save(); + if (ret) + return log_msg_ret("env", ret); + do_reset(NULL, 0, 0, NULL); + } + log_err("ERROR: No valid slot found\n"); + return -EINVAL; + } + + return 0; +} + +static int distro_rauc_boot(struct udevice *dev, struct bootflow *bflow) +{ + struct blk_desc *desc; + struct distro_rauc_priv *priv; + const struct distro_rauc_slot *slot; + char *boot_order; + const char **boot_order_list; + char *active_slot; + ulong active_slot_tries; + char raucargs[64]; + char boot_left[BOOT_LEFT_LEN]; + ulong addr; + int ret = 0; + int i; + + desc = dev_get_uclass_plat(bflow->blk); + if (desc->uclass_id != UCLASS_MMC) + return log_msg_ret("blk", -EINVAL); + priv = bflow->bootmeth_priv; + + /* Device info variables */ + ret = env_set("devtype", blk_get_devtype(bflow->blk)); + if (ret) + return log_msg_ret("env", ret); + + ret = env_set_hex("devnum", desc->devnum); + if (ret) + return log_msg_ret("env", ret); + + /* Find active, valid slot */ + ret = find_active_slot(&active_slot, &active_slot_tries); + if (ret) + return log_msg_ret("env", ret); + + /* Kernel command line arguments */ + sprintf(raucargs, "rauc.slot=%s", active_slot); + ret = env_set("raucargs", raucargs); + if (ret) + return log_msg_ret("env", ret); + + /* Active slot info */ + slot = get_slot(priv, active_slot); + if (!slot) + return log_msg_ret("env", -ENOENT); + ret = env_set_hex("distro_bootpart", slot->boot_part); + if (ret) + return log_msg_ret("env", ret); + ret = env_set_hex("distro_rootpart", slot->root_part); + if (ret) + return log_msg_ret("env", ret); + ret = env_save(); + if (ret) + return log_msg_ret("env", ret); + + /* Load distro boot script */ + ret = distro_rauc_load_boot_script(bflow, slot); + if (ret) + return log_msg_ret("load", ret); + + log_info("INFO: Booting slot %s, %lu of %d tries left\n", + active_slot, active_slot_tries, CONFIG_BOOTMETH_RAUC_DEFAULT_TRIES); + + log_debug("devtype: %s\n", env_get("devtype")); + log_debug("devnum: %s\n", env_get("devnum")); + log_debug("distro_bootpart: %s\n", env_get("distro_bootpart")); + log_debug("distro_rootpart: %s\n", env_get("distro_rootpart")); + log_debug("raucargs: %s\n", env_get("raucargs")); + boot_order = env_get("BOOT_ORDER"); + if (!boot_order) + return log_msg_ret("env", -EPERM); + log_debug("BOOT_ORDER: %s\n", boot_order); + boot_order_list = str_to_list(boot_order); + for (i = 0; boot_order_list[i]; i++) { + sprintf(boot_left, "BOOT_%s_LEFT", boot_order_list[i]); + log_debug("%s: %s\n", boot_left, env_get(boot_left)); + } + str_free_list(boot_order_list); + + /* Run distro boot script */ + addr = map_to_sysmem(bflow->buf); + ret = cmd_source_script(addr, NULL, NULL); + if (ret) + return log_msg_ret("boot", ret); + + return 0; +} + +static int distro_rauc_bootmeth_bind(struct udevice *dev) +{ + struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev); + + plat->desc = "RAUC distro boot from MMC"; + plat->flags = BOOTMETHF_GLOBAL; + + return 0; +} + +static struct bootmeth_ops distro_rauc_bootmeth_ops = { + .check = distro_rauc_check, + .read_bootflow = distro_rauc_read_bootflow, + .read_file = distro_rauc_read_file, + .boot = distro_rauc_boot, +}; + +static const struct udevice_id distro_rauc_bootmeth_ids[] = { + { .compatible = "u-boot,distro-rauc" }, + { } +}; + +U_BOOT_DRIVER(bootmeth_rauc) = { + .name = "bootmeth_rauc", + .id = UCLASS_BOOTMETH, + .of_match = distro_rauc_bootmeth_ids, + .ops = &distro_rauc_bootmeth_ops, + .bind = distro_rauc_bootmeth_bind, +}; diff --git a/boot/cedit.c b/boot/cedit.c index d69290c172e..56dc7c6af15 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -81,6 +81,8 @@ int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: scene_obj_set_pos(scn, obj->id, 50, y); @@ -100,19 +102,16 @@ int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id) return 0; } -int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, +int cedit_prepare(struct expo *exp, struct udevice *vid_dev, struct scene **scnp) { + struct udevice *dev = vid_dev; struct video_priv *vid_priv; - struct udevice *dev; struct scene *scn; uint scene_id; int ret; /* For now we only support a video console */ - ret = uclass_first_device_err(UCLASS_VIDEO, &dev); - if (ret) - return log_msg_ret("vid", ret); ret = expo_set_display(exp, dev); if (ret) return log_msg_ret("dis", ret); @@ -127,6 +126,7 @@ int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, return log_msg_ret("sid", ret); exp->popup = true; + exp->show_highlight = true; /* This is not supported for now */ if (0) @@ -143,104 +143,96 @@ int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, if (ret) return log_msg_ret("dim", ret); - *vid_privp = vid_priv; *scnp = scn; return scene_id; } -int cedit_run(struct expo *exp) +int cedit_do_action(struct expo *exp, struct scene *scn, + struct video_priv *vid_priv, struct expo_action *act) { - struct cli_ch_state s_cch, *cch = &s_cch; - struct video_priv *vid_priv; - uint scene_id; - struct scene *scn; - bool done, save; int ret; - cli_ch_init(cch); - ret = cedit_prepare(exp, &vid_priv, &scn); + switch (act->type) { + case EXPOACT_NONE: + return -EAGAIN; + case EXPOACT_POINT_ITEM: + ret = scene_menu_select_item(scn, scn->highlight_id, + act->select.id); + if (ret) + return log_msg_ret("cdp", ret); + break; + case EXPOACT_POINT_OBJ: + scene_set_highlight_id(scn, act->select.id); + cedit_arange(exp, vid_priv, scn->id); + break; + case EXPOACT_OPEN: + scene_set_open(scn, act->select.id, true); + cedit_arange(exp, vid_priv, scn->id); + switch (scn->highlight_id) { + case EXPOID_SAVE: + exp->done = true; + exp->save = true; + break; + case EXPOID_DISCARD: + exp->done = true; + break; + } + break; + case EXPOACT_CLOSE: + scene_set_open(scn, act->select.id, false); + cedit_arange(exp, vid_priv, scn->id); + break; + case EXPOACT_SELECT: + scene_set_open(scn, scn->highlight_id, false); + cedit_arange(exp, vid_priv, scn->id); + break; + case EXPOACT_QUIT: + log_debug("quitting\n"); + exp->done = true; + break; + } + + return 0; +} + +int cedit_run(struct expo *exp) +{ + struct video_priv *vid_priv; + struct udevice *dev; + struct scene *scn; + uint scene_id; + int ret; + + ret = uclass_first_device_err(UCLASS_VIDEO, &dev); + if (ret) + return log_msg_ret("vid", ret); + vid_priv = dev_get_uclass_priv(dev); + + ret = cedit_prepare(exp, dev, &scn); if (ret < 0) return log_msg_ret("prep", ret); scene_id = ret; - done = false; - save = false; + exp->done = false; + exp->save = false; do { struct expo_action act; - int ichar, key; ret = expo_render(exp); if (ret) - break; + return log_msg_ret("cer", ret); - ichar = cli_ch_process(cch, 0); - if (!ichar) { - while (!ichar && !tstc()) { - schedule(); - mdelay(2); - ichar = cli_ch_process(cch, -ETIMEDOUT); - } - if (!ichar) { - ichar = getchar(); - ichar = cli_ch_process(cch, ichar); - } - } - - key = 0; - if (ichar) { - key = bootmenu_conv_key(ichar); - if (key == BKEY_NONE || key >= BKEY_FIRST_EXTRA) - key = ichar; - } - if (!key) - continue; - - ret = expo_send_key(exp, key); - if (ret) - break; - - ret = expo_action_get(exp, &act); - if (!ret) { - switch (act.type) { - case EXPOACT_POINT_OBJ: - scene_set_highlight_id(scn, act.select.id); - cedit_arange(exp, vid_priv, scene_id); - break; - case EXPOACT_OPEN: - scene_set_open(scn, act.select.id, true); - cedit_arange(exp, vid_priv, scene_id); - switch (scn->highlight_id) { - case EXPOID_SAVE: - done = true; - save = true; - break; - case EXPOID_DISCARD: - done = true; - break; - } - break; - case EXPOACT_CLOSE: - scene_set_open(scn, act.select.id, false); - cedit_arange(exp, vid_priv, scene_id); - break; - case EXPOACT_SELECT: - scene_set_open(scn, scn->highlight_id, false); - cedit_arange(exp, vid_priv, scene_id); - break; - case EXPOACT_QUIT: - log_debug("quitting\n"); - done = true; - break; - default: - break; - } - } - } while (!done); + ret = expo_poll(exp, &act); + if (!ret) + cedit_do_action(exp, scn, vid_priv, &act); + else if (ret != -EAGAIN) + return log_msg_ret("cep", ret); + } while (!exp->done); if (ret) return log_msg_ret("end", ret); - if (!save) + if (!exp->save) return -EACCES; return 0; @@ -286,7 +278,7 @@ static int get_cur_menuitem_text(const struct scene_obj_menu *menu, if (!txt) return log_msg_ret("txt", -ENOENT); - str = expo_get_str(scn->expo, txt->str_id); + str = expo_get_str(scn->expo, txt->gen.str_id); if (!str) return log_msg_ret("str", -ENOENT); *strp = str; @@ -396,6 +388,8 @@ static int h_write_settings(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_TEXTLINE: { const struct scene_obj_textline *tline; @@ -449,8 +443,7 @@ int cedit_write_settings(struct expo *exp, struct abuf *buf) void *fdt; int ret; - abuf_init(buf); - if (!abuf_realloc(buf, CEDIT_SIZE_INC)) + if (!abuf_init_size(buf, CEDIT_SIZE_INC)) return log_msg_ret("buf", -ENOMEM); fdt = abuf_data(buf); @@ -496,6 +489,8 @@ static int h_read_settings(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_TEXTLINE: { const struct scene_obj_textline *tline; @@ -567,6 +562,8 @@ static int h_write_settings_env(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: menu = (struct scene_obj_menu *)obj; @@ -650,6 +647,8 @@ static int h_read_settings_env(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: menu = (struct scene_obj_menu *)obj; diff --git a/boot/expo.c b/boot/expo.c index 8ce645e5a8f..94413acd381 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -10,8 +10,12 @@ #include #include +#include #include +#include #include +#include +#include #include "scene_internal.h" int expo_new(const char *name, void *priv, struct expo **expp) @@ -30,6 +34,7 @@ int expo_new(const char *name, void *priv, struct expo **expp) INIT_LIST_HEAD(&exp->scene_head); INIT_LIST_HEAD(&exp->str_head); exp->next_id = EXPOID_BASE_ID; + cli_ch_init(&exp->cch); *expp = exp; @@ -81,7 +86,7 @@ int expo_str(struct expo *exp, const char *name, uint id, const char *str) return log_msg_ret("obj", -ENOMEM); estr->id = resolve_id(exp, id); - estr->str = str; + abuf_init_const(&estr->buf, str, strlen(str) + 1); list_add_tail(&estr->sibling, &exp->str_head); return estr->id; @@ -93,12 +98,33 @@ const char *expo_get_str(struct expo *exp, uint id) list_for_each_entry(estr, &exp->str_head, sibling) { if (estr->id == id) - return estr->str; + return estr->buf.data; } return NULL; } +int expo_edit_str(struct expo *exp, uint id, struct abuf *orig, + struct abuf **copyp) +{ + struct expo_string *estr; + struct abuf old; + + list_for_each_entry(estr, &exp->str_head, sibling) { + if (estr->id == id) { + old = estr->buf; + if (!abuf_copy(&old, &estr->buf)) + return -ENOMEM; + *copyp = &estr->buf; + if (orig) + *orig = old; + return 0; + } + } + + return -ENOENT; +} + int expo_set_display(struct expo *exp, struct udevice *dev) { struct udevice *cons; @@ -251,6 +277,7 @@ int expo_apply_theme(struct expo *exp, ofnode node) { struct scene *scn; struct expo_theme *theme = &exp->theme; + bool white_on_black; int ret; log_debug("Applying theme %s\n", ofnode_get_name(node)); @@ -261,6 +288,9 @@ int expo_apply_theme(struct expo *exp, ofnode node) ofnode_read_u32(node, "menuitem-gap-y", &theme->menuitem_gap_y); ofnode_read_u32(node, "menu-title-margin-x", &theme->menu_title_margin_x); + white_on_black = ofnode_read_bool(node, "white-on-black"); + if (exp->display) + video_set_white_on_black(exp->display, white_on_black); list_for_each_entry(scn, &exp->scene_head, sibling) { ret = scene_apply_theme(scn, theme); @@ -285,3 +315,41 @@ int expo_iter_scene_objs(struct expo *exp, expo_scene_obj_iterator iter, return 0; } + +int expo_poll(struct expo *exp, struct expo_action *act) +{ + int ichar, key, ret; + + ichar = cli_ch_process(&exp->cch, 0); + if (!ichar) { + int i; + + for (i = 0; i < 10 && !ichar && !tstc(); i++) { + schedule(); + mdelay(2); + ichar = cli_ch_process(&exp->cch, -ETIMEDOUT); + } + while (!ichar && tstc()) { + ichar = getchar(); + ichar = cli_ch_process(&exp->cch, ichar); + } + } + + key = 0; + if (ichar) { + key = bootmenu_conv_key(ichar); + if (key == BKEY_NONE || key >= BKEY_FIRST_EXTRA) + key = ichar; + } + if (!key) + return -EAGAIN; + + ret = expo_send_key(exp, key); + if (ret) + return log_msg_ret("epk", ret); + ret = expo_action_get(exp, act); + if (ret) + return log_msg_ret("eag", ret); + + return 0; +} diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 92f2f534ee0..b7331bb76b3 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -224,15 +224,24 @@ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end) int is_u64; uint64_t addr, size; - /* just return if the size of initrd is zero */ - if (initrd_start == initrd_end) - return 0; - /* find or create "/chosen" node. */ nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen"); if (nodeoffset < 0) return nodeoffset; + /* + * Although we didn't setup an initrd, there could be a stale + * initrd setting from the previous boot firmware in the live + * device tree. So, make sure there is no setting left if we + * don't want an initrd. + */ + if (initrd_start == initrd_end) { + fdt_delprop(fdt, nodeoffset, "linux,initrd-start"); + fdt_delprop(fdt, nodeoffset, "linux,initrd-end"); + + return 0; + } + total = fdt_num_mem_rsv(fdt); /* diff --git a/boot/image-android.c b/boot/image-android.c index 459cdb8456c..1cd2060bb3f 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -268,7 +268,8 @@ static ulong android_image_get_kernel_addr(struct andr_image_data *img_data, * * Otherwise, we will return the actual value set by the user. */ - if (img_data->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR) { + if (img_data->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR || + IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR)) { if (comp == IH_COMP_NONE) return img_data->kernel_ptr; return env_get_ulong("kernel_addr_r", 16, 0); @@ -464,7 +465,8 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, */ if (img_data.header_version > 2) { /* Ramdisk can't be used in-place, copy it to ramdisk_addr_r */ - if (img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR) { + if (img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR || + IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR)) { ramdisk_ptr = env_get_ulong("ramdisk_addr_r", 16, 0); if (!ramdisk_ptr) { printf("Invalid ramdisk_addr_r to copy ramdisk into\n"); @@ -489,7 +491,8 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, /* Ramdisk can be used in-place, use current ptr */ if (img_data.ramdisk_addr == 0 || img_data.ramdisk_addr == ANDROID_IMAGE_DEFAULT_RAMDISK_ADDR || - img_data.ramdisk_addr == img_data.kernel_addr) { + img_data.ramdisk_addr == img_data.kernel_addr || + IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR)) { *rd_data = img_data.ramdisk_ptr; } else { ramdisk_ptr = img_data.ramdisk_addr; @@ -677,7 +680,7 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, { struct andr_image_data img_data; const struct andr_boot_img_hdr_v0 *hdr; - const struct andr_vnd_boot_img_hdr *vhdr; + const struct andr_vnd_boot_img_hdr *vhdr = NULL; hdr = map_sysmem(hdr_addr, sizeof(*hdr)); if (vendor_boot_img != -1) diff --git a/boot/image-board.c b/boot/image-board.c index 514f8e63f9c..005d60caf5c 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -538,6 +539,7 @@ int boot_get_ramdisk(char const *select, struct bootm_headers *images, int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, ulong *initrd_end) { + int err; char *s; phys_addr_t initrd_high; int initrd_copy_to_ram = 1; @@ -559,25 +561,30 @@ int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, if (rd_data) { if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + phys_addr_t initrd_addr; + debug(" in-place initrd\n"); *initrd_start = rd_data; *initrd_end = rd_data + rd_len; - lmb_reserve(rd_data, rd_len, LMB_NONE); + initrd_addr = (phys_addr_t)rd_data; + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &initrd_addr, + rd_len, LMB_NONE); + if (err) { + puts("in-place initrd alloc failed\n"); + goto error; + } } else { - if (initrd_high) - *initrd_start = - (ulong)lmb_alloc_base(rd_len, - 0x1000, - initrd_high, - LMB_NONE); - else - *initrd_start = (ulong)lmb_alloc(rd_len, - 0x1000); + enum lmb_mem_type type = initrd_high ? + LMB_MEM_ALLOC_MAX : LMB_MEM_ALLOC_ANY; - if (*initrd_start == 0) { + err = lmb_alloc_mem(type, 0x1000, &initrd_high, rd_len, + LMB_NONE); + if (err) { puts("ramdisk - allocation error\n"); goto error; } + + *initrd_start = (ulong)initrd_high; bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK); *initrd_end = *initrd_start + rd_len; @@ -828,9 +835,10 @@ int boot_get_loadable(struct bootm_headers *images) */ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) { - int barg; + int barg, err; char *cmdline; char *s; + phys_addr_t addr; /* * Help the compiler detect that this function is only called when @@ -840,12 +848,14 @@ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) return 0; barg = IF_ENABLED_INT(CONFIG_SYS_BOOT_GET_CMDLINE, CONFIG_SYS_BARGSIZE); - cmdline = (char *)(ulong)lmb_alloc_base(barg, 0xf, - env_get_bootm_mapsize() + env_get_bootm_low(), - LMB_NONE); - if (!cmdline) + addr = env_get_bootm_mapsize() + env_get_bootm_low(); + + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, 0xf, &addr, barg, LMB_NONE); + if (err) return -1; + cmdline = (char *)(uintptr_t)addr; + s = env_get("bootargs"); if (!s) s = ""; @@ -874,14 +884,16 @@ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) */ int boot_get_kbd(struct bd_info **kbd) { - *kbd = (struct bd_info *)(ulong)lmb_alloc_base(sizeof(struct bd_info), - 0xf, - env_get_bootm_mapsize() + - env_get_bootm_low(), - LMB_NONE); - if (!*kbd) + int err; + phys_addr_t addr; + + addr = env_get_bootm_mapsize() + env_get_bootm_low(); + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, 0xf, &addr, + sizeof(struct bd_info), LMB_NONE); + if (err) return -1; + *kbd = (struct bd_info *)(uintptr_t)addr; **kbd = *gd->bd; debug("## kernel board info at 0x%08lx\n", (ulong)*kbd); diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 8f718ad29f6..97b6385ab7c 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -72,13 +72,15 @@ static const struct legacy_img_hdr *image_get_fdt(ulong fdt_addr) static void boot_fdt_reserve_region(u64 addr, u64 size, u32 flags) { long ret; + phys_addr_t rsv_addr; - ret = lmb_reserve(addr, size, flags); + rsv_addr = (phys_addr_t)addr; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &rsv_addr, size, flags); if (!ret) { debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", (unsigned long long)addr, (unsigned long long)size, flags); - } else if (ret != -EEXIST) { + } else if (ret != -EEXIST && ret != -EINVAL) { puts("ERROR: reserving fdt memory region failed "); printf("(addr=%llx size=%llx flags=%x)\n", (unsigned long long)addr, @@ -155,7 +157,7 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) */ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) { - u64 start, size, usable, addr, low, mapsize; + u64 start, size, usable, low, mapsize; void *fdt_blob = *of_flat_tree; void *of_start = NULL; char *fdt_high; @@ -163,6 +165,7 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) int bank; int err; int disable_relocation = 0; + phys_addr_t addr; /* nothing to do */ if (*of_size == 0) @@ -180,23 +183,32 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) /* If fdt_high is set use it to select the relocation address */ fdt_high = env_get("fdt_high"); if (fdt_high) { - ulong desired_addr = hextoul(fdt_high, NULL); + ulong high_addr = hextoul(fdt_high, NULL); - if (desired_addr == ~0UL) { + if (high_addr == ~0UL) { /* All ones means use fdt in place */ of_start = fdt_blob; - lmb_reserve(map_to_sysmem(of_start), of_len, LMB_NONE); - disable_relocation = 1; - } else if (desired_addr) { - addr = lmb_alloc_base(of_len, 0x1000, desired_addr, - LMB_NONE); - of_start = map_sysmem(addr, of_len); - if (of_start == NULL) { - puts("Failed using fdt_high value for Device Tree"); + addr = map_to_sysmem(fdt_blob); + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, + of_len, LMB_NONE); + if (err) { + printf("Failed to reserve memory for fdt at %#llx\n", + (u64)addr); goto error; } + + disable_relocation = 1; } else { - addr = lmb_alloc(of_len, 0x1000); + enum lmb_mem_type type = high_addr ? + LMB_MEM_ALLOC_MAX : LMB_MEM_ALLOC_ANY; + + addr = high_addr; + err = lmb_alloc_mem(type, 0x1000, &addr, of_len, + LMB_NONE); + if (err) { + puts("Failed to allocate memory for Device Tree relocation\n"); + goto error; + } of_start = map_sysmem(addr, of_len); } } else { @@ -218,11 +230,15 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) * for LMB allocation. */ usable = min(start + size, low + mapsize); - addr = lmb_alloc_base(of_len, 0x1000, usable, LMB_NONE); - of_start = map_sysmem(addr, of_len); - /* Allocation succeeded, use this block. */ - if (of_start != NULL) - break; + addr = usable; + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, 0x1000, + &addr, of_len, LMB_NONE); + if (!err) { + of_start = map_sysmem(addr, of_len); + /* Allocation succeeded, use this block. */ + if (of_start) + break; + } /* * Reduce the mapping size in the next bank @@ -674,7 +690,7 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb) /* Delete the old LMB reservation */ if (CONFIG_IS_ENABLED(LMB) && lmb) - lmb_free(map_to_sysmem(blob), fdt_totalsize(blob)); + lmb_free(map_to_sysmem(blob), fdt_totalsize(blob), LMB_NONE); ret = fdt_shrink_to_minimum(blob, 0); if (ret < 0) @@ -682,8 +698,17 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb) of_size = ret; /* Create a new LMB reservation */ - if (CONFIG_IS_ENABLED(LMB) && lmb) - lmb_reserve(map_to_sysmem(blob), of_size, LMB_NONE); + if (CONFIG_IS_ENABLED(LMB) && lmb) { + phys_addr_t fdt_addr; + + fdt_addr = map_to_sysmem(blob); + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &fdt_addr, + of_size, LMB_NONE); + if (ret) { + printf("Failed to reserve memory for the fdt at %#llx\n", + (u64)fdt_addr); + } + } #if defined(CONFIG_ARCH_KEYSTONE) if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c index adf3b341a20..2f851ebb28c 100644 --- a/boot/image-pre-load.c +++ b/boot/image-pre-load.c @@ -7,6 +7,7 @@ #include "mkimage.h" #else #include +#include #include DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ diff --git a/boot/image.c b/boot/image.c index 139c5bd035a..abac2c7034b 100644 --- a/boot/image.c +++ b/boot/image.c @@ -184,6 +184,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" }, { IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" }, { IH_TYPE_TFA_BL31, "tfa-bl31", "TFA BL31 Image", }, + { IH_TYPE_STM32IMAGE_V2, "stm32imagev2", "STMicroelectronics STM32 Image V2.0" }, { -1, "", "", }, }; diff --git a/boot/scene.c b/boot/scene.c index fb82ffe768c..fa8f540bfb0 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include #include @@ -31,8 +32,7 @@ int scene_new(struct expo *exp, const char *name, uint id, struct scene **scnp) return log_msg_ret("name", -ENOMEM); } - abuf_init(&scn->buf); - if (!abuf_realloc(&scn->buf, EXPO_MAX_CHARS + 1)) { + if (!abuf_init_size(&scn->buf, EXPO_MAX_CHARS + 1)) { free(scn->name); free(scn); return log_msg_ret("buf", -ENOMEM); @@ -143,6 +143,32 @@ int scene_img(struct scene *scn, const char *name, uint id, char *data, return img->obj.id; } +int scene_txt_generic_init(struct expo *exp, struct scene_txt_generic *gen, + const char *name, uint str_id, const char *str) +{ + int ret; + + if (str) { + ret = expo_str(exp, name, str_id, str); + if (ret < 0) + return log_msg_ret("str", ret); + if (str_id && ret != str_id) + return log_msg_ret("id", -EEXIST); + str_id = ret; + } else { + ret = resolve_id(exp, str_id); + if (ret < 0) + return log_msg_ret("nst", ret); + if (str_id && ret != str_id) + return log_msg_ret("nid", -EEXIST); + } + + gen->str_id = str_id; + alist_init_struct(&gen->lines, struct vidconsole_mline); + + return 0; +} + int scene_txt(struct scene *scn, const char *name, uint id, uint str_id, struct scene_obj_txt **txtp) { @@ -155,8 +181,9 @@ int scene_txt(struct scene *scn, const char *name, uint id, uint str_id, if (ret < 0) return log_msg_ret("obj", ret); - txt->str_id = str_id; - + ret = scene_txt_generic_init(scn->expo, &txt->gen, name, str_id, NULL); + if (ret) + return log_msg_ret("stg", ret); if (txtp) *txtp = txt; @@ -169,27 +196,41 @@ int scene_txt_str(struct scene *scn, const char *name, uint id, uint str_id, struct scene_obj_txt *txt; int ret; - ret = expo_str(scn->expo, name, str_id, str); - if (ret < 0) - return log_msg_ret("str", ret); - if (str_id && ret != str_id) - return log_msg_ret("id", -EEXIST); - str_id = ret; - ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXT, sizeof(struct scene_obj_txt), (struct scene_obj **)&txt); if (ret < 0) return log_msg_ret("obj", ret); - txt->str_id = str_id; - + ret = scene_txt_generic_init(scn->expo, &txt->gen, name, str_id, str); + if (ret) + return log_msg_ret("tsg", ret); if (txtp) *txtp = txt; return txt->obj.id; } +int scene_box(struct scene *scn, const char *name, uint id, uint width, + struct scene_obj_box **boxp) +{ + struct scene_obj_box *box; + int ret; + + ret = scene_obj_add(scn, name, id, SCENEOBJT_BOX, + sizeof(struct scene_obj_box), + (struct scene_obj **)&box); + if (ret < 0) + return log_msg_ret("obj", ret); + + box->width = width; + + if (boxp) + *boxp = box; + + return box->obj.id; +} + int scene_txt_set_font(struct scene *scn, uint id, const char *font_name, uint font_size) { @@ -198,8 +239,8 @@ int scene_txt_set_font(struct scene *scn, uint id, const char *font_name, txt = scene_obj_find(scn, id, SCENEOBJT_TEXT); if (!txt) return log_msg_ret("find", -ENOENT); - txt->font_name = font_name; - txt->font_size = font_size; + txt->gen.font_name = font_name; + txt->gen.font_size = font_size; return 0; } @@ -207,12 +248,17 @@ int scene_txt_set_font(struct scene *scn, uint id, const char *font_name, int scene_obj_set_pos(struct scene *scn, uint id, int x, int y) { struct scene_obj *obj; + int w, h; obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("find", -ENOENT); - obj->dim.x = x; - obj->dim.y = y; + w = obj->bbox.x1 - obj->bbox.x0; + h = obj->bbox.y1 - obj->bbox.y0; + obj->bbox.x0 = x; + obj->bbox.y0 = y; + obj->bbox.x1 = obj->bbox.x0 + w; + obj->bbox.y1 = obj->bbox.y0 + h; return 0; } @@ -224,8 +270,62 @@ int scene_obj_set_size(struct scene *scn, uint id, int w, int h) obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("find", -ENOENT); - obj->dim.w = w; - obj->dim.h = h; + obj->bbox.x1 = obj->bbox.x0 + w; + obj->bbox.y1 = obj->bbox.y0 + h; + obj->flags |= SCENEOF_SIZE_VALID; + + return 0; +} + +int scene_obj_set_width(struct scene *scn, uint id, int w) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("find", -ENOENT); + obj->bbox.x1 = obj->bbox.x0 + w; + + return 0; +} + +int scene_obj_set_bbox(struct scene *scn, uint id, int x0, int y0, int x1, + int y1) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("find", -ENOENT); + obj->bbox.x0 = x0; + obj->bbox.y0 = y0; + obj->bbox.x1 = x1; + obj->bbox.y1 = y1; + obj->flags |= SCENEOF_SIZE_VALID; + + return 0; +} + +int scene_obj_set_halign(struct scene *scn, uint id, enum scene_obj_align aln) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("osh", -ENOENT); + obj->horiz = aln; + + return 0; +} + +int scene_obj_set_valign(struct scene *scn, uint id, enum scene_obj_align aln) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("osv", -ENOENT); + obj->vert = aln; return 0; } @@ -255,6 +355,49 @@ int scene_obj_flag_clrset(struct scene *scn, uint id, uint clr, uint set) return 0; } +static void handle_alignment(enum scene_obj_align horiz, + enum scene_obj_align vert, + struct scene_obj_bbox *bbox, + struct scene_obj_dims *dims, + int xsize, int ysize, + struct scene_obj_offset *offset) +{ + int width, height; + + if (bbox->x1 == SCENEOB_DISPLAY_MAX) + bbox->x1 = xsize ?: 1280; + if (bbox->y1 == SCENEOB_DISPLAY_MAX) + bbox->y1 = ysize ?: 1024; + + width = bbox->x1 - bbox->x0; + height = bbox->y1 - bbox->y0; + + switch (horiz) { + case SCENEOA_CENTRE: + offset->xofs = (width - dims->x) / 2; + break; + case SCENEOA_RIGHT: + offset->xofs = width - dims->x; + break; + case SCENEOA_LEFT: + offset->xofs = 0; + break; + } + + switch (vert) { + case SCENEOA_CENTRE: + offset->yofs = (height - dims->y) / 2; + break; + case SCENEOA_BOTTOM: + offset->yofs = height - dims->y; + break; + case SCENEOA_TOP: + default: + offset->yofs = 0; + break; + } +} + int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) { struct scene_obj *obj; @@ -267,6 +410,7 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) case SCENEOBJT_NONE: case SCENEOBJT_MENU: case SCENEOBJT_TEXTLINE: + case SCENEOBJT_BOX: break; case SCENEOBJT_IMAGE: { struct scene_obj_img *img = (struct scene_obj_img *)obj; @@ -278,14 +422,20 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) *widthp = width; return height; } - case SCENEOBJT_TEXT: { - struct scene_obj_txt *txt = (struct scene_obj_txt *)obj; + case SCENEOBJT_TEXT: + case SCENEOBJT_TEXTEDIT: { + struct scene_txt_generic *gen; struct expo *exp = scn->expo; struct vidconsole_bbox bbox; + int len, ret, limit; const char *str; - int len, ret; - str = expo_get_str(exp, txt->str_id); + if (obj->type == SCENEOBJT_TEXT) + gen = &((struct scene_obj_txt *)obj)->gen; + else + gen = &((struct scene_obj_txtedit *)obj)->gen; + + str = expo_get_str(exp, gen->str_id); if (!str) return log_msg_ret("str", -ENOENT); len = strlen(str); @@ -297,8 +447,12 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) return 16; } - ret = vidconsole_measure(scn->expo->cons, txt->font_name, - txt->font_size, str, -1, &bbox, NULL); + limit = obj->flags & SCENEOF_SIZE_VALID ? + obj->bbox.x1 - obj->bbox.x0 : -1; + + ret = vidconsole_measure(scn->expo->cons, gen->font_name, + gen->font_size, str, limit, &bbox, + &gen->lines); if (ret) return log_msg_ret("mea", ret); if (widthp) @@ -317,12 +471,14 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) * @obj: Object to render * @box_only: true to show a box around the object, but keep the normal * background colour inside + * @cur_item: true to render the background only for the current menu item */ -static void scene_render_background(struct scene_obj *obj, bool box_only) +static void scene_render_background(struct scene_obj *obj, bool box_only, + bool cur_item) { + struct vidconsole_bbox bbox[SCENEBB_count], *sel; struct expo *exp = obj->scene->expo; const struct expo_theme *theme = &exp->theme; - struct vidconsole_bbox bbox, label_bbox; struct udevice *dev = exp->display; struct video_priv *vid_priv; struct udevice *cons = exp->cons; @@ -341,24 +497,113 @@ static void scene_render_background(struct scene_obj *obj, bool box_only) } /* see if this object wants to render a background */ - if (scene_obj_calc_bbox(obj, &bbox, &label_bbox)) + if (scene_obj_calc_bbox(obj, bbox)) + return; + + sel = cur_item ? &bbox[SCENEBB_curitem] : &bbox[SCENEBB_label]; + if (!sel->valid) return; vidconsole_push_colour(cons, fore, back, &old); - video_fill_part(dev, label_bbox.x0 - inset, label_bbox.y0 - inset, - label_bbox.x1 + inset, label_bbox.y1 + inset, + video_fill_part(dev, sel->x0 - inset, sel->y0 - inset, + sel->x1 + inset, sel->y1 + inset, vid_priv->colour_fg); vidconsole_pop_colour(cons, &old); if (box_only) { - video_fill_part(dev, label_bbox.x0, label_bbox.y0, - label_bbox.x1, label_bbox.y1, + video_fill_part(dev, sel->x0, sel->y0, sel->x1, sel->y1, vid_priv->colour_bg); } } +static int scene_txt_render(struct expo *exp, struct udevice *dev, + struct udevice *cons, struct scene_obj *obj, + struct scene_txt_generic *gen, int x, int y, + int menu_inset) +{ + const struct vidconsole_mline *mline, *last; + struct video_priv *vid_priv; + struct vidconsole_colour old; + enum colour_idx fore, back; + struct scene_obj_dims dims; + struct scene_obj_bbox bbox; + const char *str; + int ret; + + if (!cons) + return -ENOTSUPP; + + if (gen->font_name || gen->font_size) { + ret = vidconsole_select_font(cons, gen->font_name, + gen->font_size); + } else { + ret = vidconsole_select_font(cons, NULL, 0); + } + if (ret && ret != -ENOSYS) + return log_msg_ret("font", ret); + str = expo_get_str(exp, gen->str_id); + if (!str) + return 0; + + vid_priv = dev_get_uclass_priv(dev); + if (vid_priv->white_on_black) { + fore = VID_BLACK; + back = VID_WHITE; + } else { + fore = VID_LIGHT_GRAY; + back = VID_BLACK; + } + + if (obj->flags & SCENEOF_POINT) { + int inset; + + inset = exp->popup ? menu_inset : 0; + vidconsole_push_colour(cons, fore, back, &old); + video_fill_part(dev, x - inset, y, + obj->bbox.x1, obj->bbox.y1, + vid_priv->colour_bg); + } + + mline = alist_get(&gen->lines, 0, typeof(*mline)); + last = alist_get(&gen->lines, gen->lines.count - 1, typeof(*mline)); + if (mline) + dims.y = last->bbox.y1 - mline->bbox.y0; + bbox.y0 = obj->bbox.y0; + bbox.y1 = obj->bbox.y1; + + if (!mline) { + vidconsole_set_cursor_pos(cons, x, y); + vidconsole_put_string(cons, str); + } + + alist_for_each(mline, &gen->lines) { + struct scene_obj_offset offset; + + bbox.x0 = obj->bbox.x0; + bbox.x1 = obj->bbox.x1; + dims.x = mline->bbox.x1 - mline->bbox.x0; + handle_alignment(obj->horiz, obj->vert, &bbox, &dims, + obj->bbox.x1 - obj->bbox.x0, + obj->bbox.y1 - obj->bbox.y0, &offset); + + x = obj->bbox.x0 + offset.xofs; + y = obj->bbox.y0 + offset.yofs + mline->bbox.y0; + if (y > bbox.y1) + break; /* clip this line and any following */ + vidconsole_set_cursor_pos(cons, x, y); + vidconsole_put_stringn(cons, str + mline->start, mline->len); + } + if (obj->flags & SCENEOF_POINT) + vidconsole_pop_colour(cons, &old); + + return 0; +} + /** * scene_obj_render() - Render an object * + * @obj: Object to render + * @text_mode: true to use text mode + * Return: 0 if OK, -ve on error */ static int scene_obj_render(struct scene_obj *obj, bool text_mode) { @@ -367,10 +612,12 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) const struct expo_theme *theme = &exp->theme; struct udevice *dev = exp->display; struct udevice *cons = text_mode ? NULL : exp->cons; + struct video_priv *vid_priv; int x, y, ret; - x = obj->dim.x; - y = obj->dim.y; + y = obj->bbox.y0; + x = obj->bbox.x0 + obj->ofs.xofs; + vid_priv = dev_get_uclass_priv(dev); switch (obj->type) { case SCENEOBJT_NONE: @@ -388,59 +635,26 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) } case SCENEOBJT_TEXT: { struct scene_obj_txt *txt = (struct scene_obj_txt *)obj; - const char *str; - if (!cons) - return -ENOTSUPP; - - if (txt->font_name || txt->font_size) { - ret = vidconsole_select_font(cons, - txt->font_name, - txt->font_size); - } else { - ret = vidconsole_select_font(cons, NULL, 0); - } - if (ret && ret != -ENOSYS) - return log_msg_ret("font", ret); - str = expo_get_str(exp, txt->str_id); - if (str) { - struct video_priv *vid_priv; - struct vidconsole_colour old; - enum colour_idx fore, back; - - vid_priv = dev_get_uclass_priv(dev); - if (vid_priv->white_on_black) { - fore = VID_BLACK; - back = VID_WHITE; - } else { - fore = VID_LIGHT_GRAY; - back = VID_BLACK; - } - - if (obj->flags & SCENEOF_POINT) { - vidconsole_push_colour(cons, fore, back, &old); - video_fill_part(dev, x - theme->menu_inset, y, - x + obj->dim.w, - y + obj->dim.h, - vid_priv->colour_bg); - } - vidconsole_set_cursor_pos(cons, x, y); - vidconsole_put_string(cons, str); - if (obj->flags & SCENEOF_POINT) - vidconsole_pop_colour(cons, &old); - } + ret = scene_txt_render(exp, dev, cons, obj, &txt->gen, x, y, + theme->menu_inset); break; } case SCENEOBJT_MENU: { struct scene_obj_menu *menu = (struct scene_obj_menu *)obj; - if (exp->popup && (obj->flags & SCENEOF_OPEN)) { - if (!cons) - return -ENOTSUPP; + if (exp->popup) { + if (obj->flags & SCENEOF_OPEN) { + if (!cons) + return -ENOTSUPP; - /* draw a background behind the menu items */ - scene_render_background(obj, false); + /* draw a background behind the menu items */ + scene_render_background(obj, false, false); + } + } else if (exp->show_highlight) { + /* do nothing */ } + /* * With a vidconsole, the text and item pointer are rendered as * normal objects so we don't need to do anything here. The menu @@ -457,8 +671,22 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) } case SCENEOBJT_TEXTLINE: if (obj->flags & SCENEOF_OPEN) - scene_render_background(obj, true); + scene_render_background(obj, true, false); break; + case SCENEOBJT_BOX: { + struct scene_obj_box *box = (struct scene_obj_box *)obj; + + video_draw_box(dev, obj->bbox.x0, obj->bbox.y0, obj->bbox.x1, + obj->bbox.y1, box->width, vid_priv->colour_fg); + break; + } + case SCENEOBJT_TEXTEDIT: { + struct scene_obj_txtedit *ted = (struct scene_obj_txtedit *)obj; + + ret = scene_txt_render(exp, dev, cons, obj, &ted->gen, x, y, + theme->menu_inset); + break; + } } return 0; @@ -477,6 +705,8 @@ int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -510,18 +740,33 @@ int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr) int scene_arrange(struct scene *scn) { struct expo_arrange_info arr; + int xsize = 0, ysize = 0; struct scene_obj *obj; + struct udevice *dev; int ret; + dev = scn->expo->display; + if (dev) { + struct video_priv *priv = dev_get_uclass_priv(dev); + + xsize = priv->xsize; + ysize = priv->ysize; + } + ret = scene_calc_arrange(scn, &arr); if (ret < 0) return log_msg_ret("arr", ret); list_for_each_entry(obj, &scn->obj_head, sibling) { + handle_alignment(obj->horiz, obj->vert, &obj->bbox, &obj->dims, + xsize, ysize, &obj->ofs); + switch (obj->type) { case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -567,6 +812,8 @@ int scene_render_deps(struct scene *scn, uint id) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: scene_menu_render_deps(scn, @@ -686,6 +933,7 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -705,6 +953,9 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event) return log_msg_ret("key", ret); break; } + case SCENEOBJT_TEXTEDIT: + /* TODO(sjg@chromium.org): Implement this */ + break; } return 0; } @@ -724,25 +975,27 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event) return 0; } -int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox *bbox, - struct vidconsole_bbox *label_bbox) +int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox bbox[]) { switch (obj->type) { case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: return -ENOSYS; case SCENEOBJT_MENU: { struct scene_obj_menu *menu = (struct scene_obj_menu *)obj; - scene_menu_calc_bbox(menu, bbox, label_bbox); + scene_menu_calc_bbox(menu, bbox); break; } case SCENEOBJT_TEXTLINE: { struct scene_obj_textline *tline; tline = (struct scene_obj_textline *)obj; - scene_textline_calc_bbox(tline, bbox, label_bbox); + scene_textline_calc_bbox(tline, &bbox[SCENEBB_all], + &bbox[SCENEBB_label]); break; } } @@ -759,6 +1012,8 @@ int scene_calc_dims(struct scene *scn, bool do_menus) switch (obj->type) { case SCENEOBJT_NONE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: case SCENEOBJT_IMAGE: { int width; @@ -766,8 +1021,13 @@ int scene_calc_dims(struct scene *scn, bool do_menus) ret = scene_obj_get_hw(scn, obj->id, &width); if (ret < 0) return log_msg_ret("get", ret); - obj->dim.w = width; - obj->dim.h = ret; + obj->dims.x = width; + obj->dims.y = ret; + if (!(obj->flags & SCENEOF_SIZE_VALID)) { + obj->bbox.x1 = obj->bbox.x0 + width; + obj->bbox.y1 = obj->bbox.y0 + ret; + obj->flags |= SCENEOF_SIZE_VALID; + } } break; } @@ -812,8 +1072,13 @@ int scene_apply_theme(struct scene *scn, struct expo_theme *theme) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_MENU: + case SCENEOBJT_BOX: case SCENEOBJT_TEXTLINE: break; + case SCENEOBJT_TEXTEDIT: + scene_txted_set_font(scn, obj->id, NULL, + theme->font_size); + break; case SCENEOBJT_TEXT: scene_txt_set_font(scn, obj->id, NULL, theme->font_size); @@ -854,6 +1119,8 @@ static int scene_obj_open(struct scene *scn, struct scene_obj *obj) case SCENEOBJT_IMAGE: case SCENEOBJT_MENU: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_TEXTLINE: ret = scene_textline_open(scn, @@ -905,28 +1172,42 @@ int scene_iter_objs(struct scene *scn, expo_scene_obj_iterator iter, return 0; } +int scene_bbox_join(const struct vidconsole_bbox *src, int inset, + struct vidconsole_bbox *dst) +{ + if (dst->valid) { + dst->x0 = min(dst->x0, src->x0 - inset); + dst->y0 = min(dst->y0, src->y0); + dst->x1 = max(dst->x1, src->x1 + inset); + dst->y1 = max(dst->y1, src->y1); + } else { + dst->x0 = src->x0 - inset; + dst->y0 = src->y0; + dst->x1 = src->x1 + inset; + dst->y1 = src->y1; + dst->valid = true; + } + + return 0; +} + int scene_bbox_union(struct scene *scn, uint id, int inset, struct vidconsole_bbox *bbox) { struct scene_obj *obj; + struct vidconsole_bbox local; if (!id) return 0; obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("obj", -ENOENT); - if (bbox->valid) { - bbox->x0 = min(bbox->x0, obj->dim.x - inset); - bbox->y0 = min(bbox->y0, obj->dim.y); - bbox->x1 = max(bbox->x1, obj->dim.x + obj->dim.w + inset); - bbox->y1 = max(bbox->y1, obj->dim.y + obj->dim.h); - } else { - bbox->x0 = obj->dim.x - inset; - bbox->y0 = obj->dim.y; - bbox->x1 = obj->dim.x + obj->dim.w + inset; - bbox->y1 = obj->dim.y + obj->dim.h; - bbox->valid = true; - } + local.x0 = obj->bbox.x0; + local.y0 = obj->bbox.y0; + local.x1 = obj->bbox.x1; + local.y1 = obj->bbox.y1; + local.valid = true; + scene_bbox_join(&local, inset, bbox); return 0; } diff --git a/boot/scene_internal.h b/boot/scene_internal.h index ec9008ea593..95927472875 100644 --- a/boot/scene_internal.h +++ b/boot/scene_internal.h @@ -9,10 +9,44 @@ #ifndef __SCENE_INTERNAL_H #define __SCENE_INTERNAL_H +#include + +struct expo; +struct expo_action; +struct expo_arrange_info; +struct expo_theme; +struct scene_obj; +struct scene_obj_menu; +struct scene_obj_textline; +struct scene_obj_txtedit; +struct scene_txt_generic; struct vidconsole_bbox; +enum scene_obj_t; + typedef int (*expo_scene_obj_iterator)(struct scene_obj *obj, void *priv); +/** + * enum scene_bbox_t - Parts of an object which can have a bounding box + * + * Objects can provide any or all of these bounding boxes + * + * @SCENEBB_label: Menu-item label + * @SCENEBB_key: Menu-item key label + * @SCENEBB_desc: Menu-item Description + * @SCENEBB_curitem: Current item (pointed to) + * @SCENEBB_all: All the above objects combined + */ +enum scene_bbox_t { + SCENEBB_label, + SCENEBB_key, + SCENEBB_desc, + SCENEBB_curitem, + SCENEBB_all, + + SCENEBB_count, +}; + /** * expo_lookup_scene_id() - Look up a scene ID * @@ -291,6 +325,19 @@ struct scene_menitem *scene_menuitem_find_seq(const struct scene_obj_menu *menu, struct scene_menitem *scene_menuitem_find_val(const struct scene_obj_menu *menu, int val); +/** + * scene_bbox_join() - update bouding box with a given src box + * + * Updates @dst so that it encompasses the bounding box @src + * + * @src: Input bounding box + * @inset: Amount of inset to use for width + * @dst: Bounding box to update + * Return: 0 if OK, -ve on error + */ +int scene_bbox_join(const struct vidconsole_bbox *src, int inset, + struct vidconsole_bbox *dst); + /** * scene_bbox_union() - update bouding box with the demensions of an object * @@ -319,13 +366,11 @@ int scene_textline_calc_dims(struct scene_obj_textline *tline); * scene_menu_calc_bbox() - Calculate bounding boxes for the menu * * @menu: Menu to process - * @bbox: Returns bounding box of menu including prompts - * @label_bbox: Returns bounding box of labels + * @bbox: List of bounding box to fill in * Return: 0 if OK, -ve on error */ void scene_menu_calc_bbox(struct scene_obj_menu *menu, - struct vidconsole_bbox *bbox, - struct vidconsole_bbox *label_bbox); + struct vidconsole_bbox *bbox); /** * scene_textline_calc_bbox() - Calculate bounding box for the textline @@ -343,12 +388,10 @@ void scene_textline_calc_bbox(struct scene_obj_textline *menu, * scene_obj_calc_bbox() - Calculate bounding boxes for an object * * @obj: Object to process - * @bbox: Returns bounding box of object including prompts - * @label_bbox: Returns bounding box of labels (active area) + * @bbox: Returns bounding boxes for object * Return: 0 if OK, -ve on error */ -int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox *bbox, - struct vidconsole_bbox *label_bbox); +int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox *bbox); /** * scene_textline_open() - Open a textline object @@ -384,4 +427,16 @@ int scene_textline_close(struct scene *scn, struct scene_obj_textline *tline); */ int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr); +/** + * scene_txt_generic_init() - Set up the generic part of a text object + * + * @exp: Expo containing the object + * @gen: Generic text info + * @name: Object name + * @str_id: String ID for the text + * @str: Initial text string for the object, or NULL to just use str_id + */ +int scene_txt_generic_init(struct expo *exp, struct scene_txt_generic *gen, + const char *name, uint str_id, const char *str); + #endif /* __SCENE_INTERNAL_H */ diff --git a/boot/scene_menu.c b/boot/scene_menu.c index 17150af145d..8db6a2b2f4d 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -87,7 +87,7 @@ struct scene_menitem *scene_menuitem_find_val(const struct scene_obj_menu *menu, static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) { struct scene *scn = menu->obj.scene; - const bool stack = scn->expo->popup; + const bool stack = scn->expo->show_highlight; const struct scene_menitem *item; int ret; @@ -102,15 +102,23 @@ static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) label = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE); ret = scene_obj_set_pos(scn, menu->pointer_id, - menu->obj.dim.x + 200, label->dim.y); + menu->obj.bbox.x0 + 200, label->bbox.y0); if (ret < 0) return log_msg_ret("ptr", ret); } if (stack) { + uint id; + int val; + point &= scn->highlight_id == menu->obj.id; - scene_obj_flag_clrset(scn, item->label_id, SCENEOF_POINT, - point ? SCENEOF_POINT : 0); + val = point ? SCENEOF_POINT : 0; + id = item->desc_id; + if (!id) + id = item->label_id; + if (!id) + id = item->key_id; + scene_obj_flag_clrset(scn, id, SCENEOF_POINT, val); } return 0; @@ -121,64 +129,98 @@ static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) * * Sets the currently pointed-to / highlighted menu item */ -static void menu_point_to_item(struct scene_obj_menu *menu, uint item_id) +static int menu_point_to_item(struct scene_obj_menu *menu, uint item_id) { - if (menu->cur_item_id) - update_pointers(menu, menu->cur_item_id, false); + int ret; + + if (menu->cur_item_id) { + ret = update_pointers(menu, menu->cur_item_id, false); + if (ret) + return log_msg_ret("mpi", ret); + } menu->cur_item_id = item_id; - update_pointers(menu, item_id, true); + ret = update_pointers(menu, item_id, true); + if (ret) + return log_msg_ret("mpu", ret); + + return 0; } void scene_menu_calc_bbox(struct scene_obj_menu *menu, - struct vidconsole_bbox *bbox, - struct vidconsole_bbox *label_bbox) + struct vidconsole_bbox *bbox) { const struct expo_theme *theme = &menu->obj.scene->expo->theme; const struct scene_menitem *item; + int inset = theme->menu_inset; + int i; - bbox->valid = false; - scene_bbox_union(menu->obj.scene, menu->title_id, 0, bbox); + for (i = 0; i < SCENEBB_count; i++) + bbox[i].valid = false; - label_bbox->valid = false; + scene_bbox_union(menu->obj.scene, menu->title_id, 0, + &bbox[SCENEBB_all]); list_for_each_entry(item, &menu->item_head, sibling) { - scene_bbox_union(menu->obj.scene, item->label_id, - theme->menu_inset, bbox); - scene_bbox_union(menu->obj.scene, item->key_id, 0, bbox); - scene_bbox_union(menu->obj.scene, item->desc_id, 0, bbox); - scene_bbox_union(menu->obj.scene, item->preview_id, 0, bbox); + struct vidconsole_bbox local; - /* Get the bounding box of all labels */ - scene_bbox_union(menu->obj.scene, item->label_id, - theme->menu_inset, label_bbox); + local.valid = false; + scene_bbox_union(menu->obj.scene, item->label_id, inset, + &local); + scene_bbox_union(menu->obj.scene, item->key_id, 0, &local); + scene_bbox_union(menu->obj.scene, item->desc_id, 0, &local); + scene_bbox_union(menu->obj.scene, item->preview_id, 0, &local); + + scene_bbox_join(&local, 0, &bbox[SCENEBB_all]); + + /* Get the bounding box of all individual fields */ + scene_bbox_union(menu->obj.scene, item->label_id, inset, + &bbox[SCENEBB_label]); + scene_bbox_union(menu->obj.scene, item->key_id, inset, + &bbox[SCENEBB_key]); + scene_bbox_union(menu->obj.scene, item->desc_id, inset, + &bbox[SCENEBB_desc]); + + if (menu->cur_item_id == item->id) + scene_bbox_join(&local, 0, &bbox[SCENEBB_curitem]); } /* - * subtract the final menuitem's gap to keep the insert the same top - * and bottom + * subtract the final menuitem's gap to keep the inset the same top and + * bottom */ - label_bbox->y1 -= theme->menuitem_gap_y; + bbox[SCENEBB_label].y1 -= theme->menuitem_gap_y; } int scene_menu_calc_dims(struct scene_obj_menu *menu) { - struct vidconsole_bbox bbox, label_bbox; + struct vidconsole_bbox bbox[SCENEBB_count], *cur; const struct scene_menitem *item; - scene_menu_calc_bbox(menu, &bbox, &label_bbox); + scene_menu_calc_bbox(menu, bbox); - /* Make all labels the same size */ - if (label_bbox.valid) { - list_for_each_entry(item, &menu->item_head, sibling) { - scene_obj_set_size(menu->obj.scene, item->label_id, - label_bbox.x1 - label_bbox.x0, - label_bbox.y1 - label_bbox.y0); - } + /* Make all field types the same width */ + list_for_each_entry(item, &menu->item_head, sibling) { + cur = &bbox[SCENEBB_label]; + if (cur->valid) + scene_obj_set_width(menu->obj.scene, item->label_id, + cur->x1 - cur->x0); + cur = &bbox[SCENEBB_key]; + if (cur->valid) + scene_obj_set_width(menu->obj.scene, item->key_id, + cur->x1 - cur->x0); + cur = &bbox[SCENEBB_desc]; + if (cur->valid) + scene_obj_set_width(menu->obj.scene, item->desc_id, + cur->x1 - cur->x0); } - if (bbox.valid) { - menu->obj.dim.w = bbox.x1 - bbox.x0; - menu->obj.dim.h = bbox.y1 - bbox.y0; + cur = &bbox[SCENEBB_all]; + if (cur->valid) { + menu->obj.dims.x = cur->x1 - cur->x0; + menu->obj.dims.y = cur->y1 - cur->y0; + + menu->obj.bbox.x1 = cur->x1; + menu->obj.bbox.y1 = cur->y1; } return 0; @@ -196,12 +238,12 @@ int scene_menu_arrange(struct scene *scn, struct expo_arrange_info *arr, int x, y; int ret; - x = menu->obj.dim.x; - y = menu->obj.dim.y; + x = menu->obj.bbox.x0; + y = menu->obj.bbox.y0; if (menu->title_id) { int width; - ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.dim.x, y); + ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.bbox.x0, y); if (ret < 0) return log_msg_ret("tit", ret); @@ -286,6 +328,9 @@ int scene_menu_arrange(struct scene *scn, struct expo_arrange_info *arr, if (sel_id) menu_point_to_item(menu, sel_id); + menu->obj.bbox.x1 = menu->obj.bbox.x0 + menu->obj.dims.x; + menu->obj.bbox.y1 = menu->obj.bbox.y0 + menu->obj.dims.y; + menu->obj.flags |= SCENEOF_SIZE_VALID; return 0; } @@ -322,7 +367,7 @@ static struct scene_menitem *scene_menu_find_key(struct scene *scn, txt = scene_obj_find(scn, item->key_id, SCENEOBJT_TEXT); if (txt) { - str = expo_get_str(scn->expo, txt->str_id); + str = expo_get_str(scn->expo, txt->gen.str_id); if (str && *str == key) return item; } @@ -397,8 +442,6 @@ int scene_menu_send_key(struct scene *scn, struct scene_obj_menu *menu, int key, break; } - menu_point_to_item(menu, item->id); - return 0; } @@ -483,6 +526,33 @@ int scene_menu_set_pointer(struct scene *scn, uint id, uint pointer_id) return 0; } +int scene_menu_select_item(struct scene *scn, uint id, uint cur_item_id) +{ + struct scene_obj_menu *menu; + int ret; + + menu = scene_obj_find(scn, id, SCENEOBJT_MENU); + if (!menu) + return log_msg_ret("menu", -ENOENT); + + ret = menu_point_to_item(menu, cur_item_id); + if (ret) + return log_msg_ret("msi", ret); + + return 0; +} + +int scene_menu_get_cur_item(struct scene *scn, uint id) +{ + struct scene_obj_menu *menu; + + menu = scene_obj_find(scn, id, SCENEOBJT_MENU); + if (!menu) + return log_msg_ret("menu", -ENOENT); + + return menu->cur_item_id; +} + int scene_menu_display(struct scene_obj_menu *menu) { struct scene *scn = menu->obj.scene; @@ -500,7 +570,7 @@ int scene_menu_display(struct scene_obj_menu *menu) if (!txt) return log_msg_ret("txt", -EINVAL); - str = expo_get_str(exp, txt->str_id); + str = expo_get_str(exp, txt->gen.str_id); printf("%s\n\n", str); } @@ -508,7 +578,7 @@ int scene_menu_display(struct scene_obj_menu *menu) return 0; pointer = scene_obj_find(scn, menu->pointer_id, SCENEOBJT_TEXT); - pstr = expo_get_str(scn->expo, pointer->str_id); + pstr = expo_get_str(scn->expo, pointer->gen.str_id); list_for_each_entry(item, &menu->item_head, sibling) { struct scene_obj_txt *key = NULL, *label = NULL; @@ -517,15 +587,15 @@ int scene_menu_display(struct scene_obj_menu *menu) key = scene_obj_find(scn, item->key_id, SCENEOBJT_TEXT); if (key) - kstr = expo_get_str(exp, key->str_id); + kstr = expo_get_str(exp, key->gen.str_id); label = scene_obj_find(scn, item->label_id, SCENEOBJT_TEXT); if (label) - lstr = expo_get_str(exp, label->str_id); + lstr = expo_get_str(exp, label->gen.str_id); desc = scene_obj_find(scn, item->desc_id, SCENEOBJT_TEXT); if (desc) - dstr = expo_get_str(exp, desc->str_id); + dstr = expo_get_str(exp, desc->gen.str_id); printf("%3s %3s %-10s %s\n", pointer && menu->cur_item_id == item->id ? pstr : "", diff --git a/boot/scene_textedit.c b/boot/scene_textedit.c new file mode 100644 index 00000000000..8242eb39806 --- /dev/null +++ b/boot/scene_textedit.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Implementation of a menu in a scene + * + * Copyright 2025 Google LLC + * Written by Simon Glass + */ + +#define LOG_CATEGORY LOGC_EXPO + +#include +#include +#include +#include +#include "scene_internal.h" + +enum { + INITIAL_SIZE = SZ_4K, +}; + +int scene_texted(struct scene *scn, const char *name, uint id, uint str_id, + struct scene_obj_txtedit **teditp) +{ + struct scene_obj_txtedit *ted; + char *buf; + int ret; + + ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXTEDIT, + sizeof(struct scene_obj_txtedit), + (struct scene_obj **)&ted); + if (ret < 0) + return log_msg_ret("obj", ret); + + abuf_init(&ted->buf); + if (!abuf_realloc(&ted->buf, INITIAL_SIZE)) + return log_msg_ret("buf", -ENOMEM); + buf = abuf_data(&ted->buf); + *buf = '\0'; + + ret = scene_txt_generic_init(scn->expo, &ted->gen, name, str_id, buf); + if (ret) + return log_msg_ret("teg", ret); + if (teditp) + *teditp = ted; + + return ted->obj.id; +} + +int scene_txted_set_font(struct scene *scn, uint id, const char *font_name, + uint font_size) +{ + struct scene_obj_txtedit *ted; + + ted = scene_obj_find(scn, id, SCENEOBJT_TEXTEDIT); + if (!ted) + return log_msg_ret("find", -ENOENT); + ted->gen.font_name = font_name; + ted->gen.font_size = font_size; + + return 0; +} diff --git a/boot/scene_textline.c b/boot/scene_textline.c index 6adef7cc173..7bc35a997dc 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -31,8 +31,7 @@ int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, (struct scene_obj **)&tline); if (ret < 0) return log_msg_ret("obj", -ENOMEM); - abuf_init(&tline->buf); - if (!abuf_realloc(&tline->buf, max_chars + 1)) + if (!abuf_init_size(&tline->buf, max_chars + 1)) return log_msg_ret("buf", -ENOMEM); buf = abuf_data(&tline->buf); *buf = '\0'; @@ -62,7 +61,8 @@ void scene_textline_calc_bbox(struct scene_obj_textline *tline, int scene_textline_calc_dims(struct scene_obj_textline *tline) { - struct scene *scn = tline->obj.scene; + struct scene_obj *obj = &tline->obj; + struct scene *scn = obj->scene; struct vidconsole_bbox bbox; struct scene_obj_txt *txt; int ret; @@ -71,17 +71,22 @@ int scene_textline_calc_dims(struct scene_obj_textline *tline) if (!txt) return log_msg_ret("dim", -ENOENT); - ret = vidconsole_nominal(scn->expo->cons, txt->font_name, - txt->font_size, tline->max_chars, &bbox); + ret = vidconsole_nominal(scn->expo->cons, txt->gen.font_name, + txt->gen.font_size, tline->max_chars, &bbox); if (ret) return log_msg_ret("nom", ret); if (bbox.valid) { - tline->obj.dim.w = bbox.x1 - bbox.x0; - tline->obj.dim.h = bbox.y1 - bbox.y0; - - scene_obj_set_size(scn, tline->edit_id, tline->obj.dim.w, - tline->obj.dim.h); + obj->dims.x = bbox.x1 - bbox.x0; + obj->dims.y = bbox.y1 - bbox.y0; + if (!(obj->flags & SCENEOF_SIZE_VALID)) { + obj->bbox.x1 = obj->bbox.x0 + obj->dims.x; + obj->bbox.y1 = obj->bbox.y0 + obj->dims.y; + obj->flags |= SCENEOF_SIZE_VALID; + } + scene_obj_set_size(scn, tline->edit_id, + obj->bbox.x1 - obj->bbox.x0, + obj->bbox.y1 - obj->bbox.y0); } return 0; @@ -95,16 +100,16 @@ int scene_textline_arrange(struct scene *scn, struct expo_arrange_info *arr, int x, y; int ret; - x = tline->obj.dim.x; - y = tline->obj.dim.y; + x = tline->obj.bbox.x0; + y = tline->obj.bbox.y0; if (tline->label_id) { - ret = scene_obj_set_pos(scn, tline->label_id, tline->obj.dim.x, - y); + ret = scene_obj_set_pos(scn, tline->label_id, + tline->obj.bbox.x0, y); if (ret < 0) return log_msg_ret("tit", ret); ret = scene_obj_set_pos(scn, tline->edit_id, - tline->obj.dim.x + 200, y); + tline->obj.bbox.x0 + 200, y); if (ret < 0) return log_msg_ret("tit", ret); @@ -186,10 +191,10 @@ int scene_textline_render_deps(struct scene *scn, if (!txt) return log_msg_ret("cur", -ENOENT); - if (txt->font_name || txt->font_size) { + if (txt->gen.font_name || txt->gen.font_size) { ret = vidconsole_select_font(cons, - txt->font_name, - txt->font_size); + txt->gen.font_name, + txt->gen.font_size); } else { ret = vidconsole_select_font(cons, NULL, 0); } @@ -198,8 +203,8 @@ int scene_textline_render_deps(struct scene *scn, if (ret) return log_msg_ret("sav", ret); - vidconsole_set_cursor_visible(cons, true, txt->obj.dim.x, - txt->obj.dim.y, scn->cls.num); + vidconsole_set_cursor_visible(cons, true, txt->obj.bbox.x0, + txt->obj.bbox.y0, scn->cls.num); } return 0; @@ -220,7 +225,7 @@ int scene_textline_open(struct scene *scn, struct scene_obj_textline *tline) if (!txt) return log_msg_ret("cur", -ENOENT); - vidconsole_set_cursor_pos(cons, txt->obj.dim.x, txt->obj.dim.y); + vidconsole_set_cursor_pos(cons, txt->obj.bbox.x0, txt->obj.bbox.y0); vidconsole_entry_start(cons); cli_cread_init(&scn->cls, abuf_data(&tline->buf), tline->max_chars); scn->cls.insert = true; diff --git a/cmd/2048.c b/cmd/2048.c index 42cd171b0e4..aa0f82721dc 100644 --- a/cmd/2048.c +++ b/cmd/2048.c @@ -8,6 +8,7 @@ #include #include #include +#include #define SIZE 4 static uint score; diff --git a/cmd/Kconfig b/cmd/Kconfig index 057f091bf3b..1ba3cfcb28a 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1865,12 +1865,6 @@ config CMD_DHCP6 if CMD_DHCP6 -config DHCP6_PXE_CLIENTARCH - hex - default 0x16 if ARM64 - default 0x15 if ARM - default 0xFF - config DHCP6_PXE_DHCP_OPTION bool "Request & store 'pxe_configfile' from DHCP6 server" @@ -1978,15 +1972,26 @@ config BOOTP_PXE help Supported for ARM, ARM64, and x86 for now. -config BOOTP_PXE_CLIENTARCH - hex - depends on BOOTP_PXE - default 0x16 if ARM64 - default 0x15 if ARM - default 0x0 if X86 +config DHCP_PXE_CLIENTARCH + hex "DCHCP client system architecture type" + depends on BOOTP_PXE || CMD_DHCP6 + default 0x16 if ARM64 # arm 64 uboot + default 0x15 if ARM # arm 32 uboot + default 0x0 if X86 # x86 BIOS + default 0xFF # DHCP option not sent + help + DHCP option 93 (defined in RFC4578) or DHCPv6 option 61 (defined in + RFC 5970) is used to transmit the client system architecture type + to the DHCP server. The DHCP server may use this information to + choose the boot file. For a complete list of assigned values see + https://www.iana.org/assignments/dhcpv6-parameters#processor-architecture. + + If the value is set to the reserved value 0xFF, the DHCP option will + not be sent by U-Boot. config BOOTP_PXE_DHCP_OPTION bool "Request & store 'pxe_configfile' from BOOTP/DHCP server" + default y depends on BOOTP_PXE config BOOTP_VCI_STRING @@ -1997,6 +2002,13 @@ config BOOTP_VCI_STRING default "U-Boot.arm" if ARM default "U-Boot" +config BOOTP_RANDOM_XID + bool "Send random transaction ID to BOOTP/DHCP server" + depends on CMD_BOOTP && (LIB_RAND || LIB_HW_RAND) + help + Selecting this will allow for a random transaction ID to get + selected for each BOOTP/DHCPv4 exchange. + config CMD_TFTPPUT bool "tftp put" depends on CMD_TFTPBOOT @@ -2154,7 +2166,7 @@ config CMD_TFTPBOOT config CMD_WGET bool "wget" - default y if SANDBOX + default y if SANDBOX || ARCH_QEMU select WGET help wget is a simple command to download kernel, or other files, diff --git a/cmd/abootimg.c b/cmd/abootimg.c index ae7a1a7c83b..6fb52153786 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -95,7 +96,7 @@ static int abootimg_get_dtb_load_addr(int argc, char *const argv[]) return CMD_RET_USAGE; struct andr_image_data img_data = {0}; const struct andr_boot_img_hdr_v0 *hdr; - const struct andr_vnd_boot_img_hdr *vhdr; + const struct andr_vnd_boot_img_hdr *vhdr = NULL; hdr = map_sysmem(abootimg_addr(), sizeof(*hdr)); if (get_avendor_bootimg_addr() != -1) diff --git a/cmd/adc.c b/cmd/adc.c index 4d3b5b61f6f..334ba7fdeca 100644 --- a/cmd/adc.c +++ b/cmd/adc.c @@ -5,6 +5,7 @@ */ #include #include +#include #include #include diff --git a/cmd/armflash.c b/cmd/armflash.c index e292cf85c45..cde275c881b 100644 --- a/cmd/armflash.c +++ b/cmd/armflash.c @@ -7,8 +7,10 @@ */ #include #include +#include #include #include +#include #include #define MAX_REGIONS 4 diff --git a/cmd/bcb.c b/cmd/bcb.c index 16eabfe00f5..d6d944bd6b3 100644 --- a/cmd/bcb.c +++ b/cmd/bcb.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/blkmap.c b/cmd/blkmap.c index 86a123b1cd3..65edec899e2 100644 --- a/cmd/blkmap.c +++ b/cmd/blkmap.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include diff --git a/cmd/bootflow.c b/cmd/bootflow.c index a1fd59a69f4..551dffbb8b8 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -13,6 +13,9 @@ #include #include #include +#include +#include +#include #include /** @@ -104,24 +107,39 @@ __maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std, bool text_mode, struct bootflow **bflowp) { + struct expo *exp; struct bootflow *bflow; - int ret; + int ret, seq; - ret = bootflow_menu_run(std, text_mode, &bflow); - if (ret) { - if (ret == -EAGAIN) { - printf("Nothing chosen\n"); - std->cur_bootflow = NULL; - } else { - printf("Menu failed (err=%d)\n", ret); + ret = bootflow_menu_start(std, text_mode, &exp); + if (ret) + return log_msg_ret("bhs", ret); + + ret = -ERESTART; + do { + if (ret == -ERESTART) { + ret = expo_render(exp); + if (ret) + return log_msg_ret("bhr", ret); } + ret = bootflow_menu_poll(exp, &seq); + } while (ret == -EAGAIN || ret == -ERESTART); - return ret; + if (ret == -EPIPE) { + printf("Nothing chosen\n"); + std->cur_bootflow = NULL; + } else if (ret) { + printf("Menu failed (err=%d)\n", ret); + } else { + bflow = alist_getw(&std->bootflows, seq, struct bootflow); + printf("Selected: %s\n", bflow->os_name ? bflow->os_name : + bflow->name); + std->cur_bootflow = bflow; + *bflowp = bflow; } - - printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name); - std->cur_bootflow = bflow; - *bflowp = bflow; + expo_destroy(exp); + if (ret) + return ret; return 0; } diff --git a/cmd/booti.c b/cmd/booti.c index 1a57fe91397..e6f67d6e136 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -29,6 +30,7 @@ static int booti_start(struct bootm_info *bmi) uint8_t *temp; ulong dest; ulong dest_end; + phys_addr_t ep_addr; unsigned long comp_len; unsigned long decomp_len; int ctype; @@ -87,7 +89,14 @@ static int booti_start(struct bootm_info *bmi) images->os.start = relocated_addr; images->os.end = relocated_addr + image_size; - lmb_reserve(images->ep, le32_to_cpu(image_size), LMB_NONE); + ep_addr = (phys_addr_t)images->ep; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &ep_addr, + le32_to_cpu(image_size), LMB_NONE); + if (ret) { + printf("Failed to allocate memory for the image at %#llx\n", + (unsigned long long)images->ep); + return 1; + } /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index a5c979079f4..d3108778c6f 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -114,6 +114,14 @@ static char *bootmenu_choice_entry(void *data) ++menu->active; /* no menu key selected, regenerate menu */ return NULL; + case BKEY_SHORTCUT: + /* invalid shortcut, regenerate menu */ + if (cch->shortcut_key >= menu->count - 1) + return NULL; + /* shortcut_key value for Exit is is -1 */ + menu->active = cch->shortcut_key < 0 ? menu->count - 1 : + cch->shortcut_key; + fallthrough; case BKEY_SELECT: iter = menu->first; for (i = 0; i < menu->active; ++i) @@ -161,6 +169,21 @@ static void bootmenu_destroy(struct bootmenu_data *menu) free(menu); } +static char bootmenu_entry_shortcut_key(int index) +{ + switch (index) { + /* 1-9 shortcut key (0 reserved) */ + case 0 ... 8: + return '1' + index; + /* a-z shortcut key */ + case 9 ... 34: + return 'a' + index - 9; + /* We support shortcut for up to 34 options (0 reserved) */ + default: + return -ENOENT; + } +} + /** * prepare_bootmenu_entry() - generate the bootmenu_xx entries * @@ -184,6 +207,8 @@ static int prepare_bootmenu_entry(struct bootmenu_data *menu, struct bootmenu_entry *iter = *current; while ((option = bootmenu_getoption(i))) { + char shortcut_key; + int len; /* bootmenu_[num] format is "[title]=[commands]" */ sep = strchr(option, '='); @@ -196,12 +221,22 @@ static int prepare_bootmenu_entry(struct bootmenu_data *menu, if (!entry) return -ENOMEM; - entry->title = strndup(option, sep - option); + /* Add shotcut key option: %c. %s\0 */ + len = sep - option + 4; + + entry->title = malloc(len); if (!entry->title) { free(entry); return -ENOMEM; } + shortcut_key = bootmenu_entry_shortcut_key(i); + /* Use emtpy space if entry doesn't support shortcut key */ + snprintf(entry->title, len, "%c%c %s", + shortcut_key > 0 ? shortcut_key : ' ', + shortcut_key > 0 ? '.' : ' ', + option); + entry->command = strdup(sep + 1); if (!entry->command) { free(entry->title); @@ -388,9 +423,9 @@ static struct bootmenu_data *bootmenu_create(int uefi, int delay) /* Add Quit entry if exiting bootmenu is disabled */ if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) - entry->title = strdup("Exit"); + entry->title = strdup("0. Exit"); else - entry->title = strdup("Quit"); + entry->title = strdup("0. Quit"); if (!entry->title) { free(entry); diff --git a/cmd/bootmeth.c b/cmd/bootmeth.c index 2f41fa1bec6..ea4b3f47db8 100644 --- a/cmd/bootmeth.c +++ b/cmd/bootmeth.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/cmd/bootstage.c b/cmd/bootstage.c index 8248c41ca82..5c6d5a3ab45 100644 --- a/cmd/bootstage.c +++ b/cmd/bootstage.c @@ -6,6 +6,7 @@ #include #include #include +#include static int do_bootstage_report(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/bootz.c b/cmd/bootz.c index 99318ff213f..44af7d012aa 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -28,6 +28,7 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, { ulong zi_start, zi_end; struct bootm_info bmi; + phys_addr_t ep_addr; int ret; bootm_init(&bmi); @@ -56,7 +57,14 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, if (ret != 0) return 1; - lmb_reserve(images->ep, zi_end - zi_start, LMB_NONE); + ep_addr = (phys_addr_t)images->ep; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &ep_addr, zi_end - zi_start, + LMB_NONE); + if (ret) { + printf("Failed to allocate memory for the image at %#llx\n", + (unsigned long long)images->ep); + return 1; + } /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/broadcom/nitro_image_load.c b/cmd/broadcom/nitro_image_load.c index 289b184e9af..fe08679840e 100644 --- a/cmd/broadcom/nitro_image_load.c +++ b/cmd/broadcom/nitro_image_load.c @@ -4,6 +4,7 @@ */ #include +#include #include #define FW_IMAGE_SIG 0xff123456 diff --git a/cmd/cache.c b/cmd/cache.c index 3049f5c305f..b7007877ab0 100644 --- a/cmd/cache.c +++ b/cmd/cache.c @@ -10,6 +10,7 @@ #include #include #include +#include static int parse_argv(const char *); diff --git a/cmd/cat.c b/cmd/cat.c index 6828b7b364e..3167cda6032 100644 --- a/cmd/cat.c +++ b/cmd/cat.c @@ -8,6 +8,7 @@ #include #include #include +#include static int do_cat(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/cedit.c b/cmd/cedit.c index f696356419e..20f48ae0007 100644 --- a/cmd/cedit.c +++ b/cmd/cedit.c @@ -287,6 +287,8 @@ static int do_cedit_run(struct cmd_tbl *cmdtp, int flag, int argc, log_err("Failed (err=%dE)\n", ret); return CMD_RET_FAILURE; } + expo_destroy(cur_exp); + cur_exp = NULL; return 0; } diff --git a/cmd/diag.c b/cmd/diag.c index c6da5aae3fc..4a88ab00a07 100644 --- a/cmd/diag.c +++ b/cmd/diag.c @@ -9,6 +9,7 @@ */ #include #include +#include int do_diag(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/cmd/dm.c b/cmd/dm.c index ec9cfd85376..1f212c0f030 100644 --- a/cmd/dm.c +++ b/cmd/dm.c @@ -9,6 +9,7 @@ #include #include #include +#include static int do_dm_dump_driver_compat(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) diff --git a/cmd/echo.c b/cmd/echo.c index 973213a03a6..d1346504cfb 100644 --- a/cmd/echo.c +++ b/cmd/echo.c @@ -5,6 +5,7 @@ */ #include +#include static int do_echo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 6e14d34a6bd..8ac0fb98e02 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -35,6 +35,7 @@ static int avail_row; #define EFICONFIG_DESCRIPTION_MAX 32 #define EFICONFIG_OPTIONAL_DATA_MAX 64 +#define EFICONFIG_URI_MAX 512 #define EFICONFIG_MENU_HEADER_ROW_NUM 3 #define EFICONFIG_MENU_DESC_ROW_NUM 5 @@ -538,6 +539,40 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_ return dp; } +/** + * eficonfig_create_uri_device_path() - Create an URI based device path + * @uri_str: URI string to be added to the device path + * + * Take the u16 string, convert it to a u8 string, and create a URI + * device path. This will be used for the EFI HTTP boot. + * + * Return: pointer to the URI device path on success, NULL on failure + */ +static struct efi_device_path *eficonfig_create_uri_device_path(u16 *uri_str) +{ + char *pos, *p; + u32 len = 0; + efi_uintn_t uridp_len; + struct efi_device_path_uri *uridp; + + len = utf16_utf8_strlen(uri_str); + + uridp_len = sizeof(struct efi_device_path) + len + 1; + uridp = efi_alloc(uridp_len + sizeof(EFI_DP_END)); + if (!uridp) + return NULL; + + uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; + uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI; + uridp->dp.length = uridp_len; + p = (char *)&uridp->uri; + utf16_utf8_strcpy(&p, uri_str); + pos = (char *)uridp + uridp_len; + memcpy(pos, &EFI_DP_END, sizeof(EFI_DP_END)); + + return &uridp->dp; +} + /** * eficonfig_file_selected() - handler of file selection * @@ -983,6 +1018,22 @@ static efi_status_t eficonfig_boot_add_optional_data(void *data) " enter optional data:"); } +/** + * eficonfig_boot_add_uri() - handle user input for HTTP Boot URI + * + * @data: pointer to the internal boot option structure + * Return: status code + */ +static efi_status_t eficonfig_boot_add_uri(void *data) +{ + struct eficonfig_select_file_info *file_info = data; + + return handle_user_input(file_info->uri, EFICONFIG_URI_MAX, 24, + "\n ** Edit URI **\n" + "\n" + " enter HTTP Boot URI:"); +} + /** * eficonfig_boot_edit_save() - handler to save the boot option * @@ -998,7 +1049,8 @@ static efi_status_t eficonfig_boot_edit_save(void *data) bo->edit_completed = false; return EFI_NOT_READY; } - if (u16_strlen(bo->file_info.current_path) == 0) { + if (u16_strlen(bo->file_info.current_path) == 0 && + u16_strlen(bo->file_info.uri) == 0) { eficonfig_print_msg("File is not selected!"); bo->edit_completed = false; return EFI_NOT_READY; @@ -1024,9 +1076,19 @@ efi_status_t eficonfig_process_clear_file_selection(void *data) file_info->current_path[0] = u'\0'; file_info->dp_volume = NULL; + if (file_info->uri) + file_info->uri[0] = u'\0'; + return EFI_ABORTED; } +static struct eficonfig_item select_boot_file_menu_items[] = { + {"Select File", eficonfig_process_select_file}, + {"Enter URI", eficonfig_boot_add_uri}, + {"Clear", eficonfig_process_clear_file_selection}, + {"Quit", eficonfig_process_quit}, +}; + static struct eficonfig_item select_file_menu_items[] = { {"Select File", eficonfig_process_select_file}, {"Clear", eficonfig_process_clear_file_selection}, @@ -1042,16 +1104,30 @@ static struct eficonfig_item select_file_menu_items[] = { efi_status_t eficonfig_process_show_file_option(void *data) { efi_status_t ret; + unsigned int menu_count; struct efimenu *efi_menu; + struct eficonfig_item *menu_items; + struct eficonfig_select_file_info *file_info = data; - select_file_menu_items[0].data = data; - select_file_menu_items[1].data = data; - efi_menu = eficonfig_create_fixed_menu(select_file_menu_items, - ARRAY_SIZE(select_file_menu_items)); + menu_items = file_info->uri ? select_boot_file_menu_items : + select_file_menu_items; + + menu_count = file_info->uri ? + ARRAY_SIZE(select_boot_file_menu_items) : + ARRAY_SIZE(select_file_menu_items); + + menu_items[0].data = data; + menu_items[1].data = data; + menu_items[2].data = data; + + efi_menu = eficonfig_create_fixed_menu(menu_items, menu_count); if (!efi_menu) return EFI_OUT_OF_RESOURCES; - ret = eficonfig_process_common(efi_menu, " ** Update File **", + ret = eficonfig_process_common(efi_menu, + file_info->uri ? + " ** Update File/URI **" : + " ** Update File **", eficonfig_menu_desc, eficonfig_display_statusline, eficonfig_print_entry, @@ -1121,6 +1197,14 @@ out: file_info->current_path[len] = u'\0'; file_info->current_volume = tmp->current_volume; file_info->dp_volume = tmp->dp_volume; + + /* + * File being selected, set the URI string to + * null so that the file gets picked as the + * boot image. + */ + if (file_info->uri) + file_info->uri[0] = u'\0'; } list_for_each_safe(pos, n, &tmp->filepath_list) { @@ -1224,6 +1308,12 @@ static efi_status_t prepare_file_selection_entry(struct efimenu *efi_menu, char efi_handle_t handle; char *devname; + /* Check for URI based boot file */ + if (file_info->uri && utf16_utf8_strlen(file_info->uri)) + return create_boot_option_entry(efi_menu, title, file_info->uri, + eficonfig_process_show_file_option, + file_info); + devname = calloc(1, EFICONFIG_VOLUME_PATH_MAX + 1); if (!devname) return EFI_OUT_OF_RESOURCES; @@ -1340,6 +1430,27 @@ out: return ret; } +/** + * fill_dp_uri() - copy the URI string in the device path + * @dp: pointer to the URI device path + * @uri_str: URI string to be copied + * + * Copy the passed URI string to the URI device path. This + * requires utf8_utf16_strcpy() to copy the u16 string to + * the u8 array in the device path structure. + * + * Return: None + */ +static void fill_dp_uri(struct efi_device_path *dp, u16 **uri_str) +{ + u16 *p = *uri_str; + struct efi_device_path_uri *uridp; + + uridp = (struct efi_device_path_uri *)dp; + + utf8_utf16_strcpy(&p, uridp->uri); +} + /** * fill_file_info() - fill the file info from efi_device_path structure * @@ -1392,10 +1503,13 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo size_t len; efi_status_t ret; char *tmp = NULL, *p; + u16 *current_path = NULL; struct efi_load_option lo = {0}; efi_uintn_t dp_size; struct efi_device_path *dp = NULL; efi_uintn_t size = load_option_size; + struct efi_device_path *dp_volume = NULL; + struct efi_device_path *uri_dp = NULL; struct efi_device_path *device_dp = NULL; struct efi_device_path *initrd_dp = NULL; struct efi_device_path *fdt_dp = NULL; @@ -1464,6 +1578,12 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo goto out; } + bo->file_info.uri = calloc(1, EFICONFIG_URI_MAX * sizeof(u16)); + if (!bo->file_info.uri) { + ret = EFI_OUT_OF_RESOURCES; + goto out; + } + /* copy the preset value */ if (load_option) { ret = efi_deserialize_load_option(&lo, load_option, &size); @@ -1481,7 +1601,10 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo u16_strcpy(bo->description, lo.label); /* EFI image file path is a first instance */ - if (lo.file_path) + if (lo.file_path && EFI_DP_TYPE(lo.file_path, MESSAGING_DEVICE, + MSG_URI)) + fill_dp_uri(lo.file_path, &bo->file_info.uri); + else if (lo.file_path) fill_file_info(lo.file_path, &bo->file_info, device_dp); /* Initrd file path (optional) is placed at second instance. */ @@ -1512,6 +1635,9 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo goto out; } + if (utf16_utf8_strlen(bo->file_info.uri)) + uri_dp = eficonfig_create_uri_device_path(bo->file_info.uri); + if (bo->initrd_info.dp_volume) { dp = eficonfig_create_device_path(bo->initrd_info.dp_volume, bo->initrd_info.current_path); @@ -1536,7 +1662,10 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo efi_free_pool(dp); } - dp = eficonfig_create_device_path(bo->file_info.dp_volume, bo->file_info.current_path); + dp_volume = bo->file_info.dp_volume; + current_path = bo->file_info.current_path; + dp = uri_dp ? + uri_dp : eficonfig_create_device_path(dp_volume, current_path); if (!dp) { ret = EFI_OUT_OF_RESOURCES; goto out; @@ -1560,6 +1689,7 @@ out: free(tmp); free(bo->optional_data); free(bo->description); + free(bo->file_info.uri); free(bo->file_info.current_path); free(bo->initrd_info.current_path); free(bo->fdt_info.current_path); diff --git a/cmd/elf.c b/cmd/elf.c index 6b49c613703..5e0ee30a7c8 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -247,7 +247,7 @@ int do_bootvx(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ptr += sprintf(build_buf + ptr, "e=%s", tmp); tmp = env_get("netmask"); if (tmp) { - u32 mask = env_get_ip("netmask").s_addr; + u32 mask = string_to_ip(tmp).s_addr; ptr += sprintf(build_buf + ptr, ":%08x ", ntohl(mask)); } else { diff --git a/cmd/extension_board.c b/cmd/extension_board.c index 6c14d0ddebd..317b260bf36 100644 --- a/cmd/extension_board.c +++ b/cmd/extension_board.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/flash.c b/cmd/flash.c index fd660ec477c..76aa387ba59 100644 --- a/cmd/flash.c +++ b/cmd/flash.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #if defined(CONFIG_CMD_MTDPARTS) diff --git a/cmd/fuse.c b/cmd/fuse.c index 6c42c096809..e2206cdf0d5 100644 --- a/cmd/fuse.c +++ b/cmd/fuse.c @@ -14,6 +14,7 @@ #include #include #include +#include static int confirm_prog(void) { diff --git a/cmd/hash.c b/cmd/hash.c index 5b40982b098..96d0e443a5b 100644 --- a/cmd/hash.c +++ b/cmd/hash.c @@ -10,6 +10,7 @@ */ #include +#include #include #include diff --git a/cmd/ide.c b/cmd/ide.c index 036489fda97..ed30f946866 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -19,7 +19,6 @@ #include #include -#include #include #ifdef CONFIG_LED_STATUS diff --git a/cmd/irq.c b/cmd/irq.c index da223b4b2cc..58483d04de8 100644 --- a/cmd/irq.c +++ b/cmd/irq.c @@ -6,6 +6,7 @@ #include #include #include +#include static int do_interrupts(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c index 1a5271000bf..34a6da01947 100644 --- a/cmd/legacy-mtd-utils.c +++ b/cmd/legacy-mtd-utils.c @@ -4,7 +4,6 @@ #include #include #include -#include static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size, loff_t *maxsize, int devtype) diff --git a/cmd/legacy_led.c b/cmd/legacy_led.c index 50de7e89d8f..db312ae6e2d 100644 --- a/cmd/legacy_led.c +++ b/cmd/legacy_led.c @@ -12,6 +12,7 @@ #include #include #include +#include struct led_tbl_s { char *string; /* String for use in the command */ diff --git a/cmd/load.c b/cmd/load.c index 899bb4f598e..159767aa7f7 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -178,17 +178,20 @@ static ulong load_serial(long offset) #endif { void *dst; + phys_addr_t dst_addr; - ret = lmb_reserve(store_addr, binlen, LMB_NONE); + dst_addr = (phys_addr_t)store_addr; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &dst_addr, + binlen, LMB_NONE); if (ret) { printf("\nCannot overwrite reserved area (%08lx..%08lx)\n", store_addr, store_addr + binlen); return ret; } - dst = map_sysmem(store_addr, binlen); + dst = map_sysmem(dst_addr, binlen); memcpy(dst, binbuf, binlen); unmap_sysmem(dst); - lmb_free(store_addr, binlen); + lmb_free(dst_addr, binlen, LMB_NONE); } if ((store_addr) < start_addr) start_addr = store_addr; diff --git a/cmd/mbr.c b/cmd/mbr.c index 7e1f92a13bb..7fe6c9e103a 100644 --- a/cmd/mbr.c +++ b/cmd/mbr.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/cmd/mem.c b/cmd/mem.c index 9e716776393..b8afe62e474 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include #ifdef CONFIG_MTD_NOR_FLASH #include #endif diff --git a/cmd/mmc.c b/cmd/mmc.c index fe7899ec793..5340a58be8e 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/mp.c b/cmd/mp.c index 261bb8a07d4..686e1f8a82f 100644 --- a/cmd/mp.c +++ b/cmd/mp.c @@ -6,6 +6,7 @@ #include #include #include +#include static int cpu_status_all(void) { diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index a021b2d198d..571b79f091d 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -74,6 +74,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index 6b7d9ee061d..2755c26cdf7 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -185,7 +185,7 @@ static int mmc_burn_image(size_t image_size) lbaint_t blk_count; ulong blk_written; int err; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + const u8 mmc_dev_num = CONFIG_ENV_MMC_DEVICE_INDEX; #ifdef CONFIG_BLK struct blk_desc *blk_desc; #endif @@ -290,7 +290,7 @@ static size_t mmc_read_file(const char *file_name) loff_t act_read = 0; int rc; struct mmc *mmc; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + const u8 mmc_dev_num = CONFIG_ENV_MMC_DEVICE_INDEX; mmc = find_mmc_device(mmc_dev_num); if (!mmc) { diff --git a/cmd/net.c b/cmd/net.c index eaa1de5295f..886735ea14f 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -564,7 +564,7 @@ int do_sntp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) char *toff; if (argc < 2) { - net_ntp_server = env_get_ip("ntpserverip"); + net_ntp_server = string_to_ip(env_get("ntpserverip")); if (net_ntp_server.s_addr == 0) { printf("ntpserverip not set\n"); return CMD_RET_FAILURE; diff --git a/cmd/optee.c b/cmd/optee.c index e3aae5e9f9b..155c9f1bb73 100644 --- a/cmd/optee.c +++ b/cmd/optee.c @@ -6,6 +6,7 @@ #include #include #include +#include #define TA_HELLO_WORLD_CMD_INC_VALUE 0 /* This needs to match the UUID of the Hello World TA. */ diff --git a/cmd/pxe.c b/cmd/pxe.c index 0f26b3b4219..3deae5e6d47 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -64,6 +65,8 @@ static int pxe_dhcp_option_path(struct pxe_context *ctx, unsigned long pxefile_a int ret = get_pxe_file(ctx, pxelinux_configfile, pxefile_addr_r); free(pxelinux_configfile); + /* set to NULL to avoid double-free if DHCP is tried again */ + pxelinux_configfile = NULL; return ret; } diff --git a/cmd/sandbox/exception.c b/cmd/sandbox/exception.c index f9c847d8ff2..e015acf60e2 100644 --- a/cmd/sandbox/exception.c +++ b/cmd/sandbox/exception.c @@ -6,6 +6,7 @@ */ #include +#include static int do_sigsegv(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/seama.c b/cmd/seama.c index 3c8e8199234..d6287978090 100644 --- a/cmd/seama.c +++ b/cmd/seama.c @@ -5,6 +5,7 @@ */ #include +#include #include /* diff --git a/cmd/sha1sum.c b/cmd/sha1sum.c index 52aa26c78d2..f2757146bba 100644 --- a/cmd/sha1sum.c +++ b/cmd/sha1sum.c @@ -9,6 +9,7 @@ #include #include +#include #include int do_sha1sum(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/sleep.c b/cmd/sleep.c index 7616fed7556..a8c896e0c5e 100644 --- a/cmd/sleep.c +++ b/cmd/sleep.c @@ -9,6 +9,7 @@ #include #include #include +#include static int do_sleep(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/smbios.c b/cmd/smbios.c index 562dd7959be..ed419f19028 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -280,7 +280,7 @@ static void smbios_print_type3(struct smbios_type3 *table) int i; u8 *addr = (u8 *)table + offsetof(struct smbios_type3, sku_number); - printf("Baseboard Information\n"); + printf("Chassis Information\n"); smbios_print_str("Manufacturer", table, table->manufacturer); printf("\tType: 0x%02x\n", table->chassis_type); smbios_print_str("Version", table, table->version); diff --git a/cmd/smccc.c b/cmd/smccc.c index 3a4d885e37e..fa04bb05ca4 100644 --- a/cmd/smccc.c +++ b/cmd/smccc.c @@ -9,6 +9,7 @@ #include #include #include +#include static int do_call(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/spawn.c b/cmd/spawn.c index 37737b8627c..8829aa9728d 100644 --- a/cmd/spawn.c +++ b/cmd/spawn.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/cmd/stackprot_test.c b/cmd/stackprot_test.c index e7ff4a06158..78e9beba5bf 100644 --- a/cmd/stackprot_test.c +++ b/cmd/stackprot_test.c @@ -4,6 +4,7 @@ */ #include +#include static int do_test_stackprot_fail(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/strings.c b/cmd/strings.c index 5bcb0f2b567..beac2a6e6b3 100644 --- a/cmd/strings.c +++ b/cmd/strings.c @@ -9,6 +9,7 @@ #include #include #include +#include static char *start_addr, *last_addr; diff --git a/cmd/test.c b/cmd/test.c index b4c3eabf9f6..a9ac07e6143 100644 --- a/cmd/test.c +++ b/cmd/test.c @@ -7,7 +7,9 @@ #include #include #include +#include #include +#include #define OP_INVALID 0 #define OP_NOT 1 @@ -26,6 +28,7 @@ #define OP_INT_GT 14 #define OP_INT_GE 15 #define OP_FILE_EXISTS 16 +#define OP_REGEX 17 const struct { int arg; @@ -49,6 +52,9 @@ const struct { {0, "-z", OP_STR_EMPTY, 2}, {0, "-n", OP_STR_NEMPTY, 2}, {0, "-e", OP_FILE_EXISTS, 4}, +#ifdef CONFIG_REGEX + {1, "=~", OP_REGEX, 3}, +#endif }; static int do_test(struct cmd_tbl *cmdtp, int flag, int argc, @@ -141,6 +147,20 @@ static int do_test(struct cmd_tbl *cmdtp, int flag, int argc, case OP_FILE_EXISTS: expr = file_exists(ap[1], ap[2], ap[3], FS_TYPE_ANY); break; +#ifdef CONFIG_REGEX + case OP_REGEX: { + struct slre slre; + + if (slre_compile(&slre, ap[2]) == 0) { + printf("Error compiling regex: %s\n", slre.err_str); + expr = 0; + break; + } + + expr = slre_match(&slre, ap[0], strlen(ap[0]), NULL); + break; + } +#endif } switch (op) { diff --git a/cmd/timer.c b/cmd/timer.c index 04fcd84ac6a..427309e108d 100644 --- a/cmd/timer.c +++ b/cmd/timer.c @@ -6,6 +6,7 @@ #include #include +#include static int do_timer(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index a62862e94f9..346e21d27bb 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -113,7 +113,7 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; if (argc == 4) { algo = tpm2_name_to_algorithm(argv[3]); - if (algo < 0) + if (algo == TPM2_ALG_INVAL) return CMD_RET_FAILURE; } algo_len = tpm2_algorithm_to_len(algo); @@ -157,7 +157,7 @@ static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; if (argc == 4) { algo = tpm2_name_to_algorithm(argv[3]); - if (algo < 0) + if (algo == TPM2_ALG_INVAL) return CMD_RET_FAILURE; } algo_len = tpm2_algorithm_to_len(algo); @@ -288,7 +288,7 @@ static int do_tpm2_pcrallocate(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; algo = tpm2_name_to_algorithm(argv[1]); - if (algo == -EINVAL) + if (algo == TPM2_ALG_INVAL) return CMD_RET_USAGE; ret = get_tpm(&dev); diff --git a/cmd/ufs.c b/cmd/ufs.c index 6e21fbb1685..790dab50f18 100644 --- a/cmd/ufs.c +++ b/cmd/ufs.c @@ -8,6 +8,7 @@ #include #include #include +#include static int do_ufs(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/cmd/upl.c b/cmd/upl.c index c9a823bbc06..ef2183d8528 100644 --- a/cmd/upl.c +++ b/cmd/upl.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index 289865515ef..91130453039 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c index 94e602b8a5b..3876d163236 100644 --- a/cmd/x86/zboot.c +++ b/cmd/x86/zboot.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_BOOT #include +#include #include #include #include diff --git a/cmd/ximg.c b/cmd/ximg.c index 29d7c3279b3..e97167a79cc 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -27,6 +27,7 @@ #include #include #include +#include static int do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -206,11 +207,18 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) break; #ifdef CONFIG_GZIP case IH_COMP_GZIP: - printf(" Uncompressing part %d ... ", part); - if (gunzip((void *) dest, unc_len, - (uchar *) data, &len) != 0) { - puts("GUNZIP ERROR - image not loaded\n"); - return 1; + { + int ret = 0; + printf(" Uncompressing part %d ... ", part); + ret = gunzip((void *)dest, unc_len, + (uchar *)data, &len); + if (ret == Z_BUF_ERROR) { + puts("Image too large: increase CONFIG_SYS_XIMG_LEN\n"); + return 1; + } else if (ret != 0) { + puts("GUNZIP ERROR - image not loaded\n"); + return 1; + } } break; #endif diff --git a/common/Kconfig b/common/Kconfig index be517b80eb5..17539079f90 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -727,6 +727,13 @@ config BOARD_EARLY_INIT_R relocation. With this option, U-Boot calls board_early_init_r() in the post-relocation init sequence. +config BOARD_INIT + bool "Call board-specific init board_init() during init-calls" + default y if ARM || RISCV || SANDBOX + help + Some boards need an board_init() function called during the initcall + phase of startup. + config BOARD_POSTCLK_INIT bool "Call board_postclk_init" help diff --git a/common/Makefile b/common/Makefile index e589f307262..d62ea34599e 100644 --- a/common/Makefile +++ b/common/Makefile @@ -20,9 +20,11 @@ obj-y += version.o obj-y += board_f.o obj-y += board_r.o ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD +ifneq ($(CONFIG_SYS_ARM_ARCH),7) CFLAGS_REMOVE_board_f.o := $(LTO_CFLAGS) CFLAGS_REMOVE_board_r.o := $(LTO_CFLAGS) endif +endif obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o diff --git a/common/board_r.c b/common/board_r.c index 41c8dec8d49..143d51d0633 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include @@ -145,7 +144,7 @@ static int initr_reloc_global_data(void) */ fixup_cpu(); #endif -#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR +#ifdef CONFIG_ENV_RELOC_GD_ENV_ADDR /* * Relocate the early env_addr pointer unless we know it is not inside * the binary. Some systems need this and for the rest, it doesn't hurt. @@ -443,9 +442,6 @@ static int should_load_env(void) if (IS_ENABLED(CONFIG_OF_CONTROL)) return ofnode_conf_read_int("load-environment", 1); - if (IS_ENABLED(CONFIG_DELAY_ENVIRONMENT)) - return 0; - return 1; } @@ -649,8 +645,7 @@ static void initcall_run_r(void) #if CONFIG_IS_ENABLED(ADDR_MAP) INITCALL(init_addr_map); #endif -#if CONFIG_IS_ENABLED(ARM) || CONFIG_IS_ENABLED(RISCV) || \ - CONFIG_IS_ENABLED(SANDBOX) +#if CONFIG_IS_ENABLED(BOARD_INIT) INITCALL(board_init); /* Setup chipselects */ #endif /* diff --git a/common/menu.c b/common/menu.c index 5a2126aa01a..ae5afa14766 100644 --- a/common/menu.c +++ b/common/menu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -436,6 +437,29 @@ int menu_destroy(struct menu *m) return 1; } +static int bootmenu_conv_shortcut_key(struct bootmenu_data *menu, int ichar) +{ + int shortcut_key; + + ichar = tolower(ichar); + switch (ichar) { + /* a-z for bootmenu entry > 9 */ + case 'a' ... 'z': + shortcut_key = ichar - 'a' + 9; + break; + /* 1-9 for bootmenu entry <= 9 */ + case '1' ... '9': + shortcut_key = ichar - '1'; + break; + /* Reserve 0 for last option (aka Exit) */ + case '0': + default: + return -1; + } + + return shortcut_key; +} + enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, struct cli_ch_state *cch) { @@ -443,12 +467,12 @@ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, int i, c; while (menu->delay > 0) { + int ichar; + if (ansi) printf(ANSI_CURSOR_POSITION, menu->count + 5, 3); printf("Hit any key to stop autoboot: %d ", menu->delay); for (i = 0; i < 100; ++i) { - int ichar; - if (!tstc()) { schedule(); mdelay(10); @@ -470,6 +494,11 @@ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, case 0x3: /* ^C */ key = BKEY_QUIT; break; + case 'A' ... 'Z': + case 'a' ... 'z': + case '0' ... '9': + key = BKEY_SHORTCUT; + break; default: key = BKEY_NONE; break; @@ -477,6 +506,9 @@ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, break; } + if (key == BKEY_SHORTCUT) + cch->shortcut_key = bootmenu_conv_shortcut_key(menu, ichar); + if (menu->delay < 0) break; @@ -524,6 +556,11 @@ enum bootmenu_key bootmenu_conv_key(int ichar) case ' ': key = BKEY_SPACE; break; + case 'A' ... 'Z': + case 'a' ... 'z': + case '0' ... '9': + key = BKEY_SHORTCUT; + break; default: key = BKEY_NONE; break; @@ -554,5 +591,8 @@ enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu, key = bootmenu_conv_key(c); + if (key == BKEY_SHORTCUT) + cch->shortcut_key = bootmenu_conv_shortcut_key(menu, c); + return key; } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 77cf04d38ed..9a17ccb2d3d 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -80,7 +80,7 @@ config SPL_MAX_SIZE default 0x1b000 if AM33XX && !TI_SECURE_DEVICE default 0xec00 if OMAP34XX default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB - default 0xbfa0 if MACH_SUN50I_H616 + default 0xbfa0 if MACH_SUN50I_H616 || MACH_SUN50I_A133 default 0x7000 if RCAR_GEN3 default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0 default 0x7fa0 if ARCH_SUNXI @@ -423,7 +423,7 @@ config SPL_STACK default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x118000 if MACH_SUN50I_H6 default 0x52a00 if MACH_SUN50I_H616 - default 0x40000 if MACH_SUN8I_R528 + default 0x40000 if MACH_SUN8I_R528 || MACH_SUN50I_A133 default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x18000 if MACH_SUN9I default 0x8000 if ARCH_SUNXI @@ -488,7 +488,7 @@ config SPL_CUSTOM_SYS_MALLOC_ADDR config SPL_SYS_MALLOC_SIZE hex "Size of the SPL malloc pool" depends on SPL_SYS_MALLOC - default 0x180000 if BIOSEMU && RISCV + default 0x800000 if RISCV default 0x100000 config SPL_READ_ONLY @@ -1138,6 +1138,7 @@ config SPL_DM_SPI_FLASH config SPL_NET bool "Support networking" depends on !NET_LWIP + select SPL_USE_TINY_PRINTF_POINTER_SUPPORT if SPL_USE_TINY_PRINTF help Enable support for network devices (such as Ethernet) in SPL. This permits SPL to load U-Boot over a network link rather than diff --git a/common/spl/spl.c b/common/spl/spl.c index 76fd56dfe4b..d8e26605d20 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -392,7 +392,7 @@ int spl_load(struct spl_image_info *spl_image, } #endif -__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +__weak void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); @@ -689,7 +689,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) BOOT_DEVICE_NONE, BOOT_DEVICE_NONE, }; - spl_jump_to_image_t jump_to_image = &jump_to_image_no_args; + spl_jump_to_image_t jumper = &jump_to_image; struct spl_image_info spl_image; int ret, os; @@ -783,20 +783,20 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } else if (CONFIG_IS_ENABLED(ATF) && os == IH_OS_ARM_TRUSTED_FIRMWARE) { debug("Jumping to U-Boot via ARM Trusted Firmware\n"); spl_fixup_fdt(spl_image_fdt_addr(&spl_image)); - jump_to_image = &spl_invoke_atf; + jumper = &spl_invoke_atf; } else if (CONFIG_IS_ENABLED(OPTEE_IMAGE) && os == IH_OS_TEE) { debug("Jumping to U-Boot via OP-TEE\n"); spl_board_prepare_for_optee(spl_image_fdt_addr(&spl_image)); - jump_to_image = &jump_to_image_optee; + jumper = &jump_to_image_optee; } else if (CONFIG_IS_ENABLED(OPENSBI) && os == IH_OS_OPENSBI) { debug("Jumping to U-Boot via RISC-V OpenSBI\n"); - jump_to_image = &spl_invoke_opensbi; + jumper = &spl_invoke_opensbi; } else if (CONFIG_IS_ENABLED(OS_BOOT) && os == IH_OS_LINUX) { debug("Jumping to Linux\n"); if (IS_ENABLED(CONFIG_SPL_OS_BOOT)) spl_fixup_fdt((void *)SPL_PAYLOAD_ARGS_ADDR); spl_board_prepare_for_linux(); - jump_to_image = &jump_to_image_linux; + jumper = &jump_to_image_linux; } else { debug("Unsupported OS image.. Jumping nevertheless..\n"); } @@ -848,7 +848,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (CONFIG_IS_ENABLED(RELOC_LOADER)) { int ret; - ret = spl_reloc_jump(&spl_image, jump_to_image); + ret = spl_reloc_jump(&spl_image, jumper); if (ret) { if (xpl_phase() == PHASE_VPL) printf("jump failed %d\n", ret); @@ -856,7 +856,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } } - jump_to_image(&spl_image); + jumper(&spl_image); } /* diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index f426a068ff9..8b7cafa7291 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -16,6 +16,7 @@ #include #include #include +#include static int fat_registered; diff --git a/common/usb.c b/common/usb.c index 7a8435296c6..6a4ad346f4b 100644 --- a/common/usb.c +++ b/common/usb.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index d87c4754a30..53c9c236929 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -24,7 +24,7 @@ CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5208EVBe" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 8aa806894be..98e5f546dd3 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -31,7 +31,7 @@ CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="u-boot.bin" CONFIG_USE_HOSTNAME=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index c76d6556dbe..8ffd3237bc5 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -30,7 +30,7 @@ CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="u-boot.bin" CONFIG_USE_HOSTNAME=y diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index ed1446d81cb..d2626d6b8de 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -21,7 +21,7 @@ CONFIG_LOOPW=y CONFIG_CMD_MX_CYCLIC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index a1ce8ddf729..e3b1f114e1b 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -24,8 +24,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5253DEMO" # CONFIG_BLOCK_CACHE is not set diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 754b43eabbc..ca82470d61a 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5272C3" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 599eaf7b9ce..5baea74d413 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -29,8 +29,8 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_DM_I2C=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 2786c673fb9..399b270add4 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -24,7 +24,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5282EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index db3ae65b8ab..6548528ee11 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -24,7 +24,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5329EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 0cbde6ea8c2..e229bd78dc1 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5329EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index ba55e1115b6..980f4a43db5 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5373EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 004f7505e7d..62c663be831 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.0.3" CONFIG_USE_NETMASK=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 37fe5134449..e9e4fe28f9a 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -103,6 +103,5 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_ADDR_MAP=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 4bc3ebe3d52..182b395462f 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -102,5 +102,4 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 6fcc7271d97..65ebb6c341c 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -102,5 +102,4 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 2a22b8ac9d8..0ad65759f38 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -78,7 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0xc000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -132,7 +132,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index f21d79e9d7d..4797994a072 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -96,7 +96,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index d2ac0b47f53..db45b859db9 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -68,7 +68,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -117,7 +117,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 49130342f12..24190ac40e9 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -70,7 +70,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -119,7 +119,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 56e7357e550..6704d32fba0 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -77,7 +77,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0xc000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -131,7 +131,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index e1dc33496ca..e5ccb437398 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -95,7 +95,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 1beb5bb1c0f..505fd7b604c 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -67,7 +67,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -116,7 +116,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index a9275e5d22d..3b7b7bcf472 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -69,7 +69,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -118,7 +118,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index d180f3476e6..c4793830bb3 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -79,7 +79,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -135,7 +135,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 6237f630866..60e1cea9f8a 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -98,7 +98,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 4237dc960ff..551ddfaba25 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -69,7 +69,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -119,7 +119,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 3b5f6beed86..c13ebee53d9 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -71,7 +71,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -121,7 +121,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 25c51c2f0c2..8fa122e1059 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -78,7 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -134,7 +134,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index dc181151385..819d54b1b35 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -97,7 +97,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 5324e7bfaea..699f9f546e8 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -68,7 +68,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -118,7 +118,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 7bfa4ebeb84..895662546b1 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -70,7 +70,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -120,7 +120,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index c8897148fad..67036016470 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -78,7 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0xc000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -147,7 +147,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index d1e097e4d6c..5599914455e 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -69,7 +69,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -129,7 +129,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index ad7d5b637fb..5b64d8b30f9 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -71,7 +71,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -131,7 +131,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 0391d36a83c..eb8e4e5d0c9 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -109,7 +109,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 2d5c83c84d4..df94be4e3df 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -77,7 +77,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0xc000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -146,7 +146,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 679c6fe7ccd..a0cf4ba1d46 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -68,7 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -128,7 +128,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 2ccb202eb3d..390c5614047 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -70,7 +70,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -130,7 +130,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 6b7e2b5a163..e7740064d2b 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -108,7 +108,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 118f510e388..3c8bced6eec 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -80,7 +80,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x60000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -149,7 +149,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 6b6b35a08f6..7c6b6c57338 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -71,7 +71,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -131,7 +131,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index e30b54144a5..ad5babc4342 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -73,7 +73,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:128k(dtb),6016k(kernel),57088k(fs CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -133,7 +133,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index f262fa74394..a24aae42103 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -111,7 +111,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index ec80871222d..68feffd62f5 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -82,7 +82,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0xc000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -152,7 +152,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 0a658738100..e81325262b8 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -73,7 +73,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb) CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -134,7 +134,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index ce95ab8fb54..53f33faf971 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -75,7 +75,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb) CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -136,7 +136,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 8c0ce04b775..8be6d91e5fd 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -114,7 +114,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 618e8272614..f4bdfb7b1bd 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -81,7 +81,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0xc000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -151,7 +151,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index eb9ee653f3b..4d5df6579e2 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -72,7 +72,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb), CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -133,7 +133,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index f73ddc34b2a..4b16b53449a 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -74,7 +74,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb), CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -135,7 +135,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 492888672d0..95e004b4b44 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -113,7 +113,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 76b42cb6a15..71b02050c56 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -103,7 +103,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 008c87b7219..6b8e8d9de4c 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -98,7 +98,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index c01fc869322..3f12aca2dc4 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -58,7 +58,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -100,7 +100,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index fef52a61a51..1511fd7710c 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -95,7 +95,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index bb5e185ef61..14860ab9bc4 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -38,7 +38,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=20000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_PCA953X=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 159232d28ca..732a0c4e645 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -39,7 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=20000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 37dfdb4c7b3..d78d89ee07f 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 72630f12195..5e2a8739242 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -125,7 +125,8 @@ CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 8d48b399fb4..86fb67c66c8 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -128,7 +128,8 @@ CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 01a85947d87..e03fcb63d19 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 26de5bf8b3a..f3f5c27dd0b 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -125,7 +125,8 @@ CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 674246aaa7d..36d855a1ac9 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -128,7 +128,8 @@ CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 8d7ca9bbbb0..67e606548a6 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -141,7 +141,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 3ba3022d77e..b9fd336a35a 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -135,7 +135,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c1230f7e645..631789b0585 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -30,7 +30,6 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -# CONFIG_SYS_MALLOC_F is not set CONFIG_MP=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y @@ -60,7 +59,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000 CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y @@ -110,7 +109,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 1cdcd0d52f9..3e66d47a257 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -138,7 +138,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index a0dbbd0c54d..841f72ed73d 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -97,7 +97,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index b52112fcba5..1eadcce3ba7 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -110,7 +110,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 63db57b809f..c3589b19a7e 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -137,7 +137,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 04cc53d9392..becc99eff8f 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -131,7 +131,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 26c479f026a..51766dac9c0 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -134,7 +134,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 995dc7e9ef2..e7f2b02a410 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -139,7 +139,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index a66dba3c115..92defbe55b5 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -133,7 +133,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 8a87a1b3a3f..f37117d3c9d 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -136,7 +136,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 8d03c7d9171..cf0b7418fac 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -120,7 +120,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 395a27eb30e..467d61d73df 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -29,7 +29,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index a53795f5900..75eb0618454 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -30,7 +30,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 6d0130949b7..932739e5dec 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -29,7 +29,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index b1997264797..5ec2cba670b 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -30,7 +30,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index bb09354f716..5c43503ff32 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -48,7 +48,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k( CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 674ad6c06ee..208bbb163f4 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -54,7 +54,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),1 CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am335x-evm am335x-bone am335x-sancloud-bbe am335x-sancloud-bbe-lite am335x-sancloud-bbe-extended-wifi am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle am335x-bonegreen-eco" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index d53d1b6e906..5fd3e96abb1 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -45,7 +45,7 @@ CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bone CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index c550e5e121e..4f8fd5b740c 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -66,8 +66,8 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index 55f1519f0e0..b224f8635a4 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -41,7 +41,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),1 CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle am335x-bonegreen-eco" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index 1bf7b5f8a12..fd8aa3dbfa8 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -43,7 +43,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),1 CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle am335x-bonegreen-eco" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 19943881973..c36658a1cfe 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -65,11 +65,11 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="config" CONFIG_ENV_UBI_VOLUME_REDUND="config_r" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index 09753fdbd06..07367fc66b4 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 2dfcd182cca..0e1fef8b722 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -58,9 +58,9 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 61527e2724a..65d17598a02 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -56,9 +56,9 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index da9c1b3d753..1fb1518b4c3 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -60,8 +60,8 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 46e9e49a377..05a371e92ad 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -59,8 +59,8 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 1a48c05f06e..32c8e9bd39f 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -55,10 +55,10 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 0fc4c0f269a..6d41a94738e 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -45,7 +45,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),2 CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index c538c1ae352..7da9241aaa5 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -35,8 +35,8 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 @@ -53,7 +53,7 @@ CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_POWER_TPS65218=y CONFIG_POWER_TPS62362=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 0fe5479757b..cb3a588321e 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -42,7 +42,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),2 CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 8dab015991e..3ae06f25c3c 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -51,7 +51,7 @@ CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 419bcb7aed3..6c4d6eeb57b 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -41,7 +41,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),2 CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index 75725e179d7..cc444ac2817 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -36,8 +36,8 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 @@ -54,7 +54,7 @@ CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_POWER_TPS65218=y CONFIG_POWER_TPS62362=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index ab45f5f7f10..911715e6141 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -57,8 +57,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk" # CONFIG_ENV_IS_IN_FAT is not set -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index e1fd680803f..8d94b3ebf3d 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -50,8 +50,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk" # CONFIG_ENV_IS_IN_FAT is not set -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index d865b123b90..c3b6eb8c897 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -54,9 +54,9 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 4ea551b509b..52df6e0ca3f 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -59,7 +59,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index f2e1f31ef0f..21a381e8113 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config index 16cd4c89f41..373b1d0ed64 100644 --- a/configs/am62x_a53_usbdfu.config +++ b/configs/am62x_a53_usbdfu.config @@ -1,4 +1,3 @@ -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 7ca5f58ea0c..a184989ea50 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -62,7 +62,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 4e3ed7801e6..162be534ce4 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -69,7 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/am62x_evm_r5_ethboot_defconfig b/configs/am62x_evm_r5_ethboot_defconfig index 0d823743907..96b2c28825f 100644 --- a/configs/am62x_evm_r5_ethboot_defconfig +++ b/configs/am62x_evm_r5_ethboot_defconfig @@ -9,7 +9,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_MMC=n CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 -CONFIG_SPL_BSS_MAX_SIZE=0X3100 +CONFIG_SPL_BSS_MAX_SIZE=0x3100 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_ETH=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 8f7d098f770..fd2b28a1c6e 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y @@ -144,6 +143,8 @@ CONFIG_TI_ICSSG_PRUETH=y CONFIG_NVME_PCI=y CONFIG_PCI_CONFIG_HOST_BRIDGE=y CONFIG_PCIE_CDNS_TI=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCIE_CDNS_TI_EP=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index b222bcd6e43..fdf5d7803bb 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x80000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -81,7 +80,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index a41f67a43fe..438ec8a1c56 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -72,9 +71,9 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 386749ebabd..7d3eb6f8c93 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x55000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -74,7 +73,7 @@ CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index b0d333d95c2..3ac494f0126 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x57000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 90a857b8b95..63ba94ff90e 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x55000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -60,7 +59,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/am67a_beagley_ai_r5_defconfig b/configs/am67a_beagley_ai_r5_defconfig index ebd4e50e34e..b0a95da1086 100644 --- a/configs/am67a_beagley_ai_r5_defconfig +++ b/configs/am67a_beagley_ai_r5_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig index d224583f56a..e1c5d9b7fb9 100644 --- a/configs/amd_versal2_mini_defconfig +++ b/configs/amd_versal2_mini_defconfig @@ -60,7 +60,7 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_GPIO is not set diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig index 3afc6cb2736..42bab43a72b 100644 --- a/configs/amd_versal2_mini_emmc_defconfig +++ b/configs/amd_versal2_mini_emmc_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig index 54328e85784..c2934625f2e 100644 --- a/configs/amd_versal2_mini_ospi_defconfig +++ b/configs/amd_versal2_mini_ospi_defconfig @@ -54,7 +54,7 @@ CONFIG_SYS_PROMPT="versal2> " CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_GPIO is not set diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig index 48fb7ae0e7f..1c61ae821a9 100644 --- a/configs/amd_versal2_mini_qspi_defconfig +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -54,7 +54,7 @@ CONFIG_SYS_PROMPT="versal2> " CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_GPIO is not set diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 15ac0211828..3ead9f058b3 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -66,8 +66,8 @@ CONFIG_OF_BOARD=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SIMPLE_PM_BUS=y diff --git a/configs/aml-a311d-cc_defconfig b/configs/aml-a311d-cc_defconfig index 6d0d5eb403b..55b77e2a0be 100644 --- a/configs/aml-a311d-cc_defconfig +++ b/configs/aml-a311d-cc_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/aml-s905d3-cc_defconfig b/configs/aml-s905d3-cc_defconfig index 1975c67752b..c73f4981d85 100644 --- a/configs/aml-s905d3-cc_defconfig +++ b/configs/aml-s905d3-cc_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig index cfe388213ef..0ccab4f066f 100644 --- a/configs/an7581_evb_defconfig +++ b/configs/an7581_evb_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_LOG=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index 353aa0abb1f..0fa4eca481b 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -45,7 +45,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6144k # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=25000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 9083bf293f5..87914b538cc 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -45,7 +45,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6336k # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=25000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ap152_defconfig b/configs/ap152_defconfig index 0864bf46d54..aacde07b6e4 100644 --- a/configs/ap152_defconfig +++ b/configs/ap152_defconfig @@ -45,7 +45,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:256k(u-boot),64k(u-boot-env),6336k # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=25000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 15b5153ce4c..dfd586b1c14 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -49,8 +49,8 @@ CONFIG_CMD_UUID=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 73463473dfb..de30fa1b961 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -51,8 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index f51386d10a8..7d54205938e 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -69,8 +69,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 411d6354f8b..e9c9cfe940e 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -45,8 +45,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index b6e259b490b..b479e44667e 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -60,8 +60,8 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_ETHPRIME=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 0ea13d46f31..b0fff63371f 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -60,8 +60,8 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_ETHPRIME=y diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index d2564aa288c..1b08b81eb69 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_SOUND=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig deleted file mode 100644 index 8dd369d68a1..00000000000 --- a/configs/astro_mcf5373l_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_M68K=y -CONFIG_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_LEN=0x20000 -CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_SECT_SIZE=0x8000 -CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l" -CONFIG_SYS_MONITOR_LEN=262144 -CONFIG_SYS_LOAD_ADDR=0x20000 -CONFIG_ENV_ADDR=0x1FF8000 -CONFIG_TARGET_ASTRO_MCF5373L=y -CONFIG_SYS_MONITOR_BASE=0x00000400 -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="protect off 0x80000 0x1ffffff;run env_check;run xilinxload&&run alteraload&&bootm 0x80000;update;reset" -CONFIG_SYS_PBSIZE=281 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="URMEL > " -CONFIG_CMD_IMLS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_JFFS2=y -CONFIG_NO_NET=y -CONFIG_FPGA_ALTERA=y -CONFIG_FPGA_CYCLON2=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_SPARTAN3=y -CONFIG_SYS_FPGA_PROG_FEEDBACK=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_FSL=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_SHOW_PROGRESS=0 -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_SECT=259 -CONFIG_DM_RTC=y -CONFIG_MCFRTC=y -CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 -CONFIG_MCFUART=y -CONFIG_WDT=y -CONFIG_WDT_MCF=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 9b077097c69..56250bf84ec 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index dafbc768fde..8befb11930a 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 4ee101ff641..02890de8259 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -39,8 +39,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 09095e9499c..bfb2ee28951 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index d594d96cfd9..16c3b0cb019 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index f53bf3c0450..1f62bbf7a81 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -39,8 +39,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 9bfda68255e..9b083ec36b7 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 9bfda68255e..9b083ec36b7 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index e51581848ac..e860376aa70 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -42,8 +42,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 488c370581a..dcf6b417990 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x107D0000 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index d8c490d80de..337ba577fd9 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x107D0000 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index 211b20bd0ab..759eea6ee6c 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index f6529b1be32..31ef371dbb9 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 580960e8181..2e5e38a62b3 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -39,8 +39,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index 273e93c5185..a7d5f76987a 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index c4d12524282..719f0b47766 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -41,8 +41,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 752031697ce..2095ebce100 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index adf3c104f3e..3a51cd39d3f 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index e68f5036ca7..92972325a75 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -39,8 +39,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 796181b0470..4d3cd7fdb40 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index e57bd2c8296..c4fc3d6f882 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -44,8 +44,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index c50842a61d4..07dc2e0d316 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -40,7 +40,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index e7b4107f1e5..d266e71aa46 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -40,8 +40,8 @@ CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index cb4f0b548fe..354e5faf666 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -42,7 +42,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 9ebe2de1f2c..189cf430e80 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index 0fef493164e..2a18067c54f 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index c40e99817b9..967331fe147 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index c40319e9f82..0a817d8eea9 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 8db86c777ef..6959d149bd4 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 3f593953140..ac6feb2857c 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -46,8 +46,8 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 12336d0b168..4f2f6fd8538 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 9b077097c69..56250bf84ec 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index dafbc768fde..8befb11930a 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 4ee101ff641..02890de8259 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -39,8 +39,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_GPIO=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 6098e5caf5b..2090822023c 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -75,8 +75,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 8ab5addf90e..a863ea8720f 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -36,7 +36,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index c852bd9eed7..5fcca08058c 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -36,7 +36,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig index 51ef5368b56..cb17acadd43 100644 --- a/configs/bananapi-cm4-cm4io_defconfig +++ b/configs/bananapi-cm4-cm4io_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 1ce163b9cbe..0d05edd817b 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index d6440e33bf5..8088d63baa5 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig index a471f081607..8d24d5f4567 100644 --- a/configs/bananapi-m5_defconfig +++ b/configs/bananapi-m5_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index c32d535e87b..154ad12a4e2 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index ed026e58617..040ef695fec 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -34,8 +34,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DOS_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCMSTB=y diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 07294451100..1eafadf2535 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -36,8 +36,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DOS_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCMSTB=y diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 053c459e05c..2951f98b6b4 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_BCM6345_GPIO=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 8e0c5367352..caf2ae196f8 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -43,8 +43,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig index a25f42f7b6c..d811ab987f3 100644 --- a/configs/beelink-gsking-x_defconfig +++ b/configs/beelink-gsking-x_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig index 489818096c7..3bf832ac8b2 100644 --- a/configs/beelink-gt1-ultimate_defconfig +++ b/configs/beelink-gt1-ultimate_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index b5229ee0377..6ef1d311bd9 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig index fe8e9a8cc0d..cb31d04bf87 100644 --- a/configs/beelink-gtkingpro_defconfig +++ b/configs/beelink-gtkingpro_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 77744d55c3b..30c3fd0f9fb 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -74,7 +74,7 @@ CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_BOOTP_SERVERIP=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 2b72ec91632..fd3b6188776 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_TEXT_BASE=0x3f401000 CONFIG_SYS_MALLOC_LEN=0x402000 -CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x200000 @@ -54,8 +53,8 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=500 CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig index 6219a0b6f69..6d2b92e1ec3 100644 --- a/configs/brcp150_defconfig +++ b/configs/brcp150_defconfig @@ -74,7 +74,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig index 7108410c4ea..44460c510f1 100644 --- a/configs/brcp170_defconfig +++ b/configs/brcp170_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig index bfce7105e00..684800228ef 100644 --- a/configs/brcp1_1r_defconfig +++ b/configs/brcp1_1r_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig index 8ae6608798d..9b45961ef8e 100644 --- a/configs/brcp1_1r_switch_defconfig +++ b/configs/brcp1_1r_switch_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig index ec19180cdf5..357eef38601 100644 --- a/configs/brcp1_2r_defconfig +++ b/configs/brcp1_2r_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index d96fdaa2887..58da63d11dd 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -79,10 +79,10 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas " CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index d468465a9cc..04defac9a71 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts dmas dma-names" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=1500 CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index ee70220ebad..ebc885464a7 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -83,8 +83,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig index f295d70cfe9..2ed54817af4 100644 --- a/configs/brsmarc2_defconfig +++ b/configs/brsmarc2_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 245e4a582f2..2af491b065d 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -73,10 +73,10 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index 4d1bb6e1cc1..318fbaa529b 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -40,8 +40,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 311dd70bc44..01c3117e364 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -45,8 +45,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 93366dbc603..94020c8c1a7 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -68,7 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index d247505ce4c..6349667a18e 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 8cb6b34ce76..1677b671c6b 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -46,8 +46,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.back CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 0f803d9a408..02f7876f2dc 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -58,7 +58,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_OF_PLATDATA=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 3f11b110c92..cbb8beb91c2 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index a955265f9ce..928a713cd1f 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -58,7 +58,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_OF_PLATDATA=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index aa2ef298762..a9dbe33e3d6 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 0fc1279f873..16d14e14621 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -60,7 +60,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index a2231cc314f..b5b3851a010 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 45876f6e81d..7a875d42c3f 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -59,7 +59,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_OF_PLATDATA=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 6e9aa601009..ed1c62330c9 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 42337d7a11e..5e452cf7b79 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -72,7 +72,7 @@ CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_NO_NET=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index c848ebd7f34..d890a344f52 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -59,7 +59,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_OF_PLATDATA=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index a1561fd0d25..3bcf92ed1fa 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index 2b3086b8673..025c37afcff 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_FAT=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_JZ4780_EFUSE=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index b0231068daa..0676b949a27 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -69,7 +69,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_MMC is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SPL_DM=y @@ -99,6 +99,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE3000=y CONFIG_DM_REGULATOR=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index eaa8a333049..ead29d99338 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/cm3588-nas-rk3588_defconfig b/configs/cm3588-nas-rk3588_defconfig index e09451b2490..092612719cc 100644 --- a/configs/cm3588-nas-rk3588_defconfig +++ b/configs/cm3588-nas-rk3588_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 0e916771d9f..4eb86fee70b 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -65,7 +65,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index a7940c2774c..471d6bd3f49 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -65,7 +65,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index d7ce71925e9..ca2eada6291 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -22,7 +22,7 @@ CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_PING=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.100.2" diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index ba65a3c40a6..f1c6373c31e 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -47,8 +47,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 785e8a65f21..26e9b565bd5 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -58,7 +58,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 7dc4a3d042a..431987d3f90 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -50,8 +50,8 @@ CONFIG_CMD_UUID=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 9fc844b3269..1aea1d40c4e 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -68,8 +68,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 7885d0e7da2..6c24f59b28c 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -59,7 +59,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_USE_IPADDR=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index ab6a156e893..e23cc993542 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -47,8 +47,8 @@ CONFIG_CMD_CACHE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_USE_IPADDR=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 05421399042..c8a17cd40a2 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 3a8ea1c1a76..8d7a6bf7060 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -43,8 +43,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 3a806243b19..9a8fc7a4007 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -63,7 +63,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_USE_IPADDR=y diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index d83e24ebf91..203d4ef2300 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 6a49c0a6a23..22df1e9c171 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 49b353542b5..a932dc69d1a 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 6592b11dc48..dca76d9a0ab 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index 60f8f3f707e..31e928c57b9 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index bb3d7213540..a4a2949e8e0 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index c5fb5a9bbe1..d7a6be405f4 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 0e1b22c49d9..2533bb8b50c 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -67,7 +67,7 @@ CONFIG_CMD_EXT4=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="ccdc.img" CONFIG_USE_HOSTNAME=y diff --git a/configs/coreboot64-no-spl_defconfig b/configs/coreboot64-no-spl_defconfig index fe11e5d4880..aadf11e9867 100644 --- a/configs/coreboot64-no-spl_defconfig +++ b/configs/coreboot64-no-spl_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_SOUND=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 706c0cd71d7..719b2f02c1e 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -40,7 +40,7 @@ CONFIG_MAC_PARTITION=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index bd190e40ffc..dfb97a3d302 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 85cd4623c48..fe7d53bcdd8 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -67,8 +67,8 @@ CONFIG_CMD_MTDPARTS=y CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 134b3533250..fac3a85212a 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 3129cbf5f30..645c1649cbf 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/crs305-1g-4s-bit_defconfig b/configs/crs305-1g-4s-bit_defconfig index 4087504dd66..92bff3d0cdb 100644 --- a/configs/crs305-1g-4s-bit_defconfig +++ b/configs/crs305-1g-4s-bit_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index a14a5e83aea..f53526a1431 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/crs326-24g-2s-bit_defconfig b/configs/crs326-24g-2s-bit_defconfig index 815ebefb225..5c81e5bc596 100644 --- a/configs/crs326-24g-2s-bit_defconfig +++ b/configs/crs326-24g-2s-bit_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/crs326-24g-2s_defconfig b/configs/crs326-24g-2s_defconfig index bdd6e84a0a4..3cc2ccfefd2 100644 --- a/configs/crs326-24g-2s_defconfig +++ b/configs/crs326-24g-2s_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/crs328-4c-20s-4s-bit_defconfig b/configs/crs328-4c-20s-4s-bit_defconfig index d1980634f4f..a02420d29c9 100644 --- a/configs/crs328-4c-20s-4s-bit_defconfig +++ b/configs/crs328-4c-20s-4s-bit_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/crs328-4c-20s-4s_defconfig b/configs/crs328-4c-20s-4s_defconfig index 19c48338f94..5fd8ff63446 100644 --- a/configs/crs328-4c-20s-4s_defconfig +++ b/configs/crs328-4c-20s-4s_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 861bfea28e9..c76f6847d85 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -75,7 +75,7 @@ CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 27910a5b9b1..655cb5d4e9e 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -71,7 +71,7 @@ CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index e35a4f43384..c44980e9227 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -41,8 +41,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 79e3f568bf8..f790ba82f0a 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_FS_GENERIC=y # CONFIG_DOS_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 7742bf77482..48aa425f4df 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/db-88f6820-amc_nand_defconfig b/configs/db-88f6820-amc_nand_defconfig index d970cf72be7..1b96ffca2d9 100644 --- a/configs/db-88f6820-amc_nand_defconfig +++ b/configs/db-88f6820-amc_nand_defconfig @@ -59,7 +59,7 @@ CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index b93c717e5b3..33297c7895c 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 5aa19109ed9..5162f70ab9e 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig index 06e52cc41ef..e02d1873c17 100644 --- a/configs/db-xc3-24g4xg_defconfig +++ b/configs/db-xc3-24g4xg_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_DM_I2C=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 33201cec772..90076485527 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -55,7 +55,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=20 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index d9fff4e457e..7cfeba0f24e 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index a00a042ada6..16807f4e77b 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -95,8 +95,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1), CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ALTBOOTCMD="run recovery" diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 9965e00a1d0..3f07dc4b1a0 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -93,8 +93,8 @@ CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index f9cb732357c..53e7a33af3a 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -63,9 +63,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index f6f00454aaa..9b308548951 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -55,9 +55,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 850ccd934b7..f80cfde75ab 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -51,9 +51,9 @@ CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig index 6c175dd73b9..eb873d4f0f0 100644 --- a/configs/draco-etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -69,8 +69,8 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x200000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_USE_ROOTPATH=y diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index 521a090e376..f034e2ea68b 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -66,8 +66,8 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_USE_ROOTPATH=y diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index 2c16db237f8..6a405de8171 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -66,8 +66,8 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_USE_ROOTPATH=y diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index c3bd009ed10..f5bc4e637de 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -34,8 +34,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_CMD_SYSBOOT=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_APQ8016=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index b7c7b64db90..ff2c960983a 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_PMIC=y CONFIG_ENV_IS_IN_EXT4=y CONFIG_ENV_EXT4_INTERFACE="mmc" CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_STUB=y diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig index f4481b88b30..31026c8dbbd 100644 --- a/configs/ds116_defconfig +++ b/configs/ds116_defconfig @@ -59,7 +59,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(u-boot),7040k(kernel),64k(u-boot-env),-(data)" CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index ee2ee60c92c..c32fac153de 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/durian_defconfig b/configs/durian_defconfig index ea1d37e9db6..336c7a5269e 100644 --- a/configs/durian_defconfig +++ b/configs/durian_defconfig @@ -27,7 +27,7 @@ CONFIG_SYS_PROMPT="durian#" # CONFIG_CMD_UNZIP is not set CONFIG_CMD_PCI=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index e4c6aa28e0b..f0e9ff7c447 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -34,9 +34,9 @@ CONFIG_CMD_RNG=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_NO_NET=y CONFIG_CLK_EXYNOS850=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig index 43041039b46..b50e3815178 100644 --- a/configs/eDPU_defconfig +++ b/configs/eDPU_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 5e1791d63f9..e30cd1842c4 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 1c52322768e..00f24533021 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -30,7 +30,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_DM_I2C=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index a8c1b99bb05..c6cd3c74f08 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -28,7 +28,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_DM_I2C=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 1294577ea8f..733b0ebe639 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -34,8 +34,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CPU=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig index c730945f4f9..71d1bbd956e 100644 --- a/configs/efi-x86_app32_defconfig +++ b/configs/efi-x86_app32_defconfig @@ -33,7 +33,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_NO_NET=y diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig index 1831fb2d5a7..9f7b53d0106 100644 --- a/configs/efi-x86_app64_defconfig +++ b/configs/efi-x86_app64_defconfig @@ -37,7 +37,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_NO_NET=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 957fd83e432..e9c5ddf12ad 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 71612d7fb19..b82e10dc3a1 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -31,7 +31,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_INTERFACE="scsi" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 601165be85a..6108b70d75a 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig index 376862ad300..35a5cc9e449 100644 --- a/configs/emsdp_defconfig +++ b/configs/emsdp_defconfig @@ -26,7 +26,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="app.bin" CONFIG_VERSION_VARIABLE=y diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig index e216c2edafd..804b00697a1 100644 --- a/configs/endeavoru_defconfig +++ b/configs/endeavoru_defconfig @@ -51,8 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig index 1f44197d725..b23ba6026ef 100644 --- a/configs/espresso7420_defconfig +++ b/configs/espresso7420_defconfig @@ -22,4 +22,4 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="ESPRESSO7420 # " # CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 2c89f6c2eb5..7f4371aa75f 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_CLK=y diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig index c9d75e0cf8e..16e8a58ccc0 100644 --- a/configs/evb-ast2600_defconfig +++ b/configs/evb-ast2600_defconfig @@ -77,7 +77,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 8a5fb00c034..8a24b0f1461 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -50,7 +50,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 496936bcf12..aac35211369 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -56,7 +56,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_TPL_DM=y CONFIG_REGMAP=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index a456cdc10fa..93588b64eb4 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index b46da229d54..90cbf55806a 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 7a09c2c70ca..116c04c914d 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -39,7 +39,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 025c00c30f6..02347b58c22 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 777c412130f..e63f876220c 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index db71ec4dc35..e1e59d38294 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -40,8 +40,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index b88f5223207..62601fa69a4 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y # CONFIG_ROCKCHIP_IODOMAIN is not set diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 46b94953101..16f7a80588d 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -21,7 +21,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 311d37f0f91..1bbc03ffb82 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -30,8 +30,8 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 3b63537136c..f8b70767d9f 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -52,7 +52,7 @@ CONFIG_OF_LIVE=y # CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 4d07e0b2635..d7b01e67db9 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -45,7 +45,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index fc9610a122c..ab142f8ce86 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index b9e53ecc8fd..f522948a60d 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index fbcc84da9ae..d045120aad2 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -78,11 +78,11 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names" CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="ubi" CONFIG_ENV_UBI_VOLUME="uboot_env0" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_env1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 109e7d0fc6c..3c2bcc6a3c4 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -71,8 +71,8 @@ CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 1fe7d2fc40b..a7a04bfa206 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -133,7 +133,7 @@ CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xFE090000 CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 676b5bc8a28..46209761576 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -47,7 +47,7 @@ CONFIG_OF_LIST="imx6q-bx50v3 imx6q-b850v3 imx6q-b650v3 imx6q-b450v3" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 80f91de7a11..42b5c0c38a8 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -17,7 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/generic-rk3328_defconfig b/configs/generic-rk3328_defconfig index c0225b1afd0..26e010864dc 100644 --- a/configs/generic-rk3328_defconfig +++ b/configs/generic-rk3328_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_RNG=y CONFIG_SPL_OF_CONTROL=y # CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/generic-rk3399_defconfig b/configs/generic-rk3399_defconfig index 383102cddd0..4a95379c931 100644 --- a/configs/generic-rk3399_defconfig +++ b/configs/generic-rk3399_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_RNG=y CONFIG_SPL_OF_CONTROL=y # CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_ADC is not set # CONFIG_USB_FUNCTION_FASTBOOT is not set diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index dd9a501f704..09400bae27a 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -42,7 +42,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y # CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index 695eef085bf..ed2f936b324 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -36,7 +36,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y # CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/configs/grouper_defconfig b/configs/grouper_defconfig index 016fc60b41a..b9068e18b03 100644 --- a/configs/grouper_defconfig +++ b/configs/grouper_defconfig @@ -54,8 +54,8 @@ CONFIG_OF_LIST="tegra30-asus-nexus7-grouper-E1565 tegra30-asus-nexus7-grouper-PM CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index d2cc1cf7981..0f141b6f0a2 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -41,7 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_RZA1_GPIO=y CONFIG_LED=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index 9929d588f37..bde531a6003 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_TFTP_PORT=y CONFIG_TFTP_TSIZE=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index dcb1d4f5694..e046a5ee8b1 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -42,7 +42,7 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_ATA_STRIDE=4 diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 95d5b1172ff..807e48f50e4 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -91,9 +91,9 @@ CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53 CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y CONFIG_USE_IPADDR=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 1d8af5ce103..aae68d3d620 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -95,8 +95,8 @@ CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53 CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y CONFIG_USE_IPADDR=y diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig index ec05c2572e8..9578468bc48 100644 --- a/configs/gxp_defconfig +++ b/configs/gxp_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MISC=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NETCONSOLE=y CONFIG_MISC=y # CONFIG_MMC is not set diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index c38b9e19506..1ff8f818916 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_TEGRA_NAND=y diff --git a/configs/hc2910_2aghd05_defconfig b/configs/hc2910_2aghd05_defconfig index d7cc7d18ed8..2d347a20f16 100644 --- a/configs/hc2910_2aghd05_defconfig +++ b/configs/hc2910_2aghd05_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_GPIO is not set # CONFIG_I2C is not set diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index c9753e13657..f5bb28cb0c7 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -23,9 +23,9 @@ CONFIG_OF_LIST="renesas/r8a774a1-hihope-rzg2m-ex renesas/r8a774b1-hihope-rzg2n-e CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=0 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=0 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_GPIO_HOG=y CONFIG_DM_PCA953X=y CONFIG_SYS_I2C_RCAR_I2C=y diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig index a684994722c..440f257072d 100644 --- a/configs/hikey960_defconfig +++ b/configs/hikey960_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_MMC=y CONFIG_ENV_IS_IN_EXT4=y CONFIG_ENV_EXT4_INTERFACE="mmc" CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_MAX_BLK_COUNT=1024 CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index c4f63619292..59c2101110e 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -28,8 +28,8 @@ CONFIG_CMD_USB=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_HIKEY_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig index 30ee4f39f25..05e4b1ca0f0 100644 --- a/configs/hmibsc_defconfig +++ b/configs/hmibsc_defconfig @@ -42,8 +42,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_OF_UPSTREAM is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_BUTTON_QCOM_PMIC=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index 4c9d2e76866..e44c54821a4 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -41,7 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 2aab639f6a7..60110d85d55 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -40,7 +40,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 17d1c102031..5b8fa3715f4 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 1beb5837bb4..65aca43e8b9 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -41,7 +41,7 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_ATA_STRIDE=4 diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index 6cb2a21ed2d..f088aec8716 100644 --- a/configs/ibex-ast2700_defconfig +++ b/configs/ibex-ast2700_defconfig @@ -66,7 +66,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FS_GENERIC=y CONFIG_DEVICE_TREE_INCLUDES="ast2700-u-boot.dtsi" # CONFIG_OF_TAG_MIGRATE is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_RX_ETH_BUFFER=2 # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_DM_SEQ_ALIAS is not set diff --git a/configs/ibm-sbp1_defconfig b/configs/ibm-sbp1_defconfig index c86a9b33c5d..5f16301e5b5 100644 --- a/configs/ibm-sbp1_defconfig +++ b/configs/ibm-sbp1_defconfig @@ -73,7 +73,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 6ee40e380b2..20074b36862 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -43,7 +43,7 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig index a4feb364b3e..d5befae419d 100644 --- a/configs/ideapad-yoga-11_defconfig +++ b/configs/ideapad-yoga-11_defconfig @@ -50,8 +50,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 0855081c9be..726e357b91b 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -53,11 +53,11 @@ CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="config" CONFIG_ENV_UBI_VOLUME_REDUND="config_r" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NO_NET=y CONFIG_SPL_DM=y diff --git a/configs/imgtec_xilfpga_defconfig b/configs/imgtec_xilfpga_defconfig index 233c89c04ee..c8b12b3a0c0 100644 --- a/configs/imgtec_xilfpga_defconfig +++ b/configs/imgtec_xilfpga_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y # CONFIG_ISO_PARTITION is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/imx28_btt3_defconfig b/configs/imx28_btt3_defconfig new file mode 100644 index 00000000000..07c805faa2f --- /dev/null +++ b/configs/imx28_btt3_defconfig @@ -0,0 +1,140 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX28=y +CONFIG_TEXT_BASE=0x40002000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="nxp/mxs/imx28-btt3-1" +CONFIG_TARGET_BTT=y +CONFIG_SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT=y +CONFIG_SPL_MXS_PMU_DISABLE_BATT_CHARGE=y +# CONFIG_SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR is not set +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x80000 +CONFIG_MULTI_DTB_FIT_USER_DEF_ADDR=0x43000000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK=0x20000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_TEXT_BASE=0x1000 +CONFIG_SYS_LOAD_ADDR=0x42000000 +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SPL_SIZE_LIMIT=0xa000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x90000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=458752 +CONFIG_TIMESTAMP=y +CONFIG_FIT=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_VBE is not set +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200n8" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ${bootpri} ; run ${bootsec}" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run prebootcmd" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0 +CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y +CONFIG_SPL_DMA=y +CONFIG_SPL_MMC_TINY=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x44000000 +CONFIG_SPL_FALCON_BOOT_MMCSD=y +CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x40 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SYS_SPI_KERNEL_OFFS=0x100000 +CONFIG_SYS_SPI_ARGS_OFFS=0x80000 +CONFIG_SYS_SPI_ARGS_SIZE=0x8000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_SPL=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_BOARD=y +CONFIG_OF_LIST="nxp/mxs/imx28-btt3-0 nxp/mxs/imx28-btt3-1 nxp/mxs/imx28-btt3-2" +CONFIG_MULTI_DTB_FIT_GZIP=y +CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent interrupts" +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_SPL_OF_PLATDATA_PARENT is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y +CONFIG_USE_BOOTFILE=y +CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="btt3" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_DEVRES=y +CONFIG_MXS_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_MXS=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=1 +CONFIG_PHY_FIXED=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MXS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXS_SPI=y +CONFIG_SPL_CRC8=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index bf80a19bd96..8715893bbcc 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -94,7 +94,7 @@ CONFIG_SPL_OF_PLATDATA=y # CONFIG_SPL_OF_PLATDATA_PARENT is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_HOSTNAME=y diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index c7751b5dc93..d7b54baa749 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -62,7 +62,7 @@ CONFIG_SPL_OF_PLATDATA=y # CONFIG_SPL_OF_PLATDATA_PARENT is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_HOSTNAME=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 4352e3871f5..13421d478ca 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -48,7 +48,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel) CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 95797ff0f12..87e8d2ac5b3 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -57,6 +57,7 @@ CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/imx6dl_sielaff_defconfig b/configs/imx6dl_sielaff_defconfig index a364e2c9cdd..6673e1e6915 100644 --- a/configs/imx6dl_sielaff_defconfig +++ b/configs/imx6dl_sielaff_defconfig @@ -62,7 +62,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 017c27479d2..6f0ef2eaee3 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -76,8 +76,8 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 2c7b8cc2c44..d6293c58ede 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -49,7 +49,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel) CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index fd251e7cdd8..997e406a057 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -68,7 +68,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index cf4c2d9c6f1..c322fd3eff1 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -60,7 +60,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 269fe271a76..0b82fbecbee 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -69,7 +69,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_LIST="imx6q-icore imx6dl-icore" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ALTBOOTCMD="run recoveryboot" diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 2c7b8cc2c44..d6293c58ede 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -49,7 +49,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel) CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 49feb1af830..8520f90c867 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index a5c3b486987..db1f54ecedc 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -60,5 +60,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 187fae80ff9..79491674ea5 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -50,7 +50,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel) CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -66,5 +66,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index f285b82e6dc..559c833c232 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -60,5 +60,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index fe70c199288..c7fc61dd7ea 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -50,7 +50,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel) CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y @@ -66,5 +66,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index 436bfb78cc2..43862d2573d 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -40,9 +40,11 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX6UL=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_FLASH=y diff --git a/configs/imx6ulz_smm_m2b_defconfig b/configs/imx6ulz_smm_m2b_defconfig new file mode 100644 index 00000000000..c0eb1093d8b --- /dev/null +++ b/configs/imx6ulz_smm_m2b_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TEXT_BASE=0x87800000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULZ_SMM_M2=y +CONFIG_BSH_M2B_MEMORY=y +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6ulz-bsh-smm-m2" +CONFIG_SPL_SERIAL=y +CONFIG_SPL_BSS_START_ADDR=0x84100000 +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_DMA=y +CONFIG_SPL_MTD=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(nandboot),1m(env),8m(kernel),1m(nanddtb),-(rootfs)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_NO_NET=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_SYS_I2C_MXC=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x111400 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x291400 +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_SPL_USB_HOST=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="BSH" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x877fffc0 +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig index a04008c57d8..6c5be29448f 100644 --- a/configs/imx7_cm_defconfig +++ b/configs/imx7_cm_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NET_RANDOM_ETHADDR=y @@ -92,6 +92,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config index 37e11e518a8..07390037c46 100644 --- a/configs/imx8m_data_modul.config +++ b/configs/imx8m_data_modul.config @@ -198,12 +198,12 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_PBSIZE=2081 CONFIG_SYS_PROMPT="u-boot=> " -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_TEXT_BASE=0x40200000 CONFIG_TFTP_TSIZE=y CONFIG_USB=y diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index dbc439c23f5..5cb7ffd48c5 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -77,8 +77,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index ea6a8789eea..be0add6c176 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -79,9 +79,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 42926587722..544fcbf5d68 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -58,8 +58,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 86a14547095..c27bdaa15d1 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -58,8 +58,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 8a4bb896663..eb8e90a1251 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -91,9 +91,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 2b3c0969cfd..7c8a2060b1a 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -73,9 +73,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_COMPOSITE_CCF=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 27007bd8687..06cc4bb7dde 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -74,9 +74,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 81510a10a1f..5e60c9d3a08 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -77,9 +77,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 5230f7327db..c15372edc9c 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -21,6 +21,11 @@ CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL=y +CONFIG_EFI_MM_COMM_TEE=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y @@ -46,22 +51,31 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_CMD_CPU=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_CMD_OPTEE=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" @@ -70,8 +84,10 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_DFU_MMC=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -103,6 +119,8 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -118,3 +136,4 @@ CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y +CONFIG_SHA384=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index 902585b3b6d..f364e17bab2 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -62,8 +62,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index 58dd8eb83f6..cd6db3ad025 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -62,8 +62,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_COMPOSITE_CCF=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 051cd7efa81..c7e630335f3 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -61,11 +61,16 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_SETEXPR_FMT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y @@ -81,10 +86,11 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw75xx-0x" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" @@ -101,10 +107,14 @@ CONFIG_CLK_IMX8MM=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index a5bc8aea027..b71cdbb2e4e 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -82,9 +82,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 32d2a1599c8..bb483653db2 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -83,9 +83,9 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index 835654d2b63..f163871bfaa 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -82,9 +82,9 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 206d216394d..c83f6a99a7e 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -62,7 +62,7 @@ CONFIG_MTDPARTS_DEFAULT="gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),1m CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_REGMAP=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index ef486f51eee..58550c6c332 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_REGMAP=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 3cc7d2b6b13..f871bf1653d 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -65,8 +65,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index d45c83951ef..2df89f90757 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -23,6 +23,12 @@ CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_MM_COMM_TEE=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y @@ -55,26 +61,37 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE=y +CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y +CONFIG_DFU_MMC=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y @@ -99,11 +116,17 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y +CONFIG_SPL_RSA=y +CONFIG_SHA384=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 0596e33fa04..875ddcaaaa4 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -59,9 +59,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index fd8701e11a4..3cdbcec1eed 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -62,10 +62,15 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_SETEXPR_FMT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y @@ -81,9 +86,10 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" @@ -98,10 +104,14 @@ CONFIG_CLK_IMX8MN=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index b3c1b276ba2..0649d746907 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -66,8 +66,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index d0b074b1f2b..1c2f7a8501a 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -81,9 +81,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" CONFIG_SPL_DM=y diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig index cf19ceae911..2d3aca92e33 100644 --- a/configs/imx8mp_debix_model_a_defconfig +++ b/configs/imx8mp_debix_model_a_defconfig @@ -59,8 +59,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 5b2c977edf8..694bddc6699 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -23,6 +23,11 @@ CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_EFI_MM_COMM_TEE=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y @@ -51,24 +56,28 @@ CONFIG_SYS_PROMPT="u-boot=> " CONFIG_CMD_CPU=y # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" @@ -76,6 +85,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x42800000 CONFIG_FASTBOOT_BUF_SIZE=0x20000000 @@ -89,6 +99,7 @@ CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -124,6 +135,8 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_DM_USB_GADGET=y @@ -139,3 +152,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_IMX_WATCHDOG=y +CONFIG_SPL_RSA=y +CONFIG_SHA384=y diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig index d6e7edcfa28..552665d27ca 100644 --- a/configs/imx8mp_navqp_defconfig +++ b/configs/imx8mp_navqp_defconfig @@ -58,8 +58,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index ea091d32eee..b7a0b0533ba 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -95,8 +95,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 03e558b9589..1e2fad98b7d 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -95,8 +95,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index b91e69a25e2..526a954aa85 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -64,10 +64,15 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_CAT=y +CONFIG_CMD_SETEXPR_FMT=y +CONFIG_CMD_XXD=y CONFIG_CMD_DHCP6=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y @@ -83,10 +88,11 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw75xx-2x" +CONFIG_OF_LIVE=y +CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw75xx-2x freescale/imx8mp-venice-gw82xx-2x" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_PROT_TCP_SACK=y @@ -99,10 +105,14 @@ CONFIG_CLK_IMX8MP=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index 1eff6bbc800..8efbd61f9e3 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -56,8 +56,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index a2a6991bee2..21bb04d18a8 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -27,6 +27,10 @@ CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_REMAKE_ELF=y +CONFIG_EFI_MM_COMM_TEE=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y @@ -53,28 +57,34 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_USB=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_DFU_MMC=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y @@ -96,8 +106,11 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +CONFIG_SHA384=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 807c5602d66..42c9c8c3de7 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -70,8 +70,8 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig index 7d3c81c93d4..40e7bce9815 100644 --- a/configs/imx8mq_reform2_defconfig +++ b/configs/imx8mq_reform2_defconfig @@ -69,8 +69,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig index ddf6f0376a6..e066c2bcb58 100644 --- a/configs/imx8qm_dmsse20a1_defconfig +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index afcb0f30594..113e0e0284a 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -73,8 +73,8 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index cd1db0ec408..d95d10a6080 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -55,8 +55,8 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config index 463e584530f..62babf2626f 100644 --- a/configs/imx8qxp_capricorn.config +++ b/configs/imx8qxp_capricorn.config @@ -10,8 +10,8 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DM_GPIO=y CONFIG_AHAB_BOOT=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index fa36b7b77a1..951d73fefd5 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -74,8 +74,8 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig index a57c1fd01f5..b92754074a0 100644 --- a/configs/imx91_11x11_evk_defconfig +++ b/configs/imx91_11x11_evk_defconfig @@ -80,8 +80,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig index 0533acaaa6b..8a5222b6540 100644 --- a/configs/imx91_11x11_evk_inline_ecc_defconfig +++ b/configs/imx91_11x11_evk_inline_ecc_defconfig @@ -80,8 +80,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 66a431244b0..6210be64672 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -85,9 +85,9 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 16596a89d60..cb4a542cbf1 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -26,6 +26,12 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_REMAKE_ELF=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_MM_COMM_TEE=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" CONFIG_SYS_CBSIZE=2048 @@ -51,6 +57,7 @@ CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_CMD_CPU=y CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y @@ -60,9 +67,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_SNTP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y @@ -76,8 +85,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" @@ -89,10 +98,12 @@ CONFIG_ADC=y CONFIG_ADC_IMX93=y CONFIG_SPL_CLK_IMX93=y CONFIG_CLK_IMX93=y +CONFIG_DFU_MMC=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -122,9 +133,12 @@ CONFIG_FSL_LPUART=y CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_SYSRESET_PSCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_ULP_WATCHDOG=y CONFIG_WDT=y +CONFIG_SHA384=y CONFIG_LZO=y CONFIG_BZIP2=y CONFIG_UTHREAD=y diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 60dd143aeab..99c349a9295 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -78,8 +78,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig index d6084b94b98..0966f166ec6 100644 --- a/configs/imx93_9x9_qsb_inline_ecc_defconfig +++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig @@ -78,8 +78,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig index 411f2b2e236..1f7ff269487 100644 --- a/configs/imx93_var_som_defconfig +++ b/configs/imx93_var_som_defconfig @@ -87,8 +87,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig index 32aee1fa90a..814570ee2ae 100644 --- a/configs/imx95_19x19_evk_defconfig +++ b/configs/imx95_19x19_evk_defconfig @@ -86,8 +86,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/imx_dhsom.config b/configs/imx_dhsom.config index d166b2cda2b..4a3ddc7e90b 100644 --- a/configs/imx_dhsom.config +++ b/configs/imx_dhsom.config @@ -25,8 +25,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index b67dc399e5c..17c650e6950 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -45,7 +45,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_BLOCKSIZE=512 CONFIG_SPL_DM=y diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 918713a1c7d..5faf964759d 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -51,7 +51,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_BLOCKSIZE=512 CONFIG_SPL_DM=y diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig index 86acd158391..cc7e8a3e10b 100644 --- a/configs/imxrt1050-evk_fspi_defconfig +++ b/configs/imxrt1050-evk_fspi_defconfig @@ -53,7 +53,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_BLOCKSIZE=512 CONFIG_SPL_DM=y diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig index a57c35bf686..9bd3874143c 100644 --- a/configs/imxrt1170-evk_defconfig +++ b/configs/imxrt1170-evk_defconfig @@ -47,7 +47,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index bd0a7bf1c4d..c1931bd2e1c 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index aae5512a5fa..409dd341a98 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index 7aaec71a977..a831fbba3d5 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index 05fa604368c..ce7ca33efb3 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD=y diff --git a/configs/inteno_xg6846_ram_defconfig b/configs/inteno_xg6846_ram_defconfig index f325a07a522..0919289d613 100644 --- a/configs/inteno_xg6846_ram_defconfig +++ b/configs/inteno_xg6846_ram_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SPI=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DMA=y CONFIG_BCM6348_IUDMA=y diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 5bb692ef3ad..55477c85807 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -83,7 +83,7 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="ti/k3-am6528-iot2050-basic" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig index 5b7e131c9ac..aef0a995c39 100644 --- a/configs/iot_devkit_defconfig +++ b/configs/iot_devkit_defconfig @@ -31,7 +31,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="app.bin" CONFIG_NO_NET=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index a446074ad5d..3987bab5679 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y @@ -78,8 +77,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 0ae07ddf7c8..dca757fe057 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x70000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -72,7 +71,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index e3cd59343f0..00ed3d91242 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -79,8 +78,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig index 086ad99ff6d..99e96c90ef9 100644 --- a/configs/j721e_beagleboneai64_r5_defconfig +++ b/configs/j721e_beagleboneai64_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x70000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -67,7 +66,7 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="k3-j721e-r5-beagleboneai64" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 99461cf6007..02e3ac343d9 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -83,8 +82,8 @@ CONFIG_OF_LIST="ti/k3-j721e-common-proc-board" CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index c8324d4c068..3a54a4c97d1 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x70000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -80,7 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 084deea28d0..ac584f50b94 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y @@ -75,8 +74,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 6ea1d712be1..f4c0862d0a8 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -81,7 +80,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index 88717829d82..f4562bd0d68 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -68,8 +68,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 56af0230860..6b1306cf7af 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y @@ -65,8 +64,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 4f5a0c943d8..9e4170028f4 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -71,7 +70,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 03d38274b15..13cff7b1a02 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -59,7 +59,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig index b5deb9d1c19..24011b0a0e6 100644 --- a/configs/jethub_j100_defconfig +++ b/configs/jethub_j100_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_RTC=y CONFIG_CMD_REGULATOR=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_DM_I2C=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig index 89fcefb6ec6..8b5f7cdbcfd 100644 --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_RTC=y CONFIG_CMD_REGULATOR=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_DM_I2C=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 3b74845046c..13d43c02b9f 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -45,8 +45,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index ab28e15a3ff..e8635054e8c 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -63,7 +63,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 6b771dfb061..0557dd5a5b3 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -37,7 +37,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 9b8fcc591ae..02a948c251f 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -64,7 +64,7 @@ CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index af9316f753a..ca58125aa3f 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -39,7 +39,7 @@ CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 31ffb762c26..b3756c60efc 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -63,7 +63,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 0e43ca1f861..0025412b10f 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -37,7 +37,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 8f5c4855dd3..e90297cd2e9 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -63,7 +63,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 4f71a208d8d..8864b60e845 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -40,7 +40,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=32 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index c23f0ecd516..8ed3e5f3ec8 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index cac98f721cf..ec3428d34c3 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 3800bcf2ab3..3903c4e2ad1 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 59491c4d29f..1d8e0601dc9 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index a078c5d363a..765a154c150 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -56,9 +56,9 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index b77a44ce859..d105c2b40b0 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -55,9 +55,9 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index 7cc31efb752..a8126a680fa 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 43db61056ba..0625c101085 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -56,9 +56,9 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index 32d57a5b909..be65d0feb12 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -55,9 +55,9 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index 5aa08c41df8..87bacf4500e 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 775c24f7ddc..02a3b9fa471 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 76e98c9b2a4..1668ce51883 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xebf00000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="fm1-mac5" diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index cf50e2d27d8..69ef6cf3b9b 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -158,7 +158,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 7638fc2f5cf..267bbff81ae 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -137,7 +137,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 1c750455fc6..803eae06696 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -144,7 +144,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 5dd98175cd3..cd9bbc91e52 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -129,7 +129,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 2b240b3380d..f3bec1d569f 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -143,7 +143,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 9d37280138f..cdf8e406483 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -80,7 +80,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx8mm-kontron-bl imx8mm-kontron-bl-osm-s" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="kontron-mx8mm" diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index 8352176df61..7d5effe663e 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -76,7 +76,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index c5f145aadc1..6ddd21bd295 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -82,7 +82,7 @@ CONFIG_OF_UPSTREAM=y CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var3 freescale/fsl-ls1028a-kontron-sl28-var4" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SATA=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index 25edee32462..9943f5bd12c 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -39,8 +39,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 7fd2bfb0efa..84cef56706b 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -47,9 +47,9 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents interrupts dmas dma-names" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y # CONFIG_BLOCK_CACHE is not set diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 23cca4e3b28..525697842ce 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_TIME=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/lckfb-tspi-rk3566_defconfig b/configs/lckfb-tspi-rk3566_defconfig index 07eef047d6a..b5479fd90e1 100644 --- a/configs/lckfb-tspi-rk3566_defconfig +++ b/configs/lckfb-tspi-rk3566_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 2527bb8a10f..df2e17809aa 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 54976501e11..dee19a95d55 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index 5a47772bc08..8fbe4c45fd6 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -69,7 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_DEVRES=y @@ -130,6 +130,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index 17841630e2b..e3a1e084f75 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 221f5d52b49..319b416fd61 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index d27886f3ec1..d9a4b68e798 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y diff --git a/configs/linkit-smart-7688_defconfig b/configs/linkit-smart-7688_defconfig index d70af3f8b33..1602ff5b73a 100644 --- a/configs/linkit-smart-7688_defconfig +++ b/configs/linkit-smart-7688_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FS_GENERIC=y # CONFIG_DOS_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/liontron-h-a133l_defconfig b/configs/liontron-h-a133l_defconfig new file mode 100644 index 00000000000..4b769768e5f --- /dev/null +++ b/configs/liontron-h-a133l_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-a133-liontron-h-a133l" +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x7070707 +CONFIG_DRAM_SUNXI_DX_DRI=0xd0d0d0d +CONFIG_DRAM_SUNXI_CA_DRI=0xe0e +CONFIG_DRAM_SUNXI_PARA0=0xd0a050c +CONFIG_DRAM_SUNXI_MR11=0x4 +CONFIG_DRAM_SUNXI_MR12=0x72 +CONFIG_DRAM_SUNXI_MR13=0x0 +CONFIG_DRAM_SUNXI_MR14=0x7 +CONFIG_DRAM_SUNXI_TPR1=0x26 +CONFIG_DRAM_SUNXI_TPR2=0x6060606 +CONFIG_DRAM_SUNXI_TPR3=0x84040404 +CONFIG_DRAM_SUNXI_TPR6=0x48000000 +CONFIG_DRAM_SUNXI_TPR10=0x273333 +CONFIG_DRAM_SUNXI_TPR11=0x231d151c +CONFIG_DRAM_SUNXI_TPR12=0x1212110e +CONFIG_DRAM_SUNXI_TPR13=0x7521 +CONFIG_DRAM_SUNXI_TPR14=0x2023211f +CONFIG_MACH_SUN50I_A133=y +CONFIG_DRAM_CLK=792 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_SUNXI_DRAM_A133_LPDDR4=y +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_AXP803_POWER=y +CONFIG_AXP_DCDC5_VOLT=1100 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 9a81e973e3c..ed1b4441538 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NET_RANDOM_ETHADDR=y @@ -61,6 +61,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 69abd098982..32d95162e9b 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -17,7 +17,6 @@ CONFIG_AHCI=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -40,7 +39,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SATA=y CONFIG_SCSI_AHCI=y @@ -56,7 +55,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 883a007c73e..a0081d9f055 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -17,7 +17,6 @@ CONFIG_PCI=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -39,7 +38,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y @@ -55,7 +54,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 0e1452eb78c..c497cdd92a2 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -17,7 +17,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -57,7 +56,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 0ffae31dae5..70f051f76e8 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -18,7 +18,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -43,7 +42,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SATA=y CONFIG_SATA_CEVA=y @@ -60,7 +59,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 8dc27474200..ff7ebbc8d9c 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -20,7 +20,6 @@ CONFIG_PCIE1=y CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -50,7 +49,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y @@ -73,7 +72,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 26cddb55e3d..e7f7031f42d 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -22,7 +22,6 @@ CONFIG_PCIE1=y CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -57,7 +56,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=0 CONFIG_ENV_SPI_MAX_HZ=1000000 CONFIG_ENV_SPI_MODE=0x03 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SATA=y CONFIG_SCSI_AHCI=y @@ -82,7 +81,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index c63ed627305..abc1f5ab726 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -18,7 +18,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -42,7 +41,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SATA=y CONFIG_SATA_CEVA=y @@ -61,7 +60,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 15f30ebd387..428fc58e2f3 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -19,7 +19,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -44,7 +43,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SATA=y CONFIG_SATA_CEVA=y @@ -62,7 +61,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index c91d8c76b3e..e086f36d6ea 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC2" CONFIG_SATA=y @@ -67,7 +67,7 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index c2763b4048a..ea5bb34cfbe 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC2" CONFIG_SATA=y @@ -98,7 +98,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xf40000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index f56395a5451..e4adb8eeb1e 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -89,7 +89,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_SATA=y @@ -128,7 +128,8 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 29141097b75..ad4b58e517b 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -95,7 +95,7 @@ CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index ec27ad3c7a7..9f26abb123a 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_SATA=y @@ -83,7 +83,7 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 2f9d10dd6b5..10b69284d01 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -89,7 +89,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_SATA=y @@ -127,7 +127,8 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 58d1a68f595..30d6c54e4ce 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -86,7 +86,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" CONFIG_SATA=y @@ -112,7 +112,8 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 1c7f25ebc6d..bc499a51630 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_FS_UUID=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y @@ -68,7 +68,7 @@ CONFIG_SJA1105=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index ee3d9569699..6bb5c1628d7 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -71,7 +71,7 @@ CONFIG_CMD_FS_UUID=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y @@ -96,7 +96,8 @@ CONFIG_SJA1105=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 89c02fe1fd3..38bb415bb81 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index a3fd4ac9baa..ddda1a1d896 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d10000" CONFIG_SATA=y @@ -76,7 +76,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index eb648f1e783..6c12c35ab96 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -81,7 +81,7 @@ CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d10000" CONFIG_SPL_DM=y @@ -112,7 +112,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index f6edabaa76e..3f0d277703d 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -82,7 +82,7 @@ CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d10000" CONFIG_SATA=y @@ -111,7 +111,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 24d20a262bb..897f9b6408d 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -82,7 +82,7 @@ CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d10000" CONFIG_SATA=y @@ -105,7 +105,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 1cbab056fd4..f3642594ff0 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index f124098b7bf..1537f8aab91 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -66,7 +66,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=0 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y @@ -105,7 +105,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index b297af3f669..ce501dd1404 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_SATA=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 0e290ce55ee..b32adab0bad 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -46,7 +46,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_SATA=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index f7b44f64dd4..b657248f918 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -97,7 +97,7 @@ CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 2efc17b9e43..7b4d4ff92c7 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -67,7 +67,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=0 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y @@ -107,7 +107,7 @@ CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index a8f20f9b87b..d0d612bd395 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -51,7 +51,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" CONFIG_SATA=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index df86bf982ee..dafbe9b3b2b 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -61,7 +61,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="DPMAC1@xgmii" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 8d640f6594b..46390a05adb 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -57,7 +57,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="DPMAC1@xgmii" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 0685960f218..77f5a7ac708 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -68,7 +68,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="DPMAC1@xgmii" CONFIG_NET_RANDOM_ETHADDR=y @@ -111,7 +111,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_RTC_DS3231=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 44a1459749f..d07ca3217a2 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -48,7 +48,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="DPMAC1@xgmii" CONFIG_NET_RANDOM_ETHADDR=y @@ -90,7 +90,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_RTC_DS3231=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 66276ec678e..8c623d6a8e5 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -72,7 +72,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="DPMAC1@xgmii" CONFIG_NET_RANDOM_ETHADDR=y @@ -115,7 +115,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_DS3231=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 8c86b8b11eb..51475f2733f 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -55,7 +55,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="DPMAC1@xgmii" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 18de0ad7ad7..3a53d49ba83 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 018d489dbef..83a0a6f5415 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig index 0bc4ae0c7a5..f2afed1c4ba 100644 --- a/configs/lxr2_defconfig +++ b/configs/lxr2_defconfig @@ -71,8 +71,8 @@ CONFIG_EFI_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index cc6ef49b1d0..ac687b10d6e 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -70,8 +70,8 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" CONFIG_USE_ETHPRIME=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index b90d294ec7d..983e3d2425f 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 903f8a16d15..663e09c2415 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 682ce3035b5..d9192617812 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -48,7 +48,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x8060000 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 665dc9ee45a..41ae748c97e 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -46,7 +46,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x8060000 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index d99addadf86..89fac8daaa1 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_MTD_RAW_NAND=y CONFIG_TEGRA_NAND=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/meerkat96_defconfig b/configs/meerkat96_defconfig index 72beb072a10..a51158b03e5 100644 --- a/configs/meerkat96_defconfig +++ b/configs/meerkat96_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_MMC_BROKEN_CD=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 5a040cdc8fa..f6b5c01e6e0 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_PING=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index 1ce98bd5195..21a3b122acf 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 7497d20ee64..07612ef5e93 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="microblaze-generic" CONFIG_NETCONSOLE=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index f8acaa98672..bb110225488 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -19,7 +19,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_OF_UPSTREAM=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y CONFIG_SYSRESET=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 1eddb58efaf..ecddf388841 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index c09a119f862..a4d24c11fe8 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -44,7 +44,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index f0a366a6e2d..b983128e1de 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -67,7 +67,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_SPL_OF_PLATDATA=y CONFIG_TPL_OF_PLATDATA=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_TPL_DM=y CONFIG_REGMAP=y diff --git a/configs/mocha_defconfig b/configs/mocha_defconfig index ffaab6b6753..ab8cea69a02 100644 --- a/configs/mocha_defconfig +++ b/configs/mocha_defconfig @@ -53,8 +53,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/mot_defconfig b/configs/mot_defconfig index 66a62cf077d..dc6549cba76 100644 --- a/configs/mot_defconfig +++ b/configs/mot_defconfig @@ -52,8 +52,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig index 6b2bb716293..d3c0895ff2d 100644 --- a/configs/msc_sm2s_imx8mp_defconfig +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -65,8 +65,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 0577b12d17f..2cef93802f8 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -52,8 +52,8 @@ CONFIG_OF_LIST="jr2_pcb110 jr2_pcb111 serval2_pcb112" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_MSCC_SGPIO=y diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index dfd6bc08873..1fcda3f1681 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -55,8 +55,8 @@ CONFIG_OF_LIST="luton_pcb090 luton_pcb091" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_MSCC_SGPIO=y diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index 23aff7ea462..23d138d03b9 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -54,8 +54,8 @@ CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_MSCC_SGPIO=y diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index 6ddcbe1efee..74daabed3f4 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -49,8 +49,8 @@ CONFIG_OF_LIST="serval_pcb106 serval_pcb105" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_MSCC_SGPIO=y diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index 629b55561a1..755296900d5 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -47,8 +47,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_MSCC_SGPIO=y diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig index 06f37f007c2..07158e7ba9c 100644 --- a/configs/mt7620_mt7530_rfb_defconfig +++ b/configs/mt7620_mt7530_rfb_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts resets reset-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y # CONFIG_SIMPLE_BUS is not set diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig index ffe9cc8a674..62897c5545a 100644 --- a/configs/mt7620_rfb_defconfig +++ b/configs/mt7620_rfb_defconfig @@ -49,7 +49,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts resets reset-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y # CONFIG_SIMPLE_BUS is not set diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig index 350ce0651e8..d7a8f31a0fa 100644 --- a/configs/mt7621_nand_rfb_defconfig +++ b/configs/mt7621_nand_rfb_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_I2C is not set # CONFIG_INPUT is not set diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig index c44ecb19241..668d1583a9f 100644 --- a/configs/mt7621_rfb_defconfig +++ b/configs/mt7621_rfb_defconfig @@ -53,7 +53,7 @@ CONFIG_DOS_PARTITION=y CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_PARTITION_TYPE_GUID=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_I2C is not set # CONFIG_INPUT is not set diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index cf89f43297d..dc94f8b3b93 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_READ=y # CONFIG_CMD_SETEXPR is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.1.1" CONFIG_USE_SERVERIP=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 42da25ee4ca..404380558f2 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_READ=y # CONFIG_CMD_SETEXPR is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.1.1" CONFIG_USE_SERVERIP=y diff --git a/configs/mt7628_rfb_defconfig b/configs/mt7628_rfb_defconfig index 0ca8cf65352..1f45ed894ea 100644 --- a/configs/mt7628_rfb_defconfig +++ b/configs/mt7628_rfb_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SPI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_INPUT is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index f9d558819b7..9db733f6213 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_LOG=y CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-parents" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_IPADDR=y CONFIG_IPADDR="192.168.1.1" CONFIG_USE_SERVERIP=y diff --git a/configs/mt8183_pumpkin_defconfig b/configs/mt8183_pumpkin_defconfig index 9d0495f470c..4aceb73c34c 100644 --- a/configs/mt8183_pumpkin_defconfig +++ b/configs/mt8183_pumpkin_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_DOS_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DEVRES=y CONFIG_CLK=y diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig index a968e83dd54..756d974278a 100644 --- a/configs/mt8516_pumpkin_defconfig +++ b/configs/mt8516_pumpkin_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_DOS_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_CLK=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index e8984b663b5..8a1e27287a3 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -42,8 +42,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_GENERIC=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index e5de34c85fc..f0e9ae9f674 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_GENERIC=y diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index f9b03a7e77a..9e68a656c2e 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_GENERIC=y diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index 6dd6be788d3..81466f75cae 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -43,8 +43,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_GENERIC=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index e9ee88594e9..94fbcf4f2d9 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_FS_UUID=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig index 401fa91aa6d..6e270be157b 100644 --- a/configs/mvebu_espressobin_ultra-88f3720_defconfig +++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig @@ -48,7 +48,7 @@ CONFIG_MAC_PARTITION=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 90d341e0a4c..6bc127d1abd 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index 21ab2177058..72c1635592a 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 6bb3cedde12..c467a7fbe1e 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index 02cbc4be481..f303322856f 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index fdab7ef73e5..76dde53f2a5 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index d4457859f12..bcbef81d1d4 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index 614cec14102..2161fd82424 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -20,7 +20,7 @@ CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_FPGA_ALTERA=y CONFIG_FPGA_CYCLON2=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index fa7b04383e0..1f7da84fbea 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 4ec8516015f..e2a33ff0ab1 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 14c1386e11f..6a7c8d414e1 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -49,7 +49,7 @@ CONFIG_OF_LIST="imx6dl-hummingboard2-emmc-som-v15 imx6q-hummingboard2-emmc-som-v CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 800cb7df912..4011b8ef7ff 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -35,10 +35,11 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y # CONFIG_MMC is not set CONFIG_FSL_USDHC=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 916992351ce..da07b38b4bc 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NETCONSOLE=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 94b251cbdeb..66ae436b538 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -60,7 +60,7 @@ CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 312af2f57fd..75a655a0e0d 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -69,8 +69,8 @@ CONFIG_OF_CONTROL=y CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index e927bb21658..18534a1b45a 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index d529f9b8f12..f126c6e1e79 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 1e61b4214f4..134475d24d8 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 25b0b11342d..2643f13e26b 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_BOUNCE_BUFFER=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 68df8d4c741..d28880797dc 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -41,8 +41,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 737a079eaa7..0e35e5e6af5 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -56,8 +56,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 964d00a4085..e1482081493 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -54,8 +54,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 369bc0f2e0a..0422edeb53d 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -37,8 +37,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 97d4f9fc65f..36d1f96f25d 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 1a49bc2cf01..9db0251a8a0 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -33,8 +33,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 7811b17bf0f..a5a562af0c0 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 2ee8bd36252..1b2bae5e2b1 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 12f13112b63..98b99dd78e1 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y CONFIG_IMX_RGPIO2P=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 8e05d394335..af0efbd3ebf 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y CONFIG_IMX_RGPIO2P=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index baee86ae170..742713851e7 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -40,7 +40,7 @@ CONFIG_MTDPARTS_DEFAULT="gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig index b9ff95c5512..caa2d316765 100644 --- a/configs/n2350_defconfig +++ b/configs/n2350_defconfig @@ -59,7 +59,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDPARTS_DEFAULT="mtdparts=pxa3xx_nand-0:-(rootfs);spi1.0:1M(u-boot),64K@1M(u-boot-env),-(data)" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 40e99878016..b0e05d32359 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SPL_ROCKCHIP_IODOMAIN=y diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig index e081e0b064a..0f851b40977 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -45,7 +45,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_LIST="rockchip/rk3588-nanopc-t6 rockchip/rk3588-nanopc-t6-lts" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index 797a7f56723..5ab40d4a41c 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 5c53293757d..fbffca99619 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -35,7 +35,7 @@ CONFIG_SPL_OF_CONTROL=y # CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 76d2994ae57..2f5ba8e2bcb 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 17241b38946..47f2d0e64f2 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index c0aedd5288b..689b53e8618 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SPL_ROCKCHIP_IODOMAIN=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 271b12e4507..5c6be8b85a7 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -42,8 +42,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index c2d0b5a1f1d..fa2b348f2e5 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -42,8 +42,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/nanopi-r2s-plus-rk3328_defconfig b/configs/nanopi-r2s-plus-rk3328_defconfig index c5315580c83..359ac2983b8 100644 --- a/configs/nanopi-r2s-plus-rk3328_defconfig +++ b/configs/nanopi-r2s-plus-rk3328_defconfig @@ -42,7 +42,7 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 50e96b1d314..bedcda2622c 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -42,8 +42,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 3ce9bad76fe..b0951c493ef 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SPL_ROCKCHIP_IODOMAIN=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 94a4d4c0b3f..92efe4298a8 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -43,7 +43,7 @@ CONFIG_EFI_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_ATA_STRIDE=4 diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index 377cc26f937..60a83d509bc 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SPI=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_BCM6345_GPIO=y diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index e4211a8372e..92e8bbf7c06 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig index e3d74933a82..da249f905bb 100644 --- a/configs/neu2-io-rv1126_defconfig +++ b/configs/neu2-io-rv1126_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_MMC=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index a0d77725083..74525657b1e 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NETCONSOLE=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 436ce289f1f..96e743a8057 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NETCONSOLE=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 827e8830602..a3126140687 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NETCONSOLE=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 62fc8d8f3b6..f9018f12aac 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NETCONSOLE=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index d16cf2ac30f..36c635102ee 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NETCONSOLE=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index bd3ae139362..f4c08d785b7 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_NETCONSOLE=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index bcd40b3f5e5..4fd29ef8564 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -54,8 +54,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" CONFIG_USE_HOSTNAME=y @@ -82,6 +82,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y CONFIG_POWER_PFUZE100=y CONFIG_POWER_I2C=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 9a42c391556..90a2fc03214 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/nsim_700_defconfig b/configs/nsim_700_defconfig index d50e85a93fa..71802fef030 100644 --- a/configs/nsim_700_defconfig +++ b/configs/nsim_700_defconfig @@ -22,7 +22,7 @@ CONFIG_SYS_PROMPT="nsim# " # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NO_NET=y diff --git a/configs/nsim_700be_defconfig b/configs/nsim_700be_defconfig index 4832195f6b4..7401c102d12 100644 --- a/configs/nsim_700be_defconfig +++ b/configs/nsim_700be_defconfig @@ -23,7 +23,7 @@ CONFIG_SYS_PROMPT="nsim# " # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NO_NET=y diff --git a/configs/nsim_hs38_defconfig b/configs/nsim_hs38_defconfig index a652687156c..ed011d143cb 100644 --- a/configs/nsim_hs38_defconfig +++ b/configs/nsim_hs38_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_DM=y CONFIG_CMD_DHCP=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_DM_SERIAL=y diff --git a/configs/nsim_hs38be_defconfig b/configs/nsim_hs38be_defconfig index 67de123d16b..430ed914f37 100644 --- a/configs/nsim_hs38be_defconfig +++ b/configs/nsim_hs38be_defconfig @@ -24,7 +24,7 @@ CONFIG_SYS_PROMPT="nsim# " # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NO_NET=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 71f364cf7c1..6d2b1a17edf 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -56,8 +56,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index bcaab46f8bc..d92be39cc24 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_DM_I2C=y diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig index cc3d7fc7484..28ac8aa59eb 100644 --- a/configs/odroid-c4_defconfig +++ b/configs/odroid-c4_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index 4bbda284ef1..97c44b1115b 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig index 97fae4df75b..99e71cfebf2 100644 --- a/configs/odroid-hc4_defconfig +++ b/configs/odroid-hc4_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_SATA=y diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig index 344c7bdd213..15f71711193 100644 --- a/configs/odroid-m1s-rk3566_defconfig +++ b/configs/odroid-m1s-rk3566_defconfig @@ -41,7 +41,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/odroid-m2-rk3588s_defconfig b/configs/odroid-m2-rk3588s_defconfig index 21ccbd4c77a..504ddaee538 100644 --- a/configs/odroid-m2-rk3588s_defconfig +++ b/configs/odroid-m2-rk3588s_defconfig @@ -41,7 +41,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig index a8cbaee3c96..673aca491f1 100644 --- a/configs/odroid-n2_defconfig +++ b/configs/odroid-n2_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y diff --git a/configs/odroid-n2l_defconfig b/configs/odroid-n2l_defconfig index 773c8061db3..3ed3da2e230 100644 --- a/configs/odroid-n2l_defconfig +++ b/configs/odroid-n2l_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 6431f59568c..83bfa27c84e 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ADC=y CONFIG_ADC_EXYNOS=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index 93270e0129d..eec96b5a8a9 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 42c6aadea97..a813d216787 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -49,7 +49,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index c0949fc8750..02ec5a73229 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -66,7 +66,7 @@ CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 1ca0b45d93f..cfad5fb037b 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index e0cc2e65db3..e0a393e478c 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index a115691daad..23415ef12ee 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index f7ed9e49359..e9184549601 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -73,9 +73,9 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_VERSION_VARIABLE=y CONFIG_USE_ROOTPATH=y CONFIG_ROOTPATH="/tftpboot/opos6ul-root" diff --git a/configs/orangepi-3b-rk3566_defconfig b/configs/orangepi-3b-rk3566_defconfig index 99a4a135f87..0213993bc2c 100644 --- a/configs/orangepi-3b-rk3566_defconfig +++ b/configs/orangepi-3b-rk3566_defconfig @@ -48,7 +48,7 @@ CONFIG_OF_LIVE=y # CONFIG_OF_UPSTREAM is not set CONFIG_OF_LIST="rk3566-orangepi-3b rk3566-orangepi-3b-v1.1 rk3566-orangepi-3b-v2.1" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 14b1af6fe51..7e40d9d91f8 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -47,8 +47,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index f7456be1203..36977865ad4 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -47,8 +47,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 1ef429849f0..197565f9a80 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index bb69c02529b..2ec232b1950 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000 diff --git a/configs/ouya_defconfig b/configs/ouya_defconfig index d4ae9dbb57c..60cc3796c5e 100644 --- a/configs/ouya_defconfig +++ b/configs/ouya_defconfig @@ -51,8 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/p200_defconfig b/configs/p200_defconfig index 36e76d890e5..53e4832e8bb 100644 --- a/configs/p200_defconfig +++ b/configs/p200_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y diff --git a/configs/p201_defconfig b/configs/p201_defconfig index 5df5f01cbce..33d9be9c9f0 100644 --- a/configs/p201_defconfig +++ b/configs/p201_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 1c45e3d3923..2b7d2e353c1 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 93e1846a883..4d3bfaa6982 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -29,8 +29,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 1c6fe537d61..fdbe87574d5 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -37,8 +37,8 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index b2485423e1e..4fd72ffbbf4 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -30,8 +30,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index a12586523e9..462bec3bae2 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -30,8 +30,8 @@ CONFIG_CMD_SPI=y CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_TEGRA186_BPMP_I2C=y CONFIG_DWC_ETH_QOS=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 4553d707699..42043277e2d 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -29,8 +29,8 @@ CONFIG_CMD_SPI=y CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_TEGRA186_BPMP_I2C=y CONFIG_DWC_ETH_QOS=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index b59c2e0ca58..5c5ffdb427a 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -34,8 +34,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index a4e467fa05e..9d54f7b2d32 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas " -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index d0d558ab11a..64f5f777e5c 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_TEXT_BASE=0x3f401000 CONFIG_SYS_MALLOC_LEN=0x202000 -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xA0000 @@ -42,8 +41,8 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VYBRID_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index 8ab2c1c069e..aae099d647e 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -57,8 +57,8 @@ CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y diff --git a/configs/pe2201_defconfig b/configs/pe2201_defconfig index 72f6274ec41..020a2d49e60 100644 --- a/configs/pe2201_defconfig +++ b/configs/pe2201_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_BOOTMETH=y CONFIG_CMD_DM=y CONFIG_CMD_PCI=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 247df4c9036..846ea20dfc4 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index df72be8047b..7eacdb7217f 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 4b82b077ea7..321e46e8c52 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 53d54789687..b53af5be52c 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 731ca435089..561df3ee009 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 2598e477ed5..2a631176095 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index b40fb6197c5..2443af4c4d7 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -58,7 +58,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index aaf7ff8456a..ebde47bba80 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -58,7 +58,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 8f52ec2ab90..96eacec1d23 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -79,9 +79,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_COMPOSITE_CCF=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index ed2171540af..cb38898a245 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -92,9 +92,9 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index db865109d8e..ee9cc2bd822 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -51,8 +51,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index c74909dabdf..bdd7e288aa4 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -41,7 +40,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb" +CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 @@ -89,8 +88,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y @@ -129,6 +128,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_BOOTDEV_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_SPI_FLASH_SOFT_RESET=y diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig index 7bcfbe94850..8ee6ed73adc 100644 --- a/configs/phycore_am62ax_r5_defconfig +++ b/configs/phycore_am62ax_r5_defconfig @@ -64,8 +64,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 487eafb0e17..910a41fa052 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -44,7 +43,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb" +CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 @@ -92,8 +91,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -125,6 +124,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_BOOTDEV_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_SPI_FLASH_SOFT_RESET=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index a5d494cf87a..546cee09575 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -71,7 +71,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 2032a34030f..9f98b3522dc 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -40,7 +39,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y -CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb" +CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 @@ -92,8 +91,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -131,6 +130,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_BOOTDEV_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_SPI_FLASH_SOFT_RESET=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 2552479713f..189d0706ce5 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x80000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -82,7 +81,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 126caf52b08..d9e7285f544 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 547d59a7a52..729ac2be9e2 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_CACHE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index 348ea43fd75..266bfdd68d1 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=500 CONFIG_NET_RETRY_COUNT=20 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig index 1e9f5ca6bb7..f5c6619a271 100644 --- a/configs/picasso_defconfig +++ b/configs/picasso_defconfig @@ -51,8 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index 8b90285980f..e1f6e6f91f2 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 9d5241a50d0..c1389ac4066 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index b945adfe734..137541d373a 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 690139c09ca..72e1a3bccc1 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 4a9c5ac1a98..6f46d9bf8a1 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -55,7 +55,7 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index c9a0ccd15f6..70b79622be1 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 1327523e289..b5485bf8d0b 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 6009b1c65c1..4707062053b 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 02cfee2694f..63feb839c17 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -70,8 +70,8 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 9d5241a50d0..c1389ac4066 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index daff2e36b00..40db7e23797 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 28c46abed78..26fccf90db7 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 17218b91f83..cbf95b4692f 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 88a32050125..81bc6d5400d 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index a5bc1f6b284..932a2d10027 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_MTD_RAW_NAND=y CONFIG_TEGRA_NAND=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index fa8b53848b4..3fd178e0520 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -44,8 +44,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 50c92925506..b826d78d594 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -40,7 +40,7 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig index b963886d2ef..f7070543260 100644 --- a/configs/pomelo_defconfig +++ b/configs/pomelo_defconfig @@ -19,7 +19,7 @@ CONFIG_SYS_PBSIZE=280 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="pomelo#" CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCI_PHYTIUM=y diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig index 24732ad4026..95888920111 100644 --- a/configs/poplar_defconfig +++ b/configs/poplar_defconfig @@ -20,7 +20,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x20000000 diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index c76cfaa4247..95c1097bc93 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 4e8cee06775..94080c13dc0 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -55,8 +55,8 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 36de779390d..f7f4eb4a7cf 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -49,7 +49,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index f59fb8ccb36..c075d60fabd 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -49,7 +49,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 86e8e5597d2..81356419d46 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -49,7 +49,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index fd2727e48d7..05adbcbb9f3 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -76,7 +76,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_USE_ROOTPATH=y diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig index 9104cc084be..3f85890bdbd 100644 --- a/configs/qc750_defconfig +++ b/configs/qc750_defconfig @@ -52,8 +52,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/qcm6490_defconfig b/configs/qcm6490_defconfig index ba26924da16..5ddc5ab3ef8 100644 --- a/configs/qcm6490_defconfig +++ b/configs/qcm6490_defconfig @@ -19,9 +19,3 @@ CONFIG_TEXT_BASE=0x9fc00000 CONFIG_REMAKE_ELF=y CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs6490-rb3gen2" - -# Enable capsule updates -CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y -CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_IGNORE_OSINDICATIONS=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index b8399701da0..87466d23d14 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -6,6 +6,9 @@ CONFIG_ARCH_SNAPDRAGON=y CONFIG_NR_DRAM_BANKS=24 CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c" CONFIG_SYS_LOAD_ADDR=0xA0000000 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BUTTON_CMD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -42,8 +45,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM_BUILD_VENDOR=y -CONFIG_USE_DEFAULT_ENV_FILE=y -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env" +CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE=y +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/default.env" CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_STUB=y @@ -51,6 +54,8 @@ CONFIG_CLK_QCOM_APQ8016=y CONFIG_CLK_QCOM_APQ8096=y CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y +CONFIG_CLK_QCOM_QCS615=y +CONFIG_CLK_QCOM_QCS8300=y CONFIG_CLK_QCOM_SA8775P=y CONFIG_CLK_QCOM_SDM845=y CONFIG_CLK_QCOM_SM6115=y @@ -143,3 +148,5 @@ CONFIG_VIDEO_FONT_16X32=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y +CONFIG_WDT_QCOM=y +CONFIG_WDT=y diff --git a/configs/qcom_ipq5424_mmc_defconfig b/configs/qcom_ipq5424_mmc_defconfig new file mode 100644 index 00000000000..0dd46680b0f --- /dev/null +++ b/configs/qcom_ipq5424_mmc_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_NR_DRAM_BANKS=24 +CONFIG_DEFAULT_DEVICE_TREE="qcom/ipq5424-rdp466" +CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +# CONFIG_EFI_LOADER is not set +# CONFIG_EFI_BINARY_EXEC is not set +# CONFIG_EFI_VARIABLE_FILE_STORE is not set +# CONFIG_PXE_UTILS is not set +# CONFIG_BOOTSTD is not set +# CONFIG_BOOTMETH_VBE is not set +CONFIG_BOOTDELAY=2 +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_LOG_MAX_LEVEL=9 +CONFIG_LOG_DEFAULT_LEVEL=4 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_PART=y +CONFIG_OF_LIVE=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env" +CONFIG_CLK=y +CONFIG_CLK_QCOM_IPQ5424=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SCSI=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000 +CONFIG_MSM_GPIO=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_QCOM_IPQ5424=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_QCOM=y +CONFIG_RGMII=y +CONFIG_PHY=y +CONFIG_PHY_QCOM_QMP_UFS=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_SCSI=y +CONFIG_MSM_SERIAL=y +CONFIG_MSM_GENI_SERIAL=y +CONFIG_SOC_QCOM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x1a84000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 +CONFIG_TEXT_BASE=0x8a380000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_SYS_CBSIZE=1024 +CONFIG_SYS_PBSIZE=1024 +CONFIG_OF_LIVE=y +CONFIG_MSM_SERIAL=y +CONFIG_DM_EVENT=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0 +CONFIG_PARTITIONS=y +CONFIG_PARTITION_UUIDS=y +CONFIG_MTD=y +CONFIG_MTD_PARTS=y +CONFIG_HUSH_PARSER=y +CONFIG_PARTITIONS=y +CONFIG_EFI_PARTITION=y +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_SCSI is not set +# CONFIG_SPMI is not set diff --git a/configs/qcom_ipq9574_mmc_defconfig b/configs/qcom_ipq9574_mmc_defconfig index 8d7d3d92c73..c7ce4f5c237 100644 --- a/configs/qcom_ipq9574_mmc_defconfig +++ b/configs/qcom_ipq9574_mmc_defconfig @@ -28,8 +28,8 @@ CONFIG_CMD_PART=y CONFIG_EFI_PARTITION=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_USE_DEFAULT_ENV_FILE=y -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env" +CONFIG_USE_ENV_DEFAULT_ENV_TEXT_FILE=y +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/default.env" CONFIG_CLK=y CONFIG_CLK_QCOM_IPQ9574=y CONFIG_MSM_GPIO=y diff --git a/configs/qcom_qcs615_defconfig b/configs/qcom_qcs615_defconfig new file mode 100644 index 00000000000..2468267b955 --- /dev/null +++ b/configs/qcom_qcs615_defconfig @@ -0,0 +1,22 @@ +# Configuration for building U-Boot to be flashed +# to the uefi partition of QCS615 dev boards with +# the "Linux Embedded" partition layout (which have +# a dedicated "uefi" partition for edk2/U-Boot) + +#include "qcom_defconfig" + +# Otherwise buildman thinks this isn't an ARM platform +CONFIG_ARM=y + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x880000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 + +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs615-ride" + +CONFIG_REMAKE_ELF=y + +# Address where U-Boot will be loaded +CONFIG_TEXT_BASE=0x9fc00000 diff --git a/configs/qcom_qcs8300_defconfig b/configs/qcom_qcs8300_defconfig new file mode 100644 index 00000000000..5fffcddc16e --- /dev/null +++ b/configs/qcom_qcs8300_defconfig @@ -0,0 +1,21 @@ +# Configuration for building U-Boot to be flashed +# to the uefi partition of QCS8300 dev boards with +# the "Linux Embedded" partition layout (which have +# a dedicated "uefi_a" partition for edk2/U-Boot) + +#include "qcom_defconfig" + +# Otherwise buildman thinks this isn't an ARM platform +CONFIG_ARM=y + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x99C000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 + +# Address where U-Boot will be loaded +CONFIG_TEXT_BASE=0xaf000000 +CONFIG_REMAKE_ELF=y + +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs8300-ride" diff --git a/configs/qcs9100_defconfig b/configs/qcs9100_defconfig index 10ff4d25398..cd48973599b 100644 --- a/configs/qcs9100_defconfig +++ b/configs/qcs9100_defconfig @@ -14,5 +14,8 @@ CONFIG_DEBUG_UART_CLOCK=14745600 # Address where U-Boot will be loaded CONFIG_TEXT_BASE=0xaf000000 CONFIG_REMAKE_ELF=y - CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs9100-ride-r3" +CONFIG_ENV_IS_IN_SCSI=y +CONFIG_SCSI_ENV_PART_UUID="71cb9cd0-acf1-b6cb-ad91-be9572fe11a9" +# CONFIG_ENV_IS_DEFAULT is not set +# CONFIG_ENV_IS_NOWHERE is not set diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index a444899db33..3e734e57c4a 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ROOTPATH=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index b9cb780200e..cdffda26281 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -16,7 +16,7 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_CMD_SPAWN=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 8a09d80da11..3d065b6a9fb 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_CMD_SPAWN=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index c4b6d57020b..15f1a5d973d 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -20,7 +20,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 6b2fed4ad16..bf9a0b07400 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -16,7 +16,7 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_CMD_SPAWN=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 95f24ac3d55..6cc42817970 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -19,7 +19,7 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_CMD_SPAWN=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index d2b0aec8d3c..1c7cef056c4 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -19,7 +19,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 2b88eb41a8f..c16fa5726b6 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -62,7 +62,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_INTERFACE="virtio" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index c12913e94b3..a3210bc4a5c 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -45,7 +45,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_INTERFACE="virtio" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 72bd255eafa..39afb837e41 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_KVM_VIRT_INS=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_BLOBLIST_SIZE_RELOC=0x2000 diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index f13001390d4..92ba48f6af9 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_KVM_VIRT_INS=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 diff --git a/configs/qnap-ts433-rk3568_defconfig b/configs/qnap-ts433-rk3568_defconfig index 569950ef11b..e2923233980 100644 --- a/configs/qnap-ts433-rk3568_defconfig +++ b/configs/qnap-ts433-rk3568_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 0a03e6d0d9d..4ab362f0d43 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_DFU=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig index 96a5b81ed20..5ef81682caa 100644 --- a/configs/r8a77970_v3msk_defconfig +++ b/configs/r8a77970_v3msk_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_MMC=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index d46548256d7..3ebb1e73284 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_MMC=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig index 51e8d2bd368..1980191ceb6 100644 --- a/configs/r8a77980_v3hsk_defconfig +++ b/configs/r8a77980_v3hsk_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_MMC=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_RCAR_I2C=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index e7f63110420..414bfdebab1 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -31,8 +31,8 @@ CONFIG_CMD_USB=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index afabe788c45..12d92067de5 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -30,8 +30,8 @@ CONFIG_CMD_USB=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index 5d9cfc97a97..41217fa5776 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -19,7 +19,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_REMOTEPROC_RENESAS_APMU=y CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a779g3_sparrowhawk_defconfig b/configs/r8a779g3_sparrowhawk_defconfig index 7202828cd66..9aa8dc83317 100644 --- a/configs/r8a779g3_sparrowhawk_defconfig +++ b/configs/r8a779g3_sparrowhawk_defconfig @@ -24,7 +24,12 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_GPIO_HOG=y CONFIG_REMOTEPROC_RENESAS_APMU=y CONFIG_BITBANGMII=y +CONFIG_CMD_PCI=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NVME_PCI=y +CONFIG_PCI=y +CONFIG_PCI_RCAR_GEN4=y +CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index 5b9ad93a596..33009429315 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -14,7 +14,7 @@ CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779h0-gray CONFIG_DEFAULT_FDT_FILE="r8a779h0-gray-hawk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/radxa-zero-3-rk3566_defconfig b/configs/radxa-zero-3-rk3566_defconfig index 062eb5d240d..ea2e022eecb 100644 --- a/configs/radxa-zero-3-rk3566_defconfig +++ b/configs/radxa-zero-3-rk3566_defconfig @@ -38,7 +38,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_LIST="rockchip/rk3566-radxa-zero-3w rockchip/rk3566-radxa-zero-3e" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig index c1f5d405877..de2df05ed95 100644 --- a/configs/radxa-zero2_defconfig +++ b/configs/radxa-zero2_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig index 82db167e071..e0651401eb6 100644 --- a/configs/radxa-zero_defconfig +++ b/configs/radxa-zero_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 35904f19152..15ec0a45901 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -37,8 +37,8 @@ CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index 52f7d8701dd..41bdee19682 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -32,8 +32,8 @@ CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/renesas_rcar4.config b/configs/renesas_rcar4.config index 87d6a60e56e..085d02b51c3 100644 --- a/configs/renesas_rcar4.config +++ b/configs/renesas_rcar4.config @@ -12,6 +12,6 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SYS_I2C_RCAR_I2C=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTARGS=y CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index 6ec151218eb..e7c0a7e1eae 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -41,8 +41,8 @@ CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index a6562d03edc..b3e69b90d4f 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -63,7 +63,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 24c6c59ac2b..2ed3eb546c9 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -44,8 +44,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 25eaebb8be9..f0a1aaf8beb 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 9261e128da7..fc79cfb6e15 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -40,8 +40,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 89348a4fc77..02d0dbd0132 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 881a1eb7041..cfcce408c8c 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y diff --git a/configs/rock-3b-rk3568_defconfig b/configs/rock-3b-rk3568_defconfig index 0f83eaae69d..2dac4b12614 100644 --- a/configs/rock-3b-rk3568_defconfig +++ b/configs/rock-3b-rk3568_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig index c2d2049af01..1e25a3765dc 100644 --- a/configs/rock-3c-rk3566_defconfig +++ b/configs/rock-3c-rk3566_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index fd92bf51f92..992f5bc2aa4 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 19e43195fac..6a8ea95d88b 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig index 960b12c6ed5..ae553a60456 100644 --- a/configs/rock-5-itx-rk3588_defconfig +++ b/configs/rock-5-itx-rk3588_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 9092a859f6d..219f42bc7d4 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 238f1353bda..8130e126b97 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index df340b65933..4b84223be33 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -38,8 +38,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/rock-pi-e-v3-rk3328_defconfig b/configs/rock-pi-e-v3-rk3328_defconfig index 9c31cd395c6..39bbed8fdbe 100644 --- a/configs/rock-pi-e-v3-rk3328_defconfig +++ b/configs/rock-pi-e-v3-rk3328_defconfig @@ -39,8 +39,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 8a15c47edd7..a719e93d20b 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 92c9f3d8f8a..0a88037cefd 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index eb0ca5c246c..1dedbb1e865 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/rock-s0-rk3308_defconfig b/configs/rock-s0-rk3308_defconfig index e806ca8eb18..e3a21132da3 100644 --- a/configs/rock-s0-rk3308_defconfig +++ b/configs/rock-s0-rk3308_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index e76a61c74cb..35f449ab567 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 676cd38c55d..12cdf2e9e21 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -45,8 +45,8 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index f392e0709dc..db121f03ae6 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -35,8 +35,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index b6cb87df4a8..71e504713c1 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -43,7 +43,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_SPL_SIMPLE_BUS is not set diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 25a600ecaaf..24b81f794c3 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SATA=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 8d29d991606..18165be1c20 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_BCM2835_GPIO=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 1b8676e1d10..7b74e963530 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_BCM2835_GPIO=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index abc10a79ada..4644ebd4cd5 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_BCM2835_GPIO=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index b05a9193666..9de74c60208 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DFU_MMC=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 267e4978e6e..c7dbcd2970e 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DFU_MMC=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index fc58ea1fa65..9dd87bf81aa 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 993b79703b7..8362242b97f 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 64e6df41d83..e7a1961549d 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_BCM2835_GPIO=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index b2930e8044d..6084336fc21 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -77,7 +77,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_USE_ROOTPATH=y diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index 5e19d365027..0b91337b17b 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -23,7 +23,7 @@ CONFIG_OF_LIST="renesas/r8a774a1-beacon-rzg2m-kit renesas/r8a774b1-beacon-rzg2n- CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DM_PCA953X=y CONFIG_SYS_I2C_RCAR_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y diff --git a/configs/s400_defconfig b/configs/s400_defconfig index f6f461aa480..13456b17bdc 100644 --- a/configs/s400_defconfig +++ b/configs/s400_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig index 548963c933f..0b265f104e4 100644 --- a/configs/s5p4418_nanopi2_defconfig +++ b/configs/s5p4418_nanopi2_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_NO_NET=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_NEXELL=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 084e19e1258..3c70c1ccfc4 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NO_NET=y CONFIG_DFU_MMC=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index 190ec961b97..e66d29ce722 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=samsung-onenand:128k(s-boot),896k(bootloader),256k(params),2816k(config),8m(csa),7m(kernel),1m(log),12m(modem),60m(qboot),-(UBI)" CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NO_NET=y CONFIG_DFU_MMC=y diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index be89b670c60..134bac5aa54 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/sam9x60_curiosity_mmc1_defconfig b/configs/sam9x60_curiosity_mmc1_defconfig index 114589ce9af..61f4db62c09 100644 --- a/configs/sam9x60_curiosity_mmc1_defconfig +++ b/configs/sam9x60_curiosity_mmc1_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/sam9x60_curiosity_mmc_defconfig b/configs/sam9x60_curiosity_mmc_defconfig index f4e663f1923..878c95fa82f 100644 --- a/configs/sam9x60_curiosity_mmc_defconfig +++ b/configs/sam9x60_curiosity_mmc_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index 1e542e2de5c..443772e6b6a 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index c1754e80dd1..b2fe5e474da 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -54,8 +54,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index 8696b08b51f..c96525bf283 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/sam9x75_curiosity_mmc_defconfig b/configs/sam9x75_curiosity_mmc_defconfig new file mode 100644 index 00000000000..5688a6524eb --- /dev/null +++ b/configs/sam9x75_curiosity_mmc_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_ARCH_AT91=y +CONFIG_TEXT_BASE=0x23f00000 +CONFIG_SYS_MALLOC_LEN=0x81000 +CONFIG_SYS_MALLOC_F_LEN=0x12000 +CONFIG_TARGET_SAM9X75_CURIOSITY=y +CONFIG_ATMEL_LEGACY=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20015f00 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="microchip/at91-sam9x75_curiosity" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0x22000000 +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=266666666 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sam9x75_curiosity.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y +CONFIG_AT91_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_MCHP_PIT64B_TIMER=y +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 2e5a4acf27d..1618d0fd413 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -68,7 +68,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 11a536d714c..c7ec72dd1a9 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -68,7 +68,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 86cb5c287be..779c5fd017f 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -67,7 +67,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 014f0093eee..d7f2a0ad0cf 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -72,7 +72,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index efe23115f62..bb28296107f 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -76,7 +76,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d29_curiosity_mmc1_defconfig b/configs/sama5d29_curiosity_mmc1_defconfig index c8976eec02d..4e56c670357 100644 --- a/configs/sama5d29_curiosity_mmc1_defconfig +++ b/configs/sama5d29_curiosity_mmc1_defconfig @@ -68,7 +68,7 @@ CONFIG_OF_CONTROL=y # CONFIG_OF_TAG_MIGRATE is not set CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SAMA5D29" CONFIG_VERSION_VARIABLE=y diff --git a/configs/sama5d29_curiosity_mmc_defconfig b/configs/sama5d29_curiosity_mmc_defconfig index 7fe1a5b7552..28d5626a2a5 100644 --- a/configs/sama5d29_curiosity_mmc_defconfig +++ b/configs/sama5d29_curiosity_mmc_defconfig @@ -67,7 +67,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(bootstrap)ro,1M(u-boot)ro,256k(env)r CONFIG_OF_CONTROL=y # CONFIG_OF_TAG_MIGRATE is not set CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SAMA5D29" CONFIG_VERSION_VARIABLE=y diff --git a/configs/sama5d29_curiosity_qspiflash_defconfig b/configs/sama5d29_curiosity_qspiflash_defconfig index fd3551131db..e19e39cd6dc 100644 --- a/configs/sama5d29_curiosity_qspiflash_defconfig +++ b/configs/sama5d29_curiosity_qspiflash_defconfig @@ -67,7 +67,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(bootstrap)ro,1M(u-boot)ro,256k(env)r CONFIG_OF_CONTROL=y # CONFIG_OF_TAG_MIGRATE is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SAMA5D29" CONFIG_VERSION_VARIABLE=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index c27b181f19e..15d51565bc2 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -75,7 +75,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig index 463951a9d02..3cf4c9692b0 100644 --- a/configs/sama5d2_icp_qspiflash_defconfig +++ b/configs/sama5d2_icp_qspiflash_defconfig @@ -60,7 +60,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_UTMI=y diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index e62fd8c600c..7087637f3eb 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_UTMI=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index 0729cad701b..7945e19bac3 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -47,8 +47,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_UTMI=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index 76187ea52ab..2315c5dc516 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -67,7 +67,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index e752863f5e1..7c803cc03f3 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -69,7 +69,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 4b5a3c11a8e..449519ac227 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -69,7 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 8941d8fb582..0eeeb51439c 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -73,7 +73,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 217632cbc30..7ecca597f03 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 595cb9cb17f..4478a2405c8 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -44,8 +44,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 743959cf459..e4706413e76 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 984d8146992..74405df7189 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -70,7 +70,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 0e3eb7d7b01..a733e2cd9d7 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -69,8 +69,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 9d0472dea2a..a2b65e9ad12 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -69,7 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 995c9de1c80..99280f3c480 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -67,8 +67,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index cccdd8e970e..9dcfdd05606 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -70,7 +70,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index c476a9c4230..2a35208fbbe 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -65,7 +65,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_CLK=y CONFIG_SPL_CLK=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 5401f34adc6..2066cbe4213 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -65,8 +65,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_CLK=y CONFIG_SPL_CLK=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 98ec4d75f83..1e60628cb8e 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -70,7 +70,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 6e6e601aab4..2339c47b3a6 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -64,7 +64,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index b22e0dd18a3..230d4015c2e 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -64,8 +64,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 60c11f38460..7eb40867b4f 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -67,7 +67,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama7g54_curiosity_mmc_defconfig b/configs/sama7g54_curiosity_mmc_defconfig index fec883e3c17..856310a95e0 100644 --- a/configs/sama7g54_curiosity_mmc_defconfig +++ b/configs/sama7g54_curiosity_mmc_defconfig @@ -71,7 +71,7 @@ CONFIG_OF_CONTROL=y # CONFIG_OF_TAG_MIGRATE is not set CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SAMA7G54" CONFIG_VERSION_VARIABLE=y diff --git a/configs/sama7g54_curiosity_nandflash_defconfig b/configs/sama7g54_curiosity_nandflash_defconfig index 7a4cdb0d2ab..451e40ce547 100644 --- a/configs/sama7g54_curiosity_nandflash_defconfig +++ b/configs/sama7g54_curiosity_nandflash_defconfig @@ -69,7 +69,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro CONFIG_OF_CONTROL=y # CONFIG_OF_TAG_MIGRATE is not set CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SAMA7G54" CONFIG_VERSION_VARIABLE=y diff --git a/configs/sama7g54_curiosity_qspiflash_defconfig b/configs/sama7g54_curiosity_qspiflash_defconfig index adf5f558e2e..44db2dac32b 100644 --- a/configs/sama7g54_curiosity_qspiflash_defconfig +++ b/configs/sama7g54_curiosity_qspiflash_defconfig @@ -70,7 +70,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro CONFIG_OF_CONTROL=y # CONFIG_OF_TAG_MIGRATE is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SAMA7G54" CONFIG_VERSION_VARIABLE=y diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index e91135433ed..59b4e081066 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_CLK=y diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index 13896f01e49..e151abf0523 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_CLK=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 55ec3287d3a..575a510e40c 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -37,8 +37,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_TEGRA_KEYBOARD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index 6211588fe1b..a2d38c84461 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" CONFIG_USE_NETMASK=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index 6df4e9d2f0f..bebe6870da4 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -51,9 +51,9 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x6000000 diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index 0b561516caf..b7de10d71a9 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -51,9 +51,9 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x6000000 diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 7125d495376..9cdfade9c4c 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=6 # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 52677a27bdc..bbaee0f147f 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -17,7 +17,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index b1c4d00c05e..01963a4e54e 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -37,7 +37,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK=y CONFIG_DM_MTD=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index f70e3db4441..acbea7fe1bb 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_PCI=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y CONFIG_ENV_SPI_BUS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_SPL_CLK=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index c9a44247a86..acdd1ad5205 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_USB=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_RCAR_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_MMC_IO_VOLTAGE=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index 8d24a8dc42c..5d86c8ebae1 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -19,7 +19,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 7253c997b24..ad6230c6b04 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -71,8 +71,8 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index bfc4efec598..a51c22d2339 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index cecbd410976..513ed66a471 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index b1c77c7f43d..85f2d91f375 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index ae6c9b60cd5..529836e7bdd 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -49,9 +49,9 @@ CONFIG_CMD_SQUASHFS=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_BOOTFILE=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 3874b875c82..3d0f555c63c 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -23,7 +23,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index adf6213f70b..faca8200035 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 4ac0a5d9b99..33a6221979a 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -70,7 +70,7 @@ CONFIG_OF_LIST="" CONFIG_ENV_IS_IN_UBI=y CONFIG_ENV_UBI_PART="root" CONFIG_ENV_UBI_VOLUME="env" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 7c6a3c8d081..76fdc0aa4a6 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index f3c142300f2..3c860f97ae9 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 97e5fae0f53..fef4cb90516 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index 69b04979423..74ab8c700da 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 7188c46d98e..32cdf6d3a6c 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 102e781f5c1..4fabd63f2b4 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -45,7 +45,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index fe3eaad12a3..1c9ecbf2bc8 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -45,7 +45,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DFU_MMC=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 19e4ab98d59..52ed0ff7ffa 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -45,7 +45,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 38286f71f84..45d3b2f0807 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index f61a63d835a..bff0c41336f 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index f7ae13c891b..5fe35fe6eb8 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -67,7 +67,7 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 96ce2485a02..fed1dd83dc2 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index d14dc86a742..a08c7c0d9e0 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 820b935b70a..7744ff9a888 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -54,8 +54,8 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 8381dca2649..ed26f2dffde 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 43e3efde2cd..90134d8f3f3 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -61,7 +61,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="Image" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index b4e303ed6dd..f3b6cb717b3 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -61,8 +61,8 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" CONFIG_USE_HOSTNAME=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 93d2736ba89..d17b86b344d 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -68,7 +68,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe000000.nor_flash:13312k(system1),13312k(syst # CONFIG_CMD_IRQ is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xFFF00000 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 473b04a42fe..a223c20224a 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index 3730da52e00..852d7b984ba 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/sonoff-ihost-rv1126_defconfig b/configs/sonoff-ihost-rv1126_defconfig index e94c5e79136..c3bd9101540 100644 --- a/configs/sonoff-ihost-rv1126_defconfig +++ b/configs/sonoff-ihost-rv1126_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_MMC=y CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index d3b6656d631..ebe9b8fe119 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_BUS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_I2C_MUX=y diff --git a/configs/star_defconfig b/configs/star_defconfig index 6665bfa8e90..38cbdec1c3a 100644 --- a/configs/star_defconfig +++ b/configs/star_defconfig @@ -53,8 +53,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index e145ced8db8..3e34e4a87f8 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -56,7 +56,6 @@ CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x400000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2 @@ -85,7 +84,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y @@ -98,7 +97,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SPL_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0X50 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_HS400_SUPPORT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 582b5f38222..c0992f397f6 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_OF_UPSTREAM=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_REGMAP=y diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig index 0a7036a5b47..bca3d871f5c 100644 --- a/configs/stm32746g-eval_defconfig +++ b/configs/stm32746g-eval_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ARM_PL180_MMCI=y diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index 4706a72cb9c..137c91e6a8e 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index 5747187ac3c..a2ce8c80e20 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -24,7 +24,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 80e15c4cdb0..7a1fe576cc3 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 24bf6e6a086..00245dcb750 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ARM_PL180_MMCI=y diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index f1761e50ad9..b849d8f3266 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index e539fce780b..af0a7dacbe2 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ARM_PL180_MMCI=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 93c6c904331..61bbca3ec10 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index a674a202e23..38312e9a5f1 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_STM32_SDMMC2=y # CONFIG_PINCTRL_FULL is not set diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index d63e7219f33..fcbf7177690 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_STM32_SDMMC2=y # CONFIG_PINCTRL_FULL is not set diff --git a/configs/stm32h747-disco_defconfig b/configs/stm32h747-disco_defconfig new file mode 100644 index 00000000000..5bb87eee510 --- /dev/null +++ b/configs/stm32h747-disco_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_TEXT_BASE=0x08000000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="st/stm32h747i-disco" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0xd0400000 +CONFIG_STM32H7=y +CONFIG_TARGET_STM32H747_DISCO=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_DEFAULT_FDT_FILE="stm32h747i-disco" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_NO_NET=y +CONFIG_STM32_SDMMC2=y +# CONFIG_PINCTRL_FULL is not set diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig index a92a57d54ea..8a7c45f74a4 100644 --- a/configs/stm32h750-art-pi_defconfig +++ b/configs/stm32h750-art-pi_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_DM_DMA=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 530f6aa6380..18ec7f4601e 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y -CONFIG_SYS_MALLOC_F_LEN=0x180000 +CONFIG_SYS_MALLOC_F_LEN=0x210000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000 CONFIG_ENV_OFFSET=0x900000 CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp135f-dk" @@ -50,9 +50,9 @@ CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig index 2da9287ea7b..e5aaadd3920 100644 --- a/configs/stm32mp13_dhcor_defconfig +++ b/configs/stm32mp13_dhcor_defconfig @@ -34,8 +34,8 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_MMC_ENV_DEV=0 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_DEVICE_INDEX=0 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_PHY_REALTEK=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_RESET_SCMI=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index fc095ac0de1..cfbe5a4ae91 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -57,8 +57,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index b243c45d690..f6ca1700a5f 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -57,8 +57,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index e635c726459..16524245ce1 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -57,8 +57,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 9e7849ff8f0..3348b3f0546 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -57,8 +57,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" diff --git a/configs/stm32mp15-odyssey_defconfig b/configs/stm32mp15-odyssey_defconfig index 74fd2fb8e63..a317a6cae11 100644 --- a/configs/stm32mp15-odyssey_defconfig +++ b/configs/stm32mp15-odyssey_defconfig @@ -59,12 +59,12 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index e3090ec2a50..4c8ad87e72b 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -88,12 +88,12 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y # CONFIG_SPL_ENV_IS_NOWHERE is not set # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 5ddec18b520..b3ec3898861 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -60,12 +60,12 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index f0e6b64ffde..09383ed4824 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -61,12 +61,12 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 317a6d5ecd6..a10f090c347 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y -CONFIG_SYS_MALLOC_F_LEN=0x400000 +CONFIG_SYS_MALLOC_F_LEN=0x600000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000 CONFIG_ENV_OFFSET=0x900000 CONFIG_ENV_SECT_SIZE=0x40000 @@ -43,11 +43,11 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_NO_NET=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config index 01d65cfd893..777a02dfe15 100644 --- a/configs/stm32mp_dhsom.config +++ b/configs/stm32mp_dhsom.config @@ -83,8 +83,8 @@ CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_SYS_I2C_STM32F7=y CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_PROMPT="STM32MP> " -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_TFTP_TSIZE=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 79b21acd032..ae1fa34df2a 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -36,7 +36,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_CS=1 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="stmark2" CONFIG_NO_NET=y diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig index da19b34e64a..4cd543ccb9c 100644 --- a/configs/surface-rt_defconfig +++ b/configs/surface-rt_defconfig @@ -49,8 +49,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 14395a79ad2..2d473c8548a 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_FPGA_XILINX=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 29fa4ea42af..793a7f6cfa6 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -81,8 +81,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 95cff26fe28..1449660cffe 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -21,7 +21,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_PHY_GIGE=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index c307d8c23d0..070dce234d6 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -67,9 +67,9 @@ CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 1af1aa4e0bf..39fb127ce35 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 7cb13f9f5af..5e50b6711ec 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_MTD_RAW_NAND=y CONFIG_TEGRA_NAND=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/tegratab_defconfig b/configs/tegratab_defconfig index f0f83218ba5..00a0843d4d0 100644 --- a/configs/tegratab_defconfig +++ b/configs/tegratab_defconfig @@ -52,8 +52,8 @@ CONFIG_TEGRA_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/tf701t_defconfig b/configs/tf701t_defconfig index 69bc945568d..a9976bf0388 100644 --- a/configs/tf701t_defconfig +++ b/configs/tf701t_defconfig @@ -52,8 +52,8 @@ CONFIG_TEGRA_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index b9eedc6b754..39d8c948af1 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -13,10 +13,9 @@ CONFIG_SPL_BSS_MAX_SIZE=0x10000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y -# CONFIG_SMP is not set CONFIG_TARGET_TH1520_LPI4A=y CONFIG_ARCH_RV64I=y -CONFIG_OF_BOARD_FIXUP=y +CONFIG_RISCV_SMODE=y CONFIG_SYS_BOOT_GET_CMDLINE=y CONFIG_SYS_BOOT_GET_KBD=y # CONFIG_EFI_LOADER is not set @@ -75,7 +74,7 @@ CONFIG_MMC_SPEED_MODE_SET=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_SLEEP is not set CONFIG_PARTITION_TYPE_GUID=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NO_NET=y # CONFIG_BLOCK_CACHE is not set @@ -96,7 +95,6 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_SPL_THEAD_TH1520_DDR=y CONFIG_SYS_NS16550=y -CONFIG_RISCV_TIMER=y CONFIG_AES=y CONFIG_BLAKE2=y CONFIG_SHA512=y @@ -107,3 +105,4 @@ CONFIG_ZLIB_UNCOMPRESS=y CONFIG_BZIP2=y CONFIG_ZSTD=y CONFIG_LIB_RATIONAL=y +CONFIG_PINCTRL=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index fed54bc8207..b14e83f313a 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -49,8 +49,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index af81e78ccf5..07d4eee01d4 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -48,8 +48,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 0c9e6090617..3626839857e 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -46,8 +46,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index dfcc08bbce5..a72f487ccee 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -63,7 +63,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index fcfcee7f3ec..7dd75bfe365 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -31,7 +31,7 @@ CONFIG_SYS_PROMPT="ThunderX_88XX> " # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_SAVEENV is not set # CONFIG_CMD_ENV_EXISTS is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_MMC is not set CONFIG_DM_SERIAL=y diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig index c14bd9774e9..335ea4d8de3 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -60,7 +60,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 31fc67aecd2..afbb394228f 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -45,8 +45,8 @@ CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 8f20a836511..876086573d3 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -45,8 +45,8 @@ CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index e64bb768440..c90dfe517d6 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -23,7 +23,7 @@ CONFIG_CMD_ELF=n CONFIG_CMD_EXTENSION=n CONFIG_CMD_DATE=n CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_ACPIGEN=n CONFIG_AXI=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 1d0b060ef70..8e8ae74801e 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -62,7 +62,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:0x100000(qspi-boot-bin),-(qspi-rootfs)" CONFIG_CMD_UBI=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 49a6efaae0a..6c89dd40e26 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 5ffcc8b2d94..54849077782 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index 25e6d9623c1..3e7e4264b12 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -90,8 +90,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index 816488b5154..f0f7d7b7e45 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y # CONFIG_ISO_PARTITION is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index d0c5db65177..e2fd022cc38 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 953ceba6626..f98775f1ae3 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -41,8 +41,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index d6706afe040..de5a732463f 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 28b1bfc41f4..291c1f2fa33 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -41,8 +41,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index 7bed776507a..8e6935a3c48 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index 0af80d5c2e1..7c499077d0d 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -41,8 +41,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig index 1317676fe2a..c0a5a2fd02c 100644 --- a/configs/transformer_t20_defconfig +++ b/configs/transformer_t20_defconfig @@ -51,8 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index 335ef326559..eb3e41e68c5 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -55,8 +55,8 @@ CONFIG_OF_LIST="tegra30-asus-p1801-t tegra30-asus-tf201 tegra30-asus-tf300t tegr CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_CLK_GPIO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index f4afd373653..460811dd538 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NO_NET=y CONFIG_DFU_MMC=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 14849d0e691..70f7e06ba9c 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NO_NET=y CONFIG_DFU_MMC=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 47e467e71b7..46f9d43093d 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=48000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_TEGRA=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index ab0fd12bc48..dad17b39436 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -129,7 +129,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/turris_1x_nor_defconfig b/configs/turris_1x_nor_defconfig index a96fae198c7..cc7d4a1e0d6 100644 --- a/configs/turris_1x_nor_defconfig +++ b/configs/turris_1x_nor_defconfig @@ -59,7 +59,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_INITIAL_DTB_READONLY=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth2" # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/turris_1x_sdcard_defconfig b/configs/turris_1x_sdcard_defconfig index 719a394dd65..ee18cc21443 100644 --- a/configs/turris_1x_sdcard_defconfig +++ b/configs/turris_1x_sdcard_defconfig @@ -84,7 +84,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth2" CONFIG_NETCONSOLE=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 5ba7d76f9e6..acfab5755ba 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -53,8 +53,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_OF_LIST="armada-3720-turris-mox armada-3720-ripe-atlas" CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NETCONSOLE=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 29c34f9d549..de39e19ec6d 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -83,7 +83,7 @@ CONFIG_CMD_HASH=y CONFIG_CMD_BTRFS=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth2" CONFIG_ARP_TIMEOUT=200 diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index e5a99b24dab..1ef7a472ace 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -143,7 +143,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/u200_defconfig b/configs/u200_defconfig index a49f87193a1..99c2a8e980a 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_DM_MDIO=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 6fc4576fb7a..2f557801d29 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index 5730dacd060..db0d9e2c789 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 8183edd1f62..d4fb271e03a 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -41,8 +41,8 @@ CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index ece3d293d06..63aead2c352 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -48,7 +48,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)" CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_USE_GATEWAYIP=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 4472609d85e..eceac50ed99 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -49,7 +49,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)" CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_USE_GATEWAYIP=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index e77d793e9ec..782bcc5df77 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)" CONFIG_CMD_UBI=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="Image" CONFIG_USE_GATEWAYIP=y diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index d7fb61c779c..ceed01480eb 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -36,7 +36,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 3e948721e15..06b0f03fbe5 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -24,7 +24,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="usbarmory" CONFIG_DM_I2C=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 9c69d9aef97..0c1c4bb39cc 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_CACHE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" CONFIG_DM_I2C_GPIO=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 3d80197ef38..810dc3f523f 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -40,8 +40,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 5b37a98eeaa..e5ca2f9be90 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -36,8 +36,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 4bdcb4b6c46..584c416bd83 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -1,7 +1,5 @@ CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -28,8 +26,6 @@ CONFIG_SYS_BOOTM_LEN=0x40000000 CONFIG_SYS_LOAD_ADDR=0x88200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xB0000000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -53,13 +49,11 @@ CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_THERMAL=y -CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="Verdin AM62 # " CONFIG_CMD_ADTIMG=y CONFIG_CMD_ASKENV=y @@ -93,8 +87,8 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" @@ -192,8 +186,6 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_AM62=y CONFIG_USB_DWC3_AM62=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index f9580e697ff..c3a2a582f86 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -47,19 +47,13 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/verdin-am62p_a53_defconfig b/configs/verdin-am62p_a53_defconfig new file mode 100644 index 00000000000..e782ad4faca --- /dev/null +++ b/configs/verdin-am62p_a53_defconfig @@ -0,0 +1,199 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_VERDIN_AM62P_A53=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-verdin-wifi-dev" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80c80000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SYS_BOOTM_LEN=0x40000000 +CONFIG_SYS_LOAD_ADDR=0x88200000 +CONFIG_SPL_SIZE_LIMIT=0x80000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTSTD_FULL=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTDELAY=1 +CONFIG_BOOTCOMMAND="bootflow scan -b" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am62p5-verdin-${variant}-${fdt_board}.dtb" +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_THERMAL=y +CONFIG_SYS_PROMPT="Verdin AM62P # " +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BCB=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_VERSION_VARIABLE=y +CONFIG_IP_DEFRAG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x88200000 +CONFIG_FASTBOOT_BUF_SIZE=0x8000000 +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_DM_ETH_PHY=y +CONFIG_RGMII=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65219=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS65219=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_SPL_DFU=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_HEXDUMP=y diff --git a/configs/verdin-am62p_r5_defconfig b/configs/verdin-am62p_r5_defconfig new file mode 100644 index 00000000000..bbdc803eb3a --- /dev/null +++ b/configs/verdin-am62p_r5_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x08000000 +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_K3_QOS=y +CONFIG_TARGET_VERDIN_AM62P_R5=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-verdin-r5" +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SIZE_LIMIT=0x3C000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_CMD_DFU=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_ESM_K3=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 9e7c03e1e88..7db6e81ee6d 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -83,8 +83,8 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 47c28a1e49d..4cc69de041b 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -95,9 +95,9 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index c823cb0a30e..556190728e1 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_TEXT_BASE=0x3f401000 CONFIG_SYS_MALLOC_LEN=0x202000 -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 @@ -43,7 +42,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VYBRID_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index 84e73c0c665..7fe9d822110 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_VF610=y CONFIG_TEXT_BASE=0x3f401000 CONFIG_SYS_MALLOC_LEN=0x0220000 -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x180000 @@ -44,7 +43,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VYBRID_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/videostrong-kii-pro_defconfig b/configs/videostrong-kii-pro_defconfig index af0fdedde4b..9c905becff7 100644 --- a/configs/videostrong-kii-pro_defconfig +++ b/configs/videostrong-kii-pro_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_DM_I2C=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 86087d4539e..216993c57d7 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -40,7 +40,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_AT91_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -51,6 +51,7 @@ CONFIG_PHY_SMSC=y CONFIG_ETH_DESIGNWARE=y CONFIG_MACB=y CONFIG_RMII=y +CONFIG_DM_SERIAL=y CONFIG_ATMEL_USART=y CONFIG_SYSRESET=y CONFIG_SYSRESET_AT91=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 5842916fbdb..e65d0fb9ef2 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -62,9 +62,9 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig index e2604a135cf..8f96c531324 100644 --- a/configs/vocore2_defconfig +++ b/configs/vocore2_defconfig @@ -70,7 +70,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="spi0.0:312k(u-boot),4k(env),4k(factory),2368k(kernel),-(filesystem)" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index a6535975331..c9de6f8ad26 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -55,8 +55,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index e0dc56b1d00..06f8f1ec4d2 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -53,7 +53,7 @@ CONFIG_OF_LIST="imx6q-wandboard-revd1 imx6qp-wandboard-revd1 imx6dl-wandboard-re CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 6b68681553c..5a94062f5e2 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 679b6e8997e..03d68aa9a3f 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig index 89f1f616237..837d922d530 100644 --- a/configs/wetek-core2_defconfig +++ b/configs/wetek-core2_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y diff --git a/configs/wetek-hub_defconfig b/configs/wetek-hub_defconfig index ee5558f220b..954e5cd885c 100644 --- a/configs/wetek-hub_defconfig +++ b/configs/wetek-hub_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_DM_I2C=y diff --git a/configs/wetek-play2_defconfig b/configs/wetek-play2_defconfig index ee7e03643b0..543de4830a1 100644 --- a/configs/wetek-play2_defconfig +++ b/configs/wetek-play2_defconfig @@ -32,7 +32,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SARADC_MESON=y CONFIG_DM_I2C=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 0b4989ca002..0091a897ab6 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/x250_defconfig b/configs/x250_defconfig index dffe85bd6eb..35bef079fd1 100644 --- a/configs/x250_defconfig +++ b/configs/x250_defconfig @@ -45,8 +45,8 @@ CONFIG_CMD_UBI=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_IPV6=y diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig index 685cb842ad1..3081d1203cf 100644 --- a/configs/x3_t30_defconfig +++ b/configs/x3_t30_defconfig @@ -51,8 +51,8 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_EXTCON=y CONFIG_EXTCON_MAX14526=y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 861d1475453..7dde2fc0a8f 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -29,10 +29,9 @@ CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index 9398b4c240d..b96b02c6125 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -30,11 +30,10 @@ CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_UARTLITE=y diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig index c39925bd86a..77fcf4d6865 100644 --- a/configs/xilinx_mbv64_defconfig +++ b/configs/xilinx_mbv64_defconfig @@ -30,10 +30,9 @@ CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig index 811f93a2671..e53c0771baf 100644 --- a/configs/xilinx_mbv64_smode_defconfig +++ b/configs/xilinx_mbv64_smode_defconfig @@ -31,11 +31,10 @@ CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_UARTLITE=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 561459befb6..605a30b9987 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -57,7 +57,7 @@ CONFIG_SYS_ALT_MEMTEST=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_SLEEP is not set -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_MMC is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 21f241e07b1..90d6abd490e 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_MMC_SDHCI=y diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 6cb654c7a4b..df6a4165015 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_MMC_SDHCI=y diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 04dd0cdb507..7cae88b0d9f 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -61,7 +61,7 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_GPIO is not set diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig index ab201566407..30f4885d149 100644 --- a/configs/xilinx_versal_net_mini_emmc_defconfig +++ b/configs/xilinx_versal_net_mini_emmc_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index f4cac522b81..c9866deeaeb 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -66,8 +66,8 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SIMPLE_PM_BUS=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index ddf874f741d..5dc43ba00fd 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -70,8 +70,8 @@ CONFIG_OF_BOARD=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SIMPLE_PM_BUS=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 1cc314dd775..7a7abf66eb5 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -93,8 +93,8 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 48246f1b4f6..22ba8a7cc15 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -117,9 +117,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 33f85f77ce3..736d4bd4efc 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -53,7 +53,7 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_CACHE=y # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_DM_MAILBOX is not set diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 2ddaecd5875..85a6af45c57 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -67,7 +67,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 31bba1712fb..4c01a43b6e4 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -67,7 +67,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 3b202b04ab3..afb50a9ff43 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -48,7 +48,7 @@ CONFIG_CLOCKS=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_DM_MAILBOX is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 67e1a6e7037..a40a4493d5d 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -48,7 +48,7 @@ CONFIG_CLOCKS=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_DM_MAILBOX is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index f2d0d6f16ed..0367c043574 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -69,7 +69,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 # CONFIG_CMD_MP is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig index b9d7797e4b7..d4ec2b59b71 100644 --- a/configs/xilinx_zynqmp_r5_defconfig +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -24,7 +24,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ZYNQ_SERIAL=y CONFIG_TIMER=y CONFIG_CADENCE_TTC_TIMER=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 7807f6240e3..a0067793a41 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -116,9 +116,9 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/yuzukihd-chameleon_defconfig b/configs/yuzukihd-chameleon_defconfig new file mode 100644 index 00000000000..883be12c4ef --- /dev/null +++ b/configs/yuzukihd-chameleon_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-yuzukihd-chameleon" +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x03030303 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x1c12 +CONFIG_DRAM_SUNXI_ODT_EN=0x1 +CONFIG_DRAM_SUNXI_TPR6=0x33808080 +CONFIG_DRAM_SUNXI_TPR10=0x002f0006 +CONFIG_DRAM_SUNXI_TPR11=0xddddcccc +CONFIG_DRAM_SUNXI_TPR12=0xeddc7564 +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_DRAM_CLK=648 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_AXP313_POWER=y +CONFIG_AXP_DCDC3_VOLT=1500 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_MUSB_GADGET=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 7d15903bb3a..4272b7320b6 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -69,7 +69,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index fe4362d3b03..74c4595eb43 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -69,7 +69,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 824758f8289..145b7fd33bb 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -78,7 +78,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_SLEEP is not set CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/disk/part.c b/disk/part.c index 303178161c0..66e2b3a7219 100644 --- a/disk/part.c +++ b/disk/part.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -698,6 +697,45 @@ int part_get_info_by_name(struct blk_desc *desc, const char *name, return -ENOENT; } +int part_get_info_by_uuid(struct blk_desc *desc, const char *uuid, + struct disk_partition *info) +{ + struct part_driver *part_drv; + int ret; + int i; + + if (!CONFIG_IS_ENABLED(PARTITION_UUIDS)) + return -ENOENT; + + part_drv = part_driver_lookup_type(desc); + if (!part_drv) + return -1; + + if (!part_drv->get_info) { + log_debug("## Driver %s does not have the get_info() method\n", + part_drv->name); + return -ENOSYS; + } + + for (i = 1; i < part_drv->max_entries; i++) { + ret = part_drv->get_info(desc, i, info); + if (ret != 0) { + /* + * Partition with this index can't be obtained, but + * further partitions might be, so keep checking. + */ + continue; + } + + if (!strncasecmp(uuid, disk_partition_uuid(info), UUID_STR_LEN)) { + /* matched */ + return i; + } + } + + return -ENOENT; +} + /** * Get partition info from device number and partition name. * diff --git a/disk/part_amiga.c b/disk/part_amiga.c index 5b8ae5762d3..22bf99f1b88 100644 --- a/disk/part_amiga.c +++ b/disk/part_amiga.c @@ -6,7 +6,6 @@ */ #include #include -#include #include "part_amiga.h" #include #include diff --git a/disk/part_dos.c b/disk/part_dos.c index 96f748702fd..5c77225cef9 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/disk/part_efi.c b/disk/part_efi.c index 932d058c184..fb1ed534f86 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -216,6 +215,34 @@ int get_disk_guid(struct blk_desc *desc, char *guid) return 0; } +int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e) +{ + ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); + gpt_entry *gpt_pte = NULL; + + /* "part" argument must be at least 1 */ + if (part < 1) { + log_debug("Invalid Argument(s)\n"); + return -EINVAL; + } + + /* This function validates AND fills in the GPT header and PTE */ + if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1) + return -EINVAL; + + if (part > le32_to_cpu(gpt_head->num_partition_entries) || + !is_pte_valid(&gpt_pte[part - 1])) { + log_debug("Invalid partition number %d\n", part); + free(gpt_pte); + return -EPERM; + } + + memcpy(gpt_e, &gpt_pte[part - 1], sizeof(*gpt_e)); + + free(gpt_pte); + return 0; +} + static void __maybe_unused part_print_efi(struct blk_desc *desc) { ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); @@ -261,45 +288,32 @@ static void __maybe_unused part_print_efi(struct blk_desc *desc) static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part, struct disk_partition *info) { - ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); - gpt_entry *gpt_pte = NULL; + gpt_entry gpt_pte = {}; + int ret; - /* "part" argument must be at least 1 */ - if (part < 1) { - log_debug("Invalid Argument(s)\n"); - return -EINVAL; - } - - /* This function validates AND fills in the GPT header and PTE */ - if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1) - return -EINVAL; - - if (part > le32_to_cpu(gpt_head->num_partition_entries) || - !is_pte_valid(&gpt_pte[part - 1])) { - log_debug("Invalid partition number %d\n", part); - free(gpt_pte); - return -EPERM; - } + ret = part_get_gpt_pte(desc, part, &gpt_pte); + if (ret) + return ret; /* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */ - info->start = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].starting_lba); + info->start = (lbaint_t)le64_to_cpu(gpt_pte.starting_lba); /* The ending LBA is inclusive, to calculate size, add 1 to it */ - info->size = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1 + info->size = (lbaint_t)le64_to_cpu(gpt_pte.ending_lba) + 1 - info->start; info->blksz = desc->blksz; snprintf((char *)info->name, sizeof(info->name), "%s", - print_efiname(&gpt_pte[part - 1])); + print_efiname(&gpt_pte)); strcpy((char *)info->type, "U-Boot"); - info->bootable = get_bootable(&gpt_pte[part - 1]); - info->type_flags = gpt_pte[part - 1].attributes.fields.type_guid_specific; + info->bootable = get_bootable(&gpt_pte); + info->type_flags = gpt_pte.attributes.fields.type_guid_specific; if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { - uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, + uuid_bin_to_str(gpt_pte.unique_partition_guid.b, (char *)disk_partition_uuid(info), UUID_STR_FORMAT_GUID); } if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) { - uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b, + uuid_bin_to_str(gpt_pte.partition_type_guid.b, (char *)disk_partition_type_guid(info), UUID_STR_FORMAT_GUID); } @@ -307,8 +321,6 @@ static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part, log_debug("start 0x" LBAF ", size 0x" LBAF ", name %s\n", info->start, info->size, info->name); - /* Remember to free pte */ - free(gpt_pte); return 0; } diff --git a/disk/part_mac.c b/disk/part_mac.c index 21c85942fd8..dd3ce0be832 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "part_mac.h" #include diff --git a/doc/api/index.rst b/doc/api/index.rst index 506843ed74a..cf9d21e4c1c 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -17,7 +17,6 @@ U-Boot API documentation interrupt led linker_lists - lmb logging nvmem part diff --git a/doc/api/lmb.rst b/doc/api/lmb.rst deleted file mode 100644 index 2095bfa1618..00000000000 --- a/doc/api/lmb.rst +++ /dev/null @@ -1,7 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -Logical memory blocks -===================== - -.. kernel-doc:: include/lmb.h - :internal: diff --git a/doc/board/broadcom/bcm7xxx.rst b/doc/board/broadcom/bcm7xxx.rst index f1994d9f975..f559d5c290a 100644 --- a/doc/board/broadcom/bcm7xxx.rst +++ b/doc/board/broadcom/bcm7xxx.rst @@ -149,10 +149,8 @@ and with a generic ARMv7 root file system. * to the Linux source tree as a .dts file. * * To support modifications to the device tree - * in-place in U-Boot, add to Linux's - * arch/arm/boot/dts/Makefile: - * - * DTC_FLAGS ?= -p 4096 + * in-place in U-Boot, set the config variable + * CONFIG_SYS_DTC_PAD_BYTES as needed. * * This will leave some padding in the DTB and * thus reserve room for node additions. diff --git a/doc/board/index.rst b/doc/board/index.rst index 3c5a2c7d1cf..e084c7fb1df 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -38,6 +38,7 @@ Board-specific doc kontron/index lenovo/index lg/index + liebherr/index mediatek/index microchip/index microsoft/index diff --git a/doc/board/liebherr/btt.rst b/doc/board/liebherr/btt.rst new file mode 100644 index 00000000000..d22ffa205bd --- /dev/null +++ b/doc/board/liebherr/btt.rst @@ -0,0 +1,34 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Lukasz Majewski + +BTT devices +=========== + +Those devices are based on IMX's IMX287 SoC. The description regarding the +**btt** family of boards (i.e. `btt3` and `bttc`) is identical as the one for +the already supported **xea** board. + +Building +-------- + +Make sure that `CROSS_COMPILE` is set appropriately: + +.. code-block:: text + + $ make imx28_btt3_defconfig + $ make -j4 u-boot.sb u-boot.img + +Now you should see `u-boot.sb` and `u-boot.img` files in the build directory. + +For initial bringup - one can use `uuu` utulity to boot till u-boot prompt +(USB connection with the board is required). + +Flashing +-------- + +Via U-Boot: + +.. code-block:: text + + => run update_spl + => run update_uboot diff --git a/doc/board/liebherr/index.rst b/doc/board/liebherr/index.rst new file mode 100644 index 00000000000..d8db6bd188c --- /dev/null +++ b/doc/board/liebherr/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Liebherr +======== + +.. toctree:: + :maxdepth: 2 + + btt diff --git a/doc/board/qualcomm/board.rst b/doc/board/qualcomm/board.rst index 003d59a18eb..642c5095261 100644 --- a/doc/board/qualcomm/board.rst +++ b/doc/board/qualcomm/board.rst @@ -23,10 +23,7 @@ Installation ------------ Build ^^^^^ - - $ ./tools/buildman/buildman -o .output qcom - -This will build ``.output/u-boot-nodtb.bin`` using the ``qcom_defconfig``. +We will build ``u-boot-nodtb.bin`` from the u-boot source tree. Generate FIT image (optional) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -81,19 +78,20 @@ Steps: - Build u-boot -As above:: +Use the following commands:: - ./tools/buildman/buildman -o .output qcom + make CROSS_COMPILE=aarch64-linux-gnu- O=.output qcom_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- O=.output -j$(nproc) Or for db410c (and other boards not supported by the generic target):: make CROSS_COMPILE=aarch64-linux-gnu- O=.output dragonboard410c_defconfig - make O=.output -j$(nproc) + make CROSS_COMPILE=aarch64-linux-gnu- O=.output -j$(nproc) Or for smartphones:: make CROSS_COMPILE=aarch64-linux-gnu- O=.output qcom_defconfig qcom-phone.config - make O=.output -j$(nproc) + make CROSS_COMPILE=aarch64-linux-gnu- O=.output -j$(nproc) - gzip u-boot:: @@ -119,6 +117,13 @@ Or with no FIT image:: mkbootimg --kernel u-boot-nodtb.bin.gz-dtb \ --output boot.img --pagesize 4096 --base 0x80000000 +Other devices with boot image version 2 can be built like this example:: + + mkbootimg --pagesize 4096 --header_version 2 \ + --kernel_offset 0x00008000 --kernel u-boot-nodtb.bin.gz \ + --dtb_offset 0x01f00000 --dtb dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dtb \ + --output boot.img + - Flash boot.img using fastboot and erase dtbo to avoid conflicts with our DTB: .. code-block:: bash diff --git a/doc/board/qualcomm/dragonwing.rst b/doc/board/qualcomm/dragonwing.rst new file mode 100644 index 00000000000..d4899415309 --- /dev/null +++ b/doc/board/qualcomm/dragonwing.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. sectionauthor:: Balaji Selvanathan + +Qualcomm DragonWing +======================================== + +Qualcomm DragonWing are industrial-grade boards that provides various series +of processors such as IQ6 (QCS615), IQ8 (QCS8300) and IQ9 (QCS9100). +These SoCs are used for factory/industry based applications. +More information can be found on the `Qualcomm's IQ6 product page`_, +`Qualcomm's IQ8 product page`_ and `Qualcomm's IQ9 product page`_. + +.. _Qualcomm's IQ6 product page: https://docs.qualcomm.com/bundle/publicresource/87-83838-1_REV_A_Qualcomm_IQ6_Series_Product_Brief.pdf +.. _Qualcomm's IQ8 product page: https://docs.qualcomm.com/bundle/publicresource/87-83839-1_REV_A_Qualcomm_IQ8_Series_Product_Brief________.pdf +.. _Qualcomm's IQ9 product page: https://docs.qualcomm.com/bundle/publicresource/87-83840-1_REV_A_Qualcomm_IQ9_Series_Product_Brief.pdf + +Installation +------------ +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``QCS615``, ``QCS8300`` or ``QCS9100``:: + + $ export CROSS_COMPILE= + $ make qcom_qcs8300_defconfig + $ make -j8 u-boot.mbn + +Although the board does not have secure boot set up by default, +the firmware still expects firmware ELF images to be "signed". The signature +does not provide any security in this case, but it provides the firmware with +some required metadata. + +To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + + $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf + +Then flash the resulting ``u-boot.mbn`` to the ``uefi_a`` partition +on your device with ``fastboot flash uefi_a u-boot.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +Note that fastboot is not yet supported in U-Boot on Dragonwing boards, as a result, to flash +back the original firmware, or new versoins of the U-Boot, EDL mode must be used. + +A tool like bkerler's `edl`_ can be used for flashing with the firehose loader (for example, for QCS9100 +the firehose loader can be obtained from `dragonwing IQ9 bootbinaries`.) :: + +$ edl.py --loader /path/to/prog_firehose_ddr.elf w uefi_a u-boot.mbn + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign +.. _edl: https://github.com/bkerler/edl +.. _dragonwing IQ9 bootbinaries: https://artifacts.codelinaro.org/ui/native/qli-ci/flashable-binaries/qimpsdk/qcs9075-rb8-core-kit diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst index e2fcbfa19c2..ccf834208e9 100644 --- a/doc/board/qualcomm/index.rst +++ b/doc/board/qualcomm/index.rst @@ -8,6 +8,7 @@ Qualcomm dragonboard410c rb3gen2 + dragonwing board phones debugging diff --git a/doc/board/qualcomm/rdp.rst b/doc/board/qualcomm/rdp.rst index fd14f1d9829..99cf8eba57c 100644 --- a/doc/board/qualcomm/rdp.rst +++ b/doc/board/qualcomm/rdp.rst @@ -21,13 +21,16 @@ First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``IPQ9574``:: This will build ``u-boot.elf`` in the configured output directory. -Although the RDPs do not have secure boot set up by default, the firmware still -expects firmware ELF images to be "signed". The signature does not provide any -security in this case, but it provides the firmware with some required metadata. +The firmware expects the ELF images to be in MBN format. The `elftombn.py` tool +can be used to convert the ELF images to MBN format. -To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + IPQ9574: (MBN version 6) - $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf + $ python elftombn.py -f u-boot.elf -o u-boot.mbn -v6 + + IPQ5424: (MBN version 7) + + $ python elftombn.py -f u-boot.elf -o u-boot.mbn -v7 Then install the resulting ``u-boot.mbn`` to the ``0:APPSBL`` partition on your device with:: @@ -51,5 +54,5 @@ U-Boot should be running after a reboot (``reset``). Note that the support added is very basic. Restoring the original U-Boot on boards with older version of the software requires a debugger. -.. _qtestsign: https://github.com/msm8916-mainline/qtestsign +.. _elftombn.py: https://git.codelinaro.org/clo/qsdk/oss/system/tools/meta/-/tree/NHSS.QSDK.13.0.5.r2/scripts?ref_type=heads .. _edl: https://github.com/bkerler/edl diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst index 7e4c4ea81ee..acd7ac2698d 100644 --- a/doc/board/thead/lpi4a.rst +++ b/doc/board/thead/lpi4a.rst @@ -55,123 +55,70 @@ DDR driver requires a firmware to function, to build it: cd th1520-firmware lua5.4 ddr-generate.lua src/.lua th1520-ddr-firmware.bin -4. Build U-Boot images +4. Build OpenSBI Firmware -The U-Boot is capable of running in M-Mode, so we can directly build it without -OpenSBI. The DDR firmware should be copied to U-Boot source directory before +TH1520 port of proper U-Boot runs in S mode, thus OpenSBI is required as +SBI firmware to setup S-mode environment and provide SBI calls. It could +be cloned and built for TH1520 as below, + +.. code-block:: bash + + git clone https://github.com/riscv-software-src/opensbi.git + cd opensbi + make PLATFORM=generic + +TH1520 support in OpenSBI requires v1.2 or a more recent version. + +More detailed description of steps required to build fw_dynamic firmware +is beyond the scope of this document. Please refer to OpenSBI +documenation. + +5. Build U-Boot images + +The DDR firmware should be copied to U-Boot source directory before building. -.. code-block:: console +.. code-block:: bash cd cp th1520-ddr-firmware.bin make th1520_lpi4a_defconfig - make + make OPENSBI=/build/platform/generic/firmware/fw_dynamic.bin -This will generate u-boot-dtb.bin and u-boot-with-spl.bin. The former contains -only proper U-Boot and is for chainloading; the later contains also SPL and -DDR firmware and is ready for booting by BROM directly. +This will generate u-boot-with-spl.bin, which contains SPL, DDR firmware, +OpenSBI firmware and proper U-Boot. Booting ~~~~~~~ -Currently, we rely on vendor u-boot to initialize the clock, pinctrl subsystem, -and chain load the mainline u-boot image either via tftp or emmc storage, -then bootup from it. +u-boot-with-spl.bin should be loaded to SRAM through fastboot. Connect +the board to computer with Type-C cable and run -Sample boot log from Lichee PI 4A board via tftp -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +.. code-block:: bash + + fastboot flash ram u-boot-with-spl.bin + fastboot reboot + +Sample boot log from Lichee PI 4A board via fastboot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .. code-block:: none - brom_ver 8 [APP][E] protocol_connect failed, exit. + Starting download of 940681 bytes - U-Boot SPL 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000) - FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init - ddr initialized, jump to uboot - image has no header + downloading of 940681 bytes finished - - U-Boot 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000) - - CPU: rv64imafdcvsu - Model: T-HEAD c910 light - DRAM: 8 GiB - C910 CPU FREQ: 750MHz - AHB2_CPUSYS_HCLK FREQ: 250MHz - AHB3_CPUSYS_PCLK FREQ: 125MHz - PERISYS_AHB_HCLK FREQ: 250MHz - PERISYS_APB_PCLK FREQ: 62MHz - GMAC PLL POSTDIV FREQ: 1000MHZ - DPU0 PLL POSTDIV FREQ: 1188MHZ - DPU1 PLL POSTDIV FREQ: 1188MHZ - MMC: sdhci@ffe7080000: 0, sd@ffe7090000: 1 - Loading Environment from MMC... OK - Error reading output register - Warning: cannot get lcd-en GPIO - LCD panel cannot be found : -121 - splash screen startup cost 16 ms - In: serial - Out: serial - Err: serial - Net: - Warning: ethernet@ffe7070000 using MAC address from ROM - eth0: ethernet@ffe7070000ethernet@ffe7070000:0 is connected to ethernet@ffe7070000. Reconnecting to ethernet@ffe7060000 - - Warning: ethernet@ffe7060000 (eth1) using random MAC address - 42:25:d4:16:5f:fc - , eth1: ethernet@ffe7060000 - Hit any key to stop autoboot: 2 - ethernet@ffe7060000 Waiting for PHY auto negotiation to complete.. done - Speed: 1000, full duplex - Using ethernet@ffe7070000 device - TFTP from server 192.168.8.50; our IP address is 192.168.8.45 - Filename 'u-boot-dtb.bin'. - Load address: 0x1c00000 - Loading: * ######################### - 8 MiB/s - done - Bytes transferred = 376686 (5bf6e hex) - ## Starting application at 0x01C00000 ... - - U-Boot 2023.07-rc2-00004-g1befbe31c1 (May 23 2023 - 18:40:01 +0800) - - CPU: rv64imafdc - Model: Sipeed Lichee Pi 4A - DRAM: 8 GiB - Core: 13 devices, 6 uclasses, devicetree: separate - Loading Environment from ... OK - In: serial@ffe7014000 - Out: serial@ffe7014000 - Err: serial@ffe7014000 - Model: Sipeed Lichee Pi 4A - LPI4A=> - -SPL support is still in an early stage and not all of the functionalities are -available when booting from mainline SPL. When using mainline SPL, -u-boot-with-spl.bin should be loaded to SRAM through fastboot. - -Sample boot log from Lichee PI 4A board via fastboot and mainline SPL -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. code-block:: none - - brom_ver 8 - [APP][E] protocol_connect failed, exit. - Starting download of 636588 bytes - - downloading of 636588 bytes finished - - U-Boot SPL 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000) + U-Boot SPL 2025.07-rc3-00005-g3a0ef515b8bb (May 29 2025 - 10:42:46 +0000) Trying to boot from RAM - U-Boot 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000) + U-Boot 2025.07-rc3-00005-g3a0ef515b8bb (May 29 2025 - 10:42:46 +0000) CPU: thead,c910 Model: Sipeed Lichee Pi 4A DRAM: 8 GiB - Core: 30 devices, 9 uclasses, devicetree: separate + Core: 110 devices, 9 uclasses, devicetree: separate MMC: mmc@ffe7080000: 0, mmc@ffe7090000: 1 Loading Environment from ... OK In: serial@ffe7014000 diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 0d9ccd5a768..01fb9411688 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -49,6 +49,7 @@ K3 SoC based boards in other sections * :doc:`../phytec/phycore-am62x` * :doc:`../phytec/phycore-am62ax` * :doc:`../toradex/verdin-am62` +* :doc:`../toradex/verdin-am62p` Boot Flow Overview ------------------ diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 7d510a80112..68934566ad7 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -11,5 +11,6 @@ Toradex colibri-imx8x smarc-imx8mp verdin-am62 + verdin-am62p verdin-imx8mm verdin-imx8mp diff --git a/doc/board/toradex/verdin-am62p.rst b/doc/board/toradex/verdin-am62p.rst new file mode 100644 index 00000000000..2f3262b8d1e --- /dev/null +++ b/doc/board/toradex/verdin-am62p.rst @@ -0,0 +1,196 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later +.. sectionauthor:: Parth Pancholi + +Verdin AM62P Module +=================== + +- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p +- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit + +Quick Start +----------- + +- Setup environment variables +- Get binary-only TI Linux firmware +- Build the ARM trusted firmware binary +- Build the OPTEE binary +- Build U-Boot for the R5 +- Build U-Boot for the A53 +- Flash to eMMC +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 11.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: bash + + $ export CROSS_COMPILE_32=arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=aarch64-none-linux-gnu- + +Get the TI Linux Firmware +------------------------- + +.. code-block:: bash + + $ echo "Downloading TI Linux Firmware..." + $ git clone -b ti-linux-firmware https://git.ti.com/git/processor-firmware/ti-linux-firmware.git + +Get and Build the ARM Trusted Firmware (Trusted Firmware A) +----------------------------------------------------------- + +.. code-block:: bash + + $ echo "Downloading and building TF-A..." + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + +Then build ATF (TF-A): + +.. code-block:: bash + + $ export CROSS_COMPILE="$CROSS_COMPILE_64" + $ make PLAT=k3 K3_PM_SYSTEM_SUSPEND=1 TARGET_BOARD=lite SPD=opteed + +Get and Build OPTEE +------------------- + +.. code-block:: bash + + $ echo "Downloading and building OPTEE..." + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + +Then build OPTEE: + +.. code-block:: bash + + $ export CROSS_COMPILE="$CROSS_COMPILE_32" + $ export CROSS_COMPILE64="$CROSS_COMPILE_64" + $ make PLATFORM=k3-am62px CFG_ARM64_core=y + +Build U-Boot for R5 +------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE="$CROSS_COMPILE_32" + $ export BINMAN_INDIRS= + $ make O=/tmp/verdin-am62p-r5 verdin-am62p_r5_defconfig + $ make O=/tmp/verdin-am62p-r5 + +Build U-Boot for A53 +-------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ export BL31=/build/k3/lite/release/bl31.bin + $ export TEE=/out/arm-plat-k3/core/tee-pager_v2.bin + $ export BINMAN_INDIRS=" /tmp/verdin-am62p-r5" + $ make O=/tmp/verdin-am62p-a53 verdin-am62p_a53_defconfig + $ make O=/tmp/verdin-am62p-a53 + +Flash to eMMC +------------- + +.. code-block:: console + + => mmc dev 0 1 + => fatload mmc 1 ${loadaddr} tiboot3.bin + => mmc write ${loadaddr} 0x0 0x400 + => fatload mmc 1 ${loadaddr} tispl.bin + => mmc write ${loadaddr} 0x400 0x1000 + => fatload mmc 1 ${loadaddr} u-boot.img + => mmc write ${loadaddr} 0x1400 0x2000 + +As a convenience, instead of having to remember all those addresses and sizes, +one may also use the update U-Boot wrappers: + +.. code-block:: console + + => tftpboot ${loadaddr} tiboot3.bin + => run update_tiboot3 + + => tftpboot ${loadaddr} tispl.bin + => run update_tispl + + => tftpboot ${loadaddr} u-boot.img + => run update_uboot + +Boot +---- + +Output: + +.. code-block:: console + +U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:46:57 +0100) +SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') +Changed A53 CPU frequency to 1250000000Hz (U grade) in DT +SPL initial stack usage: 17080 bytes +Trying to boot from MMC1 +Authentication passed +Authentication passed +Authentication passed +Loading Environment from nowhere... OK +init_env from device 9 not supported! +Authentication passed +Authentication passed +Starting ATF on ARM64 core... + +NOTICE: BL31: v2.12.0(release):v2.12.0-1106-g4301798db096 +NOTICE: BL31: Built : 10:57:58, May 9 2025 +I/TC: +I/TC: OP-TEE version: 4.6.0-18-g76d920d354df (gcc version 12.3.1 20230626 (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35))) #4 Tue May 6 19:48:13 UTC 2025 aarch64 +I/TC: WARNING: This OP-TEE configuration might be insecure! +I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html +I/TC: Primary CPU initializing +I/TC: GIC redistributor base address not provided +I/TC: Assuming default GIC group status and modifier +I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') +I/TC: Activated SA2UL device +I/TC: Enabled firewalls for SA2UL TRNG device +I/TC: SA2UL TRNG initialized +I/TC: SA2UL Drivers initialized +I/TC: HUK Initialized +I/TC: Primary CPU switching to normal world boot + +U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) +SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') +SPL initial stack usage: 1760 bytes +HW CFG: 0x00 +Trying to boot from MMC1 +Authentication passed +Authentication passed + + +U-Boot 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) + +SoC: AM62PX SR1.0 HS-FS +DRAM: 2 GiB +Core: 147 devices, 31 uclasses, devicetree: separate +MMC: mmc@fa10000: 0, mmc@fa00000: 1 +Loading Environment from MMC... Reading from MMC(0)... OK +In: serial@2800000 +Out: serial@2800000 +Err: serial@2800000 +Model: Toradex 0099 Verdin AM62P Quad 2GB WB IT V1.0A +Serial#: 15664919 +Carrier: Toradex Dahlia V1.1D, Serial# 11287149 +am65_cpsw_nuss ethernet@8000000: K3 CPSW: nuss_ver: 0x6BA01903 cpsw_ver: 0x6BA81903 ale_ver: 0x00290105 Ports:2 +Setting variant to wifi +Net: +Warning: ethernet@8000000port@1 MAC addresses don't match: +Address in ROM is 58:a1:5f:b8:93:f9 +Address in environment is 00:14:2d:ef:07:17 +eth0: ethernet@8000000port@1 [PRIME]Could not get PHY for mdio@f00: addr 7 +am65_cpsw_nuss_port ethernet@8000000port@2: phy_connect() failed + +Hit any key to stop autoboot: 0 +Verdin AM62P # + diff --git a/doc/develop/binman_tests.rst b/doc/develop/binman_tests.rst index a632694a6fe..5e44686b8ad 100644 --- a/doc/develop/binman_tests.rst +++ b/doc/develop/binman_tests.rst @@ -431,11 +431,11 @@ error message produced by Binman. Sometimes you need to add several tests, each with their own broken image description, in order to check all the error cases. Sometimes you need to capture the console output of Binman, to check it is -correct. You can to this with ``test_util.capture_sys_output()``, for example: +correct. You can to this with ``terminal.capture()``, for example: .. code-block:: python - with test_util.capture_sys_output() as (_, stderr): + with terminal.capture() as (_, stderr): self._DoTestFile('071_gbb.dts', force_missing_bintools='futility', entry_args=entry_args) err = stderr.getvalue() @@ -572,7 +572,7 @@ In the above example, here are some possible steps: def testNxpImx8ImageMkimageMissing(self): """Test that binman can produce an iMX8 image""" - with test_util.capture_sys_output() as (_, stderr): + with terminal.capture() as (_, stderr): self._DoTestFile('339_nxp_imx8.dts', force_missing_bintools='mkimage') err = stderr.getvalue() diff --git a/doc/develop/bootstd/index.rst b/doc/develop/bootstd/index.rst index 4c4e26ccdb7..ec74fc2fb9d 100644 --- a/doc/develop/bootstd/index.rst +++ b/doc/develop/bootstd/index.rst @@ -12,5 +12,6 @@ Standard Boot qfw android cros + rauc script sandbox diff --git a/doc/develop/bootstd/overview.rst b/doc/develop/bootstd/overview.rst index 9fe5630ab16..0a237359575 100644 --- a/doc/develop/bootstd/overview.rst +++ b/doc/develop/bootstd/overview.rst @@ -443,6 +443,7 @@ Bootmeth drivers are provided for booting from various media: - :doc:`extlinux / syslinux ` boot from a storage device - :doc:`extlinux / syslinux ` boot from a network (PXE) - :doc:`sandbox ` used only for testing + - :doc:`RAUC distro `: A/B system with RAUC from MMC - :doc:`U-Boot scripts