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powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
committed by
Tom Rini
parent
73bc94c6b7
commit
70fd071001
@@ -7,7 +7,7 @@
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*
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* This file contains structures and information for the communication
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* processor channels. Some CPM control and status is available
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* throught the MPC8xx internal memory map. See immap.h for details.
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* through the MPC8xx internal memory map. See immap.h for details.
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* This file only contains what I need for the moment, not the total
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* CPM capabilities. I (or someone else) will add definitions as they
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* are needed. -- Dan
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@@ -81,7 +81,7 @@ typedef struct cpm_buf_desc {
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
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#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
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#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
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#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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@@ -582,8 +582,8 @@ typedef struct spi {
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#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
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#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
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#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
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#define SPMODE_PM(x) ((x) &0xF)
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#define SPMODE_LEN(x) ((((x) - 1) & 0xF) << 4)
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#define SPMODE_PM(x) ((x) & 0xF)
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/* HDLC parameter RAM.
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*/
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@@ -672,7 +672,7 @@ typedef struct hdlc_pram_s {
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#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
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#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
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extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
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void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
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/* CPM interrupt configuration vector.
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*/
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@@ -680,7 +680,7 @@ extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
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#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
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#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
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#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
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#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
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#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
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#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
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#define CICR_IEN ((uint)0x00000080) /* Int. enable */
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#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
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