mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
* Add support for RMU board
* Add support for TQM862L at 100/50 MHz * Patch by Pantelis Antoniou, 02 Jun 2003: major reconstruction of networking code; add "ping" support (outgoing only!)
This commit is contained in:
wdenk
@@ -81,6 +81,7 @@
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#define CFG_CMD_NAND 0x0000800000000000 /* NAND support */
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#define CFG_CMD_BMP 0x0001000000000000 /* BMP support */
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#define CFG_CMD_PORTIO 0x0002000000000000 /* Port I/O */
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#define CFG_CMD_PING 0x0004000000000000 /* ping support */
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#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFF /* ALL commands */
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@@ -113,6 +114,7 @@
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CFG_CMD_NAND | \
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CFG_CMD_PCI | \
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CFG_CMD_PCMCIA | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SAVES | \
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CFG_CMD_SCSI | \
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@@ -64,11 +64,24 @@ int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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#define CMD_TBL_DHCP
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#endif /* CFG_CMD_DHCP */
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#if (CONFIG_COMMANDS & CFG_CMD_PING)
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#define CMD_TBL_PING MK_CMD_TBL_ENTRY( \
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"ping", 4, 2, 1, do_ping, \
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"ping - check if host is reachable\n", \
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"host\n" \
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),
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int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
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#else
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#define CMD_TBL_PING
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#endif /* CFG_CMD_PING */
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#else
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#define CMD_TBL_BOOTP
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#define CMD_TBL_TFTPB
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#define CMD_TBL_RARPB
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#define CMD_TBL_DHCP
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#define CMD_TBL_PING
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#endif /* CFG_CMD_NET */
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#endif
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@@ -1254,7 +1254,11 @@ typedef struct scc_enet {
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#define PA_ENET_TXD ((ushort)0x0008)
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#define PA_ENET_TCLK ((ushort)0x0200)
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#define PA_ENET_RCLK ((ushort)0x0800)
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#if defined(CONFIG_RMU)
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#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
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#else
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#define PB_ENET_TENA ((uint)0x00002000)
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#endif
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#define PC_ENET_CLSN ((ushort)0x0040)
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#define PC_ENET_RENA ((ushort)0x0080)
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@@ -251,14 +251,15 @@
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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* If this is a 80 MHz or 100 MHz CPU,
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* set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
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*/
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
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#define CFG_PLPRCR \
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
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#else /* up to 50 MHz we use a 1:1 clock */
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#endif /* CONFIG_80MHz */
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#endif /* CONFIG_80MHz | CONFIG_100MHz */
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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@@ -267,7 +268,7 @@
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
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#define CFG_SCCR (/* SCCR_TBS | */ \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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@@ -277,7 +278,7 @@
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#endif /* CONFIG_80MHz */
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#endif /* CONFIG_80MHz | CONFIG_100MHz */
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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@@ -346,8 +347,15 @@
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/*
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* FLASH timing:
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*/
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#if defined(CONFIG_80MHz)
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/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
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#if defined(CONFIG_100MHz)
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/* 100 MHz CPU - 50 MHz bus:
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* 0x...926: 9 = OR_CSNT_SAM + OR_BI; 2 = OR_SCY_2_CLK; 6 = OR_TRLX + OR_EHTR
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* ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_2_CLK | OR_EHTR | OR_BI)
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#elif defined(CONFIG_80MHz)
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/* 80 MHz CPU - 40 MHz bus:
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* ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#elif defined(CONFIG_66MHz)
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@@ -415,11 +423,14 @@
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* --------------------------------------------
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* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
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*
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* 50 MHz => 50.000.000 / Divider = 98
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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* 50 MHz => 50.000.000 / Divider = 98
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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* 100 Mhz => 100.000.000 / Divider = 195
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*/
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#if defined(CONFIG_80MHz)
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#if defined(CONFIG_100MHz)
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#define CFG_MAMR_PTA 195
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#elif defined(CONFIG_80MHz)
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#define CFG_MAMR_PTA 156
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#elif defined(CONFIG_66MHz)
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#define CFG_MAMR_PTA 129
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379
include/configs/rmu.h
Normal file
379
include/configs/rmu.h
Normal file
@@ -0,0 +1,379 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#undef CONFIG_MPC860
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#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
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#define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */
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#define CONFIG_RMU 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFA200000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFF800000
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/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
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#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE 0xFFF00000
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/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x00740000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_MLRC10)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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/* up to 50 MHz we use a 1:1 clock */
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#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF00
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/* up to 50 MHz we use a 1:1 clock */
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#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET 0x0100
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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/*#define CFG_DER 0x2002000F*/
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#define CFG_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0 and OR0 (FLASH)
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*/
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#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
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#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
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/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
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#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
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|
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/*
|
||||
* BR1 and OR1 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
|
||||
#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000E00
|
||||
|
||||
#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
|
||||
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
/* RPXLITE mem setting */
|
||||
#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
|
||||
#define CFG_OR3_PRELIM 0xFFFF8910
|
||||
#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
|
||||
#define CFG_OR4_PRELIM 0xFFFE0970
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CFG_MAMR_PTA 20
|
||||
|
||||
/*
|
||||
* Refresh clock Prescalar
|
||||
*/
|
||||
#define CFG_MPTPR MPTPR_PTP_DIV2
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 10 column SDRAM */
|
||||
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*
|
||||
* BCSRx
|
||||
*
|
||||
* Board Status and Control Registers
|
||||
*
|
||||
*/
|
||||
|
||||
#define BCSR0 0xFA400000
|
||||
#define BCSR1 0xFA400001
|
||||
#define BCSR2 0xFA400002
|
||||
#define BCSR3 0xFA400003
|
||||
|
||||
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
|
||||
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
|
||||
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
|
||||
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
|
||||
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
|
||||
#define BCSR0_COLTEST 0x20
|
||||
#define BCSR0_ETHLPBK 0x40
|
||||
#define BCSR0_ETHEN 0x80
|
||||
|
||||
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
|
||||
#define BCSR1_PCVCTL6 0x02
|
||||
#define BCSR1_PCVCTL5 0x04
|
||||
#define BCSR1_PCVCTL4 0x08
|
||||
#define BCSR1_IPB5SEL 0x10
|
||||
|
||||
#define BCSR2_ENPA5HDR 0x08 /* USB Control */
|
||||
#define BCSR2_ENUSBCLK 0x10
|
||||
#define BCSR2_USBPWREN 0x20
|
||||
#define BCSR2_USBSPD 0x40
|
||||
#define BCSR2_USBSUSP 0x80
|
||||
|
||||
#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
|
||||
#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
|
||||
#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
|
||||
#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
|
||||
#define BCSR3_D27 0x10 /* Dip Switch settings */
|
||||
#define BCSR3_D26 0x20
|
||||
#define BCSR3_D25 0x40
|
||||
#define BCSR3_D24 0x80
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -206,7 +206,7 @@
|
||||
|
||||
#define CFG_FIRST_PCI_IRQ 9
|
||||
#define CFG_SECOND_PCI_IRQ 10
|
||||
#define CFG_THIRD_PCI_IRQ 11
|
||||
#define CFG_THIRD_PCI_IRQ 11
|
||||
#define CFG_FORTH_PCI_IRQ 12
|
||||
|
||||
|
||||
|
||||
@@ -200,7 +200,9 @@ typedef struct
|
||||
/*
|
||||
* ICMP stuff (just enough to handle (host) redirect messages)
|
||||
*/
|
||||
#define ICMP_ECHO_REPLY 0 /* Echo reply */
|
||||
#define ICMP_REDIRECT 5 /* Redirect (change route) */
|
||||
#define ICMP_ECHO_REQUEST 8 /* Echo request */
|
||||
|
||||
/* Codes for REDIRECT. */
|
||||
#define ICMP_REDIR_NET 0 /* Redirect Net */
|
||||
@@ -292,11 +294,15 @@ extern int NetState; /* Network loop state */
|
||||
extern int NetRestartWrap; /* Tried all network devices */
|
||||
#endif
|
||||
|
||||
typedef enum { BOOTP, RARP, ARP, TFTP, DHCP } proto_t;
|
||||
typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS } proto_t;
|
||||
|
||||
/* from net/net.c */
|
||||
extern char BootFile[128]; /* Boot File name */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_PING)
|
||||
extern IPaddr_t NetPingIP; /* the ip address to ping */
|
||||
#endif
|
||||
|
||||
/* Initialize the network adapter */
|
||||
extern int NetLoop(proto_t);
|
||||
|
||||
@@ -323,6 +329,9 @@ extern void NetSetTimeout(int, thand_f *); /* Set timeout handler */
|
||||
/* Transmit "NetTxPacket" */
|
||||
extern void NetSendPacket(volatile uchar *, int);
|
||||
|
||||
/* Transmit UDP packet, performing ARP request if needed */
|
||||
extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len);
|
||||
|
||||
/* Processes a received packet */
|
||||
extern void NetReceive(volatile uchar *, int);
|
||||
|
||||
@@ -373,6 +382,9 @@ static inline void NetCopyLong(ulong *to, ulong *from)
|
||||
/* Convert an IP address to a string */
|
||||
extern void ip_to_string (IPaddr_t x, char *s);
|
||||
|
||||
/* Convert a string to ip address */
|
||||
extern IPaddr_t string_to_ip(char *s);
|
||||
|
||||
/* read an IP address from a environment variable */
|
||||
extern IPaddr_t getenv_IPaddr (char *);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user