Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imx

For 2019.04

drivers/gpio/Kconfig

@@ -303,6 +303,29 @@ config DM_PCA953X
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
 
+config SPL_DM_PCA953X
+	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL"
+	depends on DM_GPIO
+	help
+	  Say yes here to provide access to several register-oriented
+	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
+	  models include:
+
+	  4 bits:	pca9536, pca9537
+
+	  8 bits:	max7310, max7315, pca6107, pca9534, pca9538, pca9554,
+			pca9556, pca9557, pca9574, tca6408, xra1202
+
+	  16 bits:	max7312, max7313, pca9535, pca9539, pca9555, pca9575,
+			tca6416
+
+	  24 bits:	tca6424
+
+	  40 bits:	pca9505, pca9698
+
+	  Now, max 24 bits chips and PCA953X compatible chips are
+	  supported
+
 config MPC8XXX_GPIO
 	bool "Freescale MPC8XXX GPIO driver"
 	depends on DM_GPIO

drivers/gpio/Makefile

@@ -9,7 +9,7 @@ obj-$(CONFIG_AXP_GPIO)		+= axp_gpio.o
 endif
 obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
 
-obj-$(CONFIG_DM_PCA953X)	+= pca953x_gpio.o
+obj-$(CONFIG_$(SPL_)DM_PCA953X)	+= pca953x_gpio.o
 obj-$(CONFIG_DM_74X164)		+= 74x164_gpio.o
 
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o

drivers/misc/imx8/scu.c

@@ -191,7 +191,11 @@ static int imx8_scu_probe(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
+#ifdef CONFIG_SPL_BUILD
+	plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
+#else
 	plat->base = (struct mu_type *)addr;
+#endif
 
 	/* U-Boot not enable interrupts, so need to enable RX interrupts */
 	mu_hal_init(plat->base);

drivers/mmc/fsl_esdhc.c

@@ -1625,6 +1625,7 @@ static struct esdhc_soc_data usdhc_imx7d_data = {
 };
 
 static const struct udevice_id fsl_esdhc_ids[] = {
+	{ .compatible = "fsl,imx53-esdhc", },
 	{ .compatible = "fsl,imx6ul-usdhc", },
 	{ .compatible = "fsl,imx6sx-usdhc", },
 	{ .compatible = "fsl,imx6sl-usdhc", },

drivers/mtd/nand/raw/mxs_nand_spl.c

@@ -185,6 +185,7 @@ static int mxs_nand_init(void)
 	mtd = nand_to_mtd(&nand_chip);
 	/* set mtd functions */
 	nand_chip.cmdfunc = mxs_nand_command;
+	nand_chip.scan_bbt = nand_default_bbt;
 	nand_chip.numchips = 1;
 
 	/* identify flash device */

drivers/net/fec_mxc.c

@@ -1264,11 +1264,32 @@ static const struct eth_ops fecmxc_ops = {
 	.read_rom_hwaddr	= fecmxc_read_rom_hwaddr,
 };
 
+static int device_get_phy_addr(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle_args;
+	int reg;
+
+	if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+				       &phandle_args)) {
+		debug("Failed to find phy-handle");
+		return -ENODEV;
+	}
+
+	reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+	return reg;
+}
+
 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 {
 	struct phy_device *phydev;
+	int addr;
 	int mask = 0xffffffff;
 
+	addr = device_get_phy_addr(dev);
+	if (addr >= 0)
+		mask = 1 << addr;
+
 #ifdef CONFIG_FEC_MXC_PHYADDR
 	mask = 1 << CONFIG_FEC_MXC_PHYADDR;
 #endif

drivers/pinctrl/nxp/pinctrl-imx.c

@@ -22,7 +22,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 	const struct fdt_property *prop;
 	u32 *pin_data;
 	int npins, size, pin_size;
-	int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
+	int mux_reg, conf_reg, input_reg;
+	u32 input_val, mux_mode, config_val;
 	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
 	int i, j = 0;
 

drivers/spi/mxc_spi.c

@@ -224,8 +224,8 @@ int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
 	u32 ts;
 	int status;
 
-	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
-		__func__, bitlen, (u32)dout, (u32)din);
+	debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
+		__func__, bitlen, (ulong)dout, (ulong)din);
 
 	mxcs->ctrl_reg = (mxcs->ctrl_reg &
 		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |