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sunxi: H6: Add DDR3 support to DRAM controller driver

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At the moment the H6 DRAM driver only supports LPDDR3 DRAM.

Extend the driver to cover DDR3 DRAM as well.

The changes are partly motivated by looking at the ZynqMP register
documentation, partly by looking at register dumps after boot0/libdram
has initialised the controller.

Many thanks to Jernej for contributing some fixes!

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Andre Przywara
2019-07-15 02:27:07 +01:00
committed by Jagan Teki
parent 770b85a418
commit 75a8a641f3
2 changed files with 62 additions and 28 deletions
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8
arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
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@@ -9,6 +9,8 @@
#ifndef _SUNXI_DRAM_SUN50I_H6_H
#define _SUNXI_DRAM_SUN50I_H6_H
#include <stdbool.h>
enum sunxi_dram_type {
SUNXI_DRAM_TYPE_DDR3 = 3,
SUNXI_DRAM_TYPE_DDR4,
@@ -16,6 +18,11 @@ enum sunxi_dram_type {
SUNXI_DRAM_TYPE_LPDDR3,
};
static inline bool sunxi_dram_is_lpddr(int type)
{
return type >= SUNXI_DRAM_TYPE_LPDDR2;
}
/*
* The following information is mainly retrieved by disassembly and some FPGA
* test code of sun50iw3 platform.
@@ -286,6 +293,7 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
#define DCR_DDR3 (3 << 0)
#define DCR_DDR4 (4 << 0)
#define DCR_DDR8BANK BIT(3)
#define DCR_DDR2T BIT(28)
/*
* The delay parameters allow to allegedly specify delay times of some