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ufs: rockchip: Add initial support
This patch adds initial support for UFS controller on Rockchip platforms. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://patch.msgid.link/1760948182-128561-2-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Shawn Lin
committed by
Neil Armstrong
Neil Armstrong
parent
84919722e6
commit
76465ce21e
@@ -575,6 +575,7 @@ F: drivers/mmc/rockchip_dw_mmc.c
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F: drivers/pinctrl/rockchip/
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F: drivers/ram/rockchip/
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F: drivers/sysreset/sysreset_rockchip.c
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F: drivers/ufs/*rockchip*
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F: drivers/video/rockchip/
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F: tools/rkcommon.c
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F: tools/rkcommon.h
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@@ -33,6 +33,15 @@ config QCOM_UFS
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This selects the platform driver for the UFS host
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controller present on Qualcomm Snapdragon SoCs.
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config ROCKCHIP_UFS
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bool "Rockchip specific hooks to UFS controller platform driver"
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depends on UFS
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help
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This selects the Rockchip specific additions to UFSHCD platform driver.
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Select this if you have UFS controller on Rockchip chipset.
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If unsure, say N.
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config TI_J721E_UFS
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bool "Glue Layer driver for UFS on TI J721E devices"
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help
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@@ -9,4 +9,5 @@ obj-$(CONFIG_QCOM_UFS) += ufs-qcom.o
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obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o
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obj-$(CONFIG_UFS_PCI) += ufs-pci.o
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obj-$(CONFIG_UFS_RENESAS) += ufs-renesas.o
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obj-$(CONFIG_ROCKCHIP_UFS) += ufs-rockchip.o
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obj-$(CONFIG_UFS_AMD_VERSAL2) += ufs-amd-versal2.o ufshcd-dwc.o
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211
drivers/ufs/ufs-rockchip.c
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211
drivers/ufs/ufs-rockchip.c
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@@ -0,0 +1,211 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2025 Rockchip Electronics Co.Ltd.
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <reset.h>
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#include <ufs.h>
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#include "ufs.h"
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#include "unipro.h"
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#include "ufs-rockchip.h"
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static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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if (status != POST_CHANGE)
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return 0;
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ufshcd_dme_reset(hba);
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ufshcd_dme_enable(hba);
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if (hba->ops->phy_initialization) {
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err = hba->ops->phy_initialization(hba);
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if (err)
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dev_err(hba->dev,
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"Phy init failed (%d)\n", err);
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}
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return err;
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}
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static void ufs_rockchip_rk3576_phy_parameter_init(struct ufs_hba *hba)
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{
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struct ufs_rockchip_host *host = dev_get_priv(hba->dev);
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ufs_sys_writel(host->mphy_base, 0x80, CMN_REG23);
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ufs_sys_writel(host->mphy_base, 0xB5, TRSV0_REG14);
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ufs_sys_writel(host->mphy_base, 0xB5, TRSV1_REG14);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG15);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG15);
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ufs_sys_writel(host->mphy_base, 0x38, TRSV0_REG08);
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ufs_sys_writel(host->mphy_base, 0x38, TRSV1_REG08);
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ufs_sys_writel(host->mphy_base, 0x50, TRSV0_REG29);
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ufs_sys_writel(host->mphy_base, 0x50, TRSV1_REG29);
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ufs_sys_writel(host->mphy_base, 0x80, TRSV0_REG2E);
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ufs_sys_writel(host->mphy_base, 0x80, TRSV1_REG2E);
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ufs_sys_writel(host->mphy_base, 0x18, TRSV0_REG3C);
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ufs_sys_writel(host->mphy_base, 0x18, TRSV1_REG3C);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG16);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG16);
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ufs_sys_writel(host->mphy_base, 0x20, TRSV0_REG17);
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ufs_sys_writel(host->mphy_base, 0x20, TRSV1_REG17);
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ufs_sys_writel(host->mphy_base, 0xC0, TRSV0_REG18);
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ufs_sys_writel(host->mphy_base, 0xC0, TRSV1_REG18);
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ufs_sys_writel(host->mphy_base, 0x03, CMN_REG25);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG3D);
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ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG3D);
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ufs_sys_writel(host->mphy_base, 0xC0, CMN_REG23);
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udelay(1);
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ufs_sys_writel(host->mphy_base, 0x00, CMN_REG23);
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udelay(200);
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}
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static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
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{
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
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/* enable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_ENABLE);
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for (int i = 0; i < 2; i++) {
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/* Configuration M-TX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, SEL_TX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, SEL_TX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_VALUE, SEL_TX_LANE0 + i), 0x44);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, SEL_TX_LANE0 + i), 0xe6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, SEL_TX_LANE0 + i), 0x07);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_TASE_VALUE, SEL_TX_LANE0 + i), 0x93);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_BASE_NVALUE, SEL_TX_LANE0 + i), 0xc9);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_POWER_SAVING_CTRL, SEL_TX_LANE0 + i), 0x00);
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/* Configuration M-RX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, SEL_RX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, SEL_RX_LANE0 + i), 0x00);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE, SEL_RX_LANE0 + i), 0x58);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE1, SEL_RX_LANE0 + i), 0x8c);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE2, SEL_RX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_OPTION, SEL_RX_LANE0 + i), 0xf6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_POWER_SAVING_CTRL, SEL_RX_LANE0 + i), 0x69);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_SAVE_DET_CTRL, SEL_RX_LANE0 + i), 0x18);
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}
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/* disable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_DISABLE);
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ufs_rockchip_rk3576_phy_parameter_init(hba);
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/* start link up */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
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return 0;
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}
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static int ufs_rockchip_common_init(struct ufs_hba *hba)
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{
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struct udevice *dev = hba->dev;
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struct ufs_rockchip_host *host = dev_get_priv(dev);
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struct resource res;
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int err;
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/* system control register for hci */
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err = dev_read_resource_byname(dev, "hci_grf", &res);
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if (err) {
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dev_err(dev, "cannot ioremap for hci system control register\n");
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return err;
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}
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host->ufs_sys_ctrl = (void *)(res.start);
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/* system control register for mphy */
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err = dev_read_resource_byname(dev, "mphy_grf", &res);
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if (err) {
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dev_err(dev, "cannot ioremap for mphy system control register\n");
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return err;
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}
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host->ufs_phy_ctrl = (void *)(res.start);
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/* mphy base register */
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err = dev_read_resource_byname(dev, "mphy", &res);
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if (err) {
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dev_err(dev, "cannot ioremap for mphy base register\n");
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return err;
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}
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host->mphy_base = (void *)(res.start);
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host->phy_config_mode = dev_read_u32_default(dev, "ufs-phy-config-mode", 0);
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err = reset_get_bulk(dev, &host->rsts);
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if (err) {
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dev_err(dev, "Can't get reset: %d\n", err);
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return err;
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}
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host->hba = hba;
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return 0;
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}
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static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
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{
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int ret = 0;
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ret = ufs_rockchip_common_init(hba);
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if (ret) {
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dev_err(hba->dev, "%s: ufs common init fail\n", __func__);
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return ret;
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}
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return 0;
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}
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static struct ufs_hba_ops ufs_hba_rk3576_vops = {
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.init = ufs_rockchip_rk3576_init,
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.phy_initialization = ufs_rockchip_rk3576_phy_init,
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.hce_enable_notify = ufs_rockchip_hce_enable_notify,
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};
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static const struct udevice_id ufs_rockchip_of_match[] = {
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{ .compatible = "rockchip,rk3576-ufshc", .data = (ulong)&ufs_hba_rk3576_vops},
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{},
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};
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static int ufs_rockchip_probe(struct udevice *dev)
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{
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struct ufs_hba_ops *ops = (struct ufs_hba_ops *)dev_get_driver_data(dev);
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int err;
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err = ufshcd_probe(dev, ops);
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if (err)
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dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
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return err;
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}
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static int ufs_rockchip_bind(struct udevice *dev)
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{
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struct udevice *scsi_dev;
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return ufs_scsi_bind(dev, &scsi_dev);
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}
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U_BOOT_DRIVER(rockchip_ufs) = {
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.name = "ufshcd-rockchip",
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.id = UCLASS_UFS,
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.of_match = ufs_rockchip_of_match,
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.probe = ufs_rockchip_probe,
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.bind = ufs_rockchip_bind,
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.priv_auto = sizeof(struct ufs_rockchip_host),
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};
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88
drivers/ufs/ufs-rockchip.h
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88
drivers/ufs/ufs-rockchip.h
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@@ -0,0 +1,88 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2025 Rockchip Electronics Co.Ltd.
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*/
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#ifndef _UFS_ROCKCHIP_H_
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#define _UFS_ROCKCHIP_H_
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#define UFS_MAX_CLKS 3
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#define SEL_TX_LANE0 0x0
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#define SEL_TX_LANE1 0x1
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#define SEL_TX_LANE2 0x2
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#define SEL_TX_LANE3 0x3
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#define SEL_RX_LANE0 0x4
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#define SEL_RX_LANE1 0x5
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#define SEL_RX_LANE2 0x6
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#define SEL_RX_LANE3 0x7
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#define VND_TX_CLK_PRD 0xAA
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#define VND_TX_CLK_PRD_EN 0xA9
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#define VND_TX_LINERESET_PVALUE2 0xAB
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#define VND_TX_LINERESET_PVALUE1 0xAC
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#define VND_TX_LINERESET_VALUE 0xAD
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#define VND_TX_BASE_NVALUE 0x93
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#define VND_TX_TASE_VALUE 0x94
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#define VND_TX_POWER_SAVING_CTRL 0x7F
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#define VND_RX_CLK_PRD 0x12
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#define VND_RX_CLK_PRD_EN 0x11
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#define VND_RX_LINERESET_PVALUE2 0x1B
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#define VND_RX_LINERESET_PVALUE1 0x1C
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#define VND_RX_LINERESET_VALUE 0x1D
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#define VND_RX_LINERESET_OPTION 0x25
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#define VND_RX_POWER_SAVING_CTRL 0x2F
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#define VND_RX_SAVE_DET_CTRL 0x1E
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#define CMN_REG23 0x8C
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#define CMN_REG25 0x94
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#define TRSV0_REG08 0xE0
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#define TRSV1_REG08 0x220
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#define TRSV0_REG14 0x110
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#define TRSV1_REG14 0x250
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#define TRSV0_REG15 0x134
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#define TRSV1_REG15 0x274
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#define TRSV0_REG16 0x128
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#define TRSV1_REG16 0x268
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#define TRSV0_REG17 0x12C
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#define TRSV1_REG17 0x26c
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#define TRSV0_REG18 0x120
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#define TRSV1_REG18 0x260
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#define TRSV0_REG29 0x164
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#define TRSV1_REG29 0x2A4
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#define TRSV0_REG2E 0x178
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#define TRSV1_REG2E 0x2B8
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#define TRSV0_REG3C 0x1B0
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#define TRSV1_REG3C 0x2F0
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#define TRSV0_REG3D 0x1B4
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#define TRSV1_REG3D 0x2F4
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#define MPHY_CFG 0x200
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#define MPHY_CFG_ENABLE 0x40
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#define MPHY_CFG_DISABLE 0x0
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#define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022
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#define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023
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struct ufs_rockchip_host {
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struct ufs_hba *hba;
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void __iomem *ufs_phy_ctrl;
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void __iomem *ufs_sys_ctrl;
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void __iomem *mphy_base;
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struct reset_ctl_bulk rsts;
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struct clk ref_out_clk;
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uint64_t caps;
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uint32_t phy_config_mode;
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};
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#define ufs_sys_writel(base, val, reg) \
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writel((val), (base) + (reg))
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#define ufs_sys_readl(base, reg) readl((base) + (reg))
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#define ufs_sys_set_bits(base, mask, reg) \
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ufs_sys_writel((base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg))
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#define ufs_sys_ctrl_clr_bits(base, mask, reg) \
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ufs_sys_writel((base), ((~(mask)) & (ufs_sys_readl((base), (reg)))), (reg))
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#endif /* _UFS_ROCKCHIP_H_ */
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