From a6fbf9455090bdfa4d92e8215e81bdf7bb397757 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Mon, 29 Jan 2018 07:36:37 +0100 Subject: [PATCH 1/3] arm: socfpga: fix qspi flash compatible (add "spi-flash") This patch adds "spi-flash" to the compatible list of the qspi flash chip for all socfpga boards. This is required to make qspi work on these boards on top of the recent fixes. Without the "spi-flash" compatible string for the flash chip, the speed cannot be read and a speed of 0Hz is used (which results in a divide-by-zero on these boards). Signed-off-by: Simon Goldschmidt --- arch/arm/dts/socfpga_arria5_socdk.dts | 2 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 1e91a65af6b..4e4b619f4f9 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -88,7 +88,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 2e2b71fefb6..ea323a16caa 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -87,7 +87,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 95a8e653d7f..3af51134bbe 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -98,7 +98,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index e3ae8a82079..e612eeed4ff 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -68,7 +68,7 @@ flash0: n25q00@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read; From 21a9f435f340b0936aa0bfc29fdd3efa1d329ea2 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 13 Feb 2018 06:34:13 +0100 Subject: [PATCH 2/3] Convert socfpga: select CONFIG_HW_WATCHDOG support for ARCH_SOCFPGA All Socfpga boards from ./include/configs/socfpga_* define CONFIG_HW_WATCHDOG. To ease CONFIG_HW_WATCHDOG conversion to Kconfig select it in config ARCH_SOCFPGA (arch/arm/Kconfig) section. Signed-off-by: Lukasz Majewski Signed-off-by: Simon Goldschmidt --- arch/arm/Kconfig | 1 + include/configs/socfpga_arria10_socdk.h | 2 -- include/configs/socfpga_arria5_socdk.h | 2 -- include/configs/socfpga_cyclone5_socdk.h | 2 -- include/configs/socfpga_de0_nano_soc.h | 2 -- include/configs/socfpga_de10_nano.h | 2 -- include/configs/socfpga_de1_soc.h | 2 -- include/configs/socfpga_is1.h | 2 -- include/configs/socfpga_mcvevk.h | 2 -- include/configs/socfpga_sockit.h | 2 -- include/configs/socfpga_socrates.h | 2 -- include/configs/socfpga_sr1500.h | 2 -- include/configs/socfpga_vining_fpga.h | 2 -- 13 files changed, 1 insertion(+), 24 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7b618d68817..f6e43c6a2aa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -701,6 +701,7 @@ config ARCH_SOCFPGA select DM_SPI_FLASH select DM_SPI select ENABLE_ARM_SOC_BOOT0_HOOK + select HW_WATCHDOG select ARCH_EARLY_INIT_R select ARCH_MISC_INIT select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 83718dd2c9c..82bb48b2777 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -9,8 +9,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Booting Linux */ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 6b6d54b97b1..cd5aac65e92 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 018a0c3bb48..9c5bd648e3d 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 275ed7ffebb..e5db00e3661 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h index bb50fcf1ff0..656af1104dd 100644 --- a/include/configs/socfpga_de10_nano.h +++ b/include/configs/socfpga_de10_nano.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h index 05975c9bde4..f57b9504259 100644 --- a/include/configs/socfpga_de1_soc.h +++ b/include/configs/socfpga_de1_soc.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index 46f5f135dd5..dc318e50dc9 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -9,8 +9,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x10000000 diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 404f064e948..f13463b8b06 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index b4f31c42c50..0bbc7e01054 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index ebb9ac588d7..b66108d0ccd 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 39bf612291f..871f587d458 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 0c76a775256..1197b40b58b 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -8,8 +8,6 @@ #include -#define CONFIG_HW_WATCHDOG - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ From fef4a545b696daf7f27f176aae82fd47b1174aba Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 13 Feb 2018 06:34:14 +0100 Subject: [PATCH 3/3] arm: socfpga: use imply instead of select where applicable Kconfig should only 'select' features that are required for an arch. Standard features that can be disabled without breaking board support should use 'imply' instead, to allow users to disable it. These options are changed for mach-socfpga: - DM_SPI & DM_SPI_FLASH: only required with QSPI support enabled - SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION: the boot rom supports a partitionless mode also, where SPL is located at address 0 - HW_WATCHDOG: while all mainline board defconfigs use it, U-Boot should still work without it. Signed-off-by: Simon Goldschmidt --- arch/arm/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f6e43c6a2aa..77cb20090c4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -698,17 +698,17 @@ config ARCH_SOCFPGA select OF_CONTROL select SPL_OF_CONTROL select DM - select DM_SPI_FLASH - select DM_SPI select ENABLE_ARM_SOC_BOOT0_HOOK - select HW_WATCHDOG select ARCH_EARLY_INIT_R select ARCH_MISC_INIT - select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION select SYS_THUMB_BUILD imply CMD_MTDPARTS imply CRC32_VERIFY + imply DM_SPI + imply DM_SPI_FLASH imply FAT_WRITE + imply HW_WATCHDOG + imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs"