From 158d648d9f02c9ee0f432bbafeea38aaa55dd943 Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Thu, 7 Dec 2023 15:46:02 +0800 Subject: [PATCH 1/3] arm: socfpga: stratix10: SPI clock support This patch is to add SPI clock support for stratix10. Get clock rate function always returning 0 because the DW-SPI driver get the rate from clock node in dts but Stratix10 does not support device tree clock node.To overcome this spi will get the clock_rate directly from spi clock controller override the weaker function. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/clock_manager_s10.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 4b4f0749dbf..45300336d52 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2023 Intel Corporation * */ @@ -399,6 +399,21 @@ unsigned int cm_get_l4_sys_free_clk_hz(void) return cm_get_l3_main_clk_hz() / 4; } +/* + * Override weak dw_spi_get_clk implementation in designware_spi.c driver + */ + +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{ + *rate = cm_get_spi_controller_clk_hz(); + if (!*rate) { + printf("SPI: clock rate is zero"); + return -EINVAL; + } + + return 0; +} + void cm_print_clock_quick_summary(void) { printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000)); From 9d8f814beb7f1857e814a42ec8362323ed88bdcc Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Fri, 15 Dec 2023 15:15:19 +0800 Subject: [PATCH 2/3] clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0) MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation but it is wrongly defined as BIT[7] in u-boot code. This register is used to hold associated pingpong counter in reset while PLL and 5:1 mux configuration is changed. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-mem-n5x.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/altera/clk-mem-n5x.h b/drivers/clk/altera/clk-mem-n5x.h index 7b687012e8f..c6bc44bb34c 100644 --- a/drivers/clk/altera/clk-mem-n5x.h +++ b/drivers/clk/altera/clk-mem-n5x.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* - * Copyright (C) 2020-2022 Intel Corporation + * Copyright (C) 2020-2023 Intel Corporation */ #ifndef _CLK_MEM_N5X_ @@ -77,7 +77,7 @@ #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 -#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) +#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(0) #define MEMCLKMGR_EXTCNTRST_ALLCNTRST \ (MEMCLKMGR_EXTCNTRST_C0CNTRST) From 3c9bb8fbdc77f6bd56e97597d875d8965db3b96c Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Fri, 15 Dec 2023 15:21:51 +0800 Subject: [PATCH 3/3] arm: dts: agilex: Increase reserved memory size to 32MB The reserved space is extended to 32MB in Linux kernel because additional space is needed for authorization execution of JIC/RBF file. U-Boot required to align with Linux. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi index c3ead2d72b9..712304d07a4 100644 --- a/arch/arm/dts/socfpga_agilex.dtsi +++ b/arch/arm/dts/socfpga_agilex.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2019-2023 Intel Corporation */ /dts-v1/; @@ -20,7 +20,7 @@ service_reserved: svcbuffer@0 { compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; + reg = <0x0 0x0 0x0 0x2000000>; alignment = <0x1000>; no-map; };