From 555ceca0886ccf24116bd32f3b5fc550ef592188 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 30 Jun 2019 18:01:53 +0200 Subject: [PATCH 001/147] rockchip: clk: rk3399: handle clk_enable requests for USB3 The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open. Signed-off-by: Mark Kettenis Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index aa6a8ad1c9c..6c73fc93fac 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1078,6 +1078,18 @@ static int rk3399_clk_enable(struct clk *clk) case PCLK_GMAC: /* Required to successfully probe the Designware GMAC driver */ return 0; + + case SCLK_USB3OTG0_REF: + case SCLK_USB3OTG1_REF: + case SCLK_USB3OTG0_SUSPEND: + case SCLK_USB3OTG1_SUSPEND: + case ACLK_USB3OTG0: + case ACLK_USB3OTG1: + case ACLK_USB3_RKSOC_AXI_PERF: + case ACLK_USB3: + case ACLK_USB3_GRF: + /* Required to successfully probe the Designware USB3 driver */ + return 0; } debug("%s: unsupported clk %ld\n", __func__, clk->id); From aaa8d6b1492297821c52bdc5074156a40198f300 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 30 Jun 2019 18:01:54 +0200 Subject: [PATCH 002/147] usb: dwc3-of-simple: Add support for RK3399 Add compatible string for RK3399 and enable it by default on Rockchip platforms with USB3 support. Signed-off-by: Mark Kettenis Reviewed-by: Kever Yang --- drivers/usb/host/Kconfig | 1 + drivers/usb/host/dwc3-of-simple.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b1188bcbf52..ac68aa2d276 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,6 +24,7 @@ config USB_XHCI_DWC3 config USB_XHCI_DWC3_OF_SIMPLE bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" depends on DM_USB + default y if ARCH_ROCKCHIP default y if DRA7XX help Support USB2/3 functionality in simple SoC integrations with diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index b118997f6ee..45df614b094 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -92,6 +92,7 @@ static int dwc3_of_simple_remove(struct udevice *dev) static const struct udevice_id dwc3_of_simple_ids[] = { { .compatible = "amlogic,meson-gxl-dwc3" }, + { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "ti,dwc3" }, { } }; From 062790f461312f1b954ae876f85da8f6ce5fcc73 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 30 Jun 2019 18:01:55 +0200 Subject: [PATCH 003/147] usb: xhci-dwc3: Add USB2 PHY configuration Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs. Signed-off-by: Mark Kettenis Reviewed-by: Kever Yang --- drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 83b9f119e71..9e8cae7ae44 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev) struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); + const char *phy; + u32 reg; int ret; hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev)); @@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev) dwc3_core_init(dwc3_reg); + /* Set dwc3 usb2 phy config */ + reg = readl(&dwc3_reg->g_usb2phycfg[0]); + + phy = dev_read_string(dev, "phy_type"); + if (phy && strcmp(phy, "utmi_wide") == 0) { + reg |= DWC3_GUSB2PHYCFG_PHYIF; + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + } + + if (dev_read_bool(dev, "snps,dis_enblslpm-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + + if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + + writel(reg, &dwc3_reg->g_usb2phycfg[0]); + dr_mode = usb_get_dr_mode(dev_of_offset(dev)); if (dr_mode == USB_DR_MODE_UNKNOWN) /* by default set dual role mode to HOST */ From c908d46f3a493356ef62a2632fa2646098b56545 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sun, 30 Jun 2019 18:01:56 +0200 Subject: [PATCH 004/147] rockchip: xhci: Remove RK3399 support Remove RK3399 compatible strings as this driver is no longer used on that SoC. Signed-off-by: Mark Kettenis Reviewed-by: Kever Yang --- drivers/usb/host/xhci-rockchip.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index f19bea3a91b..e7b0dbcca5d 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -167,7 +167,6 @@ static int xhci_usb_remove(struct udevice *dev) } static const struct udevice_id xhci_usb_ids[] = { - { .compatible = "rockchip,rk3399-xhci" }, { .compatible = "rockchip,rk3328-xhci" }, { } }; @@ -187,7 +186,6 @@ U_BOOT_DRIVER(usb_xhci) = { }; static const struct udevice_id usb_phy_ids[] = { - { .compatible = "rockchip,rk3399-usb3-phy" }, { .compatible = "rockchip,rk3328-usb3-phy" }, { } }; From 9403f80d684e7676c0d2d6391d324ac6c1722ea0 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 1 Jul 2019 17:05:49 +0100 Subject: [PATCH 005/147] arm64: rockchip: rock960: sync dts files from Linux 5.2-rc6 Sync the dts files for the Rock960 boards from Linux to get the latest changes and fixes for the devices. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang Reviewed-by: Manivannan Sadhasivam --- arch/arm/dts/rk3399-ficus.dts | 92 +++++++++++- arch/arm/dts/rk3399-rock960.dts | 91 +++++++++++- arch/arm/dts/rk3399-rock960.dtsi | 233 +++++++++++++++++++++++++------ 3 files changed, 368 insertions(+), 48 deletions(-) diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 4b2dd82b67e..6b059bd7a04 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -23,6 +23,52 @@ clock-output-names = "clkin_gmac"; #clock-cells = <0>; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, + <&user_led4>, <&wlan_led>, <&bt_led>; + + user_led1 { + label = "red:user1"; + gpios = <&gpio4 25 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "red:user2"; + gpios = <&gpio4 26 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "red:user3"; + gpios = <&gpio4 30 0>; + linux,default-trigger = "mmc1"; + }; + + user_led4 { + label = "red:user4"; + gpios = <&gpio1 0 0>; + panic-indicator; + linux,default-trigger = "none"; + }; + + wlan_active_led { + label = "red:wlan"; + gpios = <&gpio1 1 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "red:bt"; + gpios = <&gpio1 4 0>; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; }; &gmac { @@ -49,23 +95,63 @@ gmac { rgmii_sleep_pins: rgmii-sleep-pins { rockchip,pins = - <3 15 RK_FUNC_GPIO &pcfg_output_low>; + <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; }; }; pcie { pcie_drv: pcie-drv { rockchip,pins = - <1 24 RK_FUNC_GPIO &pcfg_pull_none>; + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb2 { host_vbus_drv: host-vbus-drv { rockchip,pins = - <4 27 RK_FUNC_GPIO &pcfg_pull_none>; + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + leds { + user_led1: user_led1 { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2: user_led2 { + rockchip,pins = + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led3: user_led3 { + rockchip,pins = + <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led4: user_led4 { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led: wlan_led { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_led: bt_led { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; }; &vcc3v3_pcie { diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts index 7e06bc97e51..12285c51cce 100644 --- a/arch/arm/dts/rk3399-rock960.dts +++ b/arch/arm/dts/rk3399-rock960.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2018 Manivannan Sadhasivam + * Copyright (c) 2018 Linaro Ltd. */ /dts-v1/; @@ -13,6 +13,53 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, + <&user_led4>, <&wlan_led>, <&bt_led>; + + user_led1 { + label = "green:user1"; + gpios = <&gpio4 RK_PC2 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "green:user2"; + gpios = <&gpio4 RK_PC6 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "green:user3"; + gpios = <&gpio4 RK_PD0 0>; + linux,default-trigger = "mmc1"; + }; + + user_led4 { + label = "green:user4"; + gpios = <&gpio4 RK_PD4 0>; + panic-indicator; + linux,default-trigger = "none"; + }; + + wlan_active_led { + label = "yellow:wlan"; + gpios = <&gpio4 RK_PD5 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "blue:bt"; + gpios = <&gpio4 RK_PD6 0>; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + }; &pcie0 { @@ -20,6 +67,38 @@ }; &pinctrl { + leds { + user_led1: user_led1 { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2: user_led2 { + rockchip,pins = + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led3: user_led3 { + rockchip,pins = + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led4: user_led4 { + rockchip,pins = + <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led: wlan_led { + rockchip,pins = + <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_led: bt_led { + rockchip,pins = + <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_drv: pcie-drv { rockchip,pins = @@ -35,6 +114,14 @@ }; }; +&usbdrd_dwc3_0 { + dr_mode = "otg"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + &vcc3v3_pcie { gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index 51644d6d02d..c7d48d41e18 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -1,13 +1,32 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. * Copyright (c) 2018 Linaro Ltd. */ -#include -#include #include "rk3399.dtsi" +#include "rk3399-opp.dtsi" / { + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + vcc1v8_s0: vcc1v8-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_s0"; @@ -16,12 +35,13 @@ regulator-always-on; }; - vcc_sys: vcc-sys { + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; + regulator-name = "vcc5v0_sys"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; + vin-supply = <&vcc12v_dcin>; }; vcc3v3_sys: vcc3v3-sys { @@ -30,7 +50,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_pcie: vcc3v3-pcie-regulator { @@ -54,20 +74,8 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 0>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - }; &cpu_l0 { @@ -98,7 +106,19 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { status = "okay"; }; @@ -118,7 +138,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; status = "okay"; regulator-state-mem { @@ -136,7 +156,7 @@ regulator-ramp-delay = <1000>; regulator-always-on; regulator-boot-on; - vin-supply = <&vcc_sys>; + vin-supply = <&vcc5v0_sys>; regulator-state-mem { regulator-off-in-suspend; }; @@ -154,16 +174,16 @@ #clock-cells = <1>; clock-output-names = "xin32k", "rk808-clkout2"; - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; vcc12-supply = <&vcc3v3_sys>; vddio-supply = <&vcc_1v8>; @@ -344,6 +364,10 @@ status = "okay"; }; +&i2s2 { + status = "okay"; +}; + &io_domains { bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ @@ -370,45 +394,92 @@ }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus1: sdmmc-bus1 { rockchip,pins = - <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>; + <4 RK_PB0 1 &pcfg_pull_up_8ma>; }; sdmmc_bus4: sdmmc-bus4 { rockchip,pins = - <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>, - <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>, - <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>, - <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>; + <4 RK_PB0 1 &pcfg_pull_up_8ma>, + <4 RK_PB1 1 &pcfg_pull_up_8ma>, + <4 RK_PB2 1 &pcfg_pull_up_8ma>, + <4 RK_PB3 1 &pcfg_pull_up_8ma>; }; sdmmc_clk: sdmmc-clk { rockchip,pins = - <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>; + <4 RK_PB4 1 &pcfg_pull_none_18ma>; }; sdmmc_cmd: sdmmc-cmd { rockchip,pins = - <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + <4 RK_PB5 1 &pcfg_pull_up_8ma>; + }; + }; + + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 RK_PD1 1 &pcfg_pull_none_20ma>; }; }; pmic { pmic_int_l: pmic-int-l { rockchip,pins = - <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; vsel1_gpio: vsel1-gpio { rockchip,pins = - <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; }; vsel2_gpio: vsel2-gpio { rockchip,pins = - <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; @@ -421,6 +492,32 @@ status = "okay"; }; +&sdio0 { + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + &sdhci { bus-width = <8>; mmc-hs400-1_8v; @@ -445,16 +542,42 @@ status = "okay"; }; -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <110000>; status = "okay"; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + &uart2 { status = "okay"; }; +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; @@ -497,10 +620,34 @@ status = "okay"; }; +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + &vopb { status = "okay"; }; +&vopb_mmu { + status = "okay"; +}; + &vopl { status = "okay"; }; + +&vopl_mmu { + status = "okay"; +}; From 6fe736ad0bf91848a5a579be9f82dff3c2ddb930 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 1 Jul 2019 17:05:50 +0100 Subject: [PATCH 006/147] configs: rockchip: rock960: drop options for non-existent HW The Rock960 doesn't contain SPI flash so drop related config options. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang Reviewed-by: Manivannan Sadhasivam --- configs/rock960-rk3399_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 1958b7e190e..1aa986e9cd7 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -21,7 +21,6 @@ CONFIG_SYS_PROMPT="rock960 => " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -35,7 +34,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y From 914bd85b5dba4470bee983c69110defb6e514020 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 1 Jul 2019 17:05:51 +0100 Subject: [PATCH 007/147] configs: rockchip: rock960: enable pmic and regulator commands We have both PMIC and Regulator functionality so it's useful to be able to see output and debug with the commands enabled. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang Reviewed-by: Manivannan Sadhasivam --- configs/rock960-rk3399_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 1aa986e9cd7..2381f0cd7ec 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -21,6 +21,8 @@ CONFIG_SYS_PROMPT="rock960 => " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y From ab8833638071dda0821eb3bbf862e2e3e7597545 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 1 Jul 2019 17:05:52 +0100 Subject: [PATCH 008/147] configs: rockchip: rock960: enable DMA for SDHCI controller Enable the SDMA controller so the eMMC connected to the SDHCI controller (sdhci@fe330000) can make use of it. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang Reviewed-by: Manivannan Sadhasivam --- configs/rock960-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 2381f0cd7ec..20c9cdeda3f 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y From a6a056b9a6ef714b19eb7a29597467deea06bf2b Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 1 Jul 2019 17:05:53 +0100 Subject: [PATCH 009/147] configs: rockchip: rock960: Add support for USB ethernet adapters As the Rock960 doesn't have an onboard wired ethernet interface it's useful to have some common USB wired ethernet devices added to enable testing. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang Reviewed-by: Manivannan Sadhasivam --- configs/rock960-rk3399_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 20c9cdeda3f..90115e903b1 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -48,5 +48,12 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_DM_ETH=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y From 21c0a939ff4256c943afd5e532aad83c2d9fd3f2 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Mon, 1 Jul 2019 17:05:54 +0100 Subject: [PATCH 010/147] configs: rockchip: rock960: enable USB3 support Enable USB3 support via the dwc3 XHCI driver. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang Reviewed-by: Manivannan Sadhasivam --- configs/rock960-rk3399_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 90115e903b1..5be36383e16 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -55,5 +55,8 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +# CONFIG_USB_XHCI_ROCKCHIP is not set CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y From 931729795731743f09ef9e85ed01f8ea99b26dcd Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Thu, 4 Jul 2019 14:52:47 +0800 Subject: [PATCH 011/147] rockchip: dts: rk3399: Add spl-boot-order for Rock PI 4 RK3399 use sdhci for eMMC and DW MMC for SD Card, and spl will only try to boot from SDMMC if we don't specify other boot device for spl-boot-order. So add sdhci and sdmmc for spl-boot-order here. Signed-off-by: Andy Yan Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index 7bddc3acdbb..30f2b5f4793 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -4,3 +4,8 @@ */ #include "rk3399-u-boot.dtsi" +/ { + chosen { + u-boot,spl-boot-order = &sdhci, &sdmmc; + }; +}; From 214c65aa0186d0d76d6b93d99e7adf35860bcc6e Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 16 Jul 2019 16:04:53 +0800 Subject: [PATCH 012/147] rockchip: dts: rk3399: Add 'same-as-spl' for Rock PI 4 Let the board continue boot from the storage device where it bootup. Signed-off-by: Andy Yan Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index 30f2b5f4793..f8d8e33383f 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -6,6 +6,6 @@ #include "rk3399-u-boot.dtsi" / { chosen { - u-boot,spl-boot-order = &sdhci, &sdmmc; + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; }; From f78b2ca4534b304813655cd6eda233cc8d6ab7b6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:33:05 +0800 Subject: [PATCH 013/147] rockchip: rock960-rk3399: fix mail format in MAINTAINER file The mail format should have '<>', or else the patman won't recognize it correctley. Signed-off-by: Kever Yang --- board/vamrs/rock960_rk3399/MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS index 22b2db925ac..5ee52564953 100644 --- a/board/vamrs/rock960_rk3399/MAINTAINERS +++ b/board/vamrs/rock960_rk3399/MAINTAINERS @@ -1,11 +1,11 @@ ROCK960-RK3399 -M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org +M: Manivannan Sadhasivam S: Maintained F: board/rockchip/rock960_rk3399 F: include/configs/rock960_rk3399.h F: configs/rock960-rk3399_defconfig FICUS EE -M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org +M: Manivannan Sadhasivam S: Maintained F: configs/ficus-rk3399_defconfig From 63f4d716b1094f293096b2ef652be2b76c670ac9 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:50:56 +0530 Subject: [PATCH 014/147] ram: rk3399: Fix code warnings Fix checkpatch warninigs on sdram_rk3399.c like - Avoid CamelCase - Unnecessary parentheses - Alignment should match open parenthesis - multiple blank lines - misspelled - spaces preferred around that '>>' Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 48 ++++++++++++++--------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 52518656c4a..541e4a4b1e5 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -47,7 +47,7 @@ struct dram_info { #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) -#define PHY_DRV_ODT_Hi_Z 0x0 +#define PHY_DRV_ODT_HI_Z 0x0 #define PHY_DRV_ODT_240 0x1 #define PHY_DRV_ODT_120 0x8 #define PHY_DRV_ODT_80 0x9 @@ -150,7 +150,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) + if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3) writel(0x2EC7FFFF, &denali_pi[34]); } @@ -166,10 +166,10 @@ static void set_ds_odt(const struct chan_info *chan, u32 reg_value; if (sdram_params->base.dramtype == LPDDR4) { - tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; + tsel_rd_select_p = PHY_DRV_ODT_HI_Z; tsel_wr_select_p = PHY_DRV_ODT_40; ca_tsel_wr_select_p = PHY_DRV_ODT_40; - tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; + tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_n = PHY_DRV_ODT_40; @@ -181,10 +181,10 @@ static void set_ds_odt(const struct chan_info *chan, ca_tsel_wr_select_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; + tsel_rd_select_n = PHY_DRV_ODT_HI_Z; tsel_wr_select_n = PHY_DRV_ODT_34_3; ca_tsel_wr_select_n = PHY_DRV_ODT_48; - tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; + tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_p = PHY_DRV_ODT_34_3; @@ -294,7 +294,7 @@ static void set_ds_odt(const struct chan_info *chan, } static int phy_io_config(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *sdram_params) { u32 *denali_phy = chan->publ->denali_phy; u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; @@ -423,7 +423,6 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); - /* speed setting */ if (sdram_params->base.ddr_freq < 400) speed = 0x0; @@ -492,7 +491,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, setbits_le32(&denali_pi[0], START); setbits_le32(&denali_ctl[0], START); - /* Wating for phy DLL lock */ + /* Waiting for phy DLL lock */ while (1) { tmp = readl(&denali_phy[920]); tmp1 = readl(&denali_phy[921]); @@ -547,12 +546,12 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, /* PHY_DLL_RST_EN */ clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); - /* Wating for PHY and DRAM init complete */ + /* Waiting for PHY and DRAM init complete */ tmp = get_timer(0); do { if (get_timer(tmp) > timeout_ms) { pr_err("DRAM (%s): phy failed to lock within %ld ms\n", - __func__, timeout_ms); + __func__, timeout_ms); return -ETIME; } } while (!(readl(&denali_ctl[203]) & (1 << 3))); @@ -569,7 +568,7 @@ static void select_per_cs_training_index(const struct chan_info *chan, u32 *denali_phy = chan->publ->denali_phy; /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ - if ((readl(&denali_phy[84])>>16) & 1) { + if ((readl(&denali_phy[84]) >> 16) & 1) { /* * PHY_8/136/264/392 * phy_per_cs_training_index_X 1bit offset_24 @@ -646,7 +645,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, if ((((tmp >> 11) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) && (((tmp >> 5) & 0x1) == 0x0) && - (obs_err == 0)) + obs_err == 0) break; else if ((((tmp >> 5) & 0x1) == 0x1) || (obs_err == 1)) @@ -700,7 +699,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, if ((((tmp >> 10) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) && (((tmp >> 4) & 0x1) == 0x0) && - (obs_err == 0)) + obs_err == 0) break; else if ((((tmp >> 4) & 0x1) == 0x1) || (obs_err == 1)) @@ -759,7 +758,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, if ((((tmp >> 9) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) && (((tmp >> 3) & 0x1) == 0x0) && - (obs_err == 0)) + obs_err == 0) break; else if ((((tmp >> 3) & 0x1) == 0x1) || (obs_err == 1)) @@ -955,8 +954,10 @@ static void dram_all_config(struct dram_info *dram, sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); - sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); - sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); + sys_reg |= (info->cs0_row - 13) << + SYS_REG_CS0_ROW_SHIFT(channel); + sys_reg |= (info->cs1_row - 13) << + SYS_REG_CS1_ROW_SHIFT(channel); sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); @@ -991,7 +992,7 @@ static void dram_all_config(struct dram_info *dram, } static int switch_to_phy_index1(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *sdram_params) { u32 channel; u32 *denali_phy; @@ -1026,7 +1027,7 @@ static int switch_to_phy_index1(struct dram_info *dram, denali_phy = dram->chan[channel].publ->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); ret = data_training(&dram->chan[channel], channel, - sdram_params, PI_FULL_TRAINING); + sdram_params, PI_FULL_TRAINING); if (ret) { debug("index1 training failed\n"); return ret; @@ -1116,8 +1117,8 @@ static int conv_of_platdata(struct udevice *dev) int ret; ret = regmap_init_mem_platdata(dev, dtplat->reg, - ARRAY_SIZE(dtplat->reg) / 2, - &plat->map); + ARRAY_SIZE(dtplat->reg) / 2, + &plat->map); if (ret) return ret; @@ -1199,8 +1200,8 @@ static int rk3399_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmugrf->os_reg2); + priv->info.size = + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); #endif return 0; } @@ -1218,7 +1219,6 @@ static struct ram_ops rk3399_dmc_ops = { .get_info = rk3399_dmc_get_info, }; - static const struct udevice_id rk3399_dmc_ids[] = { { .compatible = "rockchip,rk3399-dmc" }, { } From 3eaf5398490f980f9b363cd3bafc7bc82e1d3235 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:50:57 +0530 Subject: [PATCH 015/147] ram: rk3399: Some trivial code fixes - Add proper spaces in data training, rk3399_dmc_init, pctl_cfg - Order include files - Move macro after include files Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 60 +++++++++++++++++++++-------- 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 541e4a4b1e5..733864f5d23 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -14,14 +14,27 @@ #include #include #include -#include -#include #include #include #include +#include +#include #include #include +#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) +#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) +#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) + +#define PHY_DRV_ODT_HI_Z 0x0 +#define PHY_DRV_ODT_240 0x1 +#define PHY_DRV_ODT_120 0x8 +#define PHY_DRV_ODT_80 0x9 +#define PHY_DRV_ODT_60 0xc +#define PHY_DRV_ODT_48 0xd +#define PHY_DRV_ODT_40 0xe +#define PHY_DRV_ODT_34_3 0xf + struct chan_info { struct rk3399_ddr_pctl_regs *pctl; struct rk3399_ddr_pi_regs *pi; @@ -43,19 +56,6 @@ struct dram_info { struct rk3399_pmugrf_regs *pmugrf; }; -#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) -#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) -#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) - -#define PHY_DRV_ODT_HI_Z 0x0 -#define PHY_DRV_ODT_240 0x1 -#define PHY_DRV_ODT_120 0x8 -#define PHY_DRV_ODT_80 0x9 -#define PHY_DRV_ODT_60 0xc -#define PHY_DRV_ODT_48 0xd -#define PHY_DRV_ODT_40 0xe -#define PHY_DRV_ODT_34_3 0xf - #if defined(CONFIG_TPL_BUILD) || \ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) @@ -473,8 +473,10 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], sizeof(struct rk3399_ddr_pctl_regs) - 4); writel(params_ctl[0], &denali_ctl[0]); + copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], sizeof(struct rk3399_ddr_pi_regs)); + /* rank count need to set for init */ set_memory_map(chan, channel, sdram_params); @@ -620,8 +622,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_100 PI_CALVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); + /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ clrsetbits_le32(&denali_pi[92], (0x1 << 16) | (0x3 << 24), @@ -651,9 +655,11 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, (obs_err == 1)) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[100], 0x3 << 8); return 0; @@ -670,8 +676,10 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_60 PI_WRLVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); + /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ clrsetbits_le32(&denali_pi[59], (0x1 << 8) | (0x3 << 16), @@ -705,6 +713,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, (obs_err == 1)) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } @@ -726,8 +735,10 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); + /* * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 * PI_RDLVL_CS:RW:24:2 @@ -764,9 +775,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, (obs_err == 1)) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[80], 0x3 << 24); return 0; @@ -781,8 +794,10 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* PI_80 PI_RDLVL_EN:RW:16:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); + /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ clrsetbits_le32(&denali_pi[74], (0x1 << 8) | (0x3 << 24), @@ -805,9 +820,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, else if (((tmp >> 2) & 0x1) == 0x1) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[80], 0x3 << 16); return 0; @@ -822,13 +839,16 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); + /* * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */ clrbits_le32(&denali_pi[181], 0x1 << 8); + /* PI_124 PI_WDQLVL_EN:RW:16:2 */ clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); + /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ clrsetbits_le32(&denali_pi[121], (0x1 << 8) | (0x3 << 16), @@ -845,9 +865,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, else if (((tmp >> 6) & 0x1) == 0x1) return -EIO; } + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); } + clrbits_le32(&denali_pi[124], 0x3 << 16); return 0; @@ -938,6 +960,7 @@ static void dram_all_config(struct dram_info *dram, sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; sys_reg |= (sdram_params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (channel = 0, idx = 0; (idx < sdram_params->base.num_channels) && (channel < 2); channel++) { @@ -1164,6 +1187,7 @@ static int rk3399_dmc_init(struct udevice *dev) priv->chan[1].publ, priv->chan[1].msch); debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); + #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); #else @@ -1173,14 +1197,16 @@ static int rk3399_dmc_init(struct udevice *dev) printf("%s clk get failed %d\n", __func__, ret); return ret; } + ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); if (ret < 0) { printf("%s clk set failed %d\n", __func__, ret); return ret; } + ret = sdram_init(priv, params); if (ret < 0) { - printf("%s DRAM init failed%d\n", __func__, ret); + printf("%s DRAM init failed %d\n", __func__, ret); return ret; } @@ -1198,7 +1224,7 @@ static int rk3399_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); + debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); priv->info.base = CONFIG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); From fde7f457e137e42f88a712089199bac72bc111ec Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:50:58 +0530 Subject: [PATCH 016/147] ram: rk3399: s/sdram_params/params Rename variable name of struct rk3399_sdram_params from sdram_params with params for more code readability. No functionality change. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 160 ++++++++++++++-------------- 1 file changed, 78 insertions(+), 82 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 733864f5d23..c918c2e588a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -111,10 +111,9 @@ static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, } static void set_memory_map(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { - const struct rk3399_sdram_channel *sdram_ch = - &sdram_params->ch[channel]; + const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel]; u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; u32 cs_map; @@ -150,12 +149,12 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3) + if (sdram_ch->rank == 1 && params->base.dramtype == DDR3) writel(0x2EC7FFFF, &denali_pi[34]); } static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_phy = chan->publ->denali_phy; @@ -165,7 +164,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; u32 reg_value; - if (sdram_params->base.dramtype == LPDDR4) { + if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; tsel_wr_select_p = PHY_DRV_ODT_40; ca_tsel_wr_select_p = PHY_DRV_ODT_40; @@ -175,7 +174,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_n = PHY_DRV_ODT_40; ca_tsel_wr_select_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; - } else if (sdram_params->base.dramtype == LPDDR3) { + } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_p = PHY_DRV_ODT_34_3; ca_tsel_wr_select_p = PHY_DRV_ODT_48; @@ -197,7 +196,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_240; } - if (sdram_params->base.odt == 1) + if (params->base.odt == 1) tsel_rd_en = 1; else tsel_rd_en = 0; @@ -294,7 +293,7 @@ static void set_ds_odt(const struct chan_info *chan, } static int phy_io_config(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_phy = chan->publ->denali_phy; u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; @@ -304,14 +303,14 @@ static int phy_io_config(const struct chan_info *chan, u32 speed; /* vref setting */ - if (sdram_params->base.dramtype == LPDDR4) { + if (params->base.dramtype == LPDDR4) { /* LPDDR4 */ vref_mode_dq = 0x6; vref_value_dq = 0x1f; vref_mode_ac = 0x6; vref_value_ac = 0x1f; - } else if (sdram_params->base.dramtype == LPDDR3) { - if (sdram_params->base.odt == 1) { + } else if (params->base.dramtype == LPDDR3) { + if (params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ drv_value = (readl(&denali_phy[6]) >> 12) & 0xf; odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; @@ -370,7 +369,7 @@ static int phy_io_config(const struct chan_info *chan, } vref_mode_ac = 0x2; vref_value_ac = 0x1f; - } else if (sdram_params->base.dramtype == DDR3) { + } else if (params->base.dramtype == DDR3) { /* DDR3L */ vref_mode_dq = 0x1; vref_value_dq = 0x1f; @@ -397,11 +396,11 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); - if (sdram_params->base.dramtype == LPDDR4) + if (params->base.dramtype == LPDDR4) mode_sel = 0x6; - else if (sdram_params->base.dramtype == LPDDR3) + else if (params->base.dramtype == LPDDR3) mode_sel = 0x0; - else if (sdram_params->base.dramtype == DDR3) + else if (params->base.dramtype == DDR3) mode_sel = 0x1; else return -EINVAL; @@ -424,11 +423,11 @@ static int phy_io_config(const struct chan_info *chan, clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); /* speed setting */ - if (sdram_params->base.ddr_freq < 400) + if (params->base.ddr_freq < 400) speed = 0x0; - else if (sdram_params->base.ddr_freq < 800) + else if (params->base.ddr_freq < 800) speed = 0x1; - else if (sdram_params->base.ddr_freq < 1200) + else if (params->base.ddr_freq < 1200) speed = 0x2; else speed = 0x3; @@ -454,13 +453,13 @@ static int phy_io_config(const struct chan_info *chan, } static int pctl_cfg(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; - const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; - const u32 *params_phy = sdram_params->phy_regs.denali_phy; + const u32 *params_ctl = params->pctl_regs.denali_ctl; + const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; int ret; @@ -474,15 +473,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, sizeof(struct rk3399_ddr_pctl_regs) - 4); writel(params_ctl[0], &denali_ctl[0]); - copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], + copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], sizeof(struct rk3399_ddr_pi_regs)); /* rank count need to set for init */ - set_memory_map(chan, channel, sdram_params); + set_memory_map(chan, channel, params); - writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); - writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); - writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); + writel(params->phy_regs.denali_phy[910], &denali_phy[910]); + writel(params->phy_regs.denali_phy[911], &denali_phy[911]); + writel(params->phy_regs.denali_phy[912], &denali_phy[912]); pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); @@ -513,7 +512,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); - set_ds_odt(chan, sdram_params); + set_ds_odt(chan, params); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 @@ -541,7 +540,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, tmp = (readl(&denali_phy[467]) >> 16) & 0xff; clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); - ret = phy_io_config(chan, sdram_params); + ret = phy_io_config(chan, params); if (ret) return ret; @@ -612,13 +611,13 @@ static void override_write_leveling_value(const struct chan_info *chan) } static int data_training_ca(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -666,13 +665,13 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, } static int data_training_wl(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -725,13 +724,13 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, } static int data_training_rg(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -786,11 +785,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, } static int data_training_rl(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -831,11 +830,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, } static int data_training_wdql(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; + u32 rank = params->ch[channel].rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -876,7 +875,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, } static int data_training(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params, + const struct rk3399_sdram_params *params, u32 training_flag) { u32 *denali_phy = chan->publ->denali_phy; @@ -885,14 +884,14 @@ static int data_training(const struct chan_info *chan, u32 channel, setbits_le32(&denali_phy[927], (1 << 22)); if (training_flag == PI_FULL_TRAINING) { - if (sdram_params->base.dramtype == LPDDR4) { + if (params->base.dramtype == LPDDR4) { training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | PI_READ_GATE_TRAINING | PI_READ_LEVELING | PI_WDQ_LEVELING; - } else if (sdram_params->base.dramtype == LPDDR3) { + } else if (params->base.dramtype == LPDDR3) { training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | PI_READ_GATE_TRAINING; - } else if (sdram_params->base.dramtype == DDR3) { + } else if (params->base.dramtype == DDR3) { training_flag = PI_WRITE_LEVELING | PI_READ_GATE_TRAINING | PI_READ_LEVELING; @@ -901,23 +900,23 @@ static int data_training(const struct chan_info *chan, u32 channel, /* ca training(LPDDR4,LPDDR3 support) */ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) - data_training_ca(chan, channel, sdram_params); + data_training_ca(chan, channel, params); /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) - data_training_wl(chan, channel, sdram_params); + data_training_wl(chan, channel, params); /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) - data_training_rg(chan, channel, sdram_params); + data_training_rg(chan, channel, params); /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) - data_training_rl(chan, channel, sdram_params); + data_training_rl(chan, channel, params); /* wdq leveling(LPDDR4 support) */ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) - data_training_wdql(chan, channel, sdram_params); + data_training_wdql(chan, channel, params); /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ clrbits_le32(&denali_phy[927], (1 << 22)); @@ -926,7 +925,7 @@ static int data_training(const struct chan_info *chan, u32 channel, } static void set_ddrconfig(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params, + const struct rk3399_sdram_params *params, unsigned char channel, u32 ddrconfig) { /* only need to set ddrconfig */ @@ -934,14 +933,14 @@ static void set_ddrconfig(const struct chan_info *chan, unsigned int cs0_cap = 0; unsigned int cs1_cap = 0; - cs0_cap = (1 << (sdram_params->ch[channel].cs0_row - + sdram_params->ch[channel].col - + sdram_params->ch[channel].bk - + sdram_params->ch[channel].bw - 20)); - if (sdram_params->ch[channel].rank > 1) - cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row - - sdram_params->ch[channel].cs1_row); - if (sdram_params->ch[channel].row_3_4) { + cs0_cap = (1 << (params->ch[channel].cs0_row + + params->ch[channel].col + + params->ch[channel].bk + + params->ch[channel].bw - 20)); + if (params->ch[channel].rank > 1) + cs1_cap = cs0_cap >> (params->ch[channel].cs0_row + - params->ch[channel].cs1_row); + if (params->ch[channel].row_3_4) { cs0_cap = cs0_cap * 3 / 4; cs1_cap = cs1_cap * 3 / 4; } @@ -952,24 +951,22 @@ static void set_ddrconfig(const struct chan_info *chan, } static void dram_all_config(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 sys_reg = 0; unsigned int channel, idx; - sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; - sys_reg |= (sdram_params->base.num_channels - 1) - << SYS_REG_NUM_CH_SHIFT; + sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT; for (channel = 0, idx = 0; - (idx < sdram_params->base.num_channels) && (channel < 2); + (idx < params->base.num_channels) && (channel < 2); channel++) { - const struct rk3399_sdram_channel *info = - &sdram_params->ch[channel]; + const struct rk3399_sdram_channel *info = ¶ms->ch[channel]; struct rk3399_msch_regs *ddr_msch_regs; const struct rk3399_msch_timings *noc_timing; - if (sdram_params->ch[channel].col == 0) + if (params->ch[channel].col == 0) continue; idx++; sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); @@ -985,7 +982,7 @@ static void dram_all_config(struct dram_info *dram, sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); ddr_msch_regs = dram->chan[channel].msch; - noc_timing = &sdram_params->ch[channel].noc_timings; + noc_timing = ¶ms->ch[channel].noc_timings; writel(noc_timing->ddrtiminga0, &ddr_msch_regs->ddrtiminga0); writel(noc_timing->ddrtimingb0, @@ -998,14 +995,14 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ - if (sdram_params->ch[channel].rank == 1) + if (params->ch[channel].rank == 1) setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 1 << 17); } writel(sys_reg, &dram->pmugrf->os_reg2); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, - sdram_params->base.stride << 10); + params->base.stride << 10); /* reboot hold register set */ writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | @@ -1015,11 +1012,11 @@ static void dram_all_config(struct dram_info *dram, } static int switch_to_phy_index1(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { u32 channel; u32 *denali_phy; - u32 ch_count = sdram_params->base.num_channels; + u32 ch_count = params->base.num_channels; int ret; int i = 0; @@ -1050,7 +1047,7 @@ static int switch_to_phy_index1(struct dram_info *dram, denali_phy = dram->chan[channel].publ->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); ret = data_training(&dram->chan[channel], channel, - sdram_params, PI_FULL_TRAINING); + params, PI_FULL_TRAINING); if (ret) { debug("index1 training failed\n"); return ret; @@ -1061,10 +1058,10 @@ static int switch_to_phy_index1(struct dram_info *dram, } static int sdram_init(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *params) { - unsigned char dramtype = sdram_params->base.dramtype; - unsigned int ddr_freq = sdram_params->base.ddr_freq; + unsigned char dramtype = params->base.dramtype; + unsigned int ddr_freq = params->base.ddr_freq; int channel; debug("Starting SDRAM initialization...\n"); @@ -1082,10 +1079,10 @@ static int sdram_init(struct dram_info *dram, phy_dll_bypass_set(publ, ddr_freq); - if (channel >= sdram_params->base.num_channels) + if (channel >= params->base.num_channels) continue; - if (pctl_cfg(chan, channel, sdram_params) != 0) { + if (pctl_cfg(chan, channel, params) != 0) { printf("pctl_cfg fail, reset\n"); return -EIO; } @@ -1094,17 +1091,16 @@ static int sdram_init(struct dram_info *dram, if (dramtype == LPDDR3) udelay(10); - if (data_training(chan, channel, - sdram_params, PI_FULL_TRAINING)) { + if (data_training(chan, channel, params, PI_FULL_TRAINING)) { printf("SDRAM initialization failed, reset\n"); return -EIO; } - set_ddrconfig(chan, sdram_params, channel, - sdram_params->ch[channel].ddrconfig); + set_ddrconfig(chan, params, channel, + params->ch[channel].ddrconfig); } - dram_all_config(dram, sdram_params); - switch_to_phy_index1(dram, sdram_params); + dram_all_config(dram, params); + switch_to_phy_index1(dram, params); debug("Finish SDRAM initialization...\n"); return 0; From d4b4bb47c631093fe39177f889164730737c368e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:50:59 +0530 Subject: [PATCH 017/147] ram: rk3399: Handle pctl_cfg return type Add proper return type handling of pctl_cfg with meaningful print statement. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index c918c2e588a..de5d8c1b5fd 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1063,6 +1063,7 @@ static int sdram_init(struct dram_info *dram, unsigned char dramtype = params->base.dramtype; unsigned int ddr_freq = params->base.ddr_freq; int channel; + int ret; debug("Starting SDRAM initialization...\n"); @@ -1082,9 +1083,10 @@ static int sdram_init(struct dram_info *dram, if (channel >= params->base.num_channels) continue; - if (pctl_cfg(chan, channel, params) != 0) { - printf("pctl_cfg fail, reset\n"); - return -EIO; + ret = pctl_cfg(chan, channel, params); + if (ret < 0) { + printf("%s: pctl config failed\n", __func__); + return ret; } /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ From fa2b015b9cf9c4961d9b4cf59022cb25656fe4a4 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:00 +0530 Subject: [PATCH 018/147] ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n Rename tsel_wr_select_n to tsel_wr_select_dq_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index de5d8c1b5fd..85ff47f1338 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -161,7 +161,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; - u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; + u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { @@ -171,7 +171,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_n = PHY_DRV_ODT_40; + tsel_wr_select_dq_n = PHY_DRV_ODT_40; ca_tsel_wr_select_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { @@ -181,7 +181,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; - tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; ca_tsel_wr_select_n = PHY_DRV_ODT_48; tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { @@ -191,7 +191,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; tsel_idle_select_n = PHY_DRV_ODT_240; } @@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan, * for write cycles for DQ/DM */ reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | - (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | + (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); @@ -250,7 +250,7 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_n | (tsel_wr_select_p << 4)); + tsel_wr_select_dq_n | (tsel_wr_select_p << 4)); clrsetbits_le32(&denali_phy[925], 0xff, tsel_rd_select_n | (tsel_rd_select_p << 4)); From a5085ee4e8039367d22145eefdb7d043d1718125 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:01 +0530 Subject: [PATCH 019/147] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 85ff47f1338..3ec32bdbc00 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -159,14 +159,14 @@ static void set_ds_odt(const struct chan_info *chan, u32 *denali_phy = chan->publ->denali_phy; u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; - u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; + u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_wr_select_p = PHY_DRV_ODT_40; + tsel_wr_select_dq_p = PHY_DRV_ODT_40; ca_tsel_wr_select_p = PHY_DRV_ODT_40; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; @@ -176,7 +176,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; ca_tsel_wr_select_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; @@ -186,7 +186,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; tsel_idle_select_p = PHY_DRV_ODT_240; @@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan, * for write cycles for DQ/DM */ reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | - (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) | + (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); @@ -250,7 +250,7 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_dq_n | (tsel_wr_select_p << 4)); + tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4)); clrsetbits_le32(&denali_phy[925], 0xff, tsel_rd_select_n | (tsel_rd_select_p << 4)); From a12a5be7a3a0f6ac315e10536f0e35a2cb3c333b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:02 +0530 Subject: [PATCH 020/147] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 3ec32bdbc00..bdb46a01282 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -160,7 +160,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; + u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; @@ -172,7 +172,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_40; - ca_tsel_wr_select_n = PHY_DRV_ODT_40; + tsel_wr_select_ca_n = PHY_DRV_ODT_40; tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -182,7 +182,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_HI_Z; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_48; + tsel_wr_select_ca_n = PHY_DRV_ODT_48; tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -192,7 +192,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_rd_select_n = PHY_DRV_ODT_240; tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; tsel_idle_select_n = PHY_DRV_ODT_240; } @@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); + reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value); From 30bd86a399a0d6af2307ee2eb035ac93ff571b93 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:03 +0530 Subject: [PATCH 021/147] ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index bdb46a01282..8a983f9bb18 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n; + u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; tsel_wr_select_dq_p = PHY_DRV_ODT_40; - ca_tsel_wr_select_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_p = PHY_DRV_ODT_40; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan, } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_48; + tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan, } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_idle_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -228,7 +228,7 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = tsel_wr_select_ca_n | (ca_tsel_wr_select_p << 0x4); + reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); clrsetbits_le32(&denali_phy[544], 0xff, reg_value); clrsetbits_le32(&denali_phy[672], 0xff, reg_value); clrsetbits_le32(&denali_phy[800], 0xff, reg_value); From 9c4d517db8d15e56fe2316c0763bdc8009cac872 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:04 +0530 Subject: [PATCH 022/147] ram: rk3399: Order tsel variables Order tsel* variable declarations and assignment in proper and meaningful way. No functionality change. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 8a983f9bb18..043b27737d5 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -159,41 +159,48 @@ static void set_ds_odt(const struct chan_info *chan, u32 *denali_phy = chan->publ->denali_phy; u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; - u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; - u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n; - u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; + u32 tsel_idle_select_p, tsel_rd_select_p; + u32 tsel_idle_select_n, tsel_rd_select_n; + u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; + u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; u32 reg_value; if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_wr_select_dq_p = PHY_DRV_ODT_40; - tsel_wr_select_ca_p = PHY_DRV_ODT_40; - tsel_idle_select_p = PHY_DRV_ODT_HI_Z; - tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_dq_n = PHY_DRV_ODT_40; - tsel_wr_select_ca_n = PHY_DRV_ODT_40; + + tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_idle_select_n = PHY_DRV_ODT_240; + + tsel_wr_select_dq_p = PHY_DRV_ODT_40; + tsel_wr_select_dq_n = PHY_DRV_ODT_40; + + tsel_wr_select_ca_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_n = PHY_DRV_ODT_40; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - tsel_wr_select_ca_p = PHY_DRV_ODT_48; - tsel_idle_select_p = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_HI_Z; - tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - tsel_wr_select_ca_n = PHY_DRV_ODT_48; + + tsel_idle_select_p = PHY_DRV_ODT_240; tsel_idle_select_n = PHY_DRV_ODT_HI_Z; + + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_48; + tsel_wr_select_ca_n = PHY_DRV_ODT_48; } else { tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; - tsel_idle_select_p = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_idle_select_p = PHY_DRV_ODT_240; tsel_idle_select_n = PHY_DRV_ODT_240; + + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; } if (params->base.odt == 1) From 355490dc5c03f42033efd55940d3a6192b70656d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:05 +0530 Subject: [PATCH 023/147] ram: rockchip: rk3399: Add cap_info structure Group common ddr attributes like - rank - col - bk - bw - dbw - row_3_4 - cs0_row - cs1_row - ddrconfig into a common cap_info structure for more code readability and extend if possible based on the new features. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_rk3399.h | 6 +- drivers/ram/rockchip/sdram_rk3399.c | 73 ++++++++++--------- 2 files changed, 45 insertions(+), 34 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index c6a260bad89..683093d4ca9 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -71,7 +71,7 @@ struct rk3399_ddr_cic_regs { /* DENALI_CTL_274 */ #define MEM_RST_VALID 1 -struct rk3399_sdram_channel { +struct sdram_cap_info { unsigned int rank; /* dram column number, 0 means this channel is invalid */ unsigned int col; @@ -89,6 +89,10 @@ struct rk3399_sdram_channel { unsigned int cs0_row; unsigned int cs1_row; unsigned int ddrconfig; +}; + +struct rk3399_sdram_channel { + struct sdram_cap_info cap_info; struct rk3399_msch_timings noc_timings; }; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 043b27737d5..492b0975dd9 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -121,35 +121,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, u32 row; /* Get row number from ddrconfig setting */ - if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) + if (sdram_ch->cap_info.ddrconfig < 2 || + sdram_ch->cap_info.ddrconfig == 4) row = 16; - else if (sdram_ch->ddrconfig == 3) + else if (sdram_ch->cap_info.ddrconfig == 3) row = 14; else row = 15; - cs_map = (sdram_ch->rank > 1) ? 3 : 1; - reduc = (sdram_ch->bw == 2) ? 0 : 1; + cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; + reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; /* Set the dram configuration to ctrl */ - clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); + clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | + ((3 - sdram_ch->cap_info.bk) << 16) | ((16 - row) << 24)); clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), cs_map | (reduc << 16)); /* PI_199 PI_COL_DIFF:RW:0:4 */ - clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); + clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | + ((3 - sdram_ch->cap_info.bk) << 16) | ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if (sdram_ch->rank == 1 && params->base.dramtype == DDR3) + if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3) writel(0x2EC7FFFF, &denali_pi[34]); } @@ -624,7 +625,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_err = 0; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -678,7 +679,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -737,7 +738,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, u32 *denali_phy = chan->publ->denali_phy; u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -796,7 +797,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -841,7 +842,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, { u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; - u32 rank = params->ch[channel].rank; + u32 rank = params->ch[channel].cap_info.rank; for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -940,14 +941,14 @@ static void set_ddrconfig(const struct chan_info *chan, unsigned int cs0_cap = 0; unsigned int cs1_cap = 0; - cs0_cap = (1 << (params->ch[channel].cs0_row - + params->ch[channel].col - + params->ch[channel].bk - + params->ch[channel].bw - 20)); - if (params->ch[channel].rank > 1) - cs1_cap = cs0_cap >> (params->ch[channel].cs0_row - - params->ch[channel].cs1_row); - if (params->ch[channel].row_3_4) { + cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row + + params->ch[channel].cap_info.col + + params->ch[channel].cap_info.bk + + params->ch[channel].cap_info.bw - 20)); + if (params->ch[channel].cap_info.rank > 1) + cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row + - params->ch[channel].cap_info.cs1_row); + if (params->ch[channel].cap_info.row_3_4) { cs0_cap = cs0_cap * 3 / 4; cs1_cap = cs1_cap * 3 / 4; } @@ -973,20 +974,26 @@ static void dram_all_config(struct dram_info *dram, struct rk3399_msch_regs *ddr_msch_regs; const struct rk3399_msch_timings *noc_timing; - if (params->ch[channel].col == 0) + if (params->ch[channel].cap_info.col == 0) continue; idx++; - sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); + sys_reg |= info->cap_info.row_3_4 << + SYS_REG_ROW_3_4_SHIFT(channel); sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel); - sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); - sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); - sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); - sys_reg |= (info->cs0_row - 13) << + sys_reg |= (info->cap_info.rank - 1) << + SYS_REG_RANK_SHIFT(channel); + sys_reg |= (info->cap_info.col - 9) << + SYS_REG_COL_SHIFT(channel); + sys_reg |= info->cap_info.bk == 3 ? 0 : 1 << + SYS_REG_BK_SHIFT(channel); + sys_reg |= (info->cap_info.cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); - sys_reg |= (info->cs1_row - 13) << + sys_reg |= (info->cap_info.cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); - sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); - sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); + sys_reg |= (2 >> info->cap_info.bw) << + SYS_REG_BW_SHIFT(channel); + sys_reg |= (2 >> info->cap_info.dbw) << + SYS_REG_DBW_SHIFT(channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; @@ -1002,7 +1009,7 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ - if (params->ch[channel].rank == 1) + if (params->ch[channel].cap_info.rank == 1) setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 1 << 17); } @@ -1106,7 +1113,7 @@ static int sdram_init(struct dram_info *dram, } set_ddrconfig(chan, params, channel, - params->ch[channel].ddrconfig); + params->ch[channel].cap_info.ddrconfig); } dram_all_config(dram, params); switch_to_phy_index1(dram, params); From 1372a6ec47d79dfc3718150e3074b7e154793dce Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:06 +0530 Subject: [PATCH 024/147] ram: rk3399: s/rk3399_base_params/sdram_base_params Most of the ddr parameters are common in rk3399_base_params structure and which would reuse it in another controller like px30 in future. So, rename the structure from rk3399_base_params into sdram_base_params. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 683093d4ca9..5614b94ecba 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -96,7 +96,7 @@ struct rk3399_sdram_channel { struct rk3399_msch_timings noc_timings; }; -struct rk3399_base_params { +struct sdram_base_params { unsigned int ddr_freq; unsigned int dramtype; unsigned int num_channels; @@ -106,7 +106,7 @@ struct rk3399_base_params { struct rk3399_sdram_params { struct rk3399_sdram_channel ch[2]; - struct rk3399_base_params base; + struct sdram_base_params base; struct rk3399_ddr_pctl_regs pctl_regs; struct rk3399_ddr_pi_regs pi_regs; struct rk3399_ddr_publ_regs phy_regs; From e5e444aaa58402a27a173556fb4056d53f7a5501 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:07 +0530 Subject: [PATCH 025/147] ram: rk3399: Move common sdram structures in common header Move common sdram structures like sdram_cap_info, sdram_base_params into sdram_common header, this would help to reuse the same from another controllers like px30. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_common.h | 29 +++++++++++++++++++ .../include/asm/arch-rockchip/sdram_rk3399.h | 28 ------------------ 2 files changed, 29 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 671c318d50c..82ce3d3fc9c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -5,6 +5,35 @@ #ifndef _ASM_ARCH_SDRAM_COMMON_H #define _ASM_ARCH_SDRAM_COMMON_H + +struct sdram_cap_info { + unsigned int rank; + /* dram column number, 0 means this channel is invalid */ + unsigned int col; + /* dram bank number, 3:8bank, 2:4bank */ + unsigned int bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned int dbw; + /* + * row_3_4 = 1: 6Gb or 12Gb die + * row_3_4 = 0: normal die, power of 2 + */ + unsigned int row_3_4; + unsigned int cs0_row; + unsigned int cs1_row; + unsigned int ddrconfig; +}; + +struct sdram_base_params { + unsigned int ddr_freq; + unsigned int dramtype; + unsigned int num_channels; + unsigned int stride; + unsigned int odt; +}; + /* * sys_reg bitfield struct * [31] row_3_4_ch1 diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 5614b94ecba..65c92cf7443 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -71,39 +71,11 @@ struct rk3399_ddr_cic_regs { /* DENALI_CTL_274 */ #define MEM_RST_VALID 1 -struct sdram_cap_info { - unsigned int rank; - /* dram column number, 0 means this channel is invalid */ - unsigned int col; - /* dram bank number, 3:8bank, 2:4bank */ - unsigned int bk; - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int bw; - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ - unsigned int dbw; - /* - * row_3_4 = 1: 6Gb or 12Gb die - * row_3_4 = 0: normal die, power of 2 - */ - unsigned int row_3_4; - unsigned int cs0_row; - unsigned int cs1_row; - unsigned int ddrconfig; -}; - struct rk3399_sdram_channel { struct sdram_cap_info cap_info; struct rk3399_msch_timings noc_timings; }; -struct sdram_base_params { - unsigned int ddr_freq; - unsigned int dramtype; - unsigned int num_channels; - unsigned int stride; - unsigned int odt; -}; - struct rk3399_sdram_params { struct rk3399_sdram_channel ch[2]; struct sdram_base_params base; From fafd2ad4df4d1362c2eb26716b4d625c5ca32694 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:08 +0530 Subject: [PATCH 026/147] arm: include: rockchip: Move dramtypes to common header dramtype enum numbers as common across all dram controllers in rockchip, so move the eneum values in common header. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram.h | 6 ------ arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++++ arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 7 ------- arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 8 -------- 4 files changed, 8 insertions(+), 21 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index bbe425deb9f..9220763fa7f 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -8,12 +8,6 @@ #ifndef _ASM_ARCH_RK3288_SDRAM_H__ #define _ASM_ARCH_RK3288_SDRAM_H__ -enum { - DDR3 = 3, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - struct rk3288_sdram_channel { /* * bit width in address, eg: diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 82ce3d3fc9c..55abcdae774 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -6,6 +6,14 @@ #ifndef _ASM_ARCH_SDRAM_COMMON_H #define _ASM_ARCH_SDRAM_COMMON_H +enum { + DDR3 = 0x3, + LPDDR2 = 0x5, + LPDDR3 = 0x6, + LPDDR4 = 0x7, + UNUSED = 0xFF +}; + struct sdram_cap_info { unsigned int rank; /* dram column number, 0 means this channel is invalid */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h index d0091a7aaff..336c5d7e8c4 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h @@ -7,13 +7,6 @@ #include -enum { - DDR3 = 3, - LPDDR2 = 5, - LPDDR3 = 6, - UNUSED = 0xFF, -}; - struct rk322x_sdram_channel { /* * bit width in address, eg: diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 65c92cf7443..471702f9352 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -6,14 +6,6 @@ #ifndef _ASM_ARCH_SDRAM_RK3399_H #define _ASM_ARCH_SDRAM_RK3399_H -enum { - DDR3 = 0x3, - LPDDR2 = 0x5, - LPDDR3 = 0x6, - LPDDR4 = 0x7, - UNUSED = 0xFF -}; - struct rk3399_ddr_pctl_regs { u32 denali_ctl[332]; }; From 7757d1102f292a177937267badae7f146045d9c3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:09 +0530 Subject: [PATCH 027/147] arm: include: rockchip: Add DDR4 enum Add DDR4 enum number in common header. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 55abcdae774..7ac25af327c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -7,6 +7,7 @@ #define _ASM_ARCH_SDRAM_COMMON_H enum { + DDR4 = 0, DDR3 = 0x3, LPDDR2 = 0x5, LPDDR3 = 0x6, From dd7dfa217e799007f11f4649396d86ad8a40f95b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:51:10 +0530 Subject: [PATCH 028/147] clk: rockchip: rk3399: Fix check patch warnings and checks - CHECK: spaces preferred around that '*' - CHECK: spaces preferred around that '/' - CHECK: space preferred before that '|' - WARNING: macros should not use a trailing semicolon - CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv' - CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC' - CHECK: Unnecessary parentheses around 'parent->dev == clk->dev' - WARNING: line over 80 characters - CHECK: Prefer kernel type 'u8' over 'uint8_t' - Add proper macro definitions arrangements Note: there are still line over 80 characters and other warnings but fixing those making code look unreadable, so I kept it as it is. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 68 ++++++++++++++----------------- 1 file changed, 31 insertions(+), 37 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 6c73fc93fac..69a887f70cf 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -38,8 +38,8 @@ struct pll_div { }; #define RATE_TO_DIV(input_rate, output_rate) \ - ((input_rate) / (output_rate) - 1); -#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + ((input_rate) / (output_rate) - 1) +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ .refdiv = _refdiv,\ @@ -53,15 +53,15 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); #endif -static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1); +static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1); static const struct pll_div *apll_l_cfgs[] = { [APLL_L_1600_MHZ] = &apll_l_1600_cfg, [APLL_L_600_MHZ] = &apll_l_600_cfg, }; -static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1); static const struct pll_div *apll_b_cfgs[] = { [APLL_B_600_MHZ] = &apll_b_600_cfg, }; @@ -393,7 +393,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) fref_khz = ref_khz / refdiv; fbdiv = vco_khz / fref_khz; - if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) + if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv) continue; diff_khz = vco_khz - fbdiv * fref_khz; if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { @@ -409,7 +409,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) div->fbdiv = fbdiv; } - if (best_diff_khz > 4 * (MHz/KHz)) { + if (best_diff_khz > 4 * (MHz / KHz)) { printf("%s: Failed to match output frequency %u, " "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, best_diff_khz * KHz); @@ -489,28 +489,21 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru, } #define I2C_CLK_REG_MASK(bus) \ - (I2C_DIV_CON_MASK << \ - CLK_I2C ##bus## _DIV_CON_SHIFT | \ - CLK_I2C_PLL_SEL_MASK << \ - CLK_I2C ##bus## _PLL_SEL_SHIFT) + (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \ + CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT) #define I2C_CLK_REG_VALUE(bus, clk_div) \ - ((clk_div - 1) << \ - CLK_I2C ##bus## _DIV_CON_SHIFT | \ - CLK_I2C_PLL_SEL_GPLL << \ - CLK_I2C ##bus## _PLL_SEL_SHIFT) + ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \ + CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT) #define I2C_CLK_DIV_VALUE(con, bus) \ - (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ - I2C_DIV_CON_MASK; + ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK) #define I2C_PMUCLK_REG_MASK(bus) \ - (I2C_DIV_CON_MASK << \ - CLK_I2C ##bus## _DIV_CON_SHIFT) + (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT) #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ - ((clk_div - 1) << \ - CLK_I2C ##bus## _DIV_CON_SHIFT) + ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT) static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) { @@ -597,9 +590,9 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) */ struct spi_clkreg { - uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ - uint8_t div_shift; - uint8_t sel_shift; + u8 reg; /* CLKSEL_CON[reg] register in CRU */ + u8 div_shift; + u8 sel_shift; }; /* @@ -678,7 +671,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) { struct pll_div vpll_config = {0}; - int aclk_vop = 198*MHz; + int aclk_vop = 198 * MHz; void *aclkreg_addr, *dclkreg_addr; u32 div; @@ -710,7 +703,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) rkclk_set_pll(&cru->vpll_con[0], &vpll_config); rk_clrsetreg(dclkreg_addr, - DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| + DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK | DCLK_VOP_DIV_CON_MASK, DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | @@ -750,7 +743,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, ulong clk_id, ulong set_rate) { int src_clk_div; - int aclk_emmc = 198*MHz; + int aclk_emmc = 198 * MHz; switch (clk_id) { case HCLK_SDMMC: @@ -776,7 +769,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, break; case SCLK_EMMC: /* Select aclk_emmc source from GPLL */ - src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); + src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc); assert(src_clk_div - 1 < 32); rk_clrsetreg(&cru->clksel_con[21], @@ -834,23 +827,23 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ switch (set_rate) { - case 200*MHz: + case 200 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; break; - case 300*MHz: + case 300 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; break; - case 666*MHz: + case 666 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; break; - case 800*MHz: + case 800 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; break; - case 933*MHz: + case 933 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; break; @@ -916,7 +909,6 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART2: case SCLK_UART3: return 24000000; - break; case PCLK_HDMI_CTRL: break; case DCLK_VOP0: @@ -1014,7 +1006,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) return ret; } -static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) +static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, + struct clk *parent) { struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); const char *clock_output_name; @@ -1024,7 +1017,7 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa * If the requested parent is in the same clock-controller and * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. */ - if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { + if (parent->dev == clk->dev && parent->id == SCLK_MAC) { debug("%s: switching RGMII to SCLK_MAC\n", __func__); rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); return 0; @@ -1049,7 +1042,8 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa return -EINVAL; } -static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) +static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, + struct clk *parent) { switch (clk->id) { case SCLK_RMII_SRC: From 02fad6f9eda4165db33710c7c65353babf1d4455 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:39 +0530 Subject: [PATCH 029/147] ram: rk3399: Handle data training return types data trainings calls like ca, wl, rg, rl, wdql have proper return types with -EIO and the return type missed to handle in data_training function. This patch, add proper return type checks along with useful debug statement on each data training calls. Incidentally this would help to prevent the sdram initialization hang for single channel dram and when the code is trying to initialize second channel with proper return type of relevant data training call might failed. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 50 ++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 492b0975dd9..e9c0fdf2d46 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -887,6 +887,7 @@ static int data_training(const struct chan_info *chan, u32 channel, u32 training_flag) { u32 *denali_phy = chan->publ->denali_phy; + int ret; /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ setbits_le32(&denali_phy[927], (1 << 22)); @@ -907,24 +908,49 @@ static int data_training(const struct chan_info *chan, u32 channel, } /* ca training(LPDDR4,LPDDR3 support) */ - if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) - data_training_ca(chan, channel, params); + if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { + ret = data_training_ca(chan, channel, params); + if (ret < 0) { + debug("%s: data training ca failed\n", __func__); + return ret; + } + } /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ - if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) - data_training_wl(chan, channel, params); + if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { + ret = data_training_wl(chan, channel, params); + if (ret < 0) { + debug("%s: data training wl failed\n", __func__); + return ret; + } + } /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ - if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) - data_training_rg(chan, channel, params); + if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { + ret = data_training_rg(chan, channel, params); + if (ret < 0) { + debug("%s: data training rg failed\n", __func__); + return ret; + } + } /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ - if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) - data_training_rl(chan, channel, params); + if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { + ret = data_training_rl(chan, channel, params); + if (ret < 0) { + debug("%s: data training rl failed\n", __func__); + return ret; + } + } /* wdq leveling(LPDDR4 support) */ - if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) - data_training_wdql(chan, channel, params); + if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { + ret = data_training_wdql(chan, channel, params); + if (ret < 0) { + debug("%s: data training wdql failed\n", __func__); + return ret; + } + } /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ clrbits_le32(&denali_phy[927], (1 << 22)); @@ -1062,7 +1088,7 @@ static int switch_to_phy_index1(struct dram_info *dram, clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); ret = data_training(&dram->chan[channel], channel, params, PI_FULL_TRAINING); - if (ret) { + if (ret < 0) { debug("index1 training failed\n"); return ret; } @@ -1108,7 +1134,7 @@ static int sdram_init(struct dram_info *dram, udelay(10); if (data_training(chan, channel, params, PI_FULL_TRAINING)) { - printf("SDRAM initialization failed, reset\n"); + printf("%s: data training failed\n", __func__); return -EIO; } From 01976ae6f55ecfdf9ace9a453cc16d84585d49d8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:40 +0530 Subject: [PATCH 030/147] ram: rk3399: Clear PI_175 interrupts in data training Clear the PI_175 interrupts before processing actual data training in all relevant calls. This would help to clear interrupt from previous training. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index e9c0fdf2d46..fe26144f27d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -627,6 +627,9 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, u32 obs_0, obs_1, obs_2, obs_err = 0; u32 rank = params->ch[channel].cap_info.rank; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -681,6 +684,9 @@ static int data_training_wl(const struct chan_info *chan, u32 channel, u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; u32 rank = params->ch[channel].cap_info.rank; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -740,6 +746,9 @@ static int data_training_rg(const struct chan_info *chan, u32 channel, u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; u32 rank = params->ch[channel].cap_info.rank; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -799,6 +808,9 @@ static int data_training_rl(const struct chan_info *chan, u32 channel, u32 i, tmp; u32 rank = params->ch[channel].cap_info.rank; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); @@ -844,6 +856,9 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, u32 i, tmp; u32 rank = params->ch[channel].cap_info.rank; + /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ + writel(0x00003f7c, (&denali_pi[175])); + for (i = 0; i < rank; i++) { select_per_cs_training_index(chan, i); From 708e9a79dc297aeb8a62dc6ba95b651b0493e1e1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:41 +0530 Subject: [PATCH 031/147] ram: rk3399: Use rank mask in ca data training Add rank_mask based on the rank number, this would keep the ca data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index fe26144f27d..b98df20fa53 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -626,11 +626,17 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_err = 0; u32 rank = params->ch[channel].cap_info.rank; + u32 rank_mask; /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); - for (i = 0; i < rank; i++) { + rank_mask = (rank == 1) ? 0x1 : 0x3; + + for (i = 0; i < 4; i++) { + if (!(rank_mask & (1 << i))) + continue; + select_per_cs_training_index(chan, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ From 21cf392b1f3444c9d758f028de0e3630631ba75b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:42 +0530 Subject: [PATCH 032/147] ram: rk3399: Use rank mask in wdql data training Add rank_mask based on the rank number, this would keep the wdql data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index b98df20fa53..16bd9427a65 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -861,11 +861,17 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, u32 *denali_pi = chan->pi->denali_pi; u32 i, tmp; u32 rank = params->ch[channel].cap_info.rank; + u32 rank_mask; /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); - for (i = 0; i < rank; i++) { + rank_mask = (rank == 1) ? 0x1 : 0x3; + + for (i = 0; i < 4; i++) { + if (!(rank_mask & (1 << i))) + continue; + select_per_cs_training_index(chan, i); /* From 33921035be0fc69de2440e739964f54093f1d2ab Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:43 +0530 Subject: [PATCH 033/147] ram: rk3399: Add phy pctrl reset support Add support for phy pctrl reset support for both channel 0, 1. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 16bd9427a65..a5da985e1a6 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -35,6 +35,10 @@ #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf +#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ + ((n) << (8 + (ch) * 4))) +#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ + ((n) << (9 + (ch) * 4))) struct chan_info { struct rk3399_ddr_pctl_regs *pctl; struct rk3399_ddr_pi_regs *pi; @@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } } +static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, + u32 phy) +{ + channel &= 0x1; + ctl &= 0x1; + phy &= 0x1; + writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | + CRU_SFTRST_DDR_PHY(channel, phy), + &cru->softrst_con[4]); +} + +static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +{ + rkclk_ddr_reset(cru, channel, 1, 1); + udelay(10); + + rkclk_ddr_reset(cru, channel, 1, 0); + udelay(10); + + rkclk_ddr_reset(cru, channel, 0, 0); + udelay(10); +} + static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq) { @@ -1129,6 +1156,7 @@ static int sdram_init(struct dram_info *dram, { unsigned char dramtype = params->base.dramtype; unsigned int ddr_freq = params->base.ddr_freq; + struct rk3399_cru *cru = dram->cru; int channel; int ret; @@ -1145,6 +1173,7 @@ static int sdram_init(struct dram_info *dram, const struct chan_info *chan = &dram->chan[channel]; struct rk3399_ddr_publ_regs *publ = chan->publ; + phy_pctrl_reset(cru, channel); phy_dll_bypass_set(publ, ddr_freq); if (channel >= params->base.num_channels) From fe42d4a19907d58b67983b0a5a287071fb2c3ed0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:44 +0530 Subject: [PATCH 034/147] ram: rk3399: Move pwrup_srefresh_exit to dram_info Add pwrup_srefresh_exit to be part of dram_info so-that the it can help to support pwrup_srefresh_exit in individual channels while starting pctl in future. No functionality change. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index a5da985e1a6..6e944cafd9c 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -49,6 +49,7 @@ struct chan_info { struct dram_info { #if defined(CONFIG_TPL_BUILD) || \ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) + u32 pwrup_srefresh_exit; struct chan_info chan[2]; struct clk ddr_clk; struct rk3399_cru *cru; @@ -487,8 +488,8 @@ static int phy_io_config(const struct chan_info *chan, return 0; } -static int pctl_cfg(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *params) +static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, + u32 channel, const struct rk3399_sdram_params *params) { u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; @@ -496,7 +497,6 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, const u32 *params_ctl = params->pctl_regs.denali_ctl; const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; - u32 pwrup_srefresh_exit; int ret; const ulong timeout_ms = 200; @@ -518,7 +518,8 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, writel(params->phy_regs.denali_phy[911], &denali_phy[911]); writel(params->phy_regs.denali_phy[912], &denali_phy[912]); - pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; + dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) & + PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); /* PHY_DLL_RST_EN */ @@ -594,7 +595,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit); + dram->pwrup_srefresh_exit); return 0; } @@ -1179,7 +1180,7 @@ static int sdram_init(struct dram_info *dram, if (channel >= params->base.num_channels) continue; - ret = pctl_cfg(chan, channel, params); + ret = pctl_cfg(dram, chan, channel, params); if (ret < 0) { printf("%s: pctl config failed\n", __func__); return ret; From a0aebe8398415b03c8f3e31a886e4dcbf74b9a6e Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:45 +0530 Subject: [PATCH 035/147] ram: rk3399: Add pctl start support Add support for pctl start for both channel 0, 1 control and phy registers. This would also handle pwrup_srefresh_exit init based on the channel number. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 75 +++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 20 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 6e944cafd9c..084c9497289 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -49,10 +49,11 @@ struct chan_info { struct dram_info { #if defined(CONFIG_TPL_BUILD) || \ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) - u32 pwrup_srefresh_exit; + u32 pwrup_srefresh_exit[2]; struct chan_info chan[2]; struct clk ddr_clk; struct rk3399_cru *cru; + struct rk3399_grf_regs *grf; struct rk3399_pmucru *pmucru; struct rk3399_pmusgrf_regs *pmusgrf; struct rk3399_ddr_cic_regs *cic; @@ -73,6 +74,11 @@ struct rockchip_dmc_plat { struct regmap *map; }; +static void *get_ddrc0_con(struct dram_info *dram, u8 channel) +{ + return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1; +} + static void copy_to_reg(u32 *dest, const u32 *src, u32 n) { int i; @@ -328,6 +334,48 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); } +static void pctl_start(struct dram_info *dram, u8 channel) +{ + const struct chan_info *chan = &dram->chan[channel]; + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_phy = chan->publ->denali_phy; + u32 *ddrc0_con = get_ddrc0_con(dram, channel); + u32 count = 0; + u32 byte, tmp; + + writel(0x01000000, &ddrc0_con); + + clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); + + while (!(readl(&denali_ctl[203]) & (1 << 3))) { + if (count > 1000) { + printf("%s: Failed to init pctl for channel %d\n", + __func__, channel); + while (1) + ; + } + + udelay(1); + count++; + } + + writel(0x01000100, &ddrc0_con); + + for (byte = 0; byte < 4; byte++) { + tmp = 0x820; + writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]); + + clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp); + } + + clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, + dram->pwrup_srefresh_exit[channel]); +} + static int phy_io_config(const struct chan_info *chan, const struct rk3399_sdram_params *params) { @@ -498,7 +546,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; int ret; - const ulong timeout_ms = 200; /* * work around controller bug: @@ -518,8 +565,8 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, writel(params->phy_regs.denali_phy[911], &denali_phy[911]); writel(params->phy_regs.denali_phy[912], &denali_phy[912]); - dram->pwrup_srefresh_exit = readl(&denali_ctl[68]) & - PWRUP_SREFRESH_EXIT; + dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & + PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); /* PHY_DLL_RST_EN */ @@ -580,22 +627,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, if (ret) return ret; - /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); - - /* Waiting for PHY and DRAM init complete */ - tmp = get_timer(0); - do { - if (get_timer(tmp) > timeout_ms) { - pr_err("DRAM (%s): phy failed to lock within %ld ms\n", - __func__, timeout_ms); - return -ETIME; - } - } while (!(readl(&denali_ctl[203]) & (1 << 3))); - debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); - - clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - dram->pwrup_srefresh_exit); return 0; } @@ -1186,6 +1217,9 @@ static int sdram_init(struct dram_info *dram, return ret; } + /* start to trigger initialization */ + pctl_start(dram, channel); + /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ if (dramtype == LPDDR3) udelay(10); @@ -1262,6 +1296,7 @@ static int rk3399_dmc_init(struct udevice *dev) #endif priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); priv->pmucru = rockchip_get_pmucru(); From 82ee138def96acc19d72c5b77eb126c625b06ba0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:46 +0530 Subject: [PATCH 036/147] ram: rockchip: Add initial Kconfig Right now sdram drivers in rockchip SoC are built based on the SoC configs which may not be an adequate solutions while adding common or debug driver. So, add meaningful Kconfig options start with rk3399. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/Kconfig | 1 + drivers/ram/rockchip/Kconfig | 17 +++++++++++++++++ drivers/ram/rockchip/Makefile | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 drivers/ram/rockchip/Kconfig diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index fbf7d7b20fb..568d8f2c6a9 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -54,4 +54,5 @@ config K3_AM654_DDRSS config add support for the initialization of the external SDRAM devices connected to DDR subsystem. +source "drivers/ram/rockchip/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig new file mode 100644 index 00000000000..995cb487b89 --- /dev/null +++ b/drivers/ram/rockchip/Kconfig @@ -0,0 +1,17 @@ +config RAM_ROCKCHIP + bool "Ram drivers support for Rockchip SoCs" + depends on RAM && ARCH_ROCKCHIP + default y + help + This enables support for ram drivers Rockchip SoCs. + +if RAM_ROCKCHIP + +config RAM_RK3399 + bool "Ram driver for Rockchip RK3399" + default ROCKCHIP_RK3399 + help + This enables ram drivers support for the platforms based on + Rockchip RK3399 SoC. + +endif # RAM_ROCKCHIP diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 5df196066da..07d4b62a9d1 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -9,4 +9,4 @@ obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o -obj-$(CONFIG_ROCKCHIP_RK3399) = sdram_rk3399.o +obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o From 3940ab6523336c6d37dfe6b05a0dbd6ea1785445 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:47 +0530 Subject: [PATCH 037/147] debug_uart: Add printdec Add printdec, this would help to print an output a decimalism value. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- include/debug_uart.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/debug_uart.h b/include/debug_uart.h index 34e8b2fc810..cd70ae1a044 100644 --- a/include/debug_uart.h +++ b/include/debug_uart.h @@ -104,6 +104,13 @@ void printhex4(uint value); */ void printhex8(uint value); +/** + * printdec() - Output a decimalism value + * + * @value: Value to output + */ +void printdec(uint value); + #ifdef CONFIG_DEBUG_UART_ANNOUNCE #define _DEBUG_UART_ANNOUNCE printascii(" "); #else @@ -170,6 +177,18 @@ void printhex8(uint value); { \ printhex(value, 8); \ } \ +\ + void printdec(uint value) \ + { \ + if (value > 10) { \ + printdec(value / 10); \ + value %= 10; \ + } else if (value == 10) { \ + _debug_uart_putc('1'); \ + value = 0; \ + } \ + _debug_uart_putc('0' + value); \ + } \ \ void debug_uart_init(void) \ { \ From 07112672a57adcbdc8272283f631c1648245c1f8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:48 +0530 Subject: [PATCH 038/147] ram: rockchip: Add debug sdram driver Add sdram driver to handle debug across rockchip SoCs. This would help to improve code debugging feature for sdram drivers in rockchip family, whoever wants to debug the driver should call these core debug code on their respective platform sdram drivers. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_common.h | 9 +++++ drivers/ram/rockchip/Kconfig | 9 +++++ drivers/ram/rockchip/Makefile | 1 + drivers/ram/rockchip/sdram_debug.c | 34 +++++++++++++++++++ 4 files changed, 53 insertions(+) create mode 100644 drivers/ram/rockchip/sdram_debug.c diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 7ac25af327c..171b233f952 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -92,4 +92,13 @@ size_t rockchip_sdram_size(phys_addr_t reg); /* Called by U-Boot board_init_r for Rockchip SoCs */ int dram_init(void); + +#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG) +inline void sdram_print_dram_type(unsigned char dramtype) +{ +} +#else +void sdram_print_dram_type(unsigned char dramtype); +#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ + #endif diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index 995cb487b89..151ffb684d9 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -7,6 +7,15 @@ config RAM_ROCKCHIP if RAM_ROCKCHIP +config RAM_ROCKCHIP_DEBUG + bool "Rockchip ram drivers debugging" + help + This enables debugging ram driver API's for the platforms + based on Rockchip SoCs. + + This is an option for developers to understand the ram drivers + initialization, configurations and etc. + config RAM_RK3399 bool "Ram driver for Rockchip RK3399" default ROCKCHIP_RK3399 diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 07d4b62a9d1..feb1f82d007 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -3,6 +3,7 @@ # Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH # +obj-$(CONFIG_RAM_ROCKCHIP_DEBUG) += sdram_debug.o obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c new file mode 100644 index 00000000000..c13e140fa5a --- /dev/null +++ b/drivers/ram/rockchip/sdram_debug.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2019 Amarula Solutions. + * Author: Jagan Teki + */ + +#include +#include +#include + +void sdram_print_dram_type(unsigned char dramtype) +{ + switch (dramtype) { + case DDR3: + printascii("DDR3"); + break; + case DDR4: + printascii("DDR4"); + break; + case LPDDR2: + printascii("LPDDR2"); + break; + case LPDDR3: + printascii("LPDDR3"); + break; + case LPDDR4: + printascii("LPDDR4"); + break; + default: + printascii("Unknown Device"); + break; + } +} From 07894f5aacb5a4b04a762251c83e5745173849e3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:49 +0530 Subject: [PATCH 039/147] ram: rockchip: debug: Add sdram_print_ddr_info Add sdram ddr info print support, this would help to observe the sdram base parameters. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_common.h | 7 ++++ drivers/ram/rockchip/sdram_debug.c | 40 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 171b233f952..cfbb5118439 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -97,8 +97,15 @@ int dram_init(void); inline void sdram_print_dram_type(unsigned char dramtype) { } + +inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base) +{ +} #else void sdram_print_dram_type(unsigned char dramtype); +void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base); #endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ #endif diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c index c13e140fa5a..69a6f94a738 100644 --- a/drivers/ram/rockchip/sdram_debug.c +++ b/drivers/ram/rockchip/sdram_debug.c @@ -32,3 +32,43 @@ void sdram_print_dram_type(unsigned char dramtype) break; } } + +void sdram_print_ddr_info(struct sdram_cap_info *cap_info, + struct sdram_base_params *base) +{ + u32 bg; + + bg = (cap_info->dbw == 0) ? 2 : 1; + + sdram_print_dram_type(base->dramtype); + + printascii(", "); + printdec(base->ddr_freq); + printascii("MHz\n"); + + printascii("BW="); + printdec(8 << cap_info->bw); + + printascii(" Col="); + printdec(cap_info->col); + + printascii(" Bk="); + printdec(0x1 << cap_info->bk); + if (base->dramtype == DDR4) { + printascii(" BG="); + printdec(1 << bg); + } + + printascii(" CS0 Row="); + printdec(cap_info->cs0_row); + if (cap_info->rank > 1) { + printascii(" CS1 Row="); + printdec(cap_info->cs1_row); + } + + printascii(" CS="); + printdec(cap_info->rank); + + printascii(" Die BW="); + printdec(8 << cap_info->dbw); +} From 79674a62789c7fcda3dd285c618080bc0bf85189 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:50 +0530 Subject: [PATCH 040/147] ram: rockchip: debug: Get the cs capacity Add code to get the channel capacity, this would help to print the capacity of specific channel. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_debug.c | 46 +++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c index 69a6f94a738..19e9225c127 100644 --- a/drivers/ram/rockchip/sdram_debug.c +++ b/drivers/ram/rockchip/sdram_debug.c @@ -33,10 +33,46 @@ void sdram_print_dram_type(unsigned char dramtype) } } +/** + * cs = 0, cs0 + * cs = 1, cs1 + * cs => 2, cs0+cs1 + * note: it didn't consider about row_3_4 + */ +u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type) +{ + u32 bg; + u64 cap[2]; + + if (dram_type == DDR4) + /* DDR4 8bit dram BG = 2(4bank groups), + * 16bit dram BG = 1 (2 bank groups) + */ + bg = (cap_info->dbw == 0) ? 2 : 1; + else + bg = 0; + + cap[0] = 1llu << (cap_info->bw + cap_info->col + + bg + cap_info->bk + cap_info->cs0_row); + + if (cap_info->rank == 2) + cap[1] = 1llu << (cap_info->bw + cap_info->col + + bg + cap_info->bk + cap_info->cs1_row); + else + cap[1] = 0; + + if (cs == 0) + return cap[0]; + else if (cs == 1) + return cap[1]; + else + return (cap[0] + cap[1]); +} + void sdram_print_ddr_info(struct sdram_cap_info *cap_info, struct sdram_base_params *base) { - u32 bg; + u32 bg, cap; bg = (cap_info->dbw == 0) ? 2 : 1; @@ -71,4 +107,12 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info, printascii(" Die BW="); printdec(8 << cap_info->dbw); + + cap = sdram_get_cs_cap(cap_info, 3, base->dramtype); + if (cap_info->row_3_4) + cap = cap * 3 / 4; + + printascii(" Size="); + printdec(cap >> 20); + printascii("MB\n"); } From cb13534abe07afae88bdeadf24e42717a9657750 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:51 +0530 Subject: [PATCH 041/147] ram: rk3399: debug: Add sdram_print_stride Add code to print the channel stride, this would help to print the stride of associated channel. Here is sample print on LPDDR4, 50MHz. 256B stride Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_common.h | 5 ++++ drivers/ram/rockchip/sdram_debug.c | 29 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index cfbb5118439..b7549f5d8a2 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -102,10 +102,15 @@ inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info, struct sdram_base_params *base) { } + +inline void sdram_print_stride(unsigned int stride) +{ +} #else void sdram_print_dram_type(unsigned char dramtype); void sdram_print_ddr_info(struct sdram_cap_info *cap_info, struct sdram_base_params *base); +void sdram_print_stride(unsigned int stride); #endif /* CONFIG_RAM_ROCKCHIP_DEBUG */ #endif diff --git a/drivers/ram/rockchip/sdram_debug.c b/drivers/ram/rockchip/sdram_debug.c index 19e9225c127..9cf662675b2 100644 --- a/drivers/ram/rockchip/sdram_debug.c +++ b/drivers/ram/rockchip/sdram_debug.c @@ -116,3 +116,32 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info, printdec(cap >> 20); printascii("MB\n"); } + +void sdram_print_stride(unsigned int stride) +{ + switch (stride) { + case 0xc: + printf("128B stride\n"); + break; + case 5: + case 9: + case 0xd: + case 0x11: + case 0x19: + printf("256B stride\n"); + break; + case 0xa: + case 0xe: + case 0x12: + printf("512B stride\n"); + break; + case 0xf: + printf("4K stride\n"); + break; + case 0x1f: + printf("32MB + 256B stride\n"); + break; + default: + printf("no stride\n"); + } +} From 4b09719c38cea3d10095675046eb6e8e84955e85 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:52 +0530 Subject: [PATCH 042/147] ram: rk3399: Compute stride for 2 channels stride value from sdram timings can be computed dynamically based on the determined capacity for the given channel. Right now these stride values are taken as part of sdram timings via dtsi, but it possible to use same timings dtsi for given frequency even though the configured board sdram do support single channel with different size by dynamically detect the stride value. Example, NanoPi NEO4 do have DDR3-1866, but with single channel and 1GB size with dynamic stride detection it is possible to use existing rk3399-sdram-ddr3-1866.dtsi whose stride, number of channels and capacity it support is d efferent. So, add initial support to calculate the stride value for 2 channels sdram, which is available by default on existing boards. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 71 ++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 084c9497289..c626ef602cc 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1183,8 +1183,75 @@ static int switch_to_phy_index1(struct dram_info *dram, return 0; } +static unsigned char calculate_stride(struct rk3399_sdram_params *params) +{ + unsigned int stride = params->base.stride; + unsigned int channel, chinfo = 0; + unsigned int ch_cap[2] = {0, 0}; + u64 cap; + + for (channel = 0; channel < 2; channel++) { + unsigned int cs0_cap = 0; + unsigned int cs1_cap = 0; + struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info; + + if (cap_info->col == 0) + continue; + + cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + + cap_info->bk + cap_info->bw - 20)); + if (cap_info->rank > 1) + cs1_cap = cs0_cap >> (cap_info->cs0_row + - cap_info->cs1_row); + if (cap_info->row_3_4) { + cs0_cap = cs0_cap * 3 / 4; + cs1_cap = cs1_cap * 3 / 4; + } + ch_cap[channel] = cs0_cap + cs1_cap; + chinfo |= 1 << channel; + } + + /* stride calculation for 2 channels, default gstride type is 256B */ + if (ch_cap[0] == ch_cap[1]) { + cap = ch_cap[0] + ch_cap[1]; + switch (cap) { + /* 512MB */ + case 512: + stride = 0; + break; + /* 1GB */ + case 1024: + stride = 0x5; + break; + /* + * 768MB + 768MB same as total 2GB memory + * useful space: 0-768MB 1GB-1792MB + */ + case 1536: + /* 2GB */ + case 2048: + stride = 0x9; + break; + /* 1536MB + 1536MB */ + case 3072: + stride = 0x11; + break; + /* 4GB */ + case 4096: + stride = 0xD; + break; + default: + printf("%s: Unable to calculate stride for ", __func__); + print_size((cap * (1 << 20)), " capacity\n"); + break; + } + } + + return stride; +} + static int sdram_init(struct dram_info *dram, - const struct rk3399_sdram_params *params) + struct rk3399_sdram_params *params) { unsigned char dramtype = params->base.dramtype; unsigned int ddr_freq = params->base.ddr_freq; @@ -1232,6 +1299,8 @@ static int sdram_init(struct dram_info *dram, set_ddrconfig(chan, params, channel, params->ch[channel].cap_info.ddrconfig); } + + params->base.stride = calculate_stride(params); dram_all_config(dram, params); switch_to_phy_index1(dram, params); From 1ff5283d92b25e449358bd88bc0b18db4be61d4f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:53 +0530 Subject: [PATCH 043/147] ram: rk3399: Compute stride for 1 channel a Add stride computation for the sdram which support single channel a This configuration available in NanoPi NEO4 and the same can work with existing rk3399-sdram-ddr3-1866.dtsi Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index c626ef602cc..8bbacb52754 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1211,6 +1211,10 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *params) chinfo |= 1 << channel; } + /* stride calculation for 1 channel */ + if (params->base.num_channels == 1 && chinfo & 1) + return 0x17; /* channel a */ + /* stride calculation for 2 channels, default gstride type is 256B */ if (ch_cap[0] == ch_cap[1]) { cap = ch_cap[0] + ch_cap[1]; From d0ba88f5dd675af7d2bb93d33ef08f96af2ced51 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:54 +0530 Subject: [PATCH 044/147] ram: rk3399: Add rank detection support Right now the rk3399 sdram driver assume that the board has configured with 2 channels, so any possibility to enable single channel on the same driver will encounter channel #1 data training failure. Log: U-Boot TPL board init sdram_init: data training failed rk3399_dmc_init DRAM init failed -5 So, add an algorithm that can capable to compute the active or configured rank with associated channel like a) do rank loop to compute the active rank, with associated channel numbers b) then, succeed the data training only for configured channel c) preserve the rank for given channel d) do channel loop for setting the active channel e) if given rank is zero or inactive on the specific channel, clear the timings for the associated channel f) finally, return error if number of channels is zero Tested in NanoPI-NEO4 since it support single channel sdram configuration. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang (add PI_READ_GATE_TRAINING for LPDDR3 to support rk3399-evb case) Signed-off-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 122 +++++++++++++++++++++++----- 1 file changed, 100 insertions(+), 22 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 8bbacb52754..9df2f840ab2 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1254,13 +1254,52 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *params) return stride; } +static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel) +{ + params->ch[channel].cap_info.rank = 0; + params->ch[channel].cap_info.col = 0; + params->ch[channel].cap_info.bk = 0; + params->ch[channel].cap_info.bw = 32; + params->ch[channel].cap_info.dbw = 32; + params->ch[channel].cap_info.row_3_4 = 0; + params->ch[channel].cap_info.cs0_row = 0; + params->ch[channel].cap_info.cs1_row = 0; + params->ch[channel].cap_info.ddrconfig = 0; +} + +static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params) +{ + int channel; + int ret; + + for (channel = 0; channel < 2; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct rk3399_cru *cru = dram->cru; + struct rk3399_ddr_publ_regs *publ = chan->publ; + + phy_pctrl_reset(cru, channel); + phy_dll_bypass_set(publ, params->base.ddr_freq); + + ret = pctl_cfg(dram, chan, channel, params); + if (ret < 0) { + printf("%s: pctl config failed\n", __func__); + return ret; + } + + /* start to trigger initialization */ + pctl_start(dram, channel); + } + + return 0; +} + static int sdram_init(struct dram_info *dram, struct rk3399_sdram_params *params) { unsigned char dramtype = params->base.dramtype; unsigned int ddr_freq = params->base.ddr_freq; - struct rk3399_cru *cru = dram->cru; - int channel; + u32 training_flag = PI_READ_GATE_TRAINING; + int channel, ch, rank; int ret; debug("Starting SDRAM initialization...\n"); @@ -1272,36 +1311,75 @@ static int sdram_init(struct dram_info *dram, return -E2BIG; } + for (ch = 0; ch < 2; ch++) { + params->ch[ch].cap_info.rank = 2; + for (rank = 2; rank != 0; rank--) { + ret = pctl_init(dram, params); + if (ret < 0) { + printf("%s: pctl init failed\n", __func__); + return ret; + } + + /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ + if (dramtype == LPDDR3) + udelay(10); + + params->ch[ch].cap_info.rank = rank; + + /* + * LPDDR3 CA training msut be trigger before + * other training. + * DDR3 is not have CA training. + */ + if (params->base.dramtype == LPDDR3) + training_flag |= PI_CA_TRAINING; + + if (!(data_training(&dram->chan[ch], ch, + params, training_flag))) + break; + } + /* Computed rank with associated channel number */ + params->ch[ch].cap_info.rank = rank; + } + + params->base.num_channels = 0; for (channel = 0; channel < 2; channel++) { const struct chan_info *chan = &dram->chan[channel]; - struct rk3399_ddr_publ_regs *publ = chan->publ; + struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info; + u8 training_flag = PI_FULL_TRAINING; - phy_pctrl_reset(cru, channel); - phy_dll_bypass_set(publ, ddr_freq); - - if (channel >= params->base.num_channels) + if (cap_info->rank == 0) { + clear_channel_params(params, channel); continue; - - ret = pctl_cfg(dram, chan, channel, params); - if (ret < 0) { - printf("%s: pctl config failed\n", __func__); - return ret; + } else { + params->base.num_channels++; } - /* start to trigger initialization */ - pctl_start(dram, channel); + debug("Channel "); + debug(channel ? "1: " : "0: "); - /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ - if (dramtype == LPDDR3) - udelay(10); + /* LPDDR3 should have write and read gate training */ + if (params->base.dramtype == LPDDR3) + training_flag = PI_WRITE_LEVELING | + PI_READ_GATE_TRAINING; - if (data_training(chan, channel, params, PI_FULL_TRAINING)) { - printf("%s: data training failed\n", __func__); - return -EIO; + if (params->base.dramtype != LPDDR4) { + ret = data_training(dram, channel, params, + training_flag); + if (!ret) { + debug("%s: data train failed for channel %d\n", + __func__, ret); + continue; + } } - set_ddrconfig(chan, params, channel, - params->ch[channel].cap_info.ddrconfig); + set_ddrconfig(chan, params, channel, cap_info->ddrconfig); + } + + if (params->base.num_channels == 0) { + printf("%s: ", __func__); + printf(" - %dMHz failed!\n", params->base.ddr_freq); + return -EINVAL; } params->base.stride = calculate_stride(params); From a9191b8eeccaf99f77290f8389a22bf253a06409 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:55 +0530 Subject: [PATCH 045/147] ram: rk3399: Enable sdram debug functions This would help to debug the sdram base parameters while debugging existing chip or while supporting new sdram type. It require explicit enablement of CONFIG_RAM_ROCKCHIP_DEBUG for showing the debug prints. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 9df2f840ab2..c59c985c19a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1251,6 +1251,8 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *params) } } + sdram_print_stride(stride); + return stride; } @@ -1373,11 +1375,14 @@ static int sdram_init(struct dram_info *dram, } } + sdram_print_ddr_info(cap_info, ¶ms->base); + set_ddrconfig(chan, params, channel, cap_info->ddrconfig); } if (params->base.num_channels == 0) { printf("%s: ", __func__); + sdram_print_dram_type(params->base.dramtype); printf(" - %dMHz failed!\n", params->base.ddr_freq); return -EINVAL; } From 879f9fed6a695a75f558c874813c974d1c1d3658 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:26:49 +0530 Subject: [PATCH 046/147] ram: rk3399: Simply existing dram enc macro Add simplified and meaningful macro for all setting. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang (Squash the similar patches into 1 patch) Signed-off-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_common.h | 16 ++++++++++ drivers/ram/rockchip/sdram_rk3399.c | 30 +++++++------------ 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index b7549f5d8a2..47492332266 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -71,21 +71,37 @@ struct sdram_base_params { #define SYS_REG_NUM_CH_MASK 1 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) #define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch)) +#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT) +#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \ + SYS_REG_NUM_CH_SHIFT) #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) #define SYS_REG_RANK_MASK 1 +#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \ + SYS_REG_RANK_SHIFT(ch)) #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) #define SYS_REG_COL_MASK 3 +#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch)) #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) #define SYS_REG_BK_MASK 1 +#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ + SYS_REG_BK_SHIFT(ch)) #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) #define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \ + SYS_REG_CS0_ROW_SHIFT(ch)) #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \ + SYS_REG_CS1_ROW_SHIFT(ch)) #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) #define SYS_REG_BW_MASK 3 +#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch)) #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) #define SYS_REG_DBW_MASK 3 +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index c59c985c19a..9bd163fa484 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1076,8 +1076,8 @@ static void dram_all_config(struct dram_info *dram, u32 sys_reg = 0; unsigned int channel, idx; - sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; - sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); + sys_reg |= SYS_REG_ENC_NUM_CH(params->base.num_channels); for (channel = 0, idx = 0; (idx < params->base.num_channels) && (channel < 2); @@ -1089,23 +1089,15 @@ static void dram_all_config(struct dram_info *dram, if (params->ch[channel].cap_info.col == 0) continue; idx++; - sys_reg |= info->cap_info.row_3_4 << - SYS_REG_ROW_3_4_SHIFT(channel); - sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel); - sys_reg |= (info->cap_info.rank - 1) << - SYS_REG_RANK_SHIFT(channel); - sys_reg |= (info->cap_info.col - 9) << - SYS_REG_COL_SHIFT(channel); - sys_reg |= info->cap_info.bk == 3 ? 0 : 1 << - SYS_REG_BK_SHIFT(channel); - sys_reg |= (info->cap_info.cs0_row - 13) << - SYS_REG_CS0_ROW_SHIFT(channel); - sys_reg |= (info->cap_info.cs1_row - 13) << - SYS_REG_CS1_ROW_SHIFT(channel); - sys_reg |= (2 >> info->cap_info.bw) << - SYS_REG_BW_SHIFT(channel); - sys_reg |= (2 >> info->cap_info.dbw) << - SYS_REG_DBW_SHIFT(channel); + sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); + sys_reg |= SYS_REG_ENC_CHINFO(channel); + sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); + sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel); + sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel); + sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); + sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); + sys_reg |= SYS_REG_ENC_BW(info->cap_info.bw, channel); + sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; From e0ddb0ba214f0bf05a66094a347169e617936c2b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:00 +0530 Subject: [PATCH 047/147] ram: rk3399: Rename sys_reg with sys_reg2 Use dram config variable name as sys_reg2 instead of sys_reg since the final variable value is to written into a pmugrf register named as sys_reg2. This reflect the both variable and associated register names are same and also help to add next sys_reg's to add it in future. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 9bd163fa484..38ae6d174a1 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1073,11 +1073,11 @@ static void set_ddrconfig(const struct chan_info *chan, static void dram_all_config(struct dram_info *dram, const struct rk3399_sdram_params *params) { - u32 sys_reg = 0; + u32 sys_reg2 = 0; unsigned int channel, idx; - sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); - sys_reg |= SYS_REG_ENC_NUM_CH(params->base.num_channels); + sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); + sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels); for (channel = 0, idx = 0; (idx < params->base.num_channels) && (channel < 2); @@ -1089,15 +1089,15 @@ static void dram_all_config(struct dram_info *dram, if (params->ch[channel].cap_info.col == 0) continue; idx++; - sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); - sys_reg |= SYS_REG_ENC_CHINFO(channel); - sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); - sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel); - sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel); - sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); - sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); - sys_reg |= SYS_REG_ENC_BW(info->cap_info.bw, channel); - sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); + sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); + sys_reg2 |= SYS_REG_ENC_CHINFO(channel); + sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); + sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); + sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); + sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); + sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); + sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); + sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; @@ -1118,7 +1118,7 @@ static void dram_all_config(struct dram_info *dram, 1 << 17); } - writel(sys_reg, &dram->pmugrf->os_reg2); + writel(sys_reg2, &dram->pmugrf->os_reg2); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, params->base.stride << 10); From 01cc1039153d0ca4202e8b944e321637e27adc86 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:01 +0530 Subject: [PATCH 048/147] ram: rk3399: Introduce sys_reg3 for more capacity info cs0_row, cs1_row and cs1_col needs more bits to show its correct value, update to make use of both sys_reg2, sys_reg3. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang (Squash similar patches into one patch) Signed-off-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_common.h | 21 +++++++++++++++---- drivers/ram/rockchip/sdram_rk3399.c | 9 ++++++-- 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 47492332266..f5c99fea8b3 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -90,12 +90,8 @@ struct sdram_base_params { SYS_REG_BK_SHIFT(ch)) #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) #define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \ - SYS_REG_CS0_ROW_SHIFT(ch)) #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \ - SYS_REG_CS1_ROW_SHIFT(ch)) #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) #define SYS_REG_BW_MASK 3 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch)) @@ -103,6 +99,23 @@ struct sdram_base_params { #define SYS_REG_DBW_MASK 3 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) +#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (5 + 2 * (ch)); \ + } while (0) + +#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \ + (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \ + (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (4 + 2 * (ch)); \ + } while (0) + +#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch)) +#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch)) + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 38ae6d174a1..fed9f948408 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram, const struct rk3399_sdram_params *params) { u32 sys_reg2 = 0; + u32 sys_reg3 = 0; unsigned int channel, idx; sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); @@ -1094,10 +1095,13 @@ static void dram_all_config(struct dram_info *dram, sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); - sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); - sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); + SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel); + if (info->cap_info.cs1_row) + SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2, + sys_reg3, channel); + sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; @@ -1119,6 +1123,7 @@ static void dram_all_config(struct dram_info *dram, } writel(sys_reg2, &dram->pmugrf->os_reg2); + writel(sys_reg3, &dram->pmugrf->os_reg3); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, params->base.stride << 10); From b713e0291ba90847058678ae2752f08f238c8fe3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:04 +0530 Subject: [PATCH 049/147] ram: rk3399: Add ddr version enc macro Add dram config macro for handling ddr version number. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++ drivers/ram/rockchip/sdram_rk3399.c | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index f5c99fea8b3..8027b53636a 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -66,6 +66,7 @@ struct sdram_base_params { * [1:0] dbw_ch0 */ #define SYS_REG_DDRTYPE_SHIFT 13 +#define DDR_SYS_REG_VERSION 2 #define SYS_REG_DDRTYPE_MASK 7 #define SYS_REG_NUM_CH_SHIFT 12 #define SYS_REG_NUM_CH_MASK 1 @@ -99,6 +100,7 @@ struct sdram_base_params { #define SYS_REG_DBW_MASK 3 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) +#define SYS_REG_ENC_VERSION(n) ((n) << 28) #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index fed9f948408..750219921bb 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1102,6 +1102,7 @@ static void dram_all_config(struct dram_info *dram, SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2, sys_reg3, channel); sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel); + sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; From ed77ce728aa2cd2c8b1c01ec3a0f2efb8f3edc26 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:05 +0530 Subject: [PATCH 050/147] ram: rk3399: Add ddrtimingC0 Add DdrTimingC0 structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 12 +++++++++++- drivers/ram/rockchip/sdram_rk3399.c | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 471702f9352..7f41a672426 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -18,6 +18,16 @@ struct rk3399_ddr_pi_regs { u32 denali_pi[200]; }; +union noc_ddrtimingc0 { + u32 d32; + struct { + unsigned burstpenalty : 4; + unsigned reserved0 : 4; + unsigned wrtomwr : 6; + unsigned reserved1 : 18; + } b; +}; + struct rk3399_msch_regs { u32 coreid; u32 revisionid; @@ -36,7 +46,7 @@ struct rk3399_msch_regs { struct rk3399_msch_timings { u32 ddrtiminga0; u32 ddrtimingb0; - u32 ddrtimingc0; + union noc_ddrtimingc0 ddrtimingc0; u32 devtodev0; u32 ddrmode; u32 agingx0; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 750219921bb..d47e2907c75 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1110,7 +1110,7 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrtiminga0); writel(noc_timing->ddrtimingb0, &ddr_msch_regs->ddrtimingb0); - writel(noc_timing->ddrtimingc0, + writel(noc_timing->ddrtimingc0.d32, &ddr_msch_regs->ddrtimingc0); writel(noc_timing->devtodev0, &ddr_msch_regs->devtodev0); From a735550bb8471a170247fad5376d0086b15ddedd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:06 +0530 Subject: [PATCH 051/147] ram: rk3399: Add DdrMode Add DdrMode structure with associated bit fields. These would help to reconfigure sdram capabilities during lpddr4 setup related configs. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/sdram_rk3399.h | 17 ++++++++++++++++- drivers/ram/rockchip/sdram_rk3399.c | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h index 7f41a672426..dc65ae79243 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h @@ -28,6 +28,21 @@ union noc_ddrtimingc0 { } b; }; +union noc_ddrmode { + u32 d32; + struct { + unsigned autoprecharge : 1; + unsigned bypassfiltering : 1; + unsigned fawbank : 1; + unsigned burstsize : 2; + unsigned mwrsize : 2; + unsigned reserved2 : 1; + unsigned forceorder : 8; + unsigned forceorderstate : 8; + unsigned reserved3 : 8; + } b; +}; + struct rk3399_msch_regs { u32 coreid; u32 revisionid; @@ -48,7 +63,7 @@ struct rk3399_msch_timings { u32 ddrtimingb0; union noc_ddrtimingc0 ddrtimingc0; u32 devtodev0; - u32 ddrmode; + union noc_ddrmode ddrmode; u32 agingx0; }; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index d47e2907c75..5568ad98461 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1114,7 +1114,7 @@ static void dram_all_config(struct dram_info *dram, &ddr_msch_regs->ddrtimingc0); writel(noc_timing->devtodev0, &ddr_msch_regs->devtodev0); - writel(noc_timing->ddrmode, + writel(noc_timing->ddrmode.d32, &ddr_msch_regs->ddrmode); /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ From ba607fafd12e44735b6f3bc352b686101efc9155 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:07 +0530 Subject: [PATCH 052/147] ram: rk3399: Configure phy IO in ds odt Some dramtypes like lpddr4 initialization would required to configure phy IO even after pctl_cfg and after set_ds_odt. For those cases the set_ds_odt would be an initial call to setup the phy. To satisfy all the cases, trigger phy IO from set_ds_odt. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 383 ++++++++++++++-------------- 1 file changed, 190 insertions(+), 193 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 5568ad98461..cca809a7e3a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -188,194 +188,6 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, writel(0x2EC7FFFF, &denali_pi[34]); } -static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *params) -{ - u32 *denali_phy = chan->publ->denali_phy; - - u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; - u32 tsel_idle_select_p, tsel_rd_select_p; - u32 tsel_idle_select_n, tsel_rd_select_n; - u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; - u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; - u32 reg_value; - - if (params->base.dramtype == LPDDR4) { - tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_rd_select_n = PHY_DRV_ODT_240; - - tsel_idle_select_p = PHY_DRV_ODT_HI_Z; - tsel_idle_select_n = PHY_DRV_ODT_240; - - tsel_wr_select_dq_p = PHY_DRV_ODT_40; - tsel_wr_select_dq_n = PHY_DRV_ODT_40; - - tsel_wr_select_ca_p = PHY_DRV_ODT_40; - tsel_wr_select_ca_n = PHY_DRV_ODT_40; - } else if (params->base.dramtype == LPDDR3) { - tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_HI_Z; - - tsel_idle_select_p = PHY_DRV_ODT_240; - tsel_idle_select_n = PHY_DRV_ODT_HI_Z; - - tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - - tsel_wr_select_ca_p = PHY_DRV_ODT_48; - tsel_wr_select_ca_n = PHY_DRV_ODT_48; - } else { - tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_rd_select_n = PHY_DRV_ODT_240; - - tsel_idle_select_p = PHY_DRV_ODT_240; - tsel_idle_select_n = PHY_DRV_ODT_240; - - tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; - tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; - - tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; - tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; - } - - if (params->base.odt == 1) - tsel_rd_en = 1; - else - tsel_rd_en = 0; - - tsel_wr_en = 0; - tsel_idle_en = 0; - - /* - * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 - * sets termination values for read/idle cycles and drive strength - * for write cycles for DQ/DM - */ - reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | - (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | - (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); - clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); - - /* - * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 - * sets termination values for read/idle cycles and drive strength - * for write cycles for DQS - */ - clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); - - /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); - - /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ - clrsetbits_le32(&denali_phy[928], 0xff, reg_value); - - /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ - clrsetbits_le32(&denali_phy[937], 0xff, reg_value); - - /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ - clrsetbits_le32(&denali_phy[935], 0xff, reg_value); - - /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); - - /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); - - /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ - clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4)); - clrsetbits_le32(&denali_phy[925], 0xff, - tsel_rd_select_n | (tsel_rd_select_p << 4)); - - /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ - reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) - << 16; - clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); - - /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ - reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) - << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); - - /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ - reg_value = tsel_wr_en << 8; - clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); - - /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ - reg_value = tsel_wr_en << 17; - clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); - /* - * pad_rst/cke/cs/clk_term tsel 1bits - * DENALI_PHY_938/936/940/934 offset_17 - */ - clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); - - /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ - clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); -} - -static void pctl_start(struct dram_info *dram, u8 channel) -{ - const struct chan_info *chan = &dram->chan[channel]; - u32 *denali_ctl = chan->pctl->denali_ctl; - u32 *denali_phy = chan->publ->denali_phy; - u32 *ddrc0_con = get_ddrc0_con(dram, channel); - u32 count = 0; - u32 byte, tmp; - - writel(0x01000000, &ddrc0_con); - - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); - - while (!(readl(&denali_ctl[203]) & (1 << 3))) { - if (count > 1000) { - printf("%s: Failed to init pctl for channel %d\n", - __func__, channel); - while (1) - ; - } - - udelay(1); - count++; - } - - writel(0x01000100, &ddrc0_con); - - for (byte = 0; byte < 4; byte++) { - tmp = 0x820; - writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]); - writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]); - writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]); - writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]); - writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]); - - clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp); - } - - clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - dram->pwrup_srefresh_exit[channel]); -} - static int phy_io_config(const struct chan_info *chan, const struct rk3399_sdram_params *params) { @@ -536,6 +348,196 @@ static int phy_io_config(const struct chan_info *chan, return 0; } +static void set_ds_odt(const struct chan_info *chan, + const struct rk3399_sdram_params *params) +{ + u32 *denali_phy = chan->publ->denali_phy; + + u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; + u32 tsel_idle_select_p, tsel_rd_select_p; + u32 tsel_idle_select_n, tsel_rd_select_n; + u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; + u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + u32 reg_value; + + if (params->base.dramtype == LPDDR4) { + tsel_rd_select_p = PHY_DRV_ODT_HI_Z; + tsel_rd_select_n = PHY_DRV_ODT_240; + + tsel_idle_select_p = PHY_DRV_ODT_HI_Z; + tsel_idle_select_n = PHY_DRV_ODT_240; + + tsel_wr_select_dq_p = PHY_DRV_ODT_40; + tsel_wr_select_dq_n = PHY_DRV_ODT_40; + + tsel_wr_select_ca_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_n = PHY_DRV_ODT_40; + } else if (params->base.dramtype == LPDDR3) { + tsel_rd_select_p = PHY_DRV_ODT_240; + tsel_rd_select_n = PHY_DRV_ODT_HI_Z; + + tsel_idle_select_p = PHY_DRV_ODT_240; + tsel_idle_select_n = PHY_DRV_ODT_HI_Z; + + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_48; + tsel_wr_select_ca_n = PHY_DRV_ODT_48; + } else { + tsel_rd_select_p = PHY_DRV_ODT_240; + tsel_rd_select_n = PHY_DRV_ODT_240; + + tsel_idle_select_p = PHY_DRV_ODT_240; + tsel_idle_select_n = PHY_DRV_ODT_240; + + tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; + tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; + + tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; + tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + } + + if (params->base.odt == 1) + tsel_rd_en = 1; + else + tsel_rd_en = 0; + + tsel_wr_en = 0; + tsel_idle_en = 0; + + /* + * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 + * sets termination values for read/idle cycles and drive strength + * for write cycles for DQ/DM + */ + reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | + (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | + (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); + clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); + + /* + * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 + * sets termination values for read/idle cycles and drive strength + * for write cycles for DQS + */ + clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); + clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); + + /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ + reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); + clrsetbits_le32(&denali_phy[544], 0xff, reg_value); + clrsetbits_le32(&denali_phy[672], 0xff, reg_value); + clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + + /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ + clrsetbits_le32(&denali_phy[928], 0xff, reg_value); + + /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ + clrsetbits_le32(&denali_phy[937], 0xff, reg_value); + + /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ + clrsetbits_le32(&denali_phy[935], 0xff, reg_value); + + /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ + clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + + /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ + clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + + /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ + clrsetbits_le32(&denali_phy[924], 0xff, + tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4)); + clrsetbits_le32(&denali_phy[925], 0xff, + tsel_rd_select_n | (tsel_rd_select_p << 4)); + + /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ + reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) + << 16; + clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); + clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); + + /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ + reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) + << 24; + clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); + clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); + + /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ + reg_value = tsel_wr_en << 8; + clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); + clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); + clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); + + /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ + reg_value = tsel_wr_en << 17; + clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); + /* + * pad_rst/cke/cs/clk_term tsel 1bits + * DENALI_PHY_938/936/940/934 offset_17 + */ + clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); + clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); + + /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ + clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); + + phy_io_config(chan, params); +} + +static void pctl_start(struct dram_info *dram, u8 channel) +{ + const struct chan_info *chan = &dram->chan[channel]; + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_phy = chan->publ->denali_phy; + u32 *ddrc0_con = get_ddrc0_con(dram, channel); + u32 count = 0; + u32 byte, tmp; + + writel(0x01000000, &ddrc0_con); + + clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); + + while (!(readl(&denali_ctl[203]) & (1 << 3))) { + if (count > 1000) { + printf("%s: Failed to init pctl for channel %d\n", + __func__, channel); + while (1) + ; + } + + udelay(1); + count++; + } + + writel(0x01000100, &ddrc0_con); + + for (byte = 0; byte < 4; byte++) { + tmp = 0x820; + writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]); + writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]); + + clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp); + } + + clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, + dram->pwrup_srefresh_exit[channel]); +} + static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, u32 channel, const struct rk3399_sdram_params *params) { @@ -545,7 +547,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, const u32 *params_ctl = params->pctl_regs.denali_ctl; const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; - int ret; /* * work around controller bug: @@ -623,10 +624,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, tmp = (readl(&denali_phy[467]) >> 16) & 0xff; clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); - ret = phy_io_config(chan, params); - if (ret) - return ret; - return 0; } From b6cf08949d4d8ff0940c0663ae1d978737705205 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:08 +0530 Subject: [PATCH 053/147] ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry Supporting LPDDR4 code support in RK3399 would increases the size of SPL/TPL. So add kconfig entry for RK3399 LPDDR4 code so-that the boards have LPDDR4 can enable them via defconfig. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index 151ffb684d9..4f274e01b35 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -23,4 +23,11 @@ config RAM_RK3399 This enables ram drivers support for the platforms based on Rockchip RK3399 SoC. +config RAM_RK3399_LPDDR4 + bool "LPDDR4 support for Rockchip RK3399" + depends on RAM_RK3399 + help + This enables LPDDR4 sdram code support for the platforms based + on Rockchip RK3399 SoC. + endif # RAM_ROCKCHIP From 3dae87da89e4c9edb4da9e05bde2e10bb98bd885 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:09 +0530 Subject: [PATCH 054/147] ram: rk3399: Add lpddr4 rank mask for ca training Add rank_mask based on the rank number for lpddr4. This would keep the ca data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index cca809a7e3a..b7cad9274b8 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -687,7 +687,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); - rank_mask = (rank == 1) ? 0x1 : 0x3; + if (params->base.dramtype == LPDDR4) + rank_mask = (rank == 1) ? 0x5 : 0xf; + else + rank_mask = (rank == 1) ? 0x1 : 0x3; for (i = 0; i < 4; i++) { if (!(rank_mask & (1 << i))) From c716bf67f5eb54ed64538f7ce70b36da04c55352 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:10 +0530 Subject: [PATCH 055/147] ram: rk3399: Add lpddr4 rank mask for wdql training Add rank_mask based on the rank number for lpddr4. This would keep the wdql data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index b7cad9274b8..3f20aba939c 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -925,7 +925,10 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ writel(0x00003f7c, (&denali_pi[175])); - rank_mask = (rank == 1) ? 0x1 : 0x3; + if (params->base.dramtype == LPDDR4) + rank_mask = (rank == 1) ? 0x5 : 0xf; + else + rank_mask = (rank == 1) ? 0x1 : 0x3; for (i = 0; i < 4; i++) { if (!(rank_mask & (1 << i))) From 6cbd2426b34e7430b0733ab9a912d378c027b647 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:11 +0530 Subject: [PATCH 056/147] ram: rk3399: Move mode_sel assignment mode_sel assignment is based on dram type. In phy_io_config, already have vref setting based on the dram type, so move this mode_sel assignment on vref setting area. No functionality change. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 3f20aba939c..35de76adb3a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -205,6 +205,7 @@ static int phy_io_config(const struct chan_info *chan, vref_value_dq = 0x1f; vref_mode_ac = 0x6; vref_value_ac = 0x1f; + mode_sel = 0x6; } else if (params->base.dramtype == LPDDR3) { if (params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ @@ -265,12 +266,14 @@ static int phy_io_config(const struct chan_info *chan, } vref_mode_ac = 0x2; vref_value_ac = 0x1f; + mode_sel = 0x0; } else if (params->base.dramtype == DDR3) { /* DDR3L */ vref_mode_dq = 0x1; vref_value_dq = 0x1f; vref_mode_ac = 0x1; vref_value_ac = 0x1f; + mode_sel = 0x1; } else { debug("Unknown DRAM type.\n"); return -EINVAL; @@ -292,15 +295,6 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); - if (params->base.dramtype == LPDDR4) - mode_sel = 0x6; - else if (params->base.dramtype == LPDDR3) - mode_sel = 0x0; - else if (params->base.dramtype == DDR3) - mode_sel = 0x1; - else - return -EINVAL; - /* PHY_924 PHY_PAD_FDBK_DRIVE */ clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); /* PHY_926 PHY_PAD_DATA_DRIVE */ From 5cbc8669819a69c22a50d2fb22c9d4962c8bbad5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:12 +0530 Subject: [PATCH 057/147] ram: rk3399: Don't wait for PLL lock in lpddr4 lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations. So no need to wait explicitly during pctl config. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 35de76adb3a..6f6f38214df 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -570,16 +570,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, setbits_le32(&denali_pi[0], START); setbits_le32(&denali_ctl[0], START); - /* Waiting for phy DLL lock */ - while (1) { - tmp = readl(&denali_phy[920]); - tmp1 = readl(&denali_phy[921]); - tmp2 = readl(&denali_phy[922]); - if ((((tmp >> 16) & 0x1) == 0x1) && - (((tmp1 >> 16) & 0x1) == 0x1) && - (((tmp1 >> 0) & 0x1) == 0x1) && - (((tmp2 >> 0) & 0x1) == 0x1)) - break; + /** + * LPDDR4 use PLL bypass mode for init + * not need to wait for the PLL to lock + */ + if (params->base.dramtype != LPDDR4) { + /* Waiting for phy DLL lock */ + while (1) { + tmp = readl(&denali_phy[920]); + tmp1 = readl(&denali_phy[921]); + tmp2 = readl(&denali_phy[922]); + if ((((tmp >> 16) & 0x1) == 0x1) && + (((tmp1 >> 16) & 0x1) == 0x1) && + (((tmp1 >> 0) & 0x1) == 0x1) && + (((tmp2 >> 0) & 0x1) == 0x1)) + break; + } } copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); From 47627c8a5cfc0d5d60ca81446528705b3b56077b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:13 +0530 Subject: [PATCH 058/147] ram: rk3399: Avoid two channel ZQ Cal Start at the same time It is possible in lpddr4 dram, where both the channels would start at same time with ZQ Cal Start. If it uses ZQ Call start then it will use RZQ. For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe connect to both channel. If ZQ Cal Start at the same time, it will use the same RZQ. It is not a problem of using RZQ in both the channels, but can not use at the same time. So, to avoid this, we have an option of dram tINIT3 value for increasing the frequency for channel 1. This patch increase the available tINIT3 with existing running dram frequency. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 6f6f38214df..8b2c6b3cdbd 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -550,6 +550,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, sizeof(struct rk3399_ddr_pctl_regs) - 4); writel(params_ctl[0], &denali_ctl[0]); + /* + * two channel init at the same time, then ZQ Cal Start + * at the same time, it will use the same RZQ, but cannot + * start at the same time. + * + * So, increase tINIT3 for channel 1, will avoid two + * channel ZQ Cal Start at the same time + */ + if (params->base.dramtype == LPDDR4 && channel == 1) { + tmp = ((params->base.ddr_freq * MHz + 999) / 1000); + tmp1 = readl(&denali_ctl[14]); + writel(tmp + tmp1, &denali_ctl[14]); + } + copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], sizeof(struct rk3399_ddr_pi_regs)); From 009fe1bac96889bd5f10f8d7a3edf4f1ba125ff3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:14 +0530 Subject: [PATCH 059/147] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 PHY_898, PHY_919 would require to configure PHY LP4 boot pll control and ca for lpddr4. So, configure the same in pctl_cfg for LPDDR4. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 8b2c6b3cdbd..aaf786a03e0 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -574,6 +574,11 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, writel(params->phy_regs.denali_phy[911], &denali_phy[911]); writel(params->phy_regs.denali_phy[912], &denali_phy[912]); + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + writel(params->phy_regs.denali_phy[898], &denali_phy[898]); + writel(params->phy_regs.denali_phy[919], &denali_phy[919]); + } + dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); From 881860fd34bea88929a5849f7550d70b0a9d6099 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:15 +0530 Subject: [PATCH 060/147] ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4 Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index aaf786a03e0..0c8a7f81ccc 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -35,6 +35,9 @@ #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf +#define PHY_BOOSTP_EN 0x1 +#define PHY_BOOSTN_EN 0x1 + #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ ((n) << (8 + (ch) * 4))) #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ @@ -312,6 +315,27 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + /* BOOSTP_EN & BOOSTN_EN */ + reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN); + /* PHY_925 PHY_PAD_FDBK_DRIVE2 */ + clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20); + } + /* speed setting */ if (params->base.ddr_freq < 400) speed = 0x0; From f9f32d61a6d5268b0b5358005b0a0725f0d50529 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:16 +0530 Subject: [PATCH 061/147] ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4 Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 0c8a7f81ccc..d6847224442 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -37,6 +37,8 @@ #define PHY_BOOSTP_EN 0x1 #define PHY_BOOSTN_EN 0x1 +#define PHY_SLEWP_EN 0x1 +#define PHY_SLEWN_EN 0x1 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ ((n) << (8 + (ch) * 4))) @@ -334,6 +336,25 @@ static int phy_io_config(const struct chan_info *chan, clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20); /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20); + + /* SLEWP_EN & SLEWN_EN */ + reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN); + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x3f, reg_value); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x3f, reg_value); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8); } /* speed setting */ From d3d0099ca6661af0ae3cab1402fbe87121b645a5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:17 +0530 Subject: [PATCH 062/147] ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4 Configure PHY RX_CM_INPUT for lpddr4 during phy IO config. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index d6847224442..e5265128ae2 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -39,6 +39,7 @@ #define PHY_BOOSTN_EN 0x1 #define PHY_SLEWP_EN 0x1 #define PHY_SLEWN_EN 0x1 +#define PHY_RX_CM_INPUT 0x1 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ ((n) << (8 + (ch) * 4))) @@ -384,6 +385,27 @@ static int phy_io_config(const struct chan_info *chan, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + /* RX_CM_INPUT */ + reg_value = PHY_RX_CM_INPUT; + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19); + } + return 0; } From 4e9de9eba844a2432a40ffb4ce7a07f9d786e940 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:18 +0530 Subject: [PATCH 063/147] ram: rk3399: Map chipselect for lpddr4 Assign desired cs_map values for lpddr4 during set memory map. Initial cs_map values is based on the sdram parameters, so the same will adjusted based dramtype as LPDDR4. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index e5265128ae2..2498620aecd 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -188,6 +188,16 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), ((3 - sdram_ch->cap_info.bk) << 16) | ((16 - row) << 24)); + + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + if (cs_map == 1) + cs_map = 0x5; + else if (cs_map == 2) + cs_map = 0xa; + else + cs_map = 0xF; + } + /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3) From 66912baa0f00b915df5d2135c40e62b58c965669 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:19 +0530 Subject: [PATCH 064/147] ram: rk3399: Configure tsel write ca for lpddr4 tsel write ca_p and ca_n values need to write on PHY 544, 672 and 800 to configure ds odt. Configure the same PHY register for lpddr4 would require a mask value of (300 << 8). Add support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 2498620aecd..3e069ab0ef3 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -502,9 +502,18 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + /* LPDDR4 these register read always return 0, so + * can not use clrsetbits_le32(), need to write32 + */ + writel((0x300 << 8) | reg_value, &denali_phy[544]); + writel((0x300 << 8) | reg_value, &denali_phy[672]); + writel((0x300 << 8) | reg_value, &denali_phy[800]); + } else { + clrsetbits_le32(&denali_phy[544], 0xff, reg_value); + clrsetbits_le32(&denali_phy[672], 0xff, reg_value); + clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + } /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ clrsetbits_le32(&denali_phy[928], 0xff, reg_value); From 740409804e96bcc3411af66f5daa5914ff888638 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:20 +0530 Subject: [PATCH 065/147] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1 The hardware for LPDDR4 with - CLK0P/N connect to lower 16-bits - CLK1P/N connect to higher 16-bits and usually dfi dram clk is configured via CLK1P/N, so disabling dfi dram clk will disable the CLK1P/N as well. So, add patch to not to disable dfi dram clk for lpddr4, with rank 1. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 3e069ab0ef3..781d1170a09 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1225,8 +1225,18 @@ static void dram_all_config(struct dram_info *dram, writel(noc_timing->ddrmode.d32, &ddr_msch_regs->ddrmode); - /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ - if (params->ch[channel].cap_info.rank == 1) + /** + * rank 1 memory clock disable (dfi_dram_clk_disable = 1) + * + * The hardware for LPDDR4 with + * - CLK0P/N connect to lower 16-bits + * - CLK1P/N connect to higher 16-bits + * + * dfi dram clk is configured via CLK1P/N, so disabling + * dfi dram clk will disable the CLK1P/N as well for lpddr4. + */ + if (params->ch[channel].cap_info.rank == 1 && + params->base.dramtype != LPDDR4) setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 1 << 17); } From 74109de3c2ff8beb9d0a311f1a0b26a715050c06 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:21 +0530 Subject: [PATCH 066/147] ram: rk3399: Add IO settings Add IO settings for dram ctl and phy. IO settings are useful for configuring ctl, phy odt, vref, mr5, mode select and other needed input output operations for lpddr4 or any other dramtype sdram. Right now, this patch added IO setting for all supported sdram frequencies. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 104 ++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 781d1170a09..9121d5b779d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -80,6 +80,110 @@ struct rockchip_dmc_plat { struct regmap *map; }; +struct io_setting { + u32 mhz; + u32 mr5; + /* dram side */ + u32 dq_odt; + u32 ca_odt; + u32 pdds; + u32 dq_vref; + u32 ca_vref; + /* phy side */ + u32 rd_odt; + u32 wr_dq_drv; + u32 wr_ca_drv; + u32 wr_ckcs_drv; + u32 rd_odt_en; + u32 rd_vref; +} lpddr4_io_setting[] = { + { + 50 * MHz, + 0, + /* dram side */ + 0, /* dq_odt; */ + 0, /* ca_odt; */ + 6, /* pdds; */ + 0x72, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_HI_Z, /* rd_odt; */ + PHY_DRV_ODT_40, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 0, /* rd_odt_en;*/ + 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, + { + 600 * MHz, + 0, + /* dram side */ + 1, /* dq_odt; */ + 0, /* ca_odt; */ + 6, /* pdds; */ + 0x72, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_HI_Z, /* rd_odt; */ + PHY_DRV_ODT_48, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 0, /* rd_odt_en; */ + 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, + { + 800 * MHz, + 0, + /* dram side */ + 1, /* dq_odt; */ + 0, /* ca_odt; */ + 1, /* pdds; */ + 0x72, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_40, /* rd_odt; */ + PHY_DRV_ODT_48, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 1, /* rd_odt_en; */ + 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, + { + 933 * MHz, + 0, + /* dram side */ + 3, /* dq_odt; */ + 0, /* ca_odt; */ + 6, /* pdds; */ + 0x59, /* dq_vref; 32% */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_HI_Z, /* rd_odt; */ + PHY_DRV_ODT_48, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 0, /* rd_odt_en; */ + 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, + { + 1066 * MHz, + 0, + /* dram side */ + 6, /* dq_odt; */ + 0, /* ca_odt; */ + 1, /* pdds; */ + 0x10, /* dq_vref; */ + 0x72, /* ca_vref; */ + /* phy side */ + PHY_DRV_ODT_40, /* rd_odt; */ + PHY_DRV_ODT_60, /* wr_dq_drv; */ + PHY_DRV_ODT_40, /* wr_ca_drv; */ + PHY_DRV_ODT_40, /* wr_ckcs_drv; */ + 1, /* rd_odt_en; */ + 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */ + }, +}; + static void *get_ddrc0_con(struct dram_info *dram, u8 channel) { return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1; From 2fb2de33b2d89442d08a7d69f6afb9c7e46aa992 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:22 +0530 Subject: [PATCH 067/147] ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 9121d5b779d..5a2d50f9824 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -184,6 +184,33 @@ struct io_setting { }, }; +/** + * phy = 0, PHY boot freq + * phy = 1, PHY index 0 + * phy = 2, PHY index 1 + */ +static struct io_setting * +lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5) +{ + struct io_setting *io = NULL; + u32 n; + + for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) { + io = &lpddr4_io_setting[n]; + + if (io->mr5 != 0) { + if (io->mhz >= params->base.ddr_freq && + io->mr5 == mr5) + break; + } else { + if (io->mhz >= params->base.ddr_freq) + break; + } + } + + return io; +} + static void *get_ddrc0_con(struct dram_info *dram, u8 channel) { return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1; @@ -524,7 +551,7 @@ static int phy_io_config(const struct chan_info *chan, } static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *params) + const struct rk3399_sdram_params *params, u32 mr5) { u32 *denali_phy = chan->publ->denali_phy; @@ -533,19 +560,22 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_rd_select_n; u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + struct io_setting *io = NULL; u32 reg_value; if (params->base.dramtype == LPDDR4) { + io = lpddr4_get_io_settings(params, mr5); + tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_rd_select_n = io->rd_odt; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_idle_select_n = PHY_DRV_ODT_240; - tsel_wr_select_dq_p = PHY_DRV_ODT_40; + tsel_wr_select_dq_p = io->wr_dq_drv; tsel_wr_select_dq_n = PHY_DRV_ODT_40; - tsel_wr_select_ca_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_p = io->wr_ca_drv; tsel_wr_select_ca_n = PHY_DRV_ODT_40; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -723,7 +753,7 @@ static void pctl_start(struct dram_info *dram, u8 channel) } static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, - u32 channel, const struct rk3399_sdram_params *params) + u32 channel, struct rk3399_sdram_params *params) { u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; @@ -805,7 +835,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); - set_ds_odt(chan, params); + set_ds_odt(chan, params, 0); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 From aa30aae8b4e8c871a263ad67c4b4fdca236bf7c1 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:23 +0530 Subject: [PATCH 068/147] ram: rk3399: Add tsel control clock drive tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 5a2d50f9824..d958e9ddf71 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -560,6 +560,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_rd_select_n; u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + u32 tsel_ckcs_select_p, tsel_ckcs_select_n; struct io_setting *io = NULL; u32 reg_value; @@ -577,6 +578,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = io->wr_ca_drv; tsel_wr_select_ca_n = PHY_DRV_ODT_40; + + tsel_ckcs_select_p = io->wr_ckcs_drv; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -589,6 +593,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_wr_select_ca_n = PHY_DRV_ODT_48; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -601,6 +608,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } if (params->base.odt == 1) @@ -659,10 +669,12 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[935], 0xff, reg_value); /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + clrsetbits_le32(&denali_phy[939], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + clrsetbits_le32(&denali_phy[929], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff, From f288d54936d7360e934132a128d7e92d3b1c95a0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:24 +0530 Subject: [PATCH 069/147] ram: rk3399: Configure soc odt support CTL 145, 146, 159, 160 registers are used to configure soc odt on rk3399. These soc odt values are updated from CS0_MR22_VAL and CS1_MR22_VAL and for lpddr4 these values ORed with tsel_rd_select_n. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index d958e9ddf71..7ef7707a03c 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -40,6 +40,8 @@ #define PHY_SLEWP_EN 0x1 #define PHY_SLEWN_EN 0x1 #define PHY_RX_CM_INPUT 0x1 +#define CS0_MR22_VAL 0 +#define CS1_MR22_VAL 3 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ ((n) << (8 + (ch) * 4))) @@ -554,7 +556,7 @@ static void set_ds_odt(const struct chan_info *chan, const struct rk3399_sdram_params *params, u32 mr5) { u32 *denali_phy = chan->publ->denali_phy; - + u32 *denali_ctl = chan->pctl->denali_ctl; u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_rd_select_p; u32 tsel_idle_select_n, tsel_rd_select_n; @@ -562,6 +564,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; u32 tsel_ckcs_select_p, tsel_ckcs_select_n; struct io_setting *io = NULL; + u32 soc_odt = 0; u32 reg_value; if (params->base.dramtype == LPDDR4) { @@ -581,6 +584,35 @@ static void set_ds_odt(const struct chan_info *chan, tsel_ckcs_select_p = io->wr_ckcs_drv; tsel_ckcs_select_n = PHY_DRV_ODT_34_3; + switch (tsel_rd_select_n) { + case PHY_DRV_ODT_240: + soc_odt = 1; + break; + case PHY_DRV_ODT_120: + soc_odt = 2; + break; + case PHY_DRV_ODT_80: + soc_odt = 3; + break; + case PHY_DRV_ODT_60: + soc_odt = 4; + break; + case PHY_DRV_ODT_48: + soc_odt = 5; + break; + case PHY_DRV_ODT_40: + soc_odt = 6; + break; + case PHY_DRV_ODT_34_3: + soc_odt = 6; + printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n", + __func__); + break; + case PHY_DRV_ODT_HI_Z: + default: + soc_odt = 0; + break; + } } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -621,6 +653,21 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_en = 0; tsel_idle_en = 0; + /* F0_0 */ + clrsetbits_le32(&denali_ctl[145], 0xFF << 16, + (soc_odt | (CS0_MR22_VAL << 3)) << 16); + /* F2_0, F1_0 */ + clrsetbits_le32(&denali_ctl[146], 0xFF00FF, + ((soc_odt | (CS0_MR22_VAL << 3)) << 16) | + (soc_odt | (CS0_MR22_VAL << 3))); + /* F0_1 */ + clrsetbits_le32(&denali_ctl[159], 0xFF << 16, + (soc_odt | (CS1_MR22_VAL << 3)) << 16); + /* F2_1, F1_1 */ + clrsetbits_le32(&denali_ctl[160], 0xFF00FF, + ((soc_odt | (CS1_MR22_VAL << 3)) << 16) | + (soc_odt | (CS1_MR22_VAL << 3))); + /* * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 * sets termination values for read/idle cycles and drive strength From 4eceda01d5df9d90d6402dfd5fcf1bcc9c5c00e6 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:25 +0530 Subject: [PATCH 070/147] ram: rk3399: Get lpddr4 tsel_rd_en from io settings For base.odt 1 the lpddr4 tsel_rd_en value is depending on IO settings of rd_odt_en. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 7ef7707a03c..7dd3a44bfb0 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -645,10 +645,14 @@ static void set_ds_odt(const struct chan_info *chan, tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } - if (params->base.odt == 1) + if (params->base.odt == 1) { tsel_rd_en = 1; - else + + if (params->base.dramtype == LPDDR4) + tsel_rd_en = io->rd_odt_en; + } else { tsel_rd_en = 0; + } tsel_wr_en = 0; tsel_idle_en = 0; From 95be76eb5ce0d807d5b1b360efbac11f16a819af Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:26 +0530 Subject: [PATCH 071/147] ram: rk3399: Update lpddr4 vref based on io settings The vref_mode_dq, vref_value_dq on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 7dd3a44bfb0..e1e75313ad8 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -338,7 +338,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel, } static int phy_io_config(const struct chan_info *chan, - const struct rk3399_sdram_params *params) + const struct rk3399_sdram_params *params, u32 mr5) { u32 *denali_phy = chan->publ->denali_phy; u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; @@ -349,9 +349,18 @@ static int phy_io_config(const struct chan_info *chan, /* vref setting */ if (params->base.dramtype == LPDDR4) { - /* LPDDR4 */ - vref_mode_dq = 0x6; - vref_value_dq = 0x1f; + struct io_setting *io = lpddr4_get_io_settings(params, mr5); + u32 rd_vref = io->rd_vref * 1000; + + if (rd_vref < 36700) { + /* MODE_LV[2:0] = LPDDR4 (Range 2)*/ + vref_mode_dq = 0x7; + vref_value_dq = (rd_vref - 3300) / 521; + } else { + /* MODE_LV[2:0] = LPDDR4 (Range 1)*/ + vref_mode_dq = 0x6; + vref_value_dq = (rd_vref - 15300) / 521; + } vref_mode_ac = 0x6; vref_value_ac = 0x1f; mode_sel = 0x6; @@ -770,7 +779,7 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); - phy_io_config(chan, params); + phy_io_config(chan, params, mr5); } static void pctl_start(struct dram_info *dram, u8 channel) From 274c33737bcb49d9120ea222ba1a434d3fdca1c7 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:27 +0530 Subject: [PATCH 072/147] ram: rk3399: Update lpddr4 mode_sel based on io settings The mode_sel on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index e1e75313ad8..84a09fe67d5 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -347,7 +347,7 @@ static int phy_io_config(const struct chan_info *chan, u32 drv_value, odt_value; u32 speed; - /* vref setting */ + /* vref setting & mode setting */ if (params->base.dramtype == LPDDR4) { struct io_setting *io = lpddr4_get_io_settings(params, mr5); u32 rd_vref = io->rd_vref * 1000; @@ -355,15 +355,18 @@ static int phy_io_config(const struct chan_info *chan, if (rd_vref < 36700) { /* MODE_LV[2:0] = LPDDR4 (Range 2)*/ vref_mode_dq = 0x7; + /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */ + mode_sel = 0x5; vref_value_dq = (rd_vref - 3300) / 521; } else { /* MODE_LV[2:0] = LPDDR4 (Range 1)*/ vref_mode_dq = 0x6; + /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */ + mode_sel = 0x4; vref_value_dq = (rd_vref - 15300) / 521; } vref_mode_ac = 0x6; vref_value_ac = 0x1f; - mode_sel = 0x6; } else if (params->base.dramtype == LPDDR3) { if (params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ From e939f92eae5b6524c18cbb4a42f4cc3910e5d018 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:28 +0530 Subject: [PATCH 073/147] ram: rk3399: Update lpddr4 vref_mode_ac Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8% Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 84a09fe67d5..da94bbef5dd 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -366,7 +366,8 @@ static int phy_io_config(const struct chan_info *chan, vref_value_dq = (rd_vref - 15300) / 521; } vref_mode_ac = 0x6; - vref_value_ac = 0x1f; + /* VDDQ/3/2=16.8% */ + vref_value_ac = 0x3; } else if (params->base.dramtype == LPDDR3) { if (params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ From e6ae37a007c2ddc5f070c8ce65349b472e625060 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:29 +0530 Subject: [PATCH 074/147] ram: rk3399: Simplify data training first argument data training is using chan_info as first argument with channel number as second argument instead of that use dram_info as first argument so-that we can get the chan_info at data training definition. This was the argument handling is meaningful, readable and it would help to add similar data training for lpddr4 in future. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index da94bbef5dd..8a261e0fe91 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1286,10 +1286,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel, return 0; } -static int data_training(const struct chan_info *chan, u32 channel, +static int data_training(struct dram_info *dram, u32 channel, const struct rk3399_sdram_params *params, u32 training_flag) { + struct chan_info *chan = &dram->chan[channel]; u32 *denali_phy = chan->publ->denali_phy; int ret; @@ -1498,8 +1499,7 @@ static int switch_to_phy_index1(struct dram_info *dram, for (channel = 0; channel < ch_count; channel++) { denali_phy = dram->chan[channel].publ->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); - ret = data_training(&dram->chan[channel], channel, - params, PI_FULL_TRAINING); + ret = data_training(dram, channel, params, PI_FULL_TRAINING); if (ret < 0) { debug("index1 training failed\n"); return ret; @@ -1662,8 +1662,7 @@ static int sdram_init(struct dram_info *dram, if (params->base.dramtype == LPDDR3) training_flag |= PI_CA_TRAINING; - if (!(data_training(&dram->chan[ch], ch, - params, training_flag))) + if (!(data_training(dram, ch, params, training_flag))) break; } /* Computed rank with associated channel number */ From 299deecf4a8cd6bc5b17fd3691a39066601eca35 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:30 +0530 Subject: [PATCH 075/147] ram: rk3399: Handle data training via ops data training can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 43 ++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 8a261e0fe91..1a33951525b 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -65,11 +65,17 @@ struct dram_info { struct rk3399_pmucru *pmucru; struct rk3399_pmusgrf_regs *pmusgrf; struct rk3399_ddr_cic_regs *cic; + const struct sdram_rk3399_ops *ops; #endif struct ram_info info; struct rk3399_pmugrf_regs *pmugrf; }; +struct sdram_rk3399_ops { + int (*data_training)(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *sdram); +}; + #if defined(CONFIG_TPL_BUILD) || \ (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) @@ -1464,6 +1470,23 @@ static void dram_all_config(struct dram_info *dram, clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); } +static int default_data_training(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *params) +{ + u8 training_flag = PI_READ_GATE_TRAINING; + + /* + * LPDDR3 CA training msut be trigger before + * other training. + * DDR3 is not have CA training. + */ + + if (params->base.dramtype == LPDDR3) + training_flag |= PI_CA_TRAINING; + + return data_training(dram, channel, params, training_flag); +} + static int switch_to_phy_index1(struct dram_info *dram, const struct rk3399_sdram_params *params) { @@ -1626,7 +1649,6 @@ static int sdram_init(struct dram_info *dram, { unsigned char dramtype = params->base.dramtype; unsigned int ddr_freq = params->base.ddr_freq; - u32 training_flag = PI_READ_GATE_TRAINING; int channel, ch, rank; int ret; @@ -1654,16 +1676,12 @@ static int sdram_init(struct dram_info *dram, params->ch[ch].cap_info.rank = rank; - /* - * LPDDR3 CA training msut be trigger before - * other training. - * DDR3 is not have CA training. - */ - if (params->base.dramtype == LPDDR3) - training_flag |= PI_CA_TRAINING; - - if (!(data_training(dram, ch, params, training_flag))) + ret = dram->ops->data_training(dram, ch, rank, params); + if (!ret) { + debug("%s: data trained for rank %d, ch %d\n", + __func__, rank, ch); break; + } } /* Computed rank with associated channel number */ params->ch[ch].cap_info.rank = rank; @@ -1759,6 +1777,10 @@ static int conv_of_platdata(struct udevice *dev) } #endif +static const struct sdram_rk3399_ops rk3399_ops = { + .data_training = default_data_training, +}; + static int rk3399_dmc_init(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); @@ -1776,6 +1798,7 @@ static int rk3399_dmc_init(struct udevice *dev) return ret; #endif + priv->ops = &rk3399_ops; priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); From a0ded6d317b0a12e1555080e55971bde8e932026 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:31 +0530 Subject: [PATCH 076/147] ram: rk3399: Add LPPDR4 mr detection Like data training in other sdram types, mr detection need to taken care for lpddr4 with looped rank and associated channel to make sure the proper configuration held. Once the mr detection successful for active and configured rank with channel number, the same can later reused during actual LPDDR4 initialization. So, add code to support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 226 ++++++++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 1a33951525b..fe79f31cdb3 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1470,6 +1470,7 @@ static void dram_all_config(struct dram_info *dram, clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); } +#if !defined(CONFIG_RAM_RK3399_LPDDR4) static int default_data_training(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *params) { @@ -1486,6 +1487,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank, return data_training(dram, channel, params, training_flag); } +#endif static int switch_to_phy_index1(struct dram_info *dram, const struct rk3399_sdram_params *params) @@ -1532,6 +1534,226 @@ static int switch_to_phy_index1(struct dram_info *dram, return 0; } +#if defined(CONFIG_RAM_RK3399_LPDDR4) +static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf) +{ + return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F); +} + +static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) +{ + rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); +} + +static void set_cap_relate_config(const struct chan_info *chan, + struct rk3399_sdram_params *params, + unsigned int channel) +{ + u32 *denali_ctl = chan->pctl->denali_ctl; + u32 tmp; + struct rk3399_msch_timings *noc_timing; + + if (params->base.dramtype == LPDDR3) { + tmp = (8 << params->ch[channel].cap_info.bw) / + (8 << params->ch[channel].cap_info.dbw); + + /** + * memdata_ratio + * 1 -> 0, 2 -> 1, 4 -> 2 + */ + clrsetbits_le32(&denali_ctl[197], 0x7, + (tmp >> 1)); + clrsetbits_le32(&denali_ctl[198], 0x7 << 8, + (tmp >> 1) << 8); + } + + noc_timing = ¶ms->ch[channel].noc_timings; + + /* + * noc timing bw relate timing is 32 bit, and real bw is 16bit + * actually noc reg is setting at function dram_all_config + */ + if (params->ch[channel].cap_info.bw == 16 && + noc_timing->ddrmode.b.mwrsize == 2) { + if (noc_timing->ddrmode.b.burstsize) + noc_timing->ddrmode.b.burstsize -= 1; + noc_timing->ddrmode.b.mwrsize -= 1; + noc_timing->ddrtimingc0.b.burstpenalty *= 2; + noc_timing->ddrtimingc0.b.wrtomwr *= 2; + } +} + +static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel) +{ + unsigned int cs0_row = params->ch[channel].cap_info.cs0_row; + unsigned int col = params->ch[channel].cap_info.col; + unsigned int bw = params->ch[channel].cap_info.bw; + u16 ddr_cfg_2_rbc[] = { + /* + * [6] highest bit col + * [5:3] max row(14+n) + * [2] insertion row + * [1:0] col(9+n),col, data bus 32bit + * + * highbitcol, max_row, insertion_row, col + */ + ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ + ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ + ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ + ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ + ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ + ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ + ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ + ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ + }; + u32 i; + + col -= (bw == 2) ? 0 : 1; + col -= 9; + + for (i = 0; i < 4; i++) { + if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && + (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) + break; + } + + if (i >= 4) + i = -EINVAL; + + return i; +} + +/** + * read mr_num mode register + * rank = 1: cs0 + * rank = 2: cs1 + */ +static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank, + u32 mr_num, u32 *buf) +{ + s32 timeout = 100; + + writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8, + &ddr_pctl_regs->denali_ctl[118]); + + while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) & + ((1 << 21) | (1 << 12)))) { + udelay(1); + + if (timeout <= 0) { + printf("%s: pctl timeout!\n", __func__); + return -ETIMEDOUT; + } + + timeout--; + } + + if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) { + *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF; + } else { + printf("%s: read mr failed with 0x%x status\n", __func__, + readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3); + *buf = 0; + } + + setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12)); + + return 0; +} + +static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *params) +{ + u64 cs0_cap; + u32 stride; + u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0; + u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0; + u32 mr5, mr12, mr14; + struct chan_info *chan = &dram->chan[channel]; + struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl; + void __iomem *addr = NULL; + int ret = 0; + u32 val; + + stride = get_ddr_stride(dram->pmusgrf); + + if (params->ch[channel].cap_info.col == 0) { + ret = -EPERM; + goto end; + } + + cs = params->ch[channel].cap_info.rank; + col = params->ch[channel].cap_info.col; + bk = params->ch[channel].cap_info.bk; + bw = params->ch[channel].cap_info.bw; + row_3_4 = params->ch[channel].cap_info.row_3_4; + cs0_row = params->ch[channel].cap_info.cs0_row; + cs1_row = params->ch[channel].cap_info.cs1_row; + ddrconfig = params->ch[channel].cap_info.ddrconfig; + + /* 2GB */ + params->ch[channel].cap_info.rank = 2; + params->ch[channel].cap_info.col = 10; + params->ch[channel].cap_info.bk = 3; + params->ch[channel].cap_info.bw = 2; + params->ch[channel].cap_info.row_3_4 = 0; + params->ch[channel].cap_info.cs0_row = 15; + params->ch[channel].cap_info.cs1_row = 15; + params->ch[channel].cap_info.ddrconfig = 1; + + set_memory_map(chan, channel, params); + params->ch[channel].cap_info.ddrconfig = + calculate_ddrconfig(params, channel); + set_ddrconfig(chan, params, channel, + params->ch[channel].cap_info.ddrconfig); + set_cap_relate_config(chan, params, channel); + + cs0_cap = (1 << (params->ch[channel].cap_info.bw + + params->ch[channel].cap_info.col + + params->ch[channel].cap_info.bk + + params->ch[channel].cap_info.cs0_row)); + + if (params->ch[channel].cap_info.row_3_4) + cs0_cap = cs0_cap * 3 / 4; + + if (channel == 0) + set_ddr_stride(dram->pmusgrf, 0x17); + else + set_ddr_stride(dram->pmusgrf, 0x18); + + /* read and write data to DRAM, avoid be optimized by compiler. */ + if (rank == 1) + addr = (void __iomem *)0x100; + else if (rank == 2) + addr = (void __iomem *)(cs0_cap + 0x100); + + val = readl(addr); + writel(val + 1, addr); + + read_mr(ddr_pctl_regs, rank, 5, &mr5); + read_mr(ddr_pctl_regs, rank, 12, &mr12); + read_mr(ddr_pctl_regs, rank, 14, &mr14); + + if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) { + ret = -EINVAL; + goto end; + } +end: + params->ch[channel].cap_info.rank = cs; + params->ch[channel].cap_info.col = col; + params->ch[channel].cap_info.bk = bk; + params->ch[channel].cap_info.bw = bw; + params->ch[channel].cap_info.row_3_4 = row_3_4; + params->ch[channel].cap_info.cs0_row = cs0_row; + params->ch[channel].cap_info.cs1_row = cs1_row; + params->ch[channel].cap_info.ddrconfig = ddrconfig; + + set_ddr_stride(dram->pmusgrf, stride); + + return ret; +} +#endif /* CONFIG_RAM_RK3399_LPDDR4 */ + static unsigned char calculate_stride(struct rk3399_sdram_params *params) { unsigned int stride = params->base.stride; @@ -1778,7 +2000,11 @@ static int conv_of_platdata(struct udevice *dev) #endif static const struct sdram_rk3399_ops rk3399_ops = { +#if !defined(CONFIG_RAM_RK3399_LPDDR4) .data_training = default_data_training, +#else + .data_training = lpddr4_mr_detect, +#endif }; static int rk3399_dmc_init(struct udevice *dev) From 614d8ca438886fa1262d7dd34e1a68df76455dcf Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:32 +0530 Subject: [PATCH 077/147] arm: include: rockchip: Add rk3399 pmu file Add pmu header file for rk3399 SoC, this will help to configure pmu in sdram driver. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- .../include/asm/arch-rockchip/pmu_rk3399.h | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h new file mode 100644 index 00000000000..f1096dccced --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + * + */ + +#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ +#define __SOC_ROCKCHIP_RK3399_PMU_H__ + +struct rk3399_pmu_regs { + u32 pmu_wakeup_cfg[5]; + u32 pmu_pwrdn_con; + u32 pmu_pwrdn_st; + u32 pmu_pll_con; + u32 pmu_pwrmode_con; + u32 pmu_sft_con; + u32 pmu_int_con; + u32 pmu_int_st; + u32 pmu_gpio0_pos_int_con; + u32 pmu_gpio0_net_int_con; + u32 pmu_gpio1_pos_int_con; + u32 pmu_gpio1_net_int_con; + u32 pmu_gpio0_pos_int_st; + u32 pmu_gpio0_net_int_st; + u32 pmu_gpio1_pos_int_st; + u32 pmu_gpio1_net_int_st; + u32 pmu_pwrdn_inten; + u32 pmu_pwrdn_status; + u32 pmu_wakeup_status; + u32 pmu_bus_clr; + u32 pmu_bus_idle_req; + u32 pmu_bus_idle_st; + u32 pmu_bus_idle_ack; + u32 pmu_cci500_con; + u32 pmu_adb400_con; + u32 pmu_adb400_st; + u32 pmu_power_st; + u32 pmu_core_pwr_st; + u32 pmu_osc_cnt; + u32 pmu_plllock_cnt; + u32 pmu_pllrst_cnt; + u32 pmu_stable_cnt; + u32 pmu_ddrio_pwron_cnt; + u32 pmu_wakeup_rst_clr_cnt; + u32 pmu_ddr_sref_st; + u32 pmu_scu_l_pwrdn_cnt; + u32 pmu_scu_l_pwrup_cnt; + u32 pmu_scu_b_pwrdn_cnt; + u32 pmu_scu_b_pwrup_cnt; + u32 pmu_gpu_pwrdn_cnt; + u32 pmu_gpu_pwrup_cnt; + u32 pmu_center_pwrdn_cnt; + u32 pmu_center_pwrup_cnt; + u32 pmu_timeout_cnt; + u32 pmu_cpu0apm_con; + u32 pmu_cpu1apm_con; + u32 pmu_cpu2apm_con; + u32 pmu_cpu3apm_con; + u32 pmu_cpu0bpm_con; + u32 pmu_cpu1bpm_con; + u32 pmu_noc_auto_ena; + u32 pmu_pwrdn_con1; + u32 reserved0[0x4]; + u32 pmu_sys_reg_reg0; + u32 pmu_sys_reg_reg1; + u32 pmu_sys_reg_reg2; + u32 pmu_sys_reg_reg3; +}; + +check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); + +#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */ From 845a31ea2c424e4c85108fe567bb39a10a6aaafc Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:33 +0530 Subject: [PATCH 078/147] rockchip: rk3399: syscon: Add pmu support Add pmu compatible with relevant U_BOOT_DRIVER for rk3399 via syscon rk3399 driver. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index a8bb5b11e56..259ca44d68f 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -13,6 +13,7 @@ static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, { .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF }, { .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC }, + { .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU }, { } }; @@ -58,4 +59,11 @@ U_BOOT_DRIVER(rockchip_rk3399_cic) = { .of_match = rk3399_syscon_ids + 3, .bind = rk3399_syscon_bind_of_platdata, }; + +U_BOOT_DRIVER(rockchip_rk3399_pmu) = { + .name = "rockchip_rk3399_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3399_syscon_ids + 4, + .bind = rk3399_syscon_bind_of_platdata, +}; #endif From ab0ce36a169dfc497733a530e15007e72ef286f5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:34 +0530 Subject: [PATCH 079/147] rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi so-that SPL can access pmu. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index fcfce9ae021..2738a3889ef 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -3,6 +3,10 @@ * Copyright (C) 2019 Jagan Teki */ +&pmu { + u-boot,dm-pre-reloc; +}; + &sdmmc { u-boot,dm-pre-reloc; }; From 09565686372c8113f67662bbe0376d90c5796a1b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:35 +0530 Subject: [PATCH 080/147] clk: rockchip: rk3399: Set 50MHz ddr clock Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 69a887f70cf..2c001661e1e 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ switch (set_rate) { + case 50 * MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2}; + break; case 200 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; From f556d75aeda352d10d8b502056d5e22c79b063f0 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:36 +0530 Subject: [PATCH 081/147] clk: rockchip: rk3399: Set 400MHz ddr clock Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 2c001661e1e..d9950c159bd 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; break; + case 400 * MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; + break; case 666 * MHz: dpll_cfg = (struct pll_div) {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; From 4f3cc17d380559b9b2da87040e9d6f29bb33dbc3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:37 +0530 Subject: [PATCH 082/147] ram: rk3399: Add LPPDDR4-400 timings inc LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 +++++++++++++++++ 1 file changed, 1570 insertions(+) create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc new file mode 100644 index 00000000000..c50a03d9dd2 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc @@ -0,0 +1,1570 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + * (C) Copyright 2019 Amarula Solutions + */ + +{ + { + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = 0x80241d22, + .ddrtimingb0 = 0x15050f08, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = 0x00002122, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + }, + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = 0x80241d22, + .ddrtimingb0 = 0x15050f08, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = 0x00002122, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + } + }, + { + .ddr_freq = 400 * MHz, + .dramtype = LPDDR4, + .num_channels = 2, + .stride = 13, + .odt = 1, + }, + { + { + 0x00000b00, /* DENALI_CTL_00_DATA */ + 0x00000000, /* DENALI_CTL_01_DATA */ + 0x00000000, /* DENALI_CTL_02_DATA */ + 0x00000000, /* DENALI_CTL_03_DATA */ + 0x00000000, /* DENALI_CTL_04_DATA */ + 0x00013880, /* DENALI_CTL_05_DATA */ + 0x000c3500, /* DENALI_CTL_06_DATA */ + 0x00000005, /* DENALI_CTL_07_DATA */ + 0x00000320, /* DENALI_CTL_08_DATA */ + 0x00027100, /* DENALI_CTL_09_DATA */ + 0x00186a00, /* DENALI_CTL_10_DATA */ + 0x00000005, /* DENALI_CTL_11_DATA */ + 0x00000640, /* DENALI_CTL_12_DATA */ + 0x00002710, /* DENALI_CTL_13_DATA */ + 0x000186a0, /* DENALI_CTL_14_DATA */ + 0x00000005, /* DENALI_CTL_15_DATA */ + 0x01000064, /* DENALI_CTL_16_DATA */ + 0x00000000, /* DENALI_CTL_17_DATA */ + 0x02020101, /* DENALI_CTL_18_DATA */ + 0x00000102, /* DENALI_CTL_19_DATA */ + 0x00000050, /* DENALI_CTL_20_DATA */ + 0x000000c8, /* DENALI_CTL_21_DATA */ + 0x00000000, /* DENALI_CTL_22_DATA */ + 0x06140000, /* DENALI_CTL_23_DATA */ + 0x00081c00, /* DENALI_CTL_24_DATA */ + 0x0400040c, /* DENALI_CTL_25_DATA */ + 0x19042008, /* DENALI_CTL_26_DATA */ + 0x10080a11, /* DENALI_CTL_27_DATA */ + 0x22310800, /* DENALI_CTL_28_DATA */ + 0x00200f0a, /* DENALI_CTL_29_DATA */ + 0x0a030704, /* DENALI_CTL_30_DATA */ + 0x08000204, /* DENALI_CTL_31_DATA */ + 0x00000a0a, /* DENALI_CTL_32_DATA */ + 0x04006db0, /* DENALI_CTL_33_DATA */ + 0x0a0a0804, /* DENALI_CTL_34_DATA */ + 0x0600db60, /* DENALI_CTL_35_DATA */ + 0x0a0a0806, /* DENALI_CTL_36_DATA */ + 0x04000db6, /* DENALI_CTL_37_DATA */ + 0x02030404, /* DENALI_CTL_38_DATA */ + 0x0f0a0800, /* DENALI_CTL_39_DATA */ + 0x08040411, /* DENALI_CTL_40_DATA */ + 0x1400640a, /* DENALI_CTL_41_DATA */ + 0x02010a0a, /* DENALI_CTL_42_DATA */ + 0x00010001, /* DENALI_CTL_43_DATA */ + 0x04082012, /* DENALI_CTL_44_DATA */ + 0x00041109, /* DENALI_CTL_45_DATA */ + 0x00000000, /* DENALI_CTL_46_DATA */ + 0x03010000, /* DENALI_CTL_47_DATA */ + 0x06100034, /* DENALI_CTL_48_DATA */ + 0x0c280068, /* DENALI_CTL_49_DATA */ + 0x00bb0007, /* DENALI_CTL_50_DATA */ + 0x00000000, /* DENALI_CTL_51_DATA */ + 0x00060003, /* DENALI_CTL_52_DATA */ + 0x000a0003, /* DENALI_CTL_53_DATA */ + 0x000a0014, /* DENALI_CTL_54_DATA */ + 0x01000000, /* DENALI_CTL_55_DATA */ + 0x030a0000, /* DENALI_CTL_56_DATA */ + 0x0c000002, /* DENALI_CTL_57_DATA */ + 0x00000103, /* DENALI_CTL_58_DATA */ + 0x0003030a, /* DENALI_CTL_59_DATA */ + 0x00060037, /* DENALI_CTL_60_DATA */ + 0x0003006e, /* DENALI_CTL_61_DATA */ + 0x05050007, /* DENALI_CTL_62_DATA */ + 0x03020605, /* DENALI_CTL_63_DATA */ + 0x06050301, /* DENALI_CTL_64_DATA */ + 0x06020c05, /* DENALI_CTL_65_DATA */ + 0x05050302, /* DENALI_CTL_66_DATA */ + 0x03020305, /* DENALI_CTL_67_DATA */ + 0x00000301, /* DENALI_CTL_68_DATA */ + 0x00000301, /* DENALI_CTL_69_DATA */ + 0x00000001, /* DENALI_CTL_70_DATA */ + 0x00000000, /* DENALI_CTL_71_DATA */ + 0x00000000, /* DENALI_CTL_72_DATA */ + 0x01000000, /* DENALI_CTL_73_DATA */ + 0x80104002, /* DENALI_CTL_74_DATA */ + 0x00040003, /* DENALI_CTL_75_DATA */ + 0x00040005, /* DENALI_CTL_76_DATA */ + 0x00030000, /* DENALI_CTL_77_DATA */ + 0x00050004, /* DENALI_CTL_78_DATA */ + 0x00000004, /* DENALI_CTL_79_DATA */ + 0x00040003, /* DENALI_CTL_80_DATA */ + 0x00040005, /* DENALI_CTL_81_DATA */ + 0x18400000, /* DENALI_CTL_82_DATA */ + 0x00000c20, /* DENALI_CTL_83_DATA */ + 0x185030a0, /* DENALI_CTL_84_DATA */ + 0x02ec0000, /* DENALI_CTL_85_DATA */ + 0x00000176, /* DENALI_CTL_86_DATA */ + 0x00000000, /* DENALI_CTL_87_DATA */ + 0x00000000, /* DENALI_CTL_88_DATA */ + 0x00000000, /* DENALI_CTL_89_DATA */ + 0x00000000, /* DENALI_CTL_90_DATA */ + 0x00000000, /* DENALI_CTL_91_DATA */ + 0x06030300, /* DENALI_CTL_92_DATA */ + 0x00030303, /* DENALI_CTL_93_DATA */ + 0x02030200, /* DENALI_CTL_94_DATA */ + 0x00040703, /* DENALI_CTL_95_DATA */ + 0x03020302, /* DENALI_CTL_96_DATA */ + 0x02000407, /* DENALI_CTL_97_DATA */ + 0x07030203, /* DENALI_CTL_98_DATA */ + 0x00030f04, /* DENALI_CTL_99_DATA */ + 0x00070004, /* DENALI_CTL_100_DATA */ + 0x00000000, /* DENALI_CTL_101_DATA */ + 0x00000000, /* DENALI_CTL_102_DATA */ + 0x00000000, /* DENALI_CTL_103_DATA */ + 0x00000000, /* DENALI_CTL_104_DATA */ + 0x00000000, /* DENALI_CTL_105_DATA */ + 0x00000000, /* DENALI_CTL_106_DATA */ + 0x00000000, /* DENALI_CTL_107_DATA */ + 0x00010000, /* DENALI_CTL_108_DATA */ + 0x20040020, /* DENALI_CTL_109_DATA */ + 0x00200400, /* DENALI_CTL_110_DATA */ + 0x01000400, /* DENALI_CTL_111_DATA */ + 0x00000b80, /* DENALI_CTL_112_DATA */ + 0x00000000, /* DENALI_CTL_113_DATA */ + 0x00000001, /* DENALI_CTL_114_DATA */ + 0x00000002, /* DENALI_CTL_115_DATA */ + 0x0000000e, /* DENALI_CTL_116_DATA */ + 0x00000000, /* DENALI_CTL_117_DATA */ + 0x00000000, /* DENALI_CTL_118_DATA */ + 0x00000000, /* DENALI_CTL_119_DATA */ + 0x00000000, /* DENALI_CTL_120_DATA */ + 0x00000000, /* DENALI_CTL_121_DATA */ + 0x00500000, /* DENALI_CTL_122_DATA */ + 0x00640028, /* DENALI_CTL_123_DATA */ + 0x00640404, /* DENALI_CTL_124_DATA */ + 0x005000a0, /* DENALI_CTL_125_DATA */ + 0x060600c8, /* DENALI_CTL_126_DATA */ + 0x000a00c8, /* DENALI_CTL_127_DATA */ + 0x000d0005, /* DENALI_CTL_128_DATA */ + 0x000d0404, /* DENALI_CTL_129_DATA */ + 0x00000000, /* DENALI_CTL_130_DATA */ + 0x00000000, /* DENALI_CTL_131_DATA */ + 0x00000000, /* DENALI_CTL_132_DATA */ + 0x001400a3, /* DENALI_CTL_133_DATA */ + 0x00e30009, /* DENALI_CTL_134_DATA */ + 0x00120024, /* DENALI_CTL_135_DATA */ + 0x00040063, /* DENALI_CTL_136_DATA */ + 0x00000000, /* DENALI_CTL_137_DATA */ + 0x00310031, /* DENALI_CTL_138_DATA */ + 0x00000031, /* DENALI_CTL_139_DATA */ + 0x004d0000, /* DENALI_CTL_140_DATA */ + 0x004d004d, /* DENALI_CTL_141_DATA */ + 0x004d0000, /* DENALI_CTL_142_DATA */ + 0x004d004d, /* DENALI_CTL_143_DATA */ + 0x00010101, /* DENALI_CTL_144_DATA */ + 0x00000000, /* DENALI_CTL_145_DATA */ + 0x00000000, /* DENALI_CTL_146_DATA */ + 0x001400a3, /* DENALI_CTL_147_DATA */ + 0x00e30009, /* DENALI_CTL_148_DATA */ + 0x00120024, /* DENALI_CTL_149_DATA */ + 0x00040063, /* DENALI_CTL_150_DATA */ + 0x00000000, /* DENALI_CTL_151_DATA */ + 0x00310031, /* DENALI_CTL_152_DATA */ + 0x00000031, /* DENALI_CTL_153_DATA */ + 0x004d0000, /* DENALI_CTL_154_DATA */ + 0x004d004d, /* DENALI_CTL_155_DATA */ + 0x004d0000, /* DENALI_CTL_156_DATA */ + 0x004d004d, /* DENALI_CTL_157_DATA */ + 0x00010101, /* DENALI_CTL_158_DATA */ + 0x00000000, /* DENALI_CTL_159_DATA */ + 0x00000000, /* DENALI_CTL_160_DATA */ + 0x00000000, /* DENALI_CTL_161_DATA */ + 0x00000001, /* DENALI_CTL_162_DATA */ + 0x00000000, /* DENALI_CTL_163_DATA */ + 0x18151100, /* DENALI_CTL_164_DATA */ + 0x0000000c, /* DENALI_CTL_165_DATA */ + 0x00000000, /* DENALI_CTL_166_DATA */ + 0x00000000, /* DENALI_CTL_167_DATA */ + 0x00000000, /* DENALI_CTL_168_DATA */ + 0x00000000, /* DENALI_CTL_169_DATA */ + 0x00000000, /* DENALI_CTL_170_DATA */ + 0x00000000, /* DENALI_CTL_171_DATA */ + 0x00000000, /* DENALI_CTL_172_DATA */ + 0x00000000, /* DENALI_CTL_173_DATA */ + 0x00000000, /* DENALI_CTL_174_DATA */ + 0x00000000, /* DENALI_CTL_175_DATA */ + 0x00000000, /* DENALI_CTL_176_DATA */ + 0x00000000, /* DENALI_CTL_177_DATA */ + 0x00000000, /* DENALI_CTL_178_DATA */ + 0x00020003, /* DENALI_CTL_179_DATA */ + 0x00400100, /* DENALI_CTL_180_DATA */ + 0x000c0190, /* DENALI_CTL_181_DATA */ + 0x01000200, /* DENALI_CTL_182_DATA */ + 0x03200040, /* DENALI_CTL_183_DATA */ + 0x00020018, /* DENALI_CTL_184_DATA */ + 0x00400100, /* DENALI_CTL_185_DATA */ + 0x00080032, /* DENALI_CTL_186_DATA */ + 0x00140000, /* DENALI_CTL_187_DATA */ + 0x00030028, /* DENALI_CTL_188_DATA */ + 0x01010100, /* DENALI_CTL_189_DATA */ + 0x02000202, /* DENALI_CTL_190_DATA */ + 0x0b000002, /* DENALI_CTL_191_DATA */ + 0x01000f0f, /* DENALI_CTL_192_DATA */ + 0x00000000, /* DENALI_CTL_193_DATA */ + 0x00000000, /* DENALI_CTL_194_DATA */ + 0x00010003, /* DENALI_CTL_195_DATA */ + 0x00000c03, /* DENALI_CTL_196_DATA */ + 0x00040101, /* DENALI_CTL_197_DATA */ + 0x04010100, /* DENALI_CTL_198_DATA */ + 0x01000000, /* DENALI_CTL_199_DATA */ + 0x02010000, /* DENALI_CTL_200_DATA */ + 0x00000001, /* DENALI_CTL_201_DATA */ + 0x00000000, /* DENALI_CTL_202_DATA */ + 0x00000000, /* DENALI_CTL_203_DATA */ + 0x00000000, /* DENALI_CTL_204_DATA */ + 0x00000000, /* DENALI_CTL_205_DATA */ + 0x00000000, /* DENALI_CTL_206_DATA */ + 0x00000000, /* DENALI_CTL_207_DATA */ + 0x00000000, /* DENALI_CTL_208_DATA */ + 0x00000000, /* DENALI_CTL_209_DATA */ + 0x00000000, /* DENALI_CTL_210_DATA */ + 0x00010000, /* DENALI_CTL_211_DATA */ + 0x00000001, /* DENALI_CTL_212_DATA */ + 0x01010001, /* DENALI_CTL_213_DATA */ + 0x05040001, /* DENALI_CTL_214_DATA */ + 0x040a0703, /* DENALI_CTL_215_DATA */ + 0x02080808, /* DENALI_CTL_216_DATA */ + 0x020e000a, /* DENALI_CTL_217_DATA */ + 0x020f010b, /* DENALI_CTL_218_DATA */ + 0x000d0008, /* DENALI_CTL_219_DATA */ + 0x00080b0a, /* DENALI_CTL_220_DATA */ + 0x03000200, /* DENALI_CTL_221_DATA */ + 0x00000100, /* DENALI_CTL_222_DATA */ + 0x00000000, /* DENALI_CTL_223_DATA */ + 0x00000000, /* DENALI_CTL_224_DATA */ + 0x0d000001, /* DENALI_CTL_225_DATA */ + 0x00000028, /* DENALI_CTL_226_DATA */ + 0x00010000, /* DENALI_CTL_227_DATA */ + 0x00000003, /* DENALI_CTL_228_DATA */ + 0x00000000, /* DENALI_CTL_229_DATA */ + 0x00000000, /* DENALI_CTL_230_DATA */ + 0x00000000, /* DENALI_CTL_231_DATA */ + 0x00000000, /* DENALI_CTL_232_DATA */ + 0x00000000, /* DENALI_CTL_233_DATA */ + 0x00000000, /* DENALI_CTL_234_DATA */ + 0x00000000, /* DENALI_CTL_235_DATA */ + 0x00000000, /* DENALI_CTL_236_DATA */ + 0x00010100, /* DENALI_CTL_237_DATA */ + 0x01000000, /* DENALI_CTL_238_DATA */ + 0x00000001, /* DENALI_CTL_239_DATA */ + 0x00000303, /* DENALI_CTL_240_DATA */ + 0x00000000, /* DENALI_CTL_241_DATA */ + 0x00000000, /* DENALI_CTL_242_DATA */ + 0x00000000, /* DENALI_CTL_243_DATA */ + 0x00000000, /* DENALI_CTL_244_DATA */ + 0x00000000, /* DENALI_CTL_245_DATA */ + 0x00000000, /* DENALI_CTL_246_DATA */ + 0x00000000, /* DENALI_CTL_247_DATA */ + 0x00000000, /* DENALI_CTL_248_DATA */ + 0x00000000, /* DENALI_CTL_249_DATA */ + 0x00000000, /* DENALI_CTL_250_DATA */ + 0x00000000, /* DENALI_CTL_251_DATA */ + 0x00000000, /* DENALI_CTL_252_DATA */ + 0x00000000, /* DENALI_CTL_253_DATA */ + 0x00000000, /* DENALI_CTL_254_DATA */ + 0x00000000, /* DENALI_CTL_255_DATA */ + 0x000556aa, /* DENALI_CTL_256_DATA */ + 0x000aaaaa, /* DENALI_CTL_257_DATA */ + 0x000aa955, /* DENALI_CTL_258_DATA */ + 0x00055555, /* DENALI_CTL_259_DATA */ + 0x000b3133, /* DENALI_CTL_260_DATA */ + 0x0004cd33, /* DENALI_CTL_261_DATA */ + 0x0004cecc, /* DENALI_CTL_262_DATA */ + 0x000b32cc, /* DENALI_CTL_263_DATA */ + 0x00010300, /* DENALI_CTL_264_DATA */ + 0x03000100, /* DENALI_CTL_265_DATA */ + 0x00000000, /* DENALI_CTL_266_DATA */ + 0x00000000, /* DENALI_CTL_267_DATA */ + 0x00000000, /* DENALI_CTL_268_DATA */ + 0x00000000, /* DENALI_CTL_269_DATA */ + 0x00000000, /* DENALI_CTL_270_DATA */ + 0x00000000, /* DENALI_CTL_271_DATA */ + 0x00000000, /* DENALI_CTL_272_DATA */ + 0x00000000, /* DENALI_CTL_273_DATA */ + 0x00ffff00, /* DENALI_CTL_274_DATA */ + 0x1a160000, /* DENALI_CTL_275_DATA */ + 0x08000012, /* DENALI_CTL_276_DATA */ + 0x00000c20, /* DENALI_CTL_277_DATA */ + 0x00000200, /* DENALI_CTL_278_DATA */ + 0x00000200, /* DENALI_CTL_279_DATA */ + 0x00000200, /* DENALI_CTL_280_DATA */ + 0x00000200, /* DENALI_CTL_281_DATA */ + 0x00000c20, /* DENALI_CTL_282_DATA */ + 0x00007940, /* DENALI_CTL_283_DATA */ + 0x18500409, /* DENALI_CTL_284_DATA */ + 0x00000200, /* DENALI_CTL_285_DATA */ + 0x00000200, /* DENALI_CTL_286_DATA */ + 0x00000200, /* DENALI_CTL_287_DATA */ + 0x00000200, /* DENALI_CTL_288_DATA */ + 0x00001850, /* DENALI_CTL_289_DATA */ + 0x0000f320, /* DENALI_CTL_290_DATA */ + 0x0176060c, /* DENALI_CTL_291_DATA */ + 0x00000200, /* DENALI_CTL_292_DATA */ + 0x00000200, /* DENALI_CTL_293_DATA */ + 0x00000200, /* DENALI_CTL_294_DATA */ + 0x00000200, /* DENALI_CTL_295_DATA */ + 0x00000176, /* DENALI_CTL_296_DATA */ + 0x00000e9c, /* DENALI_CTL_297_DATA */ + 0x02020205, /* DENALI_CTL_298_DATA */ + 0x03030202, /* DENALI_CTL_299_DATA */ + 0x00000018, /* DENALI_CTL_300_DATA */ + 0x00000000, /* DENALI_CTL_301_DATA */ + 0x00000000, /* DENALI_CTL_302_DATA */ + 0x00001403, /* DENALI_CTL_303_DATA */ + 0x00000000, /* DENALI_CTL_304_DATA */ + 0x00000000, /* DENALI_CTL_305_DATA */ + 0x00000000, /* DENALI_CTL_306_DATA */ + 0x00030000, /* DENALI_CTL_307_DATA */ + 0x000a001c, /* DENALI_CTL_308_DATA */ + 0x000e0020, /* DENALI_CTL_309_DATA */ + 0x00060018, /* DENALI_CTL_310_DATA */ + 0x00000000, /* DENALI_CTL_311_DATA */ + 0x00000000, /* DENALI_CTL_312_DATA */ + 0x02000000, /* DENALI_CTL_313_DATA */ + 0x00090305, /* DENALI_CTL_314_DATA */ + 0x00050101, /* DENALI_CTL_315_DATA */ + 0x00000000, /* DENALI_CTL_316_DATA */ + 0x00000000, /* DENALI_CTL_317_DATA */ + 0x00000000, /* DENALI_CTL_318_DATA */ + 0x00000000, /* DENALI_CTL_319_DATA */ + 0x00000000, /* DENALI_CTL_320_DATA */ + 0x00000000, /* DENALI_CTL_321_DATA */ + 0x00000000, /* DENALI_CTL_322_DATA */ + 0x00000000, /* DENALI_CTL_323_DATA */ + 0x01000001, /* DENALI_CTL_324_DATA */ + 0x01010101, /* DENALI_CTL_325_DATA */ + 0x01000101, /* DENALI_CTL_326_DATA */ + 0x01000100, /* DENALI_CTL_327_DATA */ + 0x00010001, /* DENALI_CTL_328_DATA */ + 0x00010002, /* DENALI_CTL_329_DATA */ + 0x00020100, /* DENALI_CTL_330_DATA */ + 0x00000002 /* DENALI_CTL_331_DATA */ + } + }, + { + { + 0x00000b00, /* DENALI_PI_00_DATA */ + 0x00000000, /* DENALI_PI_01_DATA */ + 0x000002ec, /* DENALI_PI_02_DATA */ + 0x00000176, /* DENALI_PI_03_DATA */ + 0x000030a0, /* DENALI_PI_04_DATA */ + 0x00001850, /* DENALI_PI_05_DATA */ + 0x00001840, /* DENALI_PI_06_DATA */ + 0x01760c20, /* DENALI_PI_07_DATA */ + 0x00000200, /* DENALI_PI_08_DATA */ + 0x00000200, /* DENALI_PI_09_DATA */ + 0x00000200, /* DENALI_PI_10_DATA */ + 0x00000200, /* DENALI_PI_11_DATA */ + 0x00001850, /* DENALI_PI_12_DATA */ + 0x00000200, /* DENALI_PI_13_DATA */ + 0x00000200, /* DENALI_PI_14_DATA */ + 0x00000200, /* DENALI_PI_15_DATA */ + 0x00000200, /* DENALI_PI_16_DATA */ + 0x00000c20, /* DENALI_PI_17_DATA */ + 0x00000200, /* DENALI_PI_18_DATA */ + 0x00000200, /* DENALI_PI_19_DATA */ + 0x00000200, /* DENALI_PI_20_DATA */ + 0x00000200, /* DENALI_PI_21_DATA */ + 0x00010000, /* DENALI_PI_22_DATA */ + 0x00000007, /* DENALI_PI_23_DATA */ + 0x01000001, /* DENALI_PI_24_DATA */ + 0x00000000, /* DENALI_PI_25_DATA */ + 0x3fffffff, /* DENALI_PI_26_DATA */ + 0x00000000, /* DENALI_PI_27_DATA */ + 0x00000000, /* DENALI_PI_28_DATA */ + 0x00000000, /* DENALI_PI_29_DATA */ + 0x00000000, /* DENALI_PI_30_DATA */ + 0x00000000, /* DENALI_PI_31_DATA */ + 0x00000000, /* DENALI_PI_32_DATA */ + 0x00000000, /* DENALI_PI_33_DATA */ + 0x00000000, /* DENALI_PI_34_DATA */ + 0x00000000, /* DENALI_PI_35_DATA */ + 0x00000000, /* DENALI_PI_36_DATA */ + 0x00000000, /* DENALI_PI_37_DATA */ + 0x00000000, /* DENALI_PI_38_DATA */ + 0x00000000, /* DENALI_PI_39_DATA */ + 0x00000000, /* DENALI_PI_40_DATA */ + 0x0f000101, /* DENALI_PI_41_DATA */ + 0x082b3223, /* DENALI_PI_42_DATA */ + 0x080c0004, /* DENALI_PI_43_DATA */ + 0x00061c00, /* DENALI_PI_44_DATA */ + 0x00000214, /* DENALI_PI_45_DATA */ + 0x00bb0007, /* DENALI_PI_46_DATA */ + 0x0c280068, /* DENALI_PI_47_DATA */ + 0x06100034, /* DENALI_PI_48_DATA */ + 0x00000500, /* DENALI_PI_49_DATA */ + 0x00000000, /* DENALI_PI_50_DATA */ + 0x00000000, /* DENALI_PI_51_DATA */ + 0x00000000, /* DENALI_PI_52_DATA */ + 0x00000000, /* DENALI_PI_53_DATA */ + 0x00000000, /* DENALI_PI_54_DATA */ + 0x00000000, /* DENALI_PI_55_DATA */ + 0x00000000, /* DENALI_PI_56_DATA */ + 0x00000000, /* DENALI_PI_57_DATA */ + 0x04040100, /* DENALI_PI_58_DATA */ + 0x0a000004, /* DENALI_PI_59_DATA */ + 0x00000128, /* DENALI_PI_60_DATA */ + 0x00000000, /* DENALI_PI_61_DATA */ + 0x0003000f, /* DENALI_PI_62_DATA */ + 0x00000018, /* DENALI_PI_63_DATA */ + 0x00000000, /* DENALI_PI_64_DATA */ + 0x00000000, /* DENALI_PI_65_DATA */ + 0x00060002, /* DENALI_PI_66_DATA */ + 0x00010001, /* DENALI_PI_67_DATA */ + 0x00000101, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ + 0x00000000, /* DENALI_PI_71_DATA */ + 0x05030000, /* DENALI_PI_72_DATA */ + 0x070a0404, /* DENALI_PI_73_DATA */ + 0x00000000, /* DENALI_PI_74_DATA */ + 0x00000000, /* DENALI_PI_75_DATA */ + 0x00000000, /* DENALI_PI_76_DATA */ + 0x000f0f00, /* DENALI_PI_77_DATA */ + 0x0000001e, /* DENALI_PI_78_DATA */ + 0x00000000, /* DENALI_PI_79_DATA */ + 0x01010300, /* DENALI_PI_80_DATA */ + 0x00000000, /* DENALI_PI_81_DATA */ + 0x00000000, /* DENALI_PI_82_DATA */ + 0x01000000, /* DENALI_PI_83_DATA */ + 0x00000101, /* DENALI_PI_84_DATA */ + 0x55555a5a, /* DENALI_PI_85_DATA */ + 0x55555a5a, /* DENALI_PI_86_DATA */ + 0x55555a5a, /* DENALI_PI_87_DATA */ + 0x55555a5a, /* DENALI_PI_88_DATA */ + 0x0c050001, /* DENALI_PI_89_DATA */ + 0x06020009, /* DENALI_PI_90_DATA */ + 0x00010004, /* DENALI_PI_91_DATA */ + 0x00000203, /* DENALI_PI_92_DATA */ + 0x00030000, /* DENALI_PI_93_DATA */ + 0x170f0000, /* DENALI_PI_94_DATA */ + 0x00060018, /* DENALI_PI_95_DATA */ + 0x000e0020, /* DENALI_PI_96_DATA */ + 0x000a001c, /* DENALI_PI_97_DATA */ + 0x00000000, /* DENALI_PI_98_DATA */ + 0x00000000, /* DENALI_PI_99_DATA */ + 0x00000100, /* DENALI_PI_100_DATA */ + 0x140a0000, /* DENALI_PI_101_DATA */ + 0x000d010a, /* DENALI_PI_102_DATA */ + 0x0100c802, /* DENALI_PI_103_DATA */ + 0x010a0064, /* DENALI_PI_104_DATA */ + 0x000e0100, /* DENALI_PI_105_DATA */ + 0x0100000e, /* DENALI_PI_106_DATA */ + 0x00c900c9, /* DENALI_PI_107_DATA */ + 0x00650100, /* DENALI_PI_108_DATA */ + 0x1e1a0065, /* DENALI_PI_109_DATA */ + 0x10010204, /* DENALI_PI_110_DATA */ + 0x06070605, /* DENALI_PI_111_DATA */ + 0x20000202, /* DENALI_PI_112_DATA */ + 0x00201000, /* DENALI_PI_113_DATA */ + 0x00201000, /* DENALI_PI_114_DATA */ + 0x04041000, /* DENALI_PI_115_DATA */ + 0x10020100, /* DENALI_PI_116_DATA */ + 0x0003010c, /* DENALI_PI_117_DATA */ + 0x004b004a, /* DENALI_PI_118_DATA */ + 0x1a0f0000, /* DENALI_PI_119_DATA */ + 0x0102041e, /* DENALI_PI_120_DATA */ + 0x34000000, /* DENALI_PI_121_DATA */ + 0x00000000, /* DENALI_PI_122_DATA */ + 0x00000000, /* DENALI_PI_123_DATA */ + 0x00010000, /* DENALI_PI_124_DATA */ + 0x00000400, /* DENALI_PI_125_DATA */ + 0x00310000, /* DENALI_PI_126_DATA */ + 0x004d4d00, /* DENALI_PI_127_DATA */ + 0x00120024, /* DENALI_PI_128_DATA */ + 0x4d000031, /* DENALI_PI_129_DATA */ + 0x0000144d, /* DENALI_PI_130_DATA */ + 0x00310009, /* DENALI_PI_131_DATA */ + 0x004d4d00, /* DENALI_PI_132_DATA */ + 0x00000004, /* DENALI_PI_133_DATA */ + 0x4d000031, /* DENALI_PI_134_DATA */ + 0x0000244d, /* DENALI_PI_135_DATA */ + 0x00310012, /* DENALI_PI_136_DATA */ + 0x004d4d00, /* DENALI_PI_137_DATA */ + 0x00090014, /* DENALI_PI_138_DATA */ + 0x4d000031, /* DENALI_PI_139_DATA */ + 0x0004004d, /* DENALI_PI_140_DATA */ + 0x00310000, /* DENALI_PI_141_DATA */ + 0x004d4d00, /* DENALI_PI_142_DATA */ + 0x00120024, /* DENALI_PI_143_DATA */ + 0x4d000031, /* DENALI_PI_144_DATA */ + 0x0000144d, /* DENALI_PI_145_DATA */ + 0x00310009, /* DENALI_PI_146_DATA */ + 0x004d4d00, /* DENALI_PI_147_DATA */ + 0x00000004, /* DENALI_PI_148_DATA */ + 0x4d000031, /* DENALI_PI_149_DATA */ + 0x0000244d, /* DENALI_PI_150_DATA */ + 0x00310012, /* DENALI_PI_151_DATA */ + 0x004d4d00, /* DENALI_PI_152_DATA */ + 0x00090014, /* DENALI_PI_153_DATA */ + 0x4d000031, /* DENALI_PI_154_DATA */ + 0x0200004d, /* DENALI_PI_155_DATA */ + 0x00c8000d, /* DENALI_PI_156_DATA */ + 0x08080064, /* DENALI_PI_157_DATA */ + 0x040a0404, /* DENALI_PI_158_DATA */ + 0x03000d92, /* DENALI_PI_159_DATA */ + 0x010a2001, /* DENALI_PI_160_DATA */ + 0x0f11080a, /* DENALI_PI_161_DATA */ + 0x0000110a, /* DENALI_PI_162_DATA */ + 0x2200d92e, /* DENALI_PI_163_DATA */ + 0x080c2003, /* DENALI_PI_164_DATA */ + 0x0809080a, /* DENALI_PI_165_DATA */ + 0x00000a0a, /* DENALI_PI_166_DATA */ + 0x11006c97, /* DENALI_PI_167_DATA */ + 0x040a2002, /* DENALI_PI_168_DATA */ + 0x0200020a, /* DENALI_PI_169_DATA */ + 0x02000200, /* DENALI_PI_170_DATA */ + 0x02000200, /* DENALI_PI_171_DATA */ + 0x02000200, /* DENALI_PI_172_DATA */ + 0x02000200, /* DENALI_PI_173_DATA */ + 0x00000000, /* DENALI_PI_174_DATA */ + 0x00000000, /* DENALI_PI_175_DATA */ + 0x00000000, /* DENALI_PI_176_DATA */ + 0x00000000, /* DENALI_PI_177_DATA */ + 0x00000000, /* DENALI_PI_178_DATA */ + 0x00000000, /* DENALI_PI_179_DATA */ + 0x00000000, /* DENALI_PI_180_DATA */ + 0x00000000, /* DENALI_PI_181_DATA */ + 0x00000000, /* DENALI_PI_182_DATA */ + 0x00000000, /* DENALI_PI_183_DATA */ + 0x00000000, /* DENALI_PI_184_DATA */ + 0x00000000, /* DENALI_PI_185_DATA */ + 0x01000400, /* DENALI_PI_186_DATA */ + 0x00017600, /* DENALI_PI_187_DATA */ + 0x00000e9c, /* DENALI_PI_188_DATA */ + 0x00001850, /* DENALI_PI_189_DATA */ + 0x0000f320, /* DENALI_PI_190_DATA */ + 0x00000c20, /* DENALI_PI_191_DATA */ + 0x00007940, /* DENALI_PI_192_DATA */ + 0x08000000, /* DENALI_PI_193_DATA */ + 0x00000100, /* DENALI_PI_194_DATA */ + 0x00000000, /* DENALI_PI_195_DATA */ + 0x00000000, /* DENALI_PI_196_DATA */ + 0x00000000, /* DENALI_PI_197_DATA */ + 0x00000000, /* DENALI_PI_198_DATA */ + 0x00000002 /* DENALI_PI_199_DATA */ + } + }, + { + { + 0x76543210, /* DENALI_PHY_00_DATA */ + 0x0004f008, /* DENALI_PHY_01_DATA */ + 0x00020119, /* DENALI_PHY_02_DATA */ + 0x00000000, /* DENALI_PHY_03_DATA */ + 0x00000000, /* DENALI_PHY_04_DATA */ + 0x00010000, /* DENALI_PHY_05_DATA */ + 0x01665555, /* DENALI_PHY_06_DATA */ + 0x03665555, /* DENALI_PHY_07_DATA */ + 0x00010f00, /* DENALI_PHY_08_DATA */ + 0x04000100, /* DENALI_PHY_09_DATA */ + 0x00000001, /* DENALI_PHY_10_DATA */ + 0x00170180, /* DENALI_PHY_11_DATA */ + 0x00cc0201, /* DENALI_PHY_12_DATA */ + 0x00030066, /* DENALI_PHY_13_DATA */ + 0x00000000, /* DENALI_PHY_14_DATA */ + 0x00000000, /* DENALI_PHY_15_DATA */ + 0x00000000, /* DENALI_PHY_16_DATA */ + 0x00000000, /* DENALI_PHY_17_DATA */ + 0x00000000, /* DENALI_PHY_18_DATA */ + 0x00000000, /* DENALI_PHY_19_DATA */ + 0x00000000, /* DENALI_PHY_20_DATA */ + 0x00000000, /* DENALI_PHY_21_DATA */ + 0x04080000, /* DENALI_PHY_22_DATA */ + 0x04080400, /* DENALI_PHY_23_DATA */ + 0x30000000, /* DENALI_PHY_24_DATA */ + 0x0c00c007, /* DENALI_PHY_25_DATA */ + 0x00000100, /* DENALI_PHY_26_DATA */ + 0x00000000, /* DENALI_PHY_27_DATA */ + 0xfd02fe01, /* DENALI_PHY_28_DATA */ + 0xf708fb04, /* DENALI_PHY_29_DATA */ + 0xdf20ef10, /* DENALI_PHY_30_DATA */ + 0x7f80bf40, /* DENALI_PHY_31_DATA */ + 0x0001aaaa, /* DENALI_PHY_32_DATA */ + 0x00000000, /* DENALI_PHY_33_DATA */ + 0x00000000, /* DENALI_PHY_34_DATA */ + 0x00000000, /* DENALI_PHY_35_DATA */ + 0x00000000, /* DENALI_PHY_36_DATA */ + 0x00000000, /* DENALI_PHY_37_DATA */ + 0x00000000, /* DENALI_PHY_38_DATA */ + 0x00000000, /* DENALI_PHY_39_DATA */ + 0x00000000, /* DENALI_PHY_40_DATA */ + 0x00000000, /* DENALI_PHY_41_DATA */ + 0x00000000, /* DENALI_PHY_42_DATA */ + 0x00000000, /* DENALI_PHY_43_DATA */ + 0x00000000, /* DENALI_PHY_44_DATA */ + 0x00000000, /* DENALI_PHY_45_DATA */ + 0x00000000, /* DENALI_PHY_46_DATA */ + 0x00000000, /* DENALI_PHY_47_DATA */ + 0x00000000, /* DENALI_PHY_48_DATA */ + 0x00000000, /* DENALI_PHY_49_DATA */ + 0x00000000, /* DENALI_PHY_50_DATA */ + 0x00000000, /* DENALI_PHY_51_DATA */ + 0x00200000, /* DENALI_PHY_52_DATA */ + 0x00000000, /* DENALI_PHY_53_DATA */ + 0x00000000, /* DENALI_PHY_54_DATA */ + 0x00000000, /* DENALI_PHY_55_DATA */ + 0x00000000, /* DENALI_PHY_56_DATA */ + 0x00000000, /* DENALI_PHY_57_DATA */ + 0x00000000, /* DENALI_PHY_58_DATA */ + 0x02800280, /* DENALI_PHY_59_DATA */ + 0x02800280, /* DENALI_PHY_60_DATA */ + 0x02800280, /* DENALI_PHY_61_DATA */ + 0x02800280, /* DENALI_PHY_62_DATA */ + 0x00000280, /* DENALI_PHY_63_DATA */ + 0x00000000, /* DENALI_PHY_64_DATA */ + 0x00000000, /* DENALI_PHY_65_DATA */ + 0x00000000, /* DENALI_PHY_66_DATA */ + 0x00000000, /* DENALI_PHY_67_DATA */ + 0x00800000, /* DENALI_PHY_68_DATA */ + 0x00800080, /* DENALI_PHY_69_DATA */ + 0x00800080, /* DENALI_PHY_70_DATA */ + 0x00800080, /* DENALI_PHY_71_DATA */ + 0x00800080, /* DENALI_PHY_72_DATA */ + 0x00800080, /* DENALI_PHY_73_DATA */ + 0x00800080, /* DENALI_PHY_74_DATA */ + 0x00800080, /* DENALI_PHY_75_DATA */ + 0x00800080, /* DENALI_PHY_76_DATA */ + 0x01190080, /* DENALI_PHY_77_DATA */ + 0x00000001, /* DENALI_PHY_78_DATA */ + 0x00000000, /* DENALI_PHY_79_DATA */ + 0x00000000, /* DENALI_PHY_80_DATA */ + 0x00000200, /* DENALI_PHY_81_DATA */ + 0x00000000, /* DENALI_PHY_82_DATA */ + 0x51315152, /* DENALI_PHY_83_DATA */ + 0xc0003150, /* DENALI_PHY_84_DATA */ + 0x010000c0, /* DENALI_PHY_85_DATA */ + 0x00100000, /* DENALI_PHY_86_DATA */ + 0x07044204, /* DENALI_PHY_87_DATA */ + 0x000f0c18, /* DENALI_PHY_88_DATA */ + 0x01000140, /* DENALI_PHY_89_DATA */ + 0x00000c10, /* DENALI_PHY_90_DATA */ + 0x00000000, /* DENALI_PHY_91_DATA */ + 0x00000000, /* DENALI_PHY_92_DATA */ + 0x00000000, /* DENALI_PHY_93_DATA */ + 0x00000000, /* DENALI_PHY_94_DATA */ + 0x00000000, /* DENALI_PHY_95_DATA */ + 0x00000000, /* DENALI_PHY_96_DATA */ + 0x00000000, /* DENALI_PHY_97_DATA */ + 0x00000000, /* DENALI_PHY_98_DATA */ + 0x00000000, /* DENALI_PHY_99_DATA */ + 0x00000000, /* DENALI_PHY_100_DATA */ + 0x00000000, /* DENALI_PHY_101_DATA */ + 0x00000000, /* DENALI_PHY_102_DATA */ + 0x00000000, /* DENALI_PHY_103_DATA */ + 0x00000000, /* DENALI_PHY_104_DATA */ + 0x00000000, /* DENALI_PHY_105_DATA */ + 0x00000000, /* DENALI_PHY_106_DATA */ + 0x00000000, /* DENALI_PHY_107_DATA */ + 0x00000000, /* DENALI_PHY_108_DATA */ + 0x00000000, /* DENALI_PHY_109_DATA */ + 0x00000000, /* DENALI_PHY_110_DATA */ + 0x00000000, /* DENALI_PHY_111_DATA */ + 0x00000000, /* DENALI_PHY_112_DATA */ + 0x00000000, /* DENALI_PHY_113_DATA */ + 0x00000000, /* DENALI_PHY_114_DATA */ + 0x00000000, /* DENALI_PHY_115_DATA */ + 0x00000000, /* DENALI_PHY_116_DATA */ + 0x00000000, /* DENALI_PHY_117_DATA */ + 0x00000000, /* DENALI_PHY_118_DATA */ + 0x00000000, /* DENALI_PHY_119_DATA */ + 0x00000000, /* DENALI_PHY_120_DATA */ + 0x00000000, /* DENALI_PHY_121_DATA */ + 0x00000000, /* DENALI_PHY_122_DATA */ + 0x00000000, /* DENALI_PHY_123_DATA */ + 0x00000000, /* DENALI_PHY_124_DATA */ + 0x00000000, /* DENALI_PHY_125_DATA */ + 0x00000000, /* DENALI_PHY_126_DATA */ + 0x00000000, /* DENALI_PHY_127_DATA */ + 0x76543210, /* DENALI_PHY_128_DATA */ + 0x0004f008, /* DENALI_PHY_129_DATA */ + 0x00020119, /* DENALI_PHY_130_DATA */ + 0x00000000, /* DENALI_PHY_131_DATA */ + 0x00000000, /* DENALI_PHY_132_DATA */ + 0x00010000, /* DENALI_PHY_133_DATA */ + 0x01665555, /* DENALI_PHY_134_DATA */ + 0x03665555, /* DENALI_PHY_135_DATA */ + 0x00010f00, /* DENALI_PHY_136_DATA */ + 0x04000100, /* DENALI_PHY_137_DATA */ + 0x00000001, /* DENALI_PHY_138_DATA */ + 0x00170180, /* DENALI_PHY_139_DATA */ + 0x00cc0201, /* DENALI_PHY_140_DATA */ + 0x00030066, /* DENALI_PHY_141_DATA */ + 0x00000000, /* DENALI_PHY_142_DATA */ + 0x00000000, /* DENALI_PHY_143_DATA */ + 0x00000000, /* DENALI_PHY_144_DATA */ + 0x00000000, /* DENALI_PHY_145_DATA */ + 0x00000000, /* DENALI_PHY_146_DATA */ + 0x00000000, /* DENALI_PHY_147_DATA */ + 0x00000000, /* DENALI_PHY_148_DATA */ + 0x00000000, /* DENALI_PHY_149_DATA */ + 0x04080000, /* DENALI_PHY_150_DATA */ + 0x04080400, /* DENALI_PHY_151_DATA */ + 0x30000000, /* DENALI_PHY_152_DATA */ + 0x0c00c007, /* DENALI_PHY_153_DATA */ + 0x00000100, /* DENALI_PHY_154_DATA */ + 0x00000000, /* DENALI_PHY_155_DATA */ + 0xfd02fe01, /* DENALI_PHY_156_DATA */ + 0xf708fb04, /* DENALI_PHY_157_DATA */ + 0xdf20ef10, /* DENALI_PHY_158_DATA */ + 0x7f80bf40, /* DENALI_PHY_159_DATA */ + 0x0000aaaa, /* DENALI_PHY_160_DATA */ + 0x00000000, /* DENALI_PHY_161_DATA */ + 0x00000000, /* DENALI_PHY_162_DATA */ + 0x00000000, /* DENALI_PHY_163_DATA */ + 0x00000000, /* DENALI_PHY_164_DATA */ + 0x00000000, /* DENALI_PHY_165_DATA */ + 0x00000000, /* DENALI_PHY_166_DATA */ + 0x00000000, /* DENALI_PHY_167_DATA */ + 0x00000000, /* DENALI_PHY_168_DATA */ + 0x00000000, /* DENALI_PHY_169_DATA */ + 0x00000000, /* DENALI_PHY_170_DATA */ + 0x00000000, /* DENALI_PHY_171_DATA */ + 0x00000000, /* DENALI_PHY_172_DATA */ + 0x00000000, /* DENALI_PHY_173_DATA */ + 0x00000000, /* DENALI_PHY_174_DATA */ + 0x00000000, /* DENALI_PHY_175_DATA */ + 0x00000000, /* DENALI_PHY_176_DATA */ + 0x00000000, /* DENALI_PHY_177_DATA */ + 0x00000000, /* DENALI_PHY_178_DATA */ + 0x00000000, /* DENALI_PHY_179_DATA */ + 0x00200000, /* DENALI_PHY_180_DATA */ + 0x00000000, /* DENALI_PHY_181_DATA */ + 0x00000000, /* DENALI_PHY_182_DATA */ + 0x00000000, /* DENALI_PHY_183_DATA */ + 0x00000000, /* DENALI_PHY_184_DATA */ + 0x00000000, /* DENALI_PHY_185_DATA */ + 0x00000000, /* DENALI_PHY_186_DATA */ + 0x02800280, /* DENALI_PHY_187_DATA */ + 0x02800280, /* DENALI_PHY_188_DATA */ + 0x02800280, /* DENALI_PHY_189_DATA */ + 0x02800280, /* DENALI_PHY_190_DATA */ + 0x00000280, /* DENALI_PHY_191_DATA */ + 0x00000000, /* DENALI_PHY_192_DATA */ + 0x00000000, /* DENALI_PHY_193_DATA */ + 0x00000000, /* DENALI_PHY_194_DATA */ + 0x00000000, /* DENALI_PHY_195_DATA */ + 0x00800000, /* DENALI_PHY_196_DATA */ + 0x00800080, /* DENALI_PHY_197_DATA */ + 0x00800080, /* DENALI_PHY_198_DATA */ + 0x00800080, /* DENALI_PHY_199_DATA */ + 0x00800080, /* DENALI_PHY_200_DATA */ + 0x00800080, /* DENALI_PHY_201_DATA */ + 0x00800080, /* DENALI_PHY_202_DATA */ + 0x00800080, /* DENALI_PHY_203_DATA */ + 0x00800080, /* DENALI_PHY_204_DATA */ + 0x01190080, /* DENALI_PHY_205_DATA */ + 0x00000001, /* DENALI_PHY_206_DATA */ + 0x00000000, /* DENALI_PHY_207_DATA */ + 0x00000000, /* DENALI_PHY_208_DATA */ + 0x00000200, /* DENALI_PHY_209_DATA */ + 0x00000000, /* DENALI_PHY_210_DATA */ + 0x51315152, /* DENALI_PHY_211_DATA */ + 0xc0003150, /* DENALI_PHY_212_DATA */ + 0x010000c0, /* DENALI_PHY_213_DATA */ + 0x00100000, /* DENALI_PHY_214_DATA */ + 0x07044204, /* DENALI_PHY_215_DATA */ + 0x000f0c18, /* DENALI_PHY_216_DATA */ + 0x01000140, /* DENALI_PHY_217_DATA */ + 0x00000c10, /* DENALI_PHY_218_DATA */ + 0x00000000, /* DENALI_PHY_219_DATA */ + 0x00000000, /* DENALI_PHY_220_DATA */ + 0x00000000, /* DENALI_PHY_221_DATA */ + 0x00000000, /* DENALI_PHY_222_DATA */ + 0x00000000, /* DENALI_PHY_223_DATA */ + 0x00000000, /* DENALI_PHY_224_DATA */ + 0x00000000, /* DENALI_PHY_225_DATA */ + 0x00000000, /* DENALI_PHY_226_DATA */ + 0x00000000, /* DENALI_PHY_227_DATA */ + 0x00000000, /* DENALI_PHY_228_DATA */ + 0x00000000, /* DENALI_PHY_229_DATA */ + 0x00000000, /* DENALI_PHY_230_DATA */ + 0x00000000, /* DENALI_PHY_231_DATA */ + 0x00000000, /* DENALI_PHY_232_DATA */ + 0x00000000, /* DENALI_PHY_233_DATA */ + 0x00000000, /* DENALI_PHY_234_DATA */ + 0x00000000, /* DENALI_PHY_235_DATA */ + 0x00000000, /* DENALI_PHY_236_DATA */ + 0x00000000, /* DENALI_PHY_237_DATA */ + 0x00000000, /* DENALI_PHY_238_DATA */ + 0x00000000, /* DENALI_PHY_239_DATA */ + 0x00000000, /* DENALI_PHY_240_DATA */ + 0x00000000, /* DENALI_PHY_241_DATA */ + 0x00000000, /* DENALI_PHY_242_DATA */ + 0x00000000, /* DENALI_PHY_243_DATA */ + 0x00000000, /* DENALI_PHY_244_DATA */ + 0x00000000, /* DENALI_PHY_245_DATA */ + 0x00000000, /* DENALI_PHY_246_DATA */ + 0x00000000, /* DENALI_PHY_247_DATA */ + 0x00000000, /* DENALI_PHY_248_DATA */ + 0x00000000, /* DENALI_PHY_249_DATA */ + 0x00000000, /* DENALI_PHY_250_DATA */ + 0x00000000, /* DENALI_PHY_251_DATA */ + 0x00000000, /* DENALI_PHY_252_DATA */ + 0x00000000, /* DENALI_PHY_253_DATA */ + 0x00000000, /* DENALI_PHY_254_DATA */ + 0x00000000, /* DENALI_PHY_255_DATA */ + 0x76543210, /* DENALI_PHY_256_DATA */ + 0x0004f008, /* DENALI_PHY_257_DATA */ + 0x00020119, /* DENALI_PHY_258_DATA */ + 0x00000000, /* DENALI_PHY_259_DATA */ + 0x00000000, /* DENALI_PHY_260_DATA */ + 0x00010000, /* DENALI_PHY_261_DATA */ + 0x01665555, /* DENALI_PHY_262_DATA */ + 0x03665555, /* DENALI_PHY_263_DATA */ + 0x00010f00, /* DENALI_PHY_264_DATA */ + 0x04000100, /* DENALI_PHY_265_DATA */ + 0x00000001, /* DENALI_PHY_266_DATA */ + 0x00170180, /* DENALI_PHY_267_DATA */ + 0x00cc0201, /* DENALI_PHY_268_DATA */ + 0x00030066, /* DENALI_PHY_269_DATA */ + 0x00000000, /* DENALI_PHY_270_DATA */ + 0x00000000, /* DENALI_PHY_271_DATA */ + 0x00000000, /* DENALI_PHY_272_DATA */ + 0x00000000, /* DENALI_PHY_273_DATA */ + 0x00000000, /* DENALI_PHY_274_DATA */ + 0x00000000, /* DENALI_PHY_275_DATA */ + 0x00000000, /* DENALI_PHY_276_DATA */ + 0x00000000, /* DENALI_PHY_277_DATA */ + 0x04080000, /* DENALI_PHY_278_DATA */ + 0x04080400, /* DENALI_PHY_279_DATA */ + 0x30000000, /* DENALI_PHY_280_DATA */ + 0x0c00c007, /* DENALI_PHY_281_DATA */ + 0x00000100, /* DENALI_PHY_282_DATA */ + 0x00000000, /* DENALI_PHY_283_DATA */ + 0xfd02fe01, /* DENALI_PHY_284_DATA */ + 0xf708fb04, /* DENALI_PHY_285_DATA */ + 0xdf20ef10, /* DENALI_PHY_286_DATA */ + 0x7f80bf40, /* DENALI_PHY_287_DATA */ + 0x0001aaaa, /* DENALI_PHY_288_DATA */ + 0x00000000, /* DENALI_PHY_289_DATA */ + 0x00000000, /* DENALI_PHY_290_DATA */ + 0x00000000, /* DENALI_PHY_291_DATA */ + 0x00000000, /* DENALI_PHY_292_DATA */ + 0x00000000, /* DENALI_PHY_293_DATA */ + 0x00000000, /* DENALI_PHY_294_DATA */ + 0x00000000, /* DENALI_PHY_295_DATA */ + 0x00000000, /* DENALI_PHY_296_DATA */ + 0x00000000, /* DENALI_PHY_297_DATA */ + 0x00000000, /* DENALI_PHY_298_DATA */ + 0x00000000, /* DENALI_PHY_299_DATA */ + 0x00000000, /* DENALI_PHY_300_DATA */ + 0x00000000, /* DENALI_PHY_301_DATA */ + 0x00000000, /* DENALI_PHY_302_DATA */ + 0x00000000, /* DENALI_PHY_303_DATA */ + 0x00000000, /* DENALI_PHY_304_DATA */ + 0x00000000, /* DENALI_PHY_305_DATA */ + 0x00000000, /* DENALI_PHY_306_DATA */ + 0x00000000, /* DENALI_PHY_307_DATA */ + 0x00200000, /* DENALI_PHY_308_DATA */ + 0x00000000, /* DENALI_PHY_309_DATA */ + 0x00000000, /* DENALI_PHY_310_DATA */ + 0x00000000, /* DENALI_PHY_311_DATA */ + 0x00000000, /* DENALI_PHY_312_DATA */ + 0x00000000, /* DENALI_PHY_313_DATA */ + 0x00000000, /* DENALI_PHY_314_DATA */ + 0x02800280, /* DENALI_PHY_315_DATA */ + 0x02800280, /* DENALI_PHY_316_DATA */ + 0x02800280, /* DENALI_PHY_317_DATA */ + 0x02800280, /* DENALI_PHY_318_DATA */ + 0x00000280, /* DENALI_PHY_319_DATA */ + 0x00000000, /* DENALI_PHY_320_DATA */ + 0x00000000, /* DENALI_PHY_321_DATA */ + 0x00000000, /* DENALI_PHY_322_DATA */ + 0x00000000, /* DENALI_PHY_323_DATA */ + 0x00800000, /* DENALI_PHY_324_DATA */ + 0x00800080, /* DENALI_PHY_325_DATA */ + 0x00800080, /* DENALI_PHY_326_DATA */ + 0x00800080, /* DENALI_PHY_327_DATA */ + 0x00800080, /* DENALI_PHY_328_DATA */ + 0x00800080, /* DENALI_PHY_329_DATA */ + 0x00800080, /* DENALI_PHY_330_DATA */ + 0x00800080, /* DENALI_PHY_331_DATA */ + 0x00800080, /* DENALI_PHY_332_DATA */ + 0x01190080, /* DENALI_PHY_333_DATA */ + 0x00000001, /* DENALI_PHY_334_DATA */ + 0x00000000, /* DENALI_PHY_335_DATA */ + 0x00000000, /* DENALI_PHY_336_DATA */ + 0x00000200, /* DENALI_PHY_337_DATA */ + 0x00000000, /* DENALI_PHY_338_DATA */ + 0x51315152, /* DENALI_PHY_339_DATA */ + 0xc0003150, /* DENALI_PHY_340_DATA */ + 0x010000c0, /* DENALI_PHY_341_DATA */ + 0x00100000, /* DENALI_PHY_342_DATA */ + 0x07044204, /* DENALI_PHY_343_DATA */ + 0x000f0c18, /* DENALI_PHY_344_DATA */ + 0x01000140, /* DENALI_PHY_345_DATA */ + 0x00000c10, /* DENALI_PHY_346_DATA */ + 0x00000000, /* DENALI_PHY_347_DATA */ + 0x00000000, /* DENALI_PHY_348_DATA */ + 0x00000000, /* DENALI_PHY_349_DATA */ + 0x00000000, /* DENALI_PHY_350_DATA */ + 0x00000000, /* DENALI_PHY_351_DATA */ + 0x00000000, /* DENALI_PHY_352_DATA */ + 0x00000000, /* DENALI_PHY_353_DATA */ + 0x00000000, /* DENALI_PHY_354_DATA */ + 0x00000000, /* DENALI_PHY_355_DATA */ + 0x00000000, /* DENALI_PHY_356_DATA */ + 0x00000000, /* DENALI_PHY_357_DATA */ + 0x00000000, /* DENALI_PHY_358_DATA */ + 0x00000000, /* DENALI_PHY_359_DATA */ + 0x00000000, /* DENALI_PHY_360_DATA */ + 0x00000000, /* DENALI_PHY_361_DATA */ + 0x00000000, /* DENALI_PHY_362_DATA */ + 0x00000000, /* DENALI_PHY_363_DATA */ + 0x00000000, /* DENALI_PHY_364_DATA */ + 0x00000000, /* DENALI_PHY_365_DATA */ + 0x00000000, /* DENALI_PHY_366_DATA */ + 0x00000000, /* DENALI_PHY_367_DATA */ + 0x00000000, /* DENALI_PHY_368_DATA */ + 0x00000000, /* DENALI_PHY_369_DATA */ + 0x00000000, /* DENALI_PHY_370_DATA */ + 0x00000000, /* DENALI_PHY_371_DATA */ + 0x00000000, /* DENALI_PHY_372_DATA */ + 0x00000000, /* DENALI_PHY_373_DATA */ + 0x00000000, /* DENALI_PHY_374_DATA */ + 0x00000000, /* DENALI_PHY_375_DATA */ + 0x00000000, /* DENALI_PHY_376_DATA */ + 0x00000000, /* DENALI_PHY_377_DATA */ + 0x00000000, /* DENALI_PHY_378_DATA */ + 0x00000000, /* DENALI_PHY_379_DATA */ + 0x00000000, /* DENALI_PHY_380_DATA */ + 0x00000000, /* DENALI_PHY_381_DATA */ + 0x00000000, /* DENALI_PHY_382_DATA */ + 0x00000000, /* DENALI_PHY_383_DATA */ + 0x76543210, /* DENALI_PHY_384_DATA */ + 0x0004f008, /* DENALI_PHY_385_DATA */ + 0x00020119, /* DENALI_PHY_386_DATA */ + 0x00000000, /* DENALI_PHY_387_DATA */ + 0x00000000, /* DENALI_PHY_388_DATA */ + 0x00010000, /* DENALI_PHY_389_DATA */ + 0x01665555, /* DENALI_PHY_390_DATA */ + 0x03665555, /* DENALI_PHY_391_DATA */ + 0x00010f00, /* DENALI_PHY_392_DATA */ + 0x04000100, /* DENALI_PHY_393_DATA */ + 0x00000001, /* DENALI_PHY_394_DATA */ + 0x00170180, /* DENALI_PHY_395_DATA */ + 0x00cc0201, /* DENALI_PHY_396_DATA */ + 0x00030066, /* DENALI_PHY_397_DATA */ + 0x00000000, /* DENALI_PHY_398_DATA */ + 0x00000000, /* DENALI_PHY_399_DATA */ + 0x00000000, /* DENALI_PHY_400_DATA */ + 0x00000000, /* DENALI_PHY_401_DATA */ + 0x00000000, /* DENALI_PHY_402_DATA */ + 0x00000000, /* DENALI_PHY_403_DATA */ + 0x00000000, /* DENALI_PHY_404_DATA */ + 0x00000000, /* DENALI_PHY_405_DATA */ + 0x04080000, /* DENALI_PHY_406_DATA */ + 0x04080400, /* DENALI_PHY_407_DATA */ + 0x30000000, /* DENALI_PHY_408_DATA */ + 0x0c00c007, /* DENALI_PHY_409_DATA */ + 0x00000100, /* DENALI_PHY_410_DATA */ + 0x00000000, /* DENALI_PHY_411_DATA */ + 0xfd02fe01, /* DENALI_PHY_412_DATA */ + 0xf708fb04, /* DENALI_PHY_413_DATA */ + 0xdf20ef10, /* DENALI_PHY_414_DATA */ + 0x7f80bf40, /* DENALI_PHY_415_DATA */ + 0x0000aaaa, /* DENALI_PHY_416_DATA */ + 0x00000000, /* DENALI_PHY_417_DATA */ + 0x00000000, /* DENALI_PHY_418_DATA */ + 0x00000000, /* DENALI_PHY_419_DATA */ + 0x00000000, /* DENALI_PHY_420_DATA */ + 0x00000000, /* DENALI_PHY_421_DATA */ + 0x00000000, /* DENALI_PHY_422_DATA */ + 0x00000000, /* DENALI_PHY_423_DATA */ + 0x00000000, /* DENALI_PHY_424_DATA */ + 0x00000000, /* DENALI_PHY_425_DATA */ + 0x00000000, /* DENALI_PHY_426_DATA */ + 0x00000000, /* DENALI_PHY_427_DATA */ + 0x00000000, /* DENALI_PHY_428_DATA */ + 0x00000000, /* DENALI_PHY_429_DATA */ + 0x00000000, /* DENALI_PHY_430_DATA */ + 0x00000000, /* DENALI_PHY_431_DATA */ + 0x00000000, /* DENALI_PHY_432_DATA */ + 0x00000000, /* DENALI_PHY_433_DATA */ + 0x00000000, /* DENALI_PHY_434_DATA */ + 0x00000000, /* DENALI_PHY_435_DATA */ + 0x00200000, /* DENALI_PHY_436_DATA */ + 0x00000000, /* DENALI_PHY_437_DATA */ + 0x00000000, /* DENALI_PHY_438_DATA */ + 0x00000000, /* DENALI_PHY_439_DATA */ + 0x00000000, /* DENALI_PHY_440_DATA */ + 0x00000000, /* DENALI_PHY_441_DATA */ + 0x00000000, /* DENALI_PHY_442_DATA */ + 0x02800280, /* DENALI_PHY_443_DATA */ + 0x02800280, /* DENALI_PHY_444_DATA */ + 0x02800280, /* DENALI_PHY_445_DATA */ + 0x02800280, /* DENALI_PHY_446_DATA */ + 0x00000280, /* DENALI_PHY_447_DATA */ + 0x00000000, /* DENALI_PHY_448_DATA */ + 0x00000000, /* DENALI_PHY_449_DATA */ + 0x00000000, /* DENALI_PHY_450_DATA */ + 0x00000000, /* DENALI_PHY_451_DATA */ + 0x00800000, /* DENALI_PHY_452_DATA */ + 0x00800080, /* DENALI_PHY_453_DATA */ + 0x00800080, /* DENALI_PHY_454_DATA */ + 0x00800080, /* DENALI_PHY_455_DATA */ + 0x00800080, /* DENALI_PHY_456_DATA */ + 0x00800080, /* DENALI_PHY_457_DATA */ + 0x00800080, /* DENALI_PHY_458_DATA */ + 0x00800080, /* DENALI_PHY_459_DATA */ + 0x00800080, /* DENALI_PHY_460_DATA */ + 0x01190080, /* DENALI_PHY_461_DATA */ + 0x00000001, /* DENALI_PHY_462_DATA */ + 0x00000000, /* DENALI_PHY_463_DATA */ + 0x00000000, /* DENALI_PHY_464_DATA */ + 0x00000200, /* DENALI_PHY_465_DATA */ + 0x00000000, /* DENALI_PHY_466_DATA */ + 0x51315152, /* DENALI_PHY_467_DATA */ + 0xc0003150, /* DENALI_PHY_468_DATA */ + 0x010000c0, /* DENALI_PHY_469_DATA */ + 0x00100000, /* DENALI_PHY_470_DATA */ + 0x07044204, /* DENALI_PHY_471_DATA */ + 0x000f0c18, /* DENALI_PHY_472_DATA */ + 0x01000140, /* DENALI_PHY_473_DATA */ + 0x00000c10, /* DENALI_PHY_474_DATA */ + 0x00000000, /* DENALI_PHY_475_DATA */ + 0x00000000, /* DENALI_PHY_476_DATA */ + 0x00000000, /* DENALI_PHY_477_DATA */ + 0x00000000, /* DENALI_PHY_478_DATA */ + 0x00000000, /* DENALI_PHY_479_DATA */ + 0x00000000, /* DENALI_PHY_480_DATA */ + 0x00000000, /* DENALI_PHY_481_DATA */ + 0x00000000, /* DENALI_PHY_482_DATA */ + 0x00000000, /* DENALI_PHY_483_DATA */ + 0x00000000, /* DENALI_PHY_484_DATA */ + 0x00000000, /* DENALI_PHY_485_DATA */ + 0x00000000, /* DENALI_PHY_486_DATA */ + 0x00000000, /* DENALI_PHY_487_DATA */ + 0x00000000, /* DENALI_PHY_488_DATA */ + 0x00000000, /* DENALI_PHY_489_DATA */ + 0x00000000, /* DENALI_PHY_490_DATA */ + 0x00000000, /* DENALI_PHY_491_DATA */ + 0x00000000, /* DENALI_PHY_492_DATA */ + 0x00000000, /* DENALI_PHY_493_DATA */ + 0x00000000, /* DENALI_PHY_494_DATA */ + 0x00000000, /* DENALI_PHY_495_DATA */ + 0x00000000, /* DENALI_PHY_496_DATA */ + 0x00000000, /* DENALI_PHY_497_DATA */ + 0x00000000, /* DENALI_PHY_498_DATA */ + 0x00000000, /* DENALI_PHY_499_DATA */ + 0x00000000, /* DENALI_PHY_500_DATA */ + 0x00000000, /* DENALI_PHY_501_DATA */ + 0x00000000, /* DENALI_PHY_502_DATA */ + 0x00000000, /* DENALI_PHY_503_DATA */ + 0x00000000, /* DENALI_PHY_504_DATA */ + 0x00000000, /* DENALI_PHY_505_DATA */ + 0x00000000, /* DENALI_PHY_506_DATA */ + 0x00000000, /* DENALI_PHY_507_DATA */ + 0x00000000, /* DENALI_PHY_508_DATA */ + 0x00000000, /* DENALI_PHY_509_DATA */ + 0x00000000, /* DENALI_PHY_510_DATA */ + 0x00000000, /* DENALI_PHY_511_DATA */ + 0x00000000, /* DENALI_PHY_512_DATA */ + 0x00000000, /* DENALI_PHY_513_DATA */ + 0x00000000, /* DENALI_PHY_514_DATA */ + 0x00000000, /* DENALI_PHY_515_DATA */ + 0x00000000, /* DENALI_PHY_516_DATA */ + 0x00000000, /* DENALI_PHY_517_DATA */ + 0x00000000, /* DENALI_PHY_518_DATA */ + 0x00000002, /* DENALI_PHY_519_DATA */ + 0x00000000, /* DENALI_PHY_520_DATA */ + 0x00000000, /* DENALI_PHY_521_DATA */ + 0x00000000, /* DENALI_PHY_522_DATA */ + 0x00400320, /* DENALI_PHY_523_DATA */ + 0x00000040, /* DENALI_PHY_524_DATA */ + 0x00dcba98, /* DENALI_PHY_525_DATA */ + 0x00000000, /* DENALI_PHY_526_DATA */ + 0x00dcba98, /* DENALI_PHY_527_DATA */ + 0x01000000, /* DENALI_PHY_528_DATA */ + 0x00020003, /* DENALI_PHY_529_DATA */ + 0x00000000, /* DENALI_PHY_530_DATA */ + 0x00000000, /* DENALI_PHY_531_DATA */ + 0x00000000, /* DENALI_PHY_532_DATA */ + 0x0000002a, /* DENALI_PHY_533_DATA */ + 0x00000015, /* DENALI_PHY_534_DATA */ + 0x00000015, /* DENALI_PHY_535_DATA */ + 0x0000002a, /* DENALI_PHY_536_DATA */ + 0x00000033, /* DENALI_PHY_537_DATA */ + 0x0000000c, /* DENALI_PHY_538_DATA */ + 0x0000000c, /* DENALI_PHY_539_DATA */ + 0x00000033, /* DENALI_PHY_540_DATA */ + 0x0a418820, /* DENALI_PHY_541_DATA */ + 0x003f0000, /* DENALI_PHY_542_DATA */ + 0x0000003f, /* DENALI_PHY_543_DATA */ + 0x00030055, /* DENALI_PHY_544_DATA */ + 0x03000300, /* DENALI_PHY_545_DATA */ + 0x03000300, /* DENALI_PHY_546_DATA */ + 0x00000300, /* DENALI_PHY_547_DATA */ + 0x42080010, /* DENALI_PHY_548_DATA */ + 0x00000003, /* DENALI_PHY_549_DATA */ + 0x00000000, /* DENALI_PHY_550_DATA */ + 0x00000000, /* DENALI_PHY_551_DATA */ + 0x00000000, /* DENALI_PHY_552_DATA */ + 0x00000000, /* DENALI_PHY_553_DATA */ + 0x00000000, /* DENALI_PHY_554_DATA */ + 0x00000000, /* DENALI_PHY_555_DATA */ + 0x00000000, /* DENALI_PHY_556_DATA */ + 0x00000000, /* DENALI_PHY_557_DATA */ + 0x00000000, /* DENALI_PHY_558_DATA */ + 0x00000000, /* DENALI_PHY_559_DATA */ + 0x00000000, /* DENALI_PHY_560_DATA */ + 0x00000000, /* DENALI_PHY_561_DATA */ + 0x00000000, /* DENALI_PHY_562_DATA */ + 0x00000000, /* DENALI_PHY_563_DATA */ + 0x00000000, /* DENALI_PHY_564_DATA */ + 0x00000000, /* DENALI_PHY_565_DATA */ + 0x00000000, /* DENALI_PHY_566_DATA */ + 0x00000000, /* DENALI_PHY_567_DATA */ + 0x00000000, /* DENALI_PHY_568_DATA */ + 0x00000000, /* DENALI_PHY_569_DATA */ + 0x00000000, /* DENALI_PHY_570_DATA */ + 0x00000000, /* DENALI_PHY_571_DATA */ + 0x00000000, /* DENALI_PHY_572_DATA */ + 0x00000000, /* DENALI_PHY_573_DATA */ + 0x00000000, /* DENALI_PHY_574_DATA */ + 0x00000000, /* DENALI_PHY_575_DATA */ + 0x00000000, /* DENALI_PHY_576_DATA */ + 0x00000000, /* DENALI_PHY_577_DATA */ + 0x00000000, /* DENALI_PHY_578_DATA */ + 0x00000000, /* DENALI_PHY_579_DATA */ + 0x00000000, /* DENALI_PHY_580_DATA */ + 0x00000000, /* DENALI_PHY_581_DATA */ + 0x00000000, /* DENALI_PHY_582_DATA */ + 0x00000000, /* DENALI_PHY_583_DATA */ + 0x00000000, /* DENALI_PHY_584_DATA */ + 0x00000000, /* DENALI_PHY_585_DATA */ + 0x00000000, /* DENALI_PHY_586_DATA */ + 0x00000000, /* DENALI_PHY_587_DATA */ + 0x00000000, /* DENALI_PHY_588_DATA */ + 0x00000000, /* DENALI_PHY_589_DATA */ + 0x00000000, /* DENALI_PHY_590_DATA */ + 0x00000000, /* DENALI_PHY_591_DATA */ + 0x00000000, /* DENALI_PHY_592_DATA */ + 0x00000000, /* DENALI_PHY_593_DATA */ + 0x00000000, /* DENALI_PHY_594_DATA */ + 0x00000000, /* DENALI_PHY_595_DATA */ + 0x00000000, /* DENALI_PHY_596_DATA */ + 0x00000000, /* DENALI_PHY_597_DATA */ + 0x00000000, /* DENALI_PHY_598_DATA */ + 0x00000000, /* DENALI_PHY_599_DATA */ + 0x00000000, /* DENALI_PHY_600_DATA */ + 0x00000000, /* DENALI_PHY_601_DATA */ + 0x00000000, /* DENALI_PHY_602_DATA */ + 0x00000000, /* DENALI_PHY_603_DATA */ + 0x00000000, /* DENALI_PHY_604_DATA */ + 0x00000000, /* DENALI_PHY_605_DATA */ + 0x00000000, /* DENALI_PHY_606_DATA */ + 0x00000000, /* DENALI_PHY_607_DATA */ + 0x00000000, /* DENALI_PHY_608_DATA */ + 0x00000000, /* DENALI_PHY_609_DATA */ + 0x00000000, /* DENALI_PHY_610_DATA */ + 0x00000000, /* DENALI_PHY_611_DATA */ + 0x00000000, /* DENALI_PHY_612_DATA */ + 0x00000000, /* DENALI_PHY_613_DATA */ + 0x00000000, /* DENALI_PHY_614_DATA */ + 0x00000000, /* DENALI_PHY_615_DATA */ + 0x00000000, /* DENALI_PHY_616_DATA */ + 0x00000000, /* DENALI_PHY_617_DATA */ + 0x00000000, /* DENALI_PHY_618_DATA */ + 0x00000000, /* DENALI_PHY_619_DATA */ + 0x00000000, /* DENALI_PHY_620_DATA */ + 0x00000000, /* DENALI_PHY_621_DATA */ + 0x00000000, /* DENALI_PHY_622_DATA */ + 0x00000000, /* DENALI_PHY_623_DATA */ + 0x00000000, /* DENALI_PHY_624_DATA */ + 0x00000000, /* DENALI_PHY_625_DATA */ + 0x00000000, /* DENALI_PHY_626_DATA */ + 0x00000000, /* DENALI_PHY_627_DATA */ + 0x00000000, /* DENALI_PHY_628_DATA */ + 0x00000000, /* DENALI_PHY_629_DATA */ + 0x00000000, /* DENALI_PHY_630_DATA */ + 0x00000000, /* DENALI_PHY_631_DATA */ + 0x00000000, /* DENALI_PHY_632_DATA */ + 0x00000000, /* DENALI_PHY_633_DATA */ + 0x00000000, /* DENALI_PHY_634_DATA */ + 0x00000000, /* DENALI_PHY_635_DATA */ + 0x00000000, /* DENALI_PHY_636_DATA */ + 0x00000000, /* DENALI_PHY_637_DATA */ + 0x00000000, /* DENALI_PHY_638_DATA */ + 0x00000000, /* DENALI_PHY_639_DATA */ + 0x00000000, /* DENALI_PHY_640_DATA */ + 0x00000000, /* DENALI_PHY_641_DATA */ + 0x00000000, /* DENALI_PHY_642_DATA */ + 0x00000000, /* DENALI_PHY_643_DATA */ + 0x00000000, /* DENALI_PHY_644_DATA */ + 0x00000000, /* DENALI_PHY_645_DATA */ + 0x00000000, /* DENALI_PHY_646_DATA */ + 0x00000002, /* DENALI_PHY_647_DATA */ + 0x00000000, /* DENALI_PHY_648_DATA */ + 0x00000000, /* DENALI_PHY_649_DATA */ + 0x00000000, /* DENALI_PHY_650_DATA */ + 0x00400320, /* DENALI_PHY_651_DATA */ + 0x00000040, /* DENALI_PHY_652_DATA */ + 0x00000000, /* DENALI_PHY_653_DATA */ + 0x00000000, /* DENALI_PHY_654_DATA */ + 0x00000000, /* DENALI_PHY_655_DATA */ + 0x01000000, /* DENALI_PHY_656_DATA */ + 0x00020003, /* DENALI_PHY_657_DATA */ + 0x00000000, /* DENALI_PHY_658_DATA */ + 0x00000000, /* DENALI_PHY_659_DATA */ + 0x00000000, /* DENALI_PHY_660_DATA */ + 0x0000002a, /* DENALI_PHY_661_DATA */ + 0x00000015, /* DENALI_PHY_662_DATA */ + 0x00000015, /* DENALI_PHY_663_DATA */ + 0x0000002a, /* DENALI_PHY_664_DATA */ + 0x00000033, /* DENALI_PHY_665_DATA */ + 0x0000000c, /* DENALI_PHY_666_DATA */ + 0x0000000c, /* DENALI_PHY_667_DATA */ + 0x00000033, /* DENALI_PHY_668_DATA */ + 0x00000000, /* DENALI_PHY_669_DATA */ + 0x00000000, /* DENALI_PHY_670_DATA */ + 0x00000000, /* DENALI_PHY_671_DATA */ + 0x00030055, /* DENALI_PHY_672_DATA */ + 0x03000300, /* DENALI_PHY_673_DATA */ + 0x03000300, /* DENALI_PHY_674_DATA */ + 0x00000300, /* DENALI_PHY_675_DATA */ + 0x42080010, /* DENALI_PHY_676_DATA */ + 0x00000003, /* DENALI_PHY_677_DATA */ + 0x00000000, /* DENALI_PHY_678_DATA */ + 0x00000000, /* DENALI_PHY_679_DATA */ + 0x00000000, /* DENALI_PHY_680_DATA */ + 0x00000000, /* DENALI_PHY_681_DATA */ + 0x00000000, /* DENALI_PHY_682_DATA */ + 0x00000000, /* DENALI_PHY_683_DATA */ + 0x00000000, /* DENALI_PHY_684_DATA */ + 0x00000000, /* DENALI_PHY_685_DATA */ + 0x00000000, /* DENALI_PHY_686_DATA */ + 0x00000000, /* DENALI_PHY_687_DATA */ + 0x00000000, /* DENALI_PHY_688_DATA */ + 0x00000000, /* DENALI_PHY_689_DATA */ + 0x00000000, /* DENALI_PHY_690_DATA */ + 0x00000000, /* DENALI_PHY_691_DATA */ + 0x00000000, /* DENALI_PHY_692_DATA */ + 0x00000000, /* DENALI_PHY_693_DATA */ + 0x00000000, /* DENALI_PHY_694_DATA */ + 0x00000000, /* DENALI_PHY_695_DATA */ + 0x00000000, /* DENALI_PHY_696_DATA */ + 0x00000000, /* DENALI_PHY_697_DATA */ + 0x00000000, /* DENALI_PHY_698_DATA */ + 0x00000000, /* DENALI_PHY_699_DATA */ + 0x00000000, /* DENALI_PHY_700_DATA */ + 0x00000000, /* DENALI_PHY_701_DATA */ + 0x00000000, /* DENALI_PHY_702_DATA */ + 0x00000000, /* DENALI_PHY_703_DATA */ + 0x00000000, /* DENALI_PHY_704_DATA */ + 0x00000000, /* DENALI_PHY_705_DATA */ + 0x00000000, /* DENALI_PHY_706_DATA */ + 0x00000000, /* DENALI_PHY_707_DATA */ + 0x00000000, /* DENALI_PHY_708_DATA */ + 0x00000000, /* DENALI_PHY_709_DATA */ + 0x00000000, /* DENALI_PHY_710_DATA */ + 0x00000000, /* DENALI_PHY_711_DATA */ + 0x00000000, /* DENALI_PHY_712_DATA */ + 0x00000000, /* DENALI_PHY_713_DATA */ + 0x00000000, /* DENALI_PHY_714_DATA */ + 0x00000000, /* DENALI_PHY_715_DATA */ + 0x00000000, /* DENALI_PHY_716_DATA */ + 0x00000000, /* DENALI_PHY_717_DATA */ + 0x00000000, /* DENALI_PHY_718_DATA */ + 0x00000000, /* DENALI_PHY_719_DATA */ + 0x00000000, /* DENALI_PHY_720_DATA */ + 0x00000000, /* DENALI_PHY_721_DATA */ + 0x00000000, /* DENALI_PHY_722_DATA */ + 0x00000000, /* DENALI_PHY_723_DATA */ + 0x00000000, /* DENALI_PHY_724_DATA */ + 0x00000000, /* DENALI_PHY_725_DATA */ + 0x00000000, /* DENALI_PHY_726_DATA */ + 0x00000000, /* DENALI_PHY_727_DATA */ + 0x00000000, /* DENALI_PHY_728_DATA */ + 0x00000000, /* DENALI_PHY_729_DATA */ + 0x00000000, /* DENALI_PHY_730_DATA */ + 0x00000000, /* DENALI_PHY_731_DATA */ + 0x00000000, /* DENALI_PHY_732_DATA */ + 0x00000000, /* DENALI_PHY_733_DATA */ + 0x00000000, /* DENALI_PHY_734_DATA */ + 0x00000000, /* DENALI_PHY_735_DATA */ + 0x00000000, /* DENALI_PHY_736_DATA */ + 0x00000000, /* DENALI_PHY_737_DATA */ + 0x00000000, /* DENALI_PHY_738_DATA */ + 0x00000000, /* DENALI_PHY_739_DATA */ + 0x00000000, /* DENALI_PHY_740_DATA */ + 0x00000000, /* DENALI_PHY_741_DATA */ + 0x00000000, /* DENALI_PHY_742_DATA */ + 0x00000000, /* DENALI_PHY_743_DATA */ + 0x00000000, /* DENALI_PHY_744_DATA */ + 0x00000000, /* DENALI_PHY_745_DATA */ + 0x00000000, /* DENALI_PHY_746_DATA */ + 0x00000000, /* DENALI_PHY_747_DATA */ + 0x00000000, /* DENALI_PHY_748_DATA */ + 0x00000000, /* DENALI_PHY_749_DATA */ + 0x00000000, /* DENALI_PHY_750_DATA */ + 0x00000000, /* DENALI_PHY_751_DATA */ + 0x00000000, /* DENALI_PHY_752_DATA */ + 0x00000000, /* DENALI_PHY_753_DATA */ + 0x00000000, /* DENALI_PHY_754_DATA */ + 0x00000000, /* DENALI_PHY_755_DATA */ + 0x00000000, /* DENALI_PHY_756_DATA */ + 0x00000000, /* DENALI_PHY_757_DATA */ + 0x00000000, /* DENALI_PHY_758_DATA */ + 0x00000000, /* DENALI_PHY_759_DATA */ + 0x00000000, /* DENALI_PHY_760_DATA */ + 0x00000000, /* DENALI_PHY_761_DATA */ + 0x00000000, /* DENALI_PHY_762_DATA */ + 0x00000000, /* DENALI_PHY_763_DATA */ + 0x00000000, /* DENALI_PHY_764_DATA */ + 0x00000000, /* DENALI_PHY_765_DATA */ + 0x00000000, /* DENALI_PHY_766_DATA */ + 0x00000000, /* DENALI_PHY_767_DATA */ + 0x00000000, /* DENALI_PHY_768_DATA */ + 0x00000000, /* DENALI_PHY_769_DATA */ + 0x00000000, /* DENALI_PHY_770_DATA */ + 0x00000000, /* DENALI_PHY_771_DATA */ + 0x00000000, /* DENALI_PHY_772_DATA */ + 0x00000000, /* DENALI_PHY_773_DATA */ + 0x00000000, /* DENALI_PHY_774_DATA */ + 0x00000002, /* DENALI_PHY_775_DATA */ + 0x00000000, /* DENALI_PHY_776_DATA */ + 0x00000000, /* DENALI_PHY_777_DATA */ + 0x00000000, /* DENALI_PHY_778_DATA */ + 0x00400320, /* DENALI_PHY_779_DATA */ + 0x00000040, /* DENALI_PHY_780_DATA */ + 0x00000000, /* DENALI_PHY_781_DATA */ + 0x00000000, /* DENALI_PHY_782_DATA */ + 0x00000000, /* DENALI_PHY_783_DATA */ + 0x01000000, /* DENALI_PHY_784_DATA */ + 0x00020003, /* DENALI_PHY_785_DATA */ + 0x00000000, /* DENALI_PHY_786_DATA */ + 0x00000000, /* DENALI_PHY_787_DATA */ + 0x00000000, /* DENALI_PHY_788_DATA */ + 0x0000002a, /* DENALI_PHY_789_DATA */ + 0x00000015, /* DENALI_PHY_790_DATA */ + 0x00000015, /* DENALI_PHY_791_DATA */ + 0x0000002a, /* DENALI_PHY_792_DATA */ + 0x00000033, /* DENALI_PHY_793_DATA */ + 0x0000000c, /* DENALI_PHY_794_DATA */ + 0x0000000c, /* DENALI_PHY_795_DATA */ + 0x00000033, /* DENALI_PHY_796_DATA */ + 0x1ee6b16a, /* DENALI_PHY_797_DATA */ + 0x10000000, /* DENALI_PHY_798_DATA */ + 0x00000000, /* DENALI_PHY_799_DATA */ + 0x00030055, /* DENALI_PHY_800_DATA */ + 0x03000300, /* DENALI_PHY_801_DATA */ + 0x03000300, /* DENALI_PHY_802_DATA */ + 0x00000300, /* DENALI_PHY_803_DATA */ + 0x42080010, /* DENALI_PHY_804_DATA */ + 0x00000003, /* DENALI_PHY_805_DATA */ + 0x00000000, /* DENALI_PHY_806_DATA */ + 0x00000000, /* DENALI_PHY_807_DATA */ + 0x00000000, /* DENALI_PHY_808_DATA */ + 0x00000000, /* DENALI_PHY_809_DATA */ + 0x00000000, /* DENALI_PHY_810_DATA */ + 0x00000000, /* DENALI_PHY_811_DATA */ + 0x00000000, /* DENALI_PHY_812_DATA */ + 0x00000000, /* DENALI_PHY_813_DATA */ + 0x00000000, /* DENALI_PHY_814_DATA */ + 0x00000000, /* DENALI_PHY_815_DATA */ + 0x00000000, /* DENALI_PHY_816_DATA */ + 0x00000000, /* DENALI_PHY_817_DATA */ + 0x00000000, /* DENALI_PHY_818_DATA */ + 0x00000000, /* DENALI_PHY_819_DATA */ + 0x00000000, /* DENALI_PHY_820_DATA */ + 0x00000000, /* DENALI_PHY_821_DATA */ + 0x00000000, /* DENALI_PHY_822_DATA */ + 0x00000000, /* DENALI_PHY_823_DATA */ + 0x00000000, /* DENALI_PHY_824_DATA */ + 0x00000000, /* DENALI_PHY_825_DATA */ + 0x00000000, /* DENALI_PHY_826_DATA */ + 0x00000000, /* DENALI_PHY_827_DATA */ + 0x00000000, /* DENALI_PHY_828_DATA */ + 0x00000000, /* DENALI_PHY_829_DATA */ + 0x00000000, /* DENALI_PHY_830_DATA */ + 0x00000000, /* DENALI_PHY_831_DATA */ + 0x00000000, /* DENALI_PHY_832_DATA */ + 0x00000000, /* DENALI_PHY_833_DATA */ + 0x00000000, /* DENALI_PHY_834_DATA */ + 0x00000000, /* DENALI_PHY_835_DATA */ + 0x00000000, /* DENALI_PHY_836_DATA */ + 0x00000000, /* DENALI_PHY_837_DATA */ + 0x00000000, /* DENALI_PHY_838_DATA */ + 0x00000000, /* DENALI_PHY_839_DATA */ + 0x00000000, /* DENALI_PHY_840_DATA */ + 0x00000000, /* DENALI_PHY_841_DATA */ + 0x00000000, /* DENALI_PHY_842_DATA */ + 0x00000000, /* DENALI_PHY_843_DATA */ + 0x00000000, /* DENALI_PHY_844_DATA */ + 0x00000000, /* DENALI_PHY_845_DATA */ + 0x00000000, /* DENALI_PHY_846_DATA */ + 0x00000000, /* DENALI_PHY_847_DATA */ + 0x00000000, /* DENALI_PHY_848_DATA */ + 0x00000000, /* DENALI_PHY_849_DATA */ + 0x00000000, /* DENALI_PHY_850_DATA */ + 0x00000000, /* DENALI_PHY_851_DATA */ + 0x00000000, /* DENALI_PHY_852_DATA */ + 0x00000000, /* DENALI_PHY_853_DATA */ + 0x00000000, /* DENALI_PHY_854_DATA */ + 0x00000000, /* DENALI_PHY_855_DATA */ + 0x00000000, /* DENALI_PHY_856_DATA */ + 0x00000000, /* DENALI_PHY_857_DATA */ + 0x00000000, /* DENALI_PHY_858_DATA */ + 0x00000000, /* DENALI_PHY_859_DATA */ + 0x00000000, /* DENALI_PHY_860_DATA */ + 0x00000000, /* DENALI_PHY_861_DATA */ + 0x00000000, /* DENALI_PHY_862_DATA */ + 0x00000000, /* DENALI_PHY_863_DATA */ + 0x00000000, /* DENALI_PHY_864_DATA */ + 0x00000000, /* DENALI_PHY_865_DATA */ + 0x00000000, /* DENALI_PHY_866_DATA */ + 0x00000000, /* DENALI_PHY_867_DATA */ + 0x00000000, /* DENALI_PHY_868_DATA */ + 0x00000000, /* DENALI_PHY_869_DATA */ + 0x00000000, /* DENALI_PHY_870_DATA */ + 0x00000000, /* DENALI_PHY_871_DATA */ + 0x00000000, /* DENALI_PHY_872_DATA */ + 0x00000000, /* DENALI_PHY_873_DATA */ + 0x00000000, /* DENALI_PHY_874_DATA */ + 0x00000000, /* DENALI_PHY_875_DATA */ + 0x00000000, /* DENALI_PHY_876_DATA */ + 0x00000000, /* DENALI_PHY_877_DATA */ + 0x00000000, /* DENALI_PHY_878_DATA */ + 0x00000000, /* DENALI_PHY_879_DATA */ + 0x00000000, /* DENALI_PHY_880_DATA */ + 0x00000000, /* DENALI_PHY_881_DATA */ + 0x00000000, /* DENALI_PHY_882_DATA */ + 0x00000000, /* DENALI_PHY_883_DATA */ + 0x00000000, /* DENALI_PHY_884_DATA */ + 0x00000000, /* DENALI_PHY_885_DATA */ + 0x00000000, /* DENALI_PHY_886_DATA */ + 0x00000000, /* DENALI_PHY_887_DATA */ + 0x00000000, /* DENALI_PHY_888_DATA */ + 0x00000000, /* DENALI_PHY_889_DATA */ + 0x00000000, /* DENALI_PHY_890_DATA */ + 0x00000000, /* DENALI_PHY_891_DATA */ + 0x00000000, /* DENALI_PHY_892_DATA */ + 0x00000000, /* DENALI_PHY_893_DATA */ + 0x00000000, /* DENALI_PHY_894_DATA */ + 0x00000000, /* DENALI_PHY_895_DATA */ + 0x00000000, /* DENALI_PHY_896_DATA */ + 0x00000000, /* DENALI_PHY_897_DATA */ + 0x00000005, /* DENALI_PHY_898_DATA */ + 0x04000f01, /* DENALI_PHY_899_DATA */ + 0x00020040, /* DENALI_PHY_900_DATA */ + 0x00020055, /* DENALI_PHY_901_DATA */ + 0x00000000, /* DENALI_PHY_902_DATA */ + 0x00000000, /* DENALI_PHY_903_DATA */ + 0x00000000, /* DENALI_PHY_904_DATA */ + 0x00000050, /* DENALI_PHY_905_DATA */ + 0x00000000, /* DENALI_PHY_906_DATA */ + 0x01010100, /* DENALI_PHY_907_DATA */ + 0x00000600, /* DENALI_PHY_908_DATA */ + 0x00000000, /* DENALI_PHY_909_DATA */ + 0x00006400, /* DENALI_PHY_910_DATA */ + 0x03221302, /* DENALI_PHY_911_DATA */ + 0x00000000, /* DENALI_PHY_912_DATA */ + 0x000d1f01, /* DENALI_PHY_913_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_914_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_915_DATA */ + 0x00030003, /* DENALI_PHY_916_DATA */ + 0x03000300, /* DENALI_PHY_917_DATA */ + 0x00000300, /* DENALI_PHY_918_DATA */ + 0x03221302, /* DENALI_PHY_919_DATA */ + 0x00000000, /* DENALI_PHY_920_DATA */ + 0x00000000, /* DENALI_PHY_921_DATA */ + 0x01020000, /* DENALI_PHY_922_DATA */ + 0x00000001, /* DENALI_PHY_923_DATA */ + 0x00000411, /* DENALI_PHY_924_DATA */ + 0x00000411, /* DENALI_PHY_925_DATA */ + 0x00000040, /* DENALI_PHY_926_DATA */ + 0x00000040, /* DENALI_PHY_927_DATA */ + 0x00000411, /* DENALI_PHY_928_DATA */ + 0x00000411, /* DENALI_PHY_929_DATA */ + 0x00004410, /* DENALI_PHY_930_DATA */ + 0x00004410, /* DENALI_PHY_931_DATA */ + 0x00004410, /* DENALI_PHY_932_DATA */ + 0x00004410, /* DENALI_PHY_933_DATA */ + 0x00004410, /* DENALI_PHY_934_DATA */ + 0x00000411, /* DENALI_PHY_935_DATA */ + 0x00004410, /* DENALI_PHY_936_DATA */ + 0x00000411, /* DENALI_PHY_937_DATA */ + 0x00004410, /* DENALI_PHY_938_DATA */ + 0x00000411, /* DENALI_PHY_939_DATA */ + 0x00004410, /* DENALI_PHY_940_DATA */ + 0x00000000, /* DENALI_PHY_941_DATA */ + 0x00000000, /* DENALI_PHY_942_DATA */ + 0x00000000, /* DENALI_PHY_943_DATA */ + 0x64000000, /* DENALI_PHY_944_DATA */ + 0x00000000, /* DENALI_PHY_945_DATA */ + 0x00000000, /* DENALI_PHY_946_DATA */ + 0x00000408, /* DENALI_PHY_947_DATA */ + 0x00000000, /* DENALI_PHY_948_DATA */ + 0x00000000, /* DENALI_PHY_949_DATA */ + 0x00000000, /* DENALI_PHY_950_DATA */ + 0x00000000, /* DENALI_PHY_951_DATA */ + 0x00000000, /* DENALI_PHY_952_DATA */ + 0x00000000, /* DENALI_PHY_953_DATA */ + 0xe4000000, /* DENALI_PHY_954_DATA */ + 0x00000000, /* DENALI_PHY_955_DATA */ + 0x00000000, /* DENALI_PHY_956_DATA */ + 0x01010000, /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + } + }, +}, From dd2c633b2a3daf6f3acee0dcd569b0417c438dbb Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:38 +0530 Subject: [PATCH 083/147] ram: rk3399: Add LPPDDR4-800 timings inc LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 +++++++++++++++++ 1 file changed, 1570 insertions(+) create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc diff --git a/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc new file mode 100644 index 00000000000..d8ae3359a39 --- /dev/null +++ b/drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc @@ -0,0 +1,1570 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + * (C) Copyright 2019 Amarula Solutions + */ + +{ + { + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = 0x80241d22, + .ddrtimingb0 = 0x15050f08, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = 0x00002122, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + }, + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF, + .ddrconfig = 1, + }, + { + .ddrtiminga0 = 0x80241d22, + .ddrtimingb0 = 0x15050f08, + .ddrtimingc0 = { + 0x00000602, + }, + .devtodev0 = 0x00002122, + .ddrmode = { + 0x0000004c, + }, + .agingx0 = 0x00000000, + } + } + }, + { + .ddr_freq = 800 * MHz, + .dramtype = LPDDR4, + .num_channels = 2, + .stride = 13, + .odt = 1, + }, + { + { + 0x00000b00, /* DENALI_CTL_00_DATA */ + 0x00000000, /* DENALI_CTL_01_DATA */ + 0x00000000, /* DENALI_CTL_02_DATA */ + 0x00000000, /* DENALI_CTL_03_DATA */ + 0x00000000, /* DENALI_CTL_04_DATA */ + 0x00013880, /* DENALI_CTL_05_DATA */ + 0x000c3500, /* DENALI_CTL_06_DATA */ + 0x00000005, /* DENALI_CTL_07_DATA */ + 0x00000320, /* DENALI_CTL_08_DATA */ + 0x00027100, /* DENALI_CTL_09_DATA */ + 0x00186a00, /* DENALI_CTL_10_DATA */ + 0x00000005, /* DENALI_CTL_11_DATA */ + 0x00000640, /* DENALI_CTL_12_DATA */ + 0x00002710, /* DENALI_CTL_13_DATA */ + 0x000186a0, /* DENALI_CTL_14_DATA */ + 0x00000005, /* DENALI_CTL_15_DATA */ + 0x01000064, /* DENALI_CTL_16_DATA */ + 0x00000000, /* DENALI_CTL_17_DATA */ + 0x02020101, /* DENALI_CTL_18_DATA */ + 0x00000102, /* DENALI_CTL_19_DATA */ + 0x00000050, /* DENALI_CTL_20_DATA */ + 0x000000c8, /* DENALI_CTL_21_DATA */ + 0x00000000, /* DENALI_CTL_22_DATA */ + 0x06140000, /* DENALI_CTL_23_DATA */ + 0x00081c00, /* DENALI_CTL_24_DATA */ + 0x0400040c, /* DENALI_CTL_25_DATA */ + 0x19042008, /* DENALI_CTL_26_DATA */ + 0x10080a11, /* DENALI_CTL_27_DATA */ + 0x22310800, /* DENALI_CTL_28_DATA */ + 0x00200f0a, /* DENALI_CTL_29_DATA */ + 0x0a030704, /* DENALI_CTL_30_DATA */ + 0x08000204, /* DENALI_CTL_31_DATA */ + 0x00000a0a, /* DENALI_CTL_32_DATA */ + 0x04006db0, /* DENALI_CTL_33_DATA */ + 0x0a0a0804, /* DENALI_CTL_34_DATA */ + 0x0600db60, /* DENALI_CTL_35_DATA */ + 0x0a0a0806, /* DENALI_CTL_36_DATA */ + 0x04000db6, /* DENALI_CTL_37_DATA */ + 0x02030404, /* DENALI_CTL_38_DATA */ + 0x0f0a0800, /* DENALI_CTL_39_DATA */ + 0x08040411, /* DENALI_CTL_40_DATA */ + 0x1400640a, /* DENALI_CTL_41_DATA */ + 0x02010a0a, /* DENALI_CTL_42_DATA */ + 0x00010001, /* DENALI_CTL_43_DATA */ + 0x04082012, /* DENALI_CTL_44_DATA */ + 0x00041109, /* DENALI_CTL_45_DATA */ + 0x00000000, /* DENALI_CTL_46_DATA */ + 0x03010000, /* DENALI_CTL_47_DATA */ + 0x06100034, /* DENALI_CTL_48_DATA */ + 0x0c280068, /* DENALI_CTL_49_DATA */ + 0x00bb0007, /* DENALI_CTL_50_DATA */ + 0x00000000, /* DENALI_CTL_51_DATA */ + 0x00060003, /* DENALI_CTL_52_DATA */ + 0x000a0003, /* DENALI_CTL_53_DATA */ + 0x000a0014, /* DENALI_CTL_54_DATA */ + 0x01000000, /* DENALI_CTL_55_DATA */ + 0x030a0000, /* DENALI_CTL_56_DATA */ + 0x0c000002, /* DENALI_CTL_57_DATA */ + 0x00000103, /* DENALI_CTL_58_DATA */ + 0x0003030a, /* DENALI_CTL_59_DATA */ + 0x00060037, /* DENALI_CTL_60_DATA */ + 0x0003006e, /* DENALI_CTL_61_DATA */ + 0x05050007, /* DENALI_CTL_62_DATA */ + 0x03020605, /* DENALI_CTL_63_DATA */ + 0x06050301, /* DENALI_CTL_64_DATA */ + 0x06020c05, /* DENALI_CTL_65_DATA */ + 0x05050302, /* DENALI_CTL_66_DATA */ + 0x03020305, /* DENALI_CTL_67_DATA */ + 0x00000301, /* DENALI_CTL_68_DATA */ + 0x00000301, /* DENALI_CTL_69_DATA */ + 0x00000001, /* DENALI_CTL_70_DATA */ + 0x00000000, /* DENALI_CTL_71_DATA */ + 0x00000000, /* DENALI_CTL_72_DATA */ + 0x01000000, /* DENALI_CTL_73_DATA */ + 0x80104002, /* DENALI_CTL_74_DATA */ + 0x00040003, /* DENALI_CTL_75_DATA */ + 0x00040005, /* DENALI_CTL_76_DATA */ + 0x00030000, /* DENALI_CTL_77_DATA */ + 0x00050004, /* DENALI_CTL_78_DATA */ + 0x00000004, /* DENALI_CTL_79_DATA */ + 0x00040003, /* DENALI_CTL_80_DATA */ + 0x00040005, /* DENALI_CTL_81_DATA */ + 0x18400000, /* DENALI_CTL_82_DATA */ + 0x00000c20, /* DENALI_CTL_83_DATA */ + 0x185030a0, /* DENALI_CTL_84_DATA */ + 0x02ec0000, /* DENALI_CTL_85_DATA */ + 0x00000176, /* DENALI_CTL_86_DATA */ + 0x00000000, /* DENALI_CTL_87_DATA */ + 0x00000000, /* DENALI_CTL_88_DATA */ + 0x00000000, /* DENALI_CTL_89_DATA */ + 0x00000000, /* DENALI_CTL_90_DATA */ + 0x00000000, /* DENALI_CTL_91_DATA */ + 0x06030300, /* DENALI_CTL_92_DATA */ + 0x00030303, /* DENALI_CTL_93_DATA */ + 0x02030200, /* DENALI_CTL_94_DATA */ + 0x00040703, /* DENALI_CTL_95_DATA */ + 0x03020302, /* DENALI_CTL_96_DATA */ + 0x02000407, /* DENALI_CTL_97_DATA */ + 0x07030203, /* DENALI_CTL_98_DATA */ + 0x00030f04, /* DENALI_CTL_99_DATA */ + 0x00070004, /* DENALI_CTL_100_DATA */ + 0x00000000, /* DENALI_CTL_101_DATA */ + 0x00000000, /* DENALI_CTL_102_DATA */ + 0x00000000, /* DENALI_CTL_103_DATA */ + 0x00000000, /* DENALI_CTL_104_DATA */ + 0x00000000, /* DENALI_CTL_105_DATA */ + 0x00000000, /* DENALI_CTL_106_DATA */ + 0x00000000, /* DENALI_CTL_107_DATA */ + 0x00010000, /* DENALI_CTL_108_DATA */ + 0x20040020, /* DENALI_CTL_109_DATA */ + 0x00200400, /* DENALI_CTL_110_DATA */ + 0x01000400, /* DENALI_CTL_111_DATA */ + 0x00000b80, /* DENALI_CTL_112_DATA */ + 0x00000000, /* DENALI_CTL_113_DATA */ + 0x00000001, /* DENALI_CTL_114_DATA */ + 0x00000002, /* DENALI_CTL_115_DATA */ + 0x0000000e, /* DENALI_CTL_116_DATA */ + 0x00000000, /* DENALI_CTL_117_DATA */ + 0x00000000, /* DENALI_CTL_118_DATA */ + 0x00000000, /* DENALI_CTL_119_DATA */ + 0x00000000, /* DENALI_CTL_120_DATA */ + 0x00000000, /* DENALI_CTL_121_DATA */ + 0x00500000, /* DENALI_CTL_122_DATA */ + 0x00640028, /* DENALI_CTL_123_DATA */ + 0x00640404, /* DENALI_CTL_124_DATA */ + 0x005000a0, /* DENALI_CTL_125_DATA */ + 0x060600c8, /* DENALI_CTL_126_DATA */ + 0x000a00c8, /* DENALI_CTL_127_DATA */ + 0x000d0005, /* DENALI_CTL_128_DATA */ + 0x000d0404, /* DENALI_CTL_129_DATA */ + 0x00000000, /* DENALI_CTL_130_DATA */ + 0x00000000, /* DENALI_CTL_131_DATA */ + 0x00000000, /* DENALI_CTL_132_DATA */ + 0x001400a3, /* DENALI_CTL_133_DATA */ + 0x00e30009, /* DENALI_CTL_134_DATA */ + 0x00120024, /* DENALI_CTL_135_DATA */ + 0x00040063, /* DENALI_CTL_136_DATA */ + 0x00000000, /* DENALI_CTL_137_DATA */ + 0x00310031, /* DENALI_CTL_138_DATA */ + 0x00000031, /* DENALI_CTL_139_DATA */ + 0x004d0000, /* DENALI_CTL_140_DATA */ + 0x004d004d, /* DENALI_CTL_141_DATA */ + 0x004d0000, /* DENALI_CTL_142_DATA */ + 0x004d004d, /* DENALI_CTL_143_DATA */ + 0x00010101, /* DENALI_CTL_144_DATA */ + 0x00000000, /* DENALI_CTL_145_DATA */ + 0x00000000, /* DENALI_CTL_146_DATA */ + 0x001400a3, /* DENALI_CTL_147_DATA */ + 0x00e30009, /* DENALI_CTL_148_DATA */ + 0x00120024, /* DENALI_CTL_149_DATA */ + 0x00040063, /* DENALI_CTL_150_DATA */ + 0x00000000, /* DENALI_CTL_151_DATA */ + 0x00310031, /* DENALI_CTL_152_DATA */ + 0x00000031, /* DENALI_CTL_153_DATA */ + 0x004d0000, /* DENALI_CTL_154_DATA */ + 0x004d004d, /* DENALI_CTL_155_DATA */ + 0x004d0000, /* DENALI_CTL_156_DATA */ + 0x004d004d, /* DENALI_CTL_157_DATA */ + 0x00010101, /* DENALI_CTL_158_DATA */ + 0x00000000, /* DENALI_CTL_159_DATA */ + 0x00000000, /* DENALI_CTL_160_DATA */ + 0x00000000, /* DENALI_CTL_161_DATA */ + 0x00000001, /* DENALI_CTL_162_DATA */ + 0x00000000, /* DENALI_CTL_163_DATA */ + 0x18151100, /* DENALI_CTL_164_DATA */ + 0x0000000c, /* DENALI_CTL_165_DATA */ + 0x00000000, /* DENALI_CTL_166_DATA */ + 0x00000000, /* DENALI_CTL_167_DATA */ + 0x00000000, /* DENALI_CTL_168_DATA */ + 0x00000000, /* DENALI_CTL_169_DATA */ + 0x00000000, /* DENALI_CTL_170_DATA */ + 0x00000000, /* DENALI_CTL_171_DATA */ + 0x00000000, /* DENALI_CTL_172_DATA */ + 0x00000000, /* DENALI_CTL_173_DATA */ + 0x00000000, /* DENALI_CTL_174_DATA */ + 0x00000000, /* DENALI_CTL_175_DATA */ + 0x00000000, /* DENALI_CTL_176_DATA */ + 0x00000000, /* DENALI_CTL_177_DATA */ + 0x00000000, /* DENALI_CTL_178_DATA */ + 0x00020003, /* DENALI_CTL_179_DATA */ + 0x00400100, /* DENALI_CTL_180_DATA */ + 0x000c0190, /* DENALI_CTL_181_DATA */ + 0x01000200, /* DENALI_CTL_182_DATA */ + 0x03200040, /* DENALI_CTL_183_DATA */ + 0x00020018, /* DENALI_CTL_184_DATA */ + 0x00400100, /* DENALI_CTL_185_DATA */ + 0x00080032, /* DENALI_CTL_186_DATA */ + 0x00140000, /* DENALI_CTL_187_DATA */ + 0x00030028, /* DENALI_CTL_188_DATA */ + 0x01010100, /* DENALI_CTL_189_DATA */ + 0x02000202, /* DENALI_CTL_190_DATA */ + 0x0b000002, /* DENALI_CTL_191_DATA */ + 0x01000f0f, /* DENALI_CTL_192_DATA */ + 0x00000000, /* DENALI_CTL_193_DATA */ + 0x00000000, /* DENALI_CTL_194_DATA */ + 0x00010003, /* DENALI_CTL_195_DATA */ + 0x00000c03, /* DENALI_CTL_196_DATA */ + 0x00040101, /* DENALI_CTL_197_DATA */ + 0x04010100, /* DENALI_CTL_198_DATA */ + 0x01000000, /* DENALI_CTL_199_DATA */ + 0x02010000, /* DENALI_CTL_200_DATA */ + 0x00000001, /* DENALI_CTL_201_DATA */ + 0x00000000, /* DENALI_CTL_202_DATA */ + 0x00000000, /* DENALI_CTL_203_DATA */ + 0x00000000, /* DENALI_CTL_204_DATA */ + 0x00000000, /* DENALI_CTL_205_DATA */ + 0x00000000, /* DENALI_CTL_206_DATA */ + 0x00000000, /* DENALI_CTL_207_DATA */ + 0x00000000, /* DENALI_CTL_208_DATA */ + 0x00000000, /* DENALI_CTL_209_DATA */ + 0x00000000, /* DENALI_CTL_210_DATA */ + 0x00010000, /* DENALI_CTL_211_DATA */ + 0x00000001, /* DENALI_CTL_212_DATA */ + 0x01010001, /* DENALI_CTL_213_DATA */ + 0x05040001, /* DENALI_CTL_214_DATA */ + 0x040a0703, /* DENALI_CTL_215_DATA */ + 0x02080808, /* DENALI_CTL_216_DATA */ + 0x020e000a, /* DENALI_CTL_217_DATA */ + 0x020f010b, /* DENALI_CTL_218_DATA */ + 0x000d0008, /* DENALI_CTL_219_DATA */ + 0x00080b0a, /* DENALI_CTL_220_DATA */ + 0x03000200, /* DENALI_CTL_221_DATA */ + 0x00000100, /* DENALI_CTL_222_DATA */ + 0x00000000, /* DENALI_CTL_223_DATA */ + 0x00000000, /* DENALI_CTL_224_DATA */ + 0x0d000001, /* DENALI_CTL_225_DATA */ + 0x00000028, /* DENALI_CTL_226_DATA */ + 0x00010000, /* DENALI_CTL_227_DATA */ + 0x00000003, /* DENALI_CTL_228_DATA */ + 0x00000000, /* DENALI_CTL_229_DATA */ + 0x00000000, /* DENALI_CTL_230_DATA */ + 0x00000000, /* DENALI_CTL_231_DATA */ + 0x00000000, /* DENALI_CTL_232_DATA */ + 0x00000000, /* DENALI_CTL_233_DATA */ + 0x00000000, /* DENALI_CTL_234_DATA */ + 0x00000000, /* DENALI_CTL_235_DATA */ + 0x00000000, /* DENALI_CTL_236_DATA */ + 0x00010100, /* DENALI_CTL_237_DATA */ + 0x01000000, /* DENALI_CTL_238_DATA */ + 0x00000001, /* DENALI_CTL_239_DATA */ + 0x00000303, /* DENALI_CTL_240_DATA */ + 0x00000000, /* DENALI_CTL_241_DATA */ + 0x00000000, /* DENALI_CTL_242_DATA */ + 0x00000000, /* DENALI_CTL_243_DATA */ + 0x00000000, /* DENALI_CTL_244_DATA */ + 0x00000000, /* DENALI_CTL_245_DATA */ + 0x00000000, /* DENALI_CTL_246_DATA */ + 0x00000000, /* DENALI_CTL_247_DATA */ + 0x00000000, /* DENALI_CTL_248_DATA */ + 0x00000000, /* DENALI_CTL_249_DATA */ + 0x00000000, /* DENALI_CTL_250_DATA */ + 0x00000000, /* DENALI_CTL_251_DATA */ + 0x00000000, /* DENALI_CTL_252_DATA */ + 0x00000000, /* DENALI_CTL_253_DATA */ + 0x00000000, /* DENALI_CTL_254_DATA */ + 0x00000000, /* DENALI_CTL_255_DATA */ + 0x000556aa, /* DENALI_CTL_256_DATA */ + 0x000aaaaa, /* DENALI_CTL_257_DATA */ + 0x000aa955, /* DENALI_CTL_258_DATA */ + 0x00055555, /* DENALI_CTL_259_DATA */ + 0x000b3133, /* DENALI_CTL_260_DATA */ + 0x0004cd33, /* DENALI_CTL_261_DATA */ + 0x0004cecc, /* DENALI_CTL_262_DATA */ + 0x000b32cc, /* DENALI_CTL_263_DATA */ + 0x00010300, /* DENALI_CTL_264_DATA */ + 0x03000100, /* DENALI_CTL_265_DATA */ + 0x00000000, /* DENALI_CTL_266_DATA */ + 0x00000000, /* DENALI_CTL_267_DATA */ + 0x00000000, /* DENALI_CTL_268_DATA */ + 0x00000000, /* DENALI_CTL_269_DATA */ + 0x00000000, /* DENALI_CTL_270_DATA */ + 0x00000000, /* DENALI_CTL_271_DATA */ + 0x00000000, /* DENALI_CTL_272_DATA */ + 0x00000000, /* DENALI_CTL_273_DATA */ + 0x00ffff00, /* DENALI_CTL_274_DATA */ + 0x1a160000, /* DENALI_CTL_275_DATA */ + 0x08000012, /* DENALI_CTL_276_DATA */ + 0x00000c20, /* DENALI_CTL_277_DATA */ + 0x00000200, /* DENALI_CTL_278_DATA */ + 0x00000200, /* DENALI_CTL_279_DATA */ + 0x00000200, /* DENALI_CTL_280_DATA */ + 0x00000200, /* DENALI_CTL_281_DATA */ + 0x00000c20, /* DENALI_CTL_282_DATA */ + 0x00007940, /* DENALI_CTL_283_DATA */ + 0x18500409, /* DENALI_CTL_284_DATA */ + 0x00000200, /* DENALI_CTL_285_DATA */ + 0x00000200, /* DENALI_CTL_286_DATA */ + 0x00000200, /* DENALI_CTL_287_DATA */ + 0x00000200, /* DENALI_CTL_288_DATA */ + 0x00001850, /* DENALI_CTL_289_DATA */ + 0x0000f320, /* DENALI_CTL_290_DATA */ + 0x0176060c, /* DENALI_CTL_291_DATA */ + 0x00000200, /* DENALI_CTL_292_DATA */ + 0x00000200, /* DENALI_CTL_293_DATA */ + 0x00000200, /* DENALI_CTL_294_DATA */ + 0x00000200, /* DENALI_CTL_295_DATA */ + 0x00000176, /* DENALI_CTL_296_DATA */ + 0x00000e9c, /* DENALI_CTL_297_DATA */ + 0x02020205, /* DENALI_CTL_298_DATA */ + 0x03030202, /* DENALI_CTL_299_DATA */ + 0x00000018, /* DENALI_CTL_300_DATA */ + 0x00000000, /* DENALI_CTL_301_DATA */ + 0x00000000, /* DENALI_CTL_302_DATA */ + 0x00001403, /* DENALI_CTL_303_DATA */ + 0x00000000, /* DENALI_CTL_304_DATA */ + 0x00000000, /* DENALI_CTL_305_DATA */ + 0x00000000, /* DENALI_CTL_306_DATA */ + 0x00030000, /* DENALI_CTL_307_DATA */ + 0x000a001c, /* DENALI_CTL_308_DATA */ + 0x000e0020, /* DENALI_CTL_309_DATA */ + 0x00060018, /* DENALI_CTL_310_DATA */ + 0x00000000, /* DENALI_CTL_311_DATA */ + 0x00000000, /* DENALI_CTL_312_DATA */ + 0x02000000, /* DENALI_CTL_313_DATA */ + 0x00090305, /* DENALI_CTL_314_DATA */ + 0x00050101, /* DENALI_CTL_315_DATA */ + 0x00000000, /* DENALI_CTL_316_DATA */ + 0x00000000, /* DENALI_CTL_317_DATA */ + 0x00000000, /* DENALI_CTL_318_DATA */ + 0x00000000, /* DENALI_CTL_319_DATA */ + 0x00000000, /* DENALI_CTL_320_DATA */ + 0x00000000, /* DENALI_CTL_321_DATA */ + 0x00000000, /* DENALI_CTL_322_DATA */ + 0x00000000, /* DENALI_CTL_323_DATA */ + 0x01000001, /* DENALI_CTL_324_DATA */ + 0x01010101, /* DENALI_CTL_325_DATA */ + 0x01000101, /* DENALI_CTL_326_DATA */ + 0x01000100, /* DENALI_CTL_327_DATA */ + 0x00010001, /* DENALI_CTL_328_DATA */ + 0x00010002, /* DENALI_CTL_329_DATA */ + 0x00020100, /* DENALI_CTL_330_DATA */ + 0x00000002 /* DENALI_CTL_331_DATA */ + } + }, + { + { + 0x00000b00, /* DENALI_PI_00_DATA */ + 0x00000000, /* DENALI_PI_01_DATA */ + 0x000002ec, /* DENALI_PI_02_DATA */ + 0x00000176, /* DENALI_PI_03_DATA */ + 0x000030a0, /* DENALI_PI_04_DATA */ + 0x00001850, /* DENALI_PI_05_DATA */ + 0x00001840, /* DENALI_PI_06_DATA */ + 0x01760c20, /* DENALI_PI_07_DATA */ + 0x00000200, /* DENALI_PI_08_DATA */ + 0x00000200, /* DENALI_PI_09_DATA */ + 0x00000200, /* DENALI_PI_10_DATA */ + 0x00000200, /* DENALI_PI_11_DATA */ + 0x00001850, /* DENALI_PI_12_DATA */ + 0x00000200, /* DENALI_PI_13_DATA */ + 0x00000200, /* DENALI_PI_14_DATA */ + 0x00000200, /* DENALI_PI_15_DATA */ + 0x00000200, /* DENALI_PI_16_DATA */ + 0x00000c20, /* DENALI_PI_17_DATA */ + 0x00000200, /* DENALI_PI_18_DATA */ + 0x00000200, /* DENALI_PI_19_DATA */ + 0x00000200, /* DENALI_PI_20_DATA */ + 0x00000200, /* DENALI_PI_21_DATA */ + 0x00010000, /* DENALI_PI_22_DATA */ + 0x00000007, /* DENALI_PI_23_DATA */ + 0x01000001, /* DENALI_PI_24_DATA */ + 0x00000000, /* DENALI_PI_25_DATA */ + 0x3fffffff, /* DENALI_PI_26_DATA */ + 0x00000000, /* DENALI_PI_27_DATA */ + 0x00000000, /* DENALI_PI_28_DATA */ + 0x00000000, /* DENALI_PI_29_DATA */ + 0x00000000, /* DENALI_PI_30_DATA */ + 0x00000000, /* DENALI_PI_31_DATA */ + 0x00000000, /* DENALI_PI_32_DATA */ + 0x00000000, /* DENALI_PI_33_DATA */ + 0x00000000, /* DENALI_PI_34_DATA */ + 0x00000000, /* DENALI_PI_35_DATA */ + 0x00000000, /* DENALI_PI_36_DATA */ + 0x00000000, /* DENALI_PI_37_DATA */ + 0x00000000, /* DENALI_PI_38_DATA */ + 0x00000000, /* DENALI_PI_39_DATA */ + 0x00000000, /* DENALI_PI_40_DATA */ + 0x0f000101, /* DENALI_PI_41_DATA */ + 0x082b3223, /* DENALI_PI_42_DATA */ + 0x080c0004, /* DENALI_PI_43_DATA */ + 0x00061c00, /* DENALI_PI_44_DATA */ + 0x00000214, /* DENALI_PI_45_DATA */ + 0x00bb0007, /* DENALI_PI_46_DATA */ + 0x0c280068, /* DENALI_PI_47_DATA */ + 0x06100034, /* DENALI_PI_48_DATA */ + 0x00000500, /* DENALI_PI_49_DATA */ + 0x00000000, /* DENALI_PI_50_DATA */ + 0x00000000, /* DENALI_PI_51_DATA */ + 0x00000000, /* DENALI_PI_52_DATA */ + 0x00000000, /* DENALI_PI_53_DATA */ + 0x00000000, /* DENALI_PI_54_DATA */ + 0x00000000, /* DENALI_PI_55_DATA */ + 0x00000000, /* DENALI_PI_56_DATA */ + 0x00000000, /* DENALI_PI_57_DATA */ + 0x04040100, /* DENALI_PI_58_DATA */ + 0x0a000004, /* DENALI_PI_59_DATA */ + 0x00000128, /* DENALI_PI_60_DATA */ + 0x00000000, /* DENALI_PI_61_DATA */ + 0x0003000f, /* DENALI_PI_62_DATA */ + 0x00000018, /* DENALI_PI_63_DATA */ + 0x00000000, /* DENALI_PI_64_DATA */ + 0x00000000, /* DENALI_PI_65_DATA */ + 0x00060002, /* DENALI_PI_66_DATA */ + 0x00010001, /* DENALI_PI_67_DATA */ + 0x00000101, /* DENALI_PI_68_DATA */ + 0x00020001, /* DENALI_PI_69_DATA */ + 0x00080004, /* DENALI_PI_70_DATA */ + 0x00000000, /* DENALI_PI_71_DATA */ + 0x05030000, /* DENALI_PI_72_DATA */ + 0x070a0404, /* DENALI_PI_73_DATA */ + 0x00000000, /* DENALI_PI_74_DATA */ + 0x00000000, /* DENALI_PI_75_DATA */ + 0x00000000, /* DENALI_PI_76_DATA */ + 0x000f0f00, /* DENALI_PI_77_DATA */ + 0x0000001e, /* DENALI_PI_78_DATA */ + 0x00000000, /* DENALI_PI_79_DATA */ + 0x01010300, /* DENALI_PI_80_DATA */ + 0x00000000, /* DENALI_PI_81_DATA */ + 0x00000000, /* DENALI_PI_82_DATA */ + 0x01000000, /* DENALI_PI_83_DATA */ + 0x00000101, /* DENALI_PI_84_DATA */ + 0x55555a5a, /* DENALI_PI_85_DATA */ + 0x55555a5a, /* DENALI_PI_86_DATA */ + 0x55555a5a, /* DENALI_PI_87_DATA */ + 0x55555a5a, /* DENALI_PI_88_DATA */ + 0x0c050001, /* DENALI_PI_89_DATA */ + 0x06020009, /* DENALI_PI_90_DATA */ + 0x00010004, /* DENALI_PI_91_DATA */ + 0x00000203, /* DENALI_PI_92_DATA */ + 0x00030000, /* DENALI_PI_93_DATA */ + 0x170f0000, /* DENALI_PI_94_DATA */ + 0x00060018, /* DENALI_PI_95_DATA */ + 0x000e0020, /* DENALI_PI_96_DATA */ + 0x000a001c, /* DENALI_PI_97_DATA */ + 0x00000000, /* DENALI_PI_98_DATA */ + 0x00000000, /* DENALI_PI_99_DATA */ + 0x00000100, /* DENALI_PI_100_DATA */ + 0x140a0000, /* DENALI_PI_101_DATA */ + 0x000d010a, /* DENALI_PI_102_DATA */ + 0x0100c802, /* DENALI_PI_103_DATA */ + 0x010a0064, /* DENALI_PI_104_DATA */ + 0x000e0100, /* DENALI_PI_105_DATA */ + 0x0100000e, /* DENALI_PI_106_DATA */ + 0x00c900c9, /* DENALI_PI_107_DATA */ + 0x00650100, /* DENALI_PI_108_DATA */ + 0x1e1a0065, /* DENALI_PI_109_DATA */ + 0x10010204, /* DENALI_PI_110_DATA */ + 0x06070605, /* DENALI_PI_111_DATA */ + 0x20000202, /* DENALI_PI_112_DATA */ + 0x00201000, /* DENALI_PI_113_DATA */ + 0x00201000, /* DENALI_PI_114_DATA */ + 0x04041000, /* DENALI_PI_115_DATA */ + 0x10020100, /* DENALI_PI_116_DATA */ + 0x0003010c, /* DENALI_PI_117_DATA */ + 0x004b004a, /* DENALI_PI_118_DATA */ + 0x1a0f0000, /* DENALI_PI_119_DATA */ + 0x0102041e, /* DENALI_PI_120_DATA */ + 0x34000000, /* DENALI_PI_121_DATA */ + 0x00000000, /* DENALI_PI_122_DATA */ + 0x00000000, /* DENALI_PI_123_DATA */ + 0x00010000, /* DENALI_PI_124_DATA */ + 0x00000400, /* DENALI_PI_125_DATA */ + 0x00310000, /* DENALI_PI_126_DATA */ + 0x004d4d00, /* DENALI_PI_127_DATA */ + 0x00120024, /* DENALI_PI_128_DATA */ + 0x4d000031, /* DENALI_PI_129_DATA */ + 0x0000144d, /* DENALI_PI_130_DATA */ + 0x00310009, /* DENALI_PI_131_DATA */ + 0x004d4d00, /* DENALI_PI_132_DATA */ + 0x00000004, /* DENALI_PI_133_DATA */ + 0x4d000031, /* DENALI_PI_134_DATA */ + 0x0000244d, /* DENALI_PI_135_DATA */ + 0x00310012, /* DENALI_PI_136_DATA */ + 0x004d4d00, /* DENALI_PI_137_DATA */ + 0x00090014, /* DENALI_PI_138_DATA */ + 0x4d000031, /* DENALI_PI_139_DATA */ + 0x0004004d, /* DENALI_PI_140_DATA */ + 0x00310000, /* DENALI_PI_141_DATA */ + 0x004d4d00, /* DENALI_PI_142_DATA */ + 0x00120024, /* DENALI_PI_143_DATA */ + 0x4d000031, /* DENALI_PI_144_DATA */ + 0x0000144d, /* DENALI_PI_145_DATA */ + 0x00310009, /* DENALI_PI_146_DATA */ + 0x004d4d00, /* DENALI_PI_147_DATA */ + 0x00000004, /* DENALI_PI_148_DATA */ + 0x4d000031, /* DENALI_PI_149_DATA */ + 0x0000244d, /* DENALI_PI_150_DATA */ + 0x00310012, /* DENALI_PI_151_DATA */ + 0x004d4d00, /* DENALI_PI_152_DATA */ + 0x00090014, /* DENALI_PI_153_DATA */ + 0x4d000031, /* DENALI_PI_154_DATA */ + 0x0200004d, /* DENALI_PI_155_DATA */ + 0x00c8000d, /* DENALI_PI_156_DATA */ + 0x08080064, /* DENALI_PI_157_DATA */ + 0x040a0404, /* DENALI_PI_158_DATA */ + 0x03000d92, /* DENALI_PI_159_DATA */ + 0x010a2001, /* DENALI_PI_160_DATA */ + 0x0f11080a, /* DENALI_PI_161_DATA */ + 0x0000110a, /* DENALI_PI_162_DATA */ + 0x2200d92e, /* DENALI_PI_163_DATA */ + 0x080c2003, /* DENALI_PI_164_DATA */ + 0x0809080a, /* DENALI_PI_165_DATA */ + 0x00000a0a, /* DENALI_PI_166_DATA */ + 0x11006c97, /* DENALI_PI_167_DATA */ + 0x040a2002, /* DENALI_PI_168_DATA */ + 0x0200020a, /* DENALI_PI_169_DATA */ + 0x02000200, /* DENALI_PI_170_DATA */ + 0x02000200, /* DENALI_PI_171_DATA */ + 0x02000200, /* DENALI_PI_172_DATA */ + 0x02000200, /* DENALI_PI_173_DATA */ + 0x00000000, /* DENALI_PI_174_DATA */ + 0x00000000, /* DENALI_PI_175_DATA */ + 0x00000000, /* DENALI_PI_176_DATA */ + 0x00000000, /* DENALI_PI_177_DATA */ + 0x00000000, /* DENALI_PI_178_DATA */ + 0x00000000, /* DENALI_PI_179_DATA */ + 0x00000000, /* DENALI_PI_180_DATA */ + 0x00000000, /* DENALI_PI_181_DATA */ + 0x00000000, /* DENALI_PI_182_DATA */ + 0x00000000, /* DENALI_PI_183_DATA */ + 0x00000000, /* DENALI_PI_184_DATA */ + 0x00000000, /* DENALI_PI_185_DATA */ + 0x01000400, /* DENALI_PI_186_DATA */ + 0x00017600, /* DENALI_PI_187_DATA */ + 0x00000e9c, /* DENALI_PI_188_DATA */ + 0x00001850, /* DENALI_PI_189_DATA */ + 0x0000f320, /* DENALI_PI_190_DATA */ + 0x00000c20, /* DENALI_PI_191_DATA */ + 0x00007940, /* DENALI_PI_192_DATA */ + 0x08000000, /* DENALI_PI_193_DATA */ + 0x00000100, /* DENALI_PI_194_DATA */ + 0x00000000, /* DENALI_PI_195_DATA */ + 0x00000000, /* DENALI_PI_196_DATA */ + 0x00000000, /* DENALI_PI_197_DATA */ + 0x00000000, /* DENALI_PI_198_DATA */ + 0x00000002 /* DENALI_PI_199_DATA */ + } + }, + { + { + 0x76543210, /* DENALI_PHY_00_DATA */ + 0x0004f008, /* DENALI_PHY_01_DATA */ + 0x00020119, /* DENALI_PHY_02_DATA */ + 0x00000000, /* DENALI_PHY_03_DATA */ + 0x00000000, /* DENALI_PHY_04_DATA */ + 0x00010000, /* DENALI_PHY_05_DATA */ + 0x01665555, /* DENALI_PHY_06_DATA */ + 0x03665555, /* DENALI_PHY_07_DATA */ + 0x00010f00, /* DENALI_PHY_08_DATA */ + 0x05010200, /* DENALI_PHY_09_DATA */ + 0x00000002, /* DENALI_PHY_10_DATA */ + 0x00170180, /* DENALI_PHY_11_DATA */ + 0x00cc0201, /* DENALI_PHY_12_DATA */ + 0x00030066, /* DENALI_PHY_13_DATA */ + 0x00000000, /* DENALI_PHY_14_DATA */ + 0x00000000, /* DENALI_PHY_15_DATA */ + 0x00000000, /* DENALI_PHY_16_DATA */ + 0x00000000, /* DENALI_PHY_17_DATA */ + 0x00000000, /* DENALI_PHY_18_DATA */ + 0x00000000, /* DENALI_PHY_19_DATA */ + 0x00000000, /* DENALI_PHY_20_DATA */ + 0x00000000, /* DENALI_PHY_21_DATA */ + 0x04080000, /* DENALI_PHY_22_DATA */ + 0x04080400, /* DENALI_PHY_23_DATA */ + 0x30000000, /* DENALI_PHY_24_DATA */ + 0x0c00c007, /* DENALI_PHY_25_DATA */ + 0x00000100, /* DENALI_PHY_26_DATA */ + 0x00000000, /* DENALI_PHY_27_DATA */ + 0xfd02fe01, /* DENALI_PHY_28_DATA */ + 0xf708fb04, /* DENALI_PHY_29_DATA */ + 0xdf20ef10, /* DENALI_PHY_30_DATA */ + 0x7f80bf40, /* DENALI_PHY_31_DATA */ + 0x0001aaaa, /* DENALI_PHY_32_DATA */ + 0x00000000, /* DENALI_PHY_33_DATA */ + 0x00000000, /* DENALI_PHY_34_DATA */ + 0x00000000, /* DENALI_PHY_35_DATA */ + 0x00000000, /* DENALI_PHY_36_DATA */ + 0x00000000, /* DENALI_PHY_37_DATA */ + 0x00000000, /* DENALI_PHY_38_DATA */ + 0x00000000, /* DENALI_PHY_39_DATA */ + 0x00000000, /* DENALI_PHY_40_DATA */ + 0x00000000, /* DENALI_PHY_41_DATA */ + 0x00000000, /* DENALI_PHY_42_DATA */ + 0x00000000, /* DENALI_PHY_43_DATA */ + 0x00000000, /* DENALI_PHY_44_DATA */ + 0x00000000, /* DENALI_PHY_45_DATA */ + 0x00000000, /* DENALI_PHY_46_DATA */ + 0x00000000, /* DENALI_PHY_47_DATA */ + 0x00000000, /* DENALI_PHY_48_DATA */ + 0x00000000, /* DENALI_PHY_49_DATA */ + 0x00000000, /* DENALI_PHY_50_DATA */ + 0x00000000, /* DENALI_PHY_51_DATA */ + 0x00200000, /* DENALI_PHY_52_DATA */ + 0x00000000, /* DENALI_PHY_53_DATA */ + 0x00000000, /* DENALI_PHY_54_DATA */ + 0x00000000, /* DENALI_PHY_55_DATA */ + 0x00000000, /* DENALI_PHY_56_DATA */ + 0x00000000, /* DENALI_PHY_57_DATA */ + 0x00000000, /* DENALI_PHY_58_DATA */ + 0x02800280, /* DENALI_PHY_59_DATA */ + 0x02800280, /* DENALI_PHY_60_DATA */ + 0x02800280, /* DENALI_PHY_61_DATA */ + 0x02800280, /* DENALI_PHY_62_DATA */ + 0x00000280, /* DENALI_PHY_63_DATA */ + 0x00000000, /* DENALI_PHY_64_DATA */ + 0x00000000, /* DENALI_PHY_65_DATA */ + 0x00000000, /* DENALI_PHY_66_DATA */ + 0x00000000, /* DENALI_PHY_67_DATA */ + 0x00800000, /* DENALI_PHY_68_DATA */ + 0x00800080, /* DENALI_PHY_69_DATA */ + 0x00800080, /* DENALI_PHY_70_DATA */ + 0x00800080, /* DENALI_PHY_71_DATA */ + 0x00800080, /* DENALI_PHY_72_DATA */ + 0x00800080, /* DENALI_PHY_73_DATA */ + 0x00800080, /* DENALI_PHY_74_DATA */ + 0x00800080, /* DENALI_PHY_75_DATA */ + 0x00800080, /* DENALI_PHY_76_DATA */ + 0x01190080, /* DENALI_PHY_77_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ + 0x00000000, /* DENALI_PHY_79_DATA */ + 0x00000000, /* DENALI_PHY_80_DATA */ + 0x00000200, /* DENALI_PHY_81_DATA */ + 0x00000000, /* DENALI_PHY_82_DATA */ + 0x51315152, /* DENALI_PHY_83_DATA */ + 0xc0013150, /* DENALI_PHY_84_DATA */ + 0x020000c0, /* DENALI_PHY_85_DATA */ + 0x00100001, /* DENALI_PHY_86_DATA */ + 0x07054204, /* DENALI_PHY_87_DATA */ + 0x000f0c18, /* DENALI_PHY_88_DATA */ + 0x01000140, /* DENALI_PHY_89_DATA */ + 0x00000c10, /* DENALI_PHY_90_DATA */ + 0x00000000, /* DENALI_PHY_91_DATA */ + 0x00000000, /* DENALI_PHY_92_DATA */ + 0x00000000, /* DENALI_PHY_93_DATA */ + 0x00000000, /* DENALI_PHY_94_DATA */ + 0x00000000, /* DENALI_PHY_95_DATA */ + 0x00000000, /* DENALI_PHY_96_DATA */ + 0x00000000, /* DENALI_PHY_97_DATA */ + 0x00000000, /* DENALI_PHY_98_DATA */ + 0x00000000, /* DENALI_PHY_99_DATA */ + 0x00000000, /* DENALI_PHY_100_DATA */ + 0x00000000, /* DENALI_PHY_101_DATA */ + 0x00000000, /* DENALI_PHY_102_DATA */ + 0x00000000, /* DENALI_PHY_103_DATA */ + 0x00000000, /* DENALI_PHY_104_DATA */ + 0x00000000, /* DENALI_PHY_105_DATA */ + 0x00000000, /* DENALI_PHY_106_DATA */ + 0x00000000, /* DENALI_PHY_107_DATA */ + 0x00000000, /* DENALI_PHY_108_DATA */ + 0x00000000, /* DENALI_PHY_109_DATA */ + 0x00000000, /* DENALI_PHY_110_DATA */ + 0x00000000, /* DENALI_PHY_111_DATA */ + 0x00000000, /* DENALI_PHY_112_DATA */ + 0x00000000, /* DENALI_PHY_113_DATA */ + 0x00000000, /* DENALI_PHY_114_DATA */ + 0x00000000, /* DENALI_PHY_115_DATA */ + 0x00000000, /* DENALI_PHY_116_DATA */ + 0x00000000, /* DENALI_PHY_117_DATA */ + 0x00000000, /* DENALI_PHY_118_DATA */ + 0x00000000, /* DENALI_PHY_119_DATA */ + 0x00000000, /* DENALI_PHY_120_DATA */ + 0x00000000, /* DENALI_PHY_121_DATA */ + 0x00000000, /* DENALI_PHY_122_DATA */ + 0x00000000, /* DENALI_PHY_123_DATA */ + 0x00000000, /* DENALI_PHY_124_DATA */ + 0x00000000, /* DENALI_PHY_125_DATA */ + 0x00000000, /* DENALI_PHY_126_DATA */ + 0x00000000, /* DENALI_PHY_127_DATA */ + 0x76543210, /* DENALI_PHY_128_DATA */ + 0x0004f008, /* DENALI_PHY_129_DATA */ + 0x00020119, /* DENALI_PHY_130_DATA */ + 0x00000000, /* DENALI_PHY_131_DATA */ + 0x00000000, /* DENALI_PHY_132_DATA */ + 0x00010000, /* DENALI_PHY_133_DATA */ + 0x01665555, /* DENALI_PHY_134_DATA */ + 0x03665555, /* DENALI_PHY_135_DATA */ + 0x00010f00, /* DENALI_PHY_136_DATA */ + 0x05010200, /* DENALI_PHY_137_DATA */ + 0x00000002, /* DENALI_PHY_138_DATA */ + 0x00170180, /* DENALI_PHY_139_DATA */ + 0x00cc0201, /* DENALI_PHY_140_DATA */ + 0x00030066, /* DENALI_PHY_141_DATA */ + 0x00000000, /* DENALI_PHY_142_DATA */ + 0x00000000, /* DENALI_PHY_143_DATA */ + 0x00000000, /* DENALI_PHY_144_DATA */ + 0x00000000, /* DENALI_PHY_145_DATA */ + 0x00000000, /* DENALI_PHY_146_DATA */ + 0x00000000, /* DENALI_PHY_147_DATA */ + 0x00000000, /* DENALI_PHY_148_DATA */ + 0x00000000, /* DENALI_PHY_149_DATA */ + 0x04080000, /* DENALI_PHY_150_DATA */ + 0x04080400, /* DENALI_PHY_151_DATA */ + 0x30000000, /* DENALI_PHY_152_DATA */ + 0x0c00c007, /* DENALI_PHY_153_DATA */ + 0x00000100, /* DENALI_PHY_154_DATA */ + 0x00000000, /* DENALI_PHY_155_DATA */ + 0xfd02fe01, /* DENALI_PHY_156_DATA */ + 0xf708fb04, /* DENALI_PHY_157_DATA */ + 0xdf20ef10, /* DENALI_PHY_158_DATA */ + 0x7f80bf40, /* DENALI_PHY_159_DATA */ + 0x0000aaaa, /* DENALI_PHY_160_DATA */ + 0x00000000, /* DENALI_PHY_161_DATA */ + 0x00000000, /* DENALI_PHY_162_DATA */ + 0x00000000, /* DENALI_PHY_163_DATA */ + 0x00000000, /* DENALI_PHY_164_DATA */ + 0x00000000, /* DENALI_PHY_165_DATA */ + 0x00000000, /* DENALI_PHY_166_DATA */ + 0x00000000, /* DENALI_PHY_167_DATA */ + 0x00000000, /* DENALI_PHY_168_DATA */ + 0x00000000, /* DENALI_PHY_169_DATA */ + 0x00000000, /* DENALI_PHY_170_DATA */ + 0x00000000, /* DENALI_PHY_171_DATA */ + 0x00000000, /* DENALI_PHY_172_DATA */ + 0x00000000, /* DENALI_PHY_173_DATA */ + 0x00000000, /* DENALI_PHY_174_DATA */ + 0x00000000, /* DENALI_PHY_175_DATA */ + 0x00000000, /* DENALI_PHY_176_DATA */ + 0x00000000, /* DENALI_PHY_177_DATA */ + 0x00000000, /* DENALI_PHY_178_DATA */ + 0x00000000, /* DENALI_PHY_179_DATA */ + 0x00200000, /* DENALI_PHY_180_DATA */ + 0x00000000, /* DENALI_PHY_181_DATA */ + 0x00000000, /* DENALI_PHY_182_DATA */ + 0x00000000, /* DENALI_PHY_183_DATA */ + 0x00000000, /* DENALI_PHY_184_DATA */ + 0x00000000, /* DENALI_PHY_185_DATA */ + 0x00000000, /* DENALI_PHY_186_DATA */ + 0x02800280, /* DENALI_PHY_187_DATA */ + 0x02800280, /* DENALI_PHY_188_DATA */ + 0x02800280, /* DENALI_PHY_189_DATA */ + 0x02800280, /* DENALI_PHY_190_DATA */ + 0x00000280, /* DENALI_PHY_191_DATA */ + 0x00000000, /* DENALI_PHY_192_DATA */ + 0x00000000, /* DENALI_PHY_193_DATA */ + 0x00000000, /* DENALI_PHY_194_DATA */ + 0x00000000, /* DENALI_PHY_195_DATA */ + 0x00800000, /* DENALI_PHY_196_DATA */ + 0x00800080, /* DENALI_PHY_197_DATA */ + 0x00800080, /* DENALI_PHY_198_DATA */ + 0x00800080, /* DENALI_PHY_199_DATA */ + 0x00800080, /* DENALI_PHY_200_DATA */ + 0x00800080, /* DENALI_PHY_201_DATA */ + 0x00800080, /* DENALI_PHY_202_DATA */ + 0x00800080, /* DENALI_PHY_203_DATA */ + 0x00800080, /* DENALI_PHY_204_DATA */ + 0x01190080, /* DENALI_PHY_205_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ + 0x00000000, /* DENALI_PHY_207_DATA */ + 0x00000000, /* DENALI_PHY_208_DATA */ + 0x00000200, /* DENALI_PHY_209_DATA */ + 0x00000000, /* DENALI_PHY_210_DATA */ + 0x51315152, /* DENALI_PHY_211_DATA */ + 0xc0013150, /* DENALI_PHY_212_DATA */ + 0x020000c0, /* DENALI_PHY_213_DATA */ + 0x00100001, /* DENALI_PHY_214_DATA */ + 0x07054204, /* DENALI_PHY_215_DATA */ + 0x000f0c18, /* DENALI_PHY_216_DATA */ + 0x01000140, /* DENALI_PHY_217_DATA */ + 0x00000c10, /* DENALI_PHY_218_DATA */ + 0x00000000, /* DENALI_PHY_219_DATA */ + 0x00000000, /* DENALI_PHY_220_DATA */ + 0x00000000, /* DENALI_PHY_221_DATA */ + 0x00000000, /* DENALI_PHY_222_DATA */ + 0x00000000, /* DENALI_PHY_223_DATA */ + 0x00000000, /* DENALI_PHY_224_DATA */ + 0x00000000, /* DENALI_PHY_225_DATA */ + 0x00000000, /* DENALI_PHY_226_DATA */ + 0x00000000, /* DENALI_PHY_227_DATA */ + 0x00000000, /* DENALI_PHY_228_DATA */ + 0x00000000, /* DENALI_PHY_229_DATA */ + 0x00000000, /* DENALI_PHY_230_DATA */ + 0x00000000, /* DENALI_PHY_231_DATA */ + 0x00000000, /* DENALI_PHY_232_DATA */ + 0x00000000, /* DENALI_PHY_233_DATA */ + 0x00000000, /* DENALI_PHY_234_DATA */ + 0x00000000, /* DENALI_PHY_235_DATA */ + 0x00000000, /* DENALI_PHY_236_DATA */ + 0x00000000, /* DENALI_PHY_237_DATA */ + 0x00000000, /* DENALI_PHY_238_DATA */ + 0x00000000, /* DENALI_PHY_239_DATA */ + 0x00000000, /* DENALI_PHY_240_DATA */ + 0x00000000, /* DENALI_PHY_241_DATA */ + 0x00000000, /* DENALI_PHY_242_DATA */ + 0x00000000, /* DENALI_PHY_243_DATA */ + 0x00000000, /* DENALI_PHY_244_DATA */ + 0x00000000, /* DENALI_PHY_245_DATA */ + 0x00000000, /* DENALI_PHY_246_DATA */ + 0x00000000, /* DENALI_PHY_247_DATA */ + 0x00000000, /* DENALI_PHY_248_DATA */ + 0x00000000, /* DENALI_PHY_249_DATA */ + 0x00000000, /* DENALI_PHY_250_DATA */ + 0x00000000, /* DENALI_PHY_251_DATA */ + 0x00000000, /* DENALI_PHY_252_DATA */ + 0x00000000, /* DENALI_PHY_253_DATA */ + 0x00000000, /* DENALI_PHY_254_DATA */ + 0x00000000, /* DENALI_PHY_255_DATA */ + 0x76543210, /* DENALI_PHY_256_DATA */ + 0x0004f008, /* DENALI_PHY_257_DATA */ + 0x00020119, /* DENALI_PHY_258_DATA */ + 0x00000000, /* DENALI_PHY_259_DATA */ + 0x00000000, /* DENALI_PHY_260_DATA */ + 0x00010000, /* DENALI_PHY_261_DATA */ + 0x01665555, /* DENALI_PHY_262_DATA */ + 0x03665555, /* DENALI_PHY_263_DATA */ + 0x00010f00, /* DENALI_PHY_264_DATA */ + 0x05010200, /* DENALI_PHY_265_DATA */ + 0x00000002, /* DENALI_PHY_266_DATA */ + 0x00170180, /* DENALI_PHY_267_DATA */ + 0x00cc0201, /* DENALI_PHY_268_DATA */ + 0x00030066, /* DENALI_PHY_269_DATA */ + 0x00000000, /* DENALI_PHY_270_DATA */ + 0x00000000, /* DENALI_PHY_271_DATA */ + 0x00000000, /* DENALI_PHY_272_DATA */ + 0x00000000, /* DENALI_PHY_273_DATA */ + 0x00000000, /* DENALI_PHY_274_DATA */ + 0x00000000, /* DENALI_PHY_275_DATA */ + 0x00000000, /* DENALI_PHY_276_DATA */ + 0x00000000, /* DENALI_PHY_277_DATA */ + 0x04080000, /* DENALI_PHY_278_DATA */ + 0x04080400, /* DENALI_PHY_279_DATA */ + 0x30000000, /* DENALI_PHY_280_DATA */ + 0x0c00c007, /* DENALI_PHY_281_DATA */ + 0x00000100, /* DENALI_PHY_282_DATA */ + 0x00000000, /* DENALI_PHY_283_DATA */ + 0xfd02fe01, /* DENALI_PHY_284_DATA */ + 0xf708fb04, /* DENALI_PHY_285_DATA */ + 0xdf20ef10, /* DENALI_PHY_286_DATA */ + 0x7f80bf40, /* DENALI_PHY_287_DATA */ + 0x0001aaaa, /* DENALI_PHY_288_DATA */ + 0x00000000, /* DENALI_PHY_289_DATA */ + 0x00000000, /* DENALI_PHY_290_DATA */ + 0x00000000, /* DENALI_PHY_291_DATA */ + 0x00000000, /* DENALI_PHY_292_DATA */ + 0x00000000, /* DENALI_PHY_293_DATA */ + 0x00000000, /* DENALI_PHY_294_DATA */ + 0x00000000, /* DENALI_PHY_295_DATA */ + 0x00000000, /* DENALI_PHY_296_DATA */ + 0x00000000, /* DENALI_PHY_297_DATA */ + 0x00000000, /* DENALI_PHY_298_DATA */ + 0x00000000, /* DENALI_PHY_299_DATA */ + 0x00000000, /* DENALI_PHY_300_DATA */ + 0x00000000, /* DENALI_PHY_301_DATA */ + 0x00000000, /* DENALI_PHY_302_DATA */ + 0x00000000, /* DENALI_PHY_303_DATA */ + 0x00000000, /* DENALI_PHY_304_DATA */ + 0x00000000, /* DENALI_PHY_305_DATA */ + 0x00000000, /* DENALI_PHY_306_DATA */ + 0x00000000, /* DENALI_PHY_307_DATA */ + 0x00200000, /* DENALI_PHY_308_DATA */ + 0x00000000, /* DENALI_PHY_309_DATA */ + 0x00000000, /* DENALI_PHY_310_DATA */ + 0x00000000, /* DENALI_PHY_311_DATA */ + 0x00000000, /* DENALI_PHY_312_DATA */ + 0x00000000, /* DENALI_PHY_313_DATA */ + 0x00000000, /* DENALI_PHY_314_DATA */ + 0x02800280, /* DENALI_PHY_315_DATA */ + 0x02800280, /* DENALI_PHY_316_DATA */ + 0x02800280, /* DENALI_PHY_317_DATA */ + 0x02800280, /* DENALI_PHY_318_DATA */ + 0x00000280, /* DENALI_PHY_319_DATA */ + 0x00000000, /* DENALI_PHY_320_DATA */ + 0x00000000, /* DENALI_PHY_321_DATA */ + 0x00000000, /* DENALI_PHY_322_DATA */ + 0x00000000, /* DENALI_PHY_323_DATA */ + 0x00800000, /* DENALI_PHY_324_DATA */ + 0x00800080, /* DENALI_PHY_325_DATA */ + 0x00800080, /* DENALI_PHY_326_DATA */ + 0x00800080, /* DENALI_PHY_327_DATA */ + 0x00800080, /* DENALI_PHY_328_DATA */ + 0x00800080, /* DENALI_PHY_329_DATA */ + 0x00800080, /* DENALI_PHY_330_DATA */ + 0x00800080, /* DENALI_PHY_331_DATA */ + 0x00800080, /* DENALI_PHY_332_DATA */ + 0x01190080, /* DENALI_PHY_333_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ + 0x00000000, /* DENALI_PHY_335_DATA */ + 0x00000000, /* DENALI_PHY_336_DATA */ + 0x00000200, /* DENALI_PHY_337_DATA */ + 0x00000000, /* DENALI_PHY_338_DATA */ + 0x51315152, /* DENALI_PHY_339_DATA */ + 0xc0013150, /* DENALI_PHY_340_DATA */ + 0x020000c0, /* DENALI_PHY_341_DATA */ + 0x00100001, /* DENALI_PHY_342_DATA */ + 0x07054204, /* DENALI_PHY_343_DATA */ + 0x000f0c18, /* DENALI_PHY_344_DATA */ + 0x01000140, /* DENALI_PHY_345_DATA */ + 0x00000c10, /* DENALI_PHY_346_DATA */ + 0x00000000, /* DENALI_PHY_347_DATA */ + 0x00000000, /* DENALI_PHY_348_DATA */ + 0x00000000, /* DENALI_PHY_349_DATA */ + 0x00000000, /* DENALI_PHY_350_DATA */ + 0x00000000, /* DENALI_PHY_351_DATA */ + 0x00000000, /* DENALI_PHY_352_DATA */ + 0x00000000, /* DENALI_PHY_353_DATA */ + 0x00000000, /* DENALI_PHY_354_DATA */ + 0x00000000, /* DENALI_PHY_355_DATA */ + 0x00000000, /* DENALI_PHY_356_DATA */ + 0x00000000, /* DENALI_PHY_357_DATA */ + 0x00000000, /* DENALI_PHY_358_DATA */ + 0x00000000, /* DENALI_PHY_359_DATA */ + 0x00000000, /* DENALI_PHY_360_DATA */ + 0x00000000, /* DENALI_PHY_361_DATA */ + 0x00000000, /* DENALI_PHY_362_DATA */ + 0x00000000, /* DENALI_PHY_363_DATA */ + 0x00000000, /* DENALI_PHY_364_DATA */ + 0x00000000, /* DENALI_PHY_365_DATA */ + 0x00000000, /* DENALI_PHY_366_DATA */ + 0x00000000, /* DENALI_PHY_367_DATA */ + 0x00000000, /* DENALI_PHY_368_DATA */ + 0x00000000, /* DENALI_PHY_369_DATA */ + 0x00000000, /* DENALI_PHY_370_DATA */ + 0x00000000, /* DENALI_PHY_371_DATA */ + 0x00000000, /* DENALI_PHY_372_DATA */ + 0x00000000, /* DENALI_PHY_373_DATA */ + 0x00000000, /* DENALI_PHY_374_DATA */ + 0x00000000, /* DENALI_PHY_375_DATA */ + 0x00000000, /* DENALI_PHY_376_DATA */ + 0x00000000, /* DENALI_PHY_377_DATA */ + 0x00000000, /* DENALI_PHY_378_DATA */ + 0x00000000, /* DENALI_PHY_379_DATA */ + 0x00000000, /* DENALI_PHY_380_DATA */ + 0x00000000, /* DENALI_PHY_381_DATA */ + 0x00000000, /* DENALI_PHY_382_DATA */ + 0x00000000, /* DENALI_PHY_383_DATA */ + 0x76543210, /* DENALI_PHY_384_DATA */ + 0x0004f008, /* DENALI_PHY_385_DATA */ + 0x00020119, /* DENALI_PHY_386_DATA */ + 0x00000000, /* DENALI_PHY_387_DATA */ + 0x00000000, /* DENALI_PHY_388_DATA */ + 0x00010000, /* DENALI_PHY_389_DATA */ + 0x01665555, /* DENALI_PHY_390_DATA */ + 0x03665555, /* DENALI_PHY_391_DATA */ + 0x00010f00, /* DENALI_PHY_392_DATA */ + 0x05010200, /* DENALI_PHY_393_DATA */ + 0x00000002, /* DENALI_PHY_394_DATA */ + 0x00170180, /* DENALI_PHY_395_DATA */ + 0x00cc0201, /* DENALI_PHY_396_DATA */ + 0x00030066, /* DENALI_PHY_397_DATA */ + 0x00000000, /* DENALI_PHY_398_DATA */ + 0x00000000, /* DENALI_PHY_399_DATA */ + 0x00000000, /* DENALI_PHY_400_DATA */ + 0x00000000, /* DENALI_PHY_401_DATA */ + 0x00000000, /* DENALI_PHY_402_DATA */ + 0x00000000, /* DENALI_PHY_403_DATA */ + 0x00000000, /* DENALI_PHY_404_DATA */ + 0x00000000, /* DENALI_PHY_405_DATA */ + 0x04080000, /* DENALI_PHY_406_DATA */ + 0x04080400, /* DENALI_PHY_407_DATA */ + 0x30000000, /* DENALI_PHY_408_DATA */ + 0x0c00c007, /* DENALI_PHY_409_DATA */ + 0x00000100, /* DENALI_PHY_410_DATA */ + 0x00000000, /* DENALI_PHY_411_DATA */ + 0xfd02fe01, /* DENALI_PHY_412_DATA */ + 0xf708fb04, /* DENALI_PHY_413_DATA */ + 0xdf20ef10, /* DENALI_PHY_414_DATA */ + 0x7f80bf40, /* DENALI_PHY_415_DATA */ + 0x0000aaaa, /* DENALI_PHY_416_DATA */ + 0x00000000, /* DENALI_PHY_417_DATA */ + 0x00000000, /* DENALI_PHY_418_DATA */ + 0x00000000, /* DENALI_PHY_419_DATA */ + 0x00000000, /* DENALI_PHY_420_DATA */ + 0x00000000, /* DENALI_PHY_421_DATA */ + 0x00000000, /* DENALI_PHY_422_DATA */ + 0x00000000, /* DENALI_PHY_423_DATA */ + 0x00000000, /* DENALI_PHY_424_DATA */ + 0x00000000, /* DENALI_PHY_425_DATA */ + 0x00000000, /* DENALI_PHY_426_DATA */ + 0x00000000, /* DENALI_PHY_427_DATA */ + 0x00000000, /* DENALI_PHY_428_DATA */ + 0x00000000, /* DENALI_PHY_429_DATA */ + 0x00000000, /* DENALI_PHY_430_DATA */ + 0x00000000, /* DENALI_PHY_431_DATA */ + 0x00000000, /* DENALI_PHY_432_DATA */ + 0x00000000, /* DENALI_PHY_433_DATA */ + 0x00000000, /* DENALI_PHY_434_DATA */ + 0x00000000, /* DENALI_PHY_435_DATA */ + 0x00200000, /* DENALI_PHY_436_DATA */ + 0x00000000, /* DENALI_PHY_437_DATA */ + 0x00000000, /* DENALI_PHY_438_DATA */ + 0x00000000, /* DENALI_PHY_439_DATA */ + 0x00000000, /* DENALI_PHY_440_DATA */ + 0x00000000, /* DENALI_PHY_441_DATA */ + 0x00000000, /* DENALI_PHY_442_DATA */ + 0x02800280, /* DENALI_PHY_443_DATA */ + 0x02800280, /* DENALI_PHY_444_DATA */ + 0x02800280, /* DENALI_PHY_445_DATA */ + 0x02800280, /* DENALI_PHY_446_DATA */ + 0x00000280, /* DENALI_PHY_447_DATA */ + 0x00000000, /* DENALI_PHY_448_DATA */ + 0x00000000, /* DENALI_PHY_449_DATA */ + 0x00000000, /* DENALI_PHY_450_DATA */ + 0x00000000, /* DENALI_PHY_451_DATA */ + 0x00800000, /* DENALI_PHY_452_DATA */ + 0x00800080, /* DENALI_PHY_453_DATA */ + 0x00800080, /* DENALI_PHY_454_DATA */ + 0x00800080, /* DENALI_PHY_455_DATA */ + 0x00800080, /* DENALI_PHY_456_DATA */ + 0x00800080, /* DENALI_PHY_457_DATA */ + 0x00800080, /* DENALI_PHY_458_DATA */ + 0x00800080, /* DENALI_PHY_459_DATA */ + 0x00800080, /* DENALI_PHY_460_DATA */ + 0x01190080, /* DENALI_PHY_461_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ + 0x00000000, /* DENALI_PHY_463_DATA */ + 0x00000000, /* DENALI_PHY_464_DATA */ + 0x00000200, /* DENALI_PHY_465_DATA */ + 0x00000000, /* DENALI_PHY_466_DATA */ + 0x51315152, /* DENALI_PHY_467_DATA */ + 0xc0013150, /* DENALI_PHY_468_DATA */ + 0x020000c0, /* DENALI_PHY_469_DATA */ + 0x00100001, /* DENALI_PHY_470_DATA */ + 0x07054204, /* DENALI_PHY_471_DATA */ + 0x000f0c18, /* DENALI_PHY_472_DATA */ + 0x01000140, /* DENALI_PHY_473_DATA */ + 0x00000c10, /* DENALI_PHY_474_DATA */ + 0x00000000, /* DENALI_PHY_475_DATA */ + 0x00000000, /* DENALI_PHY_476_DATA */ + 0x00000000, /* DENALI_PHY_477_DATA */ + 0x00000000, /* DENALI_PHY_478_DATA */ + 0x00000000, /* DENALI_PHY_479_DATA */ + 0x00000000, /* DENALI_PHY_480_DATA */ + 0x00000000, /* DENALI_PHY_481_DATA */ + 0x00000000, /* DENALI_PHY_482_DATA */ + 0x00000000, /* DENALI_PHY_483_DATA */ + 0x00000000, /* DENALI_PHY_484_DATA */ + 0x00000000, /* DENALI_PHY_485_DATA */ + 0x00000000, /* DENALI_PHY_486_DATA */ + 0x00000000, /* DENALI_PHY_487_DATA */ + 0x00000000, /* DENALI_PHY_488_DATA */ + 0x00000000, /* DENALI_PHY_489_DATA */ + 0x00000000, /* DENALI_PHY_490_DATA */ + 0x00000000, /* DENALI_PHY_491_DATA */ + 0x00000000, /* DENALI_PHY_492_DATA */ + 0x00000000, /* DENALI_PHY_493_DATA */ + 0x00000000, /* DENALI_PHY_494_DATA */ + 0x00000000, /* DENALI_PHY_495_DATA */ + 0x00000000, /* DENALI_PHY_496_DATA */ + 0x00000000, /* DENALI_PHY_497_DATA */ + 0x00000000, /* DENALI_PHY_498_DATA */ + 0x00000000, /* DENALI_PHY_499_DATA */ + 0x00000000, /* DENALI_PHY_500_DATA */ + 0x00000000, /* DENALI_PHY_501_DATA */ + 0x00000000, /* DENALI_PHY_502_DATA */ + 0x00000000, /* DENALI_PHY_503_DATA */ + 0x00000000, /* DENALI_PHY_504_DATA */ + 0x00000000, /* DENALI_PHY_505_DATA */ + 0x00000000, /* DENALI_PHY_506_DATA */ + 0x00000000, /* DENALI_PHY_507_DATA */ + 0x00000000, /* DENALI_PHY_508_DATA */ + 0x00000000, /* DENALI_PHY_509_DATA */ + 0x00000000, /* DENALI_PHY_510_DATA */ + 0x00000000, /* DENALI_PHY_511_DATA */ + 0x00000000, /* DENALI_PHY_512_DATA */ + 0x00000000, /* DENALI_PHY_513_DATA */ + 0x00000000, /* DENALI_PHY_514_DATA */ + 0x00000000, /* DENALI_PHY_515_DATA */ + 0x00000000, /* DENALI_PHY_516_DATA */ + 0x00000000, /* DENALI_PHY_517_DATA */ + 0x00000000, /* DENALI_PHY_518_DATA */ + 0x00000002, /* DENALI_PHY_519_DATA */ + 0x00000000, /* DENALI_PHY_520_DATA */ + 0x00000000, /* DENALI_PHY_521_DATA */ + 0x00000000, /* DENALI_PHY_522_DATA */ + 0x00400320, /* DENALI_PHY_523_DATA */ + 0x00000040, /* DENALI_PHY_524_DATA */ + 0x00dcba98, /* DENALI_PHY_525_DATA */ + 0x00000000, /* DENALI_PHY_526_DATA */ + 0x00dcba98, /* DENALI_PHY_527_DATA */ + 0x01000000, /* DENALI_PHY_528_DATA */ + 0x00020003, /* DENALI_PHY_529_DATA */ + 0x00000000, /* DENALI_PHY_530_DATA */ + 0x00000000, /* DENALI_PHY_531_DATA */ + 0x00000000, /* DENALI_PHY_532_DATA */ + 0x0000002a, /* DENALI_PHY_533_DATA */ + 0x00000015, /* DENALI_PHY_534_DATA */ + 0x00000015, /* DENALI_PHY_535_DATA */ + 0x0000002a, /* DENALI_PHY_536_DATA */ + 0x00000033, /* DENALI_PHY_537_DATA */ + 0x0000000c, /* DENALI_PHY_538_DATA */ + 0x0000000c, /* DENALI_PHY_539_DATA */ + 0x00000033, /* DENALI_PHY_540_DATA */ + 0x0a418820, /* DENALI_PHY_541_DATA */ + 0x003f0000, /* DENALI_PHY_542_DATA */ + 0x0000003f, /* DENALI_PHY_543_DATA */ + 0x00030055, /* DENALI_PHY_544_DATA */ + 0x03000300, /* DENALI_PHY_545_DATA */ + 0x03000300, /* DENALI_PHY_546_DATA */ + 0x00000300, /* DENALI_PHY_547_DATA */ + 0x42080010, /* DENALI_PHY_548_DATA */ + 0x00000003, /* DENALI_PHY_549_DATA */ + 0x00000000, /* DENALI_PHY_550_DATA */ + 0x00000000, /* DENALI_PHY_551_DATA */ + 0x00000000, /* DENALI_PHY_552_DATA */ + 0x00000000, /* DENALI_PHY_553_DATA */ + 0x00000000, /* DENALI_PHY_554_DATA */ + 0x00000000, /* DENALI_PHY_555_DATA */ + 0x00000000, /* DENALI_PHY_556_DATA */ + 0x00000000, /* DENALI_PHY_557_DATA */ + 0x00000000, /* DENALI_PHY_558_DATA */ + 0x00000000, /* DENALI_PHY_559_DATA */ + 0x00000000, /* DENALI_PHY_560_DATA */ + 0x00000000, /* DENALI_PHY_561_DATA */ + 0x00000000, /* DENALI_PHY_562_DATA */ + 0x00000000, /* DENALI_PHY_563_DATA */ + 0x00000000, /* DENALI_PHY_564_DATA */ + 0x00000000, /* DENALI_PHY_565_DATA */ + 0x00000000, /* DENALI_PHY_566_DATA */ + 0x00000000, /* DENALI_PHY_567_DATA */ + 0x00000000, /* DENALI_PHY_568_DATA */ + 0x00000000, /* DENALI_PHY_569_DATA */ + 0x00000000, /* DENALI_PHY_570_DATA */ + 0x00000000, /* DENALI_PHY_571_DATA */ + 0x00000000, /* DENALI_PHY_572_DATA */ + 0x00000000, /* DENALI_PHY_573_DATA */ + 0x00000000, /* DENALI_PHY_574_DATA */ + 0x00000000, /* DENALI_PHY_575_DATA */ + 0x00000000, /* DENALI_PHY_576_DATA */ + 0x00000000, /* DENALI_PHY_577_DATA */ + 0x00000000, /* DENALI_PHY_578_DATA */ + 0x00000000, /* DENALI_PHY_579_DATA */ + 0x00000000, /* DENALI_PHY_580_DATA */ + 0x00000000, /* DENALI_PHY_581_DATA */ + 0x00000000, /* DENALI_PHY_582_DATA */ + 0x00000000, /* DENALI_PHY_583_DATA */ + 0x00000000, /* DENALI_PHY_584_DATA */ + 0x00000000, /* DENALI_PHY_585_DATA */ + 0x00000000, /* DENALI_PHY_586_DATA */ + 0x00000000, /* DENALI_PHY_587_DATA */ + 0x00000000, /* DENALI_PHY_588_DATA */ + 0x00000000, /* DENALI_PHY_589_DATA */ + 0x00000000, /* DENALI_PHY_590_DATA */ + 0x00000000, /* DENALI_PHY_591_DATA */ + 0x00000000, /* DENALI_PHY_592_DATA */ + 0x00000000, /* DENALI_PHY_593_DATA */ + 0x00000000, /* DENALI_PHY_594_DATA */ + 0x00000000, /* DENALI_PHY_595_DATA */ + 0x00000000, /* DENALI_PHY_596_DATA */ + 0x00000000, /* DENALI_PHY_597_DATA */ + 0x00000000, /* DENALI_PHY_598_DATA */ + 0x00000000, /* DENALI_PHY_599_DATA */ + 0x00000000, /* DENALI_PHY_600_DATA */ + 0x00000000, /* DENALI_PHY_601_DATA */ + 0x00000000, /* DENALI_PHY_602_DATA */ + 0x00000000, /* DENALI_PHY_603_DATA */ + 0x00000000, /* DENALI_PHY_604_DATA */ + 0x00000000, /* DENALI_PHY_605_DATA */ + 0x00000000, /* DENALI_PHY_606_DATA */ + 0x00000000, /* DENALI_PHY_607_DATA */ + 0x00000000, /* DENALI_PHY_608_DATA */ + 0x00000000, /* DENALI_PHY_609_DATA */ + 0x00000000, /* DENALI_PHY_610_DATA */ + 0x00000000, /* DENALI_PHY_611_DATA */ + 0x00000000, /* DENALI_PHY_612_DATA */ + 0x00000000, /* DENALI_PHY_613_DATA */ + 0x00000000, /* DENALI_PHY_614_DATA */ + 0x00000000, /* DENALI_PHY_615_DATA */ + 0x00000000, /* DENALI_PHY_616_DATA */ + 0x00000000, /* DENALI_PHY_617_DATA */ + 0x00000000, /* DENALI_PHY_618_DATA */ + 0x00000000, /* DENALI_PHY_619_DATA */ + 0x00000000, /* DENALI_PHY_620_DATA */ + 0x00000000, /* DENALI_PHY_621_DATA */ + 0x00000000, /* DENALI_PHY_622_DATA */ + 0x00000000, /* DENALI_PHY_623_DATA */ + 0x00000000, /* DENALI_PHY_624_DATA */ + 0x00000000, /* DENALI_PHY_625_DATA */ + 0x00000000, /* DENALI_PHY_626_DATA */ + 0x00000000, /* DENALI_PHY_627_DATA */ + 0x00000000, /* DENALI_PHY_628_DATA */ + 0x00000000, /* DENALI_PHY_629_DATA */ + 0x00000000, /* DENALI_PHY_630_DATA */ + 0x00000000, /* DENALI_PHY_631_DATA */ + 0x00000000, /* DENALI_PHY_632_DATA */ + 0x00000000, /* DENALI_PHY_633_DATA */ + 0x00000000, /* DENALI_PHY_634_DATA */ + 0x00000000, /* DENALI_PHY_635_DATA */ + 0x00000000, /* DENALI_PHY_636_DATA */ + 0x00000000, /* DENALI_PHY_637_DATA */ + 0x00000000, /* DENALI_PHY_638_DATA */ + 0x00000000, /* DENALI_PHY_639_DATA */ + 0x00000000, /* DENALI_PHY_640_DATA */ + 0x00000000, /* DENALI_PHY_641_DATA */ + 0x00000000, /* DENALI_PHY_642_DATA */ + 0x00000000, /* DENALI_PHY_643_DATA */ + 0x00000000, /* DENALI_PHY_644_DATA */ + 0x00000000, /* DENALI_PHY_645_DATA */ + 0x00000000, /* DENALI_PHY_646_DATA */ + 0x00000002, /* DENALI_PHY_647_DATA */ + 0x00000000, /* DENALI_PHY_648_DATA */ + 0x00000000, /* DENALI_PHY_649_DATA */ + 0x00000000, /* DENALI_PHY_650_DATA */ + 0x00400320, /* DENALI_PHY_651_DATA */ + 0x00000040, /* DENALI_PHY_652_DATA */ + 0x00000000, /* DENALI_PHY_653_DATA */ + 0x00000000, /* DENALI_PHY_654_DATA */ + 0x00000000, /* DENALI_PHY_655_DATA */ + 0x01000000, /* DENALI_PHY_656_DATA */ + 0x00020003, /* DENALI_PHY_657_DATA */ + 0x00000000, /* DENALI_PHY_658_DATA */ + 0x00000000, /* DENALI_PHY_659_DATA */ + 0x00000000, /* DENALI_PHY_660_DATA */ + 0x0000002a, /* DENALI_PHY_661_DATA */ + 0x00000015, /* DENALI_PHY_662_DATA */ + 0x00000015, /* DENALI_PHY_663_DATA */ + 0x0000002a, /* DENALI_PHY_664_DATA */ + 0x00000033, /* DENALI_PHY_665_DATA */ + 0x0000000c, /* DENALI_PHY_666_DATA */ + 0x0000000c, /* DENALI_PHY_667_DATA */ + 0x00000033, /* DENALI_PHY_668_DATA */ + 0x00000000, /* DENALI_PHY_669_DATA */ + 0x00000000, /* DENALI_PHY_670_DATA */ + 0x00000000, /* DENALI_PHY_671_DATA */ + 0x00030055, /* DENALI_PHY_672_DATA */ + 0x03000300, /* DENALI_PHY_673_DATA */ + 0x03000300, /* DENALI_PHY_674_DATA */ + 0x00000300, /* DENALI_PHY_675_DATA */ + 0x42080010, /* DENALI_PHY_676_DATA */ + 0x00000003, /* DENALI_PHY_677_DATA */ + 0x00000000, /* DENALI_PHY_678_DATA */ + 0x00000000, /* DENALI_PHY_679_DATA */ + 0x00000000, /* DENALI_PHY_680_DATA */ + 0x00000000, /* DENALI_PHY_681_DATA */ + 0x00000000, /* DENALI_PHY_682_DATA */ + 0x00000000, /* DENALI_PHY_683_DATA */ + 0x00000000, /* DENALI_PHY_684_DATA */ + 0x00000000, /* DENALI_PHY_685_DATA */ + 0x00000000, /* DENALI_PHY_686_DATA */ + 0x00000000, /* DENALI_PHY_687_DATA */ + 0x00000000, /* DENALI_PHY_688_DATA */ + 0x00000000, /* DENALI_PHY_689_DATA */ + 0x00000000, /* DENALI_PHY_690_DATA */ + 0x00000000, /* DENALI_PHY_691_DATA */ + 0x00000000, /* DENALI_PHY_692_DATA */ + 0x00000000, /* DENALI_PHY_693_DATA */ + 0x00000000, /* DENALI_PHY_694_DATA */ + 0x00000000, /* DENALI_PHY_695_DATA */ + 0x00000000, /* DENALI_PHY_696_DATA */ + 0x00000000, /* DENALI_PHY_697_DATA */ + 0x00000000, /* DENALI_PHY_698_DATA */ + 0x00000000, /* DENALI_PHY_699_DATA */ + 0x00000000, /* DENALI_PHY_700_DATA */ + 0x00000000, /* DENALI_PHY_701_DATA */ + 0x00000000, /* DENALI_PHY_702_DATA */ + 0x00000000, /* DENALI_PHY_703_DATA */ + 0x00000000, /* DENALI_PHY_704_DATA */ + 0x00000000, /* DENALI_PHY_705_DATA */ + 0x00000000, /* DENALI_PHY_706_DATA */ + 0x00000000, /* DENALI_PHY_707_DATA */ + 0x00000000, /* DENALI_PHY_708_DATA */ + 0x00000000, /* DENALI_PHY_709_DATA */ + 0x00000000, /* DENALI_PHY_710_DATA */ + 0x00000000, /* DENALI_PHY_711_DATA */ + 0x00000000, /* DENALI_PHY_712_DATA */ + 0x00000000, /* DENALI_PHY_713_DATA */ + 0x00000000, /* DENALI_PHY_714_DATA */ + 0x00000000, /* DENALI_PHY_715_DATA */ + 0x00000000, /* DENALI_PHY_716_DATA */ + 0x00000000, /* DENALI_PHY_717_DATA */ + 0x00000000, /* DENALI_PHY_718_DATA */ + 0x00000000, /* DENALI_PHY_719_DATA */ + 0x00000000, /* DENALI_PHY_720_DATA */ + 0x00000000, /* DENALI_PHY_721_DATA */ + 0x00000000, /* DENALI_PHY_722_DATA */ + 0x00000000, /* DENALI_PHY_723_DATA */ + 0x00000000, /* DENALI_PHY_724_DATA */ + 0x00000000, /* DENALI_PHY_725_DATA */ + 0x00000000, /* DENALI_PHY_726_DATA */ + 0x00000000, /* DENALI_PHY_727_DATA */ + 0x00000000, /* DENALI_PHY_728_DATA */ + 0x00000000, /* DENALI_PHY_729_DATA */ + 0x00000000, /* DENALI_PHY_730_DATA */ + 0x00000000, /* DENALI_PHY_731_DATA */ + 0x00000000, /* DENALI_PHY_732_DATA */ + 0x00000000, /* DENALI_PHY_733_DATA */ + 0x00000000, /* DENALI_PHY_734_DATA */ + 0x00000000, /* DENALI_PHY_735_DATA */ + 0x00000000, /* DENALI_PHY_736_DATA */ + 0x00000000, /* DENALI_PHY_737_DATA */ + 0x00000000, /* DENALI_PHY_738_DATA */ + 0x00000000, /* DENALI_PHY_739_DATA */ + 0x00000000, /* DENALI_PHY_740_DATA */ + 0x00000000, /* DENALI_PHY_741_DATA */ + 0x00000000, /* DENALI_PHY_742_DATA */ + 0x00000000, /* DENALI_PHY_743_DATA */ + 0x00000000, /* DENALI_PHY_744_DATA */ + 0x00000000, /* DENALI_PHY_745_DATA */ + 0x00000000, /* DENALI_PHY_746_DATA */ + 0x00000000, /* DENALI_PHY_747_DATA */ + 0x00000000, /* DENALI_PHY_748_DATA */ + 0x00000000, /* DENALI_PHY_749_DATA */ + 0x00000000, /* DENALI_PHY_750_DATA */ + 0x00000000, /* DENALI_PHY_751_DATA */ + 0x00000000, /* DENALI_PHY_752_DATA */ + 0x00000000, /* DENALI_PHY_753_DATA */ + 0x00000000, /* DENALI_PHY_754_DATA */ + 0x00000000, /* DENALI_PHY_755_DATA */ + 0x00000000, /* DENALI_PHY_756_DATA */ + 0x00000000, /* DENALI_PHY_757_DATA */ + 0x00000000, /* DENALI_PHY_758_DATA */ + 0x00000000, /* DENALI_PHY_759_DATA */ + 0x00000000, /* DENALI_PHY_760_DATA */ + 0x00000000, /* DENALI_PHY_761_DATA */ + 0x00000000, /* DENALI_PHY_762_DATA */ + 0x00000000, /* DENALI_PHY_763_DATA */ + 0x00000000, /* DENALI_PHY_764_DATA */ + 0x00000000, /* DENALI_PHY_765_DATA */ + 0x00000000, /* DENALI_PHY_766_DATA */ + 0x00000000, /* DENALI_PHY_767_DATA */ + 0x00000000, /* DENALI_PHY_768_DATA */ + 0x00000000, /* DENALI_PHY_769_DATA */ + 0x00000000, /* DENALI_PHY_770_DATA */ + 0x00000000, /* DENALI_PHY_771_DATA */ + 0x00000000, /* DENALI_PHY_772_DATA */ + 0x00000000, /* DENALI_PHY_773_DATA */ + 0x00000000, /* DENALI_PHY_774_DATA */ + 0x00000002, /* DENALI_PHY_775_DATA */ + 0x00000000, /* DENALI_PHY_776_DATA */ + 0x00000000, /* DENALI_PHY_777_DATA */ + 0x00000000, /* DENALI_PHY_778_DATA */ + 0x00400320, /* DENALI_PHY_779_DATA */ + 0x00000040, /* DENALI_PHY_780_DATA */ + 0x00000000, /* DENALI_PHY_781_DATA */ + 0x00000000, /* DENALI_PHY_782_DATA */ + 0x00000000, /* DENALI_PHY_783_DATA */ + 0x01000000, /* DENALI_PHY_784_DATA */ + 0x00020003, /* DENALI_PHY_785_DATA */ + 0x00000000, /* DENALI_PHY_786_DATA */ + 0x00000000, /* DENALI_PHY_787_DATA */ + 0x00000000, /* DENALI_PHY_788_DATA */ + 0x0000002a, /* DENALI_PHY_789_DATA */ + 0x00000015, /* DENALI_PHY_790_DATA */ + 0x00000015, /* DENALI_PHY_791_DATA */ + 0x0000002a, /* DENALI_PHY_792_DATA */ + 0x00000033, /* DENALI_PHY_793_DATA */ + 0x0000000c, /* DENALI_PHY_794_DATA */ + 0x0000000c, /* DENALI_PHY_795_DATA */ + 0x00000033, /* DENALI_PHY_796_DATA */ + 0x1ee6b16a, /* DENALI_PHY_797_DATA */ + 0x10000000, /* DENALI_PHY_798_DATA */ + 0x00000000, /* DENALI_PHY_799_DATA */ + 0x00030055, /* DENALI_PHY_800_DATA */ + 0x03000300, /* DENALI_PHY_801_DATA */ + 0x03000300, /* DENALI_PHY_802_DATA */ + 0x00000300, /* DENALI_PHY_803_DATA */ + 0x42080010, /* DENALI_PHY_804_DATA */ + 0x00000003, /* DENALI_PHY_805_DATA */ + 0x00000000, /* DENALI_PHY_806_DATA */ + 0x00000000, /* DENALI_PHY_807_DATA */ + 0x00000000, /* DENALI_PHY_808_DATA */ + 0x00000000, /* DENALI_PHY_809_DATA */ + 0x00000000, /* DENALI_PHY_810_DATA */ + 0x00000000, /* DENALI_PHY_811_DATA */ + 0x00000000, /* DENALI_PHY_812_DATA */ + 0x00000000, /* DENALI_PHY_813_DATA */ + 0x00000000, /* DENALI_PHY_814_DATA */ + 0x00000000, /* DENALI_PHY_815_DATA */ + 0x00000000, /* DENALI_PHY_816_DATA */ + 0x00000000, /* DENALI_PHY_817_DATA */ + 0x00000000, /* DENALI_PHY_818_DATA */ + 0x00000000, /* DENALI_PHY_819_DATA */ + 0x00000000, /* DENALI_PHY_820_DATA */ + 0x00000000, /* DENALI_PHY_821_DATA */ + 0x00000000, /* DENALI_PHY_822_DATA */ + 0x00000000, /* DENALI_PHY_823_DATA */ + 0x00000000, /* DENALI_PHY_824_DATA */ + 0x00000000, /* DENALI_PHY_825_DATA */ + 0x00000000, /* DENALI_PHY_826_DATA */ + 0x00000000, /* DENALI_PHY_827_DATA */ + 0x00000000, /* DENALI_PHY_828_DATA */ + 0x00000000, /* DENALI_PHY_829_DATA */ + 0x00000000, /* DENALI_PHY_830_DATA */ + 0x00000000, /* DENALI_PHY_831_DATA */ + 0x00000000, /* DENALI_PHY_832_DATA */ + 0x00000000, /* DENALI_PHY_833_DATA */ + 0x00000000, /* DENALI_PHY_834_DATA */ + 0x00000000, /* DENALI_PHY_835_DATA */ + 0x00000000, /* DENALI_PHY_836_DATA */ + 0x00000000, /* DENALI_PHY_837_DATA */ + 0x00000000, /* DENALI_PHY_838_DATA */ + 0x00000000, /* DENALI_PHY_839_DATA */ + 0x00000000, /* DENALI_PHY_840_DATA */ + 0x00000000, /* DENALI_PHY_841_DATA */ + 0x00000000, /* DENALI_PHY_842_DATA */ + 0x00000000, /* DENALI_PHY_843_DATA */ + 0x00000000, /* DENALI_PHY_844_DATA */ + 0x00000000, /* DENALI_PHY_845_DATA */ + 0x00000000, /* DENALI_PHY_846_DATA */ + 0x00000000, /* DENALI_PHY_847_DATA */ + 0x00000000, /* DENALI_PHY_848_DATA */ + 0x00000000, /* DENALI_PHY_849_DATA */ + 0x00000000, /* DENALI_PHY_850_DATA */ + 0x00000000, /* DENALI_PHY_851_DATA */ + 0x00000000, /* DENALI_PHY_852_DATA */ + 0x00000000, /* DENALI_PHY_853_DATA */ + 0x00000000, /* DENALI_PHY_854_DATA */ + 0x00000000, /* DENALI_PHY_855_DATA */ + 0x00000000, /* DENALI_PHY_856_DATA */ + 0x00000000, /* DENALI_PHY_857_DATA */ + 0x00000000, /* DENALI_PHY_858_DATA */ + 0x00000000, /* DENALI_PHY_859_DATA */ + 0x00000000, /* DENALI_PHY_860_DATA */ + 0x00000000, /* DENALI_PHY_861_DATA */ + 0x00000000, /* DENALI_PHY_862_DATA */ + 0x00000000, /* DENALI_PHY_863_DATA */ + 0x00000000, /* DENALI_PHY_864_DATA */ + 0x00000000, /* DENALI_PHY_865_DATA */ + 0x00000000, /* DENALI_PHY_866_DATA */ + 0x00000000, /* DENALI_PHY_867_DATA */ + 0x00000000, /* DENALI_PHY_868_DATA */ + 0x00000000, /* DENALI_PHY_869_DATA */ + 0x00000000, /* DENALI_PHY_870_DATA */ + 0x00000000, /* DENALI_PHY_871_DATA */ + 0x00000000, /* DENALI_PHY_872_DATA */ + 0x00000000, /* DENALI_PHY_873_DATA */ + 0x00000000, /* DENALI_PHY_874_DATA */ + 0x00000000, /* DENALI_PHY_875_DATA */ + 0x00000000, /* DENALI_PHY_876_DATA */ + 0x00000000, /* DENALI_PHY_877_DATA */ + 0x00000000, /* DENALI_PHY_878_DATA */ + 0x00000000, /* DENALI_PHY_879_DATA */ + 0x00000000, /* DENALI_PHY_880_DATA */ + 0x00000000, /* DENALI_PHY_881_DATA */ + 0x00000000, /* DENALI_PHY_882_DATA */ + 0x00000000, /* DENALI_PHY_883_DATA */ + 0x00000000, /* DENALI_PHY_884_DATA */ + 0x00000000, /* DENALI_PHY_885_DATA */ + 0x00000000, /* DENALI_PHY_886_DATA */ + 0x00000000, /* DENALI_PHY_887_DATA */ + 0x00000000, /* DENALI_PHY_888_DATA */ + 0x00000000, /* DENALI_PHY_889_DATA */ + 0x00000000, /* DENALI_PHY_890_DATA */ + 0x00000000, /* DENALI_PHY_891_DATA */ + 0x00000000, /* DENALI_PHY_892_DATA */ + 0x00000000, /* DENALI_PHY_893_DATA */ + 0x00000000, /* DENALI_PHY_894_DATA */ + 0x00000000, /* DENALI_PHY_895_DATA */ + 0x00000000, /* DENALI_PHY_896_DATA */ + 0x00000000, /* DENALI_PHY_897_DATA */ + 0x00000005, /* DENALI_PHY_898_DATA */ + 0x04000f01, /* DENALI_PHY_899_DATA */ + 0x00020040, /* DENALI_PHY_900_DATA */ + 0x00020055, /* DENALI_PHY_901_DATA */ + 0x00000000, /* DENALI_PHY_902_DATA */ + 0x00000000, /* DENALI_PHY_903_DATA */ + 0x00000000, /* DENALI_PHY_904_DATA */ + 0x00000050, /* DENALI_PHY_905_DATA */ + 0x00000000, /* DENALI_PHY_906_DATA */ + 0x01010100, /* DENALI_PHY_907_DATA */ + 0x00000600, /* DENALI_PHY_908_DATA */ + 0x00000000, /* DENALI_PHY_909_DATA */ + 0x00006400, /* DENALI_PHY_910_DATA */ + 0x01221102, /* DENALI_PHY_911_DATA */ + 0x00000000, /* DENALI_PHY_912_DATA */ + 0x000d1f00, /* DENALI_PHY_913_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_914_DATA */ + 0x0d1f0d1f, /* DENALI_PHY_915_DATA */ + 0x00030003, /* DENALI_PHY_916_DATA */ + 0x03000300, /* DENALI_PHY_917_DATA */ + 0x00000300, /* DENALI_PHY_918_DATA */ + 0x01221102, /* DENALI_PHY_919_DATA */ + 0x00000000, /* DENALI_PHY_920_DATA */ + 0x00000000, /* DENALI_PHY_921_DATA */ + 0x03020000, /* DENALI_PHY_922_DATA */ + 0x00000001, /* DENALI_PHY_923_DATA */ + 0x00000411, /* DENALI_PHY_924_DATA */ + 0x00000411, /* DENALI_PHY_925_DATA */ + 0x00000040, /* DENALI_PHY_926_DATA */ + 0x00000040, /* DENALI_PHY_927_DATA */ + 0x00000411, /* DENALI_PHY_928_DATA */ + 0x00000411, /* DENALI_PHY_929_DATA */ + 0x00004410, /* DENALI_PHY_930_DATA */ + 0x00004410, /* DENALI_PHY_931_DATA */ + 0x00004410, /* DENALI_PHY_932_DATA */ + 0x00004410, /* DENALI_PHY_933_DATA */ + 0x00004410, /* DENALI_PHY_934_DATA */ + 0x00000411, /* DENALI_PHY_935_DATA */ + 0x00004410, /* DENALI_PHY_936_DATA */ + 0x00000411, /* DENALI_PHY_937_DATA */ + 0x00004410, /* DENALI_PHY_938_DATA */ + 0x00000411, /* DENALI_PHY_939_DATA */ + 0x00004410, /* DENALI_PHY_940_DATA */ + 0x00000000, /* DENALI_PHY_941_DATA */ + 0x00000000, /* DENALI_PHY_942_DATA */ + 0x00000000, /* DENALI_PHY_943_DATA */ + 0x64000000, /* DENALI_PHY_944_DATA */ + 0x00000000, /* DENALI_PHY_945_DATA */ + 0x00000000, /* DENALI_PHY_946_DATA */ + 0x00000508, /* DENALI_PHY_947_DATA */ + 0x00000000, /* DENALI_PHY_948_DATA */ + 0x00000000, /* DENALI_PHY_949_DATA */ + 0x00000000, /* DENALI_PHY_950_DATA */ + 0x00000000, /* DENALI_PHY_951_DATA */ + 0x00000000, /* DENALI_PHY_952_DATA */ + 0x00000000, /* DENALI_PHY_953_DATA */ + 0xe4000000, /* DENALI_PHY_954_DATA */ + 0x00000000, /* DENALI_PHY_955_DATA */ + 0x00000000, /* DENALI_PHY_956_DATA */ + 0x01010000, /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + } + }, +}, From 1dd1cb6253c3a4326284f4f2a141297d06103e69 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:39 +0530 Subject: [PATCH 084/147] ram: rk3399: Add set_rate sdram rk3399 ops DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index fe79f31cdb3..d67123e57ee 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -74,6 +74,8 @@ struct dram_info { struct sdram_rk3399_ops { int (*data_training)(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *sdram); + int (*set_rate)(struct dram_info *dram, + const struct rk3399_sdram_params *params); }; #if defined(CONFIG_TPL_BUILD) || \ @@ -948,6 +950,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, return 0; } +#if !defined(CONFIG_RAM_RK3399_LPDDR4) static void select_per_cs_training_index(const struct chan_info *chan, u32 rank) { @@ -1368,6 +1371,7 @@ static int data_training(struct dram_info *dram, u32 channel, return 0; } +#endif static void set_ddrconfig(const struct chan_info *chan, const struct rk3399_sdram_params *params, @@ -1487,7 +1491,6 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank, return data_training(dram, channel, params, training_flag); } -#endif static int switch_to_phy_index1(struct dram_info *dram, const struct rk3399_sdram_params *params) @@ -1534,7 +1537,8 @@ static int switch_to_phy_index1(struct dram_info *dram, return 0; } -#if defined(CONFIG_RAM_RK3399_LPDDR4) +#else + static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf) { return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F); @@ -1954,7 +1958,7 @@ static int sdram_init(struct dram_info *dram, params->base.stride = calculate_stride(params); dram_all_config(dram, params); - switch_to_phy_index1(dram, params); + dram->ops->set_rate(dram, params); debug("Finish SDRAM initialization...\n"); return 0; @@ -2002,6 +2006,7 @@ static int conv_of_platdata(struct udevice *dev) static const struct sdram_rk3399_ops rk3399_ops = { #if !defined(CONFIG_RAM_RK3399_LPDDR4) .data_training = default_data_training, + .set_rate = switch_to_phy_index1, #else .data_training = lpddr4_mr_detect, #endif From c36abd087a6f25fed5e1af09124e9bf2b4fc2d73 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:40 +0530 Subject: [PATCH 085/147] ram: rk3399: Add lpddr4 set rate support Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. The lpddr4 set rate sequnce will follow by setting lpddr4 - dq out - ca odt - MR3 - MR12 - MR14 registers sets in sequential order. Here is sameple log about LPDDR4-100 init sequence in Rockpro64: Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride channel 0 training pass channel 1 training pass change freq to 400 MHz 0, 1 channel 0 training pass channel 1 training pass change freq to 800 MHz 1, 0 This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang (Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 673 +++++++++++++++++++++++++++- 1 file changed, 661 insertions(+), 12 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index d67123e57ee..81fc71c051d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -62,6 +63,7 @@ struct dram_info { struct clk ddr_clk; struct rk3399_cru *cru; struct rk3399_grf_regs *grf; + struct rk3399_pmu_regs *pmu; struct rk3399_pmucru *pmucru; struct rk3399_pmusgrf_regs *pmusgrf; struct rk3399_ddr_cic_regs *cic; @@ -75,7 +77,7 @@ struct sdram_rk3399_ops { int (*data_training)(struct dram_info *dram, u32 channel, u8 rank, struct rk3399_sdram_params *sdram); int (*set_rate)(struct dram_info *dram, - const struct rk3399_sdram_params *params); + struct rk3399_sdram_params *params); }; #if defined(CONFIG_TPL_BUILD) || \ @@ -221,6 +223,18 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5) return io; } +static void *get_denali_phy(const struct chan_info *chan, + struct rk3399_sdram_params *params, bool reg) +{ + return reg ? &chan->publ->denali_phy : ¶ms->phy_regs.denali_phy; +} + +static void *get_denali_ctl(const struct chan_info *chan, + struct rk3399_sdram_params *params, bool reg) +{ + return reg ? &chan->pctl->denali_ctl : ¶ms->pctl_regs.denali_ctl; +} + static void *get_ddrc0_con(struct dram_info *dram, u8 channel) { return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1; @@ -574,10 +588,11 @@ static int phy_io_config(const struct chan_info *chan, } static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *params, u32 mr5) + struct rk3399_sdram_params *params, + bool ctl_phy_reg, u32 mr5) { - u32 *denali_phy = chan->publ->denali_phy; - u32 *denali_ctl = chan->pctl->denali_ctl; + u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg); + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_rd_select_p; u32 tsel_idle_select_n, tsel_rd_select_n; @@ -735,7 +750,8 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[928], 0xff, reg_value); /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ - clrsetbits_le32(&denali_phy[937], 0xff, reg_value); + if (!ctl_phy_reg) + clrsetbits_le32(&denali_phy[937], 0xff, reg_value); /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ clrsetbits_le32(&denali_phy[935], 0xff, reg_value); @@ -919,7 +935,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); - set_ds_odt(chan, params, 0); + set_ds_odt(chan, params, true, 0); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 @@ -950,7 +966,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, return 0; } -#if !defined(CONFIG_RAM_RK3399_LPDDR4) static void select_per_cs_training_index(const struct chan_info *chan, u32 rank) { @@ -1308,7 +1323,7 @@ static int data_training(struct dram_info *dram, u32 channel, if (training_flag == PI_FULL_TRAINING) { if (params->base.dramtype == LPDDR4) { - training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | + training_flag = PI_WRITE_LEVELING | PI_READ_GATE_TRAINING | PI_READ_LEVELING | PI_WDQ_LEVELING; } else if (params->base.dramtype == LPDDR3) { @@ -1371,7 +1386,6 @@ static int data_training(struct dram_info *dram, u32 channel, return 0; } -#endif static void set_ddrconfig(const struct chan_info *chan, const struct rk3399_sdram_params *params, @@ -1493,7 +1507,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank, } static int switch_to_phy_index1(struct dram_info *dram, - const struct rk3399_sdram_params *params) + struct rk3399_sdram_params *params) { u32 channel; u32 *denali_phy; @@ -1539,6 +1553,31 @@ static int switch_to_phy_index1(struct dram_info *dram, #else +struct rk3399_sdram_params lpddr4_timings[] = { + #include "sdram-rk3399-lpddr4-400.inc" + #include "sdram-rk3399-lpddr4-800.inc" +}; + +static void *get_denali_pi(const struct chan_info *chan, + struct rk3399_sdram_params *params, bool reg) +{ + return reg ? &chan->pi->denali_pi : ¶ms->pi_regs.denali_pi; +} + +static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl) +{ + u32 lpddr4_phy[] = {1, 0, 0xb}; + + return lpddr4_phy[ctl]; +} + +static u32 lpddr4_get_ctl(struct rk3399_sdram_params *params, u32 phy) +{ + u32 lpddr4_ctl[] = {1, 0, 2}; + + return lpddr4_ctl[phy]; +} + static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf) { return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F); @@ -1756,6 +1795,614 @@ end: return ret; } + +static void set_lpddr4_dq_odt(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl, + bool en, bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + if (!en) + return; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = io->dq_odt; + + switch (ctl) { + case 0: + clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24); + clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24); + + clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16)); + break; + case 1: + clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0); + clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0); + + clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0)); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8)); + clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8)); + + clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16)); + clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0)); + clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16)); + break; + } +} + +static void set_lpddr4_ca_odt(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl, + bool en, bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + if (!en) + return; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = io->ca_odt; + + switch (ctl) { + case 0: + clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28); + clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28); + + clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20); + break; + case 1: + clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4); + + clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12)); + clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12)); + + clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20); + clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4); + clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20); + break; + } +} + +static void set_lpddr4_MR3(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = ((io->pdds << 3) | 1); + + switch (ctl) { + case 0: + clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value); + break; + case 1: + clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value); + clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value); + break; + } +} + +static void set_lpddr4_MR12(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = io->ca_vref; + + switch (ctl) { + case 0: + clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24); + break; + case 1: + clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24); + clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8); + clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24); + break; + } +} + +static void set_lpddr4_MR14(const struct chan_info *chan, + struct rk3399_sdram_params *params, u32 ctl, + bool ctl_phy_reg, u32 mr5) +{ + u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); + u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); + struct io_setting *io; + u32 reg_value; + + io = lpddr4_get_io_settings(params, mr5); + + reg_value = io->dq_vref; + + switch (ctl) { + case 0: + clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0); + break; + case 1: + clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value); + clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value); + + clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16); + break; + case 2: + default: + clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16, + reg_value << 16); + clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16, + reg_value << 16); + + clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0); + clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16); + clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0); + break; + } +} + +static void lpddr4_copy_phy(struct dram_info *dram, + struct rk3399_sdram_params *params, u32 phy, + struct rk3399_sdram_params *timings, + u32 channel) +{ + u32 *denali_ctl, *denali_phy; + u32 *denali_phy_params; + u32 speed = 0; + u32 ctl, mr5; + + denali_ctl = dram->chan[channel].pctl->denali_ctl; + denali_phy = dram->chan[channel].publ->denali_phy; + denali_phy_params = timings->phy_regs.denali_phy; + + /* switch index */ + clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, phy << 8); + writel(denali_phy_params[896], &denali_phy[896]); + + /* phy_pll_ctrl_ca, phy_pll_ctrl */ + writel(denali_phy_params[911], &denali_phy[911]); + + /* phy_low_freq_sel */ + clrsetbits_le32(&denali_phy[913], 0x1, + denali_phy_params[913] & 0x1); + + /* phy_grp_slave_delay_x, phy_cslvl_dly_step */ + writel(denali_phy_params[916], &denali_phy[916]); + writel(denali_phy_params[917], &denali_phy[917]); + writel(denali_phy_params[918], &denali_phy[918]); + + /* phy_adrz_sw_wraddr_shift_x */ + writel(denali_phy_params[512], &denali_phy[512]); + clrsetbits_le32(&denali_phy[513], 0xffff, + denali_phy_params[513] & 0xffff); + writel(denali_phy_params[640], &denali_phy[640]); + clrsetbits_le32(&denali_phy[641], 0xffff, + denali_phy_params[641] & 0xffff); + writel(denali_phy_params[768], &denali_phy[768]); + clrsetbits_le32(&denali_phy[769], 0xffff, + denali_phy_params[769] & 0xffff); + + writel(denali_phy_params[544], &denali_phy[544]); + writel(denali_phy_params[545], &denali_phy[545]); + writel(denali_phy_params[546], &denali_phy[546]); + writel(denali_phy_params[547], &denali_phy[547]); + + writel(denali_phy_params[672], &denali_phy[672]); + writel(denali_phy_params[673], &denali_phy[673]); + writel(denali_phy_params[674], &denali_phy[674]); + writel(denali_phy_params[675], &denali_phy[675]); + + writel(denali_phy_params[800], &denali_phy[800]); + writel(denali_phy_params[801], &denali_phy[801]); + writel(denali_phy_params[802], &denali_phy[802]); + writel(denali_phy_params[803], &denali_phy[803]); + + /* + * phy_adr_master_delay_start_x + * phy_adr_master_delay_step_x + * phy_adr_master_delay_wait_x + */ + writel(denali_phy_params[548], &denali_phy[548]); + writel(denali_phy_params[676], &denali_phy[676]); + writel(denali_phy_params[804], &denali_phy[804]); + + /* phy_adr_calvl_dly_step_x */ + writel(denali_phy_params[549], &denali_phy[549]); + writel(denali_phy_params[677], &denali_phy[677]); + writel(denali_phy_params[805], &denali_phy[805]); + + /* + * phy_clk_wrdm_slave_delay_x + * phy_clk_wrdqz_slave_delay_x + * phy_clk_wrdqs_slave_delay_x + */ + copy_to_reg((u32 *)&denali_phy[59], (u32 *)&denali_phy_params[59], + (63 - 58) * 4); + copy_to_reg((u32 *)&denali_phy[187], (u32 *)&denali_phy_params[187], + (191 - 186) * 4); + copy_to_reg((u32 *)&denali_phy[315], (u32 *)&denali_phy_params[315], + (319 - 314) * 4); + copy_to_reg((u32 *)&denali_phy[443], (u32 *)&denali_phy_params[443], + (447 - 442) * 4); + + /* + * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8 + * dqs_tsel_wr_end[7:4] add half cycle + * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8 + * dq_tsel_wr_end[7:4] add half cycle + */ + writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]); + writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]); + writel(denali_phy_params[85], &denali_phy[85]); + + writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]); + writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]); + writel(denali_phy_params[213], &denali_phy[213]); + + writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]); + writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]); + writel(denali_phy_params[341], &denali_phy[341]); + + writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]); + writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]); + writel(denali_phy_params[469], &denali_phy[469]); + + /* + * phy_gtlvl_resp_wait_cnt_x + * phy_gtlvl_dly_step_x + * phy_wrlvl_resp_wait_cnt_x + * phy_gtlvl_final_step_x + * phy_gtlvl_back_step_x + * phy_rdlvl_dly_step_x + * + * phy_master_delay_step_x + * phy_master_delay_wait_x + * phy_wrlvl_dly_step_x + * phy_rptr_update_x + * phy_wdqlvl_dly_step_x + */ + writel(denali_phy_params[87], &denali_phy[87]); + writel(denali_phy_params[88], &denali_phy[88]); + writel(denali_phy_params[89], &denali_phy[89]); + writel(denali_phy_params[90], &denali_phy[90]); + + writel(denali_phy_params[215], &denali_phy[215]); + writel(denali_phy_params[216], &denali_phy[216]); + writel(denali_phy_params[217], &denali_phy[217]); + writel(denali_phy_params[218], &denali_phy[218]); + + writel(denali_phy_params[343], &denali_phy[343]); + writel(denali_phy_params[344], &denali_phy[344]); + writel(denali_phy_params[345], &denali_phy[345]); + writel(denali_phy_params[346], &denali_phy[346]); + + writel(denali_phy_params[471], &denali_phy[471]); + writel(denali_phy_params[472], &denali_phy[472]); + writel(denali_phy_params[473], &denali_phy[473]); + writel(denali_phy_params[474], &denali_phy[474]); + + /* + * phy_gtlvl_lat_adj_start_x + * phy_gtlvl_rddqs_slv_dly_start_x + * phy_rdlvl_rddqs_dq_slv_dly_start_x + * phy_wdqlvl_dqdm_slv_dly_start_x + */ + writel(denali_phy_params[80], &denali_phy[80]); + writel(denali_phy_params[81], &denali_phy[81]); + + writel(denali_phy_params[208], &denali_phy[208]); + writel(denali_phy_params[209], &denali_phy[209]); + + writel(denali_phy_params[336], &denali_phy[336]); + writel(denali_phy_params[337], &denali_phy[337]); + + writel(denali_phy_params[464], &denali_phy[464]); + writel(denali_phy_params[465], &denali_phy[465]); + + /* + * phy_master_delay_start_x + * phy_sw_master_mode_x + * phy_rddata_en_tsel_dly_x + */ + writel(denali_phy_params[86], &denali_phy[86]); + writel(denali_phy_params[214], &denali_phy[214]); + writel(denali_phy_params[342], &denali_phy[342]); + writel(denali_phy_params[470], &denali_phy[470]); + + /* + * phy_rddqz_slave_delay_x + * phy_rddqs_dqz_fall_slave_delay_x + * phy_rddqs_dqz_rise_slave_delay_x + * phy_rddqs_dm_fall_slave_delay_x + * phy_rddqs_dm_rise_slave_delay_x + * phy_rddqs_gate_slave_delay_x + * phy_wrlvl_delay_early_threshold_x + * phy_write_path_lat_add_x + * phy_rddqs_latency_adjust_x + * phy_wrlvl_delay_period_threshold_x + * phy_wrlvl_early_force_zero_x + */ + copy_to_reg((u32 *)&denali_phy[64], (u32 *)&denali_phy_params[64], + (67 - 63) * 4); + clrsetbits_le32(&denali_phy[68], 0xfffffc00, + denali_phy_params[68] & 0xfffffc00); + copy_to_reg((u32 *)&denali_phy[69], (u32 *)&denali_phy_params[69], + (79 - 68) * 4); + copy_to_reg((u32 *)&denali_phy[192], (u32 *)&denali_phy_params[192], + (195 - 191) * 4); + clrsetbits_le32(&denali_phy[196], 0xfffffc00, + denali_phy_params[196] & 0xfffffc00); + copy_to_reg((u32 *)&denali_phy[197], (u32 *)&denali_phy_params[197], + (207 - 196) * 4); + copy_to_reg((u32 *)&denali_phy[320], (u32 *)&denali_phy_params[320], + (323 - 319) * 4); + clrsetbits_le32(&denali_phy[324], 0xfffffc00, + denali_phy_params[324] & 0xfffffc00); + copy_to_reg((u32 *)&denali_phy[325], (u32 *)&denali_phy_params[325], + (335 - 324) * 4); + + copy_to_reg((u32 *)&denali_phy[448], (u32 *)&denali_phy_params[448], + (451 - 447) * 4); + clrsetbits_le32(&denali_phy[452], 0xfffffc00, + denali_phy_params[452] & 0xfffffc00); + copy_to_reg((u32 *)&denali_phy[453], (u32 *)&denali_phy_params[453], + (463 - 452) * 4); + + /* phy_two_cyc_preamble_x */ + clrsetbits_le32(&denali_phy[7], 0x3 << 24, + denali_phy_params[7] & (0x3 << 24)); + clrsetbits_le32(&denali_phy[135], 0x3 << 24, + denali_phy_params[135] & (0x3 << 24)); + clrsetbits_le32(&denali_phy[263], 0x3 << 24, + denali_phy_params[263] & (0x3 << 24)); + clrsetbits_le32(&denali_phy[391], 0x3 << 24, + denali_phy_params[391] & (0x3 << 24)); + + /* speed */ + if (timings->base.ddr_freq < 400 * MHz) + speed = 0x0; + else if (timings->base.ddr_freq < 800 * MHz) + speed = 0x1; + else if (timings->base.ddr_freq < 1200 * MHz) + speed = 0x2; + + /* phy_924 phy_pad_fdbk_drive */ + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); + /* phy_926 phy_pad_data_drive */ + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); + /* phy_927 phy_pad_dqs_drive */ + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); + /* phy_928 phy_pad_addr_drive */ + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); + /* phy_929 phy_pad_clk_drive */ + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); + /* phy_935 phy_pad_cke_drive */ + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); + /* phy_937 phy_pad_rst_drive */ + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); + /* phy_939 phy_pad_cs_drive */ + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + + read_mr(dram->chan[channel].pctl, 1, 5, &mr5); + set_ds_odt(&dram->chan[channel], timings, true, mr5); + + ctl = lpddr4_get_ctl(timings, phy); + set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5); + set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5); + set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5); + set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5); + set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5); + + /* + * if phy_sw_master_mode_x not bypass mode, + * clear phy_slice_pwr_rdc_disable. + * note: need use timings, not ddr_publ_regs + */ + if (!((denali_phy_params[86] >> 8) & (1 << 2))) { + clrbits_le32(&denali_phy[10], 1 << 16); + clrbits_le32(&denali_phy[138], 1 << 16); + clrbits_le32(&denali_phy[266], 1 << 16); + clrbits_le32(&denali_phy[394], 1 << 16); + } + + /* + * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't + * smaller than 8 + * NOTE: need use timings, not ddr_publ_regs + */ + if ((denali_phy_params[84] >> 16) & 1) { + if (((readl(&denali_ctl[217 + ctl]) >> 16) & 0x1f) < 8) + clrsetbits_le32(&denali_ctl[217 + ctl], + 0x1f << 16, 8 << 16); + } +} + +static void lpddr4_set_phy(struct dram_info *dram, + struct rk3399_sdram_params *params, u32 phy, + struct rk3399_sdram_params *timings) +{ + u32 channel; + + for (channel = 0; channel < 2; channel++) + lpddr4_copy_phy(dram, params, phy, timings, channel); +} + +static int lpddr4_set_ctl(struct dram_info *dram, + struct rk3399_sdram_params *params, u32 ctl, u32 hz) +{ + u32 channel; + int ret_clk, ret; + + /* cci idle req stall */ + writel(0x70007, &dram->grf->soc_con0); + + /* enable all clk */ + setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); + + /* idle */ + setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); + while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) + != (0x3 << 18)) + ; + + /* change freq */ + writel((((0x3 << 4) | (1 << 2) | 1) << 16) | + (ctl << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 2))) + ; + + ret_clk = clk_set_rate(&dram->ddr_clk, hz); + if (ret_clk < 0) { + printf("%s clk set failed %d\n", __func__, ret_clk); + return ret_clk; + } + + writel(0x20002, &dram->cic->cic_ctrl0); + while (!(readl(&dram->cic->cic_status0) & (1 << 0))) + ; + + /* deidle */ + clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); + while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) + ; + + /* clear enable all clk */ + clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); + + /* lpddr4 ctl2 can not do training, all training will fail */ + if (!(params->base.dramtype == LPDDR4 && ctl == 2)) { + for (channel = 0; channel < 2; channel++) { + if (!(params->ch[channel].cap_info.col)) + continue; + ret = data_training(dram, channel, params, + PI_FULL_TRAINING); + if (ret) + printf("%s: channel %d training failed!\n", + __func__, channel); + else + debug("%s: channel %d training pass\n", + __func__, channel); + } + } + + return 0; +} + +static int lpddr4_set_rate(struct dram_info *dram, + struct rk3399_sdram_params *params) +{ + u32 ctl; + u32 phy; + + for (ctl = 0; ctl < 2; ctl++) { + phy = lpddr4_get_phy(params, ctl); + + lpddr4_set_phy(dram, params, phy, &lpddr4_timings[ctl]); + lpddr4_set_ctl(dram, params, ctl, + lpddr4_timings[ctl].base.ddr_freq); + + debug("%s: change freq to %d mhz %d, %d\n", __func__, + lpddr4_timings[ctl].base.ddr_freq / MHz, ctl, phy); + } + + return 0; +} #endif /* CONFIG_RAM_RK3399_LPDDR4 */ static unsigned char calculate_stride(struct rk3399_sdram_params *params) @@ -2009,6 +2656,7 @@ static const struct sdram_rk3399_ops rk3399_ops = { .set_rate = switch_to_phy_index1, #else .data_training = lpddr4_mr_detect, + .set_rate = lpddr4_set_rate, #endif }; @@ -2032,6 +2680,7 @@ static int rk3399_dmc_init(struct udevice *dev) priv->ops = &rk3399_ops; priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); priv->pmucru = rockchip_get_pmucru(); @@ -2050,8 +2699,8 @@ static int rk3399_dmc_init(struct udevice *dev) priv->chan[0].publ, priv->chan[0].msch, priv->chan[1].pctl, priv->chan[1].pi, priv->chan[1].publ, priv->chan[1].msch); - debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, - priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); + debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru, + priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu); #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); From f0e0ab7727219676e6e936d489c3bf8183834540 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:41 +0530 Subject: [PATCH 086/147] configs: rockpro64: Enable LPDDR4 support Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4. So, enable it for Rockpro64 board. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/rockpro64-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index e8fc7ae1414..39e68aad822 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_RAM_RK3399_LPDDR4=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y From ecd8136e5230ecfcb01d5fba046b4bb895f21419 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:42 +0530 Subject: [PATCH 087/147] configs: rock-pi-4: Enable LPDDR4 support Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4. So, enable it for Rock-PI-4 board. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/rock-pi-4-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index be670df23ff..c6fc9b995d5 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_RAM_RK3399_LPDDR4=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y From f797651f804d2c53fad306b36454f78e72183249 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:43 +0530 Subject: [PATCH 088/147] rockchip: dts: rk3399: Add LPDDR4-100 timings Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file. all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin Associated LPDDR4 board -u-boot.dtsi can include this to make these timings available during SPL or TPL stages. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 +++++++++++++++++++++ 1 file changed, 1537 insertions(+) create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi new file mode 100644 index 00000000000..4a4414a960f --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi @@ -0,0 +1,1537 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2019 Amarula Solutions. + * Author: Jagan Teki + */ + +&dmc { + rockchip,sdram-params = < + 0x2 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80241d22 + 0x15050f08 + 0x00000602 + 0x00002122 + 0x0000004c + 0x00000000 + 0x2 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80241d22 + 0x15050f08 + 0x00000602 + 0x00002122 + 0x0000004c + 0x00000000 + 50 + 7 + 2 + 13 + 1 + 0x00000b00 + 0x00000000 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+ 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000005 + 0x04000f01 + 0x00020040 + 0x00020055 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000050 + 0x00000000 + 0x01010100 + 0x00000600 + 0x00000000 + 0x00006400 + 0x09221902 + 0x00000000 + 0x000d1f01 + 0x0d1f0d1f + 0x0d1f0d1f + 0x00030003 + 0x03000300 + 0x00000300 + 0x09221902 + 0x00000000 + 0x00000000 + 0x01020000 + 0x00000001 + 0x00000411 + 0x00000411 + 0x00000040 + 0x00000040 + 0x00000411 + 0x00000411 + 0x00004410 + 0x00004410 + 0x00004410 + 0x00004410 + 0x00004410 + 0x00000411 + 0x00004410 + 0x00000411 + 0x00004410 + 0x00000411 + 0x00004410 + 0x00000000 + 0x00000000 + 0x00000000 + 0x64000000 + 0x00000000 + 0x00000000 + 0x00000108 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0xe4000000 + 0x00000000 + 0x00000000 + 0x01010000 + 0x00000000 + >; +}; From a153b034df221c5fa803c07293f7544930e7a37f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:44 +0530 Subject: [PATCH 089/147] rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi Use LPDDR4-100 sdram timings dtsi for Rockpro64 board. All these timings are processed during TPL stage of rockpro64 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 50b0ca0df54..f7f26d584f9 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" &vdd_log { regulator-init-microvolt = <950000>; From 9a7b8db9f081ce8eb30da046cbab6d23c41c2ebc Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 15 Jul 2019 23:58:56 +0530 Subject: [PATCH 090/147] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board. Since sdram rk3399 support dynamic stride and rank detection it can able to detect 1GB ddr eventough the timings are meant for dual channel, 2GB size. Bootchain after and before this change are: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper This certainly fix the second channel data training initialization since we have dynamic rank, stride where second channel capabilities are clear or memset to 0. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi index 7d22528f49d..eb0aca4758d 100644 --- a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi @@ -4,3 +4,4 @@ */ #include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi" From 852f6ddd76fad2d5adef3f7e3a75d0065c68db3b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 Jul 2019 17:27:45 +0530 Subject: [PATCH 091/147] rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi Use LPDDR4-100 sdram timings dtsi for RockPI-4 board. All these timings are processed during TPL stage of rock-pi-4 board, bootchain. This make TPL would replace rockchip in house rkbin in current bootchain. Bootchain after and before this change: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index f8d8e33383f..5bd8696666a 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -4,6 +4,8 @@ */ #include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + / { chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; From 7958a85bca4b399b99d022de95970b6689030135 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:55:27 +0800 Subject: [PATCH 092/147] rockchip: rk3399: remove pinctrl init in spl_board_init The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3399-board-spl.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 890d80025f6..2333694caa0 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -21,7 +21,6 @@ #include #include #include -#include void board_return_to_bootrom(void) { @@ -133,7 +132,6 @@ void secure_timer_init(void) void board_init_f(ulong dummy) { - struct udevice *pinctrl; struct udevice *dev; struct rk3399_pmusgrf_regs *sgrf; struct rk3399_grf_regs *grf; @@ -192,12 +190,6 @@ void board_init_f(ulong dummy) secure_timer_init(); - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - pr_err("Pinctrl init failed: %d\n", ret); - return; - } - ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { pr_err("DRAM init failed: %d\n", ret); From fcb1964a5ef9ba8a19117cfa456b979717f91446 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:55:28 +0800 Subject: [PATCH 093/147] rockchip: rk3188: remove pinctrl init in spl_board_init The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3188-board-spl.c | 1 - arch/arm/mach-rockchip/rk3188-board.c | 31 ----------------------- 2 files changed, 32 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 77b9b36d357..84c2a5756fa 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 80d8c4241ec..94fd6c01eb7 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -15,7 +15,6 @@ #include #include #include -#include __weak int rk_board_late_init(void) { @@ -42,37 +41,7 @@ int board_late_init(void) int board_init(void) { -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - struct udevice *pinctrl; - int ret; - - /* - * We need to implement sdcard iomux here for the further - * initialization, otherwise, it'll hit sdcard command sending - * timeout exception. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - return 0; -err: - printf("board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); - - return -1; -#else - return 0; -#endif } #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) From 0e9802095d454a1b2f47cb99bd6e4b48027348f3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:55:29 +0800 Subject: [PATCH 094/147] rockchip: rk3288: remove pinctrl init in spl_board_init The pinctrl will default init the io while driver is probe with new pinctrl driver. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3288-board-spl.c | 1 - arch/arm/mach-rockchip/rk3288-board.c | 27 ----------------------- 2 files changed, 28 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index d8d215db8a0..b7fab63acfd 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index e2de5b2fddb..a250d503876 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include @@ -145,33 +144,7 @@ static int veyron_init(void) int board_init(void) { #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - struct udevice *pinctrl; - int ret; - - /* - * We need to implement sdcard iomux here for the further - * initlization, otherwise, it'll hit sdcard command sending - * timeout exception. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); - if (ret) { - debug("%s: Failed to set up SD card\n", __func__); - goto err; - } - return 0; -err: - printf("board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); - - return -1; #else int ret; From c8851c9d183521f6f048549081ffe20c0276e7b4 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:55:30 +0800 Subject: [PATCH 095/147] rockchip: remove redundant pinctrl header including No code is using this header file, remove it. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3036-board.c | 1 - arch/arm/mach-rockchip/rk3328-board-spl.c | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index e6ea0e9a6ae..c594c4d61cd 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -14,7 +14,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c index 7f49d056a07..f24fd89e3f1 100644 --- a/arch/arm/mach-rockchip/rk3328-board-spl.c +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include From 5e283876f108c5acb8e60b84ae9ea0bb7da4523e Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:15 +0800 Subject: [PATCH 096/147] rockchip: fixup board choice in Kconfig Kconfig for board target select is choice option, fixup for rk3036, rk3288 and rv1108. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3036/Kconfig | 5 +++++ arch/arm/mach-rockchip/rk3288/Kconfig | 5 +++++ arch/arm/mach-rockchip/rv1108/Kconfig | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 5e04d204482..0f6b5c46293 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -1,5 +1,8 @@ if ROCKCHIP_RK3036 +choice + prompt "RK3036 board select" + config TARGET_EVB_RK3036 bool "EVB_RK3036" select BOARD_LATE_INIT @@ -8,6 +11,8 @@ config TARGET_KYLIN_RK3036 bool "KYLIN_RK3036" select BOARD_LATE_INIT +endchoice + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index c5dcd061cfd..a32cd92976f 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -1,5 +1,8 @@ if ROCKCHIP_RK3288 +choice + prompt "RK3288 board select" + config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" select BOARD_LATE_INIT @@ -125,6 +128,8 @@ config TARGET_TINKER_RK3288 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to I2C, SPI, UART, GPIOs. +endchoice + config ROCKCHIP_FAST_SPL bool "Change the CPU to full speed in SPL" depends on TARGET_CHROMEBOOK_JERRY diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index e3a63b80e13..c5402ab1bd9 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -1,5 +1,8 @@ if ROCKCHIP_RV1108 +choice + prompt "RV1108 board select" + config TARGET_EVB_RV1108 bool "EVB_RV1108" help @@ -22,6 +25,8 @@ config TARGET_ELGIN_RV1108 help RV1108 ELGIN is a board based on the Rockchip RV1108. +endchoice + config SYS_SOC default "rv1108" From 45c1d341577ac565ba944672d148738f5b570e50 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:16 +0800 Subject: [PATCH 097/147] rockchip: Kconfig: move rk322x config into its Kconfig Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 13 ------------- arch/arm/mach-rockchip/rk322x/Kconfig | 10 ++++++++++ 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1090d21879c..3f28782a09b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -68,19 +68,6 @@ config ROCKCHIP_RK322X and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. -if ROCKCHIP_RK322X - -config TPL_TEXT_BASE - default 0x10081000 - -config TPL_MAX_SIZE - default 28672 - -config TPL_STACK - default 0x10088000 - -endif - config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 8a1f95f7859..cffb53183b5 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -1,5 +1,6 @@ if ROCKCHIP_RK322X + config TARGET_EVB_RK3229 bool "EVB_RK3229" select BOARD_LATE_INIT @@ -13,6 +14,15 @@ config SYS_MALLOC_F_LEN config SPL_SERIAL_SUPPORT default y +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0x10088000 + +config TPL_TEXT_BASE + default 0x10081000 + source "board/rockchip/evb_rk3229/Kconfig" endif From 59591267711bef800858b805ed58d119425c9a11 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:17 +0800 Subject: [PATCH 098/147] rockchip: Kconfig: move rk3288 config into its Kconfig Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 13 ------------- arch/arm/mach-rockchip/rk3288/Kconfig | 9 +++++++++ 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 3f28782a09b..9ae8ec64c4b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -98,19 +98,6 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. -if ROCKCHIP_RK3288 - -config TPL_TEXT_BASE - default 0xff704000 - -config TPL_MAX_SIZE - default 32768 - -config TPL_STACK - default 0xff718000 - -endif - config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index a32cd92976f..0dc5123fb65 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -157,6 +157,15 @@ config SPL_LIBGENERIC_SUPPORT config SPL_SERIAL_SUPPORT default y +config TPL_MAX_SIZE + default 32768 + +config TPL_STACK + default 0xff718000 + +config TPL_TEXT_BASE + default 0xff704000 + source "board/amarula/vyasa-rk3288/Kconfig" source "board/chipspark/popmetal_rk3288/Kconfig" From 97fd39c69ef710881f8d9c8db934bd5b4318b297 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:18 +0800 Subject: [PATCH 099/147] rockchip: Kconfig: move rk3368 config into its Kconfig Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 13 ------------- arch/arm/mach-rockchip/rk3368/Kconfig | 9 +++++++++ 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 9ae8ec64c4b..c41f1439540 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -136,19 +136,6 @@ config ROCKCHIP_RK3368 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. -if ROCKCHIP_RK3368 - -config TPL_TEXT_BASE - default 0xff8c1000 - -config TPL_MAX_SIZE - default 28672 - -config TPL_STACK - default 0xff8cffff - -endif - config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 325572a7e40..31ef243a75d 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -53,4 +53,13 @@ source "board/rockchip/evb_px5/Kconfig" config SPL_LDSCRIPT default "arch/arm/cpu/armv8/u-boot-spl.lds" +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0xff8cffff + +config TPL_TEXT_BASE + default 0xff8c1000 + endif From c83b5a2c5353cd610af3e2b71fd81675d03bd3ed Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:19 +0800 Subject: [PATCH 100/147] rockchip: Kconfig: move rk3399 config into its Kconfig Each SoC have its config setting and its Kconfig, move the specific setting to its own Kconfig file. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 16 ---------------- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ++++++++++++ 2 files changed, 12 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c41f1439540..52b83fc6114 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -188,22 +188,6 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. -if ROCKCHIP_RK3399 - -config TPL_LDSCRIPT - default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" - -config TPL_TEXT_BASE - default 0xff8c2000 - -config TPL_MAX_SIZE - default 188416 - -config TPL_STACK - default 0xff8effff - -endif - config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 2c5c93c0b85..231ba14cca9 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -70,6 +70,18 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x0800 +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_MAX_SIZE + default 188416 + +config TPL_STACK + default 0xff8effff + +config TPL_TEXT_BASE + default 0xff8c2000 + source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" From 476dcb6b436264e5d20d908d5e28418edde6f6f2 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:20 +0800 Subject: [PATCH 101/147] rockchip: Kconfig: move ROCKCHIP_BOOT_MODE_REG to soc Kconfig Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value, move it to SoC's own Kconfig, and add address for rk3128 and rk3328 so that all SoCs have available address. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 8 -------- arch/arm/mach-rockchip/rk3036/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3128/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3188/Kconfig | 3 +++ arch/arm/mach-rockchip/rk322x/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3328/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++ arch/arm/mach-rockchip/rv1108/Kconfig | 3 +++ 10 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 52b83fc6114..85f88cea779 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -225,14 +225,6 @@ config TPL_ROCKCHIP_BACK_TO_BROM config ROCKCHIP_BOOT_MODE_REG hex "Rockchip boot mode flag register address" - default 0x200081c8 if ROCKCHIP_RK3036 - default 0x20004040 if ROCKCHIP_RK3188 - default 0x110005c8 if ROCKCHIP_RK322X - default 0xff730094 if ROCKCHIP_RK3288 - default 0xff738200 if ROCKCHIP_RK3368 - default 0xff320300 if ROCKCHIP_RK3399 - default 0x10300580 if ROCKCHIP_RV1108 - default 0 help The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 0f6b5c46293..51cd43b396f 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -13,6 +13,9 @@ config TARGET_KYLIN_RK3036 endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0x200081c8 + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index a82b7dc063f..b867401c7f5 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -13,6 +13,9 @@ config TARGET_EVB_RK3128 endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0x100a0038 + config SYS_SOC default "rk3128" diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index a6fc691fb6c..e24e68ea518 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -9,6 +9,9 @@ config TARGET_ROCK Expansion connectors provide access to display pins, I2C, SPI, UART and GPIOs. +config ROCKCHIP_BOOT_MODE_REG + default 0x20004040 + config SYS_SOC default "rk3188" diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index cffb53183b5..60e99a7e3bb 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -5,6 +5,9 @@ config TARGET_EVB_RK3229 bool "EVB_RK3229" select BOARD_LATE_INIT +config ROCKCHIP_BOOT_MODE_REG + default 0x110005c8 + config SYS_SOC default "rk322x" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 0dc5123fb65..a03b36bff3f 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -139,6 +139,9 @@ config ROCKCHIP_FAST_SPL voltage. This option is only available on boards which support it and have the required PMIC code. +config ROCKCHIP_BOOT_MODE_REG + default 0xff730094 + config SYS_SOC default "rk3288" diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index 6c5c4303a35..8ad7f56cbf6 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -12,6 +12,9 @@ config TARGET_EVB_RK3328 endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0xff1005c8 + config SYS_SOC default "rk3328" diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 31ef243a75d..141d2f67aa1 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -42,6 +42,9 @@ config TARGET_EVB_PX5 sensor STK3410. endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0xff738200 + config SYS_SOC default "rk3368" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 231ba14cca9..f582577d974 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -64,6 +64,9 @@ config TARGET_CHROMEBOOK_BOB endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0xff320300 + config SYS_SOC default "rk3399" diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index c5402ab1bd9..a12216dccf6 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -27,6 +27,9 @@ config TARGET_ELGIN_RV1108 endchoice +config ROCKCHIP_BOOT_MODE_REG + default 0x10300580 + config SYS_SOC default "rv1108" From e3d83d8e548ac9735dc3b08686e14e7120cd0826 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:21 +0800 Subject: [PATCH 102/147] rockchip: rk322x: use defconfig for SYS_MALLOC_F_LEN There is no difference in rk322x board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk322x/Kconfig | 2 +- configs/evb-rk3229_defconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 60e99a7e3bb..9d734c3a317 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -12,7 +12,7 @@ config SYS_SOC default "rk322x" config SYS_MALLOC_F_LEN - default 0x400 + default 0x800 config SPL_SERIAL_SUPPORT default y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 31c1b1719c0..6447e1852b5 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x61000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ROCKCHIP_RK322X=y CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 From 9489b5c7ba424e4e30449c61033535b56e567cf0 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:22 +0800 Subject: [PATCH 103/147] rockchip: rk3288: use default value for SYS_MALLOC_F_LEN There is no difference in rk3288 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3288/Kconfig | 2 +- configs/chromebit_mickey_defconfig | 1 - configs/chromebook_jerry_defconfig | 1 - configs/chromebook_minnie_defconfig | 1 - configs/chromebook_speedy_defconfig | 1 - configs/evb-rk3288_defconfig | 1 - configs/fennec-rk3288_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/miqi-rk3288_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - 13 files changed, 1 insertion(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index a03b36bff3f..9a4c1303862 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -146,7 +146,7 @@ config SYS_SOC default "rk3288" config SYS_MALLOC_F_LEN - default 0x0800 + default 0x2000 config SPL_DRIVERS_MISC_SUPPORT default y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 1a343093c8a..cf815dccbd0 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC_SUPPORT is not set CONFIG_TARGET_CHROMEBIT_MICKEY=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 7c7986e6aee..f6056f85ccf 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC_SUPPORT is not set CONFIG_TARGET_CHROMEBOOK_JERRY=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 17c1ea64530..b4bae3b197b 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC_SUPPORT is not set CONFIG_TARGET_CHROMEBOOK_MINNIE=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 0cc1eb6a0b4..999dc694528 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y # CONFIG_SPL_MMC_SUPPORT is not set CONFIG_TARGET_CHROMEBOOK_SPEEDY=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 843c59d30d9..2468aa21013 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 6dfaff50ffd..16d8fb155c5 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_FENNEC_RK3288=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 4cedb28d227..8abe8a648a6 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_FIREFLY_RK3288=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 936192f5472..c9a35115fbc 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_MIQI_RK3288=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 2e6a4a7621e..dfddc4af5e3 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_PHYCORE_RK3288=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 902294bc3c5..4c9a7f08246 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_POPMETAL_RK3288=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 482ee7d555b..7695652e522 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x01000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" CONFIG_TARGET_TINKER_RK3288=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 1108c6a907b..eaea6250071 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -3,7 +3,6 @@ CONFIG_ARM=y # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00100000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_VYASA_RK3288=y CONFIG_NR_DRAM_BANKS=1 From d0ae3bc4d667b4c9207d3b7c574ba9eac978a203 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:23 +0800 Subject: [PATCH 104/147] rockchip: rk3399: use default value for SYS_MALLOC_F_LEN There is no difference in rk3399 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/Kconfig | 2 +- configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - 13 files changed, 1 insertion(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index f582577d974..799b32646a7 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -71,7 +71,7 @@ config SYS_SOC default "rk3399" config SYS_MALLOC_F_LEN - default 0x0800 + default 0x4000 config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index e61e27c992e..32809a47d1d 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index f10502cb0e7..ad2197ba69c 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 6a1b279cc92..07c1287632a 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 61f05b784ff..b29098a74a9 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 7863e45db99..9fbd44663ce 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 8b9237c5ed0..76fcab8ebaa 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 5799ab39f4f..90ad927593d 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 82ec24205e3..cb44424f880 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 5cb2273a151..c771f012cf1 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_TARGET_PUMA_RK3399=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index c6fc9b995d5..53a00726230 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 5be36383e16..4db76c941e8 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 39e68aad822..9e124341b02 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 From cb32a91fbfaaa71ab595dd61360c66ebd483694d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:24 +0800 Subject: [PATCH 105/147] rockchip: rk3328: use defaule value for SYS_MALLOC_F_LEN There is no difference in rk3328 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3328/Kconfig | 2 +- configs/rock64-rk3328_defconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index 8ad7f56cbf6..a100b953ac5 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -19,7 +19,7 @@ config SYS_SOC default "rk3328" config SYS_MALLOC_F_LEN - default 0x0800 + default 0x2000 source "board/rockchip/evb_rk3328/Kconfig" diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 6529dedfb6f..1c3fb69bb85 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -4,7 +4,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 From 8ef62a4aab82eb9bb115b622227e4fa6782bc719 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:25 +0800 Subject: [PATCH 106/147] rockchip: rk3368: use defaule value for SYS_MALLOC_F_LEN There is no difference in rk3368 board use for SYS_MALLOC_F_LEN, so we can use default value. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ configs/evb-px5_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/sheep-rk3368_defconfig | 1 - 4 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 141d2f67aa1..2220f595caa 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -48,6 +48,9 @@ config ROCKCHIP_BOOT_MODE_REG config SYS_SOC default "rk3368" +config SYS_MALLOC_F_LEN + default 0x2000 + source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 9601b12afa1..6945e68b001 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3368=y CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds" CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 75e85833a7b..ef05ba5d97d 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3368=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_TPL_LIBCOMMON_SUPPORT=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index cff1905ce58..4883f5932bd 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_ROCKCHIP_RK3368=y CONFIG_TARGET_SHEEP=y CONFIG_NR_DRAM_BANKS=1 From a13f870ad45dbadd79b540f74fa006db2bea2adc Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:26 +0800 Subject: [PATCH 107/147] rockchip: rk3399: default enable SPL LIBCOMMON and LIBGENERIC We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/Kconfig | 6 ++++++ configs/chromebook_bob_defconfig | 2 -- configs/evb-rk3399_defconfig | 2 -- configs/ficus-rk3399_defconfig | 2 -- configs/firefly-rk3399_defconfig | 2 -- configs/nanopc-t4-rk3399_defconfig | 2 -- configs/nanopi-m4-rk3399_defconfig | 2 -- configs/nanopi-neo4-rk3399_defconfig | 2 -- configs/orangepi-rk3399_defconfig | 2 -- configs/puma-rk3399_defconfig | 2 -- configs/rock-pi-4-rk3399_defconfig | 2 -- configs/rock960-rk3399_defconfig | 2 -- configs/rockpro64-rk3399_defconfig | 2 -- 13 files changed, 6 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 799b32646a7..6660d05349b 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -73,6 +73,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x4000 +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 32809a47d1d..1c04f0a758e 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -2,8 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index ad2197ba69c..764d32f259b 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 07c1287632a..d1425dc3d0e 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index b29098a74a9..9f05f33dddb 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 9fbd44663ce..bca4f089662 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 76fcab8ebaa..dd2065df5fb 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 90ad927593d..46039d1d077 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index cb44424f880..16a0a17c742 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c771f012cf1..37f845cfb1c 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -2,8 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_TARGET_PUMA_RK3399=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 53a00726230..14ae39a5619 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 4db76c941e8..ed11fef7c28 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 9e124341b02..72bfff289b7 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 From 747e127535902e86f0897f1d1691476c2c5c83bc Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:27 +0800 Subject: [PATCH 108/147] rockchip: rk3328: default enable SPL LIBCOMMON and LIBGENERIC We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3328/Kconfig | 6 ++++++ configs/evb-rk3328_defconfig | 2 -- configs/rock64-rk3328_defconfig | 2 -- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index a100b953ac5..f8e15288e0b 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -21,6 +21,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x2000 +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + source "board/rockchip/evb_rk3328/Kconfig" endif diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 92d6817ad5f..fcc04f27ec9 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,7 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index 1c3fb69bb85..ef453e72c1a 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -2,8 +2,6 @@ CONFIG_SMBIOS_MANUFACTURER="pine64" CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 From 1cdb6148450e851abe1df5d7eb20aa07a409941c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:28 +0800 Subject: [PATCH 109/147] rockchip: rk322x: default enable SPL LIBCOMMON and LIBGENERIC We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk322x/Kconfig | 6 ++++++ configs/evb-rk3229_defconfig | 2 -- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 9d734c3a317..2fc6f6ea3ec 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -14,6 +14,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x800 +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + config SPL_SERIAL_SUPPORT default y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 6447e1852b5..20329784ae8 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x61000000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK322X=y CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 From d7f2d23ce4281c70e8395503382474ebdd5e4238 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:14:29 +0800 Subject: [PATCH 110/147] rockchip: rk3368: default enable SPL LIBCOMMON and LIBGENERIC We needs SPL LIBCOMMON and LIBGENERIC for all boards, so we can enable them by default and no need to define in each board. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3368/Kconfig | 6 ++++++ configs/evb-px5_defconfig | 2 -- configs/lion-rk3368_defconfig | 2 -- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 2220f595caa..d6ca5f1d244 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -51,6 +51,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x2000 +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 6945e68b001..9afba9b8733 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3368=y CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds" CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index ef05ba5d97d..ff3255be7a1 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -1,8 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3368=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_TPL_LIBCOMMON_SUPPORT=y From ccab9e7ee3c4447c4bf5f4456f56a6b46f475ad4 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:43 +0800 Subject: [PATCH 111/147] rockchip: rk3288: add arch_cpu_init in spl Add arch_cpu_init() in SPL for soc related init, and move configure_l2ctlr() into it. The arch_cpu_init() only need to run once, so no need to run in TPL. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3288-board-spl.c | 7 ++++++- arch/arm/mach-rockchip/rk3288-board-tpl.c | 2 -- arch/arm/mach-rockchip/rk3288/rk3288.c | 4 ++++ 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index b7fab63acfd..3869de91193 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -103,6 +103,11 @@ static int phycore_init(void) } #endif +__weak int arch_cpu_init(void) +{ + return 0; +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -127,7 +132,7 @@ void board_init_f(ulong dummy) } rockchip_timer_init(); - configure_l2ctlr(); + arch_cpu_init(); ret = rockchip_get_clk(&dev); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c index 787129bbaea..5adbe921852 100644 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c @@ -12,7 +12,6 @@ #include #include #include -#include #include void board_init_f(ulong dummy) @@ -38,7 +37,6 @@ void board_init_f(ulong dummy) } rockchip_timer_init(); - configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 7941ca68a64..5300650e191 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -10,11 +10,15 @@ int arch_cpu_init(void) { +#ifdef CONFIG_SPL_BUILD + configure_l2ctlr(); +#else /* We do some SoC one time setting here. */ struct rk3288_grf * const grf = (void *)GRF_BASE; /* Use rkpwm by default */ rk_setreg(&grf->soc_con2, 1 << 0); +#endif return 0; } From 25c61730994918471cd16c741c488c8e64bcb715 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:44 +0800 Subject: [PATCH 112/147] rockchip: rk3288: move configure_l2ctlr back to rk3288 The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h Signed-off-by: Kever Yang --- .../arm/include/asm/arch-rockchip/sys_proto.h | 22 ------------------- arch/arm/mach-rockchip/rk3288/rk3288.c | 22 +++++++++++++++++++ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 928e4f258bb..905c774c15b 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -6,28 +6,6 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H -#ifdef CONFIG_ROCKCHIP_RK3288 -#include - -static void configure_l2ctlr(void) -{ - uint32_t l2ctlr; - - l2ctlr = read_l2ctlr(); - l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ - - /* - * Data RAM write latency: 2 cycles - * Data RAM read latency: 2 cycles - * Data RAM setup latency: 1 cycle - * Tag RAM write latency: 1 cycle - * Tag RAM read latency: 1 cycle - * Tag RAM setup latency: 1 cycle - */ - l2ctlr |= (1 << 3 | 1 << 0); - write_l2ctlr(l2ctlr); -} -#endif /* CONFIG_ROCKCHIP_RK3288 */ /* provided to defeat compiler optimisation in board_init_f() */ void gru_dummy_function(int i); diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 5300650e191..7552472fbc4 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,12 +2,34 @@ /* * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include #define GRF_BASE 0xff770000 +#ifdef CONFIG_SPL_BUILD +static void configure_l2ctlr(void) +{ + u32 l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} +#endif + int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD From 443fe40e8b005a72c9a9085a9cd9a1d0d862e1a1 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:45 +0800 Subject: [PATCH 113/147] rockchip: rk3288: add default TPL_LDSCRIPT value in Kconfig We share the same TPL_LDSCRIPT for all rk3288 board, add default value in Kconfig. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ configs/tinker-rk3288_defconfig | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 9a4c1303862..57b7962a37c 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -160,6 +160,9 @@ config SPL_LIBGENERIC_SUPPORT config SPL_SERIAL_SUPPORT default y +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl.lds" + config TPL_MAX_SIZE default 32768 diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 7695652e522..b234539a53f 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" CONFIG_TARGET_TINKER_RK3288=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_SIZE_LIMIT=307200 From ccdcdbb5071119ac5eaef5fa6391c54f33371871 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:46 +0800 Subject: [PATCH 114/147] rockchip: rk3288: enable TPL for evb-rk3288 Enable TPL for evb-rk3288 so that we can have a free size limited SPL. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3288/Kconfig | 1 + configs/evb-rk3288_defconfig | 9 +++------ 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 57b7962a37c..de8d9c24f18 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -47,6 +47,7 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" select BOARD_LATE_INIT + select TPL help EVB-RK3288 is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 2468aa21013..a6df1432760 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -1,11 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_SYS_TEXT_BASE=0x01000000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_EVB_RK3288=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_SIZE_LIMIT=307200 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y @@ -14,9 +13,7 @@ CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0xff704000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_TEXT_BASE=0 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y From d62be2f0d2ccc192263ce486613952c2e0217076 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:47 +0800 Subject: [PATCH 115/147] rockchip: evb-rk3288: add -u-boot.dtsi Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-evb-u-boot.dtsi | 46 +++++++++++++++++++++++++++++ arch/arm/dts/rk3288-evb.dts | 25 ---------------- 2 files changed, 46 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/rk3288-evb-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-u-boot.dtsi new file mode 100644 index 00000000000..8ac7840f8f9 --- /dev/null +++ b/arch/arm/dts/rk3288-evb-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3288-u-boot.dtsi" + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&sdmmc_bus4 { + u-boot,dm-spl; +}; + +&sdmmc_clk { + u-boot,dm-spl; +}; + +&sdmmc_cmd { + u-boot,dm-spl; +}; + +&sdmmc_pwr { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts index 575de44c05d..eac91a873f2 100644 --- a/arch/arm/dts/rk3288-evb.dts +++ b/arch/arm/dts/rk3288-evb.dts @@ -26,31 +26,6 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pwm1 { status = "okay"; }; - -&uart2 { - u-boot,dm-pre-reloc; - reg-shift = <2>; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; From 680028a92d41cc101eea6b7f3f15c557170781b5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:48 +0800 Subject: [PATCH 116/147] rockchip: fennec-rk3288: add -u-boot.dtsi Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-fennec-u-boot.dtsi | 54 ++++++++++++++++++++++++++ arch/arm/dts/rk3288-fennec.dts | 25 ------------ 2 files changed, 54 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/rk3288-fennec-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-fennec-u-boot.dtsi b/arch/arm/dts/rk3288-fennec-u-boot.dtsi new file mode 100644 index 00000000000..2efb309d6bd --- /dev/null +++ b/arch/arm/dts/rk3288-fennec-u-boot.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3288-u-boot.dtsi" + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_none_drv_8ma { + u-boot,dm-spl; +}; + +&pcfg_pull_up_drv_8ma { + u-boot,dm-spl; +}; + +&sdmmc_bus4 { + u-boot,dm-spl; +}; + +&sdmmc_clk { + u-boot,dm-spl; +}; + +&sdmmc_cmd { + u-boot,dm-spl; +}; + +&sdmmc_pwr { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts index b5693071680..e1d55e31047 100644 --- a/arch/arm/dts/rk3288-fennec.dts +++ b/arch/arm/dts/rk3288-fennec.dts @@ -26,31 +26,6 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pwm1 { status = "okay"; }; - -&uart2 { - u-boot,dm-pre-reloc; - reg-shift = <2>; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; From 5631e197aeb48efe35efb66adc630b95416cede5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:49 +0800 Subject: [PATCH 117/147] rockchip: rk3288: update u-boot raw image size for all boards Some rk3288 boards are using raw image of u-boot.bin, and now it's much bigger than default 200KB, update CONFIG_SYS_MONITOR_LEN to 600KB. Signed-off-by: Kever Yang --- include/configs/rk3288_common.h | 2 ++ include/configs/tinker_rk3288.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 7c79ed61382..06073cbb611 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -35,6 +35,8 @@ #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 +#define CONFIG_SYS_MONITOR_LEN (600 * 1024) + #ifndef CONFIG_SPL_BUILD /* usb otg */ diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index 32057b3dbb3..5adae68c91b 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -18,6 +18,5 @@ func(DHCP, dchp, na) #define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MONITOR_LEN (600 * 1024) #endif From e4ea8f3c0869ef396a43bd3c9e4d3359da956349 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:50 +0800 Subject: [PATCH 118/147] rockchip: firefly-rk3288: add -u-boot.dtsi Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 54 +++++++++++++++++++++++++ arch/arm/dts/rk3288-firefly.dts | 23 ----------- 2 files changed, 54 insertions(+), 23 deletions(-) create mode 100644 arch/arm/dts/rk3288-firefly-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi new file mode 100644 index 00000000000..2efb309d6bd --- /dev/null +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3288-u-boot.dtsi" + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_none_drv_8ma { + u-boot,dm-spl; +}; + +&pcfg_pull_up_drv_8ma { + u-boot,dm-spl; +}; + +&sdmmc_bus4 { + u-boot,dm-spl; +}; + +&sdmmc_clk { + u-boot,dm-spl; +}; + +&sdmmc_cmd { + u-boot,dm-spl; +}; + +&sdmmc_pwr { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts index 2e075406f40..1cff04e7c7b 100644 --- a/arch/arm/dts/rk3288-firefly.dts +++ b/arch/arm/dts/rk3288-firefly.dts @@ -37,7 +37,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; act8846 { pmic_vsel: pmic-vsel { rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; @@ -59,25 +58,3 @@ &pwm1 { status = "okay"; }; - -&uart2 { - u-boot,dm-pre-reloc; - reg-shift = <2>; -}; - -&usb_host1 { - vbus-supply = <&vcc_host_5v>; - status = "okay"; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; From 2ea3addfa22a60500220970e481e38f9a3749118 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:51 +0800 Subject: [PATCH 119/147] rockchip: rk3288-firefly: sync sdmmc pinctrl from mainline The rk3288-firefly board have different setting for sdmmc io, sync then from kernel mainline: 6fbc7275c7a9 Linux 5.2-rc7 Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 6 +----- arch/arm/dts/rk3288-firefly.dtsi | 26 ++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 2efb309d6bd..8b9c38310fb 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -29,11 +29,7 @@ u-boot,dm-pre-reloc; }; -&pcfg_pull_none_drv_8ma { - u-boot,dm-spl; -}; - -&pcfg_pull_up_drv_8ma { +&pcfg_pull_up_drv_12ma { u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi index 2239ab9f599..b7f279f706f 100644 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ b/arch/arm/dts/rk3288-firefly.dtsi @@ -320,6 +320,11 @@ output-low; }; + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + act8846 { pwr_hold: pwr-hold { rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; @@ -363,8 +368,27 @@ }; sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; + }; + sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; From 5860d124e4b56a1ffabefa6f18fca76fc8831dbf Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:52 +0800 Subject: [PATCH 120/147] rockchip: miqi-rk3288: add -u-boot.dtsi Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-miqi-u-boot.dtsi | 38 ++++++++++++++++++++++++++++ arch/arm/dts/rk3288-miqi.dts | 18 ------------- 2 files changed, 38 insertions(+), 18 deletions(-) create mode 100644 arch/arm/dts/rk3288-miqi-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi new file mode 100644 index 00000000000..4f63fc9f131 --- /dev/null +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3288-u-boot.dtsi" + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&sdmmc_bus4 { + u-boot,dm-spl; +}; + +&sdmmc_clk { + u-boot,dm-spl; +}; + +&sdmmc_cmd { + u-boot,dm-spl; +}; + +&sdmmc_pwr { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts index 29e60dd125e..e47170c6530 100644 --- a/arch/arm/dts/rk3288-miqi.dts +++ b/arch/arm/dts/rk3288-miqi.dts @@ -25,21 +25,3 @@ 0xa60 0x40 0x10 0x0>; rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; - - -&pinctrl { - u-boot,dm-pre-reloc; -}; - -&uart2 { - u-boot,dm-pre-reloc; - reg-shift = <2>; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; From e124de6233050de84797e36986b382b6a42d08ce Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:53 +0800 Subject: [PATCH 121/147] rockchip: popmetal-rk3288: add -u-boot.dtsi Move U-Boot relate dts node/property into -u-boot.dtsi Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-popmetal-u-boot.dtsi | 46 ++++++++++++++++++++++++ arch/arm/dts/rk3288-popmetal.dts | 26 -------------- 2 files changed, 46 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/rk3288-popmetal-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi new file mode 100644 index 00000000000..8ac7840f8f9 --- /dev/null +++ b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronics Co., Ltd + */ + +#include "rk3288-u-boot.dtsi" + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&sdmmc_bus4 { + u-boot,dm-spl; +}; + +&sdmmc_clk { + u-boot,dm-spl; +}; + +&sdmmc_cmd { + u-boot,dm-spl; +}; + +&sdmmc_pwr { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts index d1e1cd51125..5c6d06f2fdb 100644 --- a/arch/arm/dts/rk3288-popmetal.dts +++ b/arch/arm/dts/rk3288-popmetal.dts @@ -26,32 +26,6 @@ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; - -&pinctrl { - u-boot,dm-pre-reloc; -}; - &pwm1 { status = "okay"; }; - -&uart2 { - u-boot,dm-pre-reloc; - reg-shift = <2>; -}; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; From 032906a858d41a83bf290f144243a1e6be5918fc Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 17 Jul 2019 18:12:20 +0800 Subject: [PATCH 122/147] rockchip: spl-boot-order: update dependency to OF_LIBFDT The fdt interfaces are actuall depends on OF_LIBFDT instead of OF_CONTROL, some boards may enable OF_CONTROL while disable OF_LIBFDT. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/spl-boot-order.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 0e485deda2f..c19c285c070 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -8,7 +8,7 @@ #include #include -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_LIBFDT) /** * spl_node_to_boot_device() - maps from a DT-node to a SPL boot device * @node: of_offset of the node From b39ab7f1e1c84ae3f22141d93e38602c2c179354 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:54 +0800 Subject: [PATCH 123/147] rockchip: rk3288: dts: enable spl-boot-order We share the same default SPL boot order for all rk3288 boards, use dts instead of hard code in board file. Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-u-boot.dtsi | 7 +++++++ arch/arm/mach-rockchip/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 4cf75c75044..3f00a3b6d35 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -3,6 +3,13 @@ * Copyright (C) 2019 Rockchip Electronics Co., Ltd */ +/ { + chosen { + u-boot,spl-boot-order = \ + "same-as-spl", &emmc, &sdmmc; + }; +}; + &dmc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 23760a959ae..0c169e92341 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -17,7 +17,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o -obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o From 35dfc0496d38e57a3c49d055b79a259a0585f44b Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 21:58:55 +0800 Subject: [PATCH 124/147] rockchip: board: rk3288: remove board_boot_order() Prefer to use dts config instead, remove all board_boot_order() for rk3288 boards. Signed-off-by: Kever Yang --- board/amarula/vyasa-rk3288/vyasa-rk3288.c | 8 -------- board/chipspark/popmetal_rk3288/popmetal-rk3288.c | 8 -------- board/mqmaker/miqi_rk3288/miqi-rk3288.c | 9 --------- board/rockchip/evb_rk3288/evb-rk3288.c | 9 --------- board/rockchip/fennec_rk3288/fennec-rk3288.c | 9 --------- 5 files changed, 43 deletions(-) diff --git a/board/amarula/vyasa-rk3288/vyasa-rk3288.c b/board/amarula/vyasa-rk3288/vyasa-rk3288.c index 2b509f529f1..baf197c4851 100644 --- a/board/amarula/vyasa-rk3288/vyasa-rk3288.c +++ b/board/amarula/vyasa-rk3288/vyasa-rk3288.c @@ -6,14 +6,6 @@ #include #ifndef CONFIG_TPL_BUILD -#include - -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard. */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} int spl_start_uboot(void) { diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c index 355c78b7b73..9ba1fbd0e27 100644 --- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c @@ -4,16 +4,8 @@ */ #include -#include #include -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} - #define GPIO7A3_HUB_RST 227 int rk_board_late_init(void) diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c index d6992a26caf..779bc646b2a 100644 --- a/board/mqmaker/miqi_rk3288/miqi-rk3288.c +++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c @@ -3,12 +3,3 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include -#include - -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard. */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c index d6992a26caf..779bc646b2a 100644 --- a/board/rockchip/evb_rk3288/evb-rk3288.c +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -3,12 +3,3 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include -#include - -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard. */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c index ce455449dd7..779bc646b2a 100644 --- a/board/rockchip/fennec_rk3288/fennec-rk3288.c +++ b/board/rockchip/fennec_rk3288/fennec-rk3288.c @@ -3,12 +3,3 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include -#include - -void board_boot_order(u32 *spl_boot_list) -{ - /* eMMC prior to sdcard */ - spl_boot_list[0] = BOOT_DEVICE_MMC2; - spl_boot_list[1] = BOOT_DEVICE_MMC1; -} From f3d689c0e051216cbcc27ab6a30e2d4c2760c46c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:22 +0800 Subject: [PATCH 125/147] rockchip: rk322x: sdram: use udelay instead of rockchip_udelay Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang --- drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index e96ac54c395..94893e17cf5 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -96,26 +95,26 @@ void phy_pctrl_reset(struct rk322x_cru *cru, 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); clrbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_RESET_MASK << SOFT_RESET_SHIFT); - rockchip_udelay(10); + udelay(10); setbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_DERESET_ANALOG); - rockchip_udelay(5); + udelay(5); setbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_DERESET_DIGITAL); - rockchip_udelay(1); + udelay(1); } void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) @@ -154,7 +153,7 @@ static void send_command(struct rk322x_ddr_pctl *pctl, u32 rank, u32 cmd, u32 arg) { writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - rockchip_udelay(1); + udelay(1); while (readl(&pctl->mcmd) & START_CMD) ; } @@ -167,7 +166,7 @@ static void memory_init(struct chan_info *chan, if (dramtype == DDR3) { send_command(pctl, 3, DESELECT_CMD, 0); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, PREA_CMD, 0); send_command(pctl, 3, MRS_CMD, (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | @@ -196,17 +195,17 @@ static void memory_init(struct chan_info *chan, (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0 & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(10); + udelay(10); send_command(pctl, 3, MRS_CMD, (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0xff & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, MRS_CMD, (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0xff & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, MRS_CMD, (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (sdram_params->phy_timing.mr[1] & @@ -243,7 +242,7 @@ static u32 data_training(struct chan_info *chan) DQS_SQU_CAL_SEL_CS0); setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); - rockchip_udelay(30); + udelay(30); ret = readl(&ddr_phy->ddrphy_reg[0xff]); clrbits_le32(&ddr_phy->ddrphy_reg[2], @@ -367,9 +366,9 @@ static void phy_softreset(struct dram_info *dram) writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); - rockchip_udelay(1); + udelay(1); setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); - rockchip_udelay(5); + udelay(5); setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); } From acea1238258eac8c298d3754032cadd4d26193c6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:23 +0800 Subject: [PATCH 126/147] rockchip: rk322x: use ARM arch timer instead of rk_timer We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 30 +++++++++++++++++++++ arch/arm/mach-rockchip/rk322x-board-tpl.c | 33 ++++++++++++++++++++--- include/configs/rk322x_common.h | 7 ++--- scripts/config_whitelist.txt | 1 + 5 files changed, 66 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 0c169e92341..933b0a182ad 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,7 +42,7 @@ endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o ifndef CONFIG_ARM64 -ifndef CONFIG_ROCKCHIP_RK3188 +ifeq ($(CONFIG_ROCKCHIP_RK3188)$(CONFIG_ROCKCHIP_RK322X),) obj-y += rk_timer.o endif endif diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index c9b41c62c08..c825e31c02d 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -19,6 +19,31 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + #define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { @@ -31,6 +56,11 @@ void board_init_f(ulong dummy) } preloader_console_init(); + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + /* Disable the ddr secure region setting to make it non-secure */ rk_clrreg(SGRF_DDR_CON0, 0x4000); } diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c index 92d40ee43ae..a0d7bc9b05a 100644 --- a/arch/arm/mach-rockchip/rk322x-board-tpl.c +++ b/arch/arm/mach-rockchip/rk322x-board-tpl.c @@ -10,13 +10,37 @@ #include #include #include -#include u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -39,8 +63,11 @@ void board_init_f(ulong dummy) hang(); } - rockchip_timer_init(); - printf("timer init done\n"); + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { printf("DRAM init failed: %d\n", ret); diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 15bb8d63b84..cc086999441 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -13,9 +13,10 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x61100000 #define CONFIG_SYS_LOAD_ADDR 0x61800800 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index bd167959b3f..e616f7229b4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1532,6 +1532,7 @@ CONFIG_RMSTP9_ENA CONFIG_ROCKCHIP_CHIP_TAG CONFIG_ROCKCHIP_MAX_INIT_SIZE CONFIG_ROCKCHIP_SDHCI_MAX_FREQ +CONFIG_ROCKCHIP_STIMER_BASE CONFIG_ROM_STUBS CONFIG_ROOTFS_OFFSET CONFIG_ROOTPATH From 19d0de3ee4d0f4fc13f09303fbbe91bf8d8d81d8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:24 +0800 Subject: [PATCH 127/147] rockchip: rk3036: sdram: use udelay instead of rockchip_udelay Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 1d940a0d77c..c39cbb8111a 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -9,7 +9,6 @@ #include #include #include -#include #include /* @@ -345,7 +344,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv) /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) - rockchip_udelay(1); + udelay(1); /* PLL enter normal-mode */ rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, @@ -373,25 +372,25 @@ void phy_pctrl_reset(struct rk3036_sdram_priv *priv) 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); clrsetbits_le32(&ddr_phy->ddrphy_reg1, SOFT_RESET_MASK << SOFT_RESET_SHIFT, 0 << SOFT_RESET_SHIFT); - rockchip_udelay(10); + udelay(10); clrsetbits_le32(&ddr_phy->ddrphy_reg1, SOFT_RESET_MASK << SOFT_RESET_SHIFT, 3 << SOFT_RESET_SHIFT); - rockchip_udelay(1); + udelay(1); } void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq) @@ -444,7 +443,7 @@ static void send_command(struct rk3036_ddr_pctl *pctl, u32 rank, u32 cmd, u32 arg) { writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - rockchip_udelay(1); + udelay(1); while (readl(&pctl->mcmd) & START_CMD) ; } @@ -454,7 +453,7 @@ static void memory_init(struct rk3036_sdram_priv *priv) struct rk3036_ddr_pctl *pctl = priv->pctl; send_command(pctl, 3, DESELECT_CMD, 0); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, PREA_CMD, 0); send_command(pctl, 3, MRS_CMD, (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | @@ -492,7 +491,7 @@ static void data_training(struct rk3036_sdram_priv *priv) clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START); - rockchip_udelay(1); + udelay(1); while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) { ; From 002d897fb143826e48c59342428748c556dcbda0 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:25 +0800 Subject: [PATCH 128/147] rockchip: rk3036: use ARM arch timer instead of rk_timer We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track the boot time. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/rk3036-board-spl.c | 29 ++++++++++++++++++++--- include/configs/rk3036_common.h | 7 +++--- 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 933b0a182ad..2a0db0af80b 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,7 +42,7 @@ endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o ifndef CONFIG_ARM64 -ifeq ($(CONFIG_ROCKCHIP_RK3188)$(CONFIG_ROCKCHIP_RK322X),) +ifeq ($(CONFIG_ROCKCHIP_RK3188)$(CONFIG_ROCKCHIP_RK322X)$(CONFIG_ROCKCHIP_RK3036),) obj-y += rk_timer.o endif endif diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 110d06dba5e..fbc89b66c47 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd */ #include @@ -8,14 +8,37 @@ #include #include #include -#include + +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void rockchip_stimer_init(void) +{ + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} void board_init_f(ulong dummy) { #ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif - rockchip_timer_init(); + + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + sdram_init(); /* return to maskrom */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index f5d09d18e5e..73be079b20f 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -12,9 +12,10 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 From ae5a3659f38acd7537c0ae86c7217b9cf40595fb Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:26 +0800 Subject: [PATCH 129/147] rockchip: rk3288: use ARM arch timer instead of rk_timer We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Makefile | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 32 +++++++++++++++++++++-- arch/arm/mach-rockchip/rk3288-board-tpl.c | 25 ++++++++++++++++-- include/configs/rk3288_common.h | 7 ++--- 4 files changed, 58 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 2a0db0af80b..3e3aa1c4214 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,7 +42,7 @@ endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o ifndef CONFIG_ARM64 -ifeq ($(CONFIG_ROCKCHIP_RK3188)$(CONFIG_ROCKCHIP_RK322X)$(CONFIG_ROCKCHIP_RK3036),) +ifeq ($(CONFIG_ROCKCHIP_RK3188)$(CONFIG_ROCKCHIP_RK322X)$(CONFIG_ROCKCHIP_RK3036)$(CONFIG_ROCKCHIP_RK3288),) obj-y += rk_timer.o endif endif diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 3869de91193..c2e168192c2 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -108,6 +107,31 @@ __weak int arch_cpu_init(void) return 0; } +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -131,7 +155,11 @@ void board_init_f(ulong dummy) hang(); } - rockchip_timer_init(); + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + arch_cpu_init(); ret = rockchip_get_clk(&dev); diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c index 5adbe921852..96de7927f06 100644 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c @@ -12,7 +12,25 @@ #include #include #include -#include + +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} void board_init_f(ulong dummy) { @@ -36,7 +54,10 @@ void board_init_f(ulong dummy) hang(); } - rockchip_timer_init(); + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); ret = rockchip_get_clk(&dev); if (ret) { diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 06073cbb611..5472a90633c 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -13,9 +13,10 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x0 once return from SPL */ From 1e72a757bb32e3ccc4fe5d23baaa6d19b3760a1e Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:27 +0800 Subject: [PATCH 130/147] rockchip: rk3128: use ARM arch timer instead of rk_timer We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track to boot time. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Makefile | 6 ------ arch/arm/mach-rockchip/rk3128-board.c | 3 --- include/configs/rk3128_common.h | 7 ++++--- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 3e3aa1c4214..9afbb055d57 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -41,12 +41,6 @@ endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o -ifndef CONFIG_ARM64 -ifeq ($(CONFIG_ROCKCHIP_RK3188)$(CONFIG_ROCKCHIP_RK322X)$(CONFIG_ROCKCHIP_RK3036)$(CONFIG_ROCKCHIP_RK3288),) -obj-y += rk_timer.o -endif -endif - obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c index fa71685af80..0945829d0e4 100644 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -12,7 +12,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -33,8 +32,6 @@ int board_init(void) { int ret = 0; - rockchip_timer_init(); - ret = regulators_enable_boot_on(false); if (ret) { debug("%s: Cannot enable boot on regulator\n", __func__); diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 0c08d7af5b3..20d62439fbb 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -14,9 +14,10 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 +#define COUNTER_FREQUENCY 24000000 +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 From 243f48b8038cbd82441f7a561cc72991f96e459f Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:28 +0800 Subject: [PATCH 131/147] rockchip: remove no use header file in board code The timer.h is no use any more, remove it from the board files. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3188-board-spl.c | 1 - arch/arm/mach-rockchip/rk3368-board-tpl.c | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 84c2a5756fa..c3efe0d7a95 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index dc65a021c81..42aeb2e91cf 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -14,7 +14,6 @@ #include #include #include -#include /* * The SPL (and also the full U-Boot stage on the RK3368) will run in From 0845a0ee669e9c360919d7cf0cc45771e3dca6ea Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:29 +0800 Subject: [PATCH 132/147] rockchip: remove rk_timer We have convert all SoC to use DM timer or ARM arch/generic timer, we can remove this rk_timer now. Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/timer.h | 3 -- arch/arm/mach-rockchip/rk_timer.c | 40 ---------------------- 2 files changed, 43 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk_timer.c diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h index a8379be9125..77b54220447 100644 --- a/arch/arm/include/asm/arch-rockchip/timer.h +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -15,7 +15,4 @@ struct rk_timer { u32 timer_int_status; }; -void rockchip_timer_init(void); -void rockchip_udelay(unsigned int usec); - #endif diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c deleted file mode 100644 index 29d379fa0ab..00000000000 --- a/arch/arm/mach-rockchip/rk_timer.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include - -struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; - -static uint64_t rockchip_get_ticks(void) -{ - uint64_t timebase_h, timebase_l; - - timebase_l = readl(&timer_ptr->timer_curr_value0); - timebase_h = readl(&timer_ptr->timer_curr_value1); - - return timebase_h << 32 | timebase_l; -} - -void rockchip_udelay(unsigned int usec) -{ - uint64_t tmp; - - /* get timestamp */ - tmp = rockchip_get_ticks() + usec_to_tick(usec); - - /* loop till event */ - while (rockchip_get_ticks() < tmp+1) - ; -} - -void rockchip_timer_init(void) -{ - writel(0xffffffff, &timer_ptr->timer_load_count0); - writel(0xffffffff, &timer_ptr->timer_load_count1); - writel(1, &timer_ptr->timer_ctrl_reg); -} From 1f6b599b6d2479ad51981bc753abcaed25907f8b Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:30 +0800 Subject: [PATCH 133/147] rockchip: rk3368: move sgrf init to spl as arch_cpu_init() The SoC related init will move to SPL and keep TPL clean, so that we can reuse the common TPL board file. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3368-board-spl.c | 6 ++ arch/arm/mach-rockchip/rk3368-board-tpl.c | 69 --------------------- arch/arm/mach-rockchip/rk3368/rk3368.c | 75 ++++++++++++++++++++++- 3 files changed, 80 insertions(+), 70 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index c6511937123..3a7d0b640ae 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -11,6 +11,11 @@ #include #include +__weak int arch_cpu_init(void) +{ + return 0; +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -22,6 +27,7 @@ void board_init_f(ulong dummy) hang(); } + arch_cpu_init(); preloader_console_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index 42aeb2e91cf..a1da8ccb0f0 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -8,74 +8,8 @@ #include #include #include -#include #include #include -#include -#include -#include - -/* - * The SPL (and also the full U-Boot stage on the RK3368) will run in - * secure mode (i.e. EL3) and an ATF will eventually be booted before - * starting up the operating system... so we can initialize the SGRF - * here and rely on the ATF installing the final (secure) policy - * later. - */ -static inline uintptr_t sgrf_soc_con_addr(unsigned no) -{ - const uintptr_t SGRF_BASE = - (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - - return SGRF_BASE + sizeof(u32) * no; -} - -static inline uintptr_t sgrf_busdmac_addr(unsigned no) -{ - const uintptr_t SGRF_BASE = - (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; - const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; - - return SGRF_BUSDMAC_BASE + sizeof(u32) * no; -} - -static void sgrf_init(void) -{ - struct rk3368_cru * const cru = - (struct rk3368_cru * const)rockchip_get_cru(); - const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); - const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); - const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); - - /* Set all configurable IP to 'non secure'-mode */ - rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); - rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); - rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); - - /* - * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c - * Original comment: "ddr space set no secure mode" - */ - rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); - rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); - rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); - - /* Set 'secure dma' to 'non secure'-mode */ - rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); - rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); - - dsb(); /* barrier */ - - rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); - rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); - - dsb(); /* barrier */ - udelay(10); - - rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); - rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); -} void board_init_f(ulong dummy) { @@ -101,9 +35,6 @@ void board_init_f(ulong dummy) hang(); } - /* Reset security, so we can use DMA in the MMC drivers */ - sgrf_init(); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index f06d27717de..47786f52ee3 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -5,12 +5,13 @@ */ #include +#include #include #include #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -97,6 +98,78 @@ int arch_early_init_r(void) } #endif +#ifdef CONFIG_SPL_BUILD +/* + * The SPL (and also the full U-Boot stage on the RK3368) will run in + * secure mode (i.e. EL3) and an ATF will eventually be booted before + * starting up the operating system... so we can initialize the SGRF + * here and rely on the ATF installing the final (secure) policy + * later. + */ +static inline uintptr_t sgrf_soc_con_addr(unsigned int no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + + return SGRF_BASE + sizeof(u32) * no; +} + +static inline uintptr_t sgrf_busdmac_addr(unsigned int no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; + const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; + + return SGRF_BUSDMAC_BASE + sizeof(u32) * no; +} + +static void sgrf_init(void) +{ + struct rk3368_cru * const cru = + (struct rk3368_cru * const)rockchip_get_cru(); + const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); + const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); + const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); + + /* Set all configurable IP to 'non secure'-mode */ + rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); + + /* + * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c + * Original comment: "ddr space set no secure mode" + */ + rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); + + /* Set 'secure dma' to 'non secure'-mode */ + rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); + rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); + + dsb(); /* barrier */ + + rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); + + dsb(); /* barrier */ + udelay(10); + + rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); +} + +int arch_cpu_init(void) +{ + /* Reset security, so we can use DMA in the MMC drivers */ + sgrf_init(); + + return 0; +} +#endif + #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { From 192445b39c0e852f7f2c054c935bbe02f7a8ea22 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:31 +0800 Subject: [PATCH 134/147] rockchip: rk3368: enable stimer for rk3368 Add stimer_init() for spl/tpl so that we able to switch to use arch timer. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3368-board-spl.c | 27 +++++++++++++++++++++++ arch/arm/mach-rockchip/rk3368-board-tpl.c | 21 ++++++++++++++++++ include/configs/rk3368_common.h | 3 ++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index 3a7d0b640ae..6ba106c63bd 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -16,6 +16,28 @@ __weak int arch_cpu_init(void) return 0; } +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -27,6 +49,11 @@ void board_init_f(ulong dummy) hang(); } + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); + arch_cpu_init(); preloader_console_init(); diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index a1da8ccb0f0..fdb1c3b3655 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -11,6 +11,22 @@ #include #include +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +__weak void rockchip_stimer_init(void) +{ + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -35,6 +51,11 @@ void board_init_f(ulong dummy) hang(); } + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/ */ + timer_init(); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 13630ba386c..8a1e3118aeb 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -20,7 +20,8 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define COUNTER_FREQUENCY 24000000 +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 +#define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_NS16550_MEM32 From 08b902dc39959b577446416b98672cb7548973fc Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:32 +0800 Subject: [PATCH 135/147] rockchip: rk3368-lion: switch to use ARM generic timer Default to use ARM generic timer in ARM64, switch from rk timer to generic timer. Signed-off-by: Kever Yang --- arch/arm/dts/rk3368-lion-u-boot.dtsi | 1 - configs/lion-rk3368_defconfig | 4 ---- 2 files changed, 5 deletions(-) diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi index fb4a4fb59ca..edc93e438f9 100644 --- a/arch/arm/dts/rk3368-lion-u-boot.dtsi +++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi @@ -12,7 +12,6 @@ chosen { stdout-path = "serial0:115200n8"; u-boot,spl-boot-order = &emmc, &sdmmc; - tick-timer = "/timer@ff810000"; }; }; diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index ff3255be7a1..2c4e11c4d4f 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -88,10 +88,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y -CONFIG_TIMER=y -CONFIG_SPL_TIMER=y -CONFIG_TPL_TIMER=y -CONFIG_ROCKCHIP_TIMER=y CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_TINY_MEMSET=y CONFIG_LZO=y From 1dea50fb22cf51226ccdef6c94eb5355635c902d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:00:33 +0800 Subject: [PATCH 136/147] rockchip: evb-px5: switch to use ARM generic timer Default to use ARM generic timer in ARM64, switch from rk timer to generic timer. Signed-off-by: Kever Yang --- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 1 - configs/evb-px5_defconfig | 4 ---- 2 files changed, 5 deletions(-) diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index f5406d4c7e1..002767a0330 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -5,7 +5,6 @@ / { chosen { u-boot,spl-boot-order = &emmc; - tick-timer = "/timer@ff810000"; }; }; diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 9afba9b8733..a2b72c765d1 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -67,10 +67,6 @@ CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYSRESET=y -CONFIG_TIMER=y -CONFIG_SPL_TIMER=y -CONFIG_TPL_TIMER=y -CONFIG_ROCKCHIP_TIMER=y CONFIG_USE_TINY_PRINTF=y CONFIG_PANIC_HANG=y CONFIG_SPL_TINY_MEMSET=y From 18f85080eb9fd790986c9cea2fde64d47355d26a Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:05:55 +0800 Subject: [PATCH 137/147] rockchip: add common tpl board file Rockchip SoCs have similar boot process, prefer to use TPL for DRAM init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL common board is a basic TPL board init which can be shared for most of SoCs to avoid copy-pase for different SoCs. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 9 ++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/tpl.c | 86 +++++++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) create mode 100644 arch/arm/mach-rockchip/tpl.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 85f88cea779..2b83a684891 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -223,6 +223,15 @@ config TPL_ROCKCHIP_BACK_TO_BROM SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. +config TPL_ROCKCHIP_COMMON_BOARD + bool "" + depends on TPL + help + Rockchip SoCs have similar boot process, prefer to use TPL for DRAM + init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL + common board is a basic TPL board init which can be shared for most + of SoCs to avoid copy-pase for different SoCs. + config ROCKCHIP_BOOT_MODE_REG hex "Rockchip boot mode flag register address" help diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 9afbb055d57..2686e0c46c2 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -8,6 +8,7 @@ # the stack-pointer is valid before switching to the U-Boot stack). obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o +obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c new file mode 100644 index 00000000000..0ff2a197edb --- /dev/null +++ b/arch/arm/mach-rockchip/tpl.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +__weak void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + +#ifndef CONFIG_ARM64 + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); +#endif + + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#ifdef CONFIG_DEBUG_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ + U_BOOT_TIME ")\n"); +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + /* Init secure timer */ + rockchip_stimer_init(); + /* Init ARM arch timer in arch/arm/cpu/ */ + timer_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} From 6ae28a30e9ad88137bb03530118de3d5e2663df4 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:05:56 +0800 Subject: [PATCH 138/147] rockchip: rk322x: use common TPL board file Use Common tpl.c instead of rk322x-board-tpl.c Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/Makefile | 1 - arch/arm/mach-rockchip/rk322x-board-tpl.c | 80 ----------------------- 3 files changed, 1 insertion(+), 81 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 2b83a684891..99a4265b66d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -59,6 +59,7 @@ config ROCKCHIP_RK322X select SPL_DRIVERS_MISC_SUPPORT imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT + imply TPL_ROCKCHIP_COMMON_BOARD select ROCKCHIP_BROM_HELPER select TPL_LIBCOMMON_SUPPORT select TPL_LIBGENERIC_SUPPORT diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 2686e0c46c2..b21742110e1 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,7 +12,6 @@ obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c deleted file mode 100644 index a0d7bc9b05a..00000000000 --- a/arch/arm/mach-rockchip/rk322x-board-tpl.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -#include -#include - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -void rockchip_stimer_init(void) -{ - /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - - if (reg & TIMER_EN) - return; - - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("TPL Init"); - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Init secure timer */ - rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ - timer_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); - return; - } - -#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} From 3338f544b14fa7bcfe4460022fb52882ce7efdd4 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:05:57 +0800 Subject: [PATCH 139/147] rockchip: rk3288: use common TPL board file Use Common tpl.c instead of rk3288-board-tpl.c Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/Makefile | 1 - arch/arm/mach-rockchip/rk3288-board-tpl.c | 89 ----------------------- 3 files changed, 1 insertion(+), 90 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 99a4265b66d..8a7f2bbea05 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -88,6 +88,7 @@ config ROCKCHIP_RK3288 imply TPL_OF_PLATDATA imply TPL_RAM imply TPL_REGMAP + imply TPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL_SUPPORT imply TPL_SYSCON imply USB_FUNCTION_ROCKUSB diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index b21742110e1..d01293bd25d 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -10,7 +10,6 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c deleted file mode 100644 index 96de7927f06..00000000000 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Amarula Solutions - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -void rockchip_stimer_init(void) -{ - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); -#endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Init secure timer */ - rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ - timer_init(); - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ - U_BOOT_TIME ")\n"); -} From 82560cb311017a656e83f797e5480768c16d7a6d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:05:58 +0800 Subject: [PATCH 140/147] rockchip: rk3368: use common TPL board file Use common tpl.c instead of rk3368-board-tpl.c Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/Makefile | 1 - arch/arm/mach-rockchip/rk3368-board-tpl.c | 74 ----------------------- 3 files changed, 1 insertion(+), 75 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 8a7f2bbea05..3c17994452b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -127,6 +127,7 @@ config ROCKCHIP_RK3368 imply SPL_SEPARATE_BSS imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT + imply TPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised into a big and little cluster with 4 cores each) Cortex-A53 including diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index d01293bd25d..c1b1c31d02c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -10,7 +10,6 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c deleted file mode 100644 index fdb1c3b3655..00000000000 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include -#include -#include -#include -#include -#include -#include - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -__weak void rockchip_stimer_init(void) -{ - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("U-Boot TPL board init\n"); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Init secure timer */ - rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/ */ - timer_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} From 87ac550862edd3540be4030f2bc266f4b5182fa3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:05:59 +0800 Subject: [PATCH 141/147] rockchip: rk3399: use common secure_timer_init() for spl/tpl SPL/TPL share the same secure_timer_init(), update to use one copy source code and update to use CONFIG_ROCKCHIP_STIMER_BASE as base address and rename to function name to rockchip_stimer_init(). Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3399-board-spl.c | 21 ++-------------- arch/arm/mach-rockchip/rk3399-board-tpl.c | 20 ++-------------- arch/arm/mach-rockchip/rk3399/rk3399.c | 29 +++++++++++++++++++++++ include/configs/rk3399_common.h | 1 + 4 files changed, 34 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 2333694caa0..7154d8e5d08 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -109,27 +109,10 @@ void spl_perform_fixups(struct spl_image_info *spl_image) "u-boot,spl-boot-device", boot_ofpath); } -#define TIMER_CHN10_BASE 0xff8680a0 -#define TIMER_END_COUNT_L 0x00 -#define TIMER_END_COUNT_H 0x04 -#define TIMER_INIT_COUNT_L 0x10 -#define TIMER_INIT_COUNT_H 0x14 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) +__weak void rockchip_stimer_init(void) { - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); - writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } - void board_init_f(ulong dummy) { struct udevice *dev; @@ -188,7 +171,7 @@ void board_init_f(ulong dummy) grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); rk_clrreg(&grf->emmccore_con[11], 0x0ff); - secure_timer_init(); + rockchip_stimer_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c index 4a301249b49..740470de460 100644 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -12,24 +12,8 @@ #include #include -#define TIMER_CHN10_BASE 0xff8680a0 -#define TIMER_END_COUNT_L 0x00 -#define TIMER_END_COUNT_H 0x04 -#define TIMER_INIT_COUNT_L 0x10 -#define TIMER_INIT_COUNT_H 0x14 -#define TIMER_CONTROL_REG 0x1c - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) +__weak void rockchip_stimer_init(void) { - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); - writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); - writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); - writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } void board_init_f(ulong dummy) @@ -55,7 +39,7 @@ void board_init_f(ulong dummy) hang(); } - secure_timer_init(); + rockchip_stimer_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index e1f9f8b8efe..0f09ea5c499 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -38,6 +38,35 @@ static struct mm_region rk3399_mem_map[] = { struct mm_region *mem_map = rk3399_mem_map; +#ifdef CONFIG_SPL_BUILD + +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; + + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H); + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L); + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \ + TIMER_CONTROL_REG); +} +#endif + int dram_init_banksize(void) { size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index f31f2658bb8..8df01802845 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -13,6 +13,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define COUNTER_FREQUENCY 24000000 +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 #define CONFIG_SYS_NS16550_MEM32 From 682a99c634eadc7e62893270c5490fd3b78e8612 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:06:00 +0800 Subject: [PATCH 142/147] rockchip: rk3399: remove TPL_BOARD_INIT RK3399 TPL do not need a dedicate board init, print the firmware info when debug init instead. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 - arch/arm/mach-rockchip/rk3399-board-tpl.c | 9 ++------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 3c17994452b..28bae2e7ee3 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -173,7 +173,6 @@ config ROCKCHIP_RK3399 imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE - imply TPL_BOARD_INIT imply TPL_BOOTROM_SUPPORT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_OF_CONTROL diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c index 740470de460..117b74cf4b3 100644 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -31,7 +31,8 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - debug("U-Boot TPL board init\n"); + printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " + U_BOOT_TIME " " U_BOOT_TZ ")\n"); #endif ret = spl_early_init(); if (ret) { @@ -58,12 +59,6 @@ u32 spl_boot_device(void) return BOOT_DEVICE_BOOTROM; } -void spl_board_init(void) -{ - puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " - U_BOOT_TIME " " U_BOOT_TZ ")\n"); -} - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { From 2738181eb98482d683a3bedfad047d81cafe4a99 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 9 Jul 2019 22:06:01 +0800 Subject: [PATCH 143/147] rockchip: rk3399: use common TPL board file Use common tpl.c instead of rk3399-board-tpl.c Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/Makefile | 2 - arch/arm/mach-rockchip/rk3399-board-tpl.c | 70 ----------------------- 3 files changed, 1 insertion(+), 72 deletions(-) delete mode 100644 arch/arm/mach-rockchip/rk3399-board-tpl.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 28bae2e7ee3..2f0d7413869 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -182,6 +182,7 @@ config ROCKCHIP_RK3399 imply TPL_RAM imply TPL_CLK imply TPL_TINY_MEMSET + imply TPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index c1b1c31d02c..a12b8d4434e 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -10,8 +10,6 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o -obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o - obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c deleted file mode 100644 index 117b74cf4b3..00000000000 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2019 Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -__weak void rockchip_stimer_init(void) -{ -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " - U_BOOT_TIME " " U_BOOT_TZ ")\n"); -#endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - rockchip_stimer_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - pr_err("DRAM init failed: %d\n", ret); - return; - } -} - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif From 79cdcaced710d955f68066d02327b86be573339c Mon Sep 17 00:00:00 2001 From: Niklas Schulze Date: Sun, 14 Jul 2019 10:40:13 +0000 Subject: [PATCH 144/147] rockchip: video: rk3288_hdmi: Add missing call to dw_hdmi_enable() The RK3288 HDMI driver's rk3288_hdmi_enable() currently lacks a call to dw_hdmi_enable(). Thus, the HDMI output never gets enabled. Signed-off-by: Niklas Schulze Cc: Philipp Tomsich Reviewed-by: Kever Yang Reviewed-by: Philipp Tomsich --- drivers/video/rockchip/rk3288_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c index 315d3adf275..3d25ce924c2 100644 --- a/drivers/video/rockchip/rk3288_hdmi.c +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -33,7 +33,7 @@ static int rk3288_hdmi_enable(struct udevice *dev, int panel_bpp, /* hdmi data from vop id */ rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); - return 0; + return dw_hdmi_enable(&priv->hdmi, edid); } static int rk3288_hdmi_ofdata_to_platdata(struct udevice *dev) From fb7b1b79c182ae00cbcdbaf56b57434479262db6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 16 Jul 2019 20:40:17 +0800 Subject: [PATCH 145/147] rockchip: enable rk322x TPL_BOOTROM_SUPPORT in Kconfig The TPL_BOOTROM_SUPPORT is needed for boot from bootrom like other storages. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 2f0d7413869..17f31e89f35 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -59,6 +59,7 @@ config ROCKCHIP_RK322X select SPL_DRIVERS_MISC_SUPPORT imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT + imply TPL_BOOTROM_SUPPORT imply TPL_ROCKCHIP_COMMON_BOARD select ROCKCHIP_BROM_HELPER select TPL_LIBCOMMON_SUPPORT From f05d5743567984b4fff6a862fc0f42760ff135da Mon Sep 17 00:00:00 2001 From: Chris Webb Date: Tue, 16 Jul 2019 20:52:57 +0100 Subject: [PATCH 146/147] rockchip: make_fit_atf.py: Eliminate pyelftools dependency make_fit_aft.py depends on the non-standard library pyelftools to pull out PT_LOAD segments from ELF files. However, this is as easy to do manually, without imposing the extra dependency on users. Structures in the ELF file are unpacked into variables named to exactly match the ELF spec to ensure the destructuring code is reasonably self-documenting. Signed-off-by: Chris Webb Reviewed-by: Andy Yan Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/make_fit_atf.py | 73 +++++++++++--------------- 1 file changed, 31 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index db0ae96ca84..b9a19882984 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -13,16 +13,7 @@ import os import sys import getopt import logging - -# pip install pyelftools -from elftools.elf.elffile import ELFFile - -ELF_SEG_P_TYPE = 'p_type' -ELF_SEG_P_PADDR = 'p_paddr' -ELF_SEG_P_VADDR = 'p_vaddr' -ELF_SEG_P_OFFSET = 'p_offset' -ELF_SEG_P_FILESZ = 'p_filesz' -ELF_SEG_P_MEMSZ = 'p_memsz' +import struct DT_HEADER = """ /* @@ -118,33 +109,19 @@ def append_conf_node(file, dtbs, segments): file.write('\n') def generate_atf_fit_dts_uboot(fit_file, uboot_file_name): - num_load_seg = 0 - p_paddr = 0xFFFFFFFF - with open(uboot_file_name, 'rb') as uboot_file: - uboot = ELFFile(uboot_file) - for i in range(uboot.num_segments()): - seg = uboot.get_segment(i) - if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD': - p_paddr = seg.__getitem__(ELF_SEG_P_PADDR) - num_load_seg = num_load_seg + 1 - - assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1) - + segments = unpack_elf(uboot_file_name) + if len(segments) != 1: + raise ValueError("Invalid u-boot ELF image '%s'" % uboot_file_name) + index, entry, p_paddr, data = segments[0] fit_file.write(DT_UBOOT % p_paddr) def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name): - with open(bl31_file_name, 'rb') as bl31_file: - bl31 = ELFFile(bl31_file) - elf_entry = bl31.header['e_entry'] - segments = bl31.num_segments() - for i in range(segments): - seg = bl31.get_segment(i) - if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD': - paddr = seg.__getitem__(ELF_SEG_P_PADDR) - append_bl31_node(fit_file, i + 1, paddr, elf_entry) + segments = unpack_elf(bl31_file_name) + for index, entry, paddr, data in segments: + append_bl31_node(fit_file, index + 1, paddr, entry) append_fdt_node(fit_file, dtbs_file_name) fit_file.write(DT_IMAGES_NODE_END) - append_conf_node(fit_file, dtbs_file_name, segments) + append_conf_node(fit_file, dtbs_file_name, len(segments)) def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name): # Generate FIT script for ATF image. @@ -162,17 +139,29 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi fit_file.close() def generate_atf_binary(bl31_file_name): - with open(bl31_file_name, 'rb') as bl31_file: - bl31 = ELFFile(bl31_file) + for index, entry, paddr, data in unpack_elf(bl31_file_name): + file_name = 'bl31_0x%08x.bin' % paddr + with open(file_name, "wb") as atf: + atf.write(data) - num = bl31.num_segments() - for i in range(num): - seg = bl31.get_segment(i) - if seg.__getitem__(ELF_SEG_P_TYPE) == 'PT_LOAD': - paddr = seg.__getitem__(ELF_SEG_P_PADDR) - file_name = 'bl31_0x%08x.bin' % paddr - with open(file_name, "wb") as atf: - atf.write(seg.data()) +def unpack_elf(filename): + with open(filename, 'rb') as file: + elf = file.read() + if elf[0:7] != b'\x7fELF\x02\x01\x01' or elf[18:20] != b'\xb7\x00': + raise ValueError("Invalid arm64 ELF file '%s'" % filename) + + e_entry, e_phoff = struct.unpack_from('<2Q', elf, 0x18) + e_phentsize, e_phnum = struct.unpack_from('<2H', elf, 0x36) + segments = [] + + for index in range(e_phnum): + offset = e_phoff + e_phentsize * index + p_type, p_flags, p_offset = struct.unpack_from(' Date: Tue, 16 Jul 2019 20:53:26 +0100 Subject: [PATCH 147/147] rockchip: Remove obsolete references to pyelftools make_fit_atf.py no longer requires pyelftools, and nothing else in the rockchip build requires it either, so remove references to installing it from the documentation. Signed-off-by: Chris Webb Reviewed-by: Kever Yang --- board/rockchip/evb_rk3399/README | 6 ------ doc/README.rockchip | 4 ---- 2 files changed, 10 deletions(-) diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README index 64698219872..ea3258cf378 100644 --- a/board/rockchip/evb_rk3399/README +++ b/board/rockchip/evb_rk3399/README @@ -35,12 +35,6 @@ Get the Source and prebuild binary > git clone https://github.com/rockchip-linux/rkbin.git > git clone https://github.com/rockchip-linux/rkdeveloptool.git -Get some prerequisites -====================== - -You need the Python elftools.elf.elffile library for make_fit_atf.py to work: - - > sudo apt-get install python-pyelftools Compile ATF =========== diff --git a/doc/README.rockchip b/doc/README.rockchip index 02e2497b158..8ccbb872645 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -123,10 +123,6 @@ For example: Option 2: Package the image with SPL: - - We need the Python elftools.elf.elffile library for make_fit_atf.py to work - - => sudo apt-get install python-pyelftools - - Export cross compiler path for aarch64 - Compile ATF