From 4ab0a58a9067bb6ceacccefe98cc7db8cbed79c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:30:19 +0200 Subject: [PATCH 1/7] mtd: rpc: renesas: Add R-Car Gen4 DT compatible Add device tree compatible string "renesas,rcar-gen4-rpc-if" to the driver to match on upstream RPC DT node in R-Car Gen4 DTs. Signed-off-by: Marek Vasut --- drivers/mtd/renesas_rpc_hf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 941f2040983..03545822b07 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -387,6 +387,7 @@ static int rpc_hf_probe(struct udevice *dev) static const struct udevice_id rpc_hf_ids[] = { { .compatible = "renesas,r7s72100-rpc-if" }, { .compatible = "renesas,rcar-gen3-rpc-if" }, + { .compatible = "renesas,rcar-gen4-rpc-if" }, {} }; From 1cc7c7e119a31c64cf64d887374c95b58ffe9993 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:44 +0200 Subject: [PATCH 2/7] mtd: spi: renesas: Write DREAR register once Instead of writing DREAR with 0 first and then overwriting DREAR again in case of 4 byte addressing mode, write DREAR in every case once with the correct content right away. No functional change. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index e6b602cf7b4..749c686a6c4 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -277,14 +277,15 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR); smenr |= RPC_DRENR_CDE; - writel(0, priv->regs + RPC_DREAR); if (op->addr.nbytes == 4) { writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1), priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0xF); } else if (op->addr.nbytes == 3) { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0x7); } else { + writel(0, priv->regs + RPC_DREAR); smenr |= RPC_DRENR_ADE(0); } From 3fba388e611e27e663c7cb4c1d1483e8909bdbc0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:45 +0200 Subject: [PATCH 3/7] mtd: spi: renesas: Write DRDMCR register once Instead of writing DRDMCR with 0 first and then overwriting DRDMCR again in case any dummy bytes have to be sent out, write DRDMCR in every case with the amount of dummy bytes that have to be sent out. In case no dummy bytes have to be sent out, the value written into DRDMCR is zero, so no dummy bytes are sent out. No functional change. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 749c686a6c4..a2ac5525b90 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -289,12 +289,10 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, smenr |= RPC_DRENR_ADE(0); } - writel(0, priv->regs + RPC_DRDMCR); - if (op->dummy.nbytes) { - writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); + if (op->dummy.nbytes) smenr |= RPC_DRENR_DME; - } + writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); writel(0, priv->regs + RPC_DROPR); writel(smenr, priv->regs + RPC_DRENR); From c90795076b30c33a95bcaf6d89979543d31fdde1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:46 +0200 Subject: [PATCH 4/7] mtd: spi: renesas: Configure DRDRENR register Make sure DRDRENR register is configured before performing external address space read. This register might have been configured by a prior stage bootloader and leaving it unconfigured would interfere with U-Boot operation. Since U-Boot RPC SPI driver does not support DDR data transfer mode yet, set this register unconditionally to 0. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index a2ac5525b90..50890981149 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -294,6 +294,7 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi, writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); writel(0, priv->regs + RPC_DROPR); + writel(0, priv->regs + RPC_DRDRENR); writel(smenr, priv->regs + RPC_DRENR); memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes); From d5162463243da66b27ac7ea96fcffb5da4c9a639 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:47 +0200 Subject: [PATCH 5/7] mtd: spi: renesas: Configure RPC PHY timing registers Make sure RPC PHY timing registers are configured before performing bus access. These registers might have been left unconfigured or may have been configured by a prior stage bootloader and leaving them unconfigured or misconfigured would interfere with U-Boot operation. Set PHYOFFSET1 DDRTMG field to 3 which enables DDR timing adjustment when SPIDRE or DRDRE = 0 and set PHYOFFSET2 OCTTMG field to 4 which makes the interface operate in Serial flash or HyperFlash mode. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 50890981149..9aab71db1de 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -145,6 +145,12 @@ #define RPC_PHYCNT_WBUF BIT(2) #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) +#define RPCIF_PHYOFFSET1 0x0080 /* R/W */ +#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) + +#define RPCIF_PHYOFFSET2 0x0084 /* R/W */ +#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) + #define RPC_PHYINT 0x0088 /* R/W */ #define RPC_PHYINT_RSTEN BIT(18) #define RPC_PHYINT_WPEN BIT(17) @@ -227,6 +233,12 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual) struct udevice *bus = dev->parent; struct rpc_spi_priv *priv = dev_get_priv(bus); + setbits_le32(priv->regs + RPCIF_PHYOFFSET1, + RPCIF_PHYOFFSET1_DDRTMG(3)); + clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2, + RPCIF_PHYOFFSET2_OCTTMG(7), + RPCIF_PHYOFFSET2_OCTTMG(4)); + /* NOTE: The 0x260 are undocumented bits, but they must be set. */ writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT); From 2e255d2e6e1a8b56f594de4e6f969c97ce1aff46 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:31:48 +0200 Subject: [PATCH 6/7] mtd: spi: renesas: Add R-Car Gen4 DT compatible Add device tree compatible string "renesas,rcar-gen4-rpc-if" to the driver to match on upstream RPC DT node in R-Car Gen4 DTs. Signed-off-by: Marek Vasut --- drivers/spi/renesas_rpc_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 9aab71db1de..f1e6f9f4e01 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -465,6 +465,7 @@ static const struct dm_spi_ops rpc_spi_ops = { static const struct udevice_id rpc_spi_ids[] = { { .compatible = "renesas,r7s72100-rpc-if" }, { .compatible = "renesas,rcar-gen3-rpc-if" }, + { .compatible = "renesas,rcar-gen4-rpc-if" }, { } }; From 3faeb78378ea32922fbd00e9ddf675ce0aa526a3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 31 Aug 2024 22:33:37 +0200 Subject: [PATCH 7/7] ARM: dts: renesas: Minimize R8A779G0 V4H RPC SPI DT node The RPC SPI DT node is now part of mainline Linux DT, remove the duplicate content from U-Boot DT extras. The SPI flash DT node name has been changed from "spi-flash@0" to "flash@0", reflect this change in this patch. Retain "bank-width" and "num-cs" DT properties which are used by U-Boot. Retain "spi-rx-bus-width" and "spi-tx-bus-width" DT properties to indicate the bus should always be operated in 1-1-1 mode as the U-Boot RPC SPI driver does not support higher bus width modes yet. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779g0-u-boot.dtsi | 1 - arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi | 22 +------------------- 2 files changed, 1 insertion(+), 22 deletions(-) diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index cc8becac996..f60eba531e4 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -8,7 +8,6 @@ #include "r8a779x-u-boot.dtsi" &rpc { - reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; bank-width = <2>; num-cs = <1>; }; diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index a102639010d..c3704d789e8 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -13,29 +13,9 @@ }; }; -&pfc { - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; -}; - &rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <40000000>; - status = "disabled"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "jedec,spi-nor"; - reg = <0>; + flash@0 { spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; - spi-max-frequency = <40000000>; }; };