diff --git a/MAINTAINERS b/MAINTAINERS index b61cbb2f736..a55742a0baf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -133,15 +133,22 @@ F: drivers/mmc/snps_dw_mmc.c APPLE M1 SOC SUPPORT M: Mark Kettenis +R: Janne Grunau S: Maintained F: arch/arm/include/asm/arch-apple/ F: arch/arm/mach-apple/ +F: board/apple/ F: configs/apple_m1_defconfig +F: doc/board/apple/ +F: drivers/input/apple_spi_kbd.c F: drivers/iommu/apple_dart.c +F: drivers/mailbox/apple-mbox.c F: drivers/nvme/nvme_apple.c F: drivers/pci/pcie_apple.c F: drivers/phy/phy-apple-atc.c F: drivers/pinctrl/pinctrl-apple.c +F: drivers/power/domain/apple-pmgr.c +F: drivers/spi/apple_spi.c F: drivers/watchdog/apple_wdt.c F: include/configs/apple.h @@ -1096,7 +1103,7 @@ EFI CLIENT M: Simon Glass M: Heinrich Schuchardt S: Maintained -W: https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html +W: https://docs.u-boot-project.org/en/latest/develop/uefi/u-boot_on_efi.html F: board/efi/efi-x86_app F: configs/efi-x86_app* F: doc/develop/uefi/u-boot_on_efi.rst @@ -1486,6 +1493,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-nios.git F: arch/nios2/ NVMe +M: Neil Armstrong M: Bin Meng S: Maintained F: drivers/nvme/ diff --git a/Makefile b/Makefile index 552328f9f2c..f07faada3d5 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2026 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -1578,6 +1578,9 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE %.scif: %.srec $(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@ +%.shdr: %.srec + $(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@ + OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec)) @@ -1682,7 +1685,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ build -u -d $(binman_dtb) -O . -m \ --allow-missing --fake-ext-blobs \ $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \ - -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ + -I . -I $(srctree)/board/$(BOARDDIR) -I $(srctree) \ $(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \ $(foreach f,$(BINMAN_INDIRS),-I $(f)) \ -a atf-bl1-path=${BL1} \ diff --git a/README b/README index 6836a917c79..5653f687e82 100644 --- a/README +++ b/README @@ -628,98 +628,6 @@ The following options need to be configured: If you do not have i2c muxes on your board, omit this define. -- Legacy I2C Support: - If you use the software i2c interface (CONFIG_SYS_I2C_SOFT) - then the following macros need to be defined (examples are - from include/configs/lwmon.h): - - I2C_INIT - - (Optional). Any commands necessary to enable the I2C - controller or configure ports. - - eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) - - I2C_ACTIVE - - The code necessary to make the I2C data line active - (driven). If the data line is open collector, this - define can be null. - - eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) - - I2C_TRISTATE - - The code necessary to make the I2C data line tri-stated - (inactive). If the data line is open collector, this - define can be null. - - eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) - - I2C_READ - - Code that returns true if the I2C data line is high, - false if it is low. - - eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) - - I2C_SDA(bit) - - If is true, sets the I2C data line high. If it - is false, it clears it (low). - - eg: #define I2C_SDA(bit) \ - if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA - - I2C_SCL(bit) - - If is true, sets the I2C clock line high. If it - is false, it clears it (low). - - eg: #define I2C_SCL(bit) \ - if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL - - I2C_DELAY - - This delay is invoked four times per clock cycle so this - controls the rate of data transfer. The data rate thus - is 1 / (I2C_DELAY * 4). Often defined to be something - like: - - #define I2C_DELAY udelay(2) - - CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA - - If your arch supports the generic GPIO framework (asm/gpio.h), - then you may alternatively define the two GPIOs that are to be - used as SCL / SDA. Any of the previous I2C_xxx macros will - have GPIO-based defaults assigned to them as appropriate. - - You should define these to the GPIO value as given directly to - the generic GPIO functions. - - CFG_SYS_I2C_NOPROBES - - This option specifies a list of I2C devices that will be skipped - when the 'i2c probe' command is issued. - - e.g. - #define CFG_SYS_I2C_NOPROBES {0x50,0x68} - - will skip addresses 0x50 and 0x68 on a board with one I2C bus - - CONFIG_SOFT_I2C_READ_REPEATED_START - - defining this will force the i2c_read() function in - the soft_i2c driver to perform an I2C repeated start - between writing the address pointer and reading the - data. If this define is omitted the default behaviour - of doing a stop-start sequence will be used. Most I2C - devices can use either method, but some require one or - the other. - - SPI Support: CONFIG_SPI Enables SPI driver (so far only tested with @@ -2373,5 +2281,5 @@ Contributing The U-Boot projects depends on contributions from the user community. If you want to participate, please, have a look at the 'General' -section of https://docs.u-boot.org/en/latest/develop/index.html +section of https://docs.u-boot-project.org/en/latest/develop/index.html where we describe coding standards and the patch submission process. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f624675eadf..514bf2000b4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1082,6 +1082,7 @@ config ARCH_APPLE imply CMD_GPT imply BOOTSTD_FULL imply OF_HAS_PRIOR_STAGE + imply OF_UPSTREAM config ARCH_OWL bool "Actions Semi OWL SoCs" diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 39479df7b21..7c0e3f6d055 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -810,8 +810,10 @@ __weak void mmu_setup(void) el = current_el(); set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL), MEMORY_ATTRIBUTES); +} - /* enable the mmu */ +void mmu_enable(void) +{ set_sctlr(get_sctlr() | CR_M); } @@ -881,6 +883,7 @@ void dcache_enable(void) if (!mmu_status()) { __asm_invalidate_tlb_all(); mmu_setup(); + mmu_enable(); } /* Set up page tables only once (it is done also by mmu_setup()) */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 7f0cb28f52d..a047494b1fd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1143,7 +1143,7 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif -#ifdef CONFIG_SYS_FSL_HAS_RGMII +#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET) /* some dpmacs in armv8a based freescale layerscape SOCs can be * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via * EC*_PMUX(rgmii) bits in RCW. @@ -1158,6 +1158,10 @@ int arch_early_init_r(void) * function of SOC, the dpmac will be enabled as RGMII even if it was * also enabled before as SGMII. If ECx_PMUX is not configured for * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init(). + * + * fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET + * (drivers/net/ldpaa_eth/); gate the call the same way so builds + * without MC-ENET still link. */ fsl_rgmii_init(); #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0f4f6c986f0..77c9ab9e50c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -32,13 +32,6 @@ dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb -dtb-$(CONFIG_ARCH_APPLE) += \ - t8103-j274.dtb \ - t8103-j293.dtb \ - t8103-j313.dtb \ - t8103-j456.dtb \ - t8103-j457.dtb - dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-lcdk.dtb \ da850-lego-ev3.dtb @@ -902,11 +895,7 @@ dtb-$(CONFIG_RZA1) += \ r7s72100-gr-peach.dtb dtb-$(CONFIG_RCAR_GEN5) += \ - r8a78000-ironhide.dtb - -ifdef CONFIG_RCAR_GEN5 -DTC_FLAGS += -R 4 -p 0x1000 -endif + r8a78000-ironhide-cm33.dtb dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb diff --git a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi index 63b37e52292..c3a66ac8dae 100644 --- a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi @@ -12,6 +12,11 @@ #if defined(CONFIG_CPU_V7R) &binman { + tiboot3_am69_gp { + insert-template = <&tiboot3_j784s4_gp>; + filename = "tiboot3-am69-gp-aquila.bin"; + }; + tiboot3-am69-hs { insert-template = <&tiboot3_j784s4_hs>; filename = "tiboot3-am69-hs-aquila.bin"; @@ -28,6 +33,10 @@ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin"; }; +&ti_fs_gp { + filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin"; +}; + &sysfw_inner_cert { filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin"; }; @@ -78,6 +87,72 @@ u-boot-unsigned { insert-template = <&u_boot_unsigned>; }; + + firmware-aquila-am69-gp.bin { + filename = "firmware-aquila-am69-gp.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-gp-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin_unsigned"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img_unsigned"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-aquila-am69-hs.bin { + filename = "firmware-aquila-am69-hs.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-hs-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-aquila-am69-hs-fs.bin { + filename = "firmware-aquila-am69-hs-fs.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-hs-fs-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; }; #endif diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi new file mode 100644 index 00000000000..2d4cdbac62a --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "r8a78000-ironhide-u-boot.dtsi" + +/ { + model = "Renesas Ironhide board CM33 based on r8a78000"; + compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33"; + + aliases { + serial1 = &hscif1; + }; + + chosen { + stdout-path = "serial1:1843200n8"; + }; + + /delete-node/ firmware; + /delete-node/ memory@40000000; + /delete-node/ memory@60600000; + /delete-node/ memory@1080000000; + /delete-node/ memory@1200000000; + /delete-node/ memory@1400000000; + /delete-node/ memory@1600000000; + /delete-node/ memory@1800000000; + /delete-node/ memory@1a00000000; + /delete-node/ memory@1c00000000; + /delete-node/ memory@1e00000000; + /delete-node/ reserved-memory; + + memory@b8400000 { + device_type = "memory"; + reg = <0x0 0xb8400000 0x0 0x00200000>; + }; + + dummy_clk_rclk: dummy-clk-rclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16660000>; + }; + + ctl: syscon@5fffd000 { + compatible = "renesas,r8a78000-ctl", + "renesas,rcar-gen5-ctl", + "syscon"; + reg = <0 0x5fffd000 0 0xc4>; + }; + + watchdog@5fffd800 { + compatible = "renesas,r8a78000-wwdt", + "renesas,rcar-gen5-wwdt"; + clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>; + clock-names = "cnt", "bus"; + reg = <0 0x5fffd800 0 0x10>; + syscon = <&ctl>; + }; + + scp@c1340000 { + compatible = "renesas,r8a78000-rproc"; + reg = <0 0xc1340000 0 0x80000>; + }; +}; + +&cpg { + /delete-property/ firmware; +}; + +ð_pcs { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&mdlc_hscn { + /delete-property/ firmware; +}; + +&mdlc_pere { + /delete-property/ firmware; +}; + +&mmc0 { + status = "disabled"; +}; + +&mp_phy { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&pfc { + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; +}; + +&rswitch3 { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&soc { + dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>; +}; + +&ufs0 { + /delete-property/ power-domains; +}; + +&ufs1 { + /delete-property/ power-domains; + status = "disabled"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide-cm33.dts b/arch/arm/dts/r8a78000-ironhide-cm33.dts new file mode 100644 index 00000000000..79ad844165c --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts" diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi index 9c72f3e55f4..299716f96a4 100644 --- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -5,4 +5,190 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include #include "r8a78000-u-boot.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &mmc0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpg { + firmware = <&scmi>; +}; + +ð_pcs { + phys = <&mp_phy 2 1>; + status = "okay"; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&mdlc_hscn { + firmware = <&scmi>; +}; + +&mdlc_pere { + firmware = <&scmi>; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-1 = <&mmc0_pins>; + pinctrl-names = "default", "state_uhs"; + + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + + status = "okay"; +}; + +&mp_phy { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + eth25g2_pins: eth25g2 { + groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; + function = "eth25g2"; + drive-strength = <24>; + }; + + ethes0_pins: ethes0 { + groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; + function = "ethes0"; + drive-strength = <24>; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; + function = "mmc0"; + drive-strength = <24>; + }; + + rsw3_pins: rsw3 { + groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; + function = "rsw3"; + drive-strength = <24>; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rswitch3 { + pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * NOTE: Only port@4 is configured for R-Car X5H board. + * Other ports (0-3, 5-12) are currently unused or not + * connected. + */ + port@4 { + reg = <4>; + renesas,connect_to_xpcs; + phy-handle = <&dp83869_phy>; + phy-mode = "sgmii"; + phys = <ð_pcs 5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83869_phy: ethernet-phy@2 { + reg = <2>; + ti,sgmii-interface; + ti,max-output-impedance; + ti,refclk-output-enable; + ti,clk-output-sel = ; + }; + }; + }; + }; +}; + +&ufs0 { + status = "okay"; +}; + +&ufs1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide.dts b/arch/arm/dts/r8a78000-ironhide.dts deleted file mode 100644 index 601f2740b54..00000000000 --- a/arch/arm/dts/r8a78000-ironhide.dts +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Ironhide board - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a78000.dtsi" -#include - -/ { - model = "Renesas Ironhide board based on r8a78000"; - compatible = "renesas,ironhide", "renesas,r8a78000"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - mmc0 = &mmc0; - serial0 = &hscif0; - }; - - chosen { - stdout-path = "serial0:1843200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x80000000>; - }; - - memory@1080000000 { - device_type = "memory"; - reg = <0x10 0x80000000 0x0 0x80000000>; - }; - - memory@1200000000 { - device_type = "memory"; - reg = <0x12 0x00000000 0x1 0x00000000>; - }; - - memory@1400000000 { - device_type = "memory"; - reg = <0x14 0x00000000 0x1 0x00000000>; - }; - - memory@1600000000 { - device_type = "memory"; - reg = <0x16 0x00000000 0x1 0x00000000>; - }; - - memory@1800000000 { - device_type = "memory"; - reg = <0x18 0x00000000 0x1 0x00000000>; - }; - - memory@1a00000000 { - device_type = "memory"; - reg = <0x1a 0x00000000 0x1 0x00000000>; - }; - - memory@1c00000000 { - device_type = "memory"; - reg = <0x1c 0x00000000 0x1 0x00000000>; - }; - - memory@1e00000000 { - device_type = "memory"; - reg = <0x1e 0x00000000 0x1 0x00000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&extal_clk { - clock-frequency = <16666600>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; -}; - -ð_pcs { - phys = <&mp_phy 2 1>; - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-1 = <&mmc0_pins>; - pinctrl-names = "default", "state_uhs"; - - bus-width = <8>; - full-pwr-cycle-in-suspend; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - no-sd; - no-sdio; - non-removable; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - - status = "okay"; -}; - -&ufs0 { - status = "okay"; -}; - -&ufs1 { - status = "okay"; -}; - -&mp_phy { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - eth25g2_pins: eth25g2 { - groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; - function = "eth25g2"; - drive-strength = <24>; - }; - - ethes0_pins: ethes0 { - groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; - function = "ethes0"; - drive-strength = <24>; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; - function = "mmc0"; - drive-strength = <24>; - }; - - rsw3_pins: rsw3 { - groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; - function = "rsw3"; - drive-strength = <24>; - }; - - scif_clk_pins: scif-clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rswitch3 { - pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; - pinctrl-names = "default"; - status = "okay"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * NOTE: Only port@4 is configured for R-Car X5H board. - * Other ports (0-3, 5-12) are currently unused or not - * connected. - */ - port@4 { - reg = <4>; - renesas,connect_to_xpcs; - phy-handle = <&dp83869_phy>; - phy-mode = "sgmii"; - phys = <ð_pcs 5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - dp83869_phy: ethernet-phy@2 { - reg = <2>; - ti,sgmii-interface; - ti,max-output-impedance; - ti,refclk-output-enable; - ti,clk-output-sel = ; - }; - }; - }; - }; -}; - -&scif_clk { - clock-frequency = <26000000>; -}; diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi index 1bc73252430..df21a9e03a2 100644 --- a/arch/arm/dts/r8a78000-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -5,9 +5,41 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include +#include +#include + / { - soc { - bootph-all; + firmware { + scmi: scmi { + compatible = "arm,scmi"; + arm,poll-transport; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0>, <&mailbox 1>; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; + #address-cells = <1>; + #size-cells = <0>; + + protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; }; /* Placeholder clock until the clock provider is in place */ @@ -32,16 +64,12 @@ clk_stub_mmc: clk-stub-mmc { compatible = "renesas,compound-clock"; #clock-cells = <0>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>, - <&scmi_clk 1691>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_SDHI0>, + <&cpg SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN>; clock-names = "mdlc", "per"; }; }; -&cpg { - bootph-all; -}; - &extal_clk { bootph-all; }; @@ -50,90 +78,311 @@ bootph-all; }; -&gpio0 { - clocks = <&clk_stub_gpio>; -}; - -&gpio1 { - clocks = <&clk_stub_gpio>; -}; - -&gpio2 { - clocks = <&clk_stub_gpio>; -}; - -&gpio3 { - clocks = <&clk_stub_gpio>; -}; - -&gpio4 { - clocks = <&clk_stub_gpio>; -}; - -&gpio5 { - clocks = <&clk_stub_gpio>; -}; - -&gpio6 { - clocks = <&clk_stub_gpio>; -}; - -&gpio7 { - clocks = <&clk_stub_gpio>; -}; - -&gpio8 { - clocks = <&clk_stub_gpio>; -}; - -&gpio9 { - clocks = <&clk_stub_gpio>; -}; - -&gpio10 { - clocks = <&clk_stub_gpio>; -}; - -&i2c0 { - clocks = <&clk_stub_i2c0>; -}; - -&i2c1 { - clocks = <&clk_stub_i2c1>; -}; - -&i2c2 { - clocks = <&clk_stub_i2c1>; -}; - -&i2c3 { - clocks = <&clk_stub_i2c1>; -}; - -&i2c4 { - clocks = <&clk_stub_i2c1>; -}; - -&i2c5 { - clocks = <&clk_stub_i2c1>; -}; - -&i2c6 { - clocks = <&clk_stub_i2c1>; -}; - -&i2c7 { - clocks = <&clk_stub_i2c1>; -}; - -&i2c8 { - clocks = <&clk_stub_i2c1>; -}; - -&mmc0 { - clocks = <&clk_stub_mmc>; -}; - &prr { bootph-all; }; + +&soc { + bootph-all; + + mailbox: mfis_mbox@18842000 { + compatible = "renesas,mfis-mbox"; + #mbox-cells = <1>; + reg = <0 0x18842004 0 0x8>; + interrupts = ; + }; + + pfc: pinctrl@c0400000 { + compatible = "renesas,pfc-r8a78000"; + reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, + <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, + <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, + <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, + <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, + <0 0xc9b00800 0 0x104>; + }; + + mmc0: mmc@c0880000 { + compatible = "renesas,rcar-gen5-sdhi"; + reg = <0 0xc0880000 0 0x2000>; + clock-names = "core"; + max-frequency = <200000000>; + clocks = <&clk_stub_mmc>; + status = "disabled"; + }; + + mdlc_pere: system-controller@c08f0000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc08f0000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; + + ufs0: ufs@c0a80000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS0>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS0>; + resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS0>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; + + ufs1: ufs@c0a90000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS1>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS1>; + resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS1>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; + + scp: sram@c1000000 { + compatible = "arm,rcar-sram-ns", "mmio-sram"; + reg = <0x0 0xc1000000 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1000000 0x80000>; + + cpu_scp_lpri0: scp-shmem@60000 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61200 0x0100>; + }; + + cpu_scp_hpri0: scp-shmem@60300 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61300 0x100>; + }; + }; + + cpg: clock-controller@c1320000 { + compatible = "renesas,r8a78000-cpg"; + reg = <0 0xc1320000 0 0x10000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <1>; + bootph-all; + }; + + i2c0: i2c@c11d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc11d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c0>; + status = "disabled"; + }; + + i2c1: i2c@c06c0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c1>; + status = "disabled"; + }; + + gpio0: gpio@c1080110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 28>; + clocks = <&clk_stub_gpio>; + }; + + gpio1: gpio@c1080910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 22>; + clocks = <&clk_stub_gpio>; + }; + + gpio2: gpio@c1081110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1081110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 29>; + clocks = <&clk_stub_gpio>; + }; + + gpio3: gpio@c0800110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + clocks = <&clk_stub_gpio>; + }; + + gpio4: gpio@c0800910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 16>; + clocks = <&clk_stub_gpio>; + }; + + gpio5: gpio@c0400110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 23>; + clocks = <&clk_stub_gpio>; + }; + + gpio6: gpio@c0400910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 31>; + clocks = <&clk_stub_gpio>; + }; + + gpio7: gpio@c0401110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 31>; + clocks = <&clk_stub_gpio>; + }; + + gpio8: gpio@c0401910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 32>; + gpio-reserved-ranges = <16 10>; + clocks = <&clk_stub_gpio>; + }; + + gpio9: gpio@c9b00110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + clocks = <&clk_stub_gpio>; + }; + + gpio10: gpio@c9b00910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 14>; + clocks = <&clk_stub_gpio>; + }; + + mp_phy: mp_phy@c9a00000 { + compatible = "renesas,r8a78000-multi-protocol-phy"; + reg = <0 0xc9a00000 0 0x100000>; + #phy-cells = <2>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_MPPHY01>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY11>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY21>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY31>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY02>; + clock-names = "mpphy01", "mpphy11", "mpphy21", + "mpphy31", "mpphy02"; + power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP0>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP1>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP2>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP3>; + resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY01>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY11>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY21>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY31>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY02>; + status = "disabled"; + }; + + rswitch3: ethernet@c9bc0000 { + compatible = "renesas,r8a78000-ether-switch3", + "renesas,etherswitch"; + reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; + reg-names = "base", "secure_base"; + power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_RSW>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_RSW3>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSN>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3AES>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3MFWD>; + clock-names = "rsw3", "rsw3tsn", "rsw3aes", + "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", + "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", + "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; + status = "disabled"; + }; + + eth_pcs: phy@c9c50000 { + compatible = "renesas,r8a78000-ether-pcs"; + reg = <0 0xc9c50000 0 0x4000>; + #phy-cells = <1>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_XPCS0>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS1>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS2>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS3>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS4>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS5>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS6>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS7>; + clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS0>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS1>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS2>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS3>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS4>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS5>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS6>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS7>; + reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + status = "disabled"; + }; + + mdlc_hscn: system-controller@c9c90000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc9c90000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; +}; diff --git a/arch/arm/dts/r8a78000.dtsi b/arch/arm/dts/r8a78000.dtsi deleted file mode 100644 index 89c2881fa94..00000000000 --- a/arch/arm/dts/r8a78000.dtsi +++ /dev/null @@ -1,1164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car X5H (R8A78000) SoC - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a78000"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a720_0>; - }; - core1 { - cpu = <&a720_1>; - }; - core2 { - cpu = <&a720_2>; - }; - core3 { - cpu = <&a720_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a720_4>; - }; - core1 { - cpu = <&a720_5>; - }; - core2 { - cpu = <&a720_6>; - }; - core3 { - cpu = <&a720_7>; - }; - }; - - cluster2 { - core0 { - cpu = <&a720_8>; - }; - core1 { - cpu = <&a720_9>; - }; - core2 { - cpu = <&a720_10>; - }; - core3 { - cpu = <&a720_11>; - }; - }; - - cluster3 { - core0 { - cpu = <&a720_12>; - }; - core1 { - cpu = <&a720_13>; - }; - core2 { - cpu = <&a720_14>; - }; - core3 { - cpu = <&a720_15>; - }; - }; - - cluster4 { - core0 { - cpu = <&a720_16>; - }; - core1 { - cpu = <&a720_17>; - }; - core2 { - cpu = <&a720_18>; - }; - core3 { - cpu = <&a720_19>; - }; - }; - - cluster5 { - core0 { - cpu = <&a720_20>; - }; - core1 { - cpu = <&a720_21>; - }; - core2 { - cpu = <&a720_22>; - }; - core3 { - cpu = <&a720_23>; - }; - }; - - cluster6 { - core0 { - cpu = <&a720_24>; - }; - core1 { - cpu = <&a720_25>; - }; - core2 { - cpu = <&a720_26>; - }; - core3 { - cpu = <&a720_27>; - }; - }; - - cluster7 { - core0 { - cpu = <&a720_28>; - }; - core1 { - cpu = <&a720_29>; - }; - core2 { - cpu = <&a720_30>; - }; - core3 { - cpu = <&a720_31>; - }; - }; - }; - - a720_0: cpu@0 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x0>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_0>; - }; - - a720_1: cpu@100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_1>; - }; - - a720_2: cpu@200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_2>; - }; - - a720_3: cpu@300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_3>; - }; - - a720_4: cpu@10000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_4>; - }; - - a720_5: cpu@10100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_5>; - }; - - a720_6: cpu@10200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_6>; - }; - - a720_7: cpu@10300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_7>; - }; - - a720_8: cpu@20000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_8>; - }; - - a720_9: cpu@20100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_9>; - }; - - a720_10: cpu@20200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_10>; - }; - - a720_11: cpu@20300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_11>; - }; - - a720_12: cpu@30000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_12>; - }; - - a720_13: cpu@30100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_13>; - }; - - a720_14: cpu@30200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_14>; - }; - - a720_15: cpu@30300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_15>; - }; - - a720_16: cpu@40000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_16>; - }; - - a720_17: cpu@40100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_17>; - }; - - a720_18: cpu@40200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_18>; - }; - - a720_19: cpu@40300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_19>; - }; - - a720_20: cpu@50000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_20>; - }; - - a720_21: cpu@50100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_21>; - }; - - a720_22: cpu@50200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_22>; - }; - - a720_23: cpu@50300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_23>; - }; - - a720_24: cpu@60000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_24>; - }; - - a720_25: cpu@60100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_25>; - }; - - a720_26: cpu@60200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_26>; - }; - - a720_27: cpu@60300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_27>; - }; - - a720_28: cpu@70000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_28>; - }; - - a720_29: cpu@70100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_29>; - }; - - a720_30: cpu@70200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_30>; - }; - - a720_31: cpu@70300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_31>; - }; - - L2_CA720_0: cache-controller-200 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_1: cache-controller-201 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_2: cache-controller-202 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_3: cache-controller-203 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_4: cache-controller-204 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_5: cache-controller-205 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_6: cache-controller-206 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_7: cache-controller-207 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_8: cache-controller-208 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_9: cache-controller-209 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_10: cache-controller-210 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_11: cache-controller-211 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_12: cache-controller-212 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_13: cache-controller-213 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_14: cache-controller-214 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_15: cache-controller-215 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_16: cache-controller-216 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_17: cache-controller-217 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_18: cache-controller-218 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_19: cache-controller-219 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_20: cache-controller-220 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_21: cache-controller-221 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_22: cache-controller-222 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_23: cache-controller-223 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_24: cache-controller-224 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_25: cache-controller-225 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_26: cache-controller-226 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_27: cache-controller-227 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_28: cache-controller-228 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_29: cache-controller-229 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_30: cache-controller-230 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_31: cache-controller-231 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L3_CA720_0: cache-controller-30 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_1: cache-controller-31 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_2: cache-controller-32 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_3: cache-controller-33 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_4: cache-controller-34 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_5: cache-controller-35 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_6: cache-controller-36 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_7: cache-controller-37 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - }; - - /* - * In the early phase, there is no clock control support, - * so assume that the clocks are enabled by default. - * Therefore, dummy clocks are used. - */ - dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <66666000>; - }; - - dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <266660000>; - }; - - extal_clk: extal-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - extalr_clk: extalr-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - firmware { - scmi { - compatible = "arm,scmi"; - arm,poll-transport; - mbox-names = "tx", "rx"; - mboxes = <&mailbox 0>, <&mailbox 1>; - shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; /* optional */ - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mailbox: mfis_mbox@18842000 { - compatible = "renesas,mfis-mbox"; - #mbox-cells = <1>; - reg = <0 0x18842004 0 0x8>; - interrupts = ; - }; - - prr: chipid@189e0044 { - compatible = "renesas,prr"; - reg = <0 0x189e0044 0 4>; - }; - - /* Application Processors manage View-1 of a GIC-720AE */ - gic: interrupt-controller@39000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x39000000 0 0x10000>, - <0 0x39080000 0 0x800000>; - interrupts = ; - }; - - pfc: pinctrl@c0400000 { - compatible = "renesas,pfc-r8a78000"; - reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, - <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, - <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, - <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, - <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, - <0 0xc9b00800 0 0x104>; - }; - - scif0: serial@c0700000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0700000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif1: serial@c0704000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0704000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif3: serial@c0708000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0708000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif4: serial@c070c000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc070c000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - mmc0: mmc@c0880000 { - compatible = "renesas,rcar-gen5-sdhi"; - reg = <0 0xc0880000 0 0x2000>; - clock-names = "core"; - max-frequency = <200000000>; - status = "disabled"; - }; - - ufs0: ufs@c0a80000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = ; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - ufs1: ufs@c0a90000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = ; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - scp: sram@c1000000 { - compatible = "arm,rcar-sram-ns", "mmio-sram"; - reg = <0x0 0xc1000000 0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc1000000 0x80000>; - - cpu_scp_lpri0: scp-shmem@60000 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61200 0x0100>; - }; - - cpu_scp_hpri0: scp-shmem@60300 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61300 0x100>; - }; - }; - - cpg: clock-controller@c64f0000 { - compatible = "renesas,r8a78000-cpg-mssr"; - reg = <0 0xc64f0000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - hscif0: serial@c0710000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0710000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif1: serial@c0714000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0714000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif2: serial@c0718000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0718000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif3: serial@c071c000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc071c000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - i2c0: i2c@c11d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc11d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@c06c0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@c06c8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@c06d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@c06d8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@c06e0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@c06e8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@c06f0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@c06f8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpio0: gpio@c1080110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 28>; - }; - - gpio1: gpio@c1080910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 22>; - }; - - gpio2: gpio@c1081110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1081110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 29>; - }; - - gpio3: gpio@c0800110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - }; - - gpio4: gpio@c0800910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 16>; - }; - - gpio5: gpio@c0400110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 23>; - }; - - gpio6: gpio@c0400910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 31>; - }; - - gpio7: gpio@c0401110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 31>; - }; - - gpio8: gpio@c0401910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 32>; - gpio-reserved-ranges = <16 10>; - }; - - gpio9: gpio@c9b00110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - }; - - gpio10: gpio@c9b00910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 14>; - }; - - mp_phy: mp_phy@c9a00000 { - compatible = "renesas,r8a78000-multi-protocol-phy"; - reg = <0 0xc9a00000 0 0x100000>; - #phy-cells = <2>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; - clock-names = "mpphy01", "mpphy11", "mpphy21", - "mpphy31", "mpphy02"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; - status = "disabled"; - }; - - rswitch3: ethernet@c9bc0000 { - compatible = "renesas,r8a78000-ether-switch3", - "renesas,etherswitch"; - reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; - reg-names = "base", "secure_base"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; - clock-names = "rsw3", "rsw3tsn", "rsw3aes", - "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", - "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", - "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; - status = "disabled"; - }; - - eth_pcs: phy@c9c50000 { - compatible = "renesas,r8a78000-ether-pcs"; - reg = <0 0xc9c50000 0 0x4000>; - #phy-cells = <1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; - clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; - reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - , - ; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; -}; diff --git a/arch/arm/dts/t8103-j274-u-boot.dtsi b/arch/arm/dts/t8103-j274-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j274-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j274.dts b/arch/arm/dts/t8103-j274.dts deleted file mode 100644 index 9bc592bcdbf..00000000000 --- a/arch/arm/dts/t8103-j274.dts +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple Mac mini (M1, 2020) - * - * target-type: J274 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; - model = "Apple Mac mini (M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,atlantisb"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-left"; -}; - -&typec1 { - label = "USB-C Back-right"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port01 { - bus-range = <2 2>; -}; - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -&i2c1 { - clock-frequency = <50000>; - - speaker_amp: codec@31 { - compatible = "ti,tas5770l", "ti,tas2770"; - reg = <0x31>; - reset-gpios = <&pinctrl_ap 181 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; -}; - -&i2c2 { - status = "okay"; - - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Mac mini integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "left_j"; - tdm-slot-width = <32>; - mclk-fs = <64>; - - link0_cpu: cpu { - sound-dai = <&mca 0>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&speaker_amp>; - }; - }; - - simple-audio-card,dai-link@1 { - bitclock-inversion; - frame-inversion; - reg = <1>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link1_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link1_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j293-u-boot.dtsi b/arch/arm/dts/t8103-j293-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j293-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j293.dts b/arch/arm/dts/t8103-j293.dts deleted file mode 100644 index de1a21d97cd..00000000000 --- a/arch/arm/dts/t8103-j293.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple MacBook Pro (13-inch, M1, 2020) - * - * target-type: J293 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; - model = "Apple MacBook Pro (13-inch, M1, 2020)"; -}; - -&wifi0 { - brcm,board-type = "apple,honshu"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Left-back"; -}; - -&typec1 { - label = "USB-C Left-front"; -}; - -&spi3 { - status = "okay"; - - hid-transport@0 { - compatible = "apple,spi-hid-transport"; - reg = <0>; - spi-max-frequency = <8000000>; - /* - * cs-setup and cs-hold delays are derived from Apple's ADT - * Mac OS driver meta data secify 45 us for 'cs to clock' and - * 'clock to cs' delays. - */ - spi-cs-setup-delay-ns = <20000>; - spi-cs-hold-delay-ns = <20000>; - spi-cs-inactive-delay-ns = <250000>; - spien-gpios = <&pinctrl_ap 195 0>; - interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; - -&i2c2 { - status = "okay"; - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "MacBook integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j313-u-boot.dtsi b/arch/arm/dts/t8103-j313-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j313-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j313.dts b/arch/arm/dts/t8103-j313.dts deleted file mode 100644 index 5efe8d7a63b..00000000000 --- a/arch/arm/dts/t8103-j313.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple MacBook Air (M1, 2020) - * - * target-type: J313 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; - model = "Apple MacBook Air (M1, 2020)"; -}; - -&wifi0 { - brcm,board-type = "apple,shikoku"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Left-back"; -}; - -&typec1 { - label = "USB-C Left-front"; -}; - -&spi3 { - status = "okay"; - - hid-transport@0 { - compatible = "apple,spi-hid-transport"; - reg = <0>; - spi-max-frequency = <8000000>; - /* - * cs-setup and cs-hold delays are derived from Apple's ADT - * Mac OS driver meta data secify 45 us for 'cs to clock' and - * 'clock to cs' delays. - */ - spi-cs-setup-delay-ns = <20000>; - spi-cs-hold-delay-ns = <20000>; - spi-cs-inactive-delay-ns = <250000>; - spien-gpios = <&pinctrl_ap 195 0>; - interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; - -&i2c3 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "MacBook integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j456-u-boot.dtsi b/arch/arm/dts/t8103-j456-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j456-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j456.dts b/arch/arm/dts/t8103-j456.dts deleted file mode 100644 index 8624168bdb7..00000000000 --- a/arch/arm/dts/t8103-j456.dts +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple iMac (24-inch, 4x USB-C, M1, 2020) - * - * target-type: J456 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,capri"; -}; - -&i2c0 { - hpm2: usb-pd@3b { - compatible = "apple,cd321x"; - reg = <0x3b>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - }; - - hpm3: usb-pd@3c { - compatible = "apple,cd321x"; - reg = <0x3c>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - }; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-right"; -}; - -&typec1 { - label = "USB-C Back-right-middle"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port01 { - bus-range = <2 2>; -}; - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -&i2c1 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "iMac integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j457-u-boot.dtsi b/arch/arm/dts/t8103-j457-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j457-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j457.dts b/arch/arm/dts/t8103-j457.dts deleted file mode 100644 index f3eec8d4729..00000000000 --- a/arch/arm/dts/t8103-j457.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple iMac (24-inch, 2x USB-C, M1, 2020) - * - * target-type: J457 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,santorini"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-right"; -}; - -&typec1 { - label = "USB-C Back-left"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -/* - * Remove unused PCIe port and disable the associated DART. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -/delete-node/ &port01; - -&i2c1 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "iMac integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-jxxx.dtsi b/arch/arm/dts/t8103-jxxx.dtsi deleted file mode 100644 index b4bd8c4238a..00000000000 --- a/arch/arm/dts/t8103-jxxx.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021) - * - * This file contains parts common to all Apple M1 devices using the t8103. - * - * target-type: J274, J293, J313, J456, J457 - * - * Copyright The Asahi Linux Contributors - */ - -#include - -/ { - aliases { - serial0 = &serial0; - serial2 = &serial2; - wifi0 = &wifi0; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "serial0"; - - framebuffer0: framebuffer@0 { - compatible = "apple,simple-framebuffer", "simple-framebuffer"; - reg = <0 0 0 0>; /* To be filled by loader */ - /* Format properties will be added by loader */ - status = "disabled"; - }; - }; - - memory@800000000 { - device_type = "memory"; - reg = <0x8 0 0x2 0>; /* To be filled by loader */ - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - hpm0: usb-pd@38 { - compatible = "apple,cd321x"; - reg = <0x38>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - typec0: connector { - compatible = "usb-c-connector"; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - typec0_con_hs: endpoint { - remote-endpoint = <&typec0_usb_hs>; - }; - }; - }; - }; - }; - - hpm1: usb-pd@3f { - compatible = "apple,cd321x"; - reg = <0x3f>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - typec1: connector { - compatible = "usb-c-connector"; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - typec1_con_hs: endpoint { - remote-endpoint = <&typec1_usb_hs>; - }; - }; - }; - }; - }; -}; - -/* USB controllers */ -&dwc3_0 { - port { - typec0_usb_hs: endpoint { - remote-endpoint = <&typec0_con_hs>; - }; - }; -}; - -&dwc3_1 { - port { - typec1_usb_hs: endpoint { - remote-endpoint = <&typec1_con_hs>; - }; - }; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ -&port00 { - bus-range = <1 1>; - pwren-gpios = <&smc 13 0>; - wifi0: network@0,0 { - compatible = "pci14e4,4425"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 00 00 00 00 00]; - apple,antenna-sku = "XX"; - }; -}; - -&spmi { - status = "okay"; - - pmu@f { - compatible = "apple,sera-pmu"; - reg = <0xf SPMI_USID>; - }; -}; diff --git a/arch/arm/dts/t8103-pmgr.dtsi b/arch/arm/dts/t8103-pmgr.dtsi deleted file mode 100644 index 82ea4aa322e..00000000000 --- a/arch/arm/dts/t8103-pmgr.dtsi +++ /dev/null @@ -1,1138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * PMGR Power domains for the Apple T8103 "M1" SoC - * - * Copyright The Asahi Linux Contributors - */ - - -&pmgr { - ps_sbr: power-controller@100 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x100 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sbr"; - apple,always-on; /* Core device */ - }; - - ps_aic: power-controller@108 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x108 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aic"; - apple,always-on; /* Core device */ - }; - - ps_dwi: power-controller@110 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x110 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dwi"; - apple,always-on; /* Core device */ - }; - - ps_soc_spmi0: power-controller@118 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x118 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi0"; - }; - - ps_soc_spmi1: power-controller@120 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x120 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi1"; - }; - - ps_soc_spmi2: power-controller@128 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x128 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi2"; - }; - - ps_gpio: power-controller@130 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x130 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "gpio"; - }; - - ps_pms_busif: power-controller@138 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x138 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_busif"; - apple,always-on; /* Core device */ - }; - - ps_pms: power-controller@140 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x140 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms"; - apple,always-on; /* Core device */ - }; - - ps_pms_fpwm0: power-controller@148 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x148 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm0"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm1: power-controller@150 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x150 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm1"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm2: power-controller@158 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x158 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm2"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm3: power-controller@160 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x160 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm3"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm4: power-controller@168 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x168 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm4"; - power-domains = <&ps_pms>; - }; - - ps_soc_dpe: power-controller@170 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x170 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_dpe"; - apple,always-on; /* Core device */ - }; - - ps_pmgr_soc_ocla: power-controller@178 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x178 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pmgr_soc_ocla"; - }; - - ps_ispsens0: power-controller@180 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x180 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens0"; - }; - - ps_ispsens1: power-controller@188 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x188 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens1"; - }; - - ps_ispsens2: power-controller@190 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x190 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens2"; - }; - - ps_ispsens3: power-controller@198 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x198 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens3"; - }; - - ps_pcie_ref: power-controller@1a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1a0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pcie_ref"; - }; - - ps_aft0: power-controller@1a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aft0"; - }; - - ps_devc0_ivdmc: power-controller@1b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "devc0_ivdmc"; - }; - - ps_imx: power-controller@1b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "imx"; - apple,always-on; /* Apple fabric, critical block */ - }; - - ps_sio_busif: power-controller@1c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_busif"; - }; - - ps_sio: power-controller@1c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio"; - power-domains = <&ps_sio_busif>; - }; - - ps_sio_cpu: power-controller@1d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_cpu"; - power-domains = <&ps_sio>; - }; - - ps_fpwm0: power-controller@1d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm0"; - }; - - ps_fpwm1: power-controller@1e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm1"; - }; - - ps_fpwm2: power-controller@1e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm2"; - }; - - ps_i2c0: power-controller@1f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c0"; - power-domains = <&ps_sio>; - }; - - ps_i2c1: power-controller@1f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c1"; - power-domains = <&ps_sio>; - }; - - ps_i2c2: power-controller@200 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x200 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c2"; - power-domains = <&ps_sio>; - }; - - ps_i2c3: power-controller@208 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x208 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c3"; - power-domains = <&ps_sio>; - }; - - ps_i2c4: power-controller@210 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x210 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c4"; - power-domains = <&ps_sio>; - }; - - ps_spi_p: power-controller@218 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x218 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi_p"; - power-domains = <&ps_sio>; - }; - - ps_uart_p: power-controller@220 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x220 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart_p"; - power-domains = <&ps_sio>; - }; - - ps_audio_p: power-controller@228 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x228 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "audio_p"; - power-domains = <&ps_sio>; - }; - - ps_sio_adma: power-controller@230 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x230 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_adma"; - power-domains = <&ps_sio>, <&ps_pms>; - }; - - ps_aes: power-controller@238 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x238 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aes"; - power-domains = <&ps_sio>; - }; - - ps_spi0: power-controller@240 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x240 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi0"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi1: power-controller@248 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x248 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi1"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi2: power-controller@250 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x250 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi2"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi3: power-controller@258 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x258 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi3"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_uart_n: power-controller@268 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x268 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart_n"; - power-domains = <&ps_uart_p>; - }; - - ps_uart0: power-controller@270 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x270 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart0"; - power-domains = <&ps_uart_p>; - }; - - ps_uart1: power-controller@278 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x278 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart1"; - power-domains = <&ps_uart_p>; - }; - - ps_uart2: power-controller@280 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x280 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart2"; - power-domains = <&ps_uart_p>; - }; - - ps_uart3: power-controller@288 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x288 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart3"; - power-domains = <&ps_uart_p>; - }; - - ps_uart4: power-controller@290 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x290 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart4"; - power-domains = <&ps_uart_p>; - }; - - ps_uart5: power-controller@298 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x298 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart5"; - power-domains = <&ps_uart_p>; - }; - - ps_uart6: power-controller@2a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2a0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart6"; - power-domains = <&ps_uart_p>; - }; - - ps_uart7: power-controller@2a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart7"; - power-domains = <&ps_uart_p>; - }; - - ps_uart8: power-controller@2b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart8"; - power-domains = <&ps_uart_p>; - }; - - ps_mca0: power-controller@2b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca0"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - }; - - ps_mca1: power-controller@2c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca1"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca2: power-controller@2c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca2"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca3: power-controller@2d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca3"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca4: power-controller@2d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca4"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca5: power-controller@2e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca5"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_dpa0: power-controller@2e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dpa0"; - power-domains = <&ps_audio_p>; - }; - - ps_dpa1: power-controller@2f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dpa1"; - power-domains = <&ps_audio_p>; - }; - - ps_mcc: power-controller@2f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mcc"; - apple,always-on; /* Memory controller */ - }; - - ps_spi4: power-controller@260 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x260 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi4"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_dcs0: power-controller@300 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x300 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs0"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs1: power-controller@310 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x310 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs1"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs2: power-controller@308 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x308 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs2"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs3: power-controller@318 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x318 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs3"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_smx: power-controller@340 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x340 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "smx"; - apple,always-on; /* Apple fabric, critical block */ - }; - - ps_apcie: power-controller@348 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x348 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie"; - power-domains = <&ps_imx>, <&ps_pcie_ref>; - }; - - ps_rmx: power-controller@350 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x350 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "rmx"; - /* Apple Fabric, display/image stuff: this can power down */ - }; - - ps_mmx: power-controller@358 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x358 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mmx"; - /* Apple Fabric, media stuff: this can power down */ - }; - - ps_disp0_fe: power-controller@360 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x360 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "disp0_fe"; - power-domains = <&ps_rmx>; - apple,always-on; /* TODO: figure out if we can enable PM here */ - }; - - ps_dispext_fe: power-controller@368 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x368 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispext_fe"; - power-domains = <&ps_rmx>; - }; - - ps_dispext_cpu0: power-controller@378 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x378 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispext_cpu0"; - power-domains = <&ps_dispext_fe>; - apple,min-state = <4>; - }; - - ps_jpg: power-controller@3c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "jpg"; - power-domains = <&ps_mmx>; - }; - - ps_msr: power-controller@3c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msr"; - power-domains = <&ps_mmx>; - }; - - ps_msr_ase_core: power-controller@3d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msr_ase_core"; - }; - - ps_pmp: power-controller@3d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pmp"; - }; - - ps_pms_sram: power-controller@3e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_sram"; - }; - - ps_apcie_gp: power-controller@3e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie_gp"; - power-domains = <&ps_apcie>; - }; - - ps_ans2: power-controller@3f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ans2"; - /* - * The ADT makes ps_apcie_st depend on ps_ans2 instead, but this - * doesn't make much sense since ANS2 uses APCIE_ST. - */ - power-domains = <&ps_apcie_st>; - }; - - ps_gfx: power-controller@3f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "gfx"; - }; - - ps_dcs4: power-controller@320 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x320 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs4"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs5: power-controller@330 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x330 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs5"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs6: power-controller@328 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x328 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs6"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs7: power-controller@338 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x338 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs7"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dispdfr_fe: power-controller@3a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispdfr_fe"; - power-domains = <&ps_rmx>; - }; - - ps_dispdfr_be: power-controller@3b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispdfr_be"; - power-domains = <&ps_dispdfr_fe>; - }; - - ps_mipi_dsi: power-controller@3b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mipi_dsi"; - power-domains = <&ps_dispdfr_be>; - }; - - ps_isp_sys: power-controller@400 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x400 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "isp_sys"; - power-domains = <&ps_rmx>; - }; - - ps_venc_sys: power-controller@408 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x408 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_sys"; - power-domains = <&ps_mmx>; - }; - - ps_avd_sys: power-controller@410 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x410 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "avd_sys"; - power-domains = <&ps_mmx>; - }; - - ps_apcie_st: power-controller@418 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x418 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie_st"; - power-domains = <&ps_apcie>; - }; - - ps_ane_sys: power-controller@470 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x470 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ane_sys"; - }; - - ps_atc0_common: power-controller@420 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x420 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_common"; - }; - - ps_atc0_pcie: power-controller@428 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x428 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_pcie"; - power-domains = <&ps_atc0_common>; - }; - - ps_atc0_cio: power-controller@430 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x430 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio"; - power-domains = <&ps_atc0_common>; - }; - - ps_atc0_cio_pcie: power-controller@438 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x438 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio_pcie"; - power-domains = <&ps_atc0_cio>; - }; - - ps_atc0_cio_usb: power-controller@440 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x440 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio_usb"; - power-domains = <&ps_atc0_cio>; - }; - - ps_atc1_common: power-controller@448 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x448 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_common"; - }; - - ps_atc1_pcie: power-controller@450 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x450 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_pcie"; - power-domains = <&ps_atc1_common>; - }; - - ps_atc1_cio: power-controller@458 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x458 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio"; - power-domains = <&ps_atc1_common>; - }; - - ps_atc1_cio_pcie: power-controller@460 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x460 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio_pcie"; - power-domains = <&ps_atc1_cio>; - }; - - ps_atc1_cio_usb: power-controller@468 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x468 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio_usb"; - power-domains = <&ps_atc1_cio>; - }; - - ps_sep: power-controller@c00 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc00 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sep"; - apple,always-on; /* Locked on */ - }; - - ps_venc_dma: power-controller@8000 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8000 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_dma"; - power-domains = <&ps_venc_sys>; - }; - - ps_venc_pipe4: power-controller@8008 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8008 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_pipe4"; - power-domains = <&ps_venc_dma>; - }; - - ps_venc_pipe5: power-controller@8010 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8010 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_pipe5"; - power-domains = <&ps_venc_dma>; - }; - - ps_venc_me0: power-controller@8018 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8018 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_me0"; - power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; - }; - - ps_venc_me1: power-controller@8020 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8020 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_me1"; - power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; - }; - - ps_ane_sys_cpu: power-controller@c000 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc000 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ane_sys_cpu"; - power-domains = <&ps_ane_sys>; - }; - - ps_disp0_cpu0: power-controller@10018 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x10018 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "disp0_cpu0"; - power-domains = <&ps_disp0_fe>; - apple,always-on; /* TODO: figure out if we can enable PM here */ - apple,min-state = <4>; - }; -}; - -&pmgr_mini { - ps_debug: power-controller@58 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x58 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_spmi0: power-controller@60 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x60 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_spmi0"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_aon: power-controller@70 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x70 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_aon"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_gpio: power-controller@80 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x80 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_gpio"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_fabric: power-controller@a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xa8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_fabric"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_sram: power-controller@b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xb0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_sram"; - apple,always-on; /* Core AON device */ - }; - - ps_debug_usb: power-controller@b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xb8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug_usb"; - apple,always-on; /* Core AON device */ - power-domains = <&ps_debug>; - }; - - ps_debug_auth: power-controller@c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug_auth"; - apple,always-on; /* Core AON device */ - power-domains = <&ps_debug>; - }; - - ps_nub_spmi1: power-controller@68 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x68 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_spmi1"; - apple,always-on; /* Core AON device */ - }; - - ps_msg: power-controller@78 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x78 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msg"; - }; - - ps_atc0_usb_aon: power-controller@88 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x88 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_usb_aon"; - }; - - ps_atc1_usb_aon: power-controller@90 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x90 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_usb_aon"; - }; - - ps_atc0_usb: power-controller@98 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x98 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_usb"; - power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; - }; - - ps_atc1_usb: power-controller@a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xa0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_usb"; - power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; - }; -}; diff --git a/arch/arm/dts/t8103-u-boot.dtsi b/arch/arm/dts/t8103-u-boot.dtsi deleted file mode 100644 index e9e593a00cf..00000000000 --- a/arch/arm/dts/t8103-u-boot.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT - -&serial0 { - bootph-all; -}; - -&pmgr { - bootph-all; -}; - -&ps_sio_busif { - bootph-all; -}; - -&ps_sio { - bootph-all; -}; - -&ps_uart_p { - bootph-all; -}; - -&ps_uart0 { - bootph-all; -}; diff --git a/arch/arm/dts/t8103.dtsi b/arch/arm/dts/t8103.dtsi deleted file mode 100644 index ed7840f94b6..00000000000 --- a/arch/arm/dts/t8103.dtsi +++ /dev/null @@ -1,696 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple T8103 "M1" SoC - * - * Other names: H13G, "Tonga" - * - * Copyright The Asahi Linux Contributors - */ - -#include -#include -#include -#include - -/ { - compatible = "apple,t8103", "apple,arm-platform"; - - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu1: cpu@1 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu2: cpu@2 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu3: cpu@3 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu4: cpu@10100 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu5: cpu@10101 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu6: cpu@10102 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10102>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu7: cpu@10103 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10103>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&aic>; - interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; - interrupts = , - , - , - ; - }; - - clkref: clock-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "clkref"; - }; - - clk_120m: clock-120m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "clk_120m"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - - ranges; - nonposted-mmio; - - i2c0: i2c@235010000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35010000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = ; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c0>; - }; - - i2c1: i2c@235014000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35014000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = ; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c1>; - }; - - i2c2: i2c@235018000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35018000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = ; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c2>; - status = "disabled"; /* not used in all devices */ - }; - - i2c3: i2c@23501c000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x3501c000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = ; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c3>; - }; - - i2c4: i2c@235020000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35020000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = ; - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c4>; - status = "disabled"; /* only used in J293 */ - }; - - spi3: spi@23510c000 { - compatible = "apple,t8103-spi", "apple,spi"; - reg = <0x2 0x3510c000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = ; - clocks = <&clk_120m>; - pinctrl-0 = <&spi3_pins>; - pinctrl-names = "default"; - power-domains = <&ps_spi3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; /* only used in J293/J313 */ - }; - - serial0: serial@235200000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x35200000 0x0 0x1000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = ; - /* - * TODO: figure out the clocking properly, there may - * be a third selectable clock. - */ - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - power-domains = <&ps_uart0>; - status = "disabled"; - }; - - serial2: serial@235208000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x35208000 0x0 0x1000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = ; - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - power-domains = <&ps_uart2>; - status = "disabled"; - }; - - aic: interrupt-controller@23b100000 { - compatible = "apple,t8103-aic", "apple,aic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2 0x3b100000 0x0 0x8000>; - power-domains = <&ps_aic>; - }; - - pmgr: power-management@23b700000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3b700000 0 0x14000>; - }; - - pinctrl_ap: pinctrl@23c100000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3c100000 0x0 0x100000>; - power-domains = <&ps_gpio>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_ap 0 0 212>; - apple,npins = <212>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; - - i2c0_pins: i2c0-pins { - pinmux = , - ; - }; - - i2c1_pins: i2c1-pins { - pinmux = , - ; - }; - - i2c2_pins: i2c2-pins { - pinmux = , - ; - }; - - i2c3_pins: i2c3-pins { - pinmux = , - ; - }; - - i2c4_pins: i2c4-pins { - pinmux = , - ; - }; - - spi3_pins: spi3-pins { - pinmux = , - , - , - ; - }; - - pcie_pins: pcie-pins { - pinmux = , - , - ; - }; - }; - - spmi: spmi@23d0d9300 { - compatible = "apple,t8103-spmi", "apple,spmi"; - reg = <0x2 0x3d0d9300 0x0 0x100>; - interrupt-parent = <&aic>; - interrupts = ; - #address-cells = <2>; - #size-cells = <0>; - status = "disabled"; - }; - - pinctrl_nub: pinctrl@23d1f0000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3d1f0000 0x0 0x4000>; - power-domains = <&ps_nub_gpio>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_nub 0 0 23>; - apple,npins = <23>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; - }; - - pmgr_mini: power-management@23d280000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3d280000 0 0x4000>; - }; - - wdt: watchdog@23d2b0000 { - compatible = "apple,t8103-wdt", "apple,wdt"; - reg = <0x2 0x3d2b0000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = ; - }; - - pinctrl_smc: pinctrl@23e820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3e820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_smc 0 0 16>; - apple,npins = <16>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; - }; - - smc_mbox: mbox@23e408000 { - compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; - reg = <0x2 0x3e408000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = , - , - , - ; - interrupt-names = "send-empty", "send-not-empty", - "recv-empty", "recv-not-empty"; - #mbox-cells = <0>; - }; - - smc: smc@23e050000 { - compatible = "apple,smc"; - reg = <0x2 0x3e050000 0x0 0x4000>; - mboxes = <&smc_mbox>; - gpio-controller; - #gpio-cells = <2>; - gpio-13 = <0x00800000>; - }; - - pinctrl_aop: pinctrl@24a820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x4a820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; - }; - - ans_mbox: mbox@277408000 { - compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; - reg = <0x2 0x77408000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = , - , - , - ; - interrupt-names = "send-empty", "send-not-empty", - "recv-empty", "recv-not-empty"; - #mbox-cells = <0>; - power-domains = <&ps_ans2>; - }; - - sart: sart@27bc50000 { - compatible = "apple,t8103-sart", "apple,sart2"; - reg = <0x2 0x7bc50000 0x0 0x10000>; - power-domains = <&ps_ans2>; - }; - - nvme@27bcc0000 { - compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; - reg = <0x2 0x7bcc0000 0x0 0x40000>, - <0x2 0x77400000 0x0 0x4000>; - reg-names = "nvme", "ans"; - interrupt-parent = <&aic>; - interrupts = ; - mboxes = <&ans_mbox>; - apple,sart = <&sart>; - power-domains = <&ps_ans2>; - resets = <&ps_ans2>; - }; - - dwc3_0: usb@382280000 { - compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3"; - reg = <0x3 0x82280000 0x0 0x100000>; - interrupt-parent = <&aic>; - interrupts = ; - usb-role-switch; - role-switch-default-mode = "host"; - iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_0_dart_0: iommu@382f00000 { - compatible = "apple,t8103-dart"; - reg = <0x3 0x82f00000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = ; - #iommu-cells = <1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_0_dart_1: iommu@382f80000 { - compatible = "apple,t8103-dart"; - reg = <0x3 0x82f80000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = ; - #iommu-cells = <1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_1: usb@502280000 { - compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3"; - reg = <0x5 0x02280000 0x0 0x100000>; - interrupt-parent = <&aic>; - interrupts = ; - usb-role-switch; - role-switch-default-mode = "host"; - iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; - power-domains = <&ps_atc1_usb>; - }; - - dwc3_1_dart_0: iommu@502f00000 { - compatible = "apple,t8103-dart"; - reg = <0x5 0x02f00000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = ; - #iommu-cells = <1>; - power-domains = <&ps_atc1_usb>; - }; - - dwc3_1_dart_1: iommu@502f80000 { - compatible = "apple,t8103-dart"; - reg = <0x5 0x02f80000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = ; - #iommu-cells = <1>; - power-domains = <&ps_atc1_usb>; - }; - - pcie0_dart_0: dart@681008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x81008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = ; - power-domains = <&ps_apcie_gp>; - }; - - pcie0_dart_1: dart@682008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x82008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = ; - power-domains = <&ps_apcie_gp>; - }; - - pcie0_dart_2: dart@683008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x83008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = ; - power-domains = <&ps_apcie_gp>; - }; - - pcie0: pcie@690000000 { - compatible = "apple,t8103-pcie", "apple,pcie"; - device_type = "pci"; - - reg = <0x6 0x90000000 0x0 0x1000000>, - <0x6 0x80000000 0x0 0x100000>, - <0x6 0x81000000 0x0 0x4000>, - <0x6 0x82000000 0x0 0x4000>, - <0x6 0x83000000 0x0 0x4000>; - reg-names = "config", "rc", "port0", "port1", "port2"; - - interrupt-parent = <&aic>; - interrupts = , - , - ; - - msi-controller; - msi-parent = <&pcie0>; - msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; - - - iommu-map = <0x100 &pcie0_dart_0 1 1>, - <0x200 &pcie0_dart_1 1 1>, - <0x300 &pcie0_dart_2 1 1>; - iommu-map-mask = <0xff00>; - - bus-range = <0 3>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, - <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; - - power-domains = <&ps_apcie_gp>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - - port00: pci@0,0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port00 0 0 0 0>, - <0 0 0 2 &port00 0 0 0 1>, - <0 0 0 3 &port00 0 0 0 2>, - <0 0 0 4 &port00 0 0 0 3>; - }; - - port01: pci@1,0 { - device_type = "pci"; - reg = <0x800 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port01 0 0 0 0>, - <0 0 0 2 &port01 0 0 0 1>, - <0 0 0 3 &port01 0 0 0 2>, - <0 0 0 4 &port01 0 0 0 3>; - }; - - port02: pci@2,0 { - device_type = "pci"; - reg = <0x1000 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port02 0 0 0 0>, - <0 0 0 2 &port02 0 0 0 1>, - <0 0 0 3 &port02 0 0 0 2>, - <0 0 0 4 &port02 0 0 0 3>; - }; - }; - - dart_sio: iommu@235004000 { - compatible = "apple,t8103-dart", "apple,dart"; - reg = <0x2 0x35004000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = ; - #iommu-cells = <1>; - power-domains = <&ps_sio_cpu>; - }; - - nco_inp: clock-ref { - compatible = "fixed-factor-clock"; - clocks = <&clkref>; - #clock-cells = <0>; - clock-mult = <75>; - clock-div = <2>; // 24 MHz * (75/2) = 900 MHz - clock-output-names = "nco_inp"; - }; - - nco: nco@23b044000 { - compatible = "apple,t8103-nco", "apple,nco"; - reg = <0x2 0x3b044000 0x0 0x14000>; - clocks = <&nco_inp>; - #clock-cells = <1>; - apple,nchannels = <5>; - }; - - admac: dma-controller@238200000 { - compatible = "apple,t8103-admac", "apple,admac"; - reg = <0x2 0x38200000 0x0 0x34000>; - dma-channels = <12>; - interrupt-parent = <&aic>; - interrupts = ; - #dma-cells = <1>; - iommus = <&dart_sio 2>; - power-domains = <&ps_sio_adma>; - }; - - mca: mca { - compatible = "apple,t8103-mca", "apple,mca"; - reg = <0x2 0x38400000 0x0 0x18000>, - <0x2 0x38300000 0x0 0x30000>; - reg-names = "clusters", "switch"; - clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; - power-domains = <&ps_mca0>; //, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - resets = <&ps_mca0>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - - #sound-dai-cells = <1>; - apple,nclusters = <6>; - apple,mclk-range = <2600000 25000000>; - - route { - dmas = <&admac 2>; - dma-names = "tx"; - apple,serdes = <1>; - sound-dai = <&mca 0>; - }; - - route2 { - dmas = <&admac 6>; - dma-names = "tx"; - apple,serdes = <3>; - sound-dai = <&mca 2>; - }; - }; - }; -}; - -#include "t8103-pmgr.dtsi" diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 8aa5f9721c4..5359b2ad87b 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -222,6 +222,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits); * mmu_setup() - Sets up the mmu page tables as per mem_map */ void mmu_setup(void); + +/** + * mmu_enable() - Enable the MMU by setting 'M' bit in SCTLR register + */ +void mmu_enable(void); #endif #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kconfig index 294690ec0e8..fdc8c32152f 100644 --- a/arch/arm/mach-apple/Kconfig +++ b/arch/arm/mach-apple/Kconfig @@ -3,12 +3,22 @@ if ARCH_APPLE config TEXT_BASE default 0x00000000 -config SYS_CONFIG_NAME - default "apple" - config SYS_SOC default "apple" +config SYS_VENDOR + default "apple" + +config SYS_BOARD + string "Board name" + default "mac" + help + This option contains information about board name. + Based on this option board// will + be used. + Apple silicon based devices are expected to use the generic board name + "mac". + config SYS_MALLOC_LEN default 0x4000000 diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 4cd8979bdc2..20054f54089 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -673,6 +673,83 @@ static struct mm_region t6022_mem_map[] = { } }; +/* Apple M3 */ + +static struct mm_region t8122_mem_map[] = { + { + /* I/O */ + .virt = 0x200000000, + .phys = 0x200000000, + .size = 4UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* NVMe */ + .virt = 0x300000000, + .phys = 0x300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC0 */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC1 */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map; int board_init(void) @@ -720,6 +797,8 @@ void build_mem_map(void) mem_map = t6020_mem_map; else if (of_machine_is_compatible("apple,t6022")) mem_map = t6022_mem_map; + else if (of_machine_is_compatible("apple,t8122")) + mem_map = t8122_mem_map; else panic("Unsupported SoC\n"); diff --git a/arch/arm/mach-apple/rtkit_helper.c b/arch/arm/mach-apple/rtkit_helper.c index b7d60e15700..cbdc204f141 100644 --- a/arch/arm/mach-apple/rtkit_helper.c +++ b/arch/arm/mach-apple/rtkit_helper.c @@ -11,6 +11,7 @@ #include #include #include +#include /* ASC registers */ #define REG_CPU_CTRL 0x0044 diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b0a75988714..19a6e24f38b 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -294,6 +294,7 @@ void enable_caches(void) __func__, ret); } + mmu_enable(); icache_enable(); dcache_enable(); } diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index 0e0e43c08e4..fcca3811241 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -13,7 +13,9 @@ menu "Select Target SoC" config R8A78000 bool "Renesas SoC R8A78000" select GICV3 + imply CLK_R8A78000 imply PINCTRL_PFC_R8A78000 + imply RENESAS_R8A78000_POWER_DOMAIN endmenu diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 652a392ba6f..83c576d6007 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -40,6 +40,27 @@ else srec_cat_le_cmd := "-l-e-constant" endif +ifneq ($(CONFIG_RCAR_GEN5),) +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ + -Output_Block_Size 16 \ + -generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \ + -generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 + +quiet_cmd_srec_shdr_cat = SRECCAT $@ + cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \ + -Output_Block_Size 16 \ + -generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \ + -generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \ + -generate 0x18402004 0x18402008 $(srec_cat_le_cmd) 0x00010010 4 \ + -generate 0x18402008 0x1840200c $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x1840200c 0x18402010 $(srec_cat_le_cmd) 0x34040000 4 \ + -generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \ + -generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 \ + -generate 0x18402018 0x1840201c $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x1840201c 0x18402020 $(srec_cat_le_cmd) 0x0 4 +else ifneq ($(CONFIG_RCAR_GEN4),) quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ @@ -106,10 +127,17 @@ quiet_cmd_srec_cat = SRECCAT $@ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif endif +endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}')) +u-boot-elf.scif: u-boot-elf.srec u-boot.bin + $(call cmd,srec_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}')) + +u-boot-elf.shdr: u-boot-elf.srec u-boot.bin + $(call cmd,srec_shdr_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}')) + # if srec_cat is present build u-boot-spl.scif by default has_srec_cat = $(call try-run,srec_cat -VERSion,y,n) INPUTS-$(has_srec_cat) += u-boot-spl.scif diff --git a/arch/arm/mach-renesas/u-boot-rsip.lds b/arch/arm/mach-renesas/u-boot-rsip.lds new file mode 100644 index 00000000000..c5a74f8a608 --- /dev/null +++ b/arch/arm/mach-renesas/u-boot-rsip.lds @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + */ + +#include +#include + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) + /* + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. + * + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. + */ + /DISCARD/ : { *(.rel._secure*) } +#endif + . = 0x00000000; + + . = ALIGN(4); + __image_copy_start = ADDR(.text); + .text : + { + CPUDIR/start.o (.text*) + *(.vectors) + } + + /* This needs to come before *(.text*) */ + .efi_runtime : { + __efi_runtime_start = .; + *(.text.efi_runtime*) + *(.rodata.efi_runtime*) + *(.data.efi_runtime*) + __efi_runtime_stop = .; + } + + .text_rest : + { + *(.text*) + } + +#ifdef CONFIG_ARMV7_NONSEC + + /* Align the secure section only if we're going to use it in situ */ + .__secure_start +#ifndef CONFIG_ARMV7_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + : { + KEEP(*(.__secure_start)) + } + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define __ARMV7_SECURE_BASE +#define __ARMV7_PSCI_STACK_IN_RAM +#else +#define __ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_BASE +#endif + + .secure_text __ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + +#ifdef CONFIG_ARMV7_PSCI + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : +#ifdef __ARMV7_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + + /* Skip addresses for stack */ + . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; + + /* Align end of stack section to page boundary */ + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + +#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE + /* + * We are not checking (__secure_end - __secure_start) here, + * as these are the load addresses, and do not include the + * stack section. Instead, use the end of the stack section + * and the start of the text section. + */ + ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE, + "Error: secure section exceeds secure memory size"); +#endif + } + +#ifndef __ARMV7_PSCI_STACK_IN_RAM + /* Reset VMA but don't allocate space if we have secure SRAM */ + . = LOADADDR(.secure_stack); +#endif + +#endif + + .__secure_end : AT(ADDR(.__secure_end)) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + __data_start = .; + *(.data*) + __data_end = .; + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); + } + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(8); + __image_copy_end = .; + + /* + * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start + * needs to be a multiple of 8 and we overlay .bss with .rel.dyn + */ + .rel.dyn ALIGN(8) : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + . = ALIGN(8); + } + + _end = .; + _image_binary_end = .; + +/* + * These sections occupy the same memory, but their lifetimes do + * not overlap: U-Boot initializes .bss only after applying dynamic + * relocations and therefore after it doesn't need .rel.dyn any more. + */ + + /* BSS goes to special read-write offset below U-Boot entry point */ + . = 0xb8400000; + .bss (OVERLAY): { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynbss) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu.hash) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } +} + +ASSERT(_image_binary_end % 8 == 0, \ + "_image_binary_end must be 8-byte aligned for device tree"); diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index b64965d204e..39f25869c1d 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -114,7 +114,6 @@ config STM32MP23X select OF_BOARD select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select STM32MP_TAMP_NVMEM select SYS_ARCH_TIMER diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 739d14f8002..414782c835f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -41,10 +41,12 @@ #ifdef CONFIG_FSL_CAAM #include #endif -#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_FSL_CORENET) #include +#if defined(CONFIG_NXP_ESBC) #include #endif +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include #include @@ -899,6 +901,8 @@ int cpu_init_r(void) #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) if (pamu_init() < 0) fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#elif defined(CONFIG_FSL_CORENET) + pamu_init(); #endif #ifdef CONFIG_FSL_CAAM diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 766b0c05951..4fd3478ac2f 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb -dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi deleted file mode 100644 index ad09b138fc8..00000000000 --- a/arch/powerpc/dts/p2041.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041 Silicon/SoC Device Tree Source (pre include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -/include/ "e500mc_power_isa.dtsi" - -/ { - compatible = "fsl,P2041"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: PowerPC,e500mc@0 { - device_type = "cpu"; - reg = <0>; - fsl,portid-mapping = <0x80000000>; - }; - cpu1: PowerPC,e500mc@1 { - device_type = "cpu"; - reg = <1>; - fsl,portid-mapping = <0x40000000>; - }; - cpu2: PowerPC,e500mc@2 { - device_type = "cpu"; - reg = <2>; - fsl,portid-mapping = <0x20000000>; - }; - cpu3: PowerPC,e500mc@3 { - device_type = "cpu"; - reg = <3>; - fsl,portid-mapping = <0x10000000>; - }; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "simple-bus"; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic", "chrp,open-pic"; - device_type = "open-pic"; - clock-frequency = <0x0>; - }; - - espi0: spi@110000 { - compatible = "fsl,mpc8536-espi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x110000 0x1000>; - fsl,espi-num-chipselects = <4>; - status = "disabled"; - }; - - usb0: usb@210000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - usb1: usb@211000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - sata: sata@220000 { - compatible = "fsl,pq-sata-v2"; - reg = <0x220000 0x1000>; - interrupts = <68 0x2 0 0>; - sata-offset = <0x1000>; - sata-number = <2>; - sata-fpdma = <0>; - }; - - esdhc: esdhc@114000 { - compatible = "fsl,esdhc"; - reg = <0x114000 0x1000>; - clock-frequency = <0>; - }; - - /include/ "qoriq-i2c-0.dtsi" - /include/ "qoriq-i2c-1.dtsi" - }; - - pcie@ffe200000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ - law_trgt_if = <0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe201000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ - law_trgt_if = <1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe202000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ - law_trgt_if = <2>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; -}; diff --git a/arch/powerpc/dts/p2041rdb-u-boot.dtsi b/arch/powerpc/dts/p2041rdb-u-boot.dtsi new file mode 100644 index 00000000000..1dc83cf846b --- /dev/null +++ b/arch/powerpc/dts/p2041rdb-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&serial0 { + bootph-all; +}; + +&soc { + i2c@118000 { + bootph-all; + }; + + spi@110000 { + flash@0 { + spi-max-frequency = <10000000>; + }; + }; +}; + +#include "u-boot.dtsi" diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts deleted file mode 100644 index 0fa1f098524..00000000000 --- a/arch/powerpc/dts/p2041rdb.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041RDB Device Tree Source - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/include/ "p2041.dtsi" - -/ { - model = "fsl,P2041RDB"; - compatible = "fsl,P2041RDB"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - aliases { - phy_rgmii_0 = &phy_rgmii_0; - phy_rgmii_1 = &phy_rgmii_1; - phy_sgmii_2 = &phy_sgmii_2; - phy_sgmii_3 = &phy_sgmii_3; - phy_sgmii_4 = &phy_sgmii_4; - phy_sgmii_1c = &phy_sgmii_1c; - phy_sgmii_1d = &phy_sgmii_1d; - phy_sgmii_1e = &phy_sgmii_1e; - phy_sgmii_1f = &phy_sgmii_1f; - phy_xgmii_2 = &phy_xgmii_2; - spi0 = &espi0; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - - fman@400000 { - ethernet@e0000 { - phy-handle = <&phy_sgmii_2>; - phy-connection-type = "sgmii"; - }; - - mdio@e1120 { - phy_rgmii_0: ethernet-phy@0 { - reg = <0x0>; - }; - - phy_rgmii_1: ethernet-phy@1 { - reg = <0x1>; - }; - - phy_sgmii_2: ethernet-phy@2 { - reg = <0x2>; - }; - - phy_sgmii_3: ethernet-phy@3 { - reg = <0x3>; - }; - - phy_sgmii_4: ethernet-phy@4 { - reg = <0x4>; - }; - - phy_sgmii_1c: ethernet-phy@1c { - reg = <0x1c>; - }; - - phy_sgmii_1d: ethernet-phy@1d { - reg = <0x1d>; - }; - - phy_sgmii_1e: ethernet-phy@1e { - reg = <0x1e>; - }; - - phy_sgmii_1f: ethernet-phy@1f { - reg = <0x1f>; - }; - }; - - ethernet@e2000 { - phy-handle = <&phy_sgmii_3>; - phy-connection-type = "sgmii"; - }; - - ethernet@e4000 { - phy-handle = <&phy_sgmii_4>; - phy-connection-type = "sgmii"; - }; - - ethernet@e6000 { - phy-handle = <&phy_rgmii_1>; - phy-connection-type = "rgmii"; - }; - - ethernet@e8000 { - phy-handle = <&phy_rgmii_0>; - phy-connection-type = "rgmii"; - }; - - ethernet@f0000 { - phy-handle = <&phy_xgmii_2>; - phy-connection-type = "xgmii"; - }; - - mdio@f1000 { - phy_xgmii_2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x0>; - }; - }; - }; - }; -}; - -&espi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - /* input clock */ - spi-max-frequency = <10000000>; - }; -}; - -/include/ "p2041si-post.dtsi" diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi deleted file mode 100644 index 8819199646f..00000000000 --- a/arch/powerpc/dts/p2041si-post.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * P2041/P2040 Silicon/SoC Device Tree Source (post include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2020 NXP - * - */ - -&soc { - -/include/ "qoriq-clockgen1.dtsi" -/include/ "qoriq-gpio-0.dtsi" -/include/ "qoriq-sec4.2-0.dtsi" - -/* include used FMan blocks */ -/include/ "qoriq-fman-0.dtsi" -/include/ "qoriq-fman-0-1g-0.dtsi" -/include/ "qoriq-fman-0-1g-1.dtsi" -/include/ "qoriq-fman-0-1g-2.dtsi" -/include/ "qoriq-fman-0-1g-3.dtsi" -/include/ "qoriq-fman-0-1g-4.dtsi" -/include/ "qoriq-fman-0-10g-0.dtsi" - fman@400000 { - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@f0000 { - }; - }; -}; diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index d94c1494d53..81daba1c5ef 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -81,12 +81,13 @@ char *soc_name_decode(void) } /* - * --rev. are 6 chars - * max platform name is qemu which is 4 chars + * --rev.-el are 9 chars + * max platform name is emu-mmd which is 7 chars * platform version number are 1+1 - * Plus 1 char for \n + * el is 1 char + * Plus 1 char for NULL byte */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20); if (!name) return NULL; diff --git a/board/apple/mac/mac.env b/board/apple/mac/mac.env new file mode 100644 index 00000000000..109379c8c67 --- /dev/null +++ b/board/apple/mac/mac.env @@ -0,0 +1,4 @@ +stdin=serial,usbkbd,spikbd +stdout=vidconsole,serial +stderr=vidconsole,serial +boot_targets=nvme usb diff --git a/board/nxp/common/i2c_mux.h b/board/nxp/common/i2c_mux.h index 0870c1918e6..ef7ce8e2e51 100644 --- a/board/nxp/common/i2c_mux.h +++ b/board/nxp/common/i2c_mux.h @@ -10,6 +10,11 @@ #ifdef CONFIG_FSL_USE_PCA9547_MUX int select_i2c_ch_pca9547(u8 ch, int bus); +#else +static inline int select_i2c_ch_pca9547(u8 ch, int bus) +{ + return -EOPNOTSUPP; +} #endif #endif diff --git a/board/nxp/ls1012afrdm/eth.c b/board/nxp/ls1012afrdm/eth.c index c431e5e611b..8761ec7845e 100644 --- a/board/nxp/ls1012afrdm/eth.c +++ b/board/nxp/ls1012afrdm/eth.c @@ -7,16 +7,6 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include #include #include diff --git a/board/nxp/ls1012ardb/eth.c b/board/nxp/ls1012ardb/eth.c index 71cb2988a56..6a6f4608fd1 100644 --- a/board/nxp/ls1012ardb/eth.c +++ b/board/nxp/ls1012ardb/eth.c @@ -6,18 +6,6 @@ #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include #include #include diff --git a/board/nxp/ls1021atsn/ls1021atsn.c b/board/nxp/ls1021atsn/ls1021atsn.c index c92430c0896..277506fdbb8 100644 --- a/board/nxp/ls1021atsn/ls1021atsn.c +++ b/board/nxp/ls1021atsn/ls1021atsn.c @@ -123,11 +123,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; diff --git a/board/nxp/ls1021atwr/ls1021atwr.c b/board/nxp/ls1021atwr/ls1021atwr.c index 0758e5eae25..135497f7c5d 100644 --- a/board/nxp/ls1021atwr/ls1021atwr.c +++ b/board/nxp/ls1021atwr/ls1021atwr.c @@ -239,11 +239,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void convert_serdes_mux(int type, int need_reset) { diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index db94d9c1fa8..007125358bd 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -103,11 +103,6 @@ int board_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/nxp/ls1043aqds/Makefile b/board/nxp/ls1043aqds/Makefile index ff830788fd7..98ad49f6f0c 100644 --- a/board/nxp/ls1043aqds/Makefile +++ b/board/nxp/ls1043aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1043aqds.o diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c deleted file mode 100644 index 5a8ca27b327..00000000000 --- a/board/nxp/ls1043aqds/eth.c +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1043aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT4 5 -#define EMI2 6 - -static const char * const mdio_names[] = { - "LS1043AQDS_MDIO_RGMII1", - "LS1043AQDS_MDIO_RGMII2", - "LS1043AQDS_MDIO_SLOT1", - "LS1043AQDS_MDIO_SLOT2", - "LS1043AQDS_MDIO_SLOT3", - "LS1043AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 2, 3, 4}; -#endif - -static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI2) - return NULL; - - name = ls1043aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1043aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1043aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1043aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1043aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1043aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1043aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1043aqds_mdio_read; - bus->write = ls1043aqds_mdio_write; - bus->reset = ls1043aqds_mdio_reset; - strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - if (port == FM1_DTSEC9) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s1-p1"); - } else if (port == FM1_DTSEC2) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s2-p1"); - } else if (port == FM1_DTSEC5) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s3-p1"); - } else if (port == FM1_DTSEC6) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s4-p1"); - } - } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (mdio_mux[port]) { - case EMI1_SLOT1: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p4"); - break; - default: - break; - } - break; - case EMI1_SLOT2: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p4"); - break; - default: - break; - } - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - port == FM1_10GEC1) { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1-slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_XGMII: - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x2555: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - break; - case 0x4555: - case 0x4558: - /* QSGMII on lane A, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S1); - break; - case 0x1355: - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x2355: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x3335: - /* SGMII on lane C, MAC 5 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3355: - case 0x3358: - /* SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3555: - case 0x3558: - /* SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x1455: - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2455: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2255: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* 2.5G SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, 2); - break; - case 0x3333: - /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, - SGMII_CARD_PORT1_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_2500_FM1_DTSEC1 + idx); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - } - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index f043599fbb8..0f115c16232 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -550,10 +550,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1043ardb/Makefile b/board/nxp/ls1043ardb/Makefile index 3f651b41606..13e0411c1ba 100644 --- a/board/nxp/ls1043ardb/Makefile +++ b/board/nxp/ls1043ardb/Makefile @@ -5,6 +5,5 @@ obj-y += ddr.o obj-y += ls1043ardb.o ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET_LEGACY) += eth.o obj-y += cpld.o endif diff --git a/board/nxp/ls1043ardb/eth.c b/board/nxp/ls1043ardb/eth.c deleted file mode 100644 index cacc49c0584..00000000000 --- a/board/nxp/ls1043ardb/eth.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x1455: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/ls1046afrwy/eth.c b/board/nxp/ls1046afrwy/eth.c index 8efc7f68424..d76841c6ab4 100644 --- a/board/nxp/ls1046afrwy/eth.c +++ b/board/nxp/ls1046afrwy/eth.c @@ -4,64 +4,7 @@ */ #include #include -#include #include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info dtsec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x3040: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(FM1_DTSEC6, dev); - fm_info_set_mdio(FM1_DTSEC5, dev); - fm_info_set_mdio(FM1_DTSEC10, dev); - fm_info_set_mdio(FM1_DTSEC1, dev); - - fm_disable_port(FM1_DTSEC9); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1046aqds/Makefile b/board/nxp/ls1046aqds/Makefile index 365247d92bc..8292726b0e4 100644 --- a/board/nxp/ls1046aqds/Makefile +++ b/board/nxp/ls1046aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1046aqds.o diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c deleted file mode 100644 index cd3500c2e96..00000000000 --- a/board/nxp/ls1046aqds/eth.c +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018-2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1046aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT4 4 - -static const char * const mdio_names[] = { - "LS1046AQDS_MDIO_RGMII1", - "LS1046AQDS_MDIO_RGMII2", - "LS1046AQDS_MDIO_SLOT1", - "LS1046AQDS_MDIO_SLOT2", - "LS1046AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes 1 & 2 lanes to default slot. */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; -#endif - -static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI1_SLOT4) - return NULL; - - name = ls1046aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1046aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1046aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1046aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1046aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1046aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1046aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1046aqds_mdio_read; - bus->write = ls1046aqds_mdio_write; - bus->reset = ls1046aqds_mdio_reset; - sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - const char *phyconn; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - switch (port) { - case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); - break; - default: - break; - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII on QDS */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - (port == FM1_10GEC1 || port == FM1_10GEC2)) { - phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", port); - } else { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "xgmii"); - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1, srds_s2; - u8 brdcfg12; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - srds_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x3333: - /* SGMII on slot 1, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - case 0x1333: - case 0x2333: - /* SGMII on slot 1, MAC 10 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1133: - case 0x2233: - /* SGMII on slot 1, MAC 5/6 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x1040: - case 0x2040: - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC10, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x3363: - /* SGMII on slot 1, MAC 9/10 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1163: - case 0x2263: - case 0x2223: - /* SGMII on slot 1, MAC 6 */ - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", - srds_s1); - break; - } - - if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) - /* SGMII on slot 4, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - if (i == FM1_DTSEC5) { - /* route lane 2 to slot1 so to have - * one sgmii riser card supports - * MAC5 and MAC6. - */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], - brdcfg12 | 0x80); - } - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else { - /* clear the bit 7 to route lane B on slot2. */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); - - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - lane_to_slot[lane] = 2; - } - - if (i == FM1_DTSEC2) - lane = 5; - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 7df12550868..679b0b2235f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -434,10 +434,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1046ardb/eth.c b/board/nxp/ls1046ardb/eth.c index fee8e0e21d4..ce9b7b81e3d 100644 --- a/board/nxp/ls1046ardb/eth.c +++ b/board/nxp/ls1046ardb/eth.c @@ -4,78 +4,7 @@ */ #include #include -#include #include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* Set the two on-board SGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); - - /* Set the on-board AQ PHY address */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - - switch (srds_s1) { - case 0x1133: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 51ec055be63..5783dd8a403 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -974,7 +974,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/ls2080ardb/eth_ls2080rdb.c b/board/nxp/ls2080ardb/eth_ls2080rdb.c index 7d5beb32417..6a8859fd0c5 100644 --- a/board/nxp/ls2080ardb/eth_ls2080rdb.c +++ b/board/nxp/ls2080ardb/eth_ls2080rdb.c @@ -9,25 +9,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ - -#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD) - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index 6f824f57c47..d08598d1c62 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -503,7 +503,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/lx2160a/eth_lx2160aqds.c b/board/nxp/lx2160a/eth_lx2160aqds.c index 9939bb6f89e..4c16f565b69 100644 --- a/board/nxp/lx2160a/eth_lx2160aqds.c +++ b/board/nxp/lx2160a/eth_lx2160aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2160ardb.c b/board/nxp/lx2160a/eth_lx2160ardb.c index 90e7c9100e1..31bbac6310e 100644 --- a/board/nxp/lx2160a/eth_lx2160ardb.c +++ b/board/nxp/lx2160a/eth_lx2160ardb.c @@ -11,23 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - return pci_eth_init(bis); -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2162aqds.c b/board/nxp/lx2160a/eth_lx2162aqds.c index 805aa705be9..81b81d47978 100644 --- a/board/nxp/lx2160a/eth_lx2162aqds.c +++ b/board/nxp/lx2160a/eth_lx2162aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index 341f82ce724..b7a6ccf46aa 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -242,13 +242,17 @@ int init_func_vid(void) return 0; } -#endif EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); +#endif int checkboard(void) { - enum boot_src src = get_boot_src(); char buf[64]; + + cpu_name(buf); + +#if IS_ENABLED(CONFIG_FSL_QIXIS) + enum boot_src src = get_boot_src(); u8 sw; #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; @@ -258,7 +262,6 @@ int checkboard(void) "100 separate SSCG"}; #endif - cpu_name(buf); #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else @@ -325,7 +328,10 @@ int checkboard(void) clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); #endif -#endif +#endif /* LX2160ARDB-inside-QIXIS switch */ +#else /* !CONFIG_FSL_QIXIS */ + printf("Board: %s\n", buf); +#endif /* CONFIG_FSL_QIXIS */ return 0; } @@ -554,7 +560,7 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); #endif -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) pci_init(); #endif return 0; @@ -788,7 +794,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); +#if IS_ENABLED(CONFIG_FSL_MC_ENET) fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); +#endif if (mc_memory_base != 0) mc_memory_bank++; @@ -818,7 +826,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/m5253demo/m5253demo.c b/board/nxp/m5253demo/m5253demo.c index 50c5320b55c..7d4b60b283e 100644 --- a/board/nxp/m5253demo/m5253demo.c +++ b/board/nxp/m5253demo/m5253demo.c @@ -133,10 +133,3 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_IDE */ - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/board/nxp/m53017evb/README b/board/nxp/m53017evb/README index 25831629266..c6dc020af37 100644 --- a/board/nxp/m53017evb/README +++ b/board/nxp/m53017evb/README @@ -90,10 +90,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/m5373evb/README b/board/nxp/m5373evb/README index c7130b32251..7217886fdfa 100644 --- a/board/nxp/m5373evb/README +++ b/board/nxp/m5373evb/README @@ -89,10 +89,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c index ac91da3f4f6..036deb464b5 100644 --- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -33,16 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ PAD_CTL_SRE_FAST) @@ -55,48 +45,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - - return enable_fec_anatop_clock(1, ENET_125MHZ); -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); - - ret = fecmxc_initialize_multi(bis, 1, - CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC%d MXC: %s:failed\n", 1, __func__); - - return ret; -} - int board_phy_config(struct phy_device *phydev) { /* diff --git a/board/nxp/mx6sxsabresd/mx6sxsabresd.c b/board/nxp/mx6sxsabresd/mx6sxsabresd.c index e3353feec68..cab0892affc 100644 --- a/board/nxp/mx6sxsabresd/mx6sxsabresd.c +++ b/board/nxp/mx6sxsabresd/mx6sxsabresd.c @@ -40,16 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) @@ -71,84 +61,16 @@ static iomux_v3_cfg_t const uart1_pads[] = { static iomux_v3_cfg_t const wdog_b_pad = { MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static iomux_v3_cfg_t const phy_control_pads[] = { - /* 25MHz Ethernet PHY Clock */ - MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - - /* ENET PHY Power */ - MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), - - /* AR8031 PHY Reset */ - MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg, ret; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); - - ret = enable_fec_anatop_clock(0, ENET_125MHZ); - if (ret) - return ret; - - imx_iomux_v3_setup_multiple_pads(phy_control_pads, - ARRAY_SIZE(phy_control_pads)); - - /* Enable the ENET power, active low */ - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); - - /* Reset AR8031 PHY */ - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(2, 7), 1); - - reg = readl(&anatop->pll_enet); - reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; - writel(reg, &anatop->pll_enet); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - setup_fec(); - - return cpu_eth_init(bis); -} - int power_init_board(void) { struct udevice *dev; diff --git a/board/nxp/p2041rdb/Makefile b/board/nxp/p2041rdb/Makefile index ebd0982b5db..5512458832d 100644 --- a/board/nxp/p2041rdb/Makefile +++ b/board/nxp/p2041rdb/Makefile @@ -7,4 +7,3 @@ obj-y += p2041rdb.o obj-y += cpld.o obj-y += ddr.o -obj-y += eth.o diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README deleted file mode 100644 index ae770277372..00000000000 --- a/board/nxp/p2041rdb/README +++ /dev/null @@ -1,138 +0,0 @@ -Overview -========= -The P2041 Processor combines four Power Architecture processor cores -with high-performance datapath acceleration architecture(DPAA), CoreNet -fabric infrastructure, as well as network and peripheral bus interfaces -required for networking, telecom/datacom, wireless infrastructure, and -military/aerospace applications. - -P2041RDB board is a quad core platform supporting the P2041 processor -of QorIQ DPAA series. - -Boot from NOR flash -=================== -1. Build image - make P2041RDB_config - make all - -2. Program image - => tftp 1000000 u-boot.bin - => protect off all - => erase eff40000 efffffff - => cp.b 1000000 eff40000 c0000 - -3. Program RCW - => tftp 1000000 rcw.bin - => protect off all - => erase e8000000 e801ffff - => cp.b 1000000 e8000000 50 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => protect off all - => erase eff00000 eff3ffff - => cp.b 1000000 eff00000 2000 - -5. Change DIP-switch - SW1[1-5] = 10110 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SDCard -=================== -1. Build image - make P2041RDB_SDCARD_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SDCard which contains RCW and U-Boot image. - -3. Program the PBL image to SDCard - => tftp 1000000 pbl_sd.bin - => mmcinfo - => mmc write 1000000 8 672 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => mmc write 1000000 690 10 - -5. Change DIP-switch - SW1[1-5] = 01100 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SPI flash -=================== -1. Build image - make P2041RDB_SPIFLASH_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SPI flash which contains RCW and U-Boot image. - -3. Program the PBL image to SPI flash - => tftp 1000000 pbl_spi.bin - => spi probe 0 - => sf erase 0 100000 - => sf write 1000000 0 $filesize - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => sf erase 110000 10000 - => sf write 1000000 110000 $filesize - -5. Change DIP-switch - SW1[1-5] = 10100 - Note: 1 stands for 'on', 0 stands for 'off' - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for p2041rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -CPLD command -============ -The CPLD is used to control the power sequence and some serdes lane -mux function. - -cpld reset - hard reset to default bank -cpld reset altbank - reset to alternate bank -cpld lane_mux - set multiplexed lane pin - lane 6: 0 -> slot1 (Default) - 1 -> SGMII - lane a: 0 -> slot2 (Default) - 1 -> AURORA - lane c: 0 -> slot2 (Default) - 1 -> SATA0 - lane d: 0 -> slot2 (Default) - 1 -> SATA1 - -Using the Device Tree Source File -================================= -To create the DTB (Device Tree Binary) image file, use a command -similar to this: - dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb - -Or use the following command: - {linux-2.6}/make p2041rdb.dtb ARCH=powerpc - -then the dtb file will be generated under the following directory: - {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb - -Booting Linux -============= -Place a linux uImage in the TFTP disk area. - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp 3000000 p2041rdb.dtb - bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/README.rst b/board/nxp/p2041rdb/README.rst new file mode 100644 index 00000000000..8b8214adc57 --- /dev/null +++ b/board/nxp/p2041rdb/README.rst @@ -0,0 +1,147 @@ +.. SPDX-License-Identifier: GPL-2.0 + +P2041-RDB Board Overview +======================== + +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== + +1. Build image:: + + make P2041RDB_config + make all + +2. Program image:: + + => tftp 1000000 u-boot.bin + => protect off all + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 + +3. Program RCW:: + + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => protect off all + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 + +5. Change DIP-switch to SW1[1-5] = 10110. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +================ + +1. Build image:: + + make P2041RDB_SDCARD_config + make all + +2. Program the PBL image to SDCard:: + + => tftp 1000000 u-boot.pbl + => mmc info + => mmc write 1000000 8 672 + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => mmc write 1000000 690 10 + +4. Change DIP-switch to SW1[1-5] = 01100. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== + +1. Build image:: + + make P2041RDB_SPIFLASH_config + make all + +2. Program the PBL image to SPI flash:: + + => tftp 1000000 u-boot.pbl + => sf probe 0 + => sf update $fileaddr 0 $filesize + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => sf update $fileaddr 110000 $filesize + +4. Change DIP-switch SW1[1-5] = 10100. Note: 1 stands for 'on', 0 stands for 'off' + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- + +Device tree support is available for p2041rdb for below mentioned boot, + +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, + +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +CPLD command +============ + +The CPLD is used to control the power sequence and some serdes lane +mux function:: + + cpld reset - hard reset to default bank + cpld reset altbank - reset to alternate bank + cpld lane_mux - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this:: + + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command:: + + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory:: + + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= + +Place a linux uImage in the TFTP disk area:: + + => tftp 1000000 uImage + => tftp 2000000 rootfs.ext2.gz.uboot + => tftp 3000000 p2041rdb.dtb + => bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c deleted file mode 100644 index 65850866777..00000000000 --- a/board/nxp/p2041rdb/eth.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Author: Mingkai Hu - */ - -/* - * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs - * are provided by the three on-board PHY or by the standard Freescale - * four-port SGMII riser card. We need to change the phy-handle in the - * kernel dts file to point to the correct PHY according to serdes mux - * and serdes protocol selection. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpld.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 -}; - -static int riser_phy_addr[] = { - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, -}; - -/* - * Initialize the lane_to_slot[] array. - * - * On the P2040RDB board the mapping is controlled by CPLD register. - */ -static void initialize_lane_to_slot(void) -{ - u8 mux = CPLD_READ(serdes_mux); - - lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; - lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; - lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; - lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - phy_interface_t intf = fm_info_get_enet_if(port); - char phy[16]; - int lane; - u8 slot; - - switch (intf) { - /* The RGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - break; - /* The SGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - if (lane < 0) - return; - slot = lane_to_slot[lane]; - if (slot) { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } else { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - case PHY_INTERFACE_MODE_XGMII: - /* XAUI */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - default: - break; - } -} -#endif /* #ifdef CONFIG_FMAN_ENET */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* - * Program the three on-board SGMII PHY addresses. If the SGMII Riser - * card used, we'll override the PHY address later. For any DTSEC that - * is RGMII, we'll also override its PHY address later. We assume that - * DTSEC4 and DTSEC5 are used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(i, riser_phy_addr[i]); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ - fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CFG_SYS_FM1_DTSEC5_PHY_ADDR : - CFG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - break; - } - - fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(FM1_10GEC1, - CFG_SYS_FM1_10GEC1_PHY_ADDR); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg new file mode 100644 index 00000000000..f22f3335e73 --- /dev/null +++ b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P2041RDB. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +649FA0C1 C3C02000 68000000 40000000 +00000000 00000000 00000000 D0030F07 +00000000 00000000 00000000 00000000 diff --git a/board/nxp/p2041rdb/rcw_p2041rdb.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg similarity index 100% rename from board/nxp/p2041rdb/rcw_p2041rdb.cfg rename to board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg diff --git a/board/nxp/t102xrdb/Makefile b/board/nxp/t102xrdb/Makefile index b0f27c47191..2a360227418 100644 --- a/board/nxp/t102xrdb/Makefile +++ b/board/nxp/t102xrdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-y += t102xrdb.o obj-$(CONFIG_TARGET_T1024RDB) += cpld.o -obj-y += eth_t102xrdb.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c deleted file mode 100644 index 7185a0abd52..00000000000 --- a/board/nxp/t102xrdb/eth_t102xrdb.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Shengzhou Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); - - switch (srds_s1) { -#ifdef CONFIG_TARGET_T1024RDB - case 0x95: - /* set the on-board RGMII2 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - - /* set 10GBase-R with Aquantia AQR105 PHY */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - break; -#endif - case 0x6a: - case 0x6b: - case 0x77: - case 0x135: - /* set the on-board 2.5G SGMII AQR105 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); -#ifdef CONFIG_TARGET_T1023RDB - /* set the on-board 1G SGMII RTL8211F PHY */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); -#endif - break; - default: - printf("SerDes protocol 0x%x is not supported on T102xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_SGMII: -#if defined(CONFIG_TARGET_T1023RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); -#elif defined(CONFIG_TARGET_T1024RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); -#endif - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_2500BASEX: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ -#if defined(CONFIG_TARGET_T1024RDB) - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || - (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && - (port == FM1_DTSEC3)) { - fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); - } -#endif -} - -void fdt_fixup_board_enet(void *fdt) -{ -} diff --git a/board/nxp/t102xrdb/t102xrdb.c b/board/nxp/t102xrdb/t102xrdb.c index 0a29e27b42c..02223497dd3 100644 --- a/board/nxp/t102xrdb/t102xrdb.c +++ b/board/nxp/t102xrdb/t102xrdb.c @@ -207,7 +207,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif #ifdef CONFIG_TARGET_T1023RDB diff --git a/board/nxp/t102xrdb/t102xrdb.h b/board/nxp/t102xrdb/t102xrdb.h index 33df0f24df8..71e2cfea22e 100644 --- a/board/nxp/t102xrdb/t102xrdb.h +++ b/board/nxp/t102xrdb/t102xrdb.h @@ -6,7 +6,6 @@ #ifndef __T1024_RDB_H__ #define __T1024_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #ifdef CONFIG_TARGET_T1023RDB static u32 t1023rdb_ctrl(u32 ctrl_type); diff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile index 9bca1a1fbcc..cee574aabb9 100644 --- a/board/nxp/t104xrdb/Makefile +++ b/board/nxp/t104xrdb/Makefile @@ -7,7 +7,6 @@ obj-y += spl.o else obj-y += t104xrdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t104xrdb/eth.c b/board/nxp/t104xrdb/eth.c deleted file mode 100644 index c35ec368a45..00000000000 --- a/board/nxp/t104xrdb/eth.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info memac_mdio_info; - unsigned int i; - int phy_addr = 0; - - printf("Initializing Fman\n"); - - memac_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fm_memac_mdio_init(bis, &memac_mdio_info); - - /* - * Program on board RGMII, SGMII PHY addresses. - */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_TARGET_T1042D4RDB - case PHY_INTERFACE_MODE_SGMII: - /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 - * & DTSEC3 - */ - if (FM1_DTSEC1 == i) - phy_addr = CFG_SYS_SGMII1_PHY_ADDR; - if (FM1_DTSEC2 == i) - phy_addr = CFG_SYS_SGMII2_PHY_ADDR; - if (FM1_DTSEC3 == i) - phy_addr = CFG_SYS_SGMII3_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; -#endif - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (FM1_DTSEC4 == i) - phy_addr = CFG_SYS_RGMII1_PHY_ADDR; - if (FM1_DTSEC5 == i) - phy_addr = CFG_SYS_RGMII2_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; - case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_phy_address(i, 0); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || - fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA) - fm_info_set_mdio(i, NULL); - else - fm_info_set_mdio(i, - miiphy_get_dev_by_name( - DEFAULT_FM_MDIO_NAME)); - } - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/t104xrdb/t104xrdb.h b/board/nxp/t104xrdb/t104xrdb.h index 678724c7e2b..5825e69cdb4 100644 --- a/board/nxp/t104xrdb/t104xrdb.h +++ b/board/nxp/t104xrdb/t104xrdb.h @@ -6,7 +6,6 @@ #ifndef __T104x_RDB_H__ #define __T104x_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xqds/Makefile b/board/nxp/t208xqds/Makefile index eb99d921b4a..4bfd2b50d8f 100644 --- a/board/nxp/t208xqds/Makefile +++ b/board/nxp/t208xqds/Makefile @@ -7,7 +7,7 @@ ifdef CONFIG_XPL_BUILD obj-y += spl.o else -obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o endif obj-y += ddr.o diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c deleted file mode 100644 index b55078c8fe1..00000000000 --- a/board/nxp/t208xqds/eth_t208xqds.c +++ /dev/null @@ -1,723 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * - * Shengzhou Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "../common/fman.h" -#include "t208xqds_qixis.h" -#include - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#if defined(CONFIG_TARGET_T2080QDS) -#define EMI1_SLOT2 6 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI2 7 -#endif - -#define PCCR1_SGMIIA_KX_MASK 0x00008000 -#define PCCR1_SGMIIB_KX_MASK 0x00004000 -#define PCCR1_SGMIIC_KX_MASK 0x00002000 -#define PCCR1_SGMIID_KX_MASK 0x00001000 -#define PCCR1_SGMIIE_KX_MASK 0x00000800 -#define PCCR1_SGMIIF_KX_MASK 0x00000400 -#define PCCR1_SGMIIG_KX_MASK 0x00000200 -#define PCCR1_SGMIIH_KX_MASK 0x00000100 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { -#if defined(CONFIG_TARGET_T2080QDS) - "T2080QDS_MDIO_RGMII1", - "T2080QDS_MDIO_RGMII2", - "T2080QDS_MDIO_SLOT1", - "T2080QDS_MDIO_SLOT3", - "T2080QDS_MDIO_SLOT4", - "T2080QDS_MDIO_SLOT5", - "T2080QDS_MDIO_SLOT2", - "T2080QDS_MDIO_10GC", -#endif -}; - -/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -#if defined(CONFIG_TARGET_T2080QDS) -static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#endif - -static const char *t208xqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = t208xqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct t208xqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void t208xqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if (muxval < 8) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t208xqds_mdio_reset(struct mii_dev *bus) -{ - struct t208xqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t208xqds_mdio_init(char *realbusname, u8 muxval) -{ - struct t208xqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate t208xqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate t208xqds private data\n"); - free(bus); - return -1; - } - - bus->read = t208xqds_mdio_read; - bus->write = t208xqds_mdio_write; - bus->reset = t208xqds_mdio_reset; - strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - int phy; - char alias[20]; - char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; - char buf[32] = "serdes-1,"; - struct fixed_link f_link; - int media_type = 0; - const char *phyconn; - int off; - - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_TARGET_T2080QDS - serdes_corenet_t *srds_regs = - (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; - u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); -#endif - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - phy = fm_info_get_phy_address(port); - switch (port) { -#if defined(CONFIG_TARGET_T2080QDS) - case FM1_DTSEC1: - if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx1"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIH_KX_MASK); - break; - } - case FM1_DTSEC2: - if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx2"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIG_KX_MASK); - break; - } - case FM1_DTSEC9: - if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx9"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIE_KX_MASK); - break; - } - case FM1_DTSEC10: - if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx10"); - fdt_status_okay_by_alias(fdt, - "1gkx_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIF_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (mdio_mux[port] == EMI1_SLOT3) { - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - } - break; - case FM1_DTSEC5: - if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx5"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); - strcat(buf, "lane-g,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIC_KX_MASK); - break; - } - case FM1_DTSEC6: - if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx6"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); - strcat(buf, "lane-h,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIID_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT1) { - sprintf(alias, "phy_sgmii_s1_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot1"); - } else if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } - break; -#endif - default: - break; - } - if (media_type) { - /* set property for 1000BASE-KX in dtb */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, "lane-instance", buf); - } - - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - switch (srds_s1) { - case 0x66: /* 10GBase-R interface */ - case 0x6b: - case 0x6c: - case 0x6d: - case 0x71: - /* - * Check hwconfig to see what is the media type, there - * are two types, fiber or copper, fix the dtb - * accordingly. - */ - switch (port) { - case FM1_10GEC1: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { - /* it's MAC9 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi9"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC2: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { - /* it's MAC10 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi10"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC3: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { - /* it's MAC1 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi1"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC4: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { - /* it's MAC2 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi2"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - default: - return; - } - - if (!media_type) { - phyconn = fdt_getprop(fdt, offset, - "phy-connection-type", - NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", - port); - } else { - /* fixed-link for 10GBase-R fiber cable */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", - &f_link, sizeof(f_link)); - } - } else { - /* set property for copper cable */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, - "lane-instance", buf); - } - break; - default: - break; - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -/* - * This function reads RCW to check if Serdes1{A:H} is configured - * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (srds_s1) { -#if defined(CONFIG_TARGET_T2080QDS) - case 0x51: - case 0x5f: - case 0x65: - case 0x6b: - case 0x71: - lane_to_slot[5] = 2; - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - case 0xd3: - case 0xd9: - case 0xcb: - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xda: - lane_to_slot[4] = 3; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; -#endif - default: - break; - } -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); -#if defined(CONFIG_TARGET_T2080QDS) - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); -#endif - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == - FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - else - fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x1b: - case 0x1c: - case 0x95: - case 0xa2: - case 0x94: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x50: - case 0x51: - case 0x5e: - case 0x5f: - case 0x64: - case 0x65: - /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x66: - case 0x67: - /* - * 10GBase-R does not need a PHY to work, but to avoid U-Boot - * use default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to 10GBase-R - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the 10GBase-R MAC, which will cause - * error. - */ - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - break; - case 0x6a: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0x6c: - case 0x6d: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x70: - case 0x71: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa4: - case 0x96: - case 0x8a: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; -#if defined(CONFIG_TARGET_T2080QDS) - case 0xd9: - case 0xd3: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; -#endif - case 0xf2: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4 || FM1_DTSEC10) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if (srds_s1 == 0x51) { - lane = serdes_get_first_lane(FSL_SRDS_1, - XAUI_FM1_MAC9 + idx); - } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { - lane = serdes_get_first_lane(FSL_SRDS_1, - HIGIG_FM1_MAC9 + idx); - } else { - if (i == FM1_10GEC1 || i == FM1_10GEC2) - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC9 + idx); - else - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC1 + idx); - } - - if (lane < 0) - break; - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - - if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || - (srds_s1 == 0x6a) || (srds_s1 == 0x70) || - (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || - (srds_s1 == 0x71)) { - /* As 10GBase-R is in cage intead of a slot, so - * ensure doesn't disable the corresponding port - */ - break; - } - - slot = lane_to_slot[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t208xqds/t208xqds.c b/board/nxp/t208xqds/t208xqds.c index 5e71da0e163..329cf59793f 100644 --- a/board/nxp/t208xqds/t208xqds.c +++ b/board/nxp/t208xqds/t208xqds.c @@ -419,7 +419,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t208xqds/t208xqds.h b/board/nxp/t208xqds/t208xqds.h index 50ebb6f6f98..4086f8c010a 100644 --- a/board/nxp/t208xqds/t208xqds.h +++ b/board/nxp/t208xqds/t208xqds.h @@ -6,7 +6,6 @@ #ifndef __CORENET_DS_H__ #define __CORENET_DS_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xrdb/eth_t208xrdb.c b/board/nxp/t208xrdb/eth_t208xrdb.c index 5223eccb280..c9e415bc446 100644 --- a/board/nxp/t208xrdb/eth_t208xrdb.c +++ b/board/nxp/t208xrdb/eth_t208xrdb.c @@ -93,8 +93,3 @@ void fdt_fixup_board_phy(void *fdt) printf("Unable to rename node ethernet-phy@1: %s\n", fdt_strerror(ret)); } - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} diff --git a/board/nxp/t208xrdb/t208xrdb.c b/board/nxp/t208xrdb/t208xrdb.c index d93edf007ad..d47ec91e7d0 100644 --- a/board/nxp/t208xrdb/t208xrdb.c +++ b/board/nxp/t208xrdb/t208xrdb.c @@ -160,7 +160,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_board_fman_ethernet(blob); - fdt_fixup_board_enet(blob); fdt_fixup_board_phy(blob); #endif diff --git a/board/nxp/t208xrdb/t208xrdb.h b/board/nxp/t208xrdb/t208xrdb.h index 26998898e82..e800270a0e2 100644 --- a/board/nxp/t208xrdb/t208xrdb.h +++ b/board/nxp/t208xrdb/t208xrdb.h @@ -10,7 +10,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); void fdt_fixup_board_phy(void *blob); diff --git a/board/nxp/t4rdb/Makefile b/board/nxp/t4rdb/Makefile index 8d94faaba1c..6d9b8df2fc1 100644 --- a/board/nxp/t4rdb/Makefile +++ b/board/nxp/t4rdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o diff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c deleted file mode 100644 index e7646365d7d..00000000000 --- a/board/nxp/t4rdb/eth.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Chunhe Lan - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" -#include "t4rdb.h" - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { - /* SGMII */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); - } else { - puts("Invalid SerDes1 protocol for T4240RDB\n"); - } - - fm_disable_port(FM1_DTSEC5); - fm_disable_port(FM1_DTSEC6); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - -#if (CFG_SYS_NUM_FMAN == 2) - if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && 10GBase-R */ - fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); - } else { - puts("Invalid SerDes2 protocol for T4240RDB\n"); - } - - fm_disable_port(FM2_DTSEC5); - fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } -#endif /* CFG_SYS_NUM_FMAN */ - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t4rdb/t4240rdb.c b/board/nxp/t4rdb/t4240rdb.c index 5cacfd27380..11e2c0f78b7 100644 --- a/board/nxp/t4rdb/t4240rdb.c +++ b/board/nxp/t4rdb/t4240rdb.c @@ -128,7 +128,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t4rdb/t4rdb.h b/board/nxp/t4rdb/t4rdb.h index bb3ce216d7d..9ec190c03cb 100644 --- a/board/nxp/t4rdb/t4rdb.h +++ b/board/nxp/t4rdb/t4rdb.h @@ -14,7 +14,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 889de8ea9ac..16902d216f6 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -45,9 +45,13 @@ endif endif ifdef CONFIG_RCAR_GEN5 +ifdef CONFIG_RCAR_64_RSIP +obj-y += gen5-cm33.o +else obj-y += gen5-common.o endif endif +endif endif endif diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c new file mode 100644 index 00000000000..e07db9817f2 --- /dev/null +++ b/board/renesas/common/gen5-cm33.c @@ -0,0 +1,1409 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gen5-cm33.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +#define PKC_PROT_LOCK 0xa5a5a500 +#define PKC_PROT_UNLOCK 0xa5a5a501 + +#define RSIP_BASE 0xe0000000 +#define RSIP_NVIC_ISER_00 (RSIP_BASE + 0xe100) +#define RSIP_NVIC_ISER_00_SETENA_INTIWDTA0 BIT(16) +#define RSIP_NVIC_ICER_00 (RSIP_BASE + 0xe180) +#define RSIP_NVIC_ICER_01 (RSIP_BASE + 0xe184) +#define RSIP_NVIC_ICER_02 (RSIP_BASE + 0xe188) +#define RSIP_NVIC_ICER_03 (RSIP_BASE + 0xe18c) +#define RSIP_NVIC_ICER_04 (RSIP_BASE + 0xe190) +#define RSIP_NVIC_ICER_05 (RSIP_BASE + 0xe194) +#define RSIP_NVIC_ICER_06 (RSIP_BASE + 0xe198) +#define RSIP_NVIC_ICER_07 (RSIP_BASE + 0xe19c) +#define RSIP_NVIC_ICER_08 (RSIP_BASE + 0xe1a0) +#define RSIP_NVIC_ICER_09 (RSIP_BASE + 0xe1a4) +#define RSIP_NVIC_ICER_10 (RSIP_BASE + 0xe1a8) +#define RSIP_NVIC_ICER_11 (RSIP_BASE + 0xe1ac) +#define RSIP_NVIC_ICER_12 (RSIP_BASE + 0xe1b0) +#define RSIP_NVIC_ICER_13 (RSIP_BASE + 0xe1b4) +#define RSIP_NVIC_ICER_14 (RSIP_BASE + 0xe1b8) +#define RSIP_NVIC_ICER_15 (RSIP_BASE + 0xe1bc) +#define RSIP_SHCSR (RSIP_BASE + 0xed24) +#define RSIP_SHCSR_USGFAULTENA BIT(18) +#define RSIP_SHCSR_BUSFAULTENA BIT(17) +#define RSIP_SHCSR_MEMFAULTENA BIT(16) + +#define RSIP_CTL_BASE 0x5fffd000 +#define RSIP_CTL_CFG4 (RSIP_CTL_BASE + 0xb0) +#define RSIP_CTL_CFG4_OPWDEN BIT(3) +#define RSIP_CTL_CFG4_OPWDVAC BIT(5) +#define RSIP_CTL_ESICREMAP0 (RSIP_CTL_BASE + 0x70) +#define RSIP_CTL_PROT0PCMD (RSIP_CTL_BASE + 0x840) +#define RSIP_CTL_PROT0PCMD_WREN 0xa5 +#define RSIP_CTL_PROT0PS (RSIP_CTL_BASE + 0x844) +#define RSIP_CTL_PROT0PS_ERR BIT(0) + +#define SYSSS_BASE 0xc1320000 +#define SYSSS_MODE1 (SYSSS_BASE + 0x1010) +#define SYSSS_MODE1_MASK GENMASK(11, 0) +#define SYSSS_MODE1_BAUDRATE_MASK GENMASK(10, 9) +#define SYSSS_MODE1_BAUDRATE_921600 1 +#define SYSSS_MODE1_BAUDRATE_1843200 2 +#define SYSSS_MODE1_BAUDRATE_3250000 3 +#define SYSSS_MODE1_BOOTMODE_MASK GENMASK(20, 18) +#define SYSSS_MODE1_BOOTMODE_HF_DMA 2 +#define SYSSS_MODE1_BOOTMODE_QSPI 4 +#define SYSSS_MODE1_BOOTMODE_UFS 6 + +#define CLK_CONTROL_TOP_BASE 0xc6480000 +#define CLK_CONTROL_SCP_BASE 0xc1330000 +#define CLK_CONTROL_PERE_BASE 0xc08f0000 + +#define CLK_CONTROL_PLL01_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1108) +#define CLK_CONTROL_PLL01_1_CR0 (CLK_CONTROL_TOP_BASE + 0x1114) +#define CLK_CONTROL_PLL02_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1120) +#define CLK_CONTROL_PLL02_1_CR0 (CLK_CONTROL_TOP_BASE + 0x112c) +#define CLK_CONTROL_PLL02_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1138) +#define CLK_CONTROL_PLL02_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1144) +#define CLK_CONTROL_PLL02_4_CR0 (CLK_CONTROL_TOP_BASE + 0x1150) +#define CLK_CONTROL_PLL02_5_CR0 (CLK_CONTROL_TOP_BASE + 0x115c) +#define CLK_CONTROL_PLL02_6_CR0 (CLK_CONTROL_TOP_BASE + 0x1168) +#define CLK_CONTROL_PLL02_7_CR0 (CLK_CONTROL_TOP_BASE + 0x1174) +#define CLK_CONTROL_PLL03_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1180) +#define CLK_CONTROL_PLL03_1_CR0 (CLK_CONTROL_TOP_BASE + 0x118c) +#define CLK_CONTROL_PLL03_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1198) +#define CLK_CONTROL_PLL03_3_CR0 (CLK_CONTROL_TOP_BASE + 0x11a4) +#define CLK_CONTROL_PLL06_CR0 (CLK_CONTROL_TOP_BASE + 0x11c8) +#define CLK_CONTROL_PLL07_CR0 (CLK_CONTROL_TOP_BASE + 0x11d4) +#define CLK_CONTROL_PLL12_CR0 (CLK_CONTROL_TOP_BASE + 0x121c) +#define CLK_CONTROL_PLL13_CR0 (CLK_CONTROL_SCP_BASE + 0x1228) +#define CLK_CONTROL_PLL14_CR0 (CLK_CONTROL_TOP_BASE + 0x1234) +#define CLK_CONTROL_PLL15_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1240) +#define CLK_CONTROL_PLL15_1_CR0 (CLK_CONTROL_TOP_BASE + 0x124c) +#define CLK_CONTROL_PLL15_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1258) +#define CLK_CONTROL_PLL15_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1264) +#define CLK_CONTROL_PLL01_0_CR1 (CLK_CONTROL_TOP_BASE + 0x110c) +#define CLK_CONTROL_PLL01_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1118) +#define CLK_CONTROL_PLL02_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1124) +#define CLK_CONTROL_PLL02_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1130) +#define CLK_CONTROL_PLL02_2_CR1 (CLK_CONTROL_TOP_BASE + 0x113c) +#define CLK_CONTROL_PLL02_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1148) +#define CLK_CONTROL_PLL02_4_CR1 (CLK_CONTROL_TOP_BASE + 0x1154) +#define CLK_CONTROL_PLL02_5_CR1 (CLK_CONTROL_TOP_BASE + 0x1160) +#define CLK_CONTROL_PLL02_6_CR1 (CLK_CONTROL_TOP_BASE + 0x116c) +#define CLK_CONTROL_PLL02_7_CR1 (CLK_CONTROL_TOP_BASE + 0x1178) +#define CLK_CONTROL_PLL03_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1184) +#define CLK_CONTROL_PLL03_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1190) +#define CLK_CONTROL_PLL03_2_CR1 (CLK_CONTROL_TOP_BASE + 0x119c) +#define CLK_CONTROL_PLL03_3_CR1 (CLK_CONTROL_TOP_BASE + 0x11a8) +#define CLK_CONTROL_PLL06_CR1 (CLK_CONTROL_TOP_BASE + 0x11cc) +#define CLK_CONTROL_PLL07_CR1 (CLK_CONTROL_TOP_BASE + 0x11d8) +#define CLK_CONTROL_PLL12_CR1 (CLK_CONTROL_TOP_BASE + 0x1220) +#define CLK_CONTROL_PLL13_CR1 (CLK_CONTROL_SCP_BASE + 0x122c) +#define CLK_CONTROL_PLL14_CR1 (CLK_CONTROL_TOP_BASE + 0x1238) +#define CLK_CONTROL_PLL15_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1244) +#define CLK_CONTROL_PLL15_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1250) +#define CLK_CONTROL_PLL15_2_CR1 (CLK_CONTROL_TOP_BASE + 0x125c) +#define CLK_CONTROL_PLL15_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1268) +#define CLK_CONTROL_PLL01_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1110) +#define CLK_CONTROL_PLL01_1_CR2 (CLK_CONTROL_TOP_BASE + 0x111c) +#define CLK_CONTROL_PLL02_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1128) +#define CLK_CONTROL_PLL02_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1134) +#define CLK_CONTROL_PLL02_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1140) +#define CLK_CONTROL_PLL02_3_CR2 (CLK_CONTROL_TOP_BASE + 0x114c) +#define CLK_CONTROL_PLL02_4_CR2 (CLK_CONTROL_TOP_BASE + 0x1158) +#define CLK_CONTROL_PLL02_5_CR2 (CLK_CONTROL_TOP_BASE + 0x1164) +#define CLK_CONTROL_PLL02_6_CR2 (CLK_CONTROL_TOP_BASE + 0x1170) +#define CLK_CONTROL_PLL02_7_CR2 (CLK_CONTROL_TOP_BASE + 0x117c) +#define CLK_CONTROL_PLL03_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1188) +#define CLK_CONTROL_PLL03_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1194) +#define CLK_CONTROL_PLL03_2_CR2 (CLK_CONTROL_TOP_BASE + 0x11a0) +#define CLK_CONTROL_PLL03_3_CR2 (CLK_CONTROL_TOP_BASE + 0x11ac) +#define CLK_CONTROL_PLL06_CR2 (CLK_CONTROL_TOP_BASE + 0x11d0) +#define CLK_CONTROL_PLL07_CR2 (CLK_CONTROL_TOP_BASE + 0x11dc) +#define CLK_CONTROL_PLL12_CR2 (CLK_CONTROL_TOP_BASE + 0x1224) +#define CLK_CONTROL_PLL13_CR2 (CLK_CONTROL_SCP_BASE + 0x1230) +#define CLK_CONTROL_PLL14_CR2 (CLK_CONTROL_TOP_BASE + 0x123c) +#define CLK_CONTROL_PLL15_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1248) +#define CLK_CONTROL_PLL15_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1254) +#define CLK_CONTROL_PLL15_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1260) +#define CLK_CONTROL_PLL15_3_CR2 (CLK_CONTROL_TOP_BASE + 0x126c) +#define CLK_CONTROL_PLL01_0_SCR (CLK_CONTROL_TOP_BASE + 0x1270) +#define CLK_CONTROL_PLL01_1_SCR (CLK_CONTROL_TOP_BASE + 0x1278) +#define CLK_CONTROL_PLL02_0_SCR (CLK_CONTROL_TOP_BASE + 0x1280) +#define CLK_CONTROL_PLL02_1_SCR (CLK_CONTROL_TOP_BASE + 0x1288) +#define CLK_CONTROL_PLL02_2_SCR (CLK_CONTROL_TOP_BASE + 0x1290) +#define CLK_CONTROL_PLL02_3_SCR (CLK_CONTROL_TOP_BASE + 0x1298) +#define CLK_CONTROL_PLL02_4_SCR (CLK_CONTROL_TOP_BASE + 0x12a0) +#define CLK_CONTROL_PLL02_5_SCR (CLK_CONTROL_TOP_BASE + 0x12a8) +#define CLK_CONTROL_PLL02_6_SCR (CLK_CONTROL_TOP_BASE + 0x12b0) +#define CLK_CONTROL_PLL02_7_SCR (CLK_CONTROL_TOP_BASE + 0x12b8) +#define CLK_CONTROL_PLL03_0_SCR (CLK_CONTROL_TOP_BASE + 0x12c0) +#define CLK_CONTROL_PLL03_1_SCR (CLK_CONTROL_TOP_BASE + 0x12c8) +#define CLK_CONTROL_PLL03_2_SCR (CLK_CONTROL_TOP_BASE + 0x12d0) +#define CLK_CONTROL_PLL03_3_SCR (CLK_CONTROL_TOP_BASE + 0x12d8) +#define CLK_CONTROL_PLL06_SCR (CLK_CONTROL_TOP_BASE + 0x12f0) +#define CLK_CONTROL_PLL07_SCR (CLK_CONTROL_TOP_BASE + 0x12f8) +#define CLK_CONTROL_PLL12_SCR (CLK_CONTROL_TOP_BASE + 0x1328) +#define CLK_CONTROL_PLL13_SCR (CLK_CONTROL_SCP_BASE + 0x1330) +#define CLK_CONTROL_PLL14_SCR (CLK_CONTROL_TOP_BASE + 0x1338) +#define CLK_CONTROL_PLL15_0_SCR (CLK_CONTROL_TOP_BASE + 0x1340) +#define CLK_CONTROL_PLL15_1_SCR (CLK_CONTROL_TOP_BASE + 0x1348) +#define CLK_CONTROL_PLL15_2_SCR (CLK_CONTROL_TOP_BASE + 0x1350) +#define CLK_CONTROL_PLL15_3_SCR (CLK_CONTROL_TOP_BASE + 0x1358) +#define CLK_CONTROL_PLL01_0_DCR (CLK_CONTROL_TOP_BASE + 0x1274) +#define CLK_CONTROL_PLL01_1_DCR (CLK_CONTROL_TOP_BASE + 0x127c) +#define CLK_CONTROL_PLL02_0_DCR (CLK_CONTROL_TOP_BASE + 0x1284) +#define CLK_CONTROL_PLL02_1_DCR (CLK_CONTROL_TOP_BASE + 0x128c) +#define CLK_CONTROL_PLL02_2_DCR (CLK_CONTROL_TOP_BASE + 0x1294) +#define CLK_CONTROL_PLL02_3_DCR (CLK_CONTROL_TOP_BASE + 0x129c) +#define CLK_CONTROL_PLL02_4_DCR (CLK_CONTROL_TOP_BASE + 0x12a4) +#define CLK_CONTROL_PLL02_5_DCR (CLK_CONTROL_TOP_BASE + 0x12ac) +#define CLK_CONTROL_PLL02_6_DCR (CLK_CONTROL_TOP_BASE + 0x12b4) +#define CLK_CONTROL_PLL02_7_DCR (CLK_CONTROL_TOP_BASE + 0x12bc) +#define CLK_CONTROL_PLL03_0_DCR (CLK_CONTROL_TOP_BASE + 0x12c4) +#define CLK_CONTROL_PLL03_1_DCR (CLK_CONTROL_TOP_BASE + 0x12cc) +#define CLK_CONTROL_PLL03_2_DCR (CLK_CONTROL_TOP_BASE + 0x12d4) +#define CLK_CONTROL_PLL03_3_DCR (CLK_CONTROL_TOP_BASE + 0x12dc) +#define CLK_CONTROL_PLL06_DCR (CLK_CONTROL_TOP_BASE + 0x12f4) +#define CLK_CONTROL_PLL07_DCR (CLK_CONTROL_TOP_BASE + 0x12fc) +#define CLK_CONTROL_PLL12_DCR (CLK_CONTROL_TOP_BASE + 0x132c) +#define CLK_CONTROL_PLL13_DCR (CLK_CONTROL_SCP_BASE + 0x1334) +#define CLK_CONTROL_PLL14_DCR (CLK_CONTROL_TOP_BASE + 0x133c) +#define CLK_CONTROL_PLL15_0_DCR (CLK_CONTROL_TOP_BASE + 0x1344) +#define CLK_CONTROL_PLL15_1_DCR (CLK_CONTROL_TOP_BASE + 0x134c) +#define CLK_CONTROL_PLL15_2_DCR (CLK_CONTROL_TOP_BASE + 0x1354) +#define CLK_CONTROL_PLL15_3_DCR (CLK_CONTROL_TOP_BASE + 0x135c) +#define CLK_CONTROL_RPCCKCR (CLK_CONTROL_PERE_BASE + 0x1030) +#define CLK_CONTROL_RPCCKCR_CKSTP1 BIT(8) +#define CLK_CONTROL_RPCCKCR_RPCFC_MASK GENMASK(4, 0) +#define CLK_CONTROL_PROT_REG_MASK 0xffff +#define CLK_CONTROL_PROT_REG 0x1370 + +#define CLK_CONTROL_PLL_CR2_PLLCLKSTAB BIT(31) +#define CLK_CONTROL_PLL_CR2_PLLDISTRG BIT(29) +#define CLK_CONTROL_PLL_CR2_PLLENTRG BIT(28) +#define CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC BIT(0) +#define CLK_CONTROL_PLL_SCR_SELACT_MASK BIT(16) +#define CLK_CONTROL_PLL_DCR_PLLDIVSYNC BIT(16) + +/** + * sysss_read_modemr() - Read MODE Register 1 + * @return: MD[11:0] pin state + */ +static u32 sysss_read_modemr(void) +{ + return readl(SYSSS_MODE1) & SYSSS_MODE1_MASK; +} + +/** + * clk_control_poll_cr2() - Poll CR2 until PLL is stable + * @cr2: PLL CR2 register address + */ +static void clk_control_poll_cr2(const u32 cr2) +{ + u32 val; + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB) + break; + } +} + +/** + * clk_control_write_cr() - Write protected clock controller register + * @reg: Register address + * @val: Value to be written + */ +static void clk_control_write_cr(const u32 reg, const u32 val) +{ + const u32 protreg = (reg & ~CLK_CONTROL_PROT_REG_MASK) | CLK_CONTROL_PROT_REG; + + writel(PKC_PROT_UNLOCK, protreg); + writel(val, reg); + writel(PKC_PROT_LOCK, protreg); +} + +/** + * clk_control_write_and_poll_dcr() - Write and poll DCR + * @dcr: DCR register address + * @val: Value to be written + */ +static void clk_control_write_and_poll_dcr(const u32 dcr, const u32 val) +{ + u32 tmp; + + clk_control_write_cr(dcr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + tmp = readl(dcr); + if (tmp & CLK_CONTROL_PLL_DCR_PLLDIVSYNC) + break; + } +} + +/** + * clk_control_switch_from_iosc_to_pll() - Switch clock from internal oscillator to PLL + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_iosc_to_pll(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from internal oscillator to PLL. */ + val = readl(scr); + val &= ~CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC; + clk_control_write_cr(scr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (!(val & CLK_CONTROL_PLL_SCR_SELACT_MASK)) + break; + } +} + +/** + * clk_control_switch_from_pll_to_iosc() - Switch clock from PLL to internal oscillator + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_pll_to_iosc(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from PLL to internal oscillator. */ + clk_control_write_cr(scr, CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (val & CLK_CONTROL_PLL_SCR_SELACT_MASK) + break; + } +} + +/** + * clk_control_set_pll_freq() - Set PLL frequency + * @cr0: PLL CR0 register address + * @cr1: PLL CR1 register address + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + * @dcr: PLL DCR register address + * @cr0_val: PLL CR0 register value + * @cr1_val: PLL CR1 register value + * @dcr_val: PLL DCR register value + */ +static void clk_control_set_pll_freq(const u32 cr0, const u32 cr1, const u32 cr2, + const u32 scr, const u32 dcr, const u32 cr0_val, + const u32 cr1_val, const u32 dcr_val) +{ + u32 val; + + clk_control_switch_from_pll_to_iosc(cr2, scr); + + /* Disable PLL trigger and wait until it unlocks */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLDISTRG); + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (!(val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB)) + break; + } + + clk_control_write_cr(cr0, cr0_val); + clk_control_write_cr(cr1, cr1_val); + clk_control_write_cr(dcr, dcr_val); + + /* Enable PLL */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLENTRG); +} + +/** + * clk_control_set_pll() - Load configuration into PLLs + */ +static void clk_control_set_pll(void) +{ + /* Switch PLLs to internal oscillator and configure dividers. */ + clk_control_set_pll_freq(CLK_CONTROL_PLL01_0_CR0, CLK_CONTROL_PLL01_0_CR1, + CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR, + CLK_CONTROL_PLL01_0_DCR, 0x06500000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL01_1_CR0, CLK_CONTROL_PLL01_1_CR1, + CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR, + CLK_CONTROL_PLL01_1_DCR, 0x04c00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL02_0_CR0, CLK_CONTROL_PLL02_0_CR1, + CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR, + CLK_CONTROL_PLL02_0_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_1_CR0, CLK_CONTROL_PLL02_1_CR1, + CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR, + CLK_CONTROL_PLL02_1_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_2_CR0, CLK_CONTROL_PLL02_2_CR1, + CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR, + CLK_CONTROL_PLL02_2_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_3_CR0, CLK_CONTROL_PLL02_3_CR1, + CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR, + CLK_CONTROL_PLL02_3_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_4_CR0, CLK_CONTROL_PLL02_4_CR1, + CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR, + CLK_CONTROL_PLL02_4_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_5_CR0, CLK_CONTROL_PLL02_5_CR1, + CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR, + CLK_CONTROL_PLL02_5_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_6_CR0, CLK_CONTROL_PLL02_6_CR1, + CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR, + CLK_CONTROL_PLL02_6_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_7_CR0, CLK_CONTROL_PLL02_7_CR1, + CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR, + CLK_CONTROL_PLL02_7_DCR, 0x08900000, 0x04000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL03_0_CR0, CLK_CONTROL_PLL03_0_CR1, + CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR, + CLK_CONTROL_PLL03_0_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_1_CR0, CLK_CONTROL_PLL03_1_CR1, + CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR, + CLK_CONTROL_PLL03_1_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_2_CR0, CLK_CONTROL_PLL03_2_CR1, + CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR, + CLK_CONTROL_PLL03_2_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_3_CR0, CLK_CONTROL_PLL03_3_CR1, + CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR, + CLK_CONTROL_PLL03_3_DCR, 0x05f00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL06_CR0, CLK_CONTROL_PLL06_CR1, + CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR, + CLK_CONTROL_PLL06_DCR, 0x0a700000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL07_CR0, CLK_CONTROL_PLL07_CR1, + CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR, + CLK_CONTROL_PLL07_DCR, 0x09500000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL12_CR0, CLK_CONTROL_PLL12_CR1, + CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR, + CLK_CONTROL_PLL12_DCR, 0x0a400000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL13_CR0, CLK_CONTROL_PLL13_CR1, + CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR, + CLK_CONTROL_PLL13_DCR, 0x08f00000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL14_CR0, CLK_CONTROL_PLL14_CR1, + CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR, + CLK_CONTROL_PLL14_DCR, 0x04700000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL15_0_CR0, CLK_CONTROL_PLL15_0_CR1, + CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR, + CLK_CONTROL_PLL15_0_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_1_CR0, CLK_CONTROL_PLL15_1_CR1, + CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR, + CLK_CONTROL_PLL15_1_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_2_CR0, CLK_CONTROL_PLL15_2_CR1, + CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR, + CLK_CONTROL_PLL15_2_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_3_CR0, CLK_CONTROL_PLL15_3_CR1, + CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR, + CLK_CONTROL_PLL15_3_DCR, 0x07700000, 0x04000000, 0x18); + + /* Switch PLLs back and wait for them to stabilize. */ + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR); + + /* Write second-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x10); + + udelay(25); + + /* Write third-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); /* 1/2 */ + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x00); + + udelay(25); +} + +#define MDLC_PERW_BASE 0xc05d0000 +#define MDLC_PERE_BASE 0xc08f0000 +#define MDLC_HSCN_BASE 0xc9c90000 +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MDLC_RT_BASE 0xb9440000 +#define MDLC_SCP_BASE 0xc1330000 + +#define MDLC_SCP_MSRES02 (MDLC_SCP_BASE + 0x908) +#define MDLC_SCP_MSRESS02 (MDLC_SCP_BASE + 0x968) +#define MDLC_SCP_MSRES02_SCP_MASK GENMASK(1, 0) +#define MDLC_SCP_PKCPROT1 (MDLC_SCP_BASE + 0xcf4) + +#define MDLC_PERW_MSRES05 (MDLC_PERW_BASE + 0x914) +#define MDLC_PERW_MSRESS05 (MDLC_PERW_BASE + 0x974) +#define MDLC_PERW_MSRES05_HSCIF0_MASK GENMASK(9, 8) +#define MDLC_PERW_MSRES05_HSCIF1_MASK GENMASK(11, 10) +#define MDLC_MSRESS_STANDBY 0 +#define MDLC_MSRESS_RESET 1 +#define MDLC_MSRESS_STOP 2 +#define MDLC_MSRESS_RUN 3 +#define MDLC_PERW_PKCPROT1 (MDLC_PERW_BASE + 0xcf4) + +#define MDLC_MPG_GATING 0 +#define MDLC_MPG_RESET 1 +#define MDLC_MPG_RUN 3 + +#define MDLC_PERE_MPIER (MDLC_PERE_BASE + 0x110) +#define MDLC_PERE_MPIMR (MDLC_PERE_BASE + 0x120) +#define MDLC_PERE_MPDG00 (MDLC_PERE_BASE + 0x200) +#define MDLC_PERE_MPDG01 (MDLC_PERE_BASE + 0x204) +#define MDLC_PERE_MPDGS00 (MDLC_PERE_BASE + 0x300) +#define MDLC_PERE_MPDGS01 (MDLC_PERE_BASE + 0x304) +#define MDLC_PERE_MSRES06 (MDLC_PERE_BASE + 0x918) +#define MDLC_PERE_MSRESS06 (MDLC_PERE_BASE + 0x978) +#define MDLC_PERE_PKCPROT0 (MDLC_PERE_BASE + 0xcf0) +#define MDLC_PERE_PKCPROT1 (MDLC_PERE_BASE + 0xcf4) +#define MDLC_PERE_MSRES06_UFS0_MASK GENMASK(1, 0) +#define MDLC_PERE_MSRES06_UFS1_MASK GENMASK(3, 2) + +#define MDLC_HSCN_MPIER (MDLC_HSCN_BASE + 0x110) +#define MDLC_HSCN_MPIMR (MDLC_HSCN_BASE + 0x120) +#define MDLC_HSCN_MPDG00 (MDLC_HSCN_BASE + 0x200) +#define MDLC_HSCN_MPDG01 (MDLC_HSCN_BASE + 0x204) +#define MDLC_HSCN_MPDG02 (MDLC_HSCN_BASE + 0x208) +#define MDLC_HSCN_MPDG03 (MDLC_HSCN_BASE + 0x20c) +#define MDLC_HSCN_MPDG04 (MDLC_HSCN_BASE + 0x210) +#define MDLC_HSCN_MPDG05 (MDLC_HSCN_BASE + 0x214) +#define MDLC_HSCN_MPDG06 (MDLC_HSCN_BASE + 0x218) +#define MDLC_HSCN_MPDGS00 (MDLC_HSCN_BASE + 0x300) +#define MDLC_HSCN_MPDGS01 (MDLC_HSCN_BASE + 0x304) +#define MDLC_HSCN_MPDGS02 (MDLC_HSCN_BASE + 0x308) +#define MDLC_HSCN_MPDGS03 (MDLC_HSCN_BASE + 0x30c) +#define MDLC_HSCN_MPDGS04 (MDLC_HSCN_BASE + 0x310) +#define MDLC_HSCN_MPDGS05 (MDLC_HSCN_BASE + 0x314) +#define MDLC_HSCN_MPDGS06 (MDLC_HSCN_BASE + 0x318) +#define MDLC_HSCN_PKCPROT0 (MDLC_HSCN_BASE + 0xcf0) + +#define MDLC_RT_MPIER (MDLC_RT_BASE + 0x110) +#define MDLC_RT_MPIMR (MDLC_RT_BASE + 0x120) +#define MDLC_RT_MPDG00 (MDLC_RT_BASE + 0x200) +#define MDLC_RT_MPDG01 (MDLC_RT_BASE + 0x204) +#define MDLC_RT_MPDG02 (MDLC_RT_BASE + 0x208) +#define MDLC_RT_MPDG03 (MDLC_RT_BASE + 0x20c) +#define MDLC_RT_MPDG04 (MDLC_RT_BASE + 0x210) +#define MDLC_RT_MPDG05 (MDLC_RT_BASE + 0x214) +#define MDLC_RT_MPDG06 (MDLC_RT_BASE + 0x218) +#define MDLC_RT_MPDG07 (MDLC_RT_BASE + 0x21c) +#define MDLC_RT_MPDG08 (MDLC_RT_BASE + 0x220) +#define MDLC_RT_MPDG09 (MDLC_RT_BASE + 0x224) +#define MDLC_RT_MPDG10 (MDLC_RT_BASE + 0x228) +#define MDLC_RT_MPDG11 (MDLC_RT_BASE + 0x22c) +#define MDLC_RT_MPDGS00 (MDLC_RT_BASE + 0x300) +#define MDLC_RT_MPDGS01 (MDLC_RT_BASE + 0x304) +#define MDLC_RT_MPDGS02 (MDLC_RT_BASE + 0x308) +#define MDLC_RT_MPDGS03 (MDLC_RT_BASE + 0x30c) +#define MDLC_RT_MPDGS04 (MDLC_RT_BASE + 0x310) +#define MDLC_RT_MPDGS05 (MDLC_RT_BASE + 0x314) +#define MDLC_RT_MPDGS06 (MDLC_RT_BASE + 0x318) +#define MDLC_RT_MPDGS07 (MDLC_RT_BASE + 0x31c) +#define MDLC_RT_MPDGS08 (MDLC_RT_BASE + 0x320) +#define MDLC_RT_MPDGS09 (MDLC_RT_BASE + 0x324) +#define MDLC_RT_MPDGS10 (MDLC_RT_BASE + 0x328) +#define MDLC_RT_MPDGS11 (MDLC_RT_BASE + 0x32c) +#define MDLC_RT_MSRES02 (MDLC_RT_BASE + 0x908) +#define MDLC_RT_MSRESS02 (MDLC_RT_BASE + 0x968) +#define MDLC_RT_MSRES03 (MDLC_RT_BASE + 0x90c) +#define MDLC_RT_MSRESS03 (MDLC_RT_BASE + 0x96c) +#define MDLC_RT_MSRES15 (MDLC_RT_BASE + 0x93c) +#define MDLC_RT_MSRESS15 (MDLC_RT_BASE + 0x99c) +#define MDLC_RT_MSRES15_INTAP0_MASK GENMASK(9, 8) +#define MDLC_RT_MSRES15_INTTP_MASK GENMASK(11, 10) +#define MDLC_RT_MSRES15_INTAP1_MASK GENMASK(13, 12) +#define MDLC_RT_PKCPROT0 (MDLC_RT_BASE + 0xcf0) +#define MDLC_RT_PKCPROT1 (MDLC_RT_BASE + 0xcf4) + +/* + * mdlc_wait_for_reset() - Wait for MDLC reset register and reset status register to align + * @res: Reset register + * @stat: Reset status register + */ +static void mdlc_wait_for_reset(const u32 res, const u32 stat) +{ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (; readl(res) != readl(stat);) + ; +} + +/** + * mdlc_write_msres() - Write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @val: Value to set in the masked out bits + */ +static void mdlc_write_msres(const u32 prot, const u32 res, const int val) +{ + writel(PKC_PROT_UNLOCK, prot); + writel(val, res); + writel(PKC_PROT_LOCK, prot); +} + +/** + * mdlc_rmw_msres() - Read-modify-write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void mdlc_rmw_msres(const u32 prot, const u32 res, const u32 mask, const int val) +{ + u32 reg; + + reg = readl(res); + reg &= ~mask; + reg |= field_prep(mask, val); + + mdlc_write_msres(prot, res, reg); +} + +/** + * mdlc_set_reset() - Set IP into reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_set_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_STANDBY); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_STANDBY || status == MDLC_MSRESS_RUN) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mdlc_release_reset() - Release IP from reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_release_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STANDBY) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_RESET || status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RUN); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mldc_mpg_module_run() - Release MPG module from gating + * @prot: Protect register + * @res: Reset register + * @stat: Reset status register + * @ier: Interrupt enable register + * @imr: Interrupt mask register + */ +static void mldc_mpg_module_run(const u32 prot, const u32 res, const u32 stat, + const u32 ier, const u32 imr) +{ + u32 val; + + mdlc_wait_for_reset(res, stat); + + val = readl(stat); + if (val == MDLC_MPG_GATING) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RESET); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } + + if (val == MDLC_MPG_RESET || val == MDLC_MPG_RUN) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RUN); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } +} + +/** + * mdlc_mpg_start() - Configure MPG module state + */ +static void mdlc_mpg_start(void) +{ + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG01, MDLC_PERE_MPDGS01, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG00, MDLC_PERE_MPDGS00, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG11, MDLC_RT_MPDGS11, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG10, MDLC_RT_MPDGS10, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG09, MDLC_RT_MPDGS09, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG08, MDLC_RT_MPDGS08, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG07, MDLC_RT_MPDGS07, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG06, MDLC_RT_MPDGS06, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG05, MDLC_RT_MPDGS05, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG04, MDLC_RT_MPDGS04, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG03, MDLC_RT_MPDGS03, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG02, MDLC_RT_MPDGS02, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG01, MDLC_RT_MPDGS01, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG00, MDLC_RT_MPDGS00, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + /* Power on RSwitch */ + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG06, MDLC_HSCN_MPDGS06, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG05, MDLC_HSCN_MPDGS05, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG04, MDLC_HSCN_MPDGS04, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG03, MDLC_HSCN_MPDGS03, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG02, MDLC_HSCN_MPDGS02, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG01, MDLC_HSCN_MPDGS01, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG00, MDLC_HSCN_MPDGS00, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); +} + +#define PFC_GP2_BASE 0xc1081000 +#define PFC_GP2_GPSR (PFC_GP2_BASE + 0x40) +#define PFC_GP2_IOINTSEL (PFC_GP2_BASE + 0x110) +#define PFC_GP2_INOUTSEL (PFC_GP2_BASE + 0x114) +#define PFC_GP2_OUTDT (PFC_GP2_BASE + 0x118) +#define PFC_GP2_POSNEG (PFC_GP2_BASE + 0x1a0) +#define PFC_GP2_PIN_AVS0 BIT(21) +#define PFC_GP2_PIN_AVS1 BIT(22) +#define PFC_GP2_PIN_AVS \ + (PFC_GP2_PIN_AVS0 | PFC_GP2_PIN_AVS1) + +#define PFC_GP3_BASE 0xc0800000 +#define PFC_GP3_PULLEN (PFC_GP3_BASE + 0xc0) +#define PFC_GP3_PUDSEL (PFC_GP3_BASE + 0xc4) + +#define PFC_GP5_BASE 0xc0400000 +#define PFC_GROUP_ADDR_MASK GENMASK(31, 11) +#define PFC_GP5_GPSR (PFC_GP5_BASE + 0x40) +#define PFC_GP5_ALTSEL0 (PFC_GP5_BASE + 0x60) +#define PFC_GP5_ALTSEL1 (PFC_GP5_BASE + 0x64) +#define PFC_GP5_ALTSEL2 (PFC_GP5_BASE + 0x68) +#define PFC_GP5_ALTSEL3 (PFC_GP5_BASE + 0x6c) +#define PFC_GP5_PIN_HTX0 BIT(0) +#define PFC_GP5_PIN_HRX0 BIT(1) +#define PFC_GP5_PIN_SCIF_CLK BIT(5) +#define PFC_GP5_PIN_HTX1 BIT(6) +#define PFC_GP5_PIN_HRX1 BIT(7) +#define PFC_GP5_PIN_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HTX0 | PFC_GP5_PIN_HRX0 | \ + PFC_GP5_PIN_HTX1 | PFC_GP5_PIN_HRX1) +#define PFC_GP5_ALTSEL_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HSCIF0_HSCIF1 | PFC_GP5_PIN_SCIF_CLK) + +/** + * pfc_rmw_reg() - Read-modify-write PFC register + * @reg: Register to write + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void pfc_rmw_reg(const u32 reg, const u32 mask, const u32 val) +{ + u32 pmmr = reg & PFC_GROUP_ADDR_MASK; + u32 tmp; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= val; + + writel(~tmp, pmmr); + writel(tmp, reg); +} + +/** + * pfc_set_hscif0_hscif1_pinmux() - Set HSCIF0 and HSCIF1 pinmux + * @bd3250k: Set to TRUE if HSCIF configured for 3.25 MBdps + * + * This function configures both HSCIF0 and HSCIF1 pin multiplexing, + * HSCIF0 is used for follow up stages, HSCIF1 is used for IPL console. + */ +static void pfc_set_hscif0_hscif1_pinmux(bool bd3250k) +{ + u32 gpsr_mask = PFC_GP5_PIN_HSCIF0_HSCIF1; + + if (bd3250k) + gpsr_mask |= PFC_GP5_PIN_SCIF_CLK; + + pfc_rmw_reg(PFC_GP5_ALTSEL0, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL1, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL2, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL3, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_GPSR, gpsr_mask, gpsr_mask); +} + +/** + * pfc_set_avs_pinmux() - Set AVS pinmux + */ +static void pfc_set_avs_pinmux(void) +{ + clrbits_le32(PFC_GP2_POSNEG, PFC_GP2_PIN_AVS); + clrbits_le32(PFC_GP2_IOINTSEL, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_OUTDT, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_INOUTSEL, PFC_GP2_PIN_AVS); + pfc_rmw_reg(PFC_GP2_GPSR, PFC_GP2_PIN_AVS, 0); +} + +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MFIS_BASE 0xb89e0000 +#define MFIS_WPCNTR (MFIS_BASE + 0x900) +#define MFIS_CODEVALUE 0xacce0000 + +/** + * mfis_unprotect() - Remove MFIS register write protection + */ +static void mfis_unprotect(void) +{ + writel(MFIS_CODEVALUE, MFIS_WPCNTR); +} + +/** + * rsip_irq_setup() - Configure RSIP interrupts + */ +static void rsip_irq_setup(void) +{ + asm volatile("cpsid i"); + + setbits_le32(RSIP_SHCSR, RSIP_SHCSR_USGFAULTENA | RSIP_SHCSR_BUSFAULTENA | + RSIP_SHCSR_MEMFAULTENA); + + writel(0xffffffff, RSIP_NVIC_ICER_00); + writel(0xffffffff, RSIP_NVIC_ICER_01); + writel(0xffffffff, RSIP_NVIC_ICER_02); + writel(0xffffffff, RSIP_NVIC_ICER_03); + writel(0xffffffff, RSIP_NVIC_ICER_04); + writel(0xffffffff, RSIP_NVIC_ICER_05); + writel(0xffffffff, RSIP_NVIC_ICER_06); + writel(0xffffffff, RSIP_NVIC_ICER_07); + writel(0xffffffff, RSIP_NVIC_ICER_08); + writel(0xffffffff, RSIP_NVIC_ICER_09); + writel(0xffffffff, RSIP_NVIC_ICER_10); + writel(0xffffffff, RSIP_NVIC_ICER_11); + writel(0xffffffff, RSIP_NVIC_ICER_12); + writel(0xffffffff, RSIP_NVIC_ICER_13); + writel(0xffffffff, RSIP_NVIC_ICER_14); + writel(0xffffffff, RSIP_NVIC_ICER_15); + + /* WDT IRQ */ + writel(RSIP_NVIC_ISER_00_SETENA_INTIWDTA0, RSIP_NVIC_ISER_00); + + asm volatile("cpsid i"); +} + +#define RPC_BASE 0xc08c0000 +#define RPC_CMNSR (RPC_BASE + 0x48) +#define RPC_PHYCNT (RPC_BASE + 0x7c) +#define RPC_CMNCR (RPC_BASE + 0x00) +#define RPC_SSLDR (RPC_BASE + 0x04) +#define RPC_DRCR (RPC_BASE + 0x0c) +#define RPC_DRCMR (RPC_BASE + 0x10) +#define RPC_DREAR (RPC_BASE + 0x14) +#define RPC_DROPR (RPC_BASE + 0x18) +#define RPC_DRENR (RPC_BASE + 0x1c) +#define RPC_SMCR (RPC_BASE + 0x20) +#define RPC_SMCMR (RPC_BASE + 0x24) +#define RPC_SMADR (RPC_BASE + 0x28) +#define RPC_SMENR (RPC_BASE + 0x30) +#define RPC_SMWDR0 (RPC_BASE + 0x40) +#define RPC_DRDMCR (RPC_BASE + 0x58) +#define RPC_DRDRENR (RPC_BASE + 0x5c) +#define RPC_PHYOFFSET1 (RPC_BASE + 0x80) +#define RPC_PHYINT (RPC_BASE + 0x88) +#define RPC_SEC_CONF (RPC_BASE + 0xb8) + +#define RPC_CMNSR_TEND BIT(0) + +#define RPC_CMNCR_MD BIT(31) +#define RPC_CMNCR_MOIIO3(n) FIELD_PREP(GENMASK(23, 22), (n)) +#define RPC_CMNCR_MOIIO2(n) FIELD_PREP(GENMASK(21, 20), (n)) +#define RPC_CMNCR_MOIIO1(n) FIELD_PREP(GENMASK(19, 18), (n)) +#define RPC_CMNCR_MOIIO0(n) FIELD_PREP(GENMASK(17, 16), (n)) +#define RPC_CMNCR_IO0FV(n) FIELD_PREP(GENMASK(9, 8), (n)) +#define RPC_CMNCR_BSZ(n) FIELD_PREP(GENMASK(1, 0), (n)) + +#define RPC_SSLDR_SPNDL_MASK GENMASK(18, 16) +#define RPC_SSLDR_SPNDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SPNDL_MASK, 1) +#define RPC_SSLDR_SLNDL_MASK GENMASK(10, 8) +#define RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES FIELD_PREP(RPC_SSLDR_SLNDL_MASK, 4) +#define RPC_SSLDR_SCKDL_MASK GENMASK(2, 0) +#define RPC_SSLDR_SCKDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SCKDL_MASK, 1) + +#define RPC_DRCR_SSLN BIT(24) +#define RPC_DRCR_RBURST_MASK GENMASK(20, 16) +#define RPC_DRCR_RCF_READ_CACHE_CLEARE BIT(9) +#define RPC_DRCR_RBE BIT(8) + +#define RPC_DRCMR_CMD_MASK GENMASK(23, 16) +#define RPC_DRCMR_CMD_HYPERFLASH_READ FIELD_PREP(RPC_DRCMR_CMD_MASK, 0xA0) + +#define RPC_DREAR_EAV_MASK GENMASK(23, 16) +#define RPC_DREAR_EAC_MASK GENMASK(2, 0) + +#define RPC_DRENR_DME BIT(15) +#define RPC_DRENR_CDE BIT(14) +#define RPC_DRENR_OCDE BIT(12) +#define RPC_DRENR_ADE_MASK GENMASK(11, 8) +#define RPC_DRENR_ADE_HYPERFLASH FIELD_PREP(RPC_DRENR_ADE_MASK, 4) +#define RPC_DRENR_OPDE_MASK GENMASK(7, 4) + +#define RPC_DRDMCR_DMCYC_MASK GENMASK(4, 0) +#define RPC_DRDMCR_DMCYC_15_CYCLE FIELD_PREP(RPC_DRDMCR_DMCYC_MASK, 0xe) + +#define RPC_DRDRENR_HYPE_MASK GENMASK(14, 12) +#define RPC_DRDRENR_HYPE_HYPERFLASH FIELD_PREP(RPC_DRDRENR_HYPE_MASK, 5) +#define RPC_DRDRENR_ADDRE BIT(8) +#define RPC_DRDRENR_OPDRE BIT(4) +#define RPC_DRDRENR_DRDRE BIT(0) + +#define RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK 0x08038000 + +#define RPC_PHYCNT_HS BIT(18) +#define RPC_PHYCNT_PHYMEM_MASK GENMASK(1, 0) +#define RPC_PHYCNT_PHYMEM_HYPERFLASH FIELD_PREP(RPC_PHYCNT_PHYMEM_MASK, 3) + +/** + * rpc_safe_setup() - Configure RPC with safe static settings + */ +static void rpc_safe_setup(void) +{ + writel(RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1) | + 0x01007000, RPC_CMNCR); + writel(RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES, RPC_SSLDR); + writel(RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, RPC_DRCR); + writel(RPC_DRCMR_CMD_HYPERFLASH_READ, RPC_DRCMR); + writel(0, RPC_DREAR); + writel(RPC_DRENR_ADE_HYPERFLASH | 0xa222d000, RPC_DRENR); + writel(0, RPC_SMCR); + writel(0, RPC_SMCMR); + writel(0, RPC_SMADR); + writel(BIT(14), RPC_SMENR); + writel(0, RPC_SMWDR0); + writel(RPC_CMNSR_TEND, RPC_CMNSR); + writel(RPC_DRDMCR_DMCYC_15_CYCLE, RPC_DRDMCR); + writel(RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR); + writel(0x08078263, RPC_PHYCNT); + writel(0x21511144, RPC_PHYOFFSET1); + writel(0x07070002, RPC_PHYINT); + writel(0x00000155, RPC_SEC_CONF); + writel(0x11, CLK_CONTROL_RPCCKCR); + writel(0x10100, PFC_GP3_PULLEN); + writel(0x10100, PFC_GP3_PUDSEL); +} + +/** + * rpc_boot_setup() - Configure RPC after boot from HF + */ +static void rpc_boot_setup(void) +{ + clrsetbits_le32(RPC_PHYCNT, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | RPC_PHYCNT_HS | + RPC_PHYCNT_PHYMEM_MASK, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | + RPC_PHYCNT_HS | RPC_PHYCNT_PHYMEM_HYPERFLASH); + + clrsetbits_le32(RPC_CMNCR, + RPC_CMNCR_MD | + RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO1(3) | + RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(3), + RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1)); + + clrsetbits_le32(RPC_SSLDR, + RPC_SSLDR_SPNDL_MASK | RPC_SSLDR_SLNDL_MASK | RPC_SSLDR_SCKDL_MASK, + RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES); + + clrsetbits_le32(RPC_DRCR, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | + RPC_DRCR_RCF_READ_CACHE_CLEARE | RPC_DRCR_RBE); + readl(RPC_DRCR); /* Dummy readback */ + + clrsetbits_le32(RPC_DRCMR, RPC_DRCMR_CMD_MASK, RPC_DRCMR_CMD_HYPERFLASH_READ); + + clrbits_le32(RPC_DREAR, RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + + writel(0, RPC_DROPR); + + clrsetbits_le32(RPC_DRENR, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_MASK | RPC_DRENR_OPDE_MASK, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_HYPERFLASH); + + clrsetbits_le32(RPC_DRDMCR, RPC_DRDMCR_DMCYC_MASK, RPC_DRDMCR_DMCYC_15_CYCLE); + + clrsetbits_le32(RPC_DRDRENR, + RPC_DRDRENR_HYPE_MASK | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_OPDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_DRDRE); +} + +/** + * rpc_setup() - Configure RPC + */ +static void rpc_setup(void) +{ + const u32 boot = field_get(SYSSS_MODE1_BOOTMODE_MASK, sysss_read_modemr()); + + if (boot != SYSSS_MODE1_BOOTMODE_HF_DMA) { + /* Not booted from HF, this may be SCIF loader, use safe setup. */ + rpc_safe_setup(); + return; + } + + /* Wait for any outstanding transfer to end. */ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + while (!(readl(RPC_CMNSR) & RPC_CMNSR_TEND)) + ; + + /* Tristate IO */ + setbits_le32(RPC_CMNCR, RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | + RPC_CMNCR_MOIIO1(3) | RPC_CMNCR_MOIIO0(3)); + + /* Set 160 MHz RPC HF clock */ + clrsetbits_le32(CLK_CONTROL_RPCCKCR, + CLK_CONTROL_RPCCKCR_CKSTP1 | CLK_CONTROL_RPCCKCR_RPCFC_MASK, + 0x11); + + rpc_boot_setup(); +} + +#define AXMM10_ADSPLCR0_CTRL 0xe9a07100 +#define AXMM10_ADSPLCR1_CTRL 0xe9a07104 +#define AXMM11_ADSPLCR0_CTRL 0xe9a07150 +#define AXMM11_ADSPLCR1_CTRL 0xe9a07154 + +/** + * axi_qos_init() - Configure AXI bus QoS + */ +static void axi_qos_init(void) +{ + writel(0x00011d0c, AXMM10_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM10_ADSPLCR1_CTRL); + writel(0x00011d0c, AXMM11_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM11_ADSPLCR1_CTRL); + dsb(); +} + +/** + * load_perm_table() - Load shared table into SRAM and hardware + * @dstaddr: SRAM destination address + * @dstsize: SRAM destination area size + * @listtable: Table of registers to write at offset 2i + * @listsize: Size of table of registers + * @listval: Value to write at offset 2i+1 + */ +static void load_perm_table(const u32 dstaddr, const u32 dstsize, + const u32 *listtable, const u32 listsize, + const u32 listval) +{ + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + u32 *dmabuf = (u32 *)(dstaddr + 0xa0000000); + u32 reg, rv; + int i; + + /* Place shared bus access permissions configuration table into SRAM */ + for (i = 0; i < dstsize / (2 * sizeof(u32)); i++) { + if (i >= listsize) { + dmabuf[2 * i] = 0; + dmabuf[(2 * i) + 1] = 0; + continue; + } + + dmabuf[2 * i] = listtable[i]; + dmabuf[(2 * i) + 1] = listval; + + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + writel(listval, reg); + } + + /* Validate hardware write. */ + for (i = 0; i < listsize; i++) { + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + rv = readl(reg); + if (rv == listval) + continue; + printf("RG[%d] = 0x%x / expected 0x%x\n", i, rv, listval); + } +} + +/** + * load_perm_tables() - Load shared tables into SRAM and hardware + */ +static void load_perm_tables(void) +{ + load_perm_table(RGIDM_SHARED_ADDR, RGIDM_SHARED_SIZE, + rgidm_register_list, ARRAY_SIZE(rgidm_register_list), 0); + load_perm_table(SEC_MODID_SHARED_ADDR, SEC_MODID_SHARED_SIZE, + sec_modid_register_list, ARRAY_SIZE(sec_modid_register_list), 0xffff); + load_perm_table(RGIDR_SHARED_ADDR, RGIDR_SHARED_SIZE, + rgidr_register_list, ARRAY_SIZE(rgidr_register_list), 1); + load_perm_table(RGIDW_SHARED_ADDR, RGIDW_SHARED_SIZE, + rgidw_register_list, ARRAY_SIZE(rgidw_register_list), 1); + + /* Override Region ID secure group settings */ + writel(0xffffffff, 0xc0983820); + writel(0xffffffff, 0xc0983828); + + writel(0xffffffff, 0xec603828); + writel(0xffffffff, 0xec60382c); + writel(0xffffffff, 0xec603830); + writel(0xffffffff, 0xec603834); + writel(0xffffffff, 0xec603838); + writel(0xffffffff, 0xec60383c); + + writel(0xffffffff, 0xc9d03880); + writel(0xffffffff, 0xc9d03884); + + /* + * The addresses in range 0x08000000..0x1fffffff + * are incremented by 0xa0000000 + */ + writel(0xffffffff, 0xba80383c); + writel(0xffffffff, 0xba803840); + writel(0xffffffff, 0xba803848); + writel(0xffffffff, 0xba80384c); + writel(0xffffffff, 0xba803974); + + writel(0xffffffff, 0xde803804); + writel(0xffffffff, 0xde803808); + writel(0xffffffff, 0xde803810); + writel(0xffffffff, 0xde803814); + writel(0xffffffff, 0xde803838); + writel(0xffffffff, 0xde80383c); + writel(0xffffffff, 0xde803840); + writel(0xffffffff, 0xde803844); + + writel(0xffffffff, 0xc1283808); + + writel(0xffffffff, 0xe9a08000); + writel(0xffffffff, 0xe9a081fc); + writel(0xffffffff, 0xe9a08200); + writel(0xffffffff, 0xe9a081fc); +} + +#define SCP_STCM_BASE 0xc1000000 +#define SCP_BASE 0xc1340000 +#define SCP_CFGVECTABLE (SCP_BASE + 0x0) +#define SCP_CFGNSSTCALIB (SCP_BASE + 0x10) +#define SCP_CPUWAIT (SCP_BASE + 0x30) +#define SCP_CFGNSSTCALIB_13_3MHZ 0x010040f0 +#define SCP_CPUWAIT_WAIT BIT(0) + +/** + * scp_initialize() - Initialize SCP + * + * Put SCP into reset, configure SCP entry point address and systick timer, + * release SCP from reset, and zero out SCP STCM regions. + */ +static void scp_initialize(void) +{ + u32 addr; + + mdlc_set_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + writel(SCP_STCM_BASE, SCP_CFGVECTABLE); + writel(SCP_CFGNSSTCALIB_13_3MHZ, SCP_CFGNSSTCALIB); + setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT); + + mdlc_release_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + /* Fill zero to SCP STCM regions 0 ... 27 */ + for (addr = SCP_STCM_BASE; addr < 0xc1061b00; addr += 8) + writeq(0, addr); + + asm volatile("dsb sy"); +} + +#define GIC720AE_GICR_PWRR(cpu) \ + (GICR_BASE + 0x24 + ((cpu) * 0x40000)) + +#define GIC720AE_GICD_IVIEWR(num) \ + (GICD_BASE + 0xf600 + ((num) * 0x4)) +#define GIC720AE_GICD_IVIEWRE(num) \ + (GICD_BASE + 0xf800 + ((num) * 0x4)) +#define GIC720AE_GICR_TYPER(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x8) +#define GIC720AE_GICR_VIEWR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x2c) +#define GIC720AE_GICR_MPIDR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x100) +#define GIC720AE_GICR_TYPER_AFF_MASK GENMASK_ULL(63, 32) + +#define CA_CORE_MAX 32 + +/** + * gic720ae_init() - GIC720AE initialization + */ +static void gic720ae_init(void) +{ + u64 val; + int i; + + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP0_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTTP_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP1_MASK); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(BIT(1), GIC720AE_GICR_PWRR(i)); + + for (i = 0; i < CA_CORE_MAX; i++) { + val = readq(GIC720AE_GICR_TYPER(i)) & GIC720AE_GICR_TYPER_AFF_MASK; + writel((u32)(val >> 32U), GIC720AE_GICR_MPIDR(i)); + } + + writel(0x3f, GICD_BASE); /* CTRL register */ + + for (i = 2; i <= 61; i++) /* From IVIEWR min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWR(i)); + + for (i = 0; i <= 63; i++) /* From IVIEWRE min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWRE(i)); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(1, GIC720AE_GICR_VIEWR(i)); /* View 1 */ +} + +/** + * mach_cpu_init() - Initialize hardware and start other cores + */ +int mach_cpu_init(void) +{ + mfis_unprotect(); + pfc_set_avs_pinmux(); + mdlc_mpg_start(); + clk_control_set_pll(); + rsip_irq_setup(); + rpc_setup(); + axi_qos_init(); + load_perm_tables(); + gic720ae_init(); + + /* Release SCP from reset */ + scp_initialize(); + + return 0; +} + +/** + * board_debug_uart_init() - Initialize all HSCIF + */ +void board_debug_uart_init(void) +{ + const u32 baud = field_get(SYSSS_MODE1_BAUDRATE_MASK, sysss_read_modemr()); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, + CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, + CLK_CONTROL_PLL01_1_SCR); + + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF0_MASK); + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF1_MASK); + + pfc_set_hscif0_hscif1_pinmux(baud == SYSSS_MODE1_BAUDRATE_3250000); +} + +/** + * board_init() - Board specific initialization + */ +int board_init(void) +{ + /* Allow WDT reset */ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK); + + return 0; +} + +/** + * arm_reserve_mmu() - Reserve space for MMU tables + */ +int arm_reserve_mmu(void) +{ + /* Reserve space for MMU tables just above stack in STCM */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = CONFIG_CUSTOM_SYS_INIT_SP_ADDR; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + return 0; +} + +/** + * reset_cpu() - Reset this CPU core + */ +void __weak reset_cpu(void) +{ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + writel(0x1, RST_SWSRES1A); +} diff --git a/board/renesas/common/gen5-cm33.h b/board/renesas/common/gen5-cm33.h new file mode 100644 index 00000000000..2dfb0b06cf7 --- /dev/null +++ b/board/renesas/common/gen5-cm33.h @@ -0,0 +1,2001 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +#ifndef __GEN5_CM33_H__ +#define __GEN5_CM33_H__ + +#define RGIDM_SHARED_ADDR 0x1001c000 +#define RGIDM_SHARED_SIZE 0x1000 +#define SEC_MODID_SHARED_ADDR 0x1001d000 +#define SEC_MODID_SHARED_SIZE 0x3000 +#define RGIDR_SHARED_ADDR 0x10020000 +#define RGIDR_SHARED_SIZE 0x8000 +#define RGIDW_SHARED_ADDR 0x10028000 +#define RGIDW_SHARED_SIZE 0x8000 + +static const u32 rgidm_register_list[] = { + 0xec601000, 0xcbf01000, 0xcbf01004, 0xcbf01008, + 0xcbf0100c, 0xcbf01010, 0xcbf01014, 0xcbf01018, + 0xcbf0101c, 0xcbf01020, 0xcbf01024, 0xcbf01028, + 0xcbf0102c, 0xcbf01030, 0xcbf01034, 0xcbf01038, + 0xcbf0103c, 0xcbf01040, 0xcbf01044, 0xcbf01048, + 0xcbf0104c, 0xcbf01050, 0xcbf01054, 0xcbf01058, + 0xcbf0105c, 0xcbf01060, 0xcbf01064, 0xcbf01068, + 0xcbf0106c, 0xcbf01070, 0xcbf01074, 0xcbf01078, + 0xcbf0107c, 0xcbf01080, 0xc9d01000, 0xc9d01004, + 0xc9d01008, 0xc9d0100c, 0xc9d01010, 0xc9d01014, + 0xc9d01018, 0xc9d0101c, 0xc9d01020, 0xc9d01024, + 0xc9d01028, 0xc9d0102c, 0xc9d01030, 0xc9d01034, + 0xc9d01038, 0xc9d0103c, 0xc9d01040, 0xde801000, + 0xde801004, 0xc1a01000, 0xc1a01004, 0xc1a01008, + 0xc1a0100c, 0xc1a01010, 0xc1a01014, 0xc1a01018, + 0xc1a0101c, 0xc1a01020, 0xc1a01024, 0xc1e01000, + 0xc1e01004, 0xc1e01008, 0xc1e0100c, 0xc1e01010, + 0xc1e01014, 0xc1e01018, 0xc1e0101c, 0xc1e01020, + 0xc1e01024, 0xe9a01000, 0xe9a01004, 0xe9a01008, + 0xe9a0100c, 0xd2f01000, 0xd2f01004, 0xd2f01008, + 0xd2f0100c, 0xd2f01010, 0xd2f01014, 0xd2f01018, + 0xd2f0101c, 0xd2f01020, 0xd2f01024, 0xd2f01028, + 0xd2f0102c, 0xd2f01030, 0xd2f01034, 0xd2f01038, + 0xd6f01000, 0xd6f01004, 0xd6f01008, 0xd6f0100c, + 0xd6f01010, 0xd6f01014, 0xd6f01018, 0xd6f0101c, + 0xd6f01020, 0xd6f01024, 0xd6f01028, 0xd6f0102c, + 0xd6f01030, 0xd6f01034, 0xd6f01038, 0xc0981000, + 0xc0981004, 0xc0981008, 0xc098100c, 0xc0581000, + 0xcb401000, 0xcb401004, 0xcb401008, 0xcb40100c, + 0xcb401010, 0xcb401014, 0x1a801000, 0x1a801004, + 0x1a801008, 0x1a80100c, 0x1a801010, 0x1a801014, + 0x1a801018, 0x1a80101c, 0x1a801020, 0x1a801024, + 0x1a801028, 0x1a80102c, 0x1a801030, 0x1a801034, + 0x1a801038, 0x1a80103c, 0x1a801040, 0x1a801044, + 0x1a801048, 0x1a80104c, 0x1a801050, 0x1a801054, + 0x1a801058, 0x1a80105c, 0x1a801060, 0x1a801064, + 0x1a801068, 0x1a80106c, 0x1a801070, 0x1a801074, + 0x1a801078, 0x1a80107c, 0x1a801080, 0x1a801084, + 0x1a801088, 0x1a80108c, 0x1a801090, 0x1a801094, + 0x18b41000, 0x18b41004, 0x18b41008, 0x18b4100c, + 0xc1281000, 0xc1281004, 0xc1281008, 0xc128100c, + 0xc1281010, 0xc1281014, 0xc5801000, 0xc5801004, + 0xc5801008, 0xc580100c, 0xc5801010, 0xc5801014, + 0xc5801018, 0xc580101c, 0xc5801020, 0xc5801024, + 0xc5801028, 0xc580102c, 0xc5801030, 0xc5801034, + 0xc5801038, 0xc580103c, 0xc5801040, 0xc5801044, + 0xc5801048, 0xc580104c, 0xc5801050, 0xc5801054, + 0xc5801058, 0xc580105c, 0xc5801060, 0xc5801064, + 0xc5801068, 0xc580106c, 0xc5801070, 0xc5801074, + 0xc5801078, 0xc580107c, 0xc5801080, 0xc5801084, + 0xc5801088, 0xc580108c, 0xc5801090, 0xc5801094, + 0xc5801098, 0xc580109c, 0xc58010a0, 0xc58010a4, + 0xc58010a8, 0xc58010ac, 0xc58010b0, 0xc58010b4, + 0xc58010b8, 0xc58010bc, 0xc58010c0, 0xc58010c4, + 0xc58010c8, 0xc58010cc, 0xc58010d0, 0xc58010d4, + 0xc58010d8, 0xc58010dc, 0xc58010e0, 0xc3021000, + 0xc3021004, 0xc3021008, 0xc302100c, 0xc3021010, + 0xc3021014, 0xc3421000, 0xc3421004, 0xc3421008, + 0xc342100c, 0xc3421010, 0xc3421014 +}; + +static const u32 rgidr_register_list[] = { + 0xe8022000, 0xe8022004, 0xe8022008, 0xe802200c, + 0xe8022010, 0xe8022014, 0xe8022018, 0xe802201c, + 0xe8022020, 0xe8022024, 0xe8022028, 0xe802202c, + 0xe8022030, 0xe8022034, 0xe8022038, 0xe802203c, + 0xe8022040, 0xe8022044, 0xe8022048, 0xe802204c, + 0xe80a2000, 0xe80a2004, 0xe80a2008, 0xe80a200c, + 0xe80a2010, 0xe80a2014, 0xe80a2018, 0xe80a201c, + 0xe80a2020, 0xe80a2024, 0xe80a2028, 0xe80a202c, + 0xe80a2030, 0xe80a2034, 0xe80a2038, 0xe80a203c, + 0xe80a2040, 0xe80a2044, 0xe80a2048, 0xe80a204c, + 0xe8122000, 0xe8122004, 0xe8122008, 0xe812200c, + 0xe8122010, 0xe8122014, 0xe8122018, 0xe812201c, + 0xe8122020, 0xe8122024, 0xe8122028, 0xe812202c, + 0xe8122030, 0xe8122034, 0xe8122038, 0xe812203c, + 0xe8122040, 0xe8122044, 0xe8122048, 0xe812204c, + 0xe81a2000, 0xe81a2004, 0xe81a2008, 0xe81a200c, + 0xe81a2010, 0xe81a2014, 0xe81a2018, 0xe81a201c, + 0xe81a2020, 0xe81a2024, 0xe81a2028, 0xe81a202c, + 0xe81a2030, 0xe81a2034, 0xe81a2038, 0xe81a203c, + 0xe81a2040, 0xe81a2044, 0xe81a2048, 0xe81a204c, + 0xe8222000, 0xe8222004, 0xe8222008, 0xe822200c, + 0xe8222010, 0xe8222014, 0xe8222018, 0xe822201c, + 0xe8222020, 0xe8222024, 0xe8222028, 0xe822202c, + 0xe8222030, 0xe8222034, 0xe8222038, 0xe822203c, + 0xe8222040, 0xe8222044, 0xe8222048, 0xe822204c, + 0xe82a2000, 0xe82a2004, 0xe82a2008, 0xe82a200c, + 0xe82a2010, 0xe82a2014, 0xe82a2018, 0xe82a201c, + 0xe82a2020, 0xe82a2024, 0xe82a2028, 0xe82a202c, + 0xe82a2030, 0xe82a2034, 0xe82a2038, 0xe82a203c, + 0xe82a2040, 0xe82a2044, 0xe82a2048, 0xe82a204c, + 0xe8322000, 0xe8322004, 0xe8322008, 0xe832200c, + 0xe8322010, 0xe8322014, 0xe8322018, 0xe832201c, + 0xe8322020, 0xe8322024, 0xe8322028, 0xe832202c, + 0xe8322030, 0xe8322034, 0xe8322038, 0xe832203c, + 0xe8322040, 0xe8322044, 0xe8322048, 0xe832204c, + 0xe83a2000, 0xe83a2004, 0xe83a2008, 0xe83a200c, + 0xe83a2010, 0xe83a2014, 0xe83a2018, 0xe83a201c, + 0xe83a2020, 0xe83a2024, 0xe83a2028, 0xe83a202c, + 0xe83a2030, 0xe83a2034, 0xe83a2038, 0xe83a203c, + 0xe83a2040, 0xe83a2044, 0xe83a2048, 0xe83a204c, + 0xc0622000, 0xc0622004, 0xc0622008, 0xc062200c, + 0xc0622010, 0xc0622014, 0xc0622018, 0xc062201c, + 0xc0622020, 0xc0622024, 0xc0622028, 0xc062202c, + 0xc0622030, 0xc0622034, 0xc0622038, 0xc062203c, + 0xc0622040, 0xc0622044, 0xc0622048, 0xc062204c, + 0xc0622050, 0xc0622054, 0xc0762000, 0xc0762004, + 0xc0762008, 0xc076200c, 0xc0762010, 0xc0762014, + 0xc0762018, 0xc076201c, 0xc0762020, 0xc0762024, + 0xc0762028, 0xc076202c, 0xc0762030, 0xc0762034, + 0xc0762038, 0xc076203c, 0xc0762040, 0xc0762044, + 0xc0762048, 0xc076204c, 0xc0762050, 0xc0762054, + 0xc0762058, 0xc076205c, 0xc0762060, 0xc0762064, + 0xc0762068, 0xc076206c, 0xc0762070, 0xc0762074, + 0xc0762078, 0xc076207c, 0xc0762080, 0xc0762084, + 0xc0762088, 0xc076208c, 0xc0762090, 0xc0762094, + 0xc0762098, 0xc076209c, 0xc07620a0, 0xc07620a4, + 0xc07620a8, 0xc07620ac, 0xc07620b0, 0xc07620b4, + 0xc07620b8, 0xc07620bc, 0xc07620c0, 0xc07620c4, + 0xc07620c8, 0xc07620cc, 0xc07620d0, 0xc07620d4, + 0xc07620d8, 0xc07620dc, 0xc07a2000, 0xc07a2004, + 0xc07a2008, 0xc07a200c, 0xc07a2010, 0xc07a2014, + 0xc07a2018, 0xc07a201c, 0xc07a2020, 0xc07a2024, + 0xc07a2028, 0xc07a202c, 0xc07a2030, 0xc07a2034, + 0xc07a2038, 0xc07a203c, 0xc07a2040, 0xc07a2044, + 0xc07a2048, 0xc07a204c, 0xc07a2050, 0xc07a2054, + 0xc07a2058, 0x1d002000, 0x1d002004, 0x1d002008, + 0x1d00200c, 0x1d002010, 0x1d002014, 0x1d002018, + 0x1d00201c, 0x1d002020, 0x1d002024, 0x1d002028, + 0x1d00202c, 0x1d002030, 0x1d002034, 0x1d002038, + 0x1d00203c, 0x1d002040, 0x1d002044, 0x1d002048, + 0x1d00204c, 0x1d002050, 0x1d002054, 0x1d002058, + 0x1d00205c, 0x1d002060, 0x1d002064, 0x1d002068, + 0x1d00206c, 0x1d002070, 0x1d002074, 0x1d002078, + 0x1d00207c, 0x1d002080, 0x1d002084, 0x1d002088, + 0x1d00208c, 0x1d002090, 0x1d002094, 0x1d002098, + 0x1d00209c, 0x1d0020a0, 0x1d0020a4, 0x1d0020a8, + 0x1d0020ac, 0x1d0020b0, 0x1d0020b4, 0x1d0020b8, + 0xc6702000, 0xc6702004, 0xc6702008, 0xc670200c, + 0xc6702010, 0xc6702014, 0xc6702018, 0xc670201c, + 0xc6702020, 0xc6702024, 0xc6702028, 0xc670202c, + 0xc6702030, 0xc6702034, 0xc6702038, 0xc670203c, + 0xc6702040, 0xc6702044, 0xc6702048, 0xc670204c, + 0xc6702050, 0xc6702054, 0xc6702058, 0xc670205c, + 0xc6702060, 0xc6702064, 0xc6702068, 0xc670206c, + 0xc6702070, 0xc6702074, 0xc6702078, 0xc670207c, + 0xc6702080, 0xc6702084, 0xc6702088, 0xc670208c, + 0xc6702090, 0xc6702094, 0xc6702098, 0xc670209c, + 0xc67020a0, 0xc67020a4, 0xc67020a8, 0xc1742000, + 0xc1742004, 0xc1742008, 0xc174200c, 0xc1742010, + 0xc1742014, 0xc1742018, 0xc174201c, 0xc1742020, + 0xc1742024, 0xc1742028, 0xc174202c, 0xc1742030, + 0xc1742034, 0xc1742038, 0xc174203c, 0xc1742040, + 0xc1742044, 0xc1742048, 0xc174204c, 0xc1742050, + 0xc1742054, 0xec602000, 0xec602004, 0xec602008, + 0xec60200c, 0xec602010, 0xec602014, 0xec602018, + 0xec60201c, 0xec602020, 0xec602024, 0xec602028, + 0xec60202c, 0xec602030, 0xec602034, 0xec602038, + 0xec60203c, 0xec602040, 0xec602044, 0xec602048, + 0xec60204c, 0xec602050, 0xec602054, 0xec602058, + 0xec60205c, 0xec602060, 0xec602064, 0xec602068, + 0xec60206c, 0xec602070, 0xec602074, 0xec602078, + 0xec60207c, 0xec602080, 0xec602084, 0xec602088, + 0xec60208c, 0xec602090, 0xec602094, 0xec602098, + 0xec60209c, 0xec6020a0, 0xec6020a4, 0xec6020a8, + 0xec6020ac, 0xec6020b0, 0xec6020b4, 0xec6020b8, + 0xec6020bc, 0xec6020c0, 0xec6020c4, 0xec6020c8, + 0xec6020cc, 0xec6020d0, 0xec6020d4, 0xec6020d8, + 0xec6020dc, 0xec6020e0, 0xec6020e4, 0xec6020e8, + 0xec6020ec, 0xec6020f0, 0xec6020f4, 0xec6020f8, + 0xec6020fc, 0xec602100, 0xec602104, 0xec602108, + 0xec60210c, 0xec602110, 0xec602114, 0xec602118, + 0xec60211c, 0xec602120, 0xec602124, 0xec602128, + 0xec60212c, 0xec602130, 0xec602134, 0xec602138, + 0xec60213c, 0xec602140, 0xec602144, 0xec602148, + 0xec60214c, 0xec602150, 0xec602154, 0xec602158, + 0xec60215c, 0xec602160, 0xec602164, 0xec602168, + 0xec60216c, 0xec602170, 0xec602174, 0xec602178, + 0xec60217c, 0xec602180, 0xec602184, 0xec602188, + 0xec60218c, 0xec602190, 0xec602194, 0xec602198, + 0xec60219c, 0xec6021a0, 0xec6021a4, 0xec6021a8, + 0xec6021ac, 0xec6021b0, 0xec6021b4, 0xec6021b8, + 0xec6021bc, 0xec6021c0, 0xec6021c4, 0xec6021c8, + 0xec6021cc, 0xec6021d0, 0xec6021d4, 0xec6021d8, + 0xec6021dc, 0xec6021e0, 0xec6021e4, 0xec6021e8, + 0xec6021ec, 0xec6021f0, 0xec6021f4, 0xec6021f8, + 0xec6021fc, 0xec602200, 0xec602204, 0xec602208, + 0xec60220c, 0xec602210, 0xec602214, 0xec602218, + 0xec60221c, 0xec602220, 0xec602224, 0xec602228, + 0xec60222c, 0xec602230, 0xec602234, 0xec602238, + 0xec60223c, 0xec602240, 0xec602244, 0xec602248, + 0xec60224c, 0xec602250, 0xec602254, 0xec602258, + 0xec60225c, 0xec602260, 0xec602264, 0xec602268, + 0xec60226c, 0xec602270, 0xec602274, 0xec602278, + 0xec60227c, 0xec602280, 0xec602284, 0xec602288, + 0xec60228c, 0xec602290, 0xec602294, 0xec602298, + 0xec60229c, 0xec6022a0, 0xec6022a4, 0xec6022a8, + 0xec6022ac, 0xec6022b0, 0xec6022b4, 0xec6022b8, + 0xec6022bc, 0xec6022c0, 0xec6022c4, 0xec6022c8, + 0xec6022cc, 0xec6022d0, 0xec6022d4, 0xec6022d8, + 0xec6022dc, 0xec6022e0, 0xec6022e4, 0xec6022e8, + 0xec6022ec, 0xec6022f0, 0xec6022f4, 0xec6022f8, + 0xec6022fc, 0xec602300, 0xec602304, 0xec602308, + 0xec60230c, 0xec602310, 0xec602314, 0xec602318, + 0xec60231c, 0xec602320, 0xec602324, 0xec602328, + 0xec60232c, 0xec602330, 0xec602334, 0xec602338, + 0xec60233c, 0xec602340, 0xec602344, 0xec602348, + 0xec60234c, 0xec602350, 0xec602354, 0xec602358, + 0xec60235c, 0xec602360, 0xec602364, 0xec602368, + 0xec60236c, 0xec602370, 0xec602374, 0xec602378, + 0xec60237c, 0xec602380, 0xec602384, 0xec602388, + 0xec60238c, 0xec602390, 0xec602394, 0xec602398, + 0xec60239c, 0xec6023a0, 0xec6023a4, 0xec6023a8, + 0xec6023ac, 0xec6023b0, 0xec6023b4, 0xec6023b8, + 0xec6023bc, 0xec6023c0, 0xec6023c4, 0xec6023c8, + 0xec6023cc, 0xec6023d0, 0xec6023d4, 0xec6023d8, + 0xec6023dc, 0xec6023e0, 0xec6023e4, 0xec6023e8, + 0xec6023ec, 0xec6023f0, 0xec6023f4, 0xec6023f8, + 0xec6023fc, 0xec602400, 0xec602404, 0xec602408, + 0xec60240c, 0xec602410, 0xec602414, 0xec602418, + 0xec60241c, 0xec602420, 0xec602424, 0xec602428, + 0xec60242c, 0xec602430, 0xec602434, 0xec602438, + 0xec60243c, 0xec602440, 0xec602444, 0xec602448, + 0xec60244c, 0xec602450, 0xec602454, 0xec602458, + 0xec60245c, 0xec602460, 0xec602464, 0xec602468, + 0xec60246c, 0xec602470, 0xec602474, 0xec602478, + 0xec60247c, 0xec602480, 0xec602484, 0xec602488, + 0xec60248c, 0xec602490, 0xec602494, 0xec602498, + 0xec60249c, 0xec6024a0, 0xec6024a4, 0xec6024a8, + 0xec6024ac, 0xec6024b0, 0xec6024b4, 0xec6024b8, + 0xec6024bc, 0xec6024c0, 0xec6024c4, 0xec6024c8, + 0xec6024cc, 0xec6024d0, 0xec6024d4, 0xec6024d8, + 0xec6024dc, 0xec6024e0, 0xec6024e4, 0xec6024e8, + 0xec6024ec, 0xec6024f0, 0xec6024f4, 0xec6024f8, + 0xec6024fc, 0xec602500, 0xec602504, 0xec602508, + 0xec60250c, 0xec602510, 0xec602514, 0xec602518, + 0xec60251c, 0xec602520, 0xec602524, 0xec602528, + 0xec60252c, 0xec602530, 0xec602534, 0xec602538, + 0xec60253c, 0xec602540, 0xec602544, 0xec602548, + 0xec60254c, 0xec602550, 0xec602554, 0xec602558, + 0xec60255c, 0xec602560, 0xec602564, 0xec602568, + 0xec60256c, 0xec602570, 0xec602574, 0xec602578, + 0xec60257c, 0xec602580, 0xec602584, 0xec602588, + 0xec60258c, 0xec602590, 0xec602594, 0xec602598, + 0xec60259c, 0xec6025a0, 0xec6025a4, 0xec6025a8, + 0xec6025ac, 0xec6025b0, 0xec6025b4, 0xec6025b8, + 0xec6025bc, 0xec6025c0, 0xec6025c4, 0xec6025c8, + 0xec6025cc, 0xec6025d0, 0xec6025d4, 0xec6025d8, + 0xec6025dc, 0xec6025e0, 0xec6025e4, 0xec6025e8, + 0xec6025ec, 0xec6025f0, 0xec6025f4, 0xec6025f8, + 0xec6025fc, 0xec602600, 0xec602604, 0xec602608, + 0xec60260c, 0xec602610, 0xec602614, 0xec602618, + 0xec60261c, 0xec602620, 0xec602624, 0xec602628, + 0xec60262c, 0xec602630, 0xec602634, 0xec602638, + 0xec60263c, 0xec602640, 0xec602644, 0xec602648, + 0xec60264c, 0xec602650, 0xec602654, 0xec602658, + 0xec60265c, 0xec602660, 0xec602664, 0xec602668, + 0xec60266c, 0xec602670, 0xec602674, 0xec602678, + 0xec60267c, 0xec602680, 0xec602684, 0xec602688, + 0xec60268c, 0xec602690, 0xec602694, 0xec602698, + 0xec60269c, 0xec6026a0, 0xec6026a4, 0xec6026a8, + 0xec6026ac, 0xec6026b0, 0xec6026b4, 0xec6026b8, + 0xec6026bc, 0xec6026c0, 0xec6026c4, 0xec6026c8, + 0xec6026cc, 0xec6026d0, 0xec6026d4, 0xec6026d8, + 0xec6026dc, 0xec6026e0, 0xec6026e4, 0xec6026e8, + 0xec6026ec, 0xec6026f0, 0xec6026f4, 0xec6026f8, + 0xec6026fc, 0xec602700, 0xec602704, 0xec602708, + 0xec60270c, 0xec602710, 0xec602714, 0xec602718, + 0xec60271c, 0xec602720, 0xec602724, 0xec602728, + 0xec60272c, 0xec602730, 0xec602734, 0xec602738, + 0xec60273c, 0xec602740, 0xec602744, 0xec602748, + 0xec60274c, 0xec602750, 0xec602754, 0xec602758, + 0xec60275c, 0xec602760, 0xec602764, 0xec602768, + 0xec60276c, 0xec602770, 0xec602774, 0xec602778, + 0xec60277c, 0xec602780, 0xec602784, 0xec602788, + 0xec60278c, 0xec602790, 0xec602794, 0xec602798, + 0xec60279c, 0xec6027a0, 0xec6027a4, 0xec6027a8, + 0xec6027ac, 0xec6027b0, 0xec6027b4, 0xec6027b8, + 0xec6027bc, 0xec6027c0, 0xec6027c4, 0xec6027c8, + 0xec6027cc, 0xec6027d0, 0xec6027d4, 0xec6027d8, + 0xec6027dc, 0xec6027e0, 0xec6027e4, 0xec6027e8, + 0xec6027ec, 0xec6027f0, 0xec6027f4, 0xec6027f8, + 0xec6027fc, 0xec602800, 0xec602804, 0xec602808, + 0xec60280c, 0xec602810, 0xec602814, 0xec602818, + 0xec60281c, 0xec602820, 0xec602824, 0xec602828, + 0xec60282c, 0xec602830, 0xec602834, 0xec602838, + 0xec60283c, 0xec602840, 0xec602844, 0xec602848, + 0xec60284c, 0xec602850, 0xec602854, 0xec602858, + 0xec60285c, 0xec602860, 0xec602864, 0xec602868, + 0xec60286c, 0xec602870, 0xec602874, 0xec602878, + 0xec60287c, 0xec602880, 0xec602884, 0xec602888, + 0xec60288c, 0xec602890, 0xec602894, 0xec602898, + 0xec60289c, 0xec6028a0, 0xec6028a4, 0xec6028a8, + 0xec6028ac, 0xec6028b0, 0xec6028b4, 0xec6028b8, + 0xec6028bc, 0xec6028c0, 0xec6028c4, 0xec6028c8, + 0xec6028cc, 0xec6028d0, 0xec6028d4, 0xec6028d8, + 0xec6028dc, 0xec6028e0, 0xec6028e4, 0xec6028e8, + 0xec6028ec, 0xec6028f0, 0xec6028f4, 0xec6028f8, + 0xec6028fc, 0xec602900, 0xec602904, 0xec602908, + 0xec60290c, 0xec602910, 0xec602914, 0xec602918, + 0xec60291c, 0xec602920, 0xec602924, 0xec602928, + 0xec60292c, 0xec602930, 0xec602934, 0xec602938, + 0xec60293c, 0xec602940, 0xec602944, 0xec602948, + 0xec60294c, 0xec602950, 0xec602954, 0xec602958, + 0xec60295c, 0xec602960, 0xec602964, 0xec602968, + 0xec60296c, 0xec602970, 0xec602974, 0xec602978, + 0xec60297c, 0xec602980, 0xec602984, 0xec602988, + 0xec60298c, 0xec602990, 0xec602994, 0xec602998, + 0xec60299c, 0xec6029a0, 0xec6029a4, 0xec6029a8, + 0xec6029ac, 0xec6029b0, 0xec6029b4, 0xec6029b8, + 0xec6029bc, 0xec6029c0, 0xec6029c4, 0xec6029c8, + 0xec6029cc, 0xec6029d0, 0xec6029d4, 0xec6029d8, + 0xec6029dc, 0xec6029e0, 0xec6029e4, 0xec6029e8, + 0xec6029ec, 0xec6029f0, 0xec6029f4, 0xec6029f8, + 0xec6029fc, 0xec602a00, 0xec602a04, 0xec602a08, + 0xec602a0c, 0xec602a10, 0xec602a14, 0xe9e22000, + 0xe9e22004, 0xe9e22008, 0xe9e2200c, 0xe9e22010, + 0xe9e22014, 0xe9e22018, 0xe9e2201c, 0xe9e22020, + 0xe9e22024, 0xe9e22028, 0xe9e2202c, 0xe9e22030, + 0xe9e22034, 0xe9e22038, 0xe9e2203c, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0xca442000, 0xca442004, 0xca442008, + 0xca44200c, 0xca442010, 0xca442014, 0xca442018, + 0xca44201c, 0xca442020, 0xca442024, 0xca442028, + 0xca44202c, 0xca442030, 0xca442034, 0xca442038, + 0xca44203c, 0xca442040, 0xca442044, 0xca442048, + 0xca44204c, 0xca442050, 0xca442054, 0xca442058, + 0xca44205c, 0xca542000, 0xca542004, 0xca542008, + 0xca54200c, 0xca542010, 0xca542014, 0xca542018, + 0xca54201c, 0xca542020, 0xca542024, 0xca542028, + 0xca54202c, 0xca542030, 0xca542034, 0xca542038, + 0xca54203c, 0xca542040, 0xca542044, 0xca542048, + 0xca54204c, 0xca542050, 0xca542054, 0xca542058, + 0xca54205c, 0xca542060, 0xca542064, 0xcbf02000, + 0xcbf02004, 0xcbf02008, 0xcbf0200c, 0xcbf02010, + 0xcbf02014, 0xcbf02018, 0xcbf0201c, 0xcbf02020, + 0xcbf02024, 0xcbf02028, 0xcbf0202c, 0xcbf02030, + 0xcbf02034, 0xcbf02038, 0xcbf0203c, 0xcbf02040, + 0xcbf02044, 0xcbf02048, 0xcbf0204c, 0xcbf02050, + 0xcbf02054, 0xcbf02058, 0xcbf0205c, 0xcbf02060, + 0xcbf02064, 0xcbf02068, 0xcbf0206c, 0xcbf02070, + 0xcbf02074, 0xcbf02078, 0xcbf0207c, 0xcbf02080, + 0xcbf02084, 0xcbf02088, 0xcbf0208c, 0xcbf02090, + 0xcbf02094, 0xcbf02098, 0xcbf0209c, 0xcbf020a0, + 0xcbf020a4, 0xcbf020a8, 0xcbf020ac, 0xcbf020b0, + 0xcbf020b4, 0xcbf020b8, 0xcbf020bc, 0xcbf020c0, + 0xcbf020c4, 0xcbf020c8, 0xcbf020cc, 0xcbf020d0, + 0xcbf020d4, 0xcbf020d8, 0xcbf020dc, 0xcbf020e0, + 0xcbf020e4, 0xcbf020e8, 0xcbf020ec, 0xcbf020f0, + 0xcbf020f4, 0xcbf020f8, 0xcbf020fc, 0xcbf02100, + 0xcbf02104, 0xcbf02108, 0xcbf0210c, 0xcbf02110, + 0xcbf02114, 0xcbf02118, 0xcbf0211c, 0xcbf02120, + 0xc9d02000, 0xc9d02004, 0xc9d02008, 0xc9d0200c, + 0xc9d02010, 0xc9d02014, 0xc9d02018, 0xc9d0201c, + 0xc9d02020, 0xc9d02024, 0xc9d02028, 0xc9d0202c, + 0xc9d02030, 0xc9d02034, 0xc9d02038, 0xc9d0203c, + 0xc9d02040, 0xc9d02044, 0xc9d02048, 0xc9d0204c, + 0xc9d02050, 0xc9d02054, 0xc9d02058, 0xc9d0205c, + 0xc9d02060, 0xc9d02064, 0xc9d02068, 0xc9d0206c, + 0xc9d02070, 0xc9d02074, 0xc9d02078, 0xc9d0207c, + 0xc9d02080, 0xc9d02084, 0xc9d02088, 0xc9d0208c, + 0xc9d02090, 0xc9d02094, 0xc9d02098, 0xc9d0209c, + 0xc9d020a0, 0xc9d020a4, 0xc9d020a8, 0xc9d020ac, + 0xc9d020b0, 0xc9d020b4, 0xc9d020b8, 0xc9d020bc, + 0xc9d020c0, 0xc9d020c4, 0xc9d020c8, 0xc9d020cc, + 0xc9d020d0, 0xc9d020d4, 0xc9d020d8, 0xc9d020dc, + 0xc9d020e0, 0xc9d020e4, 0xc9d020e8, 0xc9d020ec, + 0xc9d020f0, 0xc9d020f4, 0xc9d020f8, 0xc9d020fc, + 0xc9d02100, 0xc9d02104, 0xc9d02108, 0xc9d0210c, + 0xc9d02110, 0xc9d02114, 0xc9d02118, 0xc9d0211c, + 0xc9d02120, 0xc9d02124, 0xc9d02128, 0xc9d0212c, + 0xc9d02130, 0xc9d02134, 0xc9d02138, 0xc9d0213c, + 0xc9d02140, 0xc9d02144, 0xc9d02148, 0xc9d0214c, + 0xc9d02150, 0xc9d02154, 0xc9d02158, 0xc9d0215c, + 0xc9d02160, 0xc9d02164, 0xc9d02168, 0xc9d0216c, + 0xc9d02170, 0xc9d02174, 0xc9d02178, 0xc9d0217c, + 0xc9d02180, 0xc9d02184, 0xc9d02188, 0xc9d0218c, + 0xc9d02190, 0xc9d02194, 0xc9d02198, 0xde802000, + 0xde802004, 0xde802008, 0xde80200c, 0xde802010, + 0xde802014, 0xde802018, 0xde80201c, 0xde802020, + 0xde802024, 0xde802028, 0xde80202c, 0xde802030, + 0xde802034, 0xde802038, 0xde80203c, 0xde802040, + 0xde802044, 0xde802048, 0xde80204c, 0xde802050, + 0xde802054, 0xde802058, 0xde80205c, 0xde802060, + 0xde802064, 0xde802068, 0xde80206c, 0xde802070, + 0xde802074, 0xde802078, 0xde80207c, 0xde802080, + 0xde802084, 0xde802088, 0xde80208c, 0xde802090, + 0xde802094, 0xde802098, 0xde80209c, 0xde8020a0, + 0xde8020a4, 0xde8020a8, 0xde8020ac, 0xde8020b0, + 0xde8020b4, 0xde8020b8, 0xde8020bc, 0xde8020c0, + 0xde8020c4, 0xde8020c8, 0xde8020cc, 0xde8020d0, + 0xde8020d4, 0xde8020d8, 0xde8020dc, 0xde8020e0, + 0xde8020e4, 0xde8020e8, 0xde8020ec, 0xde8020f0, + 0xde8020f4, 0xde8020f8, 0xde8020fc, 0xde802100, + 0xde802104, 0xde802108, 0xde80210c, 0xde802110, + 0xde802114, 0xde802118, 0xde80211c, 0xde802120, + 0xde802124, 0xde802128, 0xde80212c, 0xde802130, + 0xde802134, 0xde802138, 0xde80213c, 0xde802140, + 0xde802144, 0xde802148, 0xde80214c, 0xde802150, + 0xde802154, 0xde802158, 0xde80215c, 0xde802160, + 0xde802164, 0xde802168, 0xde80216c, 0xde802170, + 0xde802174, 0xde802178, 0xde80217c, 0xde802180, + 0xde802184, 0xde802188, 0xde80218c, 0xde802190, + 0xde802194, 0xde802198, 0xde80219c, 0xde8021a0, + 0xde8021a4, 0xde8021a8, 0xde8021ac, 0xde8021b0, + 0xde8021b4, 0xde8021b8, 0xde8021bc, 0xde8021c0, + 0xde8021c4, 0xde8021c8, 0xde8021cc, 0xde8021d0, + 0xde8021d4, 0xde8021d8, 0xde8021dc, 0xde8021e0, + 0xde8021e4, 0xde8021e8, 0xde8021ec, 0xde8021f0, + 0xde8021f4, 0xde8021f8, 0xde8021fc, 0xde802200, + 0xde802204, 0xde802208, 0xde80220c, 0xde802210, + 0xde802214, 0xde802218, 0xde80221c, 0xde802220, + 0xde802224, 0xde802228, 0xde80222c, 0xde802230, + 0xde802234, 0xde802238, 0xde80223c, 0xde802240, + 0xde802244, 0xde802248, 0xde80224c, 0xde802250, + 0xde802254, 0xde802258, 0xde80225c, 0xde802260, + 0xde802264, 0xde802268, 0xde80226c, 0xde802270, + 0xde802274, 0xde802278, 0xde80227c, 0xde802280, + 0xde802284, 0xde802288, 0xde80228c, 0xde802290, + 0xde802294, 0xde802298, 0xde80229c, 0xde8022a0, + 0xde8022a4, 0xde8022a8, 0xde8022ac, 0xde8022b0, + 0xde8022b4, 0xde8022b8, 0xde8022bc, 0xde8022c0, + 0xde8022c4, 0xde8022c8, 0xde8022cc, 0xde8022d0, + 0xde8022d4, 0xde8022d8, 0xde8022dc, 0xde8022e0, + 0xde8022e4, 0xde8022e8, 0xde8022ec, 0xde8022f0, + 0xde8022f4, 0xde8022f8, 0xde8022fc, 0xde802300, + 0xde802304, 0xde802308, 0xde80230c, 0xde802310, + 0xde802314, 0xde802318, 0xde80231c, 0xde802320, + 0xde802324, 0xde802328, 0xde80232c, 0xde802330, + 0xde802334, 0xde802338, 0xde80233c, 0xde802340, + 0xde802344, 0xde802348, 0xde80234c, 0xde802350, + 0xde802354, 0xde802358, 0xde80235c, 0xde802360, + 0xde802364, 0xde802368, 0xde80236c, 0xde802370, + 0xde802374, 0xde802378, 0xde80237c, 0xde802380, + 0xde802384, 0xde802388, 0xde80238c, 0xde802390, + 0xde802394, 0xde802398, 0xde80239c, 0xde8023a0, + 0xde8023a4, 0xde8023a8, 0xde8023ac, 0xde8023b0, + 0xde8023b4, 0xde8023b8, 0xde8023bc, 0xde8023c0, + 0xde8023c4, 0xde8023c8, 0xde8023cc, 0xde8023d0, + 0xde8023d4, 0xde8023d8, 0xde8023dc, 0xde8023e0, + 0xde8023e4, 0xde8023e8, 0xde8023ec, 0xde8023f0, + 0xde8023f4, 0xde8023f8, 0xde8023fc, 0xde802400, + 0xde802404, 0xde802408, 0xde80240c, 0xde802410, + 0xde802414, 0xde802418, 0xde80241c, 0xde802420, + 0xde802424, 0xde802428, 0xde80242c, 0xde802430, + 0xde802434, 0xde802438, 0xde80243c, 0xde802440, + 0xde802444, 0xde802448, 0xde80244c, 0xde802450, + 0xde802454, 0xde802458, 0xde80245c, 0xde802460, + 0xde802464, 0xde802468, 0xde80246c, 0xde802470, + 0xde802474, 0xde802478, 0xde80247c, 0xde802480, + 0xde802484, 0xde802488, 0xde80248c, 0xde802490, + 0xde802494, 0xde802498, 0xde80249c, 0xde8024a0, + 0xde8024a4, 0xde8024a8, 0xde8024ac, 0xde8024b0, + 0xde8024b4, 0xde8024b8, 0xc1a02000, 0xc1a02004, + 0xc1a02008, 0xc1a0200c, 0xc1a02010, 0xc1a02014, + 0xc1a02018, 0xc1a0201c, 0xc1a02020, 0xc1a02024, + 0xc1a02028, 0xc1a0202c, 0xc1a02030, 0xc1a02034, + 0xc1a02038, 0xc1a0203c, 0xc1a02040, 0xc1a02044, + 0xc1a02048, 0xc1a0204c, 0xc1a02050, 0xc1a02054, + 0xc1a02058, 0xc1a0205c, 0xc1a02060, 0xc1a02064, + 0xc1a02068, 0xc1a0206c, 0xc1a02070, 0xc1a02074, + 0xc1a02078, 0xc1a0207c, 0xc1a02080, 0xc1a02084, + 0xc1a02088, 0xc1a0208c, 0xc1a02090, 0xc1a02094, + 0xc1a02098, 0xc1a0209c, 0xc1a020a0, 0xc1e02000, + 0xc1e02004, 0xc1e02008, 0xc1e0200c, 0xc1e02010, + 0xc1e02014, 0xc1e02018, 0xc1e0201c, 0xc1e02020, + 0xc1e02024, 0xc1e02028, 0xc1e0202c, 0xc1e02030, + 0xc1e02034, 0xc1e02038, 0xc1e0203c, 0xc1e02040, + 0xc1e02044, 0xc1e02048, 0xc1e0204c, 0xc1e02050, + 0xc1e02054, 0xc1e02058, 0xc1e0205c, 0xc1e02060, + 0xc1e02064, 0xc1e02068, 0xc1e0206c, 0xc1e02070, + 0xc1e02074, 0xc1e02078, 0xc1e0207c, 0xc1e02080, + 0xc1e02084, 0xc1e02088, 0xc1e0208c, 0xc1e02090, + 0xc1e02094, 0xc1e02098, 0xc1e0209c, 0xc1e020a0, + 0xe9a02000, 0xe9a02004, 0xe9a02008, 0xe9a0200c, + 0xe9a02010, 0xe9a02014, 0xe9a02018, 0xe9a0201c, + 0xe9a02020, 0xe9a02024, 0xe9a02028, 0xe9a0202c, + 0xe9a02030, 0xe9a02034, 0xe9a02038, 0xe9a0203c, + 0xe9a02040, 0xe9a02044, 0xe9a02048, 0xe9a0204c, + 0xe9a02050, 0xe9a02054, 0xe9a02058, 0xe9a0205c, + 0xe9a02060, 0xe9a02064, 0xe9a02068, 0xe9a0206c, + 0xe9a02070, 0xe9a02074, 0xe9a02078, 0xe9a0207c, + 0xe9a02080, 0xe9a02084, 0xe9a02088, 0xe9a0208c, + 0xe9a02090, 0xe9a02094, 0xe9a02098, 0xe9a0209c, + 0xe9a020a0, 0xe9a020a4, 0xe9a020a8, 0xe9a020ac, + 0xe9a020b0, 0xe9a020b4, 0xe9a020b8, 0xe9a020bc, + 0xe9a020c0, 0xe9a020c4, 0xe9a020c8, 0xe9a020cc, + 0xe9a020d0, 0xe9a020d4, 0xe9a020d8, 0xe9a020dc, + 0xe9a020e0, 0xe9a020e4, 0xe9a020e8, 0xe9a020ec, + 0xe9a020f0, 0xe9a020f4, 0xe9a020f8, 0xe9a020fc, + 0xe9a02100, 0xe9a02104, 0xe9a02108, 0xe9a0210c, + 0xe9a02110, 0xe9a02114, 0xe9a02118, 0xe9a0211c, + 0xe9a02120, 0xe9a02124, 0xe9a02128, 0xe9a0212c, + 0xe9a02130, 0xe9a02134, 0xe9a02138, 0xe9a0213c, + 0xe9a02140, 0xe9a02144, 0xe9a02148, 0xe9a0214c, + 0xe9a02150, 0xe9a02154, 0xe9a02158, 0xe9a0215c, + 0xe9a02160, 0xe9a02164, 0xe9a02168, 0xe9a0216c, + 0xe9a02170, 0xe9a02174, 0xe9a02178, 0xe9a0217c, + 0xe9a02180, 0xe9a02184, 0xe9a02188, 0xe9a0218c, + 0xe9a02190, 0xe9a02194, 0xe9a02198, 0xe9a0219c, + 0xe9a021a0, 0xe9a021a4, 0xe9a021a8, 0xe9a021ac, + 0xe9a021b0, 0xe9a021b4, 0xe9a021b8, 0xe9a021bc, + 0xe9a021c0, 0xe9a021c4, 0xe9a021c8, 0xe9a021cc, + 0xe9a021d0, 0xe9a021d4, 0xe9a021d8, 0xe9a021dc, + 0xe9a021e0, 0xe9a021e4, 0xe9a021e8, 0xe9a021ec, + 0xe9a021f0, 0xe9a021f4, 0xe9a021f8, 0xe9a021fc, + 0xe9a02200, 0xe9a02204, 0xe9a02208, 0xe9a0220c, + 0xe9a02210, 0xe9a02214, 0xe9a02218, 0xe9a0221c, + 0xe9a02220, 0xe9a02224, 0xe9a02228, 0xe9a0222c, + 0xe9a02230, 0xe9a02234, 0xe9a02238, 0xe9a0223c, + 0xe9a02240, 0xe9a02244, 0xe9a02248, 0xe9a0224c, + 0xe9a02250, 0xe9a02254, 0xe9a02258, 0xe9a0225c, + 0xe9a02260, 0xe9a02264, 0xe9a02268, 0xe9a0226c, + 0xe9a02270, 0xe9a02274, 0xe9a02278, 0xe9a0227c, + 0xe9a02280, 0xe9a02284, 0xd2f02000, 0xd2f02004, + 0xd2f02008, 0xd2f0200c, 0xd2f02010, 0xd2f02014, + 0xd2f02018, 0xd2f0201c, 0xd2f02020, 0xd2f02024, + 0xd2f02028, 0xd2f0202c, 0xd2f02030, 0xd2f02034, + 0xd2f02038, 0xd2f0203c, 0xd2f02040, 0xd2f02044, + 0xd2f02048, 0xd2f0204c, 0xd2f02050, 0xd2f02054, + 0xd2f02058, 0xd2f0205c, 0xd2f02060, 0xd2f02064, + 0xd2f02068, 0xd2f0206c, 0xd2f02070, 0xd2f02074, + 0xd2f02078, 0xd2f0207c, 0xd2f02080, 0xd2f02084, + 0xd2f02088, 0xd2f0208c, 0xd2f02090, 0xd2f02094, + 0xd2f02098, 0xd2f0209c, 0xd2f020a0, 0xd2f020a4, + 0xd2f020a8, 0xd2f020ac, 0xd2f020b0, 0xd2f020b4, + 0xd2f020b8, 0xd2f020bc, 0xd2f020c0, 0xd2f020c4, + 0xd2f020c8, 0xd2f020cc, 0xd2f020d0, 0xd2f020d4, + 0xd2f020d8, 0xd2f020dc, 0xd6f02000, 0xd6f02004, + 0xd6f02008, 0xd6f0200c, 0xd6f02010, 0xd6f02014, + 0xd6f02018, 0xd6f0201c, 0xd6f02020, 0xd6f02024, + 0xd6f02028, 0xd6f0202c, 0xd6f02030, 0xd6f02034, + 0xd6f02038, 0xd6f0203c, 0xd6f02040, 0xd6f02044, + 0xd6f02048, 0xd6f0204c, 0xd6f02050, 0xd6f02054, + 0xd6f02058, 0xd6f0205c, 0xd6f02060, 0xd6f02064, + 0xd6f02068, 0xd6f0206c, 0xd6f02070, 0xd6f02074, + 0xd6f02078, 0xd6f0207c, 0xd6f02080, 0xd6f02084, + 0xd6f02088, 0xd6f0208c, 0xd6f02090, 0xd6f02094, + 0xd6f02098, 0xd6f0209c, 0xd6f020a0, 0xd6f020a4, + 0xd6f020a8, 0xd6f020ac, 0xd6f020b0, 0xd6f020b4, + 0xd6f020b8, 0xd6f020bc, 0xd6f020c0, 0xd6f020c4, + 0xd6f020c8, 0xd6f020cc, 0xd6f020d0, 0xd6f020d4, + 0xd6f020d8, 0xd6f020dc, 0xc0982000, 0xc0982004, + 0xc0982008, 0xc098200c, 0xc0982010, 0xc0982014, + 0xc0982018, 0xc098201c, 0xc0982020, 0xc0982024, + 0xc0982028, 0xc098202c, 0xc0982030, 0xc0982034, + 0xc0982038, 0xc098203c, 0xc0982040, 0xc0982044, + 0xc0982048, 0xc098204c, 0xc0982050, 0xc0982054, + 0xc0982058, 0xc098205c, 0xc0982060, 0xc0982064, + 0xc0982068, 0xc098206c, 0xc0982070, 0xc0982074, + 0xc0982078, 0xc098207c, 0xc0982080, 0xc0982084, + 0xc0982088, 0xc098208c, 0xc0982090, 0xc0982094, + 0xc0982098, 0xc098209c, 0xc09820a0, 0xc09820a4, + 0xc09820a8, 0xc09820ac, 0xc09820b0, 0xc09820b4, + 0xc09820b8, 0xc09820bc, 0xc09820c0, 0xc09820c4, + 0xc09820c8, 0xc09820cc, 0xc09820d0, 0xc09820d4, + 0xc09820d8, 0xc09820dc, 0xc09820e0, 0xc09820e4, + 0xc09820e8, 0xc09820ec, 0xc09820f0, 0xc09820f4, + 0xc09820f8, 0xc09820fc, 0xc0982100, 0xc0982104, + 0xc0982108, 0xc098210c, 0xc0982110, 0xc0982114, + 0xc0982118, 0xc098211c, 0xc0982120, 0xc0982124, + 0xc0982128, 0xc098212c, 0xc0982130, 0xc0982134, + 0xc0982138, 0xc098213c, 0xc0982140, 0xc0982144, + 0xc0982148, 0xc098214c, 0xc0982150, 0xc0982154, + 0xc0982158, 0xc098215c, 0xc0982160, 0xc0982164, + 0xc0982168, 0xc098216c, 0xc0982170, 0xc0982174, + 0xc0982178, 0xc098217c, 0xc0982180, 0xc0982184, + 0xc0982188, 0xc098218c, 0xc0982190, 0xc0982194, + 0xc0982198, 0xc098219c, 0xc09821a0, 0xc09821a4, + 0xc09821a8, 0xc09821ac, 0xc09821b0, 0xc09821b4, + 0xc09821b8, 0xc09821bc, 0xc09821c0, 0xc09821c4, + 0xc09821c8, 0xc09821cc, 0xc09821d0, 0xc09821d4, + 0xc09821d8, 0xc09821dc, 0xc09821e0, 0xc09821e4, + 0xc09821e8, 0xc09821ec, 0xc09821f0, 0xc09821f4, + 0xc09821f8, 0xc09821fc, 0xc0582000, 0xc0582004, + 0xc0582008, 0xc058200c, 0xc0582010, 0xc0582014, + 0xc0582018, 0xc058201c, 0xc0582020, 0xc0582024, + 0xc0582028, 0xc058202c, 0xc0582030, 0xc0582034, + 0xc0582038, 0xc058203c, 0xc0582040, 0xc0582044, + 0xc0582048, 0xc058204c, 0xc0582050, 0xc0582054, + 0xc0582058, 0xc058205c, 0xc0582060, 0xc0582064, + 0xc0582068, 0xc058206c, 0xc0582070, 0xc0582074, + 0xc0582078, 0xc058207c, 0xc0582080, 0xc0582084, + 0xc0582088, 0xc058208c, 0xc0582090, 0xc0582094, + 0xc0582098, 0xc058209c, 0xc05820a0, 0xc05820a4, + 0xc05820a8, 0xc05820ac, 0xc05820b0, 0xc05820b4, + 0xc05820b8, 0xc05820bc, 0xc05820c0, 0xc05820c4, + 0xc05820c8, 0xc05820cc, 0xc05820d0, 0xc05820d4, + 0xc05820d8, 0xc05820dc, 0xc05820e0, 0xc05820e4, + 0xc05820e8, 0xc05820ec, 0xc05820f0, 0xc05820f4, + 0xc05820f8, 0xc05820fc, 0xc0582100, 0xc0582104, + 0xc0582108, 0xc058210c, 0xc0582110, 0xc0582114, + 0xc0582118, 0xc058211c, 0xc0582120, 0xc0582124, + 0xc0582128, 0xc058212c, 0xc0582130, 0xc0582134, + 0xc0582138, 0xc058213c, 0xc0582140, 0xc0582144, + 0xc0582148, 0xc058214c, 0xc0582150, 0xc0582154, + 0xc0582158, 0xc058215c, 0xc0582160, 0xc0582164, + 0xc0582168, 0xc058216c, 0xc0582170, 0xc0582174, + 0xc0582178, 0xc058217c, 0xc0582180, 0xc0582184, + 0xc0582188, 0xc058218c, 0xc0582190, 0xc0582194, + 0xc0582198, 0xc058219c, 0xc05821a0, 0xc05821a4, + 0xc05821a8, 0xc05821ac, 0xc05821b0, 0xc05821b4, + 0xc05821b8, 0xc05821bc, 0xc05821c0, 0xc05821c4, + 0xc05821c8, 0xc05821cc, 0xc05821d0, 0xc05821d4, + 0xc05821d8, 0xc05821dc, 0xc05821e0, 0xc05821e4, + 0xc05821e8, 0xc05821ec, 0xc05821f0, 0xc05821f4, + 0xc05821f8, 0xc05821fc, 0xc0582200, 0xc0582204, + 0xc0582208, 0xc058220c, 0xc0582210, 0xc0582214, + 0xc0582218, 0xc058221c, 0xc0582220, 0xc0582224, + 0xc0582228, 0xc058222c, 0xc0582230, 0xc0582234, + 0xc0582238, 0xc058223c, 0xc0582240, 0xc0582244, + 0xc0582248, 0xc058224c, 0xcb402000, 0xcb402004, + 0xcb402008, 0xcb40200c, 0xcb402010, 0xcb402014, + 0xcb402018, 0xcb40201c, 0xcb402020, 0xcb402024, + 0xcb402028, 0xcb40202c, 0xcb402030, 0xcb402034, + 0xcb402038, 0xcb40203c, 0xcb402040, 0xcb402044, + 0xcb402048, 0xcb40204c, 0xcb402050, 0xcb402054, + 0xcb402058, 0xcb40205c, 0xcb402060, 0xcb402064, + 0xcb402068, 0xcb40206c, 0xcb402070, 0xcb402074, + 0xcb402078, 0xcb40207c, 0xcb402080, 0xcb402084, + 0xcb402088, 0xcb40208c, 0xcb402090, 0xcb402094, + 0xcb402098, 0xcb40209c, 0xcb4020a0, 0xcb4020a4, + 0xcb4020a8, 0xcb4020ac, 0xcb4020b0, 0xcb4020b4, + 0xcb4020b8, 0xcb4020bc, 0xcb4020c0, 0xcb4020c4, + 0xcb4020c8, 0xcb4020cc, 0xcb4020d0, 0xcb4020d4, + 0xcb4020d8, 0x1a802000, 0x1a802004, 0x1a802008, + 0x1a80200c, 0x1a802010, 0x1a802014, 0x1a802018, + 0x1a80201c, 0x1a802020, 0x1a802024, 0x1a802028, + 0x1a80202c, 0x1a802030, 0x1a802034, 0x1a802038, + 0x1a80203c, 0x1a802040, 0x1a802044, 0x1a802048, + 0x1a80204c, 0x1a802050, 0x1a802054, 0x1a802058, + 0x1a80205c, 0x1a802060, 0x1a802064, 0x1a802068, + 0x1a80206c, 0x1a802070, 0x1a802074, 0x1a802078, + 0x1a80207c, 0x1a802080, 0x1a802084, 0x1a802088, + 0x1a80208c, 0x1a802090, 0x1a802094, 0x1a802098, + 0x1a80209c, 0x1a8020a0, 0x1a8020a4, 0x1a8020a8, + 0x1a8020ac, 0x1a8020b0, 0x1a8020b4, 0x1a8020b8, + 0x1a8020bc, 0x1a8020c0, 0x1a8020c4, 0x1a8020c8, + 0x1a8020cc, 0x1a8020d0, 0x1a8020d4, 0x1a8020d8, + 0x1a8020dc, 0x1a8020e0, 0x1a8020e4, 0x1a8020e8, + 0x1a8020ec, 0x1a8020f0, 0x1a8020f4, 0x1a8020f8, + 0x1a8020fc, 0x1a802100, 0x1a802104, 0x1a802108, + 0x1a80210c, 0x1a802110, 0x1a802114, 0x1a802118, + 0x1a80211c, 0x1a802120, 0x1a802124, 0x1a802128, + 0x1a80212c, 0x1a802130, 0x1a802134, 0x1a802138, + 0x1a80213c, 0x1a802140, 0x1a802144, 0x1a802148, + 0x1a80214c, 0x1a802150, 0x1a802154, 0x1a802158, + 0x1a80215c, 0x1a802160, 0x1a802164, 0x1a802168, + 0x1a80216c, 0x1a802170, 0x1a802174, 0x1a802178, + 0x1a80217c, 0x1a802180, 0x1a802184, 0x1a802188, + 0x1a80218c, 0x1a802190, 0x1a802194, 0x1a802198, + 0x1a80219c, 0x1a8021a0, 0x1a8021a4, 0x1a8021a8, + 0x1a8021ac, 0x1a8021b0, 0x1a8021b4, 0x1a8021b8, + 0x1a8021bc, 0x1a8021c0, 0x1a8021c4, 0x1a8021c8, + 0x1a8021cc, 0x1a8021d0, 0x1a8021d4, 0x1a8021d8, + 0x1a8021dc, 0x1a8021e0, 0x1a8021e4, 0x1a8021e8, + 0x1a8021ec, 0x1a8021f0, 0x1a8021f4, 0x1a8021f8, + 0x1a8021fc, 0x1a802200, 0x1a802204, 0x1a802208, + 0x1a80220c, 0x1a802210, 0x1a802214, 0x1a802218, + 0x1a80221c, 0x1a802220, 0x1a802224, 0x1a802228, + 0x1a80222c, 0x1a802230, 0x1a802234, 0x1a802238, + 0x1a80223c, 0x1a802240, 0x1a802244, 0x1a802248, + 0x1a80224c, 0x1a802250, 0x1a802254, 0x1a802258, + 0x1a80225c, 0x1a802260, 0x1a802264, 0x1a802268, + 0x1a80226c, 0x1a802270, 0x1a802274, 0x1a802278, + 0x1a80227c, 0x1a802280, 0x1a802284, 0x1a802288, + 0x1a80228c, 0x1a802290, 0x1a802294, 0x1a802298, + 0x1a80229c, 0x1a8022a0, 0x1a8022a4, 0x1a8022a8, + 0x1a8022ac, 0x1a8022b0, 0x1a8022b4, 0x1a8022b8, + 0x1a8022bc, 0x1a8022c0, 0x1a8022c4, 0x1a8022c8, + 0x1a8022cc, 0x1a8022d0, 0x1a8022d4, 0x1a8022d8, + 0x1a8022dc, 0x1a8022e0, 0x1a8022e4, 0x1a8022e8, + 0x1a8022ec, 0x1a8022f0, 0x1a8022f4, 0x1a8022f8, + 0x1a8022fc, 0x1a802300, 0x1a802304, 0x1a802308, + 0x1a80230c, 0x1a802310, 0x1a802314, 0x1a802318, + 0x1a80231c, 0x1a802320, 0x1a802324, 0x1a802328, + 0x1a80232c, 0x1a802330, 0x1a802334, 0x1a802338, + 0x1a80233c, 0x1a802340, 0x1a802344, 0x1a802348, + 0x1a80234c, 0x1a802350, 0x1a802354, 0x1a802358, + 0x1a80235c, 0x1a802360, 0x1a802364, 0x1a802368, + 0x1a80236c, 0x1a802370, 0x1a802374, 0x1a802378, + 0x1a80237c, 0x1a802380, 0x1a802384, 0x1a802388, + 0x1a80238c, 0x1a802390, 0x1a802394, 0x1a802398, + 0x1a80239c, 0x1a8023a0, 0x1a8023a4, 0x1a8023a8, + 0x1a8023ac, 0x1a8023b0, 0x1a8023b4, 0x1a8023b8, + 0x1a8023bc, 0x1a8023c0, 0x1a8023c4, 0x1a8023c8, + 0x1a8023cc, 0x1a8023d0, 0x1a8023d4, 0x1a8023d8, + 0x1a8023dc, 0x1a8023e0, 0x1a8023e4, 0x1a8023e8, + 0x1a8023ec, 0x1a8023f0, 0x1a8023f4, 0x1a8023f8, + 0x1a8023fc, 0x1a802400, 0x1a802404, 0x1a802408, + 0x1a80240c, 0x1a802410, 0x1a802414, 0x1a802418, + 0x1a80241c, 0x1a802420, 0x1a802424, 0x1a802428, + 0x1a80242c, 0x1a802430, 0x1a802434, 0x1a802438, + 0x1a80243c, 0x1a802440, 0x1a802444, 0x1a802448, + 0x1a80244c, 0x1a802450, 0x1a802454, 0x1a802458, + 0x1a80245c, 0x1a802460, 0x1a802464, 0x1a802468, + 0x1a80246c, 0x1a802470, 0x1a802474, 0x1a802478, + 0x1a80247c, 0x1a802480, 0x1a802484, 0x1a802488, + 0x1a80248c, 0x1a802490, 0x1a802494, 0x1a802498, + 0x1a80249c, 0x1a8024a0, 0x1a8024a4, 0x1a8024a8, + 0x1a8024ac, 0x1a8024b0, 0x1a8024b4, 0x1a8024b8, + 0x1a8024bc, 0x1a8024c0, 0x1a8024c4, 0x1a8024c8, + 0x1a8024cc, 0x1a8024d0, 0x1a8024d4, 0x1a8024d8, + 0x1a8024dc, 0x1a8024e0, 0x1a8024e4, 0x1a8024e8, + 0x1a8024ec, 0x1a8024f0, 0x1a8024f4, 0x1a8024f8, + 0x1a8024fc, 0x1a802500, 0x1a802504, 0x1a802508, + 0x1a80250c, 0x1a802510, 0x1a802514, 0x1a802518, + 0x1a80251c, 0x1a802520, 0x1a802524, 0x1a802528, + 0x1a80252c, 0x1a802530, 0x1a802534, 0x1a802538, + 0x1a80253c, 0x1a802540, 0x1a802544, 0x1a802548, + 0x1a80254c, 0x1a802550, 0x1a802554, 0x1a802558, + 0x1a80255c, 0x1a802560, 0x1a802564, 0x1a802568, + 0x1a80256c, 0x1a802570, 0x1a802574, 0x1a802578, + 0x1a80257c, 0x1a802580, 0x1a802584, 0x1a802588, + 0x1a80258c, 0x1a802590, 0x1a802594, 0x1a802598, + 0x1a80259c, 0x1a8025a0, 0x1a8025a4, 0x1a8025a8, + 0x1a8025ac, 0x1a8025b0, 0x1a8025b4, 0x1a8025b8, + 0x1a8025bc, 0x1a8025c0, 0x1a8025c4, 0x1a8025c8, + 0x1a8025cc, 0x1a8025d0, 0x1a8025d4, 0x1a8025d8, + 0x18b42000, 0x18b42004, 0x18b42008, 0x18b4200c, + 0x18b42010, 0x18b42014, 0x18b42018, 0x18b4201c, + 0x18b42020, 0x18b42024, 0x18b42028, 0x18b4202c, + 0x18b42030, 0x18b42034, 0x18b42038, 0x18b4203c, + 0x18b42040, 0x18b42044, 0x18b42048, 0x18b4204c, + 0x18b42050, 0x18b42054, 0x18b42058, 0x18b4205c, + 0x18b42060, 0x18b42064, 0x18b42068, 0x18b4206c, + 0x18b42070, 0x18b42074, 0x18b42078, 0x18b4207c, + 0x18b42080, 0x18b42084, 0x18b42088, 0x18b4208c, + 0x18b42090, 0x18b42094, 0x18b42098, 0x18b4209c, + 0x18b420a0, 0x18b420a4, 0x18b420a8, 0x18b420ac, + 0x18b420b0, 0x18b420b4, 0x18b420b8, 0x18b420bc, + 0x18b420c0, 0x18b420c4, 0x18b420c8, 0x18b420cc, + 0x18b420d0, 0x18b420d4, 0x18b420d8, 0x18b420dc, + 0x18b420e0, 0x18b420e4, 0x18b420e8, 0x18b420ec, + 0x18b420f0, 0x18b420f4, 0x18b420f8, 0x18b420fc, + 0x18b42100, 0x18b42104, 0x18b42108, 0x18b4210c, + 0x18b42110, 0x18b42114, 0x18b42118, 0x18b4211c, + 0x18b42120, 0x18b42124, 0x18b42128, 0x18b4212c, + 0x18b42130, 0x18b42134, 0x18b42138, 0x18b4213c, + 0x18b42140, 0x18b42144, 0x18b42148, 0x18b4214c, + 0x18b42150, 0x18b42154, 0x18b42158, 0x18b4215c, + 0x18b42160, 0x18b42164, 0x18b42168, 0x18b4216c, + 0x18b42170, 0x18b42174, 0x18b42178, 0x18b4217c, + 0x18b42180, 0x18b42184, 0x18b42188, 0x18b4218c, + 0x18b42190, 0x18b42194, 0x18b42198, 0x18b4219c, + 0x18b421a0, 0x18b421a4, 0x18b421a8, 0x18b421ac, + 0x18b421b0, 0x18b421b4, 0x18b421b8, 0x18b421bc, + 0x18b421c0, 0x18b421c4, 0x18b421c8, 0x18b421cc, + 0x18b421d0, 0x18b421d4, 0x18b421d8, 0x18b421dc, + 0x18b421e0, 0x18b421e4, 0x18b421e8, 0x18b421ec, + 0x18b421f0, 0x18b421f4, 0x18b421f8, 0x18b421fc, + 0x18b42200, 0x18b42204, 0x18b42208, 0x18b4220c, + 0x18b42210, 0x18b42214, 0x18b42218, 0x18b4221c, + 0x18b42220, 0x18b42224, 0x18b42228, 0x18b4222c, + 0x18b42230, 0xc1282000, 0xc1282004, 0xc1282008, + 0xc128200c, 0xc1282010, 0xc1282014, 0xc1282018, + 0xc128201c, 0xc1282020, 0xc1282024, 0xc1282028, + 0xc128202c, 0xc1282030, 0xc1282034, 0xc1282038, + 0xc128203c, 0xc1282040, 0xc1282044, 0xc1282048, + 0xc128204c, 0xc1282050, 0xc1282054, 0xc1282058, + 0xc128205c, 0xc1282060, 0xc1282064, 0xc1282068, + 0xc128206c, 0xc1282070, 0xc1282074, 0xc1282078, + 0xc128207c, 0xc1282080, 0xc1282084, 0xc1282088, + 0xc128208c, 0xc1282090, 0xc1282094, 0xc1282098, + 0xc128209c, 0xc12820a0, 0xc12820a4, 0xc12820a8, + 0xc12820ac, 0xc12820b0, 0xc12820b4, 0xc12820b8, + 0xc12820bc, 0xc12820c0, 0xc12820c4, 0xc12820c8, + 0xc12820cc, 0xc12820d0, 0xc12820d4, 0xc12820d8, + 0xc12820dc, 0xc12820e0, 0xc12820e4, 0xc12820e8, + 0xc12820ec, 0xc12820f0, 0xc12820f4, 0xc12820f8, + 0xc12820fc, 0xc1282100, 0xc1282104, 0xc1282108, + 0xc128210c, 0xc1282110, 0xc1282114, 0xc1282118, + 0xc128211c, 0xc1282120, 0xc1282124, 0xc1282128, + 0xc128212c, 0xc1282130, 0xc1282134, 0xc1282138, + 0xc128213c, 0xc1282140, 0xc1282144, 0xc1282148, + 0xc128214c, 0xc1282150, 0xc1282154, 0xc1282158, + 0xc128215c, 0xc1282160, 0xc1282164, 0xc1282168, + 0xc128216c, 0xc1282170, 0xc1282174, 0xc1282178, + 0xc128217c, 0xc1282180, 0xc1282184, 0xc1282188, + 0xc128218c, 0xc1282190, 0xc1282194, 0xc1282198, + 0xc128219c, 0xc12821a0, 0xc12821a4, 0xc12821a8, + 0xc12821ac, 0xc12821b0, 0xc12821b4, 0xc12821b8, + 0xc12821bc, 0xc12821c0, 0xc12821c4, 0xc12821c8, + 0xc12821cc, 0xc12821d0, 0xc12821d4, 0xc12821d8, + 0xc12821dc, 0xc12821e0, 0xc12821e4, 0xc12821e8, + 0xc12821ec, 0xc12821f0, 0xc12821f4, 0xc12821f8, + 0xc12821fc, 0xc1282200, 0xc1282204, 0xc1282208, + 0xc128220c, 0xc1282210, 0xc1282214, 0xc1282218, + 0xc128221c, 0xc1282220, 0xc1282224, 0xc1282228, + 0xc128222c, 0xc1282230, 0xc1282234, 0xc1282238, + 0xc128223c, 0xc1282240, 0xc1282244, 0xc1282248, + 0xc128224c, 0xc1282250, 0xc1282254, 0xc1282258, + 0xc128225c, 0xc1282260, 0xc1282264, 0xc1282268, + 0xc128226c, 0xc1282270, 0xc1282274, 0xc1282278, + 0xc128227c, 0xc1282280, 0xc1282284, 0xc1282288, + 0xc128228c, 0xc1282290, 0xc1282294, 0xc1282298, + 0xc128229c, 0xc12822a0, 0xc12822a4, 0xc12822a8, + 0xc12822ac, 0xc12822b0, 0xc12822b4, 0xc12822b8, + 0xc6802000, 0xc6802004, 0xc6802008, 0xc680200c, + 0xc6802010, 0xc6802014, 0xc6802018, 0xc680201c, + 0xc6802020, 0xc6802024, 0xc6802028, 0xc680202c, + 0xc6802030, 0xc6802034, 0xc6802038, 0xc680203c, + 0xc6802040, 0xc6802044, 0xc6802048, 0xc680204c, + 0xc6802050, 0xc6802054, 0xc6802058, 0xc680205c, + 0xc6802060, 0xc6802064, 0xc6802068, 0xc680206c, + 0xc6802070, 0xc6802074, 0xc6802078, 0xc680207c, + 0xc6802080, 0xc6802084, 0xc6802088, 0xc680208c, + 0xc6802090, 0xc6802094, 0xc6802098, 0xc680209c, + 0xc68020a0, 0xc68020a4, 0xc68020a8, 0xc68020ac, + 0xc68020b0, 0xc68020b4, 0xc68020b8, 0xc68020bc, + 0xc68020c0, 0xc68020c4, 0xc68020c8, 0xc68020cc, + 0xc5802000, 0xc5802004, 0xc5802008, 0xc580200c, + 0xc5802010, 0xc5802014, 0xc5802018, 0xc580201c, + 0xc5802020, 0xc5802024, 0xc5802028, 0xc580202c, + 0xc5802030, 0xc5802034, 0xc5802038, 0xc580203c, + 0xc5802040, 0xc5802044, 0xc5802048, 0xc580204c, + 0xc5802050, 0xc5802054, 0xc5802058, 0xc580205c, + 0xc5802060, 0xc5802064, 0xc5802068, 0xc580206c, + 0xc5802070, 0xc5802074, 0xc5802078, 0xc580207c, + 0xc5802080, 0xc5802084, 0xc5802088, 0xc580208c, + 0xc5802090, 0xc5802094, 0xc5802098, 0xc580209c, + 0xc58020a0, 0xc58020a4, 0xc58020a8, 0xc58020ac, + 0xc58020b0, 0xc58020b4, 0xc58020b8, 0xc58020bc, + 0xc58020c0, 0xc58020c4, 0xc58020c8, 0xc58020cc, + 0xc58020d0, 0xc58020d4, 0xc58020d8, 0xc58020dc, + 0xc58020e0, 0xc58020e4, 0xc58020e8, 0xc58020ec, + 0xc58020f0, 0xc58020f4, 0xc58020f8, 0xc58020fc, + 0xc5802100, 0xc5802104, 0xc5802108, 0xc580210c, + 0xc5802110, 0xc5802114, 0xc5802118, 0xc580211c, + 0xc5802120, 0xc5802124, 0xc5802128, 0xc580212c, + 0xc5802130, 0xc5802134, 0xc5802138, 0xc580213c, + 0xc5802140, 0xc5802144, 0xc5802148, 0xc580214c, + 0xc5802150, 0xc5802154, 0xc5802158, 0xc580215c, + 0xc5802160, 0xc5802164, 0xc5802168, 0xc580216c, + 0xc5802170, 0xc5802174, 0xc5802178, 0xc580217c, + 0xc5802180, 0xc5802184, 0xc5802188, 0xc580218c, + 0xc5802190, 0xc5802194, 0xc5802198, 0xc580219c, + 0xc58021a0, 0xc58021a4, 0xc58021a8, 0xc58021ac, + 0xc58021b0, 0xc58021b4, 0xc58021b8, 0xc58021bc, + 0xc58021c0, 0xc58021c4, 0xc58021c8, 0xc58021cc, + 0xc58021d0, 0xc58021d4, 0xc58021d8, 0xc58021dc, + 0xc58021e0, 0xc58021e4, 0xc58021e8, 0xc58021ec, + 0xc58021f0, 0xc58021f4, 0xc58021f8, 0xc58021fc, + 0xc5802200, 0xc5802204, 0xc5802208, 0xc580220c, + 0xc5802210, 0xc5802214, 0xc5802218, 0xc580221c, + 0xc5802220, 0xc5802224, 0xc5802228, 0xc580222c, + 0xc5802230, 0xc5802234, 0xc5802238, 0xc580223c, + 0xc5802240, 0xc5802244, 0xc5802248, 0xc580224c, + 0xc5802250, 0xc5802254, 0xc5802258, 0xc580225c, + 0xc5802260, 0xc5802264, 0xc5802268, 0xc580226c, + 0xc5802270, 0xc5802274, 0xc5802278, 0xc580227c, + 0xc5802280, 0xc5802284, 0xc5802288, 0xc580228c, + 0xc5802290, 0xc5802294, 0xc5802298, 0xc580229c, + 0xc58022a0, 0xc58022a4, 0xc58022a8, 0xc58022ac, + 0xc58022b0, 0xc58022b4, 0xc58022b8, 0xc58022bc, + 0xc58022c0, 0xc58022c4, 0xc58022c8, 0xc58022cc, + 0xc58022d0, 0xc58022d4, 0xc58022d8, 0xc58022dc, + 0xc58022e0, 0xc58022e4, 0xc58022e8, 0xc58022ec, + 0xc58022f0, 0xc58022f4, 0xc58022f8, 0xc58022fc, + 0xc5802300, 0xc5802304, 0xc5802308, 0xc580230c, + 0xc3022000, 0xc3022004, 0xc3022008, 0xc302200c, + 0xc3022010, 0xc3022014, 0xc3022018, 0xc302201c, + 0xc3022020, 0xc3022024, 0xc3022028, 0xc302202c, + 0xc3022030, 0xc3022034, 0xc3022038, 0xc302203c, + 0xc3022040, 0xc3022044, 0xc3022048, 0xc302204c, + 0xc3022050, 0xc3022054, 0xc3022058, 0xc302205c, + 0xc3022060, 0xc3022064, 0xc3022068, 0xc302206c, + 0xc3022070, 0xc3022074, 0xc3022078, 0xc302207c, + 0xc3022080, 0xc3022084, 0xc3022088, 0xc302208c, + 0xc3022090, 0xc3022094, 0xc3022098, 0xc302209c, + 0xc30220a0, 0xc30220a4, 0xc30220a8, 0xc30220ac, + 0xc30220b0, 0xc3422000, 0xc3422004, 0xc3422008, + 0xc342200c, 0xc3422010, 0xc3422014, 0xc3422018, + 0xc342201c, 0xc3422020, 0xc3422024, 0xc3422028, + 0xc342202c, 0xc3422030, 0xc3422034, 0xc3422038, + 0xc342203c, 0xc3422040, 0xc3422044, 0xc3422048, + 0xc342204c, 0xc3422050, 0xc3422054, 0xc3422058, + 0xc342205c, 0xc3422060, 0xc3422064, 0xc3422068, + 0xc342206c, 0xc3422070, 0xc3422074, 0xc3422078, + 0xc342207c, 0xc3422080, 0xc3422084, 0xc3422088, + 0xc342208c, 0xc3422090, 0xc3422094, 0xc3422098, + 0xc342209c, 0xc34220a0, 0xc34220a4, 0xc34220a8, + 0xc34220ac, 0xc34220b0 +}; + +static const u32 rgidw_register_list[] = { + 0xe8026000, 0xe8026004, 0xe8026008, 0xe802600c, + 0xe8026010, 0xe8026014, 0xe8026018, 0xe802601c, + 0xe8026020, 0xe8026024, 0xe8026028, 0xe802602c, + 0xe8026030, 0xe8026034, 0xe8026038, 0xe802603c, + 0xe8026040, 0xe8026044, 0xe8026048, 0xe802604c, + 0xe80a6000, 0xe80a6004, 0xe80a6008, 0xe80a600c, + 0xe80a6010, 0xe80a6014, 0xe80a6018, 0xe80a601c, + 0xe80a6020, 0xe80a6024, 0xe80a6028, 0xe80a602c, + 0xe80a6030, 0xe80a6034, 0xe80a6038, 0xe80a603c, + 0xe80a6040, 0xe80a6044, 0xe80a6048, 0xe80a604c, + 0xe8126000, 0xe8126004, 0xe8126008, 0xe812600c, + 0xe8126010, 0xe8126014, 0xe8126018, 0xe812601c, + 0xe8126020, 0xe8126024, 0xe8126028, 0xe812602c, + 0xe8126030, 0xe8126034, 0xe8126038, 0xe812603c, + 0xe8126040, 0xe8126044, 0xe8126048, 0xe812604c, + 0xe81a6000, 0xe81a6004, 0xe81a6008, 0xe81a600c, + 0xe81a6010, 0xe81a6014, 0xe81a6018, 0xe81a601c, + 0xe81a6020, 0xe81a6024, 0xe81a6028, 0xe81a602c, + 0xe81a6030, 0xe81a6034, 0xe81a6038, 0xe81a603c, + 0xe81a6040, 0xe81a6044, 0xe81a6048, 0xe81a604c, + 0xe8226000, 0xe8226004, 0xe8226008, 0xe822600c, + 0xe8226010, 0xe8226014, 0xe8226018, 0xe822601c, + 0xe8226020, 0xe8226024, 0xe8226028, 0xe822602c, + 0xe8226030, 0xe8226034, 0xe8226038, 0xe822603c, + 0xe8226040, 0xe8226044, 0xe8226048, 0xe822604c, + 0xe82a6000, 0xe82a6004, 0xe82a6008, 0xe82a600c, + 0xe82a6010, 0xe82a6014, 0xe82a6018, 0xe82a601c, + 0xe82a6020, 0xe82a6024, 0xe82a6028, 0xe82a602c, + 0xe82a6030, 0xe82a6034, 0xe82a6038, 0xe82a603c, + 0xe82a6040, 0xe82a6044, 0xe82a6048, 0xe82a604c, + 0xe8326000, 0xe8326004, 0xe8326008, 0xe832600c, + 0xe8326010, 0xe8326014, 0xe8326018, 0xe832601c, + 0xe8326020, 0xe8326024, 0xe8326028, 0xe832602c, + 0xe8326030, 0xe8326034, 0xe8326038, 0xe832603c, + 0xe8326040, 0xe8326044, 0xe8326048, 0xe832604c, + 0xe83a6000, 0xe83a6004, 0xe83a6008, 0xe83a600c, + 0xe83a6010, 0xe83a6014, 0xe83a6018, 0xe83a601c, + 0xe83a6020, 0xe83a6024, 0xe83a6028, 0xe83a602c, + 0xe83a6030, 0xe83a6034, 0xe83a6038, 0xe83a603c, + 0xe83a6040, 0xe83a6044, 0xe83a6048, 0xe83a604c, + 0xc0626000, 0xc0626004, 0xc0626008, 0xc062600c, + 0xc0626010, 0xc0626014, 0xc0626018, 0xc062601c, + 0xc0626020, 0xc0626024, 0xc0626028, 0xc062602c, + 0xc0626030, 0xc0626034, 0xc0626038, 0xc062603c, + 0xc0626040, 0xc0626044, 0xc0626048, 0xc062604c, + 0xc0626050, 0xc0626054, 0xc0766000, 0xc0766004, + 0xc0766008, 0xc076600c, 0xc0766010, 0xc0766014, + 0xc0766018, 0xc076601c, 0xc0766020, 0xc0766024, + 0xc0766028, 0xc076602c, 0xc0766030, 0xc0766034, + 0xc0766038, 0xc076603c, 0xc0766040, 0xc0766044, + 0xc0766048, 0xc076604c, 0xc0766050, 0xc0766054, + 0xc0766058, 0xc076605c, 0xc0766060, 0xc0766064, + 0xc0766068, 0xc076606c, 0xc0766070, 0xc0766074, + 0xc0766078, 0xc076607c, 0xc0766080, 0xc0766084, + 0xc0766088, 0xc076608c, 0xc0766090, 0xc0766094, + 0xc0766098, 0xc076609c, 0xc07660a0, 0xc07660a4, + 0xc07660a8, 0xc07660ac, 0xc07660b0, 0xc07660b4, + 0xc07660b8, 0xc07660bc, 0xc07660c0, 0xc07660c4, + 0xc07660c8, 0xc07660cc, 0xc07660d0, 0xc07660d4, + 0xc07660d8, 0xc07660dc, 0xc07a6000, 0xc07a6004, + 0xc07a6008, 0xc07a600c, 0xc07a6010, 0xc07a6014, + 0xc07a6018, 0xc07a601c, 0xc07a6020, 0xc07a6024, + 0xc07a6028, 0xc07a602c, 0xc07a6030, 0xc07a6034, + 0xc07a6038, 0xc07a603c, 0xc07a6040, 0xc07a6044, + 0xc07a6048, 0xc07a604c, 0xc07a6050, 0xc07a6054, + 0xc07a6058, 0x1d006000, 0x1d006004, 0x1d006008, + 0x1d00600c, 0x1d006010, 0x1d006014, 0x1d006018, + 0x1d00601c, 0x1d006020, 0x1d006024, 0x1d006028, + 0x1d00602c, 0x1d006030, 0x1d006034, 0x1d006038, + 0x1d00603c, 0x1d006040, 0x1d006044, 0x1d006048, + 0x1d00604c, 0x1d006050, 0x1d006054, 0x1d006058, + 0x1d00605c, 0x1d006060, 0x1d006064, 0x1d006068, + 0x1d00606c, 0x1d006070, 0x1d006074, 0x1d006078, + 0x1d00607c, 0x1d006080, 0x1d006084, 0x1d006088, + 0x1d00608c, 0x1d006090, 0x1d006094, 0x1d006098, + 0x1d00609c, 0x1d0060a0, 0x1d0060a4, 0x1d0060a8, + 0x1d0060ac, 0x1d0060b0, 0x1d0060b4, 0x1d0060b8, + 0xc6706000, 0xc6706004, 0xc6706008, 0xc670600c, + 0xc6706010, 0xc6706014, 0xc6706018, 0xc670601c, + 0xc6706020, 0xc6706024, 0xc6706028, 0xc670602c, + 0xc6706030, 0xc6706034, 0xc6706038, 0xc670603c, + 0xc6706040, 0xc6706044, 0xc6706048, 0xc670604c, + 0xc6706050, 0xc6706054, 0xc6706058, 0xc670605c, + 0xc6706060, 0xc6706064, 0xc6706068, 0xc670606c, + 0xc6706070, 0xc6706074, 0xc6706078, 0xc670607c, + 0xc6706080, 0xc6706084, 0xc6706088, 0xc670608c, + 0xc6706090, 0xc6706094, 0xc6706098, 0xc670609c, + 0xc67060a0, 0xc67060a4, 0xc67060a8, 0xc1746000, + 0xc1746004, 0xc1746008, 0xc174600c, 0xc1746010, + 0xc1746014, 0xc1746018, 0xc174601c, 0xc1746020, + 0xc1746024, 0xc1746028, 0xc174602c, 0xc1746030, + 0xc1746034, 0xc1746038, 0xc174603c, 0xc1746040, + 0xc1746044, 0xc1746048, 0xc174604c, 0xc1746050, + 0xc1746054, 0xec606000, 0xec606004, 0xec606008, + 0xec60600c, 0xec606010, 0xec606014, 0xec606018, + 0xec60601c, 0xec606020, 0xec606024, 0xec606028, + 0xec60602c, 0xec606030, 0xec606034, 0xec606038, + 0xec60603c, 0xec606040, 0xec606044, 0xec606048, + 0xec60604c, 0xec606050, 0xec606054, 0xec606058, + 0xec60605c, 0xec606060, 0xec606064, 0xec606068, + 0xec60606c, 0xec606070, 0xec606074, 0xec606078, + 0xec60607c, 0xec606080, 0xec606084, 0xec606088, + 0xec60608c, 0xec606090, 0xec606094, 0xec606098, + 0xec60609c, 0xec6060a0, 0xec6060a4, 0xec6060a8, + 0xec6060ac, 0xec6060b0, 0xec6060b4, 0xec6060b8, + 0xec6060bc, 0xec6060c0, 0xec6060c4, 0xec6060c8, + 0xec6060cc, 0xec6060d0, 0xec6060d4, 0xec6060d8, + 0xec6060dc, 0xec6060e0, 0xec6060e4, 0xec6060e8, + 0xec6060ec, 0xec6060f0, 0xec6060f4, 0xec6060f8, + 0xec6060fc, 0xec606100, 0xec606104, 0xec606108, + 0xec60610c, 0xec606110, 0xec606114, 0xec606118, + 0xec60611c, 0xec606120, 0xec606124, 0xec606128, + 0xec60612c, 0xec606130, 0xec606134, 0xec606138, + 0xec60613c, 0xec606140, 0xec606144, 0xec606148, + 0xec60614c, 0xec606150, 0xec606154, 0xec606158, + 0xec60615c, 0xec606160, 0xec606164, 0xec606168, + 0xec60616c, 0xec606170, 0xec606174, 0xec606178, + 0xec60617c, 0xec606180, 0xec606184, 0xec606188, + 0xec60618c, 0xec606190, 0xec606194, 0xec606198, + 0xec60619c, 0xec6061a0, 0xec6061a4, 0xec6061a8, + 0xec6061ac, 0xec6061b0, 0xec6061b4, 0xec6061b8, + 0xec6061bc, 0xec6061c0, 0xec6061c4, 0xec6061c8, + 0xec6061cc, 0xec6061d0, 0xec6061d4, 0xec6061d8, + 0xec6061dc, 0xec6061e0, 0xec6061e4, 0xec6061e8, + 0xec6061ec, 0xec6061f0, 0xec6061f4, 0xec6061f8, + 0xec6061fc, 0xec606200, 0xec606204, 0xec606208, + 0xec60620c, 0xec606210, 0xec606214, 0xec606218, + 0xec60621c, 0xec606220, 0xec606224, 0xec606228, + 0xec60622c, 0xec606230, 0xec606234, 0xec606238, + 0xec60623c, 0xec606240, 0xec606244, 0xec606248, + 0xec60624c, 0xec606250, 0xec606254, 0xec606258, + 0xec60625c, 0xec606260, 0xec606264, 0xec606268, + 0xec60626c, 0xec606270, 0xec606274, 0xec606278, + 0xec60627c, 0xec606280, 0xec606284, 0xec606288, + 0xec60628c, 0xec606290, 0xec606294, 0xec606298, + 0xec60629c, 0xec6062a0, 0xec6062a4, 0xec6062a8, + 0xec6062ac, 0xec6062b0, 0xec6062b4, 0xec6062b8, + 0xec6062bc, 0xec6062c0, 0xec6062c4, 0xec6062c8, + 0xec6062cc, 0xec6062d0, 0xec6062d4, 0xec6062d8, + 0xec6062dc, 0xec6062e0, 0xec6062e4, 0xec6062e8, + 0xec6062ec, 0xec6062f0, 0xec6062f4, 0xec6062f8, + 0xec6062fc, 0xec606300, 0xec606304, 0xec606308, + 0xec60630c, 0xec606310, 0xec606314, 0xec606318, + 0xec60631c, 0xec606320, 0xec606324, 0xec606328, + 0xec60632c, 0xec606330, 0xec606334, 0xec606338, + 0xec60633c, 0xec606340, 0xec606344, 0xec606348, + 0xec60634c, 0xec606350, 0xec606354, 0xec606358, + 0xec60635c, 0xec606360, 0xec606364, 0xec606368, + 0xec60636c, 0xec606370, 0xec606374, 0xec606378, + 0xec60637c, 0xec606380, 0xec606384, 0xec606388, + 0xec60638c, 0xec606390, 0xec606394, 0xec606398, + 0xec60639c, 0xec6063a0, 0xec6063a4, 0xec6063a8, + 0xec6063ac, 0xec6063b0, 0xec6063b4, 0xec6063b8, + 0xec6063bc, 0xec6063c0, 0xec6063c4, 0xec6063c8, + 0xec6063cc, 0xec6063d0, 0xec6063d4, 0xec6063d8, + 0xec6063dc, 0xec6063e0, 0xec6063e4, 0xec6063e8, + 0xec6063ec, 0xec6063f0, 0xec6063f4, 0xec6063f8, + 0xec6063fc, 0xec606400, 0xec606404, 0xec606408, + 0xec60640c, 0xec606410, 0xec606414, 0xec606418, + 0xec60641c, 0xec606420, 0xec606424, 0xec606428, + 0xec60642c, 0xec606430, 0xec606434, 0xec606438, + 0xec60643c, 0xec606440, 0xec606444, 0xec606448, + 0xec60644c, 0xec606450, 0xec606454, 0xec606458, + 0xec60645c, 0xec606460, 0xec606464, 0xec606468, + 0xec60646c, 0xec606470, 0xec606474, 0xec606478, + 0xec60647c, 0xec606480, 0xec606484, 0xec606488, + 0xec60648c, 0xec606490, 0xec606494, 0xec606498, + 0xec60649c, 0xec6064a0, 0xec6064a4, 0xec6064a8, + 0xec6064ac, 0xec6064b0, 0xec6064b4, 0xec6064b8, + 0xec6064bc, 0xec6064c0, 0xec6064c4, 0xec6064c8, + 0xec6064cc, 0xec6064d0, 0xec6064d4, 0xec6064d8, + 0xec6064dc, 0xec6064e0, 0xec6064e4, 0xec6064e8, + 0xec6064ec, 0xec6064f0, 0xec6064f4, 0xec6064f8, + 0xec6064fc, 0xec606500, 0xec606504, 0xec606508, + 0xec60650c, 0xec606510, 0xec606514, 0xec606518, + 0xec60651c, 0xec606520, 0xec606524, 0xec606528, + 0xec60652c, 0xec606530, 0xec606534, 0xec606538, + 0xec60653c, 0xec606540, 0xec606544, 0xec606548, + 0xec60654c, 0xec606550, 0xec606554, 0xec606558, + 0xec60655c, 0xec606560, 0xec606564, 0xec606568, + 0xec60656c, 0xec606570, 0xec606574, 0xec606578, + 0xec60657c, 0xec606580, 0xec606584, 0xec606588, + 0xec60658c, 0xec606590, 0xec606594, 0xec606598, + 0xec60659c, 0xec6065a0, 0xec6065a4, 0xec6065a8, + 0xec6065ac, 0xec6065b0, 0xec6065b4, 0xec6065b8, + 0xec6065bc, 0xec6065c0, 0xec6065c4, 0xec6065c8, + 0xec6065cc, 0xec6065d0, 0xec6065d4, 0xec6065d8, + 0xec6065dc, 0xec6065e0, 0xec6065e4, 0xec6065e8, + 0xec6065ec, 0xec6065f0, 0xec6065f4, 0xec6065f8, + 0xec6065fc, 0xec606600, 0xec606604, 0xec606608, + 0xec60660c, 0xec606610, 0xec606614, 0xec606618, + 0xec60661c, 0xec606620, 0xec606624, 0xec606628, + 0xec60662c, 0xec606630, 0xec606634, 0xec606638, + 0xec60663c, 0xec606640, 0xec606644, 0xec606648, + 0xec60664c, 0xec606650, 0xec606654, 0xec606658, + 0xec60665c, 0xec606660, 0xec606664, 0xec606668, + 0xec60666c, 0xec606670, 0xec606674, 0xec606678, + 0xec60667c, 0xec606680, 0xec606684, 0xec606688, + 0xec60668c, 0xec606690, 0xec606694, 0xec606698, + 0xec60669c, 0xec6066a0, 0xec6066a4, 0xec6066a8, + 0xec6066ac, 0xec6066b0, 0xec6066b4, 0xec6066b8, + 0xec6066bc, 0xec6066c0, 0xec6066c4, 0xec6066c8, + 0xec6066cc, 0xec6066d0, 0xec6066d4, 0xec6066d8, + 0xec6066dc, 0xec6066e0, 0xec6066e4, 0xec6066e8, + 0xec6066ec, 0xec6066f0, 0xec6066f4, 0xec6066f8, + 0xec6066fc, 0xec606700, 0xec606704, 0xec606708, + 0xec60670c, 0xec606710, 0xec606714, 0xec606718, + 0xec60671c, 0xec606720, 0xec606724, 0xec606728, + 0xec60672c, 0xec606730, 0xec606734, 0xec606738, + 0xec60673c, 0xec606740, 0xec606744, 0xec606748, + 0xec60674c, 0xec606750, 0xec606754, 0xec606758, + 0xec60675c, 0xec606760, 0xec606764, 0xec606768, + 0xec60676c, 0xec606770, 0xec606774, 0xec606778, + 0xec60677c, 0xec606780, 0xec606784, 0xec606788, + 0xec60678c, 0xec606790, 0xec606794, 0xec606798, + 0xec60679c, 0xec6067a0, 0xec6067a4, 0xec6067a8, + 0xec6067ac, 0xec6067b0, 0xec6067b4, 0xec6067b8, + 0xec6067bc, 0xec6067c0, 0xec6067c4, 0xec6067c8, + 0xec6067cc, 0xec6067d0, 0xec6067d4, 0xec6067d8, + 0xec6067dc, 0xec6067e0, 0xec6067e4, 0xec6067e8, + 0xec6067ec, 0xec6067f0, 0xec6067f4, 0xec6067f8, + 0xec6067fc, 0xec606800, 0xec606804, 0xec606808, + 0xec60680c, 0xec606810, 0xec606814, 0xec606818, + 0xec60681c, 0xec606820, 0xec606824, 0xec606828, + 0xec60682c, 0xec606830, 0xec606834, 0xec606838, + 0xec60683c, 0xec606840, 0xec606844, 0xec606848, + 0xec60684c, 0xec606850, 0xec606854, 0xec606858, + 0xec60685c, 0xec606860, 0xec606864, 0xec606868, + 0xec60686c, 0xec606870, 0xec606874, 0xec606878, + 0xec60687c, 0xec606880, 0xec606884, 0xec606888, + 0xec60688c, 0xec606890, 0xec606894, 0xec606898, + 0xec60689c, 0xec6068a0, 0xec6068a4, 0xec6068a8, + 0xec6068ac, 0xec6068b0, 0xec6068b4, 0xec6068b8, + 0xec6068bc, 0xec6068c0, 0xec6068c4, 0xec6068c8, + 0xec6068cc, 0xec6068d0, 0xec6068d4, 0xec6068d8, + 0xec6068dc, 0xec6068e0, 0xec6068e4, 0xec6068e8, + 0xec6068ec, 0xec6068f0, 0xec6068f4, 0xec6068f8, + 0xec6068fc, 0xec606900, 0xec606904, 0xec606908, + 0xec60690c, 0xec606910, 0xec606914, 0xec606918, + 0xec60691c, 0xec606920, 0xec606924, 0xec606928, + 0xec60692c, 0xec606930, 0xec606934, 0xec606938, + 0xec60693c, 0xec606940, 0xec606944, 0xec606948, + 0xec60694c, 0xec606950, 0xec606954, 0xec606958, + 0xec60695c, 0xec606960, 0xec606964, 0xec606968, + 0xec60696c, 0xec606970, 0xec606974, 0xec606978, + 0xec60697c, 0xec606980, 0xec606984, 0xec606988, + 0xec60698c, 0xec606990, 0xec606994, 0xec606998, + 0xec60699c, 0xec6069a0, 0xec6069a4, 0xec6069a8, + 0xec6069ac, 0xec6069b0, 0xec6069b4, 0xec6069b8, + 0xec6069bc, 0xec6069c0, 0xec6069c4, 0xec6069c8, + 0xec6069cc, 0xec6069d0, 0xec6069d4, 0xec6069d8, + 0xec6069dc, 0xec6069e0, 0xec6069e4, 0xec6069e8, + 0xec6069ec, 0xec6069f0, 0xec6069f4, 0xec6069f8, + 0xec6069fc, 0xec606a00, 0xec606a04, 0xec606a08, + 0xec606a0c, 0xec606a10, 0xec606a14, 0xe9e26000, + 0xe9e26004, 0xe9e26008, 0xe9e2600c, 0xe9e26010, + 0xe9e26014, 0xe9e26018, 0xe9e2601c, 0xe9e26020, + 0xe9e26024, 0xe9e26028, 0xe9e2602c, 0xe9e26030, + 0xe9e26034, 0xe9e26038, 0xe9e2603c, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0xca446000, 0xca446004, 0xca446008, + 0xca44600c, 0xca446010, 0xca446014, 0xca446018, + 0xca44601c, 0xca446020, 0xca446024, 0xca446028, + 0xca44602c, 0xca446030, 0xca446034, 0xca446038, + 0xca44603c, 0xca446040, 0xca446044, 0xca446048, + 0xca44604c, 0xca446050, 0xca446054, 0xca446058, + 0xca44605c, 0xca546000, 0xca546004, 0xca546008, + 0xca54600c, 0xca546010, 0xca546014, 0xca546018, + 0xca54601c, 0xca546020, 0xca546024, 0xca546028, + 0xca54602c, 0xca546030, 0xca546034, 0xca546038, + 0xca54603c, 0xca546040, 0xca546044, 0xca546048, + 0xca54604c, 0xca546050, 0xca546054, 0xca546058, + 0xca54605c, 0xca546060, 0xca546064, 0xcbf06000, + 0xcbf06004, 0xcbf06008, 0xcbf0600c, 0xcbf06010, + 0xcbf06014, 0xcbf06018, 0xcbf0601c, 0xcbf06020, + 0xcbf06024, 0xcbf06028, 0xcbf0602c, 0xcbf06030, + 0xcbf06034, 0xcbf06038, 0xcbf0603c, 0xcbf06040, + 0xcbf06044, 0xcbf06048, 0xcbf0604c, 0xcbf06050, + 0xcbf06054, 0xcbf06058, 0xcbf0605c, 0xcbf06060, + 0xcbf06064, 0xcbf06068, 0xcbf0606c, 0xcbf06070, + 0xcbf06074, 0xcbf06078, 0xcbf0607c, 0xcbf06080, + 0xcbf06084, 0xcbf06088, 0xcbf0608c, 0xcbf06090, + 0xcbf06094, 0xcbf06098, 0xcbf0609c, 0xcbf060a0, + 0xcbf060a4, 0xcbf060a8, 0xcbf060ac, 0xcbf060b0, + 0xcbf060b4, 0xcbf060b8, 0xcbf060bc, 0xcbf060c0, + 0xcbf060c4, 0xcbf060c8, 0xcbf060cc, 0xcbf060d0, + 0xcbf060d4, 0xcbf060d8, 0xcbf060dc, 0xcbf060e0, + 0xcbf060e4, 0xcbf060e8, 0xcbf060ec, 0xcbf060f0, + 0xcbf060f4, 0xcbf060f8, 0xcbf060fc, 0xcbf06100, + 0xcbf06104, 0xcbf06108, 0xcbf0610c, 0xcbf06110, + 0xcbf06114, 0xcbf06118, 0xcbf0611c, 0xcbf06120, + 0xc9d06000, 0xc9d06004, 0xc9d06008, 0xc9d0600c, + 0xc9d06010, 0xc9d06014, 0xc9d06018, 0xc9d0601c, + 0xc9d06020, 0xc9d06024, 0xc9d06028, 0xc9d0602c, + 0xc9d06030, 0xc9d06034, 0xc9d06038, 0xc9d0603c, + 0xc9d06040, 0xc9d06044, 0xc9d06048, 0xc9d0604c, + 0xc9d06050, 0xc9d06054, 0xc9d06058, 0xc9d0605c, + 0xc9d06060, 0xc9d06064, 0xc9d06068, 0xc9d0606c, + 0xc9d06070, 0xc9d06074, 0xc9d06078, 0xc9d0607c, + 0xc9d06080, 0xc9d06084, 0xc9d06088, 0xc9d0608c, + 0xc9d06090, 0xc9d06094, 0xc9d06098, 0xc9d0609c, + 0xc9d060a0, 0xc9d060a4, 0xc9d060a8, 0xc9d060ac, + 0xc9d060b0, 0xc9d060b4, 0xc9d060b8, 0xc9d060bc, + 0xc9d060c0, 0xc9d060c4, 0xc9d060c8, 0xc9d060cc, + 0xc9d060d0, 0xc9d060d4, 0xc9d060d8, 0xc9d060dc, + 0xc9d060e0, 0xc9d060e4, 0xc9d060e8, 0xc9d060ec, + 0xc9d060f0, 0xc9d060f4, 0xc9d060f8, 0xc9d060fc, + 0xc9d06100, 0xc9d06104, 0xc9d06108, 0xc9d0610c, + 0xc9d06110, 0xc9d06114, 0xc9d06118, 0xc9d0611c, + 0xc9d06120, 0xc9d06124, 0xc9d06128, 0xc9d0612c, + 0xc9d06130, 0xc9d06134, 0xc9d06138, 0xc9d0613c, + 0xc9d06140, 0xc9d06144, 0xc9d06148, 0xc9d0614c, + 0xc9d06150, 0xc9d06154, 0xc9d06158, 0xc9d0615c, + 0xc9d06160, 0xc9d06164, 0xc9d06168, 0xc9d0616c, + 0xc9d06170, 0xc9d06174, 0xc9d06178, 0xc9d0617c, + 0xc9d06180, 0xc9d06184, 0xc9d06188, 0xc9d0618c, + 0xc9d06190, 0xc9d06194, 0xc9d06198, 0xde806000, + 0xde806004, 0xde806008, 0xde80600c, 0xde806010, + 0xde806014, 0xde806018, 0xde80601c, 0xde806020, + 0xde806024, 0xde806028, 0xde80602c, 0xde806030, + 0xde806034, 0xde806038, 0xde80603c, 0xde806040, + 0xde806044, 0xde806048, 0xde80604c, 0xde806050, + 0xde806054, 0xde806058, 0xde80605c, 0xde806060, + 0xde806064, 0xde806068, 0xde80606c, 0xde806070, + 0xde806074, 0xde806078, 0xde80607c, 0xde806080, + 0xde806084, 0xde806088, 0xde80608c, 0xde806090, + 0xde806094, 0xde806098, 0xde80609c, 0xde8060a0, + 0xde8060a4, 0xde8060a8, 0xde8060ac, 0xde8060b0, + 0xde8060b4, 0xde8060b8, 0xde8060bc, 0xde8060c0, + 0xde8060c4, 0xde8060c8, 0xde8060cc, 0xde8060d0, + 0xde8060d4, 0xde8060d8, 0xde8060dc, 0xde8060e0, + 0xde8060e4, 0xde8060e8, 0xde8060ec, 0xde8060f0, + 0xde8060f4, 0xde8060f8, 0xde8060fc, 0xde806100, + 0xde806104, 0xde806108, 0xde80610c, 0xde806110, + 0xde806114, 0xde806118, 0xde80611c, 0xde806120, + 0xde806124, 0xde806128, 0xde80612c, 0xde806130, + 0xde806134, 0xde806138, 0xde80613c, 0xde806140, + 0xde806144, 0xde806148, 0xde80614c, 0xde806150, + 0xde806154, 0xde806158, 0xde80615c, 0xde806160, + 0xde806164, 0xde806168, 0xde80616c, 0xde806170, + 0xde806174, 0xde806178, 0xde80617c, 0xde806180, + 0xde806184, 0xde806188, 0xde80618c, 0xde806190, + 0xde806194, 0xde806198, 0xde80619c, 0xde8061a0, + 0xde8061a4, 0xde8061a8, 0xde8061ac, 0xde8061b0, + 0xde8061b4, 0xde8061b8, 0xde8061bc, 0xde8061c0, + 0xde8061c4, 0xde8061c8, 0xde8061cc, 0xde8061d0, + 0xde8061d4, 0xde8061d8, 0xde8061dc, 0xde8061e0, + 0xde8061e4, 0xde8061e8, 0xde8061ec, 0xde8061f0, + 0xde8061f4, 0xde8061f8, 0xde8061fc, 0xde806200, + 0xde806204, 0xde806208, 0xde80620c, 0xde806210, + 0xde806214, 0xde806218, 0xde80621c, 0xde806220, + 0xde806224, 0xde806228, 0xde80622c, 0xde806230, + 0xde806234, 0xde806238, 0xde80623c, 0xde806240, + 0xde806244, 0xde806248, 0xde80624c, 0xde806250, + 0xde806254, 0xde806258, 0xde80625c, 0xde806260, + 0xde806264, 0xde806268, 0xde80626c, 0xde806270, + 0xde806274, 0xde806278, 0xde80627c, 0xde806280, + 0xde806284, 0xde806288, 0xde80628c, 0xde806290, + 0xde806294, 0xde806298, 0xde80629c, 0xde8062a0, + 0xde8062a4, 0xde8062a8, 0xde8062ac, 0xde8062b0, + 0xde8062b4, 0xde8062b8, 0xde8062bc, 0xde8062c0, + 0xde8062c4, 0xde8062c8, 0xde8062cc, 0xde8062d0, + 0xde8062d4, 0xde8062d8, 0xde8062dc, 0xde8062e0, + 0xde8062e4, 0xde8062e8, 0xde8062ec, 0xde8062f0, + 0xde8062f4, 0xde8062f8, 0xde8062fc, 0xde806300, + 0xde806304, 0xde806308, 0xde80630c, 0xde806310, + 0xde806314, 0xde806318, 0xde80631c, 0xde806320, + 0xde806324, 0xde806328, 0xde80632c, 0xde806330, + 0xde806334, 0xde806338, 0xde80633c, 0xde806340, + 0xde806344, 0xde806348, 0xde80634c, 0xde806350, + 0xde806354, 0xde806358, 0xde80635c, 0xde806360, + 0xde806364, 0xde806368, 0xde80636c, 0xde806370, + 0xde806374, 0xde806378, 0xde80637c, 0xde806380, + 0xde806384, 0xde806388, 0xde80638c, 0xde806390, + 0xde806394, 0xde806398, 0xde80639c, 0xde8063a0, + 0xde8063a4, 0xde8063a8, 0xde8063ac, 0xde8063b0, + 0xde8063b4, 0xde8063b8, 0xde8063bc, 0xde8063c0, + 0xde8063c4, 0xde8063c8, 0xde8063cc, 0xde8063d0, + 0xde8063d4, 0xde8063d8, 0xde8063dc, 0xde8063e0, + 0xde8063e4, 0xde8063e8, 0xde8063ec, 0xde8063f0, + 0xde8063f4, 0xde8063f8, 0xde8063fc, 0xde806400, + 0xde806404, 0xde806408, 0xde80640c, 0xde806410, + 0xde806414, 0xde806418, 0xde80641c, 0xde806420, + 0xde806424, 0xde806428, 0xde80642c, 0xde806430, + 0xde806434, 0xde806438, 0xde80643c, 0xde806440, + 0xde806444, 0xde806448, 0xde80644c, 0xde806450, + 0xde806454, 0xde806458, 0xde80645c, 0xde806460, + 0xde806464, 0xde806468, 0xde80646c, 0xde806470, + 0xde806474, 0xde806478, 0xde80647c, 0xde806480, + 0xde806484, 0xde806488, 0xde80648c, 0xde806490, + 0xde806494, 0xde806498, 0xde80649c, 0xde8064a0, + 0xde8064a4, 0xde8064a8, 0xde8064ac, 0xde8064b0, + 0xde8064b4, 0xde8064b8, 0xc1a06000, 0xc1a06004, + 0xc1a06008, 0xc1a0600c, 0xc1a06010, 0xc1a06014, + 0xc1a06018, 0xc1a0601c, 0xc1a06020, 0xc1a06024, + 0xc1a06028, 0xc1a0602c, 0xc1a06030, 0xc1a06034, + 0xc1a06038, 0xc1a0603c, 0xc1a06040, 0xc1a06044, + 0xc1a06048, 0xc1a0604c, 0xc1a06050, 0xc1a06054, + 0xc1a06058, 0xc1a0605c, 0xc1a06060, 0xc1a06064, + 0xc1a06068, 0xc1a0606c, 0xc1a06070, 0xc1a06074, + 0xc1a06078, 0xc1a0607c, 0xc1a06080, 0xc1a06084, + 0xc1a06088, 0xc1a0608c, 0xc1a06090, 0xc1a06094, + 0xc1a06098, 0xc1a0609c, 0xc1a060a0, 0xc1e06000, + 0xc1e06004, 0xc1e06008, 0xc1e0600c, 0xc1e06010, + 0xc1e06014, 0xc1e06018, 0xc1e0601c, 0xc1e06020, + 0xc1e06024, 0xc1e06028, 0xc1e0602c, 0xc1e06030, + 0xc1e06034, 0xc1e06038, 0xc1e0603c, 0xc1e06040, + 0xc1e06044, 0xc1e06048, 0xc1e0604c, 0xc1e06050, + 0xc1e06054, 0xc1e06058, 0xc1e0605c, 0xc1e06060, + 0xc1e06064, 0xc1e06068, 0xc1e0606c, 0xc1e06070, + 0xc1e06074, 0xc1e06078, 0xc1e0607c, 0xc1e06080, + 0xc1e06084, 0xc1e06088, 0xc1e0608c, 0xc1e06090, + 0xc1e06094, 0xc1e06098, 0xc1e0609c, 0xc1e060a0, + 0xe9a06000, 0xe9a06004, 0xe9a06008, 0xe9a0600c, + 0xe9a06010, 0xe9a06014, 0xe9a06018, 0xe9a0601c, + 0xe9a06020, 0xe9a06024, 0xe9a06028, 0xe9a0602c, + 0xe9a06030, 0xe9a06034, 0xe9a06038, 0xe9a0603c, + 0xe9a06040, 0xe9a06044, 0xe9a06048, 0xe9a0604c, + 0xe9a06050, 0xe9a06054, 0xe9a06058, 0xe9a0605c, + 0xe9a06060, 0xe9a06064, 0xe9a06068, 0xe9a0606c, + 0xe9a06070, 0xe9a06074, 0xe9a06078, 0xe9a0607c, + 0xe9a06080, 0xe9a06084, 0xe9a06088, 0xe9a0608c, + 0xe9a06090, 0xe9a06094, 0xe9a06098, 0xe9a0609c, + 0xe9a060a0, 0xe9a060a4, 0xe9a060a8, 0xe9a060ac, + 0xe9a060b0, 0xe9a060b4, 0xe9a060b8, 0xe9a060bc, + 0xe9a060c0, 0xe9a060c4, 0xe9a060c8, 0xe9a060cc, + 0xe9a060d0, 0xe9a060d4, 0xe9a060d8, 0xe9a060dc, + 0xe9a060e0, 0xe9a060e4, 0xe9a060e8, 0xe9a060ec, + 0xe9a060f0, 0xe9a060f4, 0xe9a060f8, 0xe9a060fc, + 0xe9a06100, 0xe9a06104, 0xe9a06108, 0xe9a0610c, + 0xe9a06110, 0xe9a06114, 0xe9a06118, 0xe9a0611c, + 0xe9a06120, 0xe9a06124, 0xe9a06128, 0xe9a0612c, + 0xe9a06130, 0xe9a06134, 0xe9a06138, 0xe9a0613c, + 0xe9a06140, 0xe9a06144, 0xe9a06148, 0xe9a0614c, + 0xe9a06150, 0xe9a06154, 0xe9a06158, 0xe9a0615c, + 0xe9a06160, 0xe9a06164, 0xe9a06168, 0xe9a0616c, + 0xe9a06170, 0xe9a06174, 0xe9a06178, 0xe9a0617c, + 0xe9a06180, 0xe9a06184, 0xe9a06188, 0xe9a0618c, + 0xe9a06190, 0xe9a06194, 0xe9a06198, 0xe9a0619c, + 0xe9a061a0, 0xe9a061a4, 0xe9a061a8, 0xe9a061ac, + 0xe9a061b0, 0xe9a061b4, 0xe9a061b8, 0xe9a061bc, + 0xe9a061c0, 0xe9a061c4, 0xe9a061c8, 0xe9a061cc, + 0xe9a061d0, 0xe9a061d4, 0xe9a061d8, 0xe9a061dc, + 0xe9a061e0, 0xe9a061e4, 0xe9a061e8, 0xe9a061ec, + 0xe9a061f0, 0xe9a061f4, 0xe9a061f8, 0xe9a061fc, + 0xe9a06200, 0xe9a06204, 0xe9a06208, 0xe9a0620c, + 0xe9a06210, 0xe9a06214, 0xe9a06218, 0xe9a0621c, + 0xe9a06220, 0xe9a06224, 0xe9a06228, 0xe9a0622c, + 0xe9a06230, 0xe9a06234, 0xe9a06238, 0xe9a0623c, + 0xe9a06240, 0xe9a06244, 0xe9a06248, 0xe9a0624c, + 0xe9a06250, 0xe9a06254, 0xe9a06258, 0xe9a0625c, + 0xe9a06260, 0xe9a06264, 0xe9a06268, 0xe9a0626c, + 0xe9a06270, 0xe9a06274, 0xe9a06278, 0xe9a0627c, + 0xe9a06280, 0xe9a06284, 0xd2f06000, 0xd2f06004, + 0xd2f06008, 0xd2f0600c, 0xd2f06010, 0xd2f06014, + 0xd2f06018, 0xd2f0601c, 0xd2f06020, 0xd2f06024, + 0xd2f06028, 0xd2f0602c, 0xd2f06030, 0xd2f06034, + 0xd2f06038, 0xd2f0603c, 0xd2f06040, 0xd2f06044, + 0xd2f06048, 0xd2f0604c, 0xd2f06050, 0xd2f06054, + 0xd2f06058, 0xd2f0605c, 0xd2f06060, 0xd2f06064, + 0xd2f06068, 0xd2f0606c, 0xd2f06070, 0xd2f06074, + 0xd2f06078, 0xd2f0607c, 0xd2f06080, 0xd2f06084, + 0xd2f06088, 0xd2f0608c, 0xd2f06090, 0xd2f06094, + 0xd2f06098, 0xd2f0609c, 0xd2f060a0, 0xd2f060a4, + 0xd2f060a8, 0xd2f060ac, 0xd2f060b0, 0xd2f060b4, + 0xd2f060b8, 0xd2f060bc, 0xd2f060c0, 0xd2f060c4, + 0xd2f060c8, 0xd2f060cc, 0xd2f060d0, 0xd2f060d4, + 0xd2f060d8, 0xd2f060dc, 0xd6f06000, 0xd6f06004, + 0xd6f06008, 0xd6f0600c, 0xd6f06010, 0xd6f06014, + 0xd6f06018, 0xd6f0601c, 0xd6f06020, 0xd6f06024, + 0xd6f06028, 0xd6f0602c, 0xd6f06030, 0xd6f06034, + 0xd6f06038, 0xd6f0603c, 0xd6f06040, 0xd6f06044, + 0xd6f06048, 0xd6f0604c, 0xd6f06050, 0xd6f06054, + 0xd6f06058, 0xd6f0605c, 0xd6f06060, 0xd6f06064, + 0xd6f06068, 0xd6f0606c, 0xd6f06070, 0xd6f06074, + 0xd6f06078, 0xd6f0607c, 0xd6f06080, 0xd6f06084, + 0xd6f06088, 0xd6f0608c, 0xd6f06090, 0xd6f06094, + 0xd6f06098, 0xd6f0609c, 0xd6f060a0, 0xd6f060a4, + 0xd6f060a8, 0xd6f060ac, 0xd6f060b0, 0xd6f060b4, + 0xd6f060b8, 0xd6f060bc, 0xd6f060c0, 0xd6f060c4, + 0xd6f060c8, 0xd6f060cc, 0xd6f060d0, 0xd6f060d4, + 0xd6f060d8, 0xd6f060dc, 0xc0986000, 0xc0986004, + 0xc0986008, 0xc098600c, 0xc0986010, 0xc0986014, + 0xc0986018, 0xc098601c, 0xc0986020, 0xc0986024, + 0xc0986028, 0xc098602c, 0xc0986030, 0xc0986034, + 0xc0986038, 0xc098603c, 0xc0986040, 0xc0986044, + 0xc0986048, 0xc098604c, 0xc0986050, 0xc0986054, + 0xc0986058, 0xc098605c, 0xc0986060, 0xc0986064, + 0xc0986068, 0xc098606c, 0xc0986070, 0xc0986074, + 0xc0986078, 0xc098607c, 0xc0986080, 0xc0986084, + 0xc0986088, 0xc098608c, 0xc0986090, 0xc0986094, + 0xc0986098, 0xc098609c, 0xc09860a0, 0xc09860a4, + 0xc09860a8, 0xc09860ac, 0xc09860b0, 0xc09860b4, + 0xc09860b8, 0xc09860bc, 0xc09860c0, 0xc09860c4, + 0xc09860c8, 0xc09860cc, 0xc09860d0, 0xc09860d4, + 0xc09860d8, 0xc09860dc, 0xc09860e0, 0xc09860e4, + 0xc09860e8, 0xc09860ec, 0xc09860f0, 0xc09860f4, + 0xc09860f8, 0xc09860fc, 0xc0986100, 0xc0986104, + 0xc0986108, 0xc098610c, 0xc0986110, 0xc0986114, + 0xc0986118, 0xc098611c, 0xc0986120, 0xc0986124, + 0xc0986128, 0xc098612c, 0xc0986130, 0xc0986134, + 0xc0986138, 0xc098613c, 0xc0986140, 0xc0986144, + 0xc0986148, 0xc098614c, 0xc0986150, 0xc0986154, + 0xc0986158, 0xc098615c, 0xc0986160, 0xc0986164, + 0xc0986168, 0xc098616c, 0xc0986170, 0xc0986174, + 0xc0986178, 0xc098617c, 0xc0986180, 0xc0986184, + 0xc0986188, 0xc098618c, 0xc0986190, 0xc0986194, + 0xc0986198, 0xc098619c, 0xc09861a0, 0xc09861a4, + 0xc09861a8, 0xc09861ac, 0xc09861b0, 0xc09861b4, + 0xc09861b8, 0xc09861bc, 0xc09861c0, 0xc09861c4, + 0xc09861c8, 0xc09861cc, 0xc09861d0, 0xc09861d4, + 0xc09861d8, 0xc09861dc, 0xc09861e0, 0xc09861e4, + 0xc09861e8, 0xc09861ec, 0xc09861f0, 0xc09861f4, + 0xc09861f8, 0xc09861fc, 0xc0586000, 0xc0586004, + 0xc0586008, 0xc058600c, 0xc0586010, 0xc0586014, + 0xc0586018, 0xc058601c, 0xc0586020, 0xc0586024, + 0xc0586028, 0xc058602c, 0xc0586030, 0xc0586034, + 0xc0586038, 0xc058603c, 0xc0586040, 0xc0586044, + 0xc0586048, 0xc058604c, 0xc0586050, 0xc0586054, + 0xc0586058, 0xc058605c, 0xc0586060, 0xc0586064, + 0xc0586068, 0xc058606c, 0xc0586070, 0xc0586074, + 0xc0586078, 0xc058607c, 0xc0586080, 0xc0586084, + 0xc0586088, 0xc058608c, 0xc0586090, 0xc0586094, + 0xc0586098, 0xc058609c, 0xc05860a0, 0xc05860a4, + 0xc05860a8, 0xc05860ac, 0xc05860b0, 0xc05860b4, + 0xc05860b8, 0xc05860bc, 0xc05860c0, 0xc05860c4, + 0xc05860c8, 0xc05860cc, 0xc05860d0, 0xc05860d4, + 0xc05860d8, 0xc05860dc, 0xc05860e0, 0xc05860e4, + 0xc05860e8, 0xc05860ec, 0xc05860f0, 0xc05860f4, + 0xc05860f8, 0xc05860fc, 0xc0586100, 0xc0586104, + 0xc0586108, 0xc058610c, 0xc0586110, 0xc0586114, + 0xc0586118, 0xc058611c, 0xc0586120, 0xc0586124, + 0xc0586128, 0xc058612c, 0xc0586130, 0xc0586134, + 0xc0586138, 0xc058613c, 0xc0586140, 0xc0586144, + 0xc0586148, 0xc058614c, 0xc0586150, 0xc0586154, + 0xc0586158, 0xc058615c, 0xc0586160, 0xc0586164, + 0xc0586168, 0xc058616c, 0xc0586170, 0xc0586174, + 0xc0586178, 0xc058617c, 0xc0586180, 0xc0586184, + 0xc0586188, 0xc058618c, 0xc0586190, 0xc0586194, + 0xc0586198, 0xc058619c, 0xc05861a0, 0xc05861a4, + 0xc05861a8, 0xc05861ac, 0xc05861b0, 0xc05861b4, + 0xc05861b8, 0xc05861bc, 0xc05861c0, 0xc05861c4, + 0xc05861c8, 0xc05861cc, 0xc05861d0, 0xc05861d4, + 0xc05861d8, 0xc05861dc, 0xc05861e0, 0xc05861e4, + 0xc05861e8, 0xc05861ec, 0xc05861f0, 0xc05861f4, + 0xc05861f8, 0xc05861fc, 0xc0586200, 0xc0586204, + 0xc0586208, 0xc058620c, 0xc0586210, 0xc0586214, + 0xc0586218, 0xc058621c, 0xc0586220, 0xc0586224, + 0xc0586228, 0xc058622c, 0xc0586230, 0xc0586234, + 0xc0586238, 0xc058623c, 0xc0586240, 0xc0586244, + 0xc0586248, 0xc058624c, 0xcb406000, 0xcb406004, + 0xcb406008, 0xcb40600c, 0xcb406010, 0xcb406014, + 0xcb406018, 0xcb40601c, 0xcb406020, 0xcb406024, + 0xcb406028, 0xcb40602c, 0xcb406030, 0xcb406034, + 0xcb406038, 0xcb40603c, 0xcb406040, 0xcb406044, + 0xcb406048, 0xcb40604c, 0xcb406050, 0xcb406054, + 0xcb406058, 0xcb40605c, 0xcb406060, 0xcb406064, + 0xcb406068, 0xcb40606c, 0xcb406070, 0xcb406074, + 0xcb406078, 0xcb40607c, 0xcb406080, 0xcb406084, + 0xcb406088, 0xcb40608c, 0xcb406090, 0xcb406094, + 0xcb406098, 0xcb40609c, 0xcb4060a0, 0xcb4060a4, + 0xcb4060a8, 0xcb4060ac, 0xcb4060b0, 0xcb4060b4, + 0xcb4060b8, 0xcb4060bc, 0xcb4060c0, 0xcb4060c4, + 0xcb4060c8, 0xcb4060cc, 0xcb4060d0, 0xcb4060d4, + 0xcb4060d8, 0x1a806000, 0x1a806004, 0x1a806008, + 0x1a80600c, 0x1a806010, 0x1a806014, 0x1a806018, + 0x1a80601c, 0x1a806020, 0x1a806024, 0x1a806028, + 0x1a80602c, 0x1a806030, 0x1a806034, 0x1a806038, + 0x1a80603c, 0x1a806040, 0x1a806044, 0x1a806048, + 0x1a80604c, 0x1a806050, 0x1a806054, 0x1a806058, + 0x1a80605c, 0x1a806060, 0x1a806064, 0x1a806068, + 0x1a80606c, 0x1a806070, 0x1a806074, 0x1a806078, + 0x1a80607c, 0x1a806080, 0x1a806084, 0x1a806088, + 0x1a80608c, 0x1a806090, 0x1a806094, 0x1a806098, + 0x1a80609c, 0x1a8060a0, 0x1a8060a4, 0x1a8060a8, + 0x1a8060ac, 0x1a8060b0, 0x1a8060b4, 0x1a8060b8, + 0x1a8060bc, 0x1a8060c0, 0x1a8060c4, 0x1a8060c8, + 0x1a8060cc, 0x1a8060d0, 0x1a8060d4, 0x1a8060d8, + 0x1a8060dc, 0x1a8060e0, 0x1a8060e4, 0x1a8060e8, + 0x1a8060ec, 0x1a8060f0, 0x1a8060f4, 0x1a8060f8, + 0x1a8060fc, 0x1a806100, 0x1a806104, 0x1a806108, + 0x1a80610c, 0x1a806110, 0x1a806114, 0x1a806118, + 0x1a80611c, 0x1a806120, 0x1a806124, 0x1a806128, + 0x1a80612c, 0x1a806130, 0x1a806134, 0x1a806138, + 0x1a80613c, 0x1a806140, 0x1a806144, 0x1a806148, + 0x1a80614c, 0x1a806150, 0x1a806154, 0x1a806158, + 0x1a80615c, 0x1a806160, 0x1a806164, 0x1a806168, + 0x1a80616c, 0x1a806170, 0x1a806174, 0x1a806178, + 0x1a80617c, 0x1a806180, 0x1a806184, 0x1a806188, + 0x1a80618c, 0x1a806190, 0x1a806194, 0x1a806198, + 0x1a80619c, 0x1a8061a0, 0x1a8061a4, 0x1a8061a8, + 0x1a8061ac, 0x1a8061b0, 0x1a8061b4, 0x1a8061b8, + 0x1a8061bc, 0x1a8061c0, 0x1a8061c4, 0x1a8061c8, + 0x1a8061cc, 0x1a8061d0, 0x1a8061d4, 0x1a8061d8, + 0x1a8061dc, 0x1a8061e0, 0x1a8061e4, 0x1a8061e8, + 0x1a8061ec, 0x1a8061f0, 0x1a8061f4, 0x1a8061f8, + 0x1a8061fc, 0x1a806200, 0x1a806204, 0x1a806208, + 0x1a80620c, 0x1a806210, 0x1a806214, 0x1a806218, + 0x1a80621c, 0x1a806220, 0x1a806224, 0x1a806228, + 0x1a80622c, 0x1a806230, 0x1a806234, 0x1a806238, + 0x1a80623c, 0x1a806240, 0x1a806244, 0x1a806248, + 0x1a80624c, 0x1a806250, 0x1a806254, 0x1a806258, + 0x1a80625c, 0x1a806260, 0x1a806264, 0x1a806268, + 0x1a80626c, 0x1a806270, 0x1a806274, 0x1a806278, + 0x1a80627c, 0x1a806280, 0x1a806284, 0x1a806288, + 0x1a80628c, 0x1a806290, 0x1a806294, 0x1a806298, + 0x1a80629c, 0x1a8062a0, 0x1a8062a4, 0x1a8062a8, + 0x1a8062ac, 0x1a8062b0, 0x1a8062b4, 0x1a8062b8, + 0x1a8062bc, 0x1a8062c0, 0x1a8062c4, 0x1a8062c8, + 0x1a8062cc, 0x1a8062d0, 0x1a8062d4, 0x1a8062d8, + 0x1a8062dc, 0x1a8062e0, 0x1a8062e4, 0x1a8062e8, + 0x1a8062ec, 0x1a8062f0, 0x1a8062f4, 0x1a8062f8, + 0x1a8062fc, 0x1a806300, 0x1a806304, 0x1a806308, + 0x1a80630c, 0x1a806310, 0x1a806314, 0x1a806318, + 0x1a80631c, 0x1a806320, 0x1a806324, 0x1a806328, + 0x1a80632c, 0x1a806330, 0x1a806334, 0x1a806338, + 0x1a80633c, 0x1a806340, 0x1a806344, 0x1a806348, + 0x1a80634c, 0x1a806350, 0x1a806354, 0x1a806358, + 0x1a80635c, 0x1a806360, 0x1a806364, 0x1a806368, + 0x1a80636c, 0x1a806370, 0x1a806374, 0x1a806378, + 0x1a80637c, 0x1a806380, 0x1a806384, 0x1a806388, + 0x1a80638c, 0x1a806390, 0x1a806394, 0x1a806398, + 0x1a80639c, 0x1a8063a0, 0x1a8063a4, 0x1a8063a8, + 0x1a8063ac, 0x1a8063b0, 0x1a8063b4, 0x1a8063b8, + 0x1a8063bc, 0x1a8063c0, 0x1a8063c4, 0x1a8063c8, + 0x1a8063cc, 0x1a8063d0, 0x1a8063d4, 0x1a8063d8, + 0x1a8063dc, 0x1a8063e0, 0x1a8063e4, 0x1a8063e8, + 0x1a8063ec, 0x1a8063f0, 0x1a8063f4, 0x1a8063f8, + 0x1a8063fc, 0x1a806400, 0x1a806404, 0x1a806408, + 0x1a80640c, 0x1a806410, 0x1a806414, 0x1a806418, + 0x1a80641c, 0x1a806420, 0x1a806424, 0x1a806428, + 0x1a80642c, 0x1a806430, 0x1a806434, 0x1a806438, + 0x1a80643c, 0x1a806440, 0x1a806444, 0x1a806448, + 0x1a80644c, 0x1a806450, 0x1a806454, 0x1a806458, + 0x1a80645c, 0x1a806460, 0x1a806464, 0x1a806468, + 0x1a80646c, 0x1a806470, 0x1a806474, 0x1a806478, + 0x1a80647c, 0x1a806480, 0x1a806484, 0x1a806488, + 0x1a80648c, 0x1a806490, 0x1a806494, 0x1a806498, + 0x1a80649c, 0x1a8064a0, 0x1a8064a4, 0x1a8064a8, + 0x1a8064ac, 0x1a8064b0, 0x1a8064b4, 0x1a8064b8, + 0x1a8064bc, 0x1a8064c0, 0x1a8064c4, 0x1a8064c8, + 0x1a8064cc, 0x1a8064d0, 0x1a8064d4, 0x1a8064d8, + 0x1a8064dc, 0x1a8064e0, 0x1a8064e4, 0x1a8064e8, + 0x1a8064ec, 0x1a8064f0, 0x1a8064f4, 0x1a8064f8, + 0x1a8064fc, 0x1a806500, 0x1a806504, 0x1a806508, + 0x1a80650c, 0x1a806510, 0x1a806514, 0x1a806518, + 0x1a80651c, 0x1a806520, 0x1a806524, 0x1a806528, + 0x1a80652c, 0x1a806530, 0x1a806534, 0x1a806538, + 0x1a80653c, 0x1a806540, 0x1a806544, 0x1a806548, + 0x1a80654c, 0x1a806550, 0x1a806554, 0x1a806558, + 0x1a80655c, 0x1a806560, 0x1a806564, 0x1a806568, + 0x1a80656c, 0x1a806570, 0x1a806574, 0x1a806578, + 0x1a80657c, 0x1a806580, 0x1a806584, 0x1a806588, + 0x1a80658c, 0x1a806590, 0x1a806594, 0x1a806598, + 0x1a80659c, 0x1a8065a0, 0x1a8065a4, 0x1a8065a8, + 0x1a8065ac, 0x1a8065b0, 0x1a8065b4, 0x1a8065b8, + 0x1a8065bc, 0x1a8065c0, 0x1a8065c4, 0x1a8065c8, + 0x1a8065cc, 0x1a8065d0, 0x1a8065d4, 0x1a8065d8, + 0x18b46000, 0x18b46004, 0x18b46008, 0x18b4600c, + 0x18b46010, 0x18b46014, 0x18b46018, 0x18b4601c, + 0x18b46020, 0x18b46024, 0x18b46028, 0x18b4602c, + 0x18b46030, 0x18b46034, 0x18b46038, 0x18b4603c, + 0x18b46040, 0x18b46044, 0x18b46048, 0x18b4604c, + 0x18b46050, 0x18b46054, 0x18b46058, 0x18b4605c, + 0x18b46060, 0x18b46064, 0x18b46068, 0x18b4606c, + 0x18b46070, 0x18b46074, 0x18b46078, 0x18b4607c, + 0x18b46080, 0x18b46084, 0x18b46088, 0x18b4608c, + 0x18b46090, 0x18b46094, 0x18b46098, 0x18b4609c, + 0x18b460a0, 0x18b460a4, 0x18b460a8, 0x18b460ac, + 0x18b460b0, 0x18b460b4, 0x18b460b8, 0x18b460bc, + 0x18b460c0, 0x18b460c4, 0x18b460c8, 0x18b460cc, + 0x18b460d0, 0x18b460d4, 0x18b460d8, 0x18b460dc, + 0x18b460e0, 0x18b460e4, 0x18b460e8, 0x18b460ec, + 0x18b460f0, 0x18b460f4, 0x18b460f8, 0x18b460fc, + 0x18b46100, 0x18b46104, 0x18b46108, 0x18b4610c, + 0x18b46110, 0x18b46114, 0x18b46118, 0x18b4611c, + 0x18b46120, 0x18b46124, 0x18b46128, 0x18b4612c, + 0x18b46130, 0x18b46134, 0x18b46138, 0x18b4613c, + 0x18b46140, 0x18b46144, 0x18b46148, 0x18b4614c, + 0x18b46150, 0x18b46154, 0x18b46158, 0x18b4615c, + 0x18b46160, 0x18b46164, 0x18b46168, 0x18b4616c, + 0x18b46170, 0x18b46174, 0x18b46178, 0x18b4617c, + 0x18b46180, 0x18b46184, 0x18b46188, 0x18b4618c, + 0x18b46190, 0x18b46194, 0x18b46198, 0x18b4619c, + 0x18b461a0, 0x18b461a4, 0x18b461a8, 0x18b461ac, + 0x18b461b0, 0x18b461b4, 0x18b461b8, 0x18b461bc, + 0x18b461c0, 0x18b461c4, 0x18b461c8, 0x18b461cc, + 0x18b461d0, 0x18b461d4, 0x18b461d8, 0x18b461dc, + 0x18b461e0, 0x18b461e4, 0x18b461e8, 0x18b461ec, + 0x18b461f0, 0x18b461f4, 0x18b461f8, 0x18b461fc, + 0x18b46200, 0x18b46204, 0x18b46208, 0x18b4620c, + 0x18b46210, 0x18b46214, 0x18b46218, 0x18b4621c, + 0x18b46220, 0x18b46224, 0x18b46228, 0x18b4622c, + 0x18b46230, 0xc1286000, 0xc1286004, 0xc1286008, + 0xc128600c, 0xc1286010, 0xc1286014, 0xc1286018, + 0xc128601c, 0xc1286020, 0xc1286024, 0xc1286028, + 0xc128602c, 0xc1286030, 0xc1286034, 0xc1286038, + 0xc128603c, 0xc1286040, 0xc1286044, 0xc1286048, + 0xc128604c, 0xc1286050, 0xc1286054, 0xc1286058, + 0xc128605c, 0xc1286060, 0xc1286064, 0xc1286068, + 0xc128606c, 0xc1286070, 0xc1286074, 0xc1286078, + 0xc128607c, 0xc1286080, 0xc1286084, 0xc1286088, + 0xc128608c, 0xc1286090, 0xc1286094, 0xc1286098, + 0xc128609c, 0xc12860a0, 0xc12860a4, 0xc12860a8, + 0xc12860ac, 0xc12860b0, 0xc12860b4, 0xc12860b8, + 0xc12860bc, 0xc12860c0, 0xc12860c4, 0xc12860c8, + 0xc12860cc, 0xc12860d0, 0xc12860d4, 0xc12860d8, + 0xc12860dc, 0xc12860e0, 0xc12860e4, 0xc12860e8, + 0xc12860ec, 0xc12860f0, 0xc12860f4, 0xc12860f8, + 0xc12860fc, 0xc1286100, 0xc1286104, 0xc1286108, + 0xc128610c, 0xc1286110, 0xc1286114, 0xc1286118, + 0xc128611c, 0xc1286120, 0xc1286124, 0xc1286128, + 0xc128612c, 0xc1286130, 0xc1286134, 0xc1286138, + 0xc128613c, 0xc1286140, 0xc1286144, 0xc1286148, + 0xc128614c, 0xc1286150, 0xc1286154, 0xc1286158, + 0xc128615c, 0xc1286160, 0xc1286164, 0xc1286168, + 0xc128616c, 0xc1286170, 0xc1286174, 0xc1286178, + 0xc128617c, 0xc1286180, 0xc1286184, 0xc1286188, + 0xc128618c, 0xc1286190, 0xc1286194, 0xc1286198, + 0xc128619c, 0xc12861a0, 0xc12861a4, 0xc12861a8, + 0xc12861ac, 0xc12861b0, 0xc12861b4, 0xc12861b8, + 0xc12861bc, 0xc12861c0, 0xc12861c4, 0xc12861c8, + 0xc12861cc, 0xc12861d0, 0xc12861d4, 0xc12861d8, + 0xc12861dc, 0xc12861e0, 0xc12861e4, 0xc12861e8, + 0xc12861ec, 0xc12861f0, 0xc12861f4, 0xc12861f8, + 0xc12861fc, 0xc1286200, 0xc1286204, 0xc1286208, + 0xc128620c, 0xc1286210, 0xc1286214, 0xc1286218, + 0xc128621c, 0xc1286220, 0xc1286224, 0xc1286228, + 0xc128622c, 0xc1286230, 0xc1286234, 0xc1286238, + 0xc128623c, 0xc1286240, 0xc1286244, 0xc1286248, + 0xc128624c, 0xc1286250, 0xc1286254, 0xc1286258, + 0xc128625c, 0xc1286260, 0xc1286264, 0xc1286268, + 0xc128626c, 0xc1286270, 0xc1286274, 0xc1286278, + 0xc128627c, 0xc1286280, 0xc1286284, 0xc1286288, + 0xc128628c, 0xc1286290, 0xc1286294, 0xc1286298, + 0xc128629c, 0xc12862a0, 0xc12862a4, 0xc12862a8, + 0xc12862ac, 0xc12862b0, 0xc12862b4, 0xc12862b8, + 0xc6806000, 0xc6806004, 0xc6806008, 0xc680600c, + 0xc6806010, 0xc6806014, 0xc6806018, 0xc680601c, + 0xc6806020, 0xc6806024, 0xc6806028, 0xc680602c, + 0xc6806030, 0xc6806034, 0xc6806038, 0xc680603c, + 0xc6806040, 0xc6806044, 0xc6806048, 0xc680604c, + 0xc6806050, 0xc6806054, 0xc6806058, 0xc680605c, + 0xc6806060, 0xc6806064, 0xc6806068, 0xc680606c, + 0xc6806070, 0xc6806074, 0xc6806078, 0xc680607c, + 0xc6806080, 0xc6806084, 0xc6806088, 0xc680608c, + 0xc6806090, 0xc6806094, 0xc6806098, 0xc680609c, + 0xc68060a0, 0xc68060a4, 0xc68060a8, 0xc68060ac, + 0xc68060b0, 0xc68060b4, 0xc68060b8, 0xc68060bc, + 0xc68060c0, 0xc68060c4, 0xc68060c8, 0xc68060cc, + 0xc5806000, 0xc5806004, 0xc5806008, 0xc580600c, + 0xc5806010, 0xc5806014, 0xc5806018, 0xc580601c, + 0xc5806020, 0xc5806024, 0xc5806028, 0xc580602c, + 0xc5806030, 0xc5806034, 0xc5806038, 0xc580603c, + 0xc5806040, 0xc5806044, 0xc5806048, 0xc580604c, + 0xc5806050, 0xc5806054, 0xc5806058, 0xc580605c, + 0xc5806060, 0xc5806064, 0xc5806068, 0xc580606c, + 0xc5806070, 0xc5806074, 0xc5806078, 0xc580607c, + 0xc5806080, 0xc5806084, 0xc5806088, 0xc580608c, + 0xc5806090, 0xc5806094, 0xc5806098, 0xc580609c, + 0xc58060a0, 0xc58060a4, 0xc58060a8, 0xc58060ac, + 0xc58060b0, 0xc58060b4, 0xc58060b8, 0xc58060bc, + 0xc58060c0, 0xc58060c4, 0xc58060c8, 0xc58060cc, + 0xc58060d0, 0xc58060d4, 0xc58060d8, 0xc58060dc, + 0xc58060e0, 0xc58060e4, 0xc58060e8, 0xc58060ec, + 0xc58060f0, 0xc58060f4, 0xc58060f8, 0xc58060fc, + 0xc5806100, 0xc5806104, 0xc5806108, 0xc580610c, + 0xc5806110, 0xc5806114, 0xc5806118, 0xc580611c, + 0xc5806120, 0xc5806124, 0xc5806128, 0xc580612c, + 0xc5806130, 0xc5806134, 0xc5806138, 0xc580613c, + 0xc5806140, 0xc5806144, 0xc5806148, 0xc580614c, + 0xc5806150, 0xc5806154, 0xc5806158, 0xc580615c, + 0xc5806160, 0xc5806164, 0xc5806168, 0xc580616c, + 0xc5806170, 0xc5806174, 0xc5806178, 0xc580617c, + 0xc5806180, 0xc5806184, 0xc5806188, 0xc580618c, + 0xc5806190, 0xc5806194, 0xc5806198, 0xc580619c, + 0xc58061a0, 0xc58061a4, 0xc58061a8, 0xc58061ac, + 0xc58061b0, 0xc58061b4, 0xc58061b8, 0xc58061bc, + 0xc58061c0, 0xc58061c4, 0xc58061c8, 0xc58061cc, + 0xc58061d0, 0xc58061d4, 0xc58061d8, 0xc58061dc, + 0xc58061e0, 0xc58061e4, 0xc58061e8, 0xc58061ec, + 0xc58061f0, 0xc58061f4, 0xc58061f8, 0xc58061fc, + 0xc5806200, 0xc5806204, 0xc5806208, 0xc580620c, + 0xc5806210, 0xc5806214, 0xc5806218, 0xc580621c, + 0xc5806220, 0xc5806224, 0xc5806228, 0xc580622c, + 0xc5806230, 0xc5806234, 0xc5806238, 0xc580623c, + 0xc5806240, 0xc5806244, 0xc5806248, 0xc580624c, + 0xc5806250, 0xc5806254, 0xc5806258, 0xc580625c, + 0xc5806260, 0xc5806264, 0xc5806268, 0xc580626c, + 0xc5806270, 0xc5806274, 0xc5806278, 0xc580627c, + 0xc5806280, 0xc5806284, 0xc5806288, 0xc580628c, + 0xc5806290, 0xc5806294, 0xc5806298, 0xc580629c, + 0xc58062a0, 0xc58062a4, 0xc58062a8, 0xc58062ac, + 0xc58062b0, 0xc58062b4, 0xc58062b8, 0xc58062bc, + 0xc58062c0, 0xc58062c4, 0xc58062c8, 0xc58062cc, + 0xc58062d0, 0xc58062d4, 0xc58062d8, 0xc58062dc, + 0xc58062e0, 0xc58062e4, 0xc58062e8, 0xc58062ec, + 0xc58062f0, 0xc58062f4, 0xc58062f8, 0xc58062fc, + 0xc5806300, 0xc5806304, 0xc5806308, 0xc580630c, + 0xc3026000, 0xc3026004, 0xc3026008, 0xc302600c, + 0xc3026010, 0xc3026014, 0xc3026018, 0xc302601c, + 0xc3026020, 0xc3026024, 0xc3026028, 0xc302602c, + 0xc3026030, 0xc3026034, 0xc3026038, 0xc302603c, + 0xc3026040, 0xc3026044, 0xc3026048, 0xc302604c, + 0xc3026050, 0xc3026054, 0xc3026058, 0xc302605c, + 0xc3026060, 0xc3026064, 0xc3026068, 0xc302606c, + 0xc3026070, 0xc3026074, 0xc3026078, 0xc302607c, + 0xc3026080, 0xc3026084, 0xc3026088, 0xc302608c, + 0xc3026090, 0xc3026094, 0xc3026098, 0xc302609c, + 0xc30260a0, 0xc30260a4, 0xc30260a8, 0xc30260ac, + 0xc30260b0, 0xc3426000, 0xc3426004, 0xc3426008, + 0xc342600c, 0xc3426010, 0xc3426014, 0xc3426018, + 0xc342601c, 0xc3426020, 0xc3426024, 0xc3426028, + 0xc342602c, 0xc3426030, 0xc3426034, 0xc3426038, + 0xc342603c, 0xc3426040, 0xc3426044, 0xc3426048, + 0xc342604c, 0xc3426050, 0xc3426054, 0xc3426058, + 0xc342605c, 0xc3426060, 0xc3426064, 0xc3426068, + 0xc342606c, 0xc3426070, 0xc3426074, 0xc3426078, + 0xc342607c, 0xc3426080, 0xc3426084, 0xc3426088, + 0xc342608c, 0xc3426090, 0xc3426094, 0xc3426098, + 0xc342609c, 0xc34260a0, 0xc34260a4, 0xc34260a8, + 0xc34260ac, 0xc34260b0 +}; + +static const u32 sec_modid_register_list[] = { + 0xe8023800, 0xe8023804, 0xe8023808, 0xe802380c, + 0xe8023810, 0xe8023814, 0xe80a3800, 0xe80a3804, + 0xe80a3808, 0xe80a380c, 0xe80a3810, 0xe80a3814, + 0xe8123800, 0xe8123804, 0xe8123808, 0xe812380c, + 0xe8123810, 0xe8123814, 0xe81a3800, 0xe81a3804, + 0xe81a3808, 0xe81a380c, 0xe81a3810, 0xe81a3814, + 0xe8223800, 0xe8223804, 0xe8223808, 0xe822380c, + 0xe8223810, 0xe8223814, 0xe82a3800, 0xe82a3804, + 0xe82a3808, 0xe82a380c, 0xe82a3810, 0xe82a3814, + 0xe8323800, 0xe8323804, 0xe8323808, 0xe832380c, + 0xe8323810, 0xe8323814, 0xe83a3800, 0xe83a3804, + 0xe83a3808, 0xe83a380c, 0xe83a3810, 0xe83a3814, + 0xc0623800, 0xc0623804, 0xc0623808, 0xc062380c, + 0xc0623810, 0xc0623814, 0xc0623818, 0xc062381c, + 0xc0623820, 0xc0623824, 0xc0623828, 0xc0763800, + 0xc0763804, 0xc0763808, 0xc076380c, 0xc0763810, + 0xc0763814, 0xc0763818, 0xc076381c, 0xc0763820, + 0xc0763824, 0xc0763828, 0xc076382c, 0xc0763830, + 0xc0763834, 0xc0763838, 0xc076383c, 0xc0763840, + 0xc0763844, 0xc0763848, 0xc076384c, 0xc0763850, + 0xc0763854, 0xc0763858, 0xc076385c, 0xc0763860, + 0xc0763864, 0xc0763868, 0xc076386c, 0xc0763870, + 0xc0763874, 0xc0763878, 0xc076387c, 0xc0763880, + 0xc0763884, 0xc0763888, 0xc076388c, 0xc0763890, + 0xc0763894, 0xc0763898, 0xc076389c, 0xc07638a0, + 0xc07638a4, 0xc07638a8, 0xc07638ac, 0xc07638b0, + 0xc07a3800, 0xc07a3804, 0xc07a3808, 0xc07a380c, + 0xc07a3810, 0xc07a3814, 0xc07a3818, 0xc07a381c, + 0xc07a3820, 0xc07a3824, 0xc07a3828, 0xc07a382c, + 0x1d003800, 0x1d003804, 0x1d003808, 0x1d00380c, + 0x1d003810, 0x1d003814, 0x1d003818, 0x1d00381c, + 0x1d003820, 0x1d003824, 0x1d003828, 0x1d00382c, + 0x1d003830, 0x1d003834, 0x1d003838, 0x1d00383c, + 0x1d003840, 0x1d003844, 0x1d003848, 0x1d00384c, + 0x1d003850, 0x1d003854, 0x1d003858, 0x1d00385c, + 0x1d003860, 0x1d003864, 0x1d003868, 0x1d00386c, + 0x1d003870, 0x1d003874, 0x1d003878, 0x1d00387c, + 0x1d003880, 0x1d003884, 0xc6703800, 0xc6703804, + 0xc6703808, 0xc670380c, 0xc6703810, 0xc6703814, + 0xc6703818, 0xc670381c, 0xc6703820, 0xc6703824, + 0xc6703828, 0xc670382c, 0xc6703830, 0xc6703834, + 0xc6703838, 0xc670383c, 0xc6703840, 0xc6703844, + 0xc6703848, 0xc1743800, 0xc1743804, 0xc1743808, + 0xc174380c, 0xc1743810, 0xc1743814, 0xc1743818, + 0xc174381c, 0xc1743820, 0xc1743824, 0xc1743828, + 0xec603800, 0xec603804, 0xec603808, 0xec60380c, + 0xec603810, 0xec603814, 0xec603818, 0xec60381c, + 0xec603820, 0xec603824, 0xec603828, 0xec60382c, + 0xec603830, 0xec603834, 0xec603838, 0xec60383c, + 0xec603840, 0xec603844, 0xec603848, 0xec60384c, + 0xec603850, 0xec603854, 0xec603858, 0xec60385c, + 0xec603860, 0xec603864, 0xec603868, 0xec60386c, + 0xec603870, 0xec603874, 0xec603878, 0xec60387c, + 0xec603880, 0xec603884, 0xec603888, 0xec60388c, + 0xec603890, 0xec603894, 0xec603898, 0xec60389c, + 0xec6038a0, 0xec6038a4, 0xec6038a8, 0xec6038ac, + 0xec6038b0, 0xe9e23800, 0xe9e23804, 0xe9e23808, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0xca443800, + 0xca443804, 0xca443808, 0xca44380c, 0xca443810, + 0xca443814, 0xca443818, 0xca44381c, 0xca443820, + 0xca443824, 0xca543800, 0xca543804, 0xca543808, + 0xca54380c, 0xca543810, 0xca543814, 0xca543818, + 0xca54381c, 0xca543820, 0xcbf03800, 0xcbf03804, + 0xcbf03808, 0xcbf0380c, 0xcbf03810, 0xcbf03814, + 0xcbf03818, 0xcbf0381c, 0xcbf03820, 0xcbf03824, + 0xcbf03828, 0xcbf0382c, 0xcbf03830, 0xcbf03834, + 0xcbf03838, 0xcbf0383c, 0xcbf03840, 0xcbf03844, + 0xcbf03848, 0xcbf0384c, 0xcbf03850, 0xcbf03854, + 0xcbf03858, 0xcbf0385c, 0xcbf03860, 0xcbf03864, + 0xcbf03868, 0xcbf0386c, 0xcbf03870, 0xcbf03874, + 0xcbf03878, 0xcbf0387c, 0xcbf03880, 0xcbf03884, + 0xcbf03888, 0xcbf0388c, 0xcbf03890, 0xcbf03894, + 0xcbf03898, 0xcbf0389c, 0xcbf038a0, 0xcbf038a4, + 0xcbf038a8, 0xcbf038ac, 0xc9d03800, 0xc9d03804, + 0xc9d03808, 0xc9d0380c, 0xc9d03810, 0xc9d03814, + 0xc9d03818, 0xc9d0381c, 0xc9d03820, 0xc9d03824, + 0xc9d03828, 0xc9d0382c, 0xc9d03830, 0xc9d03834, + 0xc9d03838, 0xc9d0383c, 0xc9d03840, 0xc9d03844, + 0xc9d03848, 0xc9d0384c, 0xc9d03850, 0xc9d03854, + 0xc9d03858, 0xc9d0385c, 0xc9d03860, 0xc9d03864, + 0xc9d03868, 0xc9d0386c, 0xc9d03870, 0xc9d03874, + 0xc9d03878, 0xc9d0387c, 0xc9d03880, 0xc9d03884, + 0xc9d03888, 0xc9d0388c, 0xc9d03890, 0xc9d03894, + 0xc9d03898, 0xc9d0389c, 0xc9d038a0, 0xc9d038a4, + 0xc9d038a8, 0xc9d038ac, 0xc9d038b0, 0xc9d038b4, + 0xc9d038b8, 0xc9d038bc, 0xc9d038c0, 0xc9d038c4, + 0xc9d038c8, 0xc9d038cc, 0xde803800, 0xde803804, + 0xde803808, 0xde80380c, 0xde803810, 0xde803814, + 0xde803818, 0xde80381c, 0xde803820, 0xde803824, + 0xde803828, 0xde80382c, 0xde803830, 0xde803834, + 0xde803838, 0xde80383c, 0xde803840, 0xde803844, + 0xde803848, 0xde80384c, 0xde803850, 0xde803854, + 0xde803858, 0xc1a03800, 0xc1a03804, 0xc1a03808, + 0xc1a0380c, 0xc1a03810, 0xc1a03814, 0xc1a03818, + 0xc1a0381c, 0xc1a03820, 0xc1a03824, 0xc1a03828, + 0xc1a0382c, 0xc1a03830, 0xc1e03800, 0xc1e03804, + 0xc1e03808, 0xc1e0380c, 0xc1e03810, 0xc1e03814, + 0xc1e03818, 0xc1e0381c, 0xc1e03820, 0xc1e03824, + 0xc1e03828, 0xc1e0382c, 0xc1e03830, 0xe9a03800, + 0xe9a03804, 0xe9a03808, 0xe9a0380c, 0xe9a03810, + 0xe9a03814, 0xe9a03818, 0xe9a0381c, 0xe9a03820, + 0xe9a03824, 0xe9a03828, 0xe9a0382c, 0xe9a03830, + 0xe9a03834, 0xe9a03838, 0xe9a0383c, 0xe9a03840, + 0xe9a03844, 0xe9a03848, 0xe9a0384c, 0xe9a03850, + 0xe9a03854, 0xe9a03858, 0xe9a0385c, 0xe9a03860, + 0xe9a03864, 0xe9a03868, 0xe9a0386c, 0xe9a03870, + 0xe9a03874, 0xe9a03878, 0xe9a0387c, 0xe9a03880, + 0xe9a03884, 0xe9a03888, 0xe9a0388c, 0xe9a03890, + 0xe9a03894, 0xe9a03898, 0xe9a0389c, 0xe9a038a0, + 0xe9a038a4, 0xe9a038a8, 0xe9a038ac, 0xe9a038b0, + 0xe9a038b4, 0xe9a038b8, 0xe9a038bc, 0xe9a038c0, + 0xe9a038c4, 0xe9a038c8, 0xe9a038cc, 0xe9a038d0, + 0xe9a038d4, 0xe9a038d8, 0xe9a038dc, 0xe9a038e0, + 0xe9a038e4, 0xe9a038e8, 0xe9a038ec, 0xe9a038f0, + 0xe9a038f4, 0xe9a038f8, 0xe9a038fc, 0xe9a03900, + 0xe9a03904, 0xe9a03908, 0xe9a0390c, 0xe9a03910, + 0xe9a03914, 0xe9a03918, 0xe9a0391c, 0xe9a03920, + 0xe9a03924, 0xe9a03928, 0xe9a0392c, 0xe9a03930, + 0xe9a03934, 0xe9a03938, 0xe9a0393c, 0xe9a03940, + 0xe9a03944, 0xe9a03948, 0xe9a0394c, 0xe9a03950, + 0xe9a03954, 0xe9a03958, 0xd2f03800, 0xd2f03804, + 0xd2f03808, 0xd2f0380c, 0xd2f03810, 0xd2f03814, + 0xd2f03818, 0xd2f0381c, 0xd2f03820, 0xd2f03824, + 0xd2f03828, 0xd2f0382c, 0xd2f03830, 0xd2f03834, + 0xd2f03838, 0xd2f0383c, 0xd2f03840, 0xd2f03844, + 0xd2f03848, 0xd2f0384c, 0xd2f03850, 0xd6f03800, + 0xd6f03804, 0xd6f03808, 0xd6f0380c, 0xd6f03810, + 0xd6f03814, 0xd6f03818, 0xd6f0381c, 0xd6f03820, + 0xd6f03824, 0xd6f03828, 0xd6f0382c, 0xd6f03830, + 0xd6f03834, 0xd6f03838, 0xd6f0383c, 0xd6f03840, + 0xd6f03844, 0xd6f03848, 0xd6f0384c, 0xd6f03850, + 0xc0983800, 0xc0983804, 0xc0983808, 0xc098380c, + 0xc0983810, 0xc0983814, 0xc0983818, 0xc098381c, + 0xc0983820, 0xc0983824, 0xc0983828, 0xc098382c, + 0xc0983830, 0xc0983834, 0xc0983838, 0xc098383c, + 0xc0983840, 0xc0583800, 0xc0583804, 0xc0583808, + 0xc058380c, 0xc0583810, 0xc0583814, 0xc0583818, + 0xc058381c, 0xc0583820, 0xc0583824, 0xc0583828, + 0xc058382c, 0xc0583830, 0xc0583834, 0xc0583838, + 0xc058383c, 0xc0583840, 0xc0583844, 0xc0583848, + 0xc058384c, 0xc0583850, 0xc0583854, 0xc0583858, + 0xc058385c, 0xc0583860, 0xc0583864, 0xc0583868, + 0xc058386c, 0xc0583870, 0xc0583874, 0xc0583878, + 0xc058387c, 0xc0583880, 0xc0583884, 0xc0583888, + 0xc058388c, 0xc0583890, 0xc0583894, 0xc0583898, + 0xc058389c, 0xc05838a0, 0xc05838a4, 0xc05838a8, + 0xc05838ac, 0xc05838b0, 0xc05838b4, 0xc05838b8, + 0xc05838bc, 0xc05838c0, 0xc05838c4, 0xc05838c8, + 0xc05838cc, 0xc05838d0, 0xc05838d4, 0xc05838d8, + 0xc05838dc, 0xc05838e0, 0xc05838e4, 0xc05838e8, + 0xc05838ec, 0xc05838f0, 0xc05838f4, 0xc05838f8, + 0xc05838fc, 0xc0583900, 0xc0583904, 0xc0583908, + 0xc058390c, 0xc0583910, 0xcb403800, 0xcb403804, + 0xcb403808, 0xcb40380c, 0xcb403810, 0xcb403814, + 0xcb403818, 0xcb40381c, 0xcb403820, 0xcb403824, + 0xcb403828, 0x1a803800, 0x1a803804, 0x1a803808, + 0x1a80380c, 0x1a803810, 0x1a803814, 0x1a803818, + 0x1a80381c, 0x1a803820, 0x1a803824, 0x1a803828, + 0x1a80382c, 0x1a803830, 0x1a803834, 0x1a803838, + 0x1a80383c, 0x1a803840, 0x1a803844, 0x1a803848, + 0x1a80384c, 0x1a803850, 0x1a803854, 0x1a803858, + 0x1a80385c, 0x1a803860, 0x1a803864, 0x1a803868, + 0x1a80386c, 0x1a803870, 0x1a803874, 0x1a803878, + 0x1a80387c, 0x1a803880, 0x1a803884, 0x1a803888, + 0x1a80388c, 0x1a803890, 0x1a803894, 0x1a803898, + 0x1a80389c, 0x1a8038a0, 0x1a8038a4, 0x1a8038a8, + 0x1a8038ac, 0x1a8038b0, 0x1a8038b4, 0x1a8038b8, + 0x1a8038bc, 0x1a8038c0, 0x1a8038c4, 0x1a8038c8, + 0x1a8038cc, 0x1a8038d0, 0x1a8038d4, 0x1a8038d8, + 0x1a8038dc, 0x1a8038e0, 0x1a8038e4, 0x1a8038e8, + 0x1a8038ec, 0x1a8038f0, 0x1a8038f4, 0x1a8038f8, + 0x1a8038fc, 0x1a803900, 0x1a803904, 0x1a803908, + 0x1a80390c, 0x1a803910, 0x1a803914, 0x1a803918, + 0x1a80391c, 0x1a803920, 0x1a803924, 0x1a803928, + 0x1a80392c, 0x1a803930, 0x1a803934, 0x1a803938, + 0x1a80393c, 0x1a803940, 0x1a803944, 0x1a803948, + 0x1a80394c, 0x1a803950, 0x1a803954, 0x1a803958, + 0x1a80395c, 0x1a803960, 0x1a803964, 0x1a803968, + 0x1a80396c, 0x1a803970, 0x1a803974, 0x1a803978, + 0x1a80397c, 0x1a803980, 0x1a803984, 0x1a803988, + 0x1a80398c, 0x1a803990, 0x1a803994, 0x18b43800, + 0x18b43804, 0x18b43808, 0x18b4380c, 0x18b43810, + 0x18b43814, 0x18b43818, 0x18b4381c, 0x18b43820, + 0x18b43824, 0x18b43828, 0x18b4382c, 0x18b43830, + 0x18b43834, 0x18b43838, 0x18b4383c, 0x18b43840, + 0x18b43844, 0x18b43848, 0x18b4384c, 0x18b43850, + 0x18b43854, 0x18b43858, 0x18b4385c, 0x18b43860, + 0x18b43864, 0x18b43868, 0x18b4386c, 0x18b43870, + 0x18b43874, 0x18b43878, 0x18b4387c, 0x18b43880, + 0x18b43884, 0x18b43888, 0x18b4388c, 0x18b43890, + 0x18b43894, 0x18b43898, 0x18b4389c, 0x18b438a0, + 0x18b438a4, 0x18b438a8, 0x18b438ac, 0x18b438b0, + 0x18b438b4, 0xc1283800, 0xc1283804, 0xc1283808, + 0xc128380c, 0xc1283810, 0xc1283814, 0xc1283818, + 0xc128381c, 0xc1283820, 0xc1283824, 0xc1283828, + 0xc128382c, 0xc1283830, 0xc1283834, 0xc1283838, + 0xc128383c, 0xc1283840, 0xc1283844, 0xc1283848, + 0xc128384c, 0xc1283850, 0xc1283854, 0xc1283858, + 0xc128385c, 0xc1283860, 0xc1283864, 0xc1283868, + 0xc128386c, 0xc1283870, 0xc1283874, 0xc1283878, + 0xc128387c, 0xc1283880, 0xc1283884, 0xc1283888, + 0xc128388c, 0xc1283890, 0xc1283894, 0xc1283898, + 0xc128389c, 0xc12838a0, 0xc12838a4, 0xc12838a8, + 0xc12838ac, 0xc12838b0, 0xc12838b4, 0xc12838b8, + 0xc12838bc, 0xc12838c0, 0xc12838c4, 0xc12838c8, + 0xc12838cc, 0xc12838d0, 0xc12838d4, 0xc12838d8, + 0xc12838dc, 0xc12838e0, 0xc12838e4, 0xc12838e8, + 0xc12838ec, 0xc12838f0, 0xc12838f4, 0xc12838f8, + 0xc6803800, 0xc6803804, 0xc6803808, 0xc680380c, + 0xc6803810, 0xc6803814, 0xc6803818, 0xc680381c, + 0xc6803820, 0xc6803824, 0xc6803828, 0xc680382c, + 0xc6803830, 0xc5803800, 0xc5803804, 0xc5803808, + 0xc580380c, 0xc5803810, 0xc5803814, 0xc5803818, + 0xc580381c, 0xc5803820, 0xc5803824, 0xc5803828, + 0xc580382c, 0xc5803830, 0xc5803834, 0xc5803838, + 0xc580383c, 0xc5803840, 0xc5803844, 0xc5803848, + 0xc580384c, 0xc5803850, 0xc5803854, 0xc5803858, + 0xc580385c, 0xc5803860, 0xc5803864, 0xc5803868, + 0xc580386c, 0xc5803870, 0xc5803874, 0xc5803878, + 0xc580387c, 0xc5803880, 0xc5803884, 0xc5803888, + 0xc580388c, 0xc5803890, 0xc5803894, 0xc5803898, + 0xc580389c, 0xc58038a0, 0xc58038a4, 0xc58038a8, + 0xc58038ac, 0xc58038b0, 0xc58038b4, 0xc58038b8, + 0xc58038bc, 0xc58038c0, 0xc58038c4, 0xc58038c8, + 0xc58038cc, 0xc58038d0, 0xc58038d4, 0xc58038d8, + 0xc58038dc, 0xc58038e0, 0xc58038e4, 0xc58038e8, + 0xc58038ec, 0xc58038f0, 0xc58038f4, 0xc58038f8, + 0xc58038fc, 0xc5803900, 0xc5803904, 0xc5803908, + 0xc580390c, 0xc5803910, 0xc5803914, 0xc5803918, + 0xc580391c, 0xc5803920, 0xc5803924, 0xc5803928, + 0xc580392c, 0xc5803930, 0xc5803934, 0xc5803938, + 0xc580393c, 0xc5803940, 0xc5803944, 0xc5803948, + 0xc580394c, 0xc5803950, 0xc5803954, 0xc5803958, + 0xc580395c, 0xc5803960, 0xc5803964, 0xc5803968, + 0xc580396c, 0xc5803970, 0xc5803974, 0xc5803978, + 0xc580397c, 0xc5803980, 0xc5803984, 0xc5803988, + 0xc580398c, 0xc5803990, 0xc5803994, 0xc5803998, + 0xc580399c, 0xc58039a0, 0xc58039a4, 0xc58039a8, + 0xc58039ac, 0xc58039b0, 0xc58039b4, 0xc58039b8, + 0xc58039bc, 0xc58039c0, 0xc58039c4, 0xc58039c8, + 0xc58039cc, 0xc58039d0, 0xc58039d4, 0xc58039d8, + 0xc58039dc, 0xc58039e0, 0xc58039e4, 0xc58039e8, + 0xc58039ec, 0xc58039f0, 0xc58039f4, 0xc58039f8, + 0xc58039fc, 0xc5803a00, 0xc5803a04, 0xc5803a08, + 0xc5803a0c, 0xc5803a10, 0xc5803a14, 0xc5803a18, + 0xc5803a1c, 0xc5803a20, 0xc5803a24, 0xc5803a28, + 0xc5803a2c, 0xc5803a30, 0xc5803a34, 0xc5803a38, + 0xc5803a3c, 0xc5803a40, 0xc5803a44, 0xc5803a48, + 0xc5803a4c, 0xc5803a50, 0xc5803a54, 0xc5803a58, + 0xc5803a5c, 0xc5803a60, 0xc5803a64, 0xc5803a68, + 0xc5803a6c, 0xc5803a70, 0xc5803a74, 0xc5803a78, + 0xc5803a7c, 0xc5803a80, 0xc5803a84, 0xc5803a88, + 0xc5803a8c, 0xc5803a90, 0xc5803a94, 0xc5803a98, + 0xc5803a9c, 0xc5803aa0, 0xc5803aa4, 0xc5803aa8, + 0xc5803aac, 0xc5803ab0, 0xc5803ab4, 0xc5803ab8, + 0xc5803abc, 0xc5803ac0, 0xc3023800, 0xc3023804, + 0xc3023808, 0xc302380c, 0xc3023810, 0xc3023814, + 0xc3023818, 0xc302381c, 0xc3023820, 0xc3023824, + 0xc3023828, 0xc302382c, 0xc3023830, 0xc3023834, + 0xc3023838, 0xc302383c, 0xc3023840, 0xc3423800, + 0xc3423804, 0xc3423808, 0xc342380c, 0xc3423810, + 0xc3423814, 0xc3423818, 0xc342381c, 0xc3423820, + 0xc3423824, 0xc3423828, 0xc342382c, 0xc3423830, + 0xc3423834, 0xc3423838, 0xc342383c, 0xc3423840, +}; + +#endif /* __GEN5_CM33_H__ */ diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 43bc583378e..5cbbbc322a3 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -208,4 +208,36 @@ void fwu_plat_get_bootidx(uint *boot_idx) *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; } + +int fwu_platform_hook(struct udevice *dev, struct fwu_data *data) +{ + uint boot_idx; + efi_guid_t boot_uuid, root_uuid; + const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR; + const efi_guid_t root_type_guid = + PARTITION_LINUX_FILE_SYSTEM_DATA_GUID; + char uuidbuf[UUID_STR_LEN + 1]; + int retb, retr; + + fwu_plat_get_bootidx(&boot_idx); + + retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx); + retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx); + + if (!retb && !retr) { + uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("boot_partuuid", uuidbuf); + + uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("root_partuuid", uuidbuf); + } else if (!retb && retr) { + log_warning("%s: found boot GUID but missing root GUID (%d)\n", + __func__, retr); + } else if (!retr && retb) { + log_warning("%s: found root GUID but missing boot GUID (%d)\n", + __func__, retb); + } + + return 0; +} #endif /* CONFIG_FWU_MULTI_BANK_UPDATE */ diff --git a/board/ti/am57xx/am57xx.env b/board/ti/am57xx/am57xx.env index a7cbbced099..4f712c5575a 100644 --- a/board/ti/am57xx/am57xx.env +++ b/board/ti/am57xx/am57xx.env @@ -2,6 +2,7 @@ #include #include +bootm_size=0x10000000 bootpart=0:2 bootdir=/boot get_name_kern= diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index 5941ed11a60..ac8c9a9a81a 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -285,7 +285,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) } if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/cmd/boot.c b/cmd/boot.c index d80f9d8c05d..29cdf4a9a81 100644 --- a/cmd/boot.c +++ b/cmd/boot.c @@ -60,8 +60,11 @@ U_BOOT_CMD( reset, 2, 0, do_reset, "Perform RESET of the CPU", "- cold boot without level specifier\n" +#if IS_ENABLED(CONFIG_SYSRESET_CMD_RESET_ARGS) +// All options handled by sysreset drivers via their sysreset_ops.request_arg callback #ifdef CONFIG_SYSRESET_QCOM_PSCI "reset -edl - Boot to Emergency DownLoad mode\n" +#endif #endif "reset -w - warm reset if implemented" ); diff --git a/cmd/part.c b/cmd/part.c index 5e520d707f3..3191d5861fd 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -144,6 +144,10 @@ static int do_part_info(int argc, char *const argv[], enum cmd_part_info param) err = part_get_info(desc, part, &info); if (err) return 1; + } else if (uuid_str_valid(argv[2])) { + part = part_get_info_by_uuid(desc, argv[2], &info); + if (part < 0) + return 1; } else { part = part_get_info_by_name(desc, argv[2], &info); if (part < 0) @@ -517,13 +521,13 @@ U_BOOT_CMD( " flags can be -bootable (list only bootable partitions)\n" "part start \n" " - set environment variable to the start of the partition (in blocks)\n" - " part can be either partition number or partition name\n" + " part can be either partition number, UUID or name\n" "part size \n" " - set environment variable to the size of the partition (in blocks)\n" - " part can be either partition number or partition name\n" + " part can be either partition number, UUID or name\n" "part number \n" - " - set environment variable to the partition number using the partition name\n" - " part must be specified as partition name\n" + " - set environment variable to the partition number using the partition UUID or name\n" + " part must be specified as partition UUID or name\n" "part name \n" " - set environment variable to the partition name using the partition number\n" " part must be specified as partition number\n" diff --git a/common/board_r.c b/common/board_r.c index ae686d18ae8..a397e20959d 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -687,7 +687,7 @@ static void initcall_run_r(void) INITCALL(initr_flash); #endif WATCHDOG_RESET(); -#if CONFIG_IS_ENABLED(PPC) || CONFIG_IS_ENABLED(M68K) || CONFIG_IS_ENABLED(X86) +#if IS_ENABLED(CONFIG_PPC) || CONFIG_IS_ENABLED(M68K) || CONFIG_IS_ENABLED(X86) /* initialize higher level parts of CPU like time base and timers */ INITCALL(cpu_init_r); #endif diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig deleted file mode 100644 index 65c5840a13c..00000000000 --- a/configs/P2041RDB_NAND_defconfig +++ /dev/null @@ -1,117 +0,0 @@ -CONFIG_PPC=y -CONFIG_TEXT_BASE=0xFFF40000 -CONFIG_SYS_MALLOC_LEN=0x100000 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" -CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_MPC85xx=y -CONFIG_SYS_INIT_RAM_LOCK=y -CONFIG_SYS_SRIO=y -CONFIG_SRIO1=y -CONFIG_SRIO2=y -CONFIG_SRIO_PCIE_BOOT_MASTER=y -CONFIG_TARGET_P2041RDB=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_ENABLE_36BIT_PHYS=y -CONFIG_SYS_BOOK3E_HV=y -CONFIG_SYS_CACHE_STASHING=y -CONFIG_USE_UBOOTPATH=y -CONFIG_PCIE1=y -CONFIG_PCIE2=y -CONFIG_PCIE3=y -CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_MP=y -CONFIG_DYNAMIC_SYS_CLK_FREQ=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg" -CONFIG_BOOTDELAY=10 -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" -CONFIG_SYS_PBSIZE=276 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_ID_EEPROM=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_CMD_DM=y -CONFIG_CMD_I2C=y -CONFIG_LOADS_ECHO=y -CONFIG_SYS_LOADS_BAUD_CHANGE=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="uImage" -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="FM1@DTSEC1" -CONFIG_USE_ROOTPATH=y -CONFIG_FSL_SATA_V2=y -CONFIG_SYS_SATA_MAX_DEVICE=2 -CONFIG_FSL_CAAM=y -CONFIG_SYS_BR0_PRELIM_BOOL=y -CONFIG_SYS_BR0_PRELIM=0xFFA00C21 -CONFIG_SYS_OR0_PRELIM=0xFFFC0796 -CONFIG_SYS_BR1_PRELIM_BOOL=y -CONFIG_SYS_BR1_PRELIM=0xE8001001 -CONFIG_SYS_OR1_PRELIM=0xF8000F85 -CONFIG_SYS_BR3_PRELIM_BOOL=y -CONFIG_SYS_BR3_PRELIM=0xFFDF0801 -CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7 -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_FLASH_QUIET_TEST=y -CONFIG_SYS_MAX_FLASH_SECT=1024 -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_FSL_ELBC=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_DM_MDIO=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_SYS_FMAN_FW_ADDR=0x100000 -CONFIG_MII=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_DM_SERIAL=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_EHCI_FSL=y -CONFIG_USB_MAX_CONTROLLER_COUNT=2 -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_POST=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 02feeaf9858..20951f2d64a 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -1,10 +1,11 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xFFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x600 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xCF400 -CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y @@ -28,7 +29,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -54,6 +55,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 599eda68f37..0b0a856a1e5 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -1,11 +1,12 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xFFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x600 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y @@ -30,7 +31,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -56,6 +57,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index f9e6a9e454c..c2c00d54bfa 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -1,10 +1,11 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x600 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y @@ -52,6 +53,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_USE_BOOTFILE=y diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig index ddef8bd1b9f..07569fa0a4e 100644 --- a/configs/an7581_evb_defconfig +++ b/configs/an7581_evb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_AIROHA=y CONFIG_TARGET_AN7581=y CONFIG_TEXT_BASE=0x81E00000 @@ -42,6 +43,7 @@ CONFIG_CMD_LOG=y CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +# CONFIG_ENV_IS_IN_MTD is not set CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index 1ce69f2882a..fdc015b9071 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_APPLE=y -CONFIG_DEFAULT_DEVICE_TREE="t8103-j274" +CONFIG_DEFAULT_DEVICE_TREE="apple/t8103-j274" CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_BOOTCOMMAND="bootflow scan -b" @@ -12,6 +12,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_LATE_INIT=y CONFIG_CMD_SMBIOS=y CONFIG_CMD_SELECT_FONT=y +CONFIG_OF_UPSTREAM_BUILD_VENDOR=y +CONFIG_OF_UPSTREAM_VENDOR="apple" CONFIG_NO_NET=y CONFIG_SYS_64BIT_LBA=y CONFIG_APPLE_SPI_KEYB=y diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/r8a78000_ironhide_cm33_defconfig new file mode 100644 index 00000000000..dda096634b5 --- /dev/null +++ b/configs/r8a78000_ironhide_cm33_defconfig @@ -0,0 +1,80 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_RCAR_64_RSIP=y +CONFIG_RCAR_GEN5=y +CONFIG_TARGET_IRONHIDE=y +CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide-cm33" +CONFIG_DEFAULT_FDT_FILE="r8a78000-ironhide-cm33.dtb" + +CONFIG_TEXT_BASE=0x18410000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x3fe10000 +CONFIG_SYS_CUSTOM_LDSCRIPT=y +CONFIG_SYS_LDSCRIPT="arch/arm/mach-renesas/u-boot-rsip.lds" +CONFIG_SKIP_RELOCATE_CODE=y +CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000 + +CONFIG_ARCH_CPU_INIT=y +CONFIG_BAUDRATE=1843200 +CONFIG_BOOTCOMMAND="" +CONFIG_BOUNCE_BUFFER=y +CONFIG_CMD_IMI=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_UFS=y +CONFIG_DM_DMA=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_RESET=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_NET_LWIP=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_LIVE=y +CONFIG_PHY_R8A78000_ETHERNET_PCS=y +CONFIG_PHY_R8A78000_MP_PHY=y +CONFIG_PHY_TI_DP83869=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_REMOTEPROC_RENESAS_RSIP=y +CONFIG_RENESAS_ETHER_SWITCH=y +CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y +CONFIG_SCSI=y +CONFIG_SERIAL_PROBE_ALL=y +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SIMPLE_BUS_CORRECT_RANGE=y +CONFIG_SKIP_RELOCATE=y +CONFIG_SYS_ARCH_TIMER=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_CLK_FREQ=16666666 +CONFIG_SYS_LOAD_ADDR=0xb8000000 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_SYS_TIMER_COUNTS_DOWN=y +CONFIG_UFS=y +CONFIG_UFS_RENESAS_GEN5=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=2000 +CONFIG_WDT=y +CONFIG_WDT_RENESAS_WWDT=y +# CONFIG_DM_THERMAL is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTFLOW is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_PROT_TCP is not set +# CONFIG_OF_UPSTREAM is not set +# CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_OF_BOARD_SETUP is not set +# CONFIG_SYS_ARCH_TIMER is not set + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_SCIF=y +CONFIG_DEBUG_UART_BASE=0xc0714000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_DEBUG_UART_BOARD_INIT=y diff --git a/configs/r8a78000_ironhide_defconfig b/configs/r8a78000_ironhide_defconfig index 180704e75af..f8a1403ae0d 100644 --- a/configs/r8a78000_ironhide_defconfig +++ b/configs/r8a78000_ironhide_defconfig @@ -5,12 +5,11 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN5=y CONFIG_TARGET_IRONHIDE=y -# CONFIG_OF_UPSTREAM is not set CONFIG_ARMV8_PSCI=y CONFIG_ARM_SMCCC=y CONFIG_BAUDRATE=1843200 CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}" -CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide" +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a78000-ironhide" CONFIG_CLK_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_SCMI=y diff --git a/doc/CONTRIBUTE.rst b/doc/CONTRIBUTE.rst index a47dfdca221..a6e1cd1fb68 100644 --- a/doc/CONTRIBUTE.rst +++ b/doc/CONTRIBUTE.rst @@ -22,7 +22,7 @@ Repository The official U-Boot repository is located at https://source.denx.de/u-boot/u-boot Further more detailed documentation can be found at the following link: -https://docs.u-boot.org/en/latest/index.html +https://docs.u-boot-project.org/en/latest/index.html Contributions ------------- diff --git a/doc/README.gpt b/doc/README.gpt index 386ac2e0fc8..a6e1fd7ce8d 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -286,6 +286,8 @@ Some strings can be also used at the place of known GUID : (E6D6D379-F507-44C2-A23C-238F2A3DF928) "u-boot-env" = PARTITION_U_BOOT_ENVIRONMENT (3DE21764-95BD-54BD-A5C3-4ABE786F38A8) + "xbootldr" = PARTITION_XBOOTLDR + (BC13C2FF-59E6-4262-A352-B275FD6F7172) "uuid_disk=...;name=u-boot,size=60MiB,uuid=...; name=kernel,size=60MiB,uuid=...,type=linux;" diff --git a/doc/board/apple/m1.rst b/doc/board/apple/m1.rst index 8fa7637629e..900c5e6d91e 100644 --- a/doc/board/apple/m1.rst +++ b/doc/board/apple/m1.rst @@ -8,21 +8,24 @@ developed by the Asahi Linux project. At this point the machines with the following SoCs work: - Apple M1 SoC (t8103) + - Apple M2 SoC (t8112) - Apple M1 Pro SoC (t6000) - Apple M1 Max SoC (t6001) - Apple M1 Ultra SoC (t6002) + - Apple M2 Pro SoC (t6020) + - Apple M2 Max SoC (t6021) + - Apple M2 Ultra SoC (t6022) On these SoCs the following hardware is supported: - S5L serial port - - SPI keyboard (on laptops) + - SPI keyboard (on M1 laptops) - Framebuffer - NVMe storage - USB 3.1 Type-C ports -Device trees are currently provided for the M1 Mac mini (2020, J274), -M1 MacBook Pro 13" (2020, J293), M1 MacBook Air (2020, J313) and M1 -iMac (2021, J456/J457). +Device trees are provided in dts/upstream/src/arm64/apple/ and available +for all M1 and M2 (t8103, t8112, t600x and t602x) devices. Building U-Boot --------------- @@ -77,7 +80,7 @@ supported SoCs. * - SoC - Base Address - * - M1 (t8103) + * - M1 (t8103) and M2 (t8112) - 0x235200000 - * - M1 Pro/Max/Ultra (t6000/t6001/t6002) + * - M1 Pro/Max/Ultra (t6000/t6001/t6002) and M2 Pro/Max/Ultra (t6020/t6021/t6022) - 0x39b200000 diff --git a/doc/build/documentation.rst b/doc/build/documentation.rst index b55a4666643..65f767440bd 100644 --- a/doc/build/documentation.rst +++ b/doc/build/documentation.rst @@ -40,7 +40,7 @@ The *htmldocs* target is used to build the HTML documentation. It uses the # Display the documentation in a graphical web browser x-www-browser doc/output/index.html -The HTML documentation is published at https://docs.u-boot.org. The build +The HTML documentation is published at https://docs.u-boot-project.org. The build process for that site is controlled by the file *.readthedocs.yml*. Infodoc documentation diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 9a3ebd7e5f8..b53eac45504 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -75,7 +75,7 @@ For the next scheduled release, release candidates were made on: * U-Boot |next_ver|-rc2 was released on Mon 11 May 2026. -.. * U-Boot |next_ver|-rc3 was released on Mon 25 May 2026. +* U-Boot |next_ver|-rc3 was released on Mon 25 May 2026. .. * U-Boot |next_ver|-rc4 was released on Mon 08 June 2026. diff --git a/doc/device-tree-bindings/bootcount-syscon.txt b/doc/device-tree-bindings/bootcount-syscon.txt index ea27b246c8a..8e6060a711e 100644 --- a/doc/device-tree-bindings/bootcount-syscon.txt +++ b/doc/device-tree-bindings/bootcount-syscon.txt @@ -1,6 +1,6 @@ Bootcount Configuration This is the implementation of the feature as described in -https://docs.u-boot.org/en/latest/api/bootcount.html +https://docs.u-boot-project.org/en/latest/api/bootcount.html Required Properties: - compatible: must be "u-boot,bootcount-syscon". diff --git a/doc/device-tree-bindings/pinctrl/apple,pinctrl.yaml b/doc/device-tree-bindings/pinctrl/apple,pinctrl.yaml deleted file mode 100644 index d50571affd1..00000000000 --- a/doc/device-tree-bindings/pinctrl/apple,pinctrl.yaml +++ /dev/null @@ -1,106 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Apple GPIO controller - -maintainers: - - Mark Kettenis - -description: | - The Apple GPIO controller is a simple combined pin and GPIO - controller present on Apple ARM SoC platforms, including various - iPhone and iPad devices and the "Apple Silicon" Macs. - -properties: - compatible: - items: - - const: apple,t8103-pinctrl - - const: apple,pinctrl - - reg: - maxItems: 1 - - clocks: - maxItems: 1 - - gpio-controller: true - - '#gpio-cells': - const: 2 - - gpio-ranges: - maxItems: 1 - - interrupts: - description: One interrupt for each of the (up to 7) interrupt - groups supported by the controller sorted by interrupt group - number in ascending order. - minItems: 1 - maxItems: 7 - - interrupt-controller: true - -patternProperties: - '-pins$': - type: object - $ref: pinmux-node.yaml# - - properties: - pinmux: - description: - Values are constructed from pin number and alternate function - configuration number using the APPLE_PINMUX() helper macro - defined in include/dt-bindings/pinctrl/apple.h. - - required: - - pinmux - - additionalProperties: false - -required: - - compatible - - reg - - gpio-controller - - '#gpio-cells' - - gpio-ranges - -additionalProperties: false - -examples: - - | - #include - #include - - soc { - #address-cells = <2>; - #size-cells = <2>; - - pinctrl: pinctrl@23c100000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3c100000 0x0 0x100000>; - clocks = <&gpio_clk>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 212>; - - interrupt-controller; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; - - pcie_pins: pcie-pins { - pinmux = , - , - ; - }; - }; - }; diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 index d6653ec4247..ed296730eeb 100644 --- a/doc/mkeficapsule.1 +++ b/doc/mkeficapsule.1 @@ -153,4 +153,4 @@ The directory in which all capsule files be placed Written by AKASHI Takahiro .SH HOMEPAGE -http://www.u-boot.org/ +http://www.u-boot-project.org/ diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst index b91f6541f7f..a0e7be08a9a 100644 --- a/doc/usage/cmd/part.rst +++ b/doc/usage/cmd/part.rst @@ -52,7 +52,7 @@ The 'part list' command prints or sets an environment variable to the list of pa an optional environment variable to store the list of partitions value into. The 'part start' command sets an environment variable to the start of the partition (in blocks), -part can be either partition number or partition name. +part can be either partition number, partition UUID or partition name. interface interface for accessing the block device (mmc, sata, scsi, usb, ....) @@ -64,7 +64,7 @@ part can be either partition number or partition name. a variable to store the current start of the partition value into. The 'part size' command sets an environment variable to the size of the partition (in blocks), -part can be either partition number or partition name. +part can be either partition number, partition UUID or partition name. interface interface for accessing the block device (mmc, sata, scsi, usb, ....) @@ -76,7 +76,7 @@ part can be either partition number or partition name. a variable to store the current size of the partition value into. The 'part number' command sets an environment variable to the partition number using the partition name, -part must be specified as partition name. +part must be specified as partition UUID or partition name. interface interface for accessing the block device (mmc, sata, scsi, usb, ....) diff --git a/doc/usage/cmd/reset.rst b/doc/usage/cmd/reset.rst index 366b17eea16..79bc8b9deca 100644 --- a/doc/usage/cmd/reset.rst +++ b/doc/usage/cmd/reset.rst @@ -11,7 +11,9 @@ Synopsis :: - reset [-w] + reset + reset -w + reset -edl Description ----------- @@ -20,10 +22,14 @@ Perform reset of the CPU. By default does COLD reset, which resets CPU, DDR and peripherals, on some boards also resets external PMIC. -w - Do warm WARM, reset CPU but keep peripheral/DDR/PMIC active. + Do WARM reset: reset CPU but keep peripheral/DDR/PMIC active. + +All other options require CONFIG_SYSRESET_CMD_RESET_ARGS=y. -edl - Boot to Emergency DownLoad mode on supported Qualcomm platforms. + Boot to Emergency DownLoad mode on supported Qualcomm platforms. Unsupported + platforms will print an error message but the command will successfully + return (having done nothing). Requires CONFIG_SYSRESET_QCOM_PSCI=y. Return value ------------ diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 99b6c7534fd..4c0c8d89bb4 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -6,7 +6,7 @@ menuconfig BOOTCOUNT_LIMIT bool "Enable support for checking boot count limit" help Enable checking for exceeding the boot count limit. - More information: https://docs.u-boot.org/en/latest/api/bootcount.html + More information: https://docs.u-boot-project.org/en/latest/api/bootcount.html if BOOTCOUNT_LIMIT diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 51c87cc3606..72f99e9fa1b 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -157,6 +157,12 @@ config CLK_R8A779H0 help Enable this to support the clocks on Renesas R8A779H0 SoC. +config CLK_R8A78000 + bool "Renesas R8A78000 clock driver" + depends on CLK_RENESAS + help + Enable this to support the clocks on Renesas R8A78000 SoC. + config CLK_R9A06G032 bool "Renesas R9A06G032 clock driver" depends on CLK_RENESAS diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 354035baf2d..fb8d4c1f2f6 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A78000) += r8a78000-cpg.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c new file mode 100644 index 00000000000..e9ca06476f6 --- /dev/null +++ b/drivers/clk/renesas/r8a78000-cpg.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas R-Car Gen5 CPG driver + * + * Copyright (C) 2026 Marek Vasut + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#if IS_ENABLED(CONFIG_CLK_SCMI) +struct gen5_clk_priv { + struct udevice *clk; + u32 basever; +}; + +static struct clk *gen5_clk_get_by_scmi_id(struct clk *clk) +{ + struct gen5_clk_priv *priv = dev_get_priv(clk->dev); + struct udevice *sdev; + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_CLK, sdev, uc) + if (sdev->seq_ == priv->clk->seq_ + clk->id + 1) + return dev_get_clk_ptr(sdev); + + return NULL; +} + +static ulong gen5_clk_round_rate(struct clk *clk, ulong rate) +{ + struct clk *scmi = gen5_clk_get_by_scmi_id(clk); + + if (!scmi) + return -ENODEV; + + return clk_round_rate(scmi, rate); +} + +static ulong gen5_clk_get_rate(struct clk *clk) +{ + struct clk *scmi = gen5_clk_get_by_scmi_id(clk); + + if (!scmi) + return -ENODEV; + + return clk_get_rate(scmi); +} + +static ulong gen5_clk_set_rate(struct clk *clk, ulong rate) +{ + struct clk *scmi = gen5_clk_get_by_scmi_id(clk); + + if (!scmi) + return -ENODEV; + + return clk_set_rate(scmi, rate); +} + +static int gen5_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *scmi = gen5_clk_get_by_scmi_id(clk); + + if (!scmi) + return -ENODEV; + + return clk_set_parent(scmi, parent); +} + +static int gen5_clk_enable(struct clk *clk) +{ + struct clk *scmi = gen5_clk_get_by_scmi_id(clk); + + if (!scmi) + return -ENODEV; + + return clk_enable(scmi); +} + +static int gen5_clk_disable(struct clk *clk) +{ + struct clk *scmi = gen5_clk_get_by_scmi_id(clk); + + if (!scmi) + return -ENODEV; + + return clk_disable(scmi); +} + +struct clk_map_in { + u16 dt_id; /* DT binding clock ID */ + u16 fw_id; /* SCMI firmware clock ID */ +}; + +#define GEN5_SCMI_SDK_4_28 0x010a0000 +#define GEN5_SCMI_SDK_4_29 0x010b0000 +#define GEN5_SCMI_SDK_4_30 0x010c0000 +#define GEN5_SCMI_SDK_4_31 0x010d0000 +#define GEN5_SCMI_SDK_4_32 0x010e0000 + +static const struct clk_map_in gen5_clk_map_dt_sdk_4_28[] = { + { SCP_CLOCK_ID_MDLC_UFS0, 202 }, + { SCP_CLOCK_ID_MDLC_UFS1, 203 }, + { SCP_CLOCK_ID_MDLC_SDHI0, 204 }, + { SCP_CLOCK_ID_MDLC_XPCS0, 316 }, + { SCP_CLOCK_ID_MDLC_XPCS1, 317 }, + { SCP_CLOCK_ID_MDLC_XPCS2, 318 }, + { SCP_CLOCK_ID_MDLC_XPCS3, 319 }, + { SCP_CLOCK_ID_MDLC_XPCS4, 320 }, + { SCP_CLOCK_ID_MDLC_XPCS5, 321 }, + { SCP_CLOCK_ID_MDLC_XPCS6, 322 }, + { SCP_CLOCK_ID_MDLC_XPCS7, 323 }, + { SCP_CLOCK_ID_MDLC_RSW3, 324 }, + { SCP_CLOCK_ID_MDLC_RSW3TSN, 325 }, + { SCP_CLOCK_ID_MDLC_RSW3AES, 326 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES0, 327 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES1, 328 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES2, 329 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES3, 330 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES4, 331 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES5, 332 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES6, 333 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES7, 334 }, + { SCP_CLOCK_ID_MDLC_RSW3MFWD, 335 }, + { SCP_CLOCK_ID_MDLC_MPPHY01, 344 }, + { SCP_CLOCK_ID_MDLC_MPPHY11, 345 }, + { SCP_CLOCK_ID_MDLC_MPPHY21, 346 }, + { SCP_CLOCK_ID_MDLC_MPPHY31, 347 }, + { SCP_CLOCK_ID_MDLC_MPPHY02, 348 }, + { SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN, 1691 }, +}; + +static const struct clk_map_in gen5_clk_map_dt_sdk_4_31[] = { + { SCP_CLOCK_ID_MDLC_UFS0, 198 }, + { SCP_CLOCK_ID_MDLC_UFS1, 199 }, + { SCP_CLOCK_ID_MDLC_SDHI0, 200 }, + { SCP_CLOCK_ID_MDLC_XPCS0, 312 }, + { SCP_CLOCK_ID_MDLC_XPCS1, 313 }, + { SCP_CLOCK_ID_MDLC_XPCS2, 314 }, + { SCP_CLOCK_ID_MDLC_XPCS3, 315 }, + { SCP_CLOCK_ID_MDLC_XPCS4, 316 }, + { SCP_CLOCK_ID_MDLC_XPCS5, 317 }, + { SCP_CLOCK_ID_MDLC_XPCS6, 318 }, + { SCP_CLOCK_ID_MDLC_XPCS7, 319 }, + { SCP_CLOCK_ID_MDLC_RSW3, 320 }, + { SCP_CLOCK_ID_MDLC_RSW3TSN, 321 }, + { SCP_CLOCK_ID_MDLC_RSW3AES, 322 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES0, 323 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES1, 324 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES2, 325 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES3, 326 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES4, 327 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES5, 328 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES6, 329 }, + { SCP_CLOCK_ID_MDLC_RSW3TSNTES7, 330 }, + { SCP_CLOCK_ID_MDLC_RSW3MFWD, 331 }, + { SCP_CLOCK_ID_MDLC_MPPHY01, 340 }, + { SCP_CLOCK_ID_MDLC_MPPHY11, 341 }, + { SCP_CLOCK_ID_MDLC_MPPHY21, 342 }, + { SCP_CLOCK_ID_MDLC_MPPHY31, 343 }, + { SCP_CLOCK_ID_MDLC_MPPHY02, 344 }, + { SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN, 1687 }, +}; + +static int gen5_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + struct gen5_clk_priv *priv = dev_get_priv(clk->dev); + const struct clk_map_in *map; + unsigned int map_size; + int i; + + if (args->args_count != 1) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (priv->basever == GEN5_SCMI_SDK_4_28) { + map = gen5_clk_map_dt_sdk_4_28; + map_size = ARRAY_SIZE(gen5_clk_map_dt_sdk_4_28); + } else if (priv->basever == GEN5_SCMI_SDK_4_31 || + priv->basever == GEN5_SCMI_SDK_4_32) { + map = gen5_clk_map_dt_sdk_4_31; + map_size = ARRAY_SIZE(gen5_clk_map_dt_sdk_4_31); + } else { + printf("Unsupported SCMI base protocol version %x\n", priv->basever); + return -EINVAL; + } + + clk->id = -1; + for (i = 0; i < map_size; i++) { + if (map[i].dt_id != args->args[0]) + continue; + clk->id = map[i].fw_id; + break; + } + + if (clk->id == -1) + return -EINVAL; + + return 0; +} + +static const struct clk_ops gen5_clk_ops = { + .round_rate = gen5_clk_round_rate, + .get_rate = gen5_clk_get_rate, + .set_rate = gen5_clk_set_rate, + .set_parent = gen5_clk_set_parent, + .enable = gen5_clk_enable, + .disable = gen5_clk_disable, + .of_xlate = gen5_clk_of_xlate, +}; + +static int gen5_clk_probe(struct udevice *dev) +{ + struct gen5_clk_priv *priv = dev_get_priv(dev); + struct udevice *agent; + int ret; + + ret = uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent); + if (ret) + return ret; + + if (!agent) + return -ENODEV; + + priv->basever = scmi_impl_version(agent); + + return uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), + &priv->clk); +} +#else +static int gen5_clk_enable(struct clk *clk) +{ + return 0; +} + +static int gen5_clk_disable(struct clk *clk) +{ + return 0; +} + +static int gen5_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + if (args->args_count != 1) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + clk->id = args->args[0]; + + return 0; +} + +static const struct clk_ops gen5_clk_ops = { + .enable = gen5_clk_enable, + .disable = gen5_clk_disable, + .of_xlate = gen5_clk_of_xlate, +}; +#endif + +static const struct udevice_id r8a78000_mdlc_ids[] = { + { .compatible = "renesas,r8a78000-cpg", }, + { } +}; + +U_BOOT_DRIVER(clk_gen5) = { + .name = "clk_gen5", + .id = UCLASS_CLK, + .of_match = r8a78000_mdlc_ids, + .priv_auto = CONFIG_IS_ENABLED(CLK_SCMI, (sizeof(struct gen5_clk_priv)), (0)), + .ops = &gen5_clk_ops, + .probe = CONFIG_IS_ENABLED(CLK_SCMI, (gen5_clk_probe), (NULL)), + .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL, +}; diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index 010bf99fbc6..832bfb55711 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -1341,7 +1341,7 @@ static const struct udevice_id sandbox_scmi_test_ids[] = { { } }; -struct scmi_agent_ops sandbox_scmi_test_ops = { +static const struct scmi_agent_ops sandbox_scmi_test_ops = { .of_get_channel = sandbox_scmi_of_get_channel, .process_msg = sandbox_scmi_test_process_msg, }; diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 630d1ecfea3..3cb56cc0dc9 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -17,7 +17,7 @@ static ulong versal_align_dma_buffer(ulong *buf, u32 len) if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) { new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN); - memcpy(new_buf, buf, len); + memmove(new_buf, buf, len); buf = new_buf; } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 55465dc1d46..37288a47eb7 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -624,26 +624,6 @@ config SH_I2C_CLOCK default 104000000 endif -config SYS_I2C_SOFT - bool "Legacy software I2C interface" - depends on !COMPILE_TEST - help - Enable the legacy software defined I2C interface - -config SYS_I2C_SOFT_SPEED - int "Software I2C bus speed" - depends on SYS_I2C_SOFT - default 100000 - help - Speed of the software I2C bus - -config SYS_I2C_SOFT_SLAVE - hex "Software I2C slave address" - depends on SYS_I2C_SOFT - default 0xfe - help - Slave address of the software I2C bus - config SYS_I2C_OCTEON bool "Octeon II/III/TX/TX2 I2C driver" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 5fe30d0df4f..2da649e97d3 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o -obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o obj-$(CONFIG_SYS_I2C_SUN8I_RSB) += sun8i_rsb.o diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index c21c412231c..ad4122c2abd 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -168,7 +168,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops dw_i2c_acpi_ops = { +static struct acpi_ops dw_i2c_acpi_ops = { .fill_ssdt = dw_i2c_acpi_fill_ssdt, }; diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 4102375e5b7..e69de29bb2d 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * Changes for multibus/multiadapter I2C support. - * - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This has been changed substantially by Gerald Van Baren, Custom IDEAS, - * vanbaren@cideas.com. It was heavily influenced by LiMon, written by - * Neil Russell. - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.rst for instructions. - */ - -#include -#if defined(CONFIG_AT91FAMILY) -#include -#include -#include -#ifdef CONFIG_ATMEL_LEGACY -#include -#endif -#endif -#include -#include - -#if defined(CONFIG_SOFT_I2C_GPIO_SCL) -# include - -# ifndef I2C_GPIO_SYNC -# define I2C_GPIO_SYNC -# endif - -# ifndef I2C_INIT -# define I2C_INIT \ - do { \ - gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \ - gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \ - } while (0) -# endif - -# ifndef I2C_ACTIVE -# define I2C_ACTIVE do { } while (0) -# endif - -# ifndef I2C_TRISTATE -# define I2C_TRISTATE do { } while (0) -# endif - -# ifndef I2C_READ -# define I2C_READ gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA) -# endif - -# ifndef I2C_SDA -# define I2C_SDA(bit) \ - do { \ - if (bit) \ - gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA); \ - else \ - gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0); \ - I2C_GPIO_SYNC; \ - } while (0) -# endif - -# ifndef I2C_SCL -# define I2C_SCL(bit) \ - do { \ - gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, bit); \ - I2C_GPIO_SYNC; \ - } while (0) -# endif - -# ifndef I2C_DELAY -# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -# endif - -#endif - -/* #define DEBUG_I2C */ - -#ifndef I2C_SOFT_DECLARATIONS -# define I2C_SOFT_DECLARATIONS -#endif - -/*----------------------------------------------------------------------- - * Definitions - */ -#define RETRIES 0 - -#define I2C_ACK 0 /* PD_SDA level to ack a byte */ -#define I2C_NOACK 1 /* PD_SDA level to noack a byte */ - -#ifdef DEBUG_I2C -#define PRINTD(fmt,args...) do { \ - printf (fmt ,##args); \ - } while (0) -#else -#define PRINTD(fmt,args...) -#endif - -/*----------------------------------------------------------------------- - * Local functions - */ -static void send_reset (void); -static void send_start (void); -static void send_stop (void); -static void send_ack (int); -static int write_byte (uchar byte); -static uchar read_byte (int); - -/*----------------------------------------------------------------------- - * Send a reset sequence consisting of 9 clocks with the data signal high - * to clock any confused device back into an idle state. Also send a - * at the end of the sequence for belts & suspenders. - */ -static void send_reset(void) -{ - I2C_SOFT_DECLARATIONS /* intentional without ';' */ - int j; - - I2C_SCL(1); - I2C_SDA(1); -#ifdef I2C_INIT - I2C_INIT; -#endif - I2C_TRISTATE; - for(j = 0; j < 9; j++) { - I2C_SCL(0); - I2C_DELAY; - I2C_DELAY; - I2C_SCL(1); - I2C_DELAY; - I2C_DELAY; - } - send_stop(); - I2C_TRISTATE; -} - -/*----------------------------------------------------------------------- - * START: High -> Low on SDA while SCL is High - */ -static void send_start(void) -{ - I2C_SOFT_DECLARATIONS /* intentional without ';' */ - - I2C_DELAY; - I2C_SDA(1); - I2C_ACTIVE; - I2C_DELAY; - I2C_SCL(1); - I2C_DELAY; - I2C_SDA(0); - I2C_DELAY; -} - -/*----------------------------------------------------------------------- - * STOP: Low -> High on SDA while SCL is High - */ -static void send_stop(void) -{ - I2C_SOFT_DECLARATIONS /* intentional without ';' */ - - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(0); - I2C_ACTIVE; - I2C_DELAY; - I2C_SCL(1); - I2C_DELAY; - I2C_SDA(1); - I2C_DELAY; - I2C_TRISTATE; -} - -/*----------------------------------------------------------------------- - * ack should be I2C_ACK or I2C_NOACK - */ -static void send_ack(int ack) -{ - I2C_SOFT_DECLARATIONS /* intentional without ';' */ - - I2C_SCL(0); - I2C_DELAY; - I2C_ACTIVE; - I2C_SDA(ack); - I2C_DELAY; - I2C_SCL(1); - I2C_DELAY; - I2C_DELAY; - I2C_SCL(0); - I2C_DELAY; -} - -/*----------------------------------------------------------------------- - * Send 8 bits and look for an acknowledgement. - */ -static int write_byte(uchar data) -{ - I2C_SOFT_DECLARATIONS /* intentional without ';' */ - int j; - int nack; - - I2C_ACTIVE; - for(j = 0; j < 8; j++) { - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(data & 0x80); - I2C_DELAY; - I2C_SCL(1); - I2C_DELAY; - I2C_DELAY; - - data <<= 1; - } - - /* - * Look for an (negative logic) and return it. - */ - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(1); - I2C_TRISTATE; - I2C_DELAY; - I2C_SCL(1); - I2C_DELAY; - I2C_DELAY; - nack = I2C_READ; - I2C_SCL(0); - I2C_DELAY; - I2C_ACTIVE; - - return(nack); /* not a nack is an ack */ -} - -/*----------------------------------------------------------------------- - * if ack == I2C_ACK, ACK the byte so can continue reading, else - * send I2C_NOACK to end the read. - */ -static uchar read_byte(int ack) -{ - I2C_SOFT_DECLARATIONS /* intentional without ';' */ - int data; - int j; - - /* - * Read 8 bits, MSB first. - */ - I2C_TRISTATE; - I2C_SDA(1); - data = 0; - for(j = 0; j < 8; j++) { - I2C_SCL(0); - I2C_DELAY; - I2C_SCL(1); - I2C_DELAY; - data <<= 1; - data |= I2C_READ; - I2C_DELAY; - } - send_ack(ack); - - return(data); -} - -/*----------------------------------------------------------------------- - * Initialization - */ -static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - /* - * WARNING: Do NOT save speed in a static variable: if the - * I2C routines are called before RAM is initialized (to read - * the DIMM SPD, for instance), RAM won't be usable and your - * system will crash. - */ - send_reset (); -} - -/*----------------------------------------------------------------------- - * Probe to see if a chip is present. Also good for checking for the - * completion of EEPROM writes since the chip stops responding until - * the write completes (typically 10mSec). - */ -static int soft_i2c_probe(struct i2c_adapter *adap, uint8_t addr) -{ - int rc; - - /* - * perform 1 byte write transaction with just address byte - * (fake write) - */ - send_start(); - rc = write_byte ((addr << 1) | 0); - send_stop(); - - return (rc ? 1 : 0); -} - -/*----------------------------------------------------------------------- - * Read bytes - */ -static int soft_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - int shift; - PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n", - chip, addr, alen, buffer, len); - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of - * address and the extra bits end up in the "chip address" - * bit slots. This makes a 24WC08 (1Kbyte) chip look like - * four 256 byte chips. - * - * Note that we consider the length of the address field to - * still be one byte because the extra address bits are - * hidden in the chip address. - */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); - - PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n", - chip, addr); -#endif - - /* - * Do the addressing portion of a write cycle to set the - * chip's address pointer. If the address length is zero, - * don't do the normal write cycle to set the address pointer, - * there is no address pointer in this chip. - */ - send_start(); - if(alen > 0) { - if(write_byte(chip << 1)) { /* write cycle */ - send_stop(); - PRINTD("i2c_read, no chip responded %02X\n", chip); - return(1); - } - shift = (alen-1) * 8; - while(alen-- > 0) { - if(write_byte(addr >> shift)) { - PRINTD("i2c_read, address not ed\n"); - return(1); - } - shift -= 8; - } - - /* Some I2C chips need a stop/start sequence here, - * other chips don't work with a full stop and need - * only a start. Default behaviour is to send the - * stop/start sequence. - */ -#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START - send_start(); -#else - send_stop(); - send_start(); -#endif - } - /* - * Send the chip address again, this time for a read cycle. - * Then read the data. On the last byte, we do a NACK instead - * of an ACK(len == 0) to terminate the read. - */ - write_byte((chip << 1) | 1); /* read cycle */ - while(len-- > 0) { - *buffer++ = read_byte(len == 0); - } - send_stop(); - return(0); -} - -/*----------------------------------------------------------------------- - * Write bytes - */ -static int soft_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - int shift, failures = 0; - - PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n", - chip, addr, alen, buffer, len); - - send_start(); - if(write_byte(chip << 1)) { /* write cycle */ - send_stop(); - PRINTD("i2c_write, no chip responded %02X\n", chip); - return(1); - } - shift = (alen-1) * 8; - while(alen-- > 0) { - if(write_byte(addr >> shift)) { - PRINTD("i2c_write, address not ed\n"); - return(1); - } - shift -= 8; - } - - while(len-- > 0) { - if(write_byte(*buffer++)) { - failures++; - } - } - send_stop(); - return(failures); -} - -/* - * Register soft i2c adapters - */ -U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE, - 0) diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index bfd4ad20105..ebef28d0b9d 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 5bbc18dfa51..a76f9e8d6bd 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -39,6 +39,9 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; +static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, + unsigned int opcode); + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, u8 addr, u8 data) { @@ -155,8 +158,93 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) sdhci_cdns6_phy_adj(mmc->dev, plat, mmc->selected_mode); } +static __maybe_unused bool sdhci_cdns_sd_needs_tuning(struct mmc *mmc) +{ + struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev); + + if (!IS_SD(mmc)) + return false; + + if (!dev_read_bool(mmc->dev, "cdns,sd-hs-tuning")) + return false; + + /* Already tuned for this mode */ + if (plat->tuned_mode == mmc->selected_mode) + return false; + + switch (mmc->selected_mode) { + case SD_HS: + return mmc->bus_width == 4; + /* Add future modes here, e.g.: + * case UHS_SDR50: + * return true; + */ + default: + return false; + } +} + +static int sdhci_cdns_set_ios_post(struct sdhci_host *host) +{ + struct mmc *mmc = host->mmc; + struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev); + int ret __maybe_unused; + /* + * The SD6HC soft PHY requires runtime DLL delay calibration + * for SD High Speed mode. The default PHY_DLL_SLAVE_CTRL_REG + * values (READ_DQS_CMD_DELAY and READ_DQS_DELAY = 0) do not + * provide sufficient timing margin due to PVT and board trace + * variations. + * + * Tuning is performed once per entry into SD_HS mode + * (tracked by plat->tuned_mode state). The calibrated PHY delay + * values remain valid while the card stays in SD_HS mode, and + * leaving that tuned mode clears the state so re-entering SD_HS + * triggers tuning again. + * + * This must be done in set_ios_post (not set_control_reg) + * because the SDHCI controller must already be operating at + * the target bus width, clock, and speed mode before CMD19 + * tuning commands can succeed. + */ + + if (IS_ENABLED(CONFIG_MMC_SUPPORTS_TUNING)) { + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_420 && + sdhci_cdns_sd_needs_tuning(mmc)) { + ret = sdhci_cdns_execute_tuning(mmc->dev, + MMC_CMD_SEND_TUNING_BLOCK); + if (ret) { + dev_err(mmc->dev, + "SD_HS tuning failed (ret=%d), using default PHY\n", + ret); + /* Restore default PHY settings and avoid retrying in this mode */ + sdhci_cdns6_phy_adj(mmc->dev, plat, + mmc->selected_mode); + plat->tuned_mode = mmc->selected_mode; + plat->tuned_dll_slave_ctrl = sdhci_cdns6_phy_get_dll_slave(plat); + return 0; + } + /* + * Tuning succeeded. The tuned_mode is already set by + * execute_tuning(), so the tuned value will be preserved + * across subsequent PHY reconfigurations. + */ + dev_dbg(mmc->dev, "SD_HS tuning successful\n"); + } + + /* Reset when mode changes away from a tuned mode */ + if (mmc->selected_mode != plat->tuned_mode) { + plat->tuned_mode = MMC_MODES_END; + plat->tuned_dll_slave_ctrl = 0; + } + } + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_control_reg = sdhci_cdns_set_control_reg, + .set_ios_post = sdhci_cdns_set_ios_post, }; static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, @@ -204,6 +292,7 @@ static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, int cur_streak = 0; int max_streak = 0; int end_of_streak = 0; + int ret; int i; /* @@ -229,7 +318,24 @@ static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, return -EIO; } - return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2); + ret = sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2); + if (ret) + return ret; + + /* + * Mark this mode as tuned. This is critical for both driver tuning + * (SD_HS via set_ios_post) and framework tuning (UHS_SDR104, MMC_HS_200, + * MMC_HS_400) so that subsequent PHY reconfigurations restore the + * calibrated DLL value instead of overwriting with DT defaults. + * + * For HS400, tuning is performed while the controller is in HS200 mode + * (mmc->selected_mode == MMC_HS_200 and mmc->hs400_tuning == true). + * Record the tuned mode as MMC_HS_400 so the calibrated DLL value is + * preserved across the HS200→HS400 transition. + */ + plat->tuned_mode = mmc->hs400_tuning ? MMC_HS_400 : mmc->selected_mode; + + return 0; } static struct dm_mmc_ops sdhci_cdns_mmc_ops; diff --git a/drivers/mmc/sdhci-cadence.h b/drivers/mmc/sdhci-cadence.h index 7101f00b75b..ea517491860 100644 --- a/drivers/mmc/sdhci-cadence.h +++ b/drivers/mmc/sdhci-cadence.h @@ -7,6 +7,8 @@ #ifndef SDHCI_CADENCE_H_ #define SDHCI_CADENCE_H_ +#include + /* HRS - Host Register Set (specific to Cadence) */ /* PHY access port */ #define SDHCI_CDNS_HRS04 0x10 @@ -60,10 +62,13 @@ struct sdhci_cdns_plat { struct mmc_config cfg; struct mmc mmc; void __iomem *hrs_addr; + enum bus_mode tuned_mode; + u32 tuned_dll_slave_ctrl; }; int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode); int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat); int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val); +u32 sdhci_cdns6_phy_get_dll_slave(struct sdhci_cdns_plat *plat); #endif diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c index ca1086e2359..c8b42532e17 100644 --- a/drivers/mmc/sdhci-cadence6.c +++ b/drivers/mmc/sdhci-cadence6.c @@ -173,6 +173,30 @@ static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u3 writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05); } +static bool sdhci_cdns6_mode_is_tuned(struct sdhci_cdns_plat *plat, u32 mode) +{ + /* + * Check if the given mode has a valid tuned DLL value. + * Only modes that support tuning (driver or framework) can have + * valid tuned values. This prevents the initial state (tuned_mode=0) + * from falsely matching MMC_LEGACY. + */ + if (plat->tuned_mode != mode) + return false; + + switch (mode) { + case SD_HS: /* Driver tuning via set_ios_post */ + case UHS_SDR50: /* Future driver tuning support */ + case UHS_SDR104: /* Framework tuning */ + case MMC_HS_200: /* Framework tuning */ + case MMC_HS_400: /* Framework tuning */ + case MMC_HS_400_ES: /* Framework tuning */ + return true; + default: + return false; + } +} + static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset) { void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09; @@ -259,7 +283,18 @@ int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 m sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val); sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val); sdhci_cdns6_write_phy_reg(plat, PHY_DLL_MASTER_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[4].val); - sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val); + if (sdhci_cdns6_mode_is_tuned(plat, mode)) { + /* + * Use previously saved tuned DLL slave control value. + * Note: 0 is a valid tuned value (e.g., optimal tap at position 0), + * so we check both mode match AND that it's a tunable mode. + */ + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, + plat->tuned_dll_slave_ctrl); + } else { + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, + sdhci_cdns6_phy_cfgs[2].val); + } /* Switch Off the DLL Reset */ ret = sdhci_cdns6_reset_phy_dll(plat, false); @@ -318,6 +353,9 @@ int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val) sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp); + /* Store tuned DLL slave control value which will be reapplied via set_ios(). */ + plat->tuned_dll_slave_ctrl = tmp; + /* Switch Off the DLL Reset */ ret = sdhci_cdns6_reset_phy_dll(plat, false); if (ret) { @@ -327,3 +365,8 @@ int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val) return 0; } + +u32 sdhci_cdns6_phy_get_dll_slave(struct sdhci_cdns_plat *plat) +{ + return sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR); +} diff --git a/drivers/nvme/nvme-uclass.c b/drivers/nvme/nvme-uclass.c index 44c88ad27f3..4ab9567450f 100644 --- a/drivers/nvme/nvme-uclass.c +++ b/drivers/nvme/nvme-uclass.c @@ -44,7 +44,7 @@ UCLASS_DRIVER(nvme) = { .id = UCLASS_NVME, }; -struct bootdev_ops nvme_bootdev_ops = { +static const struct bootdev_ops nvme_bootdev_ops = { }; static const struct udevice_id nvme_bootdev_ids[] = { diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 2b14437f69c..0631b190b97 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -94,7 +94,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + page_size); i = 0; - prp_pool += page_size; + prp_pool = (u64 *)((uintptr_t)prp_pool + page_size); } *(prp_pool + i++) = cpu_to_le64(dma_addr); dma_addr += page_size; @@ -112,7 +112,10 @@ static __le16 nvme_get_cmd_id(void) { static unsigned short cmdid; - return cpu_to_le16((cmdid < USHRT_MAX) ? cmdid++ : 0); + if (cmdid >= USHRT_MAX) + cmdid = 0; + + return cpu_to_le16(cmdid++); } static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index) diff --git a/drivers/nvme/nvme_apple.c b/drivers/nvme/nvme_apple.c index 7e7538553e3..e674eda8344 100644 --- a/drivers/nvme/nvme_apple.c +++ b/drivers/nvme/nvme_apple.c @@ -13,6 +13,7 @@ #include #include #include +#include /* ASC registers */ #define REG_CPU_CTRL 0x0044 @@ -87,6 +88,9 @@ static int apple_nvme_setup_queue(struct nvme_queue *nvmeq) } priv->tcbs[nvmeq->qid] = (void *)memalign(4096, ANS_NVMMU_TCB_SIZE); + if (!priv->tcbs[nvmeq->qid]) + return -ENOMEM; + memset((void *)priv->tcbs[nvmeq->qid], 0, ANS_NVMMU_TCB_SIZE); switch (nvmeq->qid) { @@ -287,6 +291,7 @@ static const struct nvme_ops apple_nvme_ops = { }; static const struct udevice_id apple_nvme_ids[] = { + { .compatible = "apple,t8103-nvme-ans2" }, { .compatible = "apple,nvme-ans2" }, { /* sentinel */ } }; diff --git a/drivers/pinctrl/pinctrl-apple.c b/drivers/pinctrl/pinctrl-apple.c index f373afde58e..083ea6d6cd5 100644 --- a/drivers/pinctrl/pinctrl-apple.c +++ b/drivers/pinctrl/pinctrl-apple.c @@ -192,6 +192,7 @@ static struct pinctrl_ops apple_pinctrl_ops = { }; static const struct udevice_id apple_pinctrl_ids[] = { + { .compatible = "apple,t8103-pinctrl" }, { .compatible = "apple,pinctrl" }, { /* sentinel */ } }; diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 012d7762384..4112b777371 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -98,6 +98,14 @@ config QCOM_RPMH_POWER_DOMAIN The RPMH power domain driver is responsible for managing power domains on Qualcomm SoCs. +config RENESAS_R8A78000_POWER_DOMAIN + bool "Enable the Renesas R-Car MDLC Power domain and reset driver" + depends on POWER_DOMAIN && ARCH_RENESAS + help + Enable support for Renesas R-Car R8A78000 X5H MDLC Power domain + and reset driver. The MDLC is responsible for managing both + power domains and resets on R-Car R8A78000 X5H SoC. + config SANDBOX_POWER_DOMAIN bool "Enable the sandbox power domain test driver" depends on POWER_DOMAIN && SANDBOX diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index f373fc01395..110153d5cf8 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o +obj-$(CONFIG_RENESAS_R8A78000_POWER_DOMAIN) += renesas-r8a78000-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o obj-$(CONFIG_SCMI_POWER_DOMAIN) += scmi-power-domain.o diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index 37fac815242..9873d3cd8db 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -110,6 +110,7 @@ static int apple_pmgr_of_xlate(struct power_domain *power_domain, } static const struct udevice_id apple_pmgr_ids[] = { + { .compatible = "apple,t8103-pmgr-pwrstate" }, { .compatible = "apple,pmgr-pwrstate" }, { /* sentinel */ } }; diff --git a/drivers/power/domain/renesas-r8a78000-power-domain.c b/drivers/power/domain/renesas-r8a78000-power-domain.c new file mode 100644 index 00000000000..d621373f90d --- /dev/null +++ b/drivers/power/domain/renesas-r8a78000-power-domain.c @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R-Car Gen5 MDLC driver + * + * Copyright (C) 2026 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +#define PKC_PROT_LOCK 0xa5a5a500 +#define PKC_PROT_UNLOCK 0xa5a5a501 + +#define MDLC_MSRESS_STANDBY 0 +#define MDLC_MSRESS_RESET 1 +#define MDLC_MSRESS_STOP 2 +#define MDLC_MSRESS_RUN 3 + +#define MDLC_MSRES00 0x900 +#define MDLC_MSRESS00 0x960 +#define MDLC_PKCPROT1 0xcf4 + +struct gen5_mdlc_priv { +#if IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN) + struct udevice *pd; +#endif +#if IS_ENABLED(CONFIG_RESET_SCMI) + struct udevice *rst; +#endif +#if IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN) || IS_ENABLED(CONFIG_RESET_SCMI) + u32 basever; +#endif +#if !IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN) && !IS_ENABLED(CONFIG_RESET_SCMI) + void __iomem *base; +#endif +}; + +static int gen5_pd_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + /* Perform direct remap until the bindings stabilize. */ + power_domain->id = args->args[0]; + + return 0; +} + +#if IS_ENABLED(CONFIG_SCMI_POWER_DOMAIN) +static int gen5_pd_on(struct power_domain *power_domain) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(power_domain->dev->parent); + struct power_domain_ops *ops = (struct power_domain_ops *)priv->pd->driver->ops; + struct power_domain scmi = { + .dev = priv->pd, + .id = power_domain->id + }; + + return ops->on(&scmi); +} + +static int gen5_pd_off(struct power_domain *power_domain) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(power_domain->dev->parent); + struct power_domain_ops *ops = (struct power_domain_ops *)priv->pd->driver->ops; + struct power_domain scmi = { + .dev = priv->pd, + .id = power_domain->id + }; + + return ops->off(&scmi); +} + +static const struct power_domain_ops pd_gen5_ops = { + .on = gen5_pd_on, + .off = gen5_pd_off, + .of_xlate = gen5_pd_of_xlate, +}; + +static int gen5_pd_probe(struct udevice *dev) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(dev->parent); + struct udevice *agent; + int ret; + + if (!priv->basever) { + ret = uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent); + if (ret) + return ret; + + if (!agent) + return -ENODEV; + + priv->basever = scmi_impl_version(agent); + } + + return uclass_get_device_by_driver(UCLASS_POWER_DOMAIN, + DM_DRIVER_GET(scmi_power_domain), + &priv->pd); +} + +U_BOOT_DRIVER(pd_gen5) = { + .name = "pd_gen5", + .id = UCLASS_POWER_DOMAIN, + .ops = &pd_gen5_ops, + .probe = gen5_pd_probe, + .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL, +}; +#else +static const struct power_domain_ops pd_gen5_ops = { + .of_xlate = gen5_pd_of_xlate, +}; + +U_BOOT_DRIVER(pd_gen5) = { + .name = "pd_gen5", + .id = UCLASS_POWER_DOMAIN, + .ops = &pd_gen5_ops, + .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL, +}; +#endif + +#if IS_ENABLED(CONFIG_RESET_SCMI) +static int gen5_reset_assert(struct reset_ctl *reset_ctl) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent); + struct reset_ops *ops = (struct reset_ops *)priv->rst->driver->ops; + struct reset_ctl scmi = { + .dev = priv->rst, + .id = reset_ctl->id + }; + + return ops->rst_assert(&scmi); +} + +static int gen5_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent); + struct reset_ops *ops = (struct reset_ops *)priv->rst->driver->ops; + struct reset_ctl scmi = { + .dev = priv->rst, + .id = reset_ctl->id + }; + + return ops->rst_deassert(&scmi); +} + +struct rst_map_in { + u16 dt_id; /* DT binding clock ID */ + u16 fw_id; /* SCMI firmware clock ID */ +}; + +#define GEN5_SCMI_SDK_4_28 0x010a0000 +#define GEN5_SCMI_SDK_4_29 0x010b0000 +#define GEN5_SCMI_SDK_4_30 0x010c0000 +#define GEN5_SCMI_SDK_4_31 0x010d0000 +#define GEN5_SCMI_SDK_4_32 0x010e0000 + +static const struct rst_map_in gen5_rst_map_dt_sdk_4_28[] = { + { SCP_RESET_DOMAIN_ID_UFS0, 202 }, + { SCP_RESET_DOMAIN_ID_UFS1, 203 }, + { SCP_RESET_DOMAIN_ID_XPCS0, 316 }, + { SCP_RESET_DOMAIN_ID_XPCS1, 317 }, + { SCP_RESET_DOMAIN_ID_XPCS2, 318 }, + { SCP_RESET_DOMAIN_ID_XPCS3, 319 }, + { SCP_RESET_DOMAIN_ID_XPCS4, 320 }, + { SCP_RESET_DOMAIN_ID_XPCS5, 321 }, + { SCP_RESET_DOMAIN_ID_XPCS6, 322 }, + { SCP_RESET_DOMAIN_ID_XPCS7, 323 }, + { SCP_RESET_DOMAIN_ID_MPPHY01, 344 }, + { SCP_RESET_DOMAIN_ID_MPPHY11, 345 }, + { SCP_RESET_DOMAIN_ID_MPPHY21, 346 }, + { SCP_RESET_DOMAIN_ID_MPPHY31, 347 }, + { SCP_RESET_DOMAIN_ID_MPPHY02, 348 }, +}; + +static const struct rst_map_in gen5_rst_map_dt_sdk_4_31[] = { + { SCP_RESET_DOMAIN_ID_UFS0, 198 }, + { SCP_RESET_DOMAIN_ID_UFS1, 199 }, + { SCP_RESET_DOMAIN_ID_XPCS0, 312 }, + { SCP_RESET_DOMAIN_ID_XPCS1, 313 }, + { SCP_RESET_DOMAIN_ID_XPCS2, 314 }, + { SCP_RESET_DOMAIN_ID_XPCS3, 315 }, + { SCP_RESET_DOMAIN_ID_XPCS4, 316 }, + { SCP_RESET_DOMAIN_ID_XPCS5, 317 }, + { SCP_RESET_DOMAIN_ID_XPCS6, 318 }, + { SCP_RESET_DOMAIN_ID_XPCS7, 319 }, + { SCP_RESET_DOMAIN_ID_MPPHY01, 340 }, + { SCP_RESET_DOMAIN_ID_MPPHY11, 341 }, + { SCP_RESET_DOMAIN_ID_MPPHY21, 342 }, + { SCP_RESET_DOMAIN_ID_MPPHY31, 343 }, + { SCP_RESET_DOMAIN_ID_MPPHY02, 344 }, +}; + +static int gen5_reset_of_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent); + const struct rst_map_in *map; + unsigned int map_size; + int i; + + if (args->args_count != 1) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (priv->basever == GEN5_SCMI_SDK_4_28) { + map = gen5_rst_map_dt_sdk_4_28; + map_size = ARRAY_SIZE(gen5_rst_map_dt_sdk_4_28); + } else if (priv->basever == GEN5_SCMI_SDK_4_31 || + priv->basever == GEN5_SCMI_SDK_4_32) { + map = gen5_rst_map_dt_sdk_4_31; + map_size = ARRAY_SIZE(gen5_rst_map_dt_sdk_4_31); + } else { + printf("Unsupported SCMI base protocol version %x\n", priv->basever); + return -EINVAL; + } + + reset_ctl->id = -1; + for (i = 0; i < map_size; i++) { + if (map[i].dt_id != args->args[0]) + continue; + reset_ctl->id = map[i].fw_id; + break; + } + + return 0; +} + +static const struct reset_ops rst_gen5_ops = { + .rst_assert = gen5_reset_assert, + .rst_deassert = gen5_reset_deassert, + .of_xlate = gen5_reset_of_xlate, +}; + +static int gen5_rst_probe(struct udevice *dev) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(dev->parent); + struct udevice *agent; + int ret = 0; + + if (!priv->basever) { + ret = uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent); + if (ret) + return ret; + + if (!agent) + return -ENODEV; + + priv->basever = scmi_impl_version(agent); + } + + return uclass_get_device_by_driver(UCLASS_RESET, + DM_DRIVER_GET(scmi_reset_domain), + &priv->rst); +} +#else +static int mdlc_wait_for_reset(struct reset_ctl *reset_ctl) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent); + const u32 offset = (reset_ctl->id / 16) * 4; + void __iomem *res = priv->base + MDLC_MSRES00 + offset; + void __iomem *stat = priv->base + MDLC_MSRESS00 + offset; + u32 val; + int ret; + + /* Wait 100ms for reset controller to synchronize. */ + ret = readl_poll_timeout(res, val, val == readl(stat), 100000); + if (ret < 0) + dev_err(reset_ctl->dev, "Reset controller out of sync!\n"); + + return ret; +} + +static void mdlc_rmw_msres(struct reset_ctl *reset_ctl, const int val) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent); + const u32 offset = (reset_ctl->id / 16) * 4; + const u32 mask = 3 << ((reset_ctl->id % 16) * 2); + void __iomem *prot = priv->base + MDLC_PKCPROT1; + void __iomem *res = priv->base + MDLC_MSRES00 + offset; + u32 reg; + + reg = readl(res); + reg &= ~mask; + reg |= field_prep(mask, val); + + writel(PKC_PROT_UNLOCK, prot); + writel(reg, res); + writel(PKC_PROT_LOCK, prot); +} + +static int gen5_reset_toggle(struct reset_ctl *reset_ctl, const u8 step1, + const u8 step2, const u8 step3, const u8 step4) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(reset_ctl->dev->parent); + const u32 offset = (reset_ctl->id / 16) * 4; + const u32 mask = 3 << ((reset_ctl->id % 16) * 2); + void __iomem *stat = priv->base + MDLC_MSRESS00 + offset; + u32 status; + int ret; + + ret = mdlc_wait_for_reset(reset_ctl); + if (ret) + return ret; + + status = field_get(mask, readl(stat)); + if (status == step1) { + mdlc_rmw_msres(reset_ctl, step2); + ret = mdlc_wait_for_reset(reset_ctl); + if (ret) + return ret; + status = field_get(mask, readl(stat)); + } + + if (status == step2 || status == step3) { + mdlc_rmw_msres(reset_ctl, step4); + ret = mdlc_wait_for_reset(reset_ctl); + if (ret) + return ret; + } + + return 0; +} + +static int gen5_reset_assert(struct reset_ctl *reset_ctl) +{ + return gen5_reset_toggle(reset_ctl, + MDLC_MSRESS_STOP, MDLC_MSRESS_STANDBY, + MDLC_MSRESS_RUN, MDLC_MSRESS_RESET); +} + +static int gen5_reset_deassert(struct reset_ctl *reset_ctl) +{ + return gen5_reset_toggle(reset_ctl, + MDLC_MSRESS_STANDBY, MDLC_MSRESS_RESET, + MDLC_MSRESS_STOP, MDLC_MSRESS_RUN); +} + +static int gen5_reset_of_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + /* Perform direct remap until the bindings stabilize. */ + reset_ctl->id = args->args[0]; + + return 0; +} + +static const struct reset_ops rst_gen5_ops = { + .rst_assert = gen5_reset_assert, + .rst_deassert = gen5_reset_deassert, + .of_xlate = gen5_reset_of_xlate, +}; + +static int gen5_rst_probe(struct udevice *dev) +{ + struct gen5_mdlc_priv *priv = dev_get_priv(dev->parent); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + return 0; +} +#endif + +U_BOOT_DRIVER(rst_gen5) = { + .name = "rst_gen5", + .id = UCLASS_RESET, + .ops = &rst_gen5_ops, + .probe = gen5_rst_probe, + .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL, +}; + +int gen5_mdlc_bind(struct udevice *parent) +{ + struct udevice *pdev, *rdev; + struct driver *pdrv, *rdrv; + int ret; + + pdrv = lists_driver_lookup_name("pd_gen5"); + if (!pdrv) + return -ENOENT; + + rdrv = lists_driver_lookup_name("rst_gen5"); + if (!rdrv) + return -ENOENT; + + ret = device_bind_with_driver_data(parent, pdrv, "pd_gen5", 0, + dev_ofnode(parent), &pdev); + if (ret) + return ret; + + ret = device_bind_with_driver_data(parent, rdrv, "rst_gen5", (ulong)pdev, + dev_ofnode(parent), &rdev); + if (ret) + device_unbind(pdev); + + return ret; +} + +static const struct udevice_id r8a78000_mdlc_ids[] = { + { .compatible = "renesas,r8a78000-mdlc", }, + { } +}; + +U_BOOT_DRIVER(mdlc_gen5) = { + .name = "mdlc_gen5", + .id = UCLASS_NOP, + .of_match = r8a78000_mdlc_ids, + .bind = gen5_mdlc_bind, + .priv_auto = sizeof(struct gen5_mdlc_priv), +}; diff --git a/drivers/reset/stm32/stm32-reset-mp21.c b/drivers/reset/stm32/stm32-reset-mp21.c index 7d169d7582f..0e92b0f5d5d 100644 --- a/drivers/reset/stm32/stm32-reset-mp21.c +++ b/drivers/reset/stm32/stm32-reset-mp21.c @@ -5,7 +5,7 @@ */ #include -#include +#include "stm32-reset-core.h" #include #include diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c index acb74886708..acc87ea7bdc 100644 --- a/drivers/spi/apple_spi.c +++ b/drivers/spi/apple_spi.c @@ -270,6 +270,7 @@ static int apple_spi_probe(struct udevice *dev) } static const struct udevice_id apple_spi_of_match[] = { + { .compatible = "apple,t8103-spi" }, { .compatible = "apple,spi" }, { /* sentinel */ } }; diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 117e36376b7..c5bc603b5c0 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -216,13 +216,13 @@ int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, break; case SPI_XFER_BEGIN | SPI_XFER_END: len = data_len; - buffer = (unsigned char *)malloc(len * 2); + buffer = (unsigned char *)malloc(len); if (!buffer) { debug("SF: Failed to malloc memory.\n"); return 1; } memcpy(buffer, data_out, len); - rx_offset = len; + rx_offset = 0; cmd_len = 0; break; } @@ -275,7 +275,7 @@ int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, } } if (data_in) { - memcpy(data_in, buffer + rx_offset, tran_len); + memcpy(data_in, buffer + 2 * cmd_len, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index f7a92ded6da..a2eee2bca2c 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -289,10 +289,6 @@ static int usba_ep_disable(struct usb_ep *_ep) if (!ep->desc) { spin_unlock_irqrestore(&udc->lock, flags); - /* REVISIT because this driver disables endpoints in - * reset_all_endpoints() before calling disconnect(), - * most gadget drivers would trigger this non-error ... - */ if (udc->gadget.speed != USB_SPEED_UNKNOWN) DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name); @@ -571,20 +567,6 @@ static void reset_all_endpoints(struct usba_udc *udc) list_del_init(&req->queue); request_complete(ep, req, -ECONNRESET); } - - /* NOTE: normally, the next call to the gadget driver is in - * charge of disabling endpoints... usually disconnect(). - * The exception would be entering a high speed test mode. - * - * FIXME remove this code ... and retest thoroughly. - */ - list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { - if (ep->desc) { - spin_unlock(&udc->lock); - usba_ep_disable(&ep->ep); - spin_lock(&udc->lock); - } - } } static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex) diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c index 8f7256069f5..b6c11d97a62 100644 --- a/drivers/usb/gadget/f_acm.c +++ b/drivers/usb/gadget/f_acm.c @@ -548,13 +548,11 @@ static int acm_add(struct usb_configuration *c) status = udc_device_get_by_index(0, &f_acm->udc); if (status) - return status; + goto err; status = usb_add_function(c, &f_acm->usb_function); - if (status) { - free(f_acm); - return status; - } + if (status) + goto err; buf_init(&f_acm->rx_buf, 2048); buf_init(&f_acm->tx_buf, 2048); @@ -562,6 +560,10 @@ static int acm_add(struct usb_configuration *c) if (!default_acm_function) default_acm_function = f_acm; + return 0; + +err: + free(f_acm); return status; } diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 94968ef1c75..404d9140cb2 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "virtio_blk.h" #include @@ -181,7 +182,7 @@ static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, ret = virtio_blk_do_single_req(dev, sector + i, blk_per_sg, buffer + i * 512, type); - if (ret < 0) + if (IS_ERR_VALUE(ret)) return ret; i += blk_per_sg; } diff --git a/drivers/watchdog/apple_wdt.c b/drivers/watchdog/apple_wdt.c index c7307f41cb7..9e998994216 100644 --- a/drivers/watchdog/apple_wdt.c +++ b/drivers/watchdog/apple_wdt.c @@ -78,6 +78,7 @@ static const struct wdt_ops apple_wdt_ops = { }; static const struct udevice_id apple_wdt_ids[] = { + { .compatible = "apple,t8103-wdt" }, { .compatible = "apple,wdt" }, { /* sentinel */ } }; diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index aafbd01a028..3f2e2037745 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -608,9 +608,6 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) root_inum = inum; name = next; } - - kfree(buf); - return 0; } int ubifs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index f88fb9cdb9a..3525e29acc4 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -149,6 +149,8 @@ * shorted - index 1 */ +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/apple.h b/include/configs/apple.h deleted file mode 100644 index 1e08b114480..00000000000 --- a/include/configs/apple.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* Environment */ -#define ENV_DEVICE_SETTINGS \ - "stdin=serial,usbkbd,spikbd\0" \ - "stdout=vidconsole,serial\0" \ - "stderr=vidconsole,serial\0" - -#define BOOT_TARGETS "nvme usb" - -#define CFG_EXTRA_ENV_SETTINGS \ - ENV_DEVICE_SETTINGS \ - "boot_targets=" BOOT_TARGETS "\0" - -#endif diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 45b5cbdd85a..dc0d24dca0a 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -197,10 +197,10 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif -#ifdef CONFIG_MMC +#ifdef CONFIG_CMD_MMC #define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance) #else -#define BOOT_TARGET_DEVICES_MMC(func) +#define BOOT_TARGET_DEVICES_MMC(func, instance) #endif #ifdef CONFIG_SCSI diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 81b5e2aa5bb..5ff2a76fc05 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -10,10 +10,15 @@ /* Console */ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } +#define CFG_HSCIF /* Memory */ -#define DRAM_RSV_SIZE 0x08000000 +#define DRAM_RSV_SIZE 0x20600000 +#ifdef CONFIG_RCAR_64_RSIP +#define CFG_SYS_SDRAM_BASE 0xb8400000 +#else #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#endif #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 3e3f49abae0..e707b146f90 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -33,6 +33,12 @@ #define BOOT_TARGET_MMC1(func) #endif +#ifdef CONFIG_CMD_UBIFS +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) +#else +#define BOOT_TARGET_UBIFS(func) +#endif + #ifdef CONFIG_CMD_USB #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -41,12 +47,14 @@ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC1(func) \ + BOOT_TARGET_UBIFS(func) \ BOOT_TARGET_MMC0(func) \ BOOT_TARGET_USB(func) /* * default bootcmd for stm32mp13: * for serial/usb: execute the stm32prog command + * for nand or spi-nand boot, distro boot with ubifs on UBI partition * for mmc boot (eMMC, SD card), distro boot on the same mmc device */ #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ @@ -56,7 +64,10 @@ "else " \ "run env_check;" \ "if test ${boot_device} = mmc;" \ - "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi; " \ + "if test ${boot_device} = nand ||" \ + " test ${boot_device} = spi-nand ;" \ + "then env set boot_targets ubifs0; fi;" \ "run distro_bootcmd;" \ "fi;\0" diff --git a/include/configs/stm32mp25_st_common.h b/include/configs/stm32mp25_st_common.h index cb679eb1be2..0b0267ae99b 100644 --- a/include/configs/stm32mp25_st_common.h +++ b/include/configs/stm32mp25_st_common.h @@ -8,7 +8,22 @@ #ifndef __CONFIG_STM32MP25_ST_COMMON_H__ #define __CONFIG_STM32MP25_ST_COMMON_H__ +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define SCAN_DEV_FOR_BOOT_PARTS \ + "setenv devplist; " \ + "env exists boot_partuuid && " \ + "part number ${devtype} ${devnum} ${boot_partuuid} devplist; " \ + "env exists devplist || " \ + "part list ${devtype} ${devnum} -bootable devplist; " + +#define ST_STM32MP25_FWU_ENV \ + "altbootcmd=${bootcmd}\0" +#else +#define ST_STM32MP25_FWU_ENV +#endif + #define STM32MP_BOARD_EXTRA_ENV \ + ST_STM32MP25_FWU_ENV \ "usb_pgood_delay=2000\0" \ "console=ttySTM0\0" diff --git a/include/dt-bindings/clock/r8a78000-clock-scmi.h b/include/dt-bindings/clock/r8a78000-clock-scmi.h index 455402ee8cc..663effddeb4 100644 --- a/include/dt-bindings/clock/r8a78000-clock-scmi.h +++ b/include/dt-bindings/clock/r8a78000-clock-scmi.h @@ -43,4 +43,6 @@ #define SCP_CLOCK_ID_MDLC_MPPHY31 347 #define SCP_CLOCK_ID_MDLC_MPPHY02 348 +#define SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN 1691 + #endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */ diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h index e0d10caa589..3d84bfb073a 100644 --- a/include/dt-bindings/reset/r8a78000-reset-scmi.h +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -1,33 +1,27 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2025 Renesas Electronics Corp. - * - * IDs match SCP 4.27 + * Copyright (C) 2025-2026 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__ #define __DT_BINDINGS_R8A78000_SCMI_RESET_H__ -/* - * These definition indices match the Reset ID defined by SCP FW 4.27. - */ +#define SCP_RESET_DOMAIN_ID_UFS0 0x60 +#define SCP_RESET_DOMAIN_ID_UFS1 0x61 -#define SCP_RESET_DOMAIN_ID_UFS0 202 -#define SCP_RESET_DOMAIN_ID_UFS1 203 +#define SCP_RESET_DOMAIN_ID_XPCS0 0x30 +#define SCP_RESET_DOMAIN_ID_XPCS1 0x31 +#define SCP_RESET_DOMAIN_ID_XPCS2 0x32 +#define SCP_RESET_DOMAIN_ID_XPCS3 0x33 +#define SCP_RESET_DOMAIN_ID_XPCS4 0x34 +#define SCP_RESET_DOMAIN_ID_XPCS5 0x35 +#define SCP_RESET_DOMAIN_ID_XPCS6 0x36 +#define SCP_RESET_DOMAIN_ID_XPCS7 0x37 -#define SCP_RESET_DOMAIN_ID_XPCS0 316 -#define SCP_RESET_DOMAIN_ID_XPCS1 317 -#define SCP_RESET_DOMAIN_ID_XPCS2 318 -#define SCP_RESET_DOMAIN_ID_XPCS3 319 -#define SCP_RESET_DOMAIN_ID_XPCS4 320 -#define SCP_RESET_DOMAIN_ID_XPCS5 321 -#define SCP_RESET_DOMAIN_ID_XPCS6 322 -#define SCP_RESET_DOMAIN_ID_XPCS7 323 - -#define SCP_RESET_DOMAIN_ID_MPPHY01 344 -#define SCP_RESET_DOMAIN_ID_MPPHY11 345 -#define SCP_RESET_DOMAIN_ID_MPPHY21 346 -#define SCP_RESET_DOMAIN_ID_MPPHY31 347 -#define SCP_RESET_DOMAIN_ID_MPPHY02 348 +#define SCP_RESET_DOMAIN_ID_MPPHY01 0x64 +#define SCP_RESET_DOMAIN_ID_MPPHY11 0x65 +#define SCP_RESET_DOMAIN_ID_MPPHY21 0x66 +#define SCP_RESET_DOMAIN_ID_MPPHY31 0x67 +#define SCP_RESET_DOMAIN_ID_MPPHY02 0x68 #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ diff --git a/include/fwu.h b/include/fwu.h index 9cee8fb085c..68a51fb4296 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -396,6 +396,17 @@ void fwu_populate_mdata_image_info(struct fwu_data *data); */ int fwu_get_mdata_size(uint32_t *mdata_size); +/** + * fwu_mdata_get_image_guid() - Get image GUID for a type and bank + * @image_guid: Pointer to be filled with the found image GUID + * @image_type_guid: Pointer to the image type GUID to search for + * @bank_index: Index of the bank + * + * Return: 0 if OK, -ve on error + */ +int fwu_mdata_get_image_guid(efi_guid_t *image_guid, + const efi_guid_t *image_type_guid, u32 bank_index); + /** * fwu_state_machine_updates() - Update FWU state of the platform * @state: FWU bank state diff --git a/include/part_efi.h b/include/part_efi.h index 2cea5088046..5713b3018f4 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -60,6 +60,9 @@ #define PARTITION_U_BOOT_ENVIRONMENT \ EFI_GUID( 0x3de21764, 0x95bd, 0x54bd, \ 0xa5, 0xc3, 0x4a, 0xbe, 0x78, 0x6f, 0x38, 0xa8) +#define PARTITION_XBOOTLDR \ + EFI_GUID( 0xbc13c2ff, 0x59e6, 0x4262, \ + 0xa3, 0x52, 0xb2, 0x75, 0xfd, 0x6f, 0x71, 0x72) /* Special ChromiumOS things */ #define PARTITION_CROS_KERNEL \ diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c index 330d7c5830b..7bf51ad43d1 100644 --- a/lib/efi_loader/efi_hii.c +++ b/lib/efi_loader/efi_hii.c @@ -324,7 +324,8 @@ add_keyboard_package(struct efi_hii_packagelist *hii, list_add_tail(&layout_data->link_sys, &efi_keyboard_layout_list); - layout += layout_length; + layout = (struct efi_hii_keyboard_layout *) + ((uintptr_t)layout + layout_length); } list_add_tail(&package_data->link, &hii->keyboard_packages); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 046a2bb4641..2feb29f0a2c 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -495,7 +495,9 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, /* Map would overlap, bail out */ lmb_free(addr, (u64)pages << EFI_PAGE_SHIFT, flags); unmap_sysmem((void *)(uintptr_t)efi_addr); - return EFI_OUT_OF_RESOURCES; + if (type == EFI_ALLOCATE_ADDRESS) + return EFI_NOT_FOUND; + return EFI_OUT_OF_RESOURCES; } *memory = efi_addr; diff --git a/lib/efi_selftest/efi_selftest_hii.c b/lib/efi_selftest/efi_selftest_hii.c index 228dc296950..fdbb08fb417 100644 --- a/lib/efi_selftest/efi_selftest_hii.c +++ b/lib/efi_selftest/efi_selftest_hii.c @@ -452,8 +452,7 @@ out: * test_hii_database_get_keyboard_layout() - test retrieval of keyboard layout * * This test adds two package lists, each of which has two keyboard layouts - * and then tries to get a handle to keyboard layout with a specific guid - * and the current one. + * and then tries to get a handle to every keyboard layout and the current one. * * @Return: status code */ @@ -463,7 +462,11 @@ static int test_hii_database_get_keyboard_layout(void) struct efi_hii_keyboard_layout *kb_layout; u16 kb_layout_size; efi_status_t ret; - int result = EFI_ST_FAILURE; + int result = EFI_ST_FAILURE, i; + static efi_guid_t *const kb_layout_guids[] = { + &kb_layout_guid11, &kb_layout_guid12, + &kb_layout_guid21, &kb_layout_guid22 + }; PRINT_TESTNAME; ret = hii_database_protocol->new_package_list(hii_database_protocol, @@ -484,33 +487,37 @@ static int test_hii_database_get_keyboard_layout(void) goto out; } - /* specific keyboard_layout(guid11) */ - kb_layout = NULL; - kb_layout_size = 0; - ret = hii_database_protocol->get_keyboard_layout(hii_database_protocol, - &kb_layout_guid11, &kb_layout_size, kb_layout); - if (ret != EFI_BUFFER_TOO_SMALL) { - efi_st_error("get_keyboard_layout returned %u\n", - (unsigned int)ret); - goto out; - } - ret = boottime->allocate_pool(EFI_LOADER_DATA, kb_layout_size, - (void **)&kb_layout); - if (ret != EFI_SUCCESS) { - efi_st_error("AllocatePool failed\n"); - goto out; - } - ret = hii_database_protocol->get_keyboard_layout(hii_database_protocol, - &kb_layout_guid11, &kb_layout_size, kb_layout); - if (ret != EFI_SUCCESS) { - efi_st_error("get_keyboard_layout returned %u\n", - (unsigned int)ret); - goto out; - } - ret = boottime->free_pool(kb_layout); - if (ret != EFI_SUCCESS) { - efi_st_error("FreePool failed\n"); - goto out; + /* Verify all keyboard layouts */ + for (i = 0; i < ARRAY_SIZE(kb_layout_guids); i++) { + efi_guid_t *kb_layout_guid = kb_layout_guids[i]; + + kb_layout = NULL; + kb_layout_size = 0; + ret = hii_database_protocol->get_keyboard_layout(hii_database_protocol, + kb_layout_guid, &kb_layout_size, kb_layout); + if (ret != EFI_BUFFER_TOO_SMALL) { + efi_st_error("get_keyboard_layout returned %u\n", + (unsigned int)ret); + goto out; + } + ret = boottime->allocate_pool(EFI_LOADER_DATA, kb_layout_size, + (void **)&kb_layout); + if (ret != EFI_SUCCESS) { + efi_st_error("AllocatePool failed\n"); + goto out; + } + ret = hii_database_protocol->get_keyboard_layout(hii_database_protocol, + kb_layout_guid, &kb_layout_size, kb_layout); + if (ret != EFI_SUCCESS) { + efi_st_error("get_keyboard_layout returned %u\n", + (unsigned int)ret); + goto out; + } + ret = boottime->free_pool(kb_layout); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + goto out; + } } /* current */ diff --git a/lib/efi_selftest/efi_selftest_hii_data.c b/lib/efi_selftest/efi_selftest_hii_data.c index 5fc890112b4..2d29bb045d3 100644 --- a/lib/efi_selftest/efi_selftest_hii_data.c +++ b/lib/efi_selftest/efi_selftest_hii_data.c @@ -428,6 +428,18 @@ static efi_guid_t kb_layout_guid11 = EFI_GUID(0x8d40e495, 0xe2aa, 0x4c6f, 0x89, 0x70, 0x68, 0x85, 0x09, 0xee, 0xc7, 0xd2); +static efi_guid_t kb_layout_guid12 = + EFI_GUID(0x2ae60b3e, 0xb9d6, 0x49d8, + 0x9a, 0x16, 0xc2, 0x48, 0xf1, 0xeb, 0xa8, 0xdb); + +static efi_guid_t kb_layout_guid21 = + EFI_GUID(0xe0f56a1f, 0xdf6b, 0x4a7e, + 0xa3, 0x9a, 0xe7, 0xa5, 0x19, 0x15, 0x45, 0xd6); + +static efi_guid_t kb_layout_guid22 = + EFI_GUID(0x47be6ac9, 0x54cc, 0x46f9, + 0xa2, 0x62, 0xd5, 0x3b, 0x25, 0x6a, 0x0c, 0x34); + static efi_guid_t package_guid = EFI_GUID(0x0387c95a, 0xd703, 0x2346, 0xb2, 0xab, 0xd0, 0xc7, 0xdd, 0x90, 0x44, 0xf8); diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index e82600a29a4..2b11e5da061 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -243,6 +243,39 @@ int fwu_sync_mdata(struct fwu_mdata *mdata, int part) return 0; } +/** + * fwu_mdata_get_image_guid() - Get image GUID for a type and bank + * @image_guid: Pointer to be filled with the found image GUID + * @image_type_guid: Pointer to the image type GUID to search for + * @bank_index: Index of the bank + * + * Return: 0 if OK, -ve on error + */ +int fwu_mdata_get_image_guid(efi_guid_t *image_guid, + const efi_guid_t *image_type_guid, u32 bank_index) +{ + struct fwu_data *data = &g_fwu_data; + struct fwu_image_entry *image; + int i; + + if (bank_index >= data->num_banks) + return -EINVAL; + + for (i = 0; i < data->num_images; i++) { + image = &data->fwu_images[i]; + + if (!guidcmp(image_type_guid, &image->image_type_guid)) { + struct fwu_image_bank_info *bank; + + bank = &image->img_bank_info[bank_index]; + guidcpy(image_guid, &bank->image_guid); + return 0; + } + } + + return -ENOENT; +} + /** * fwu_mdata_copies_allocate() - Allocate memory for metadata * @mdata_size: Size of the metadata structure diff --git a/lib/smbios.c b/lib/smbios.c index d5f18c8bd69..906d2753517 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -292,7 +292,7 @@ static int smbios_get_val_si(struct smbios_ctx * __maybe_unused ctx, /* If the node is still missing, try with the mapping values */ nprop = convert_sysinfo_to_dt(ctx->subnode_name, prop); - if (!ofnode_read_u32(ofnode_root(), nprop->dt_str, &val)) + if (nprop && !ofnode_read_u32(ofnode_root(), nprop->dt_str, &val)) return val; #endif return val_def; diff --git a/lib/uuid.c b/lib/uuid.c index 3a666d0430d..d7c164ea06b 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -86,6 +86,7 @@ static const struct { {"swap", NULL, PARTITION_LINUX_SWAP_GUID}, {"lvm", NULL, PARTITION_LINUX_LVM_GUID}, {"u-boot-env", NULL, PARTITION_U_BOOT_ENVIRONMENT}, + {"xbootldr", NULL, PARTITION_XBOOTLDR}, {"cros-kern", NULL, PARTITION_CROS_KERNEL}, {"cros-root", NULL, PARTITION_CROS_ROOT}, {"cros-fw", NULL, PARTITION_CROS_FIRMWARE}, diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 5f2815b1bb6..8d6932f1176 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CMD_LOADM) += loadm.o obj-$(CONFIG_CMD_MEMINFO) += meminfo.o obj-$(CONFIG_CMD_MEMORY) += mem_copy.o obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o +obj-$(CONFIG_CMD_PART) += part.o ifdef CONFIG_CMD_PCI obj-$(CONFIG_CMD_PCI_MPS) += pci_mps.o endif diff --git a/test/cmd/part.c b/test/cmd/part.c new file mode 100644 index 00000000000..e0149011476 --- /dev/null +++ b/test/cmd/part.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for part command + * + * Copyright (C) 2026 Amarula Solutions + * Written by Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct disk_partition gpt_parts[] = { + { + .start = 48, + .size = 1, + .name = "test1", + .uuid = "c5bce7a2-03f0-4d03-9048-01ff23b9d527", + }, + { + .start = 49, + .size = 2, + .name = "test2", + .uuid = "9df346e8-2c53-4cd8-b9ac-3af83f9a9b74", + }, +}; + +static char disk_guid[UUID_STR_LEN + 1] = + "8d60b397-1bb6-4d33-80ee-b1587d24c2f8"; + +static int setup_gpt_partitions(struct unit_test_state *uts, + unsigned int mmc_dev_num) +{ + struct blk_desc *mmc_dev_desc; + char dev_str[10]; + int i, ret; + + if (!CONFIG_IS_ENABLED(MMC)) + return -EAGAIN; + + snprintf(dev_str, sizeof(dev_str), "%u", mmc_dev_num); + + ret = blk_get_device_by_str("mmc", dev_str, &mmc_dev_desc); + if (ret == -ENODEV) + return -EAGAIN; + + ut_asserteq(mmc_dev_num, ret); + + if (CONFIG_IS_ENABLED(RANDOM_UUID)) { + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) + gen_rand_uuid_str(gpt_parts[i].uuid, + UUID_STR_FORMAT_STD); + + gen_rand_uuid_str(disk_guid, UUID_STR_FORMAT_STD); + } + + ut_assertok(gpt_restore(mmc_dev_desc, disk_guid, gpt_parts, + ARRAY_SIZE(gpt_parts))); + return 0; +} + +static int cmd_test_part_number(struct unit_test_state *uts) +{ + unsigned int mmc_dev_num = 2; + char expected[10]; + int i, ret; + + ret = setup_gpt_partitions(uts, mmc_dev_num); + if (ret == -EAGAIN) + return ret; + + ut_assertok(ret); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partnum", NULL); + ut_assertok(run_commandf("part number mmc %u %s partnum", + mmc_dev_num, gpt_parts[i].name)); + snprintf(expected, sizeof(expected), "0x%x", i + 1); + ut_asserteq_str(expected, env_get("partnum")); + } + + env_set("partnum", NULL); + ut_asserteq(1, run_commandf("part number mmc %u bogus partnum", + mmc_dev_num)); + ut_assertnull(env_get("partnum")); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partnum", NULL); + ut_assertok(run_commandf("part number mmc %u %s partnum", + mmc_dev_num, gpt_parts[i].uuid)); + snprintf(expected, sizeof(expected), "0x%x", i + 1); + ut_asserteq_str(expected, env_get("partnum")); + } + + env_set("partnum", NULL); + ut_asserteq(1, run_commandf("part number mmc %u %s partnum", + mmc_dev_num, + "00000000-0000-0000-0000-000000000000")); + ut_assertnull(env_get("partnum")); + + return 0; +} +CMD_TEST(cmd_test_part_number, UTF_CONSOLE); + +static int cmd_test_part_start(struct unit_test_state *uts) +{ + unsigned int mmc_dev_num = 2; + char expected[32]; + int i, ret; + + ret = setup_gpt_partitions(uts, mmc_dev_num); + if (ret == -EAGAIN) + return ret; + + ut_assertok(ret); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partstart", NULL); + ut_assertok(run_commandf("part start mmc %u %d partstart", + mmc_dev_num, i + 1)); + snprintf(expected, sizeof(expected), "%lx", + (unsigned long)gpt_parts[i].start); + ut_asserteq_str(expected, env_get("partstart")); + } + + env_set("partstart", NULL); + ut_asserteq(1, run_commandf("part start mmc %u 3 partstart", + mmc_dev_num)); + ut_assertnull(env_get("partstart")); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partstart", NULL); + ut_assertok(run_commandf("part start mmc %u %s partstart", + mmc_dev_num, gpt_parts[i].name)); + snprintf(expected, sizeof(expected), "%lx", + (unsigned long)gpt_parts[i].start); + ut_asserteq_str(expected, env_get("partstart")); + } + + env_set("partstart", NULL); + ut_asserteq(1, run_commandf("part start mmc %u bogus partstart", + mmc_dev_num)); + ut_assertnull(env_get("partstart")); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partstart", NULL); + ut_assertok(run_commandf("part start mmc %u %s partstart", + mmc_dev_num, gpt_parts[i].uuid)); + snprintf(expected, sizeof(expected), "%lx", + (unsigned long)gpt_parts[i].start); + ut_asserteq_str(expected, env_get("partstart")); + } + + env_set("partstart", NULL); + ut_asserteq(1, run_commandf("part start mmc %u %s partstart", + mmc_dev_num, + "00000000-0000-0000-0000-000000000000")); + ut_assertnull(env_get("partstart")); + + return 0; +} +CMD_TEST(cmd_test_part_start, UTF_CONSOLE); + +static int cmd_test_part_size(struct unit_test_state *uts) +{ + unsigned int mmc_dev_num = 2; + char expected[32]; + int i, ret; + + ret = setup_gpt_partitions(uts, mmc_dev_num); + if (ret == -EAGAIN) + return ret; + + ut_assertok(ret); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partsize", NULL); + ut_assertok(run_commandf("part size mmc %u %d partsize", + mmc_dev_num, i + 1)); + snprintf(expected, sizeof(expected), "%lx", + (unsigned long)gpt_parts[i].size); + ut_asserteq_str(expected, env_get("partsize")); + } + + env_set("partsize", NULL); + ut_asserteq(1, run_commandf("part size mmc %u 3 partsize", + mmc_dev_num)); + ut_assertnull(env_get("partsize")); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partsize", NULL); + ut_assertok(run_commandf("part size mmc %u %s partsize", + mmc_dev_num, gpt_parts[i].name)); + snprintf(expected, sizeof(expected), "%lx", + (unsigned long)gpt_parts[i].size); + ut_asserteq_str(expected, env_get("partsize")); + } + + env_set("partsize", NULL); + ut_asserteq(1, run_commandf("part size mmc %u bogus partsize", + mmc_dev_num)); + ut_assertnull(env_get("partsize")); + + for (i = 0; i < ARRAY_SIZE(gpt_parts); i++) { + env_set("partsize", NULL); + ut_assertok(run_commandf("part size mmc %u %s partsize", + mmc_dev_num, gpt_parts[i].uuid)); + snprintf(expected, sizeof(expected), "%lx", + (unsigned long)gpt_parts[i].size); + ut_asserteq_str(expected, env_get("partsize")); + } + + env_set("partsize", NULL); + ut_asserteq(1, run_commandf("part size mmc %u %s partsize", + mmc_dev_num, + "00000000-0000-0000-0000-000000000000")); + ut_assertnull(env_get("partsize")); + + return 0; +} +CMD_TEST(cmd_test_part_size, UTF_CONSOLE); diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c index cfe543d8a23..8624ccf61f7 100644 --- a/test/dm/fwu_mdata.c +++ b/test/dm/fwu_mdata.c @@ -143,3 +143,51 @@ static int dm_test_fwu_mdata_write(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_fwu_mdata_write, UTF_SCAN_FDT); + +static int dm_test_fwu_mdata_get_image_guid(struct unit_test_state *uts) +{ + efi_guid_t image_type_guid = + EFI_GUID(0x09d7cf52, 0x0720, 0x4710, \ + 0x91, 0xd1, 0x08, 0x46, 0x9b, 0x7f, 0xe9, 0xc8); + efi_guid_t bank_0_image_guid = + EFI_GUID(0x10057a86, 0xdaf1, 0x4f93, \ + 0xba, 0x7f, 0xb1, 0x95, 0xf7, 0xfa, 0x41, 0x70); + efi_guid_t bank_1_image_guid = + EFI_GUID(0xdb62ed3e, 0x6237, 0x4fb4, \ + 0x80, 0xc4, 0x1b, 0x74, 0xd8, 0x46, 0xa8, 0xe7); + efi_guid_t wrong_image_type_guid = + EFI_GUID(0x12345678, 0x1302, 0x133f, \ + 0x18, 0x0a, 0x14, 0x05, 0x18, 0x05, 0x14, 0x0b); + struct udevice *dev; + efi_guid_t image_guid; + + ut_assertok(setup_blk_device(uts)); + ut_assertok(populate_mmc_disk_image(uts)); + ut_assertok(write_mmc_blk_device(uts)); + + /* + * Trigger lib/fwu_updates/fwu.c fwu_boottime_checks() + * to populate g_dev global pointer in that library. + */ + ut_assertok(event_notify_null(EVT_POST_PREBOOT)); + + ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev)); + + ut_assertok(fwu_init()); + + ut_assertok(fwu_mdata_get_image_guid(&image_guid, &image_type_guid, 0)); + ut_assertok(guidcmp(&image_guid, &bank_0_image_guid)); + + ut_assertok(fwu_mdata_get_image_guid(&image_guid, &image_type_guid, 1)); + ut_assertok(guidcmp(&image_guid, &bank_1_image_guid)); + + ut_asserteq(-EINVAL, fwu_mdata_get_image_guid(&image_guid, + &image_type_guid, 2)); + + ut_asserteq(-ENOENT, fwu_mdata_get_image_guid(&image_guid, + &wrong_image_type_guid, + 0)); + + return 0; +} +DM_TEST(dm_test_fwu_mdata_get_image_guid, UTF_SCAN_FDT); diff --git a/test/dm/part.c b/test/dm/part.c index caae23bd4aa..ad37d7f406f 100644 --- a/test/dm/part.c +++ b/test/dm/part.c @@ -195,3 +195,56 @@ static int dm_test_part_get_info_by_type(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_part_get_info_by_type, UTF_SCAN_PDATA | UTF_SCAN_FDT); + +static int dm_test_part_get_info_by_uuid(struct unit_test_state *uts) +{ + struct disk_partition parts[] = { + { + .start = 48, + .size = 1, + .name = "test1", + .uuid = "c5bce7a2-03f0-4d03-9048-01ff23b9d527", + }, + { + .start = 49, + .size = 1, + .name = "test2", + .uuid = "9df346e8-2c53-4cd8-b9ac-3af83f9a9b74", + }, + }; + char disk_guid[UUID_STR_LEN + 1] = + "8d60b397-1bb6-4d33-80ee-b1587d24c2f8"; + struct blk_desc *mmc_dev_desc; + struct disk_partition info; + int part, i; + + ut_asserteq(2, blk_get_device_by_str("mmc", "2", &mmc_dev_desc)); + + if (CONFIG_IS_ENABLED(RANDOM_UUID)) { + for (i = 0; i < ARRAY_SIZE(parts); i++) + gen_rand_uuid_str(parts[i].uuid, UUID_STR_FORMAT_STD); + + gen_rand_uuid_str(disk_guid, UUID_STR_FORMAT_STD); + } + + ut_assertok(gpt_restore(mmc_dev_desc, disk_guid, parts, + ARRAY_SIZE(parts))); + + for (i = 0; i < ARRAY_SIZE(parts); i++) { + part = part_get_info_by_uuid(mmc_dev_desc, parts[i].uuid, + &info); + + ut_asserteq(i + 1, part); + ut_asserteq_str(parts[i].name, info.name); + ut_asserteq(parts[i].start, info.start); + ut_asserteq(parts[i].size, info.size); + } + + part = part_get_info_by_uuid(mmc_dev_desc, + "00000000-0000-0000-0000-000000000000", + &info); + ut_assert(part < 0); + + return 0; +} +DM_TEST(dm_test_part_get_info_by_uuid, UTF_SCAN_PDATA | UTF_SCAN_FDT); diff --git a/tools/binman/etype/atf_fip.py b/tools/binman/etype/atf_fip.py index 636e073afc8..681b7900682 100644 --- a/tools/binman/etype/atf_fip.py +++ b/tools/binman/etype/atf_fip.py @@ -163,7 +163,7 @@ class Entry_atf_fip(Entry_section): .. _FIP: https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#firmware-image-package-fip .. _`TF-A source tree`: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git - .. _`send a patch`: https://docs.u-boot.org/en/latest/develop/sending_patches.html + .. _`send a patch`: https://docs.u-boot-project.org/en/latest/develop/sending_patches.html """ def __init__(self, section, etype, node): # Put this here to allow entry-docs and help to work without libfdt diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help index d2ed35bef4d..27dc620bd35 100644 --- a/tools/binman/missing-blob-help +++ b/tools/binman/missing-blob-help @@ -55,7 +55,7 @@ HS-FS and HS-SE parts will not boot without this certificate. Have a look at your board's documentation to find and include the latest TIFS certificate blobs and how to include them in the build. - https://docs.u-boot.org/en/latest/board/ti/k3.html + https://docs.u-boot-project.org/en/latest/board/ti/k3.html tee-os: See the documentation for your board. You may need to build Open Portable @@ -69,7 +69,7 @@ will not boot without this firmware. Have a look at your board's documentation to find the latest version of the DM firmware binary and how to include it in the build. - https://docs.u-boot.org/en/latest/board/ti/k3.html + https://docs.u-boot-project.org/en/latest/board/ti/k3.html ti-fs-enc.bin: You are missing TI's Foundational Security (TIFS) firmware which is @@ -80,4 +80,4 @@ this firmware. Have a look at your board's documentation to find the latest version of the TIFS firmware binary and how to include them in the build. - https://docs.u-boot.org/en/latest/board/ti/k3.html + https://docs.u-boot-project.org/en/latest/board/ti/k3.html diff --git a/tools/binman/pyproject.toml b/tools/binman/pyproject.toml index 7c9ab0f2a27..2f17588e9df 100644 --- a/tools/binman/pyproject.toml +++ b/tools/binman/pyproject.toml @@ -19,7 +19,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://docs.u-boot.org/en/latest/develop/package/index.html" +"Homepage" = "https://docs.u-boot-project.org/en/latest/develop/package/index.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] diff --git a/tools/buildman/pyproject.toml b/tools/buildman/pyproject.toml index 274042df155..5f5c405afbf 100644 --- a/tools/buildman/pyproject.toml +++ b/tools/buildman/pyproject.toml @@ -23,7 +23,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://docs.u-boot.org/en/latest/build/buildman.html" +"Homepage" = "https://docs.u-boot-project.org/en/latest/build/buildman.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] diff --git a/tools/dtoc/pyproject.toml b/tools/dtoc/pyproject.toml index cc96cf784c6..53b09dba885 100644 --- a/tools/dtoc/pyproject.toml +++ b/tools/dtoc/pyproject.toml @@ -19,7 +19,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://docs.u-boot.org/en/latest/develop/driver-model/of-plat.html" +"Homepage" = "https://docs.u-boot-project.org/en/latest/develop/driver-model/of-plat.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] diff --git a/tools/fwumdata_src/fwumdata.c b/tools/fwumdata_src/fwumdata.c index c5b0f56842d..44195ce2bf2 100644 --- a/tools/fwumdata_src/fwumdata.c +++ b/tools/fwumdata_src/fwumdata.c @@ -84,6 +84,7 @@ static int parse_config(const char *fname) if (line[0] == '#' || line[0] == '\n') continue; + devname = NULL; rc = sscanf(line, "%ms %lli %lx %lx", &devname, &devices[i].devoff, diff --git a/tools/patman/pyproject.toml b/tools/patman/pyproject.toml index 91802c8cc27..0fc4b7d4ecd 100644 --- a/tools/patman/pyproject.toml +++ b/tools/patman/pyproject.toml @@ -19,7 +19,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://docs.u-boot.org/en/latest/develop/patman.html" +"Homepage" = "https://docs.u-boot-project.org/en/latest/develop/patman.html" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [project.scripts] diff --git a/tools/u_boot_pylib/pyproject.toml b/tools/u_boot_pylib/pyproject.toml index ed04d956b4e..1c6a023ee4b 100644 --- a/tools/u_boot_pylib/pyproject.toml +++ b/tools/u_boot_pylib/pyproject.toml @@ -18,7 +18,7 @@ classifiers = [ ] [project.urls] -"Homepage" = "https://docs.u-boot.org" +"Homepage" = "https://docs.u-boot-project.org" "Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" [tool.setuptools]