Merge tag 'u-boot-imx-20221024' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20221024 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13916 - for 2022.01 - rework Kontron boards (mx6 and mx8) - fixes for Toradex - fixes (SPI, CAAM, ) - sync DT with Linux - fixes for Gateworks GW7903 and GW7904 PMIC - Engicam i.Core MX8M Plus EDIMM2.2
2026-06-13 15:03:58 +03:00 · 2022-10-24 10:04:30 -04:00
parent 1e892ef0b5 0f5caf351c
commit 7d8ab3cd63
170 changed files with 9621 additions and 6450 deletions
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -70,11 +70,11 @@

 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x20000000\0" \
-	"fdt_addr_r=0x12100000\0" \
-	"kernel_addr_r=0x11000000\0" \
-	"pxefile_addr_r=0x17100000\0" \
-	"ramdisk_addr_r=0x12200000\0" \
-	"scriptaddr=0x17000000\0"
+	"fdt_addr_r=0x18200000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"pxefile_addr_r=0x18300000\0" \
+	"ramdisk_addr_r=0x18400000\0" \
+	"scriptaddr=0x18280000\0"

 #define CONFIG_EXTRA_ENV_SETTINGS \
 	BOOTENV \
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -43,11 +43,11 @@

 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x10000000\0" \
-	"fdt_addr_r=0x82100000\0" \
-	"kernel_addr_r=0x81000000\0" \
-	"pxefile_addr_r=0x87100000\0" \
-	"ramdisk_addr_r=0x82200000\0" \
-	"scriptaddr=0x87000000\0"
+	"fdt_addr_r=0x88200000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"pxefile_addr_r=0x88300000\0" \
+	"ramdisk_addr_r=0x88400000\0" \
+	"scriptaddr=0x88280000\0"

 #define UBI_BOOTCMD \
 	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -66,11 +66,11 @@

 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x10000000\0" \
-	"fdt_addr_r=0x12100000\0" \
-	"kernel_addr_r=0x11000000\0" \
-	"pxefile_addr_r=0x17100000\0" \
-	"ramdisk_addr_r=0x12200000\0" \
-	"scriptaddr=0x17000000\0"
+	"fdt_addr_r=0x18200000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"pxefile_addr_r=0x18300000\0" \
+	"ramdisk_addr_r=0x18400000\0" \
+	"scriptaddr=0x18280000\0"

 #define CONFIG_EXTRA_ENV_SETTINGS \
 	BOOTENV \
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -83,11 +83,11 @@

 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0x10000000\0" \
-	"fdt_addr_r=0x82000000\0" \
-	"kernel_addr_r=0x81000000\0" \
-	"pxefile_addr_r=0x87100000\0" \
-	"ramdisk_addr_r=0x82100000\0" \
-	"scriptaddr=0x87000000\0"
+	"fdt_addr_r=0x88200000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"pxefile_addr_r=0x88300000\0" \
+	"ramdisk_addr_r=0x88400000\0" \
+	"scriptaddr=0x88280000\0"

 #define UBI_BOOTCMD	\
 	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -60,8 +60,7 @@
 	"fdtfile=imx6q-dhcom-pdk2.dtb\0"\
 	"update_sf=" /* Erase SPI NOR and install U-Boot from SD */	\
 		"load mmc 0:1 ${loadaddr} /boot/u-boot-with-spl.imx && "\
-		"sf probe && sf erase 0x0 0x100000 && "			\
-		"sf write ${loadaddr} 0x400 ${filesize}\0"		\
+		"sf probe && sf update ${loadaddr} 0x400 ${filesize}\0"	\
 	BOOTENV

 #define BOOT_TARGET_DEVICES(func) \
--- a/include/configs/imx8mm-mx8menlo.h
+++ b/include/configs/imx8mm-mx8menlo.h
@@ -25,7 +25,7 @@
 		"fi ; "							\
 		"boot\0"						\
 	"boot_file=fitImage\0"						\
-	"console=ttymxc1\0"						\
+	"console=ttymxc0\0"						\
 	"fdt_addr=0x43000000\0"						\
 	"initrd_addr=0x43800000\0"					\
 	"kernel_image=fitImage\0"
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -55,11 +55,9 @@
 #define CONFIG_SYS_INIT_RAM_SIZE	0x80000


-/* Totally 6GB DDR */
+/* Totally 2GB DDR */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define PHYS_SDRAM			0x40000000
-#define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
-#define PHYS_SDRAM_2			0x100000000
-#define PHYS_SDRAM_2_SIZE		0xC0000000	/* 3 GB */
+#define PHYS_SDRAM_SIZE			0x80000000

 #endif
--- a/include/configs/imx8mp_icore_mx8mp.h
+++ b/include/configs/imx8mp_icore_mx8mp.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2022 Amarula Solutions(India)
+ */
+
+#ifndef __IMX8MP_ICORE_MX8MP_H
+#define __IMX8MP_ICORE_MX8MP_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+#define CONFIG_POWER_PCA9450
+
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_FEC_MXC_PHYADDR          1
+
+#define DWC_NET_PHYADDR			1
+
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	BOOTENV \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"fdt_addr_r=0x43000000\0"			\
+	"boot_fdt=try\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"bootm_size=0x10000000\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+
+/* Totally 2GB DDR */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x80000000
+
+#endif /* __IMX8MP_ICORE_MX8MP_H */
--- a/include/configs/kontron-sl-mx6ul.h
+++ b/include/configs/kontron-sl-mx6ul.h
@@ -49,14 +49,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif

-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernel_addr_r=0x82000000\0" \
-	"ramdisk_addr_r=0x88080000\0" \
-	"pxefile_addr_r=0x80100000\0" \
-	"scriptaddr=0x80100000\0" \
-	"bootdelay=3\0" \
-	"ethact=" CONFIG_ETHPRIME "\0" \
-	"hostname=" CONFIG_HOSTNAME "\0" \
-	BOOTENV
+#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV

 #endif /* __KONTRON_MX6UL_CONFIG_H */
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -50,20 +50,6 @@
 #define CONFIG_MALLOC_F_ADDR		0x930000
 #endif

-#define ENV_MEM_LAYOUT_SETTINGS \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"kernel_addr_r=0x42000000\0" \
-	"fdt_addr_r=0x48000000\0" \
-	"fdtoverlay_addr_r=0x49000000\0" \
-	"ramdisk_addr_r=0x48080000\0" \
-	"scriptaddr=0x40000000\0"\
-	"pxefile_addr_r=0x40100000\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \
-	"bootdelay=3\0" \
-	"hostname=" CONFIG_HOSTNAME "\0" \
-	ENV_MEM_LAYOUT_SETTINGS \
-	BOOTENV
+#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV

 #endif /* __KONTRON_MX8MM_CONFIG_H */
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -76,7 +76,7 @@
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"fdt_addr_r=0x18000000\0" \
-	"fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \
+	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"  \
 	"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -61,10 +61,6 @@
 	"pxefile_addr_r=0x10100000\0" \
 	"ramdisk_addr_r=0x18080000\0" \
 	"scriptaddr=0x10000000\0" \
-	"set_con_serial=setenv stdout serial; " \
-			"setenv stderr serial\0" \
-	"set_con_hdmi=setenv stdout serial,vidconsole; " \
-			"setenv stderr serial,vidconsole\0" \
 	"stderr=serial,vidconsole\0" \
 	"stdin=serial,usbkbd\0" \
 	"stdout=serial,vidconsole\0"
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -23,7 +23,7 @@
 	"fdt_addr_r=0x50200000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"kernel_comp_addr_r=0x40200000\0" \
-	"kernel_comp_size=0x08080000\0" \
+	"kernel_comp_size=0x08000000\0" \
 	"ramdisk_addr_r=0x50300000\0" \
 	"scriptaddr=0x50280000\0"

@@ -67,9 +67,6 @@
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE			SZ_2G /* 2GB DDR */

-/* ENET */
-#define CONFIG_FEC_MXC_PHYADDR          7
-
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)

--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -25,19 +25,11 @@
 #define CONFIG_SYS_I2C
 #endif /* CONFIG_SPL_BUILD */

-/* ENET Config */
-/* ENET1 */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_FEC_MXC_PHYADDR		7
-
-#define PHY_ANEG_TIMEOUT 20000
-#endif /* CONFIG_CMD_NET */
-
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"fdt_addr_r=0x50200000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"kernel_comp_addr_r=0x40200000\0" \
-	"kernel_comp_size=0x08080000\0" \
+	"kernel_comp_size=0x08000000\0" \
 	"ramdisk_addr_r=0x50300000\0" \
 	"scriptaddr=0x50280000\0"

--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
 * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
 */

 #ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
@@ -175,6 +171,8 @@
 #define IMX6SL_CLK_SSI2_IPG		162
 #define IMX6SL_CLK_SSI3_IPG		163
 #define IMX6SL_CLK_SPDIF_GCLK		164
-#define IMX6SL_CLK_END			165
+#define IMX6SL_CLK_MMDC_P0_IPG		165
+#define IMX6SL_CLK_MMDC_P1_IPG		166
+#define IMX6SL_CLK_END			167

 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
--- a/include/dt-bindings/clock/imx6sll-clock.h
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -1,9 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017-2018 NXP.
 *
 */

@@ -199,6 +197,14 @@
 #define IMX6SLL_CLK_EXTERN_AUDIO_PODF   171
 #define IMX6SLL_CLK_EXTERN_AUDIO        172

-#define IMX6SLL_CLK_END			173
+#define IMX6SLL_CLK_GPIO1               173
+#define IMX6SLL_CLK_GPIO2               174
+#define IMX6SLL_CLK_GPIO3               175
+#define IMX6SLL_CLK_GPIO4               176
+#define IMX6SLL_CLK_GPIO5               177
+#define IMX6SLL_CLK_GPIO6               178
+#define IMX6SLL_CLK_MMDC_P1_IPG		179
+
+#define IMX6SLL_CLK_END			180

 #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -1,21 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * Copyright 2017~2018 NXP
 *
 */

 #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
 #define __DT_BINDINGS_CLOCK_IMX7ULP_H

-#define IMX7ULP_CLK_DUMMY		0
-#define IMX7ULP_CLK_CKIL		1
-#define IMX7ULP_CLK_OSC			2
-#define IMX7ULP_CLK_FIRC		3
-
 /* SCG1 */
+
+#define IMX7ULP_CLK_DUMMY		0
+#define IMX7ULP_CLK_ROSC		1
+#define IMX7ULP_CLK_SOSC		2
+#define IMX7ULP_CLK_FIRC		3
 #define IMX7ULP_CLK_SPLL_PRE_SEL	4
 #define IMX7ULP_CLK_SPLL_PRE_DIV	5
 #define IMX7ULP_CLK_SPLL		6
@@ -51,111 +49,71 @@
 #define IMX7ULP_CLK_NIC1_DIV		36
 #define IMX7ULP_CLK_NIC1_BUS_DIV	37
 #define IMX7ULP_CLK_NIC1_EXT_DIV	38
+/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
+#define IMX7ULP_CLK_MIPI_PLL		39
+#define IMX7ULP_CLK_SIRC		40
+#define IMX7ULP_CLK_SOSC_BUS_CLK	41
+#define IMX7ULP_CLK_FIRC_BUS_CLK	42
+#define IMX7ULP_CLK_SPLL_BUS_CLK	43
+#define IMX7ULP_CLK_HSRUN_SYS_SEL	44
+#define IMX7ULP_CLK_HSRUN_CORE_DIV	45

-/* PCG2 */
-#define IMX7ULP_CLK_DMA1		39
-#define IMX7ULP_CLK_RGPIO2P1		40
-#define IMX7ULP_CLK_FLEXBUS		41
-#define IMX7ULP_CLK_SEMA42_1		42
-#define IMX7ULP_CLK_DMA_MUX1		43
-#define IMX7ULP_CLK_SNVS		44
-#define IMX7ULP_CLK_CAAM		45
-#define IMX7ULP_CLK_LPTPM4		46
-#define IMX7ULP_CLK_LPTPM5		47
-#define IMX7ULP_CLK_LPIT1		48
-#define IMX7ULP_CLK_LPSPI2		49
-#define IMX7ULP_CLK_LPSPI3		50
-#define IMX7ULP_CLK_LPI2C4		51
-#define IMX7ULP_CLK_LPI2C5		52
-#define IMX7ULP_CLK_LPUART4		53
-#define IMX7ULP_CLK_LPUART5		54
-#define IMX7ULP_CLK_FLEXIO1		55
-#define IMX7ULP_CLK_USB0		56
-#define IMX7ULP_CLK_USB1		57
-#define IMX7ULP_CLK_USB_PHY		58
-#define IMX7ULP_CLK_USB_PL301		59
-#define IMX7ULP_CLK_USDHC0		60
-#define IMX7ULP_CLK_USDHC1		61
-#define IMX7ULP_CLK_WDG1		62
-#define IMX7ULP_CLK_WDG2		63
+#define IMX7ULP_CLK_CORE		46
+#define IMX7ULP_CLK_HSRUN_CORE		47

-/* PCG3 */
-#define IMX7ULP_CLK_LPTPM6		64
-#define IMX7ULP_CLK_LPTPM7		65
-#define IMX7ULP_CLK_LPI2C6		66
-#define IMX7ULP_CLK_LPI2C7		67
-#define IMX7ULP_CLK_LPUART6		68
-#define IMX7ULP_CLK_LPUART7		69
-#define IMX7ULP_CLK_VIU			70
-#define IMX7ULP_CLK_DSI			71
-#define IMX7ULP_CLK_LCDIF		72
-#define IMX7ULP_CLK_MMDC		73
-#define IMX7ULP_CLK_PCTLC		74
-#define IMX7ULP_CLK_PCTLD		75
-#define IMX7ULP_CLK_PCTLE		76
-#define IMX7ULP_CLK_PCTLF		77
-#define IMX7ULP_CLK_GPU3D		78
-#define IMX7ULP_CLK_GPU2D		79
+#define IMX7ULP_CLK_SCG1_END		48

-#define IMX7ULP_CLK_MIPI_PLL		80
-#define IMX7ULP_CLK_SIRC		81
+/* PCC2 */
+#define IMX7ULP_CLK_DMA1		0
+#define IMX7ULP_CLK_RGPIO2P1		1
+#define IMX7ULP_CLK_FLEXBUS		2
+#define IMX7ULP_CLK_SEMA42_1		3
+#define IMX7ULP_CLK_DMA_MUX1		4
+#define IMX7ULP_CLK_CAAM		6
+#define IMX7ULP_CLK_LPTPM4		7
+#define IMX7ULP_CLK_LPTPM5		8
+#define IMX7ULP_CLK_LPIT1		9
+#define IMX7ULP_CLK_LPSPI2		10
+#define IMX7ULP_CLK_LPSPI3		11
+#define IMX7ULP_CLK_LPI2C4		12
+#define IMX7ULP_CLK_LPI2C5		13
+#define IMX7ULP_CLK_LPUART4		14
+#define IMX7ULP_CLK_LPUART5		15
+#define IMX7ULP_CLK_FLEXIO1		16
+#define IMX7ULP_CLK_USB0		17
+#define IMX7ULP_CLK_USB1		18
+#define IMX7ULP_CLK_USB_PHY		19
+#define IMX7ULP_CLK_USB_PL301		20
+#define IMX7ULP_CLK_USDHC0		21
+#define IMX7ULP_CLK_USDHC1		22
+#define IMX7ULP_CLK_WDG1		23
+#define IMX7ULP_CLK_WDG2		24

-#define IMX7ULP_CLK_SCG1_CLKOUT		82
+#define IMX7ULP_CLK_PCC2_END		25

-#define IMX7ULP_CLK_END			83
+/* PCC3 */
+#define IMX7ULP_CLK_LPTPM6		0
+#define IMX7ULP_CLK_LPTPM7		1
+#define IMX7ULP_CLK_LPI2C6		2
+#define IMX7ULP_CLK_LPI2C7		3
+#define IMX7ULP_CLK_LPUART6		4
+#define IMX7ULP_CLK_LPUART7		5
+#define IMX7ULP_CLK_VIU			6
+#define IMX7ULP_CLK_DSI			7
+#define IMX7ULP_CLK_LCDIF		8
+#define IMX7ULP_CLK_MMDC		9
+#define IMX7ULP_CLK_PCTLC		10
+#define IMX7ULP_CLK_PCTLD		11
+#define IMX7ULP_CLK_PCTLE		12
+#define IMX7ULP_CLK_PCTLF		13
+#define IMX7ULP_CLK_GPU3D		14
+#define IMX7ULP_CLK_GPU2D		15

-/*cm4 clocks*/
-#define IMX7ULP_CM4_CLK_DUMMY		0
-#define IMX7ULP_CM4_CLK_CKIL		1
-#define IMX7ULP_CM4_CLK_OSC		2
-#define IMX7ULP_CM4_CLK_FIRC		3
-#define IMX7ULP_CM4_CLK_SIRC		4
+#define IMX7ULP_CLK_PCC3_END		16

-/* SCG0 */
-#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL	5
-#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV	6
-#define IMX7ULP_CM4_CLK_SPLL		7
-#define IMX7ULP_CM4_CLK_SPLL_VCO	8
-#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1	9
-#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2	10
-#define IMX7ULP_CM4_CLK_SPLL_PFD0	11
-#define IMX7ULP_CM4_CLK_SPLL_PFD1	12
-#define IMX7ULP_CM4_CLK_SPLL_PFD2	13
-#define IMX7ULP_CM4_CLK_SPLL_PFD3	14
-#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL	15
-#define IMX7ULP_CM4_CLK_SPLL_PFD	16
-#define IMX7ULP_CM4_CLK_SPLL_SEL	17
-#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL	18
-#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV	19
-#define IMX7ULP_CM4_CLK_APLL		20
-#define IMX7ULP_CM4_CLK_APLL_VCO	21
-#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1	22
-#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2	23
-#define IMX7ULP_CM4_CLK_APLL_PFD0	24
-#define IMX7ULP_CM4_CLK_APLL_PFD1	25
-#define IMX7ULP_CM4_CLK_APLL_PFD2	26
-#define IMX7ULP_CM4_CLK_APLL_PFD3	27
-#define IMX7ULP_CM4_CLK_APLL_PFD_SEL	28
-#define IMX7ULP_CM4_CLK_APLL_PFD	29
-#define IMX7ULP_CM4_CLK_APLL_SEL	30
-#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV	31
-#define IMX7ULP_CM4_CLK_SYS_SEL		32
-#define IMX7ULP_CM4_CLK_CORE_DIV	33
-#define IMX7ULP_CM4_CLK_BUS_DIV		34
-#define IMX7ULP_CM4_CLK_PLAT_DIV	35
-#define IMX7ULP_CM4_CLK_SLOW_DIV	36
+/* SMC1 */
+#define IMX7ULP_CLK_ARM			0

-#define IMX7ULP_CM4_CLK_SAI0_SEL	37
-#define IMX7ULP_CM4_CLK_SAI0_DIV	38
-#define IMX7ULP_CM4_CLK_SAI0_ROOT	39
-#define IMX7ULP_CM4_CLK_SAI0_IPG	40
-#define IMX7ULP_CM4_CLK_SAI1_SEL	41
-#define IMX7ULP_CM4_CLK_SAI1_DIV	42
-#define IMX7ULP_CM4_CLK_SAI1_ROOT	43
-#define IMX7ULP_CM4_CLK_SAI1_IPG	44
-
-#define IMX7ULP_CLK_SCG0_CLKOUT		45
-
-#define IMX7ULP_CM4_CLK_END		46
+#define IMX7ULP_CLK_SMC1_END		1

 #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */