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arm: mvebu: Move SoC selection (A38X vs AXP) into Kconfig
Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
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@@ -10,8 +10,6 @@
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_ARMADA_38X
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#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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@@ -170,10 +168,6 @@
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#endif
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#endif
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR_A38X
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#define CONFIG_DDR3
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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@@ -10,8 +10,6 @@
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_ARMADA_38X
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#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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@@ -170,10 +168,6 @@
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#endif
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#endif
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR_A38X
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#define CONFIG_DDR3
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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@@ -10,7 +10,6 @@
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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@@ -144,7 +143,6 @@
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR_AXP
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#define CONFIG_SPD_EEPROM 0x4e
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#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
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@@ -10,7 +10,6 @@
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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/*
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@@ -106,7 +105,6 @@
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR_AXP
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#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
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#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
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