configs: Migrate CONFIG_NR_DRAM_BANKS

We have the following cases:
- CONFIG_NR_DRAM_BANKS was defined, migrate normally
- CONFIG_NR_DRAM_BANKS_MAX was defined and then used for
  CONFIG_NR_DRAM_BANKS after a check, just migrate it over now.
- CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 +
  2), set this to 8.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2018-08-16 08:16:24 -04:00
parent 999a772d9f
commit 86cf1c8285
1017 changed files with 746 additions and 334 deletions

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@@ -47,7 +47,6 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0xc8000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \

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@@ -51,7 +51,6 @@
*/
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \

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@@ -91,7 +91,6 @@
* Other required minimal configurations
*/
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */

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@@ -91,7 +91,6 @@
* Other required minimal configurations
*/
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */

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@@ -97,8 +97,6 @@
#define PHYS_SDRAM_1 \
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */

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@@ -194,8 +194,6 @@
#define PHYS_SDRAM_1 \
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */

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@@ -203,7 +203,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -176,7 +176,6 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1

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@@ -12,8 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's

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@@ -16,8 +16,6 @@
#define CONFIG_IODELAY_RECALIBRATION
#define CONFIG_NR_DRAM_BANKS 2
/* MMC ENV related defines */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* eMMC */
#define CONFIG_SYS_MMC_ENV_PART 0

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@@ -250,7 +250,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -48,7 +48,6 @@
* Memory configurations
*/
#define CONFIG_NR_DRAM_POPULATED 1
#define CONFIG_NR_DRAM_BANKS 2
#define ACFG_SDRAM_MBYTE_SYZE 64

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@@ -17,7 +17,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1

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@@ -138,7 +138,6 @@
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -51,7 +51,6 @@
#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
64 * 1024 * 1024)
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)

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@@ -33,8 +33,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
- GENERATED_GBL_DATA_SIZE)
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
/*

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@@ -22,7 +22,6 @@
* TBD: dcache to be used for this
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
#define CONFIG_NR_DRAM_BANKS_MAX 2
/*
* Commands configuration

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@@ -54,7 +54,6 @@
/*
* Memory Configuration
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE SZ_32M

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@@ -53,7 +53,6 @@
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000

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@@ -51,7 +51,6 @@
#define CONFIG_BOOTP_BOOTFILESIZE
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_SP_ADDR \

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@@ -52,7 +52,6 @@
#define CONFIG_BOOTP_BOOTFILESIZE 1
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000

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@@ -43,7 +43,6 @@
#define CONFIG_BOOTP_BOOTFILESIZE
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x70000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000

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@@ -33,7 +33,6 @@
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000

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@@ -41,7 +41,6 @@
#undef CONFIG_FB_ADDR
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000

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@@ -31,7 +31,6 @@
*/
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */

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@@ -45,7 +45,6 @@
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1 \
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */

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@@ -20,7 +20,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */

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@@ -19,7 +19,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_SIZE 0x80000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */

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@@ -12,8 +12,6 @@
#define CONFIG_SYS_NS16550_COM3 0xf040ab00
#define CONFIG_NR_DRAM_BANKS 3
#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000

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@@ -24,8 +24,6 @@
#error CONFIG_SYS_SDRAM_SIZE must be defined!
#endif
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* Some commands use this as the default load address */

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@@ -14,7 +14,6 @@
#define V2M_BASE 0x80000000
#define PHYS_SDRAM_1 V2M_BASE
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G)
#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1

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@@ -6,7 +6,6 @@
#define __CONFIGS_BG0900_H__
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* USB */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* USB */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* USB */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 120000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* USB */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* USB */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* USB */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* USB */

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@@ -10,7 +10,6 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

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@@ -12,7 +12,6 @@
/* SDRAM Definitions */
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_SIZE 0x80000000
/* Generic Timer Definitions */

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@@ -63,7 +63,6 @@
* always, even when we have more. We always start at 0x80000000,
* and we place the initial stack pointer in our SRAM.
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)

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@@ -122,8 +122,6 @@
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
/*
* Serial Driver info
*/

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@@ -202,7 +202,6 @@
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -10,8 +10,6 @@
#ifndef __CONFIG_CL_SOM_AM57X_H
#define __CONFIG_CL_SOM_AM57X_H
#define CONFIG_NR_DRAM_BANKS 2
#define CONSOLEDEV "ttyO2"
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */

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@@ -133,7 +133,6 @@
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -24,7 +24,6 @@
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

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@@ -172,7 +172,6 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
/*-----------------------------------------------------------------------

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@@ -172,7 +172,6 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define CONFIG_SYS_CS0_SIZE (256 << 20)

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@@ -134,7 +134,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -225,7 +225,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -126,7 +126,6 @@
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -84,7 +84,6 @@
/*
* DRAM Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */

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@@ -133,7 +133,6 @@
#define CONFIG_SYS_HZ 1000
/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)

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@@ -55,7 +55,6 @@
#define CONFIG_BOOTP_BOOTFILESIZE
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CONFIG_SYS_SDRAM_SIZE 0x08000000

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@@ -57,8 +57,6 @@
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI1 | \

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@@ -23,7 +23,6 @@
/*
* Memory configurations
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M

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@@ -31,7 +31,6 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <configs/ti_omap3_common.h>

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@@ -146,7 +146,6 @@
#endif
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -378,7 +378,6 @@
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -28,8 +28,6 @@
* Commands configuration
*/
#define CONFIG_NR_DRAM_BANKS 1
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros

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@@ -16,7 +16,6 @@
#define CONFIG_IODELAY_RECALIBRATION
#define CONFIG_VERY_BIG_RAM
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_MAX_MEM_MAPPED 0x80000000
#ifndef CONFIG_QSPI_BOOT

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@@ -14,7 +14,6 @@
#define CONFIG_MISC_INIT_R /* To stop autoboot */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
/* 1008 MB (the last ~30Mb are secured for TrustZone by ATF*/
#define PHYS_SDRAM_1_SIZE 0x3da00000

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@@ -14,7 +14,6 @@
#define CONFIG_MISC_INIT_R /* To stop autoboot */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_SIZE 0xC0000000
#define PHYS_SDRAM_1 0x80000000

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@@ -43,8 +43,6 @@
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
/*
* Serial Driver info
*/

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@@ -137,7 +137,6 @@
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)

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@@ -25,8 +25,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_PHYSMEM
#define CONFIG_NR_DRAM_BANKS 3
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE

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@@ -189,7 +189,6 @@
* Other required minimal configurations
*/
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_MEMTEST_START 0x00400000

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@@ -84,7 +84,6 @@
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -64,7 +64,6 @@
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -24,7 +24,6 @@
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 8
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#endif /* __CONFIG_ESPRESSO7420_H */

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@@ -33,7 +33,6 @@
GENERATED_GBL_DATA_SIZE)
/* 128MB SDRAM in 1 bank */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE

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@@ -29,7 +29,6 @@
#define CONFIG_USB_XHCI_EXYNOS
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 8
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#endif /* __CONFIG_5250_H */

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@@ -91,7 +91,6 @@
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)

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@@ -167,7 +167,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -28,7 +28,6 @@
* TBD: dcache to be used for this
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
#define CONFIG_NR_DRAM_BANKS_MAX 2
/*
* Commands configuration

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@@ -157,7 +157,6 @@
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

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@@ -12,7 +12,6 @@
#define CONFIG_CPU_PXA25X 1
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */

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@@ -53,7 +53,6 @@
* Physical Memory Map
* The DRAM is already setup, so do not touch the DT node later.
*/
#define CONFIG_NR_DRAM_BANKS 0
#define PHYS_SDRAM_1_SIZE (4089 << 20)
#define CONFIG_SYS_MEMTEST_START 0x100000
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000)

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@@ -22,7 +22,6 @@
/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
#define CONFIG_NR_DRAM_BANKS 6
#define PHYS_SDRAM_1 0x00000000
/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/

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@@ -72,7 +72,6 @@
/* memtest start address */
#define CONFIG_SYS_MEMTEST_START 0xA0000000
#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */

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@@ -117,7 +117,6 @@
#endif
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -122,7 +122,6 @@
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

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@@ -83,7 +83,6 @@
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -64,7 +64,6 @@
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1

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@@ -42,8 +42,6 @@
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_UART2 | \

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@@ -39,8 +39,6 @@
* DRAM
*/
#define CONFIG_NR_DRAM_BANKS 1
/*
* Memory
*/

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@@ -125,7 +125,6 @@
* Other required minimal configurations
*/
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
/*

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@@ -88,7 +88,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * SZ_1M)
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE)

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@@ -116,7 +116,6 @@
#endif
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -24,7 +24,6 @@
#define KZM_SDRAM_BASE (0x40000000)
#define PHYS_SDRAM KZM_SDRAM_BASE
#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
#define CONFIG_NR_DRAM_BANKS (1)
/* NOR Flash */
#define KZM_FLASH_BASE (0x00000000)

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@@ -47,7 +47,6 @@
/*
* SDRAM configuration
*/
#define CONFIG_NR_DRAM_BANKS 1
/*
* Different SDRAM configuration and size for some of the boards derived

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@@ -37,8 +37,6 @@
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
/*
* Serial Driver info
*/

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@@ -112,7 +112,6 @@
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM

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@@ -11,7 +11,6 @@
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_CMD_MEMINFO
#define CONFIG_SYS_MEMTEST_START 0x80000000

View File

@@ -11,7 +11,6 @@
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_CMD_MEMINFO

View File

@@ -15,7 +15,6 @@
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define SYS_SDRAM_SIZE_512 0x20000000
#define SYS_SDRAM_SIZE_1024 0x40000000
#define CONFIG_CHIP_SELECTS_PER_CTRL 1

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@@ -11,7 +11,6 @@
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_CMD_MEMINFO
#define CONFIG_SYS_MEMTEST_START 0x80000000

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