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Merge git://git.denx.de/u-boot-x86

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- Allow x86 boards to use TPL, SPL and U-Boot proper
- Update sysreset x86 driver to utilize ACPI registers to do power off
- Add a new chromebook_samus_tpl board for TPL support
- Several minor changes in binman tool
This commit is contained in:
Tom Rini
2019-05-08 09:20:19 -04:00
parent d4c352138c ffe403762b
commit 8c66fb88e3
64 changed files with 2076 additions and 995 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
include/configs/chromebook_link.h
View File

@@ -18,9 +18,6 @@
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x003f8000
#define BOOT_DEVICE_SPI 10
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#define BOOT_DEVICE_BOARD 11
#endif /* __CONFIG_H */

2
include/configs/chromebook_samus.h
View File

@@ -23,4 +23,6 @@
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x003f8000
#define CONFIG_TPL_TEXT_BASE 0xfffd8000
#endif /* __CONFIG_H */

5
include/configs/qemu-x86.h
View File

@@ -33,11 +33,6 @@
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
#define CONFIG_ATAPI
/* SPI is not supported */
#define BOOT_DEVICE_SPI 10
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#define BOOT_DEVICE_BOARD 11
#endif /* __CONFIG_H */

1
include/configs/x86-common.h
View File

@@ -36,7 +36,6 @@
/*-----------------------------------------------------------------------
* Real Time Clock Configuration
*/
#define CONFIG_RTC_MC146818
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS

18
include/pch.h
View File

@@ -16,6 +16,9 @@ enum pch_req_t {
/* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
PCH_REQ_HDA_CONFIG,
/* Fills out a struct pch_pmbase_info if available */
PCH_REQ_PMBASE_INFO,
PCH_REQ_TEST1, /* Test requests for sandbox driver */
PCH_REQ_TEST2,
PCH_REQ_TEST3,
@@ -23,6 +26,21 @@ enum pch_req_t {
PCH_REQ_COUNT, /* Number of ioctrls supported */
};
/**
* struct pch_pmbase_info - Information filled in by PCH_REQ_PMBASE_INFO
*
* @pmbase: IO address of power-management controller
* @gpio0_en_ofs: Offset of GPIO0 enable register
* @pm1_sts_ofs: Offset of status register
* @pm1_cnt_ofs: Offset of control register
*/
struct pch_pmbase_info {
u16 base;
u8 gpio0_en_ofs;
u8 pm1_sts_ofs;
u8 pm1_cnt_ofs;
};
/**
* struct pch_ops - Operations for the Platform Controller Hub
*

6
include/pci.h
View File

@@ -546,11 +546,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
#ifdef CONFIG_NR_DRAM_BANKS
#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
#else
#define MAX_PCI_REGIONS 7
#endif
#define MAX_PCI_REGIONS 7
#define INDIRECT_TYPE_NO_PCIE_LINK 1