diff --git a/Kconfig b/Kconfig index ce25ea24a60..7f00e76ba78 100644 --- a/Kconfig +++ b/Kconfig @@ -474,6 +474,23 @@ config SKIP_RELOCATE Skips relocation of U-Boot allowing for systems that have extremely limited RAM to run U-Boot. +config SKIP_RELOCATE_CODE + bool + help + Skips relocation of U-Boot code to the end of RAM, but still does + relocate data to the end of RAM. This is mainly meant to relocate + data to read-write portion of the RAM, while the code remains in + read-only portion of the RAM from which it is allowed to execute. + This split configuration is present on various secure cores. + +config SKIP_RELOCATE_CODE_DATA_OFFSET + hex + default 0x0 + depends on SKIP_RELOCATE_CODE + help + Offset of the read-write memory which contains data, from read-only + memory which contains executable text. + endif # EXPERT config PHYS_64BIT @@ -524,8 +541,8 @@ config BUILD_TARGET default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL default "u-boot-with-spl.imx" if ARCH_MX6 && SPL default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL - default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 - default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 + default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_ARRIA10 + default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_GEN5 default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ RISCV || ARCH_ZYNQMP) default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL @@ -615,9 +632,11 @@ config STACK_SIZE default 0x4000 if ARCH_STM32 default 0x1000000 help - Define Max stack size that can be used by U-Boot. This value is used - by the UEFI sub-system. On some boards initrd_high is calculated as - base stack pointer minus this stack size. + Define Max stack size that can be used by U-Boot. The UEFI sub-system + considers this value when setting up the memory map. The UEFI + specification requires 128 KiB or more of available stack space. On + some boards initrd_high is calculated as base stack pointer minus this + stack size. config SYS_MEM_TOP_HIDE hex "Exclude some memory from U-Boot / OS information" @@ -785,14 +804,14 @@ config NO_NET config NET bool "Legacy U-Boot networking stack" - imply NETDEVICES + select NETDEVICES help Include networking support with U-Boot's internal implementation of the TCP/IP protocol stack. config NET_LWIP bool "Use lwIP for networking stack" - imply NETDEVICES + select NETDEVICES help Include networking support based on the lwIP (lightweight IP) TCP/IP stack (https://nongnu.org/lwip). This is a replacement for diff --git a/MAINTAINERS b/MAINTAINERS index d4b527560aa..6c596971ae4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -323,6 +323,7 @@ F: doc/imx/ F: drivers/mailbox/imx-mailbox.c F: drivers/remoteproc/imx* F: drivers/serial/serial_mxc.c +F: drivers/spi/nxp_xspi.c F: include/imx_container.h ARM HISILICON @@ -414,7 +415,10 @@ M: Ryder Lee M: Weijie Gao M: Chunfeng Yun M: Igor Belwon +M: David Lechner +M: Julien Stephan R: GSS_MTK_Uboot_upstream +T: git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git S: Maintained F: arch/arm/dts/mt* F: arch/arm/mach-mediatek/ @@ -432,6 +436,8 @@ F: drivers/net/phy/mediatek/ F: drivers/phy/phy-mtk-* F: drivers/pinctrl/mediatek/ F: drivers/power/domain/mtk-power-domain.c +F: drivers/power/pmic/mtk-pwrap.c +F: drivers/power/regulator/mt*.c F: drivers/pci/pcie_mediatek_gen3.c F: drivers/pci/pcie_mediatek.c F: drivers/pwm/pwm-mtk.c @@ -448,6 +454,7 @@ F: drivers/reset/reset-mediatek.c F: drivers/serial/serial_mtk.c F: include/dt-bindings/clock/mediatek,* F: include/dt-bindings/power/mediatek,* +F: include/power/mt*.h F: tools/mtk_image.c F: tools/mtk_image.h F: tools/mtk_nand_headers.c @@ -1237,11 +1244,16 @@ F: drivers/watchdog/sbsa_gwdt.c FWU Multi Bank Update M: Sughosh Ganu +M: Kory Maincent S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git +F: doc/fwumdata.1 +F: doc/mkfwumdata.1 F: lib/fwu_updates/* F: drivers/fwu-mdata/* -F: tools/mkfwumdata.c +F: tools/fwumdata_src/fwumdata.c +F: tools/fwumdata_src/fwumdata.h +F: tools/fwumdata_src/mkfwumdata.c GATEWORKS_SC M: Tim Harvey @@ -1381,7 +1393,10 @@ F: drivers/net/phy/ca_phy.c MIPS MEDIATEK M: Weijie Gao +M: David Lechner +M: Julien Stephan R: GSS_MTK_Uboot_upstream +T: git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git S: Maintained F: arch/mips/mach-mtmips/ F: arch/mips/dts/mt7620.dtsi @@ -1767,13 +1782,15 @@ F: drivers/spmi/ F: include/spmi/ SQUASHFS -M: Joao Marcos Costa +M: Joao Marcos Costa +M: Richard Genoud R: Thomas Petazzoni R: Miquel Raynal S: Maintained +F: cmd/sqfs.c +F: common/spl/spl_squashfs.c F: fs/squashfs/ F: include/sqfs.h -F: cmd/sqfs.c F: test/py/tests/test_fs/test_squashfs/ STACKPROTECTOR @@ -1841,10 +1858,14 @@ F: drivers/tpm/ F: include/tpm* F: lib/tpm* -TQ GROUP -#M: Martin Krause -S: Orphaned (Since 2016-02) -T: git git://git.denx.de/u-boot-tq-group.git +TQ-SYSTEMS +L: u-boot@ew.tq-group.com +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: board/tq/* +F: doc/board/tq/* +F: include/configs/tq*.h +F: include/env/tq/* TEE M: Jens Wiklander @@ -1886,6 +1907,7 @@ M: Neil Armstrong M: Bhupesh Sharma M: Neha Malcom Francis S: Maintained +F: common/spl/spl_ufs.c F: drivers/ufs/ UPL diff --git a/Makefile b/Makefile index 4c86f5ac409..8af18668b0f 100644 --- a/Makefile +++ b/Makefile @@ -1231,6 +1231,7 @@ ifneq ($(CONFIG_SPL_TARGET),) INPUTS-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif INPUTS-$(CONFIG_REMAKE_ELF) += u-boot.elf +INPUTS-$(CONFIG_SPL_REMAKE_ELF) += spl/u-boot-spl.elf INPUTS-$(CONFIG_EFI_APP) += u-boot-app.efi INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi @@ -1422,7 +1423,6 @@ endif PHONY += dtbs dtbs_check dtbs: dts/dt.dtb - @: dts/dt.dtb: dtbs_prepare u-boot $(Q)$(MAKE) $(build)=dts dtbs @@ -2001,6 +2001,15 @@ u-boot.elf: u-boot.bin u-boot-elf.lds FORCE $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o $(call if_changed,u-boot-elf) +quiet_cmd_u-boot-spl-elf ?= LD $@ + cmd_u-boot-spl-elf ?= $(LD) spl/u-boot-spl-elf.o -o $@ \ + $(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \ + -T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SPL_TEXT_BASE) \ + -Ttext=$(CONFIG_SPL_TEXT_BASE) +spl/u-boot-spl.elf: spl/u-boot-spl.bin u-boot-elf.lds + $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< spl/u-boot-spl-elf.o + $(call if_changed,u-boot-spl-elf) + u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE $(call if_changed_dep,cpp_lds) @@ -2138,6 +2147,7 @@ quiet_cmd_gen_envp = ENVP $@ -D__ASSEMBLY__ \ -D__UBOOT_CONFIG__ \ -DDEFAULT_DEVICE_TREE=$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE)) \ + -DDEFAULT_FDT_FILE=$(subst ",,$(CONFIG_DEFAULT_FDT_FILE)) \ -I . -I include -I $(srctree)/include \ -include linux/kconfig.h -include include/config.h \ -I$(srctree)/arch/$(ARCH)/include \ @@ -2737,21 +2747,19 @@ help: @echo 'Execute "make" or "make all" to build all targets marked with [*] ' @echo 'For further info see the ./README file' -ifneq ($(filter tests pcheck qcheck tcheck,$(MAKECMDGOALS)),) -export sub_make_done := 0 -endif +run_tests = $(Q)env -u sub_make_done $(srctree)/test/run tests check: - $(srctree)/test/run + $(run_tests) pcheck: - $(srctree)/test/run parallel + $(run_tests) parallel qcheck: - $(srctree)/test/run quick + $(run_tests) quick tcheck: - $(srctree)/test/run tools + $(run_tests) tools # Documentation targets # --------------------------------------------------------------------------- diff --git a/README b/README index e2d49e2ebd3..6836a917c79 100644 --- a/README +++ b/README @@ -597,32 +597,6 @@ The following options need to be configured: A byte containing the id of the VLAN. -- Status LED: CONFIG_LED_STATUS - - Several configurations allow to display the current - status using a LED. For instance, the LED will blink - fast while running U-Boot code, stop blinking as - soon as a reply to a BOOTP request was received, and - start blinking slow once the Linux kernel is running - (supported by a status LED driver in the Linux - kernel). Defining CONFIG_LED_STATUS enables this - feature in U-Boot. - - Additional options: - - CONFIG_LED_STATUS_GPIO - The status LED can be connected to a GPIO pin. - In such cases, the gpio_led driver can be used as a - status LED backend implementation. Define CONFIG_LED_STATUS_GPIO - to include the gpio_led driver in the U-Boot binary. - - CFG_GPIO_LED_INVERTED_TABLE - Some GPIO connected LEDs may have inverted polarity in which - case the GPIO high value corresponds to LED off state and - GPIO low value corresponds to LED on state. - In such cases CFG_GPIO_LED_INVERTED_TABLE may be defined - with a list of GPIO LEDs that have inverted polarity. - - I2C Support: CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. diff --git a/arch/Kconfig b/arch/Kconfig index 4af0da2485f..4c4c070df87 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -190,6 +190,7 @@ config SANDBOX select HAVE_SETJMP select HAVE_INITJMP select ARCH_SUPPORTS_LTO + select AXI select BOARD_LATE_INIT select BZIP2 select CMD_POWEROFF if CMDLINE @@ -199,24 +200,37 @@ config SANDBOX select DM_GPIO select DM_I2C select DM_KEYBOARD + select DM_MAILBOX + select DM_RESET select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO select GZIP_COMPRESSED + select I2C select LZO select MMC select MTD select OF_BOARD_SETUP + select OF_CONTROL select PCI_ENDPOINT + select SANDBOX_RESET select SPI + select SERIAL select SUPPORT_OF_CONTROL select SUPPORT_BIG_ENDIAN select SUPPORT_LITTLE_ENDIAN - select SYSRESET_CMD_POWEROFF if CMD_POWEROFF + select SYSRESET + select SYSRESET_CMD_RESET + select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF select SYS_CACHE_SHIFT_4 select IRQ select SUPPORT_EXTENSION_SCAN if CMDLINE select SUPPORT_ACPI + select TIMER + select SPL_TIMER if SPL + select TPL_TIMER if TPL + select VPL_TIMER if VPL imply BITREVERSE select BLOBLIST imply LTO @@ -240,7 +254,7 @@ config SANDBOX imply AVB_VERIFY imply LIBAVB imply CMD_AVB - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply SCP03 imply CMD_SCP03 imply UDP_FUNCTION_FASTBOOT @@ -250,7 +264,7 @@ config SANDBOX # Re-enable this when fully implemented # imply VIRTIO_BLK imply VIRTIO_NET - imply DM_SOUND + imply SOUND imply PCI_SANDBOX_EP imply PCH imply PHYLIB @@ -266,7 +280,6 @@ config SANDBOX imply PHY_FIXED imply DM_DSA imply CMD_EXTENSION - imply KEYBOARD imply PHYSMEM imply GENERATE_ACPI_TABLE imply BINMAN @@ -284,6 +297,7 @@ config SH config X86 bool "x86 architecture" + select AHCI select HAVE_SETJMP select SUPPORT_SPL select SUPPORT_TPL diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index b143392ee6c..91165a06a46 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int cleanup_before_linux(void) { @@ -53,17 +50,13 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) { ulong kernel_entry; unsigned int r0, r2; - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - kernel_entry = images->ep; debug("## Transferring control to Linux (at address %08lx)...\n", kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + bootm_final(flag); if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { r0 = 2; @@ -75,7 +68,7 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) cleanup_before_linux(); - if (!fake) + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) board_jump_and_run(kernel_entry, r0, 0, r2); } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cd6a454fd60..03416c55265 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -30,7 +30,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M + default 200000000 if ARCH_SOCFPGA_AGILEX5 || ARCH_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -834,6 +834,9 @@ config ARCH_K3 imply DM_RNG if ARM64 imply TEE if ARM64 imply OPTEE if ARM64 + imply TPM if ARM64 && MMC + imply TPM2_FTPM_TEE if ARM64 && MMC + imply SUPPORT_EMMC_RPMB if ARM64 && MMC config ARCH_OMAP2PLUS bool "TI OMAP2+" @@ -1145,35 +1148,35 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R - select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_SOC64 - select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select ARCH_MISC_INIT if !ARCH_SOCFPGA_ARRIA10 + select ARM64 if ARCH_SOCFPGA_SOC64 + select CPU_V7A if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 select DM select DM_SERIAL select GPIO_EXTRA_HEADER - select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64 + select ENABLE_ARM_SOC_BOOT0_HOOK if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 + select LMB_ARCH_MEM_MAP if ARCH_SOCFPGA_SOC64 select OF_CONTROL select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 - select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 - select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64 + select SPL_SEPARATE_BSS if ARCH_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if ARCH_SOCFPGA_SOC64 + select SPL_SOCFPGA_DT_REG if ARCH_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG select SUPPORT_SPL select SYS_NS16550 - select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYS_THUMB_BUILD if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 select SYSRESET - select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ - TARGET_SOCFPGA_SOC64 - select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 - select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 + select SYSRESET_SOCFPGA_SOC64 if !ARCH_SOCFPGA_AGILEX5 && \ + ARCH_SOCFPGA_SOC64 + select SYSRESET_PSCI if ARCH_SOCFPGA_AGILEX5 + select USE_BOOTFILE if SPL_ATF && ARCH_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY @@ -2154,7 +2157,6 @@ config TARGET_POMELO select SCSI_AHCI select AHCI_PCI select PCI - select DM_PCI select SCSI select DM_SERIAL imply CMD_PCI diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 27ffb450378..2c550439559 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -15,8 +14,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #ifndef CONFIG_ARCH_CPU_INIT #error must be define the macro "CONFIG_ARCH_CPU_INIT" #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 82ad3035308..d90e02ca4e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,17 +58,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3128) += \ dtb-$(CONFIG_ROCKCHIP_RK322X) += \ rk3229-evb.dtb -dtb-$(CONFIG_ROCKCHIP_RK3288) += \ - rk3288-evb.dtb \ - rk3288-popmetal.dtb \ - rk3288-rock2-square.dtb \ - rk3288-rock-pi-n8.dtb \ - rk3288-veyron-jerry.dtb \ - rk3288-veyron-mickey.dtb \ - rk3288-veyron-minnie.dtb \ - rk3288-veyron-speedy.dtb \ - rk3288-vyasa.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ @@ -469,6 +458,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_cyclone5_ac501soc.dtb \ + socfpga_cyclone5_ac550soc.dtb \ socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi index c5e24c76457..4548076b96a 100644 --- a/arch/arm/dts/an7581-u-boot.dtsi +++ b/arch/arm/dts/an7581-u-boot.dtsi @@ -35,6 +35,48 @@ reg = <0x0 0x1fa20000 0x0 0x388>; }; + pon_pcs: pcs@1fa08000 { + compatible = "airoha,an7581-pcs-pon"; + reg = <0x0 0x1fa08000 0x0 0x1000>, + <0x0 0x1fa80000 0x0 0x60>, + <0x0 0x1fa80a00 0x0 0x164>, + <0x0 0x1fa84000 0x0 0x450>, + <0x0 0x1fa85900 0x0 0x338>, + <0x0 0x1fa86000 0x0 0x300>, + <0x0 0x1fa8a000 0x0 0x1000>, + <0x0 0x1fa8b000 0x0 0x1000>; + reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "xfi_ana", "xfi_pma"; + + resets = <&scuclk EN7581_XPON_MAC_RST>, + <&scuclk EN7581_XPON_PHY_RST>; + reset-names = "mac", "phy"; + + airoha,scu = <&scuclk>; + }; + + eth_pcs: pcs@1fa09000 { + compatible = "airoha,an7581-pcs-eth"; + reg = <0x0 0x1fa09000 0x0 0x1000>, + <0x0 0x1fa70000 0x0 0x60>, + <0x0 0x1fa70a00 0x0 0x164>, + <0x0 0x1fa74000 0x0 0x450>, + <0x0 0x1fa75900 0x0 0x338>, + <0x0 0x1fa76000 0x0 0x300>, + <0x0 0x1fa7a000 0x0 0x1000>, + <0x0 0x1fa7b000 0x0 0x1000>; + reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs", + "multi_sgmii", "usxgmii", + "hsgmii_rate_adp", "xfi_ana", "xfi_pma"; + + resets = <&scuclk EN7581_XSI_MAC_RST>, + <&scuclk EN7581_XSI_PHY_RST>; + reset-names = "mac", "phy"; + + airoha,scu = <&scuclk>; + }; + eth: ethernet@1fb50000 { compatible = "airoha,en7581-eth"; reg = <0 0x1fb50000 0 0x2600>, @@ -52,6 +94,35 @@ reset-names = "fe", "pdma", "qdma", "hsi0-mac", "hsi1-mac", "hsi-mac", "xfp-mac"; + + gdm1: ethernet@1 { + compatible = "airoha,eth-mac"; + reg = <1>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gdm2: ethernet@2 { + compatible = "airoha,eth-mac"; + reg = <2>; + pcs = <&pon_pcs>; + + status = "disabled"; + }; + + gdm4: ethernet@4 { + compatible = "airoha,eth-mac"; + reg = <4>; + pcs = <ð_pcs>; + + status = "disabled"; + }; }; switch: switch@1fb58000 { diff --git a/arch/arm/dts/cros-ec-sbs.dtsi b/arch/arm/dts/cros-ec-sbs.dtsi deleted file mode 100644 index 71f5c5ecce4..00000000000 --- a/arch/arm/dts/cros-ec-sbs.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Smart battery dts fragment for devices that use cros-ec-sbs - * - * Copyright (c) 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -&i2c_tunnel { - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; -}; diff --git a/arch/arm/dts/en7523-evb-u-boot.dtsi b/arch/arm/dts/en7523-evb-u-boot.dtsi index c109d6794fb..d6ab621d590 100644 --- a/arch/arm/dts/en7523-evb-u-boot.dtsi +++ b/arch/arm/dts/en7523-evb-u-boot.dtsi @@ -9,3 +9,7 @@ }; #include "en7523-u-boot.dtsi" + +&gdm1 { + status = "okay"; +}; diff --git a/arch/arm/dts/en7523-u-boot.dtsi b/arch/arm/dts/en7523-u-boot.dtsi index 9eadaccc500..62d1a724678 100644 --- a/arch/arm/dts/en7523-u-boot.dtsi +++ b/arch/arm/dts/en7523-u-boot.dtsi @@ -37,6 +37,19 @@ <&scu EN7523_HSI_MAC_RST>; reset-names = "fe", "pdma", "qdma", "hsi0-mac", "hsi1-mac", "hsi-mac"; + + gdm1: ethernet@1 { + compatible = "airoha,eth-mac"; + reg = <1>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; }; switch: switch@1fb58000 { diff --git a/arch/arm/dts/en7581-evb-u-boot.dtsi b/arch/arm/dts/en7581-evb-u-boot.dtsi index ebd3b8b4958..9a02122fbfa 100644 --- a/arch/arm/dts/en7581-evb-u-boot.dtsi +++ b/arch/arm/dts/en7581-evb-u-boot.dtsi @@ -9,3 +9,21 @@ }; #include "an7581-u-boot.dtsi" + +&gdm1 { + status = "okay"; +}; + +&gdm2 { + status = "okay"; + + managed = "in-band-status"; + phy-mode = "10gbase-r"; +}; + +&gdm4 { + status = "okay"; + + managed = "in-band-status"; + phy-mode = "usxgmii"; +}; diff --git a/arch/arm/dts/imx23-olinuxino-u-boot.dtsi b/arch/arm/dts/imx23-olinuxino-u-boot.dtsi index dee8433696f..3f2f117b953 100644 --- a/arch/arm/dts/imx23-olinuxino-u-boot.dtsi +++ b/arch/arm/dts/imx23-olinuxino-u-boot.dtsi @@ -1,5 +1,20 @@ // SPDX-License-Identifier: GPL-2.0+ +/ { + leds { + user_led: user { + default-state = "on"; + }; + }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&user_led>; + }; + }; +}; + &ssp0 { non-removable; }; diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts index 2f8597579f3..b40410b2b6f 100644 --- a/arch/arm/dts/imx8-capricorn-cxg3.dts +++ b/arch/arm/dts/imx8-capricorn-cxg3.dts @@ -102,6 +102,26 @@ pinctrl-0 = <&pinctrl_gpio_keys>; muxcgrp: imx8qxp-som { + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 + + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + >; + }; + pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 @@ -127,3 +147,27 @@ >; }; }; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rmii"; + + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/dts/imx8-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi index 3734a9d21f1..f640daa775f 100644 --- a/arch/arm/dts/imx8-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -63,41 +63,6 @@ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 - SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 - SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 - SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 - SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 - SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 - SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 - SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021 - //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021 - >; - }; - - pinctrl_fec2: fec2grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - - SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 - SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 - - SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */ >; }; }; @@ -126,6 +91,7 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; + max-frequency = <52000000>; clock-frequency=<52000000>; no-1-8-v; bus-width = <8>; @@ -160,27 +126,3 @@ &fec1 { status ="disabled"; }; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec2>; - phy-mode = "rmii"; - - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi index cf2a87a9b90..13e1070c28e 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi @@ -22,6 +22,18 @@ bootph-pre-ram; }; +&pca9450 { + bootph-all; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + &pinctrl_uart2 { bootph-pre-ram; }; @@ -63,7 +75,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &i2c2 { @@ -118,3 +130,7 @@ phy-reset-duration = <15>; phy-reset-post-delay = <100>; }; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi index 1320f1540ed..f917b71be90 100644 --- a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -33,6 +33,18 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { bootph-pre-ram; }; @@ -78,11 +90,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pmic { - bootph-pre-ram; + bootph-all; }; /* USB1 Type-C */ @@ -120,6 +132,12 @@ &usdhc2 { bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 4804a204e92..e9403d9ea82 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -34,6 +34,18 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { bootph-pre-ram; }; @@ -83,11 +95,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pmic { - bootph-pre-ram; + bootph-all; }; &usb_dwc3_0 { @@ -96,6 +108,12 @@ &usdhc2 { bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 7b45a87450b..3b0af5bc0a0 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -70,7 +70,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; eeprom_module: eeprom@50 { compatible = "i2c-eeprom"; @@ -104,7 +104,7 @@ }; &pca9450 { - bootph-pre-ram; + bootph-all; }; &pinctrl_ctrl_sleep_moci { @@ -112,7 +112,11 @@ }; &pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; }; &pinctrl_usdhc2_pwr_en { @@ -159,6 +163,12 @@ sd-uhs-ddr50; sd-uhs-sdr104; bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { @@ -173,3 +183,7 @@ &wdog1 { bootph-pre-ram; }; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; diff --git a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi new file mode 100644 index 00000000000..64ed7af9946 --- /dev/null +++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + * + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc0", "mmc1", "ethernet"; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_cd { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_default { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + }; + }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&wdog3 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi new file mode 100644 index 00000000000..5d788854de5 --- /dev/null +++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + * + */ + +#include "imx91-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" + +/ { + /* + * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as + * reference, but does only make use of its SoM (phyCORE) contained + * periphery. + */ + model = "PHYTEC phyCORE-i.MX91"; +}; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 646b617949d..b80ce20e942 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -9,6 +9,7 @@ */ #include "imx93-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" / { /* @@ -17,224 +18,4 @@ * periphery. */ model = "PHYTEC phyCORE-i.MX93"; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog3>; - bootph-pre-ram; - bootph-some-ram; - }; - - aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - }; - - bootstd { - bootph-verify; - compatible = "u-boot,boot-std"; - - filename-prefixes = "/", "/boot/"; - bootdev-order = "mmc0", "mmc1", "ethernet"; - - rauc { - compatible = "u-boot,distro-rauc"; - }; - - script { - compatible = "u-boot,script"; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -&{/soc@0} { - bootph-all; - bootph-pre-ram; -}; - -&aips1 { - bootph-pre-ram; - bootph-all; -}; - -&aips2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&aips3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&iomuxc { - bootph-pre-ram; - bootph-some-ram; -}; - -®_usdhc2_vmmc { - u-boot,off-on-delay-us = <20000>; - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_lpi2c3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_pmic { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_reg_usdhc2_vmmc { - bootph-pre-ram; -}; - -&pinctrl_uart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_cd { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_default { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio4 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpuart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc2 { - bootph-pre-ram; - bootph-some-ram; - fsl,signal-voltage-switch-extra-delay-ms = <8>; -}; - -&lpi2c1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c3 { - bootph-pre-ram; - bootph-some-ram; - - pmic@25 { - bootph-pre-ram; - bootph-some-ram; - - regulators { - bootph-pre-ram; - bootph-some-ram; - }; - }; - - eeprom@50 { - bootph-pre-ram; - bootph-some-ram; - }; -}; - -&s4muap { - bootph-pre-ram; - bootph-some-ram; - status = "okay"; -}; - -&clk { - bootph-all; - bootph-pre-ram; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; - /delete-property/ assigned-clock-parents; -}; - -&osc_32k { - bootph-all; - bootph-pre-ram; -}; - -&osc_24m { - bootph-all; - bootph-pre-ram; -}; - -&clk_ext1 { - bootph-all; - bootph-pre-ram; -}; - -&wdog3 { - bootph-all; - bootph-pre-ram; }; diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi index 528b3b02a3f..247a7ed6838 100644 --- a/arch/arm/dts/imx943-evk-u-boot.dtsi +++ b/arch/arm/dts/imx943-evk-u-boot.dtsi @@ -157,6 +157,24 @@ status = "disabled"; }; +&xspi1 { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1>; + status = "okay"; + + mt35xu512aba: flash@0 { + bootph-pre-ram; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &scmi_iomuxc { pinctrl_emdio: emdiogrp { fsl,pins = < @@ -205,6 +223,22 @@ IMX94_PAD_GPIO_IO17__LPI2C3_SCL 0x40000b9e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe + IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x3fe + IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x3fe + IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x3fe + IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x3fe + IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x3fe + IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x3fe + IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x3fe + IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x3fe + IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x3fe + IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe + >; + }; }; &pinctrl_reg_usdhc2_vmmc { diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi index 2b93ba9a38b..3457442a3b0 100644 --- a/arch/arm/dts/imx943-u-boot.dtsi +++ b/arch/arm/dts/imx943-u-boot.dtsi @@ -141,6 +141,22 @@ &aips3 { bootph-all; + + xspi1: spi@42b90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx94-xspi"; + reg = <0x42b90000 0x50000>, <0x28000000 0x08000000>; + reg-names = "xspi_base", "xspi_mmap"; + interrupts = , // EENV0 + , // EENV1 + , // EENV2 + , // EENV3 + ; // EENV4 + clocks = <&scmi_clk IMX94_CLK_XSPI1>; + clock-names = "xspi"; + status = "disabled"; + }; }; &clk_ext1 { diff --git a/arch/arm/dts/imx952-evk-u-boot.dtsi b/arch/arm/dts/imx952-evk-u-boot.dtsi new file mode 100644 index 00000000000..b872c3a7273 --- /dev/null +++ b/arch/arm/dts/imx952-evk-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "imx952-u-boot.dtsi" + +&wdog3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi new file mode 100644 index 00000000000..e977014992e --- /dev/null +++ b/arch/arm/dts/imx952-u-boot.dtsi @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +/ { + binman { + multiple-images; + + m33-oei-ddrfw { + pad-byte = <0x00>; + align-size = <0x8>; + filename = "m33-oei-ddrfw.bin"; + + oei-m33-ddr { + align-size = <0x4>; + filename = "oei-m33-ddr.bin"; + type = "blob-ext"; + }; + + imx-lpddr { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem { + filename = "lpddr4x_imem_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem { + filename = "lpddr4x_dmem_v202409.bin"; + type = "blob-ext"; + }; + }; + + imx-lpddr-qb { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem-qb { + filename = "lpddr4x_imem_qb_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem-qb { + filename = "lpddr4x_dmem_qb_v202409.bin"; + type = "blob-ext"; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + type = "nxp-imx9image"; + cfg-path = "spl/u-boot-spl.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + append = "mx952a0-ahab-container.img"; + container; + dummy-ddr; + image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000"; + hold = <0x10000>; + image1 = "m33", "m33_image.bin", "0x1ffc0000"; + image2 = "a55", "spl/u-boot-spl.bin", "0x20480000"; + dummy-v2x = <0x8b000000>; + }; + + u-boot { + type = "nxp-imx9image"; + cfg-path = "u-boot-container.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + container; + image0 = "a55", "bl31.bin", "0x8a200000"; + image1 = "a55", "u-boot.bin", "0x90200000"; + }; + }; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + }; +}; + +&A55_0 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_1 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_2 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_3 { + clocks = <&scmi_clk IMX952_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&aips1 { + bootph-all; +}; + +&aips2 { + bootph-all; +}; + +&aips3 { + bootph-all; +}; + +&clk_ext1 { + bootph-all; +}; + +&clk_dummy { + bootph-all; +}; + +&clk_osc_24m { + bootph-all; +}; + +&elemu1 { + status = "okay"; + bootph-all; +}; + +&elemu3 { + status = "okay"; + bootph-all; +}; + +&{/firmware} { + bootph-all; +}; + +&{/firmware/scmi} { + bootph-all; +}; + +&{/firmware/scmi/protocol@11} { + bootph-all; +}; + +&{/firmware/scmi/protocol@13} { + bootph-all; +}; + +&{/firmware/scmi/protocol@14} { + bootph-all; +}; + +&{/firmware/scmi/protocol@15} { + bootph-all; +}; + +&{/firmware/scmi/protocol@19} { + bootph-all; +}; + +&gpio1 { + reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; +}; + +&gpio2 { + reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>; + bootph-pre-ram; + /* + * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2 + * is assigned to M7, disable gpio2 here + */ + status = "disabled"; +}; + +&gpio3 { + reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>; + bootph-pre-ram; +}; + +&gpio4 { + reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>; + bootph-pre-ram; +}; + +&gpio5 { + reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>; + bootph-pre-ram; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&mu2 { + bootph-all; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&scmi_buf0 { + reg = <0x0 0x400>; + bootph-all; +}; + +&scmi_buf1 { + bootph-all; +}; + +&{/soc} { + bootph-all; +}; + +&sram0 { + bootph-all; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&scmi_iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + bootph-pre-ram; + + fsl,pins = < + IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x3fe + IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e + IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x3fe + IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x3fe + >; + }; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts index 46b621242b5..ac6f1022a55 100644 --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts @@ -21,11 +21,6 @@ }; }; -&a53_0 { - clock-names = "gtc"; - clocks = <&k3_clks 61 0>; -}; - &main_pktdma { ti,sci = <&dm_tifs>; }; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 8d6015e44a9..ba29a047406 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -7,6 +7,10 @@ #ifdef CONFIG_TARGET_AM625_R5_EVM +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62x-hs-evm.bin { filename = "tiboot3-am62x-hs-evm.bin"; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index dfd960aaf3c..971bb752052 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -24,7 +24,6 @@ }; &a53_0 { - clocks = <&k3_clks 61 0>; /* * FIXME: Currently only the SPL running on the R5 has a clock * driver. As a workaround therefore move the assigned-clock diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts index b54cd9d48a4..c949485017e 100644 --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -22,11 +22,6 @@ }; }; -&a53_0 { - clocks = <&k3_clks 61 0>; - clock-names = "gtc"; -}; - &cbass_main { bootph-pre-ram; sa3_secproxy: secproxy@44880000 { diff --git a/arch/arm/dts/k3-am62d2-r5.dtsi b/arch/arm/dts/k3-am62d2-r5.dtsi index 23dfc49c2ea..4a58711bfbc 100644 --- a/arch/arm/dts/k3-am62d2-r5.dtsi +++ b/arch/arm/dts/k3-am62d2-r5.dtsi @@ -73,3 +73,21 @@ clock-frequency = <25000000>; bootph-pre-ram; }; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; + +&main_bcdma { + ti,sci = <&dm_tifs>; +}; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 603487341d2..cca56b76d69 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -7,6 +7,10 @@ #if IS_ENABLED(CONFIG_TARGET_AM62P5_R5_EVM) +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62px-hs-fs-evm.bin { filename = "tiboot3-am62px-hs-fs-evm.bin"; diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts index 4b7a63db4ce..6f3a2628353 100644 --- a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts @@ -21,8 +21,3 @@ ethernet0 = &cpsw3g; }; }; - -&a53_0 { - clock-names = "gtc"; - clocks = <&k3_clks 61 0>; -}; diff --git a/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts b/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts index a2674a3e1f8..c641a2b59d6 100644 --- a/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts +++ b/arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts @@ -14,6 +14,15 @@ #include "k3-am68-phyboard-izar-u-boot.dtsi" #include "k3-j721s2-r5.dtsi" +&pmic { + bootph-pre-ram; + + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; +}; + &wkup_vtm0 { bootph-pre-ram; vdd-supply-2 = <&vdd_cpu_avs>; diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index 0fd93f9536a..ad127663d03 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -477,7 +477,7 @@ FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD)>; start_address = <0x0 CONFIG_K3_ATF_LOAD_ADDR>; - end_address = <0x0 (CONFIG_K3_ATF_LOAD_ADDR + 0x1ffff)>; + end_address = <0x0 (CONFIG_K3_ATF_LOAD_ADDR + CONFIG_K3_ATF_RESERVED_SIZE - 1)>; }; firewall_armv8_optee_fg: template-8 { control = <(FWCTRL_EN | FWCTRL_LOCK | @@ -486,7 +486,7 @@ FWPERM_SECURE_PRIV_RWCD | FWPERM_SECURE_USER_RWCD)>; start_address = <0x0 CONFIG_K3_OPTEE_LOAD_ADDR>; - end_address = <0x0 (CONFIG_K3_OPTEE_LOAD_ADDR + 0x17fffff)>; + end_address = <0x0 (CONFIG_K3_OPTEE_LOAD_ADDR + CONFIG_K3_OPTEE_RESERVED_SIZE - 1)>; }; ti_falcon_template: template-9 { diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 54eb9b4072c..8d51fea72b8 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -107,10 +107,6 @@ }; }; -&ospi1 { - status = "disabled"; -}; - &usbss0 { bootph-all; }; diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index c1c12e217d2..7d4a6dc5301 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -90,6 +90,11 @@ <0x0 0x50000000 0x0 0x8000000>; }; +&ospi1 { + reg = <0x0 0x47050000 0x0 0x100>, + <0x0 0x58000000 0x0 0x8000000>; +}; + &fss { /* fss node has 64 bit address regions mapped to it and since the ospi * nodes is being override, override the fss node ranges as well diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 2d89fa08b4d..d75a4e4be87 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -37,7 +37,7 @@ }; }; - snfi: snfi@1100d000 { + snfi: spi@1100d000 { compatible = "mediatek,mtk-snfi-spi"; reg = <0x1100d000 0x2000>; clocks = <&pericfg CLK_PERI_NFI_PD>, @@ -53,7 +53,7 @@ #size-cells = <0>; }; - snor: snor@11014000 { + snor: spi@11014000 { compatible = "mediatek,mtk-snor"; reg = <0x11014000 0x1000>; clocks = <&pericfg CLK_PERI_FLASH_PD>, @@ -86,7 +86,7 @@ clock-names = "system-clk"; }; - infracfg: infracfg@10000000 { + infracfg: clock-controller@10000000 { compatible = "mediatek,mt7622-infracfg", "syscon"; reg = <0x10000000 0x1000>; @@ -94,13 +94,13 @@ #reset-cells = <1>; }; - pericfg: pericfg@10002000 { + pericfg: clock-controller@10002000 { compatible = "mediatek,mt7622-pericfg", "syscon"; reg = <0x10002000 0x1000>; #clock-cells = <1>; }; - scpsys: scpsys@10006000 { + scpsys: power-controller@10006000 { compatible = "mediatek,mt7622-scpsys", "syscon"; #power-domain-cells = <1>; @@ -122,13 +122,13 @@ interrupt-parent = <&gic>; }; - apmixedsys: apmixedsys@10209000 { + apmixedsys: clock-controller@10209000 { compatible = "mediatek,mt7622-apmixedsys"; reg = <0x10209000 0x1000>; #clock-cells = <1>; }; - topckgen: topckgen@10210000 { + topckgen: clock-controller@10210000 { compatible = "mediatek,mt7622-topckgen"; reg = <0x10210000 0x1000>; #clock-cells = <1>; @@ -198,7 +198,7 @@ status = "disabled"; }; - ssusbsys: ssusbsys@1a000000 { + ssusbsys: clock-controller@1a000000 { compatible = "mediatek,mt7622-ssusbsys", "syscon"; reg = <0x1a000000 0x1000>; @@ -206,7 +206,7 @@ #reset-cells = <1>; }; - pciesys: pciesys@1a100800 { + pciesys: clock-controller@1a100800 { compatible = "mediatek,mt7622-pciesys", "syscon"; reg = <0x1a100800 0x1000>; #clock-cells = <1>; @@ -364,7 +364,7 @@ }; }; - ethsys: syscon@1b000000 { + ethsys: clock-controller@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>; #clock-cells = <1>; @@ -399,7 +399,7 @@ status = "disabled"; }; - sgmiisys: sgmiisys@1b128000 { + sgmiisys: syscon@1b128000 { compatible = "mediatek,mt7622-sgmiisys", "syscon"; reg = <0x1b128000 0x3000>; #clock-cells = <1>; @@ -424,7 +424,7 @@ status = "disabled"; }; - soft_i2c: soft_i2c@0 { + soft_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi similarity index 100% rename from arch/arm/dts/rk3288-evb-u-boot.dtsi rename to arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts deleted file mode 100644 index bb24a96cddf..00000000000 --- a/arch/arm/dts/rk3288-evb.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-evb.dtsi" - -/ { - model = "Evb-RK3288"; - compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi deleted file mode 100644 index 0e347beb154..00000000000 --- a/arch/arm/dts/rk3288-evb.dtsi +++ /dev/null @@ -1,476 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - button@0 { - gpio-key,wakeup = <1>; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = <116>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_sys>; - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <50>; - pwms = <&pwm0 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - pwm-delay-us = <10000>; - status = "disabled"; - }; - - panel: panel { - compatible = "simple-panel"; - power-supply = <&vcc_io>; - backlight = <&backlight>; - enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - status = "okay"; -}; - -&gmac { - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "vcca_codec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_tp: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_pmu: REG9 { - regulator-name = "vccio_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - broken-cd; - bus-width = <4>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vcc_18>; - status = "disabled"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&mipi_dsi { - status = "disabled"; - rockchip,panel = <&panel>; - display-timings { - timing0 { - bits-per-pixel = <24>; - clock-frequency = <160000000>; - hfront-porch = <120>; - hsync-len = <20>; - hback-porch = <21>; - hactive = <1200>; - vfront-porch = <21>; - vsync-len = <3>; - vback-porch = <18>; - vactive = <1920>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts deleted file mode 100644 index 736dc51e261..00000000000 --- a/arch/arm/dts/rk3288-popmetal.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-popmetal.dtsi" - -/ { - model = "PopMetal-RK3288"; - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi deleted file mode 100644 index ecff641b109..00000000000 --- a/arch/arm/dts/rk3288-popmetal.dtsi +++ /dev/null @@ -1,547 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "rk3288.dtsi" - -/ { - memory{ - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ - vcc18_dvp: vcc18-dvp-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc18-dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - - vcc28_dvp: vcc28-dvp-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dvp_pwr>; - regulator-name = "vcc28_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vcc_io>; - }; - - vcc5v0_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lan: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_lan"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - ldo5: LDO_REG5 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ldo5"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_33: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_33"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vccio_wl"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - ak8963: ak8963@0d { - compatible = "asahi-kasei,ak8975"; - reg = <0x0d>; - interrupt-parent = <&gpio8>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&comp_int>; - }; - - l3g4200d: l3g4200d@68 { - compatible = "st,l3g4200d-gyro"; - st,drdy-int-pin = <2>; - reg = <0x6b>; - }; - - mma8452: mma8452@1d { - compatible = "fsl,mma8452"; - reg = <0x1d>; - interrupt-parent = <&gpio8>; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca_33>; - bb-supply = <&vcc_io>; - dvp-supply = <&vcc18_dvp>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vccio_wl>; - status = "okay"; -}; - -&pinctrl { - ak8963 { - comp_int: comp-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dvp { - dvp_pwr: dvp-pwr { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - mma8452 { - gsensor_int: gsensor-int { - rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = ; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usb_host1 { - vbus-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-rock-pi-n8.dts b/arch/arm/dts/rk3288-rock-pi-n8.dts deleted file mode 100644 index c9894a60e70..00000000000 --- a/arch/arm/dts/rk3288-rock-pi-n8.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -/dts-v1/; -#include "rk3288.dtsi" -#include -#include "rk3288-vmarc-som.dtsi" - -/ { - model = "Radxa ROCK Pi N8"; - compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", - "rockchip,rk3288"; -}; diff --git a/arch/arm/dts/rk3288-rock2-som.dtsi b/arch/arm/dts/rk3288-rock2-som.dtsi deleted file mode 100644 index 58e32fbb80f..00000000000 --- a/arch/arm/dts/rk3288-rock2-som.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - mmc-pwrseq = <&emmc_pwrseq>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vccio_pmu>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins &phy_rst>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 30000>; - rx_delay = <0x10>; - tx_delay = <0x30>; -}; - -&i2c0 { - status = "okay"; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - system-power-controller; - inl1-supply = <&vcc_io>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_codec: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcca_tp: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccio_pmu: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-enable-ramp-delay = <300>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <3 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts deleted file mode 100644 index 41676696ba3..00000000000 --- a/arch/arm/dts/rk3288-rock2-square.dts +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-rock2-som.dtsi" - -/ { - model = "Radxa Rock 2 Square"; - compatible = "radxa,rock2-square", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vcc_usb_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - /* Always on as the rockchip usb phy doesn't have a vbus-supply - * property - */ - regulator-always-on; - regulator-name = "vcc_host"; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&gmac { - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - - }; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart2 { - status = "okay"; - reg-shift = <2>; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/dts/rk3288-veyron-chromebook.dtsi deleted file mode 100644 index 143eaae26db..00000000000 --- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron (and derivatives) board device tree source - * - * Copyright 2014 Google, Inc - */ - -#include -#include -#include "rk3288-veyron.dtsi" - -/ { - aliases { - i2c20 = &i2c_tunnel; - video0 = &vopl; - video1 = &vopb; - }; - - gpio_keys: gpio-keys { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; - lid { - label = "Lid"; - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - linux,code = <0>; /* SW_LID */ - linux,input-type = <5>; /* EV_SW */ - debounce-interval = <1>; - gpio-key,wakeup; - }; - }; - - gpio-charger { - compatible = "gpio-charger"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ac_present_ap>; - charger-type = "mains"; - }; - - /* A non-regulated voltage from power supply or battery */ - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vccsys"; - regulator-boot-on; - regulator-always-on; - }; - - vcc33_sys: vcc33-sys { - vin-supply = <&vccsys>; - }; - - vcc_5v: vcc-5v { - vin-supply = <&vccsys>; - }; - - /* This turns on vbus for host1 (dwc2) */ - vcc5_host1: vcc5-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host1_pwr_en>; - regulator-name = "vcc5_host1"; - regulator-always-on; - regulator-boot-on; - }; - - /* This turns on vbus for otg for host mode (dwc2) */ - vcc5v_otg: vcc5v-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usbotg_pwren_h>; - regulator-name = "vcc5_host2"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&rk808 { - regulators { - vcc33_ccd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_ccd"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&spi0 { - status = "okay"; - spi-activate-delay = <100>; - spi-max-frequency = <3000000>; - spi-deactivate-delay = <200>; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio7>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - ec-interrupt = <&gpio7 7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_int>; - reg = <0>; - google,cros-ec-spi-pre-delay = <30>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&i2c4 { - trackpad@15 { - compatible = "elan,i2c_touchpad"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int>; - reg = <0x15>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; - -&pinctrl { - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &suspend_l_wake - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &suspend_l_sleep - &bt_dev_wake_sleep - >; - - buttons { - ap_lid_int_l: ap-lid-int-l { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - charger { - ac_present_ap: ac-present-ap { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - cros-ec { - ec_int: ec-int { - rockchip,pins = <7 7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_wp_gpio: sdmmc-wp-gpio { - rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - suspend { - suspend_l_wake: suspend-l-wake { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_low>; - }; - - suspend_l_sleep: suspend-l-sleep { - rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - trackpad { - trackpad_int: trackpad-int { - rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-host { - host1_pwr_en: host1-pwr-en { - rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbotg_pwren_h: usbotg-pwren-h { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts deleted file mode 100644 index 40fee55c750..00000000000 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron Jerry Rev 3+ board device tree source - * - * Copyright 2014 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" - -/ { - model = "Google Jerry"; - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; - - sound { - compatible = "rockchip,audio-max98090-jerry"; - - cpu { - sound-dai = <&i2s 0>; - }; - - codec { - sound-dai = <&max98090 0>; - }; - }; -}; - -&gpio_keys { - power { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; -}; - -&backlight { - power-supply = <&backlight_regulator>; -}; - -&panel { - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - regulators { - mic_vcc: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "mic_vcc"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&sdmmc { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; - disable-wp; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&edp { - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - emmc { - /* Make sure eMMC is not in reset */ - emmc_deassert_reset: emmc-deassert-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&i2c4 { - status = "okay"; - - /* - * Trackpad pin control is shared between Elan and Synaptics devices - * so we have to pull it up to the bus level. - */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer &trackpad_int>; - - trackpad@15 { - compatible = "elan,i2c_touchpad"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - /* - * Remove the inherited pinctrl settings to avoid clashing - * with bus-wide ones. - */ - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - reg = <0x15>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; - - trackpad@2c { - compatible = "hid-over-i2c"; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; - wakeup-source; - }; -}; diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts deleted file mode 100644 index 0521d9e0e9a..00000000000 --- a/arch/arm/dts/rk3288-veyron-mickey.dts +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Google Veyron Mickey Rev 0 board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" - -/ { - model = "Google Mickey"; - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - - vcc_5v: vcc-5v { - vin-supply = <&vcc33_sys>; - }; - - vcc33_io: vcc33_io { - compatible = "regulator-fixed"; - regulator-name = "vcc33_io"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc33_sys>; - }; -}; - -&cpu_thermal { - /delete-node/ trips; - /delete-node/ cooling-maps; - - trips { - cpu_alert_almost_warm: cpu_alert_almost_warm { - temperature = <63000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_warm: cpu_alert_warm { - temperature = <65000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_almost_hot: cpu_alert_almost_hot { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hot: cpu_alert_hot { - temperature = <82000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_hotter: cpu_alert_hotter { - temperature = <84000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert_very_hot: cpu_alert_very_hot { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - /* - * After 1st level, throttle the CPU down to as low as 1.4 GHz - * and don't let the GPU go faster than 400 MHz. Note that we - * won't throttle the GPU lower than 400 MHz due to CPU - * heat--we'll let the GPU do the rest itself. - */ - cpu_warm_limit_cpu { - trip = <&cpu_alert_warm>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 4>; - }; - - /* - * Add some discrete steps to help throttling system deal - * with the fact that there are two passive cooling devices: - * the CPU and the GPU. - * - * - 1.2 GHz - 1.0 GHz (almost hot) - * - 800 MHz (hot) - * - 800 MHz - 696 MHz (hotter) - * - 696 MHz - min (very hot) - * - * Note: - * - 800 MHz appears to be a "sweet spot" for me. I can run - * some pretty serious workload here and be happy. - * - After 696 MHz we stop lowering voltage, so throttling - * past there is less effective. - */ - cpu_almost_hot_limit_cpu { - trip = <&cpu_alert_almost_hot>; - cooling-device = - <&cpu0 5 6>; - }; - cpu_hot_limit_cpu { - trip = <&cpu_alert_hot>; - cooling-device = - <&cpu0 7 7>; - }; - cpu_hotter_limit_cpu { - trip = <&cpu_alert_hotter>; - cooling-device = - <&cpu0 7 8>; - }; - cpu_very_hot_limit_cpu { - trip = <&cpu_alert_very_hot>; - cooling-device = - <&cpu0 8 THERMAL_NO_LIMIT>; - }; - }; -}; - -&emmc { - /delete-property/mmc-hs200-1_8v; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&i2s { - status = "okay"; - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - - /delete-property/ vcc6-supply; - /delete-property/ vcc12-supply; - - vcc11-supply = <&vcc33_sys>; - - regulators { - /* vcc33_io is sourced directly from vcc33_sys */ - /delete-node/ LDO_REG1; - /delete-node/ LDO_REG7; - - /* This is not a pwren anymore, but the real power supply */ - vdd10_lcd: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-suspend-mem-disabled; - }; - }; -}; - -&pinctrl { - hdmi { - power_hdmi_on: power-hdmi-on { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&sdmmc { - status = "disabled"; -}; - -&sdio0 { - status = "disabled"; -}; - -&sdmmc { - status = "disabled"; -}; - -&spi0 { - status = "disabled"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host1 { - status = "disabled"; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&power_hdmi_on>; -}; diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts deleted file mode 100644 index b56a3f4f51a..00000000000 --- a/arch/arm/dts/rk3288-veyron-minnie.dts +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Google Veyron Minnie Rev 0+ board device tree source - * - * Copyright 2015 Google, Inc - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" - -/ { - model = "Google Minnie"; - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - sound { - compatible = "rockchip,audio-max98090-jerry"; - - cpu { - sound-dai = <&i2s 0>; - }; - - codec { - sound-dai = <&max98090 0>; - }; - }; -}; - -&backlight { - /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = < - 0 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - power-supply = <&backlight_regulator>; -}; - -&emmc { - /delete-property/mmc-hs200-1_8v; -}; - -&gpio_keys { - pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>; - - volum_down { - label = "Volum_down"; - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; - - volum_up { - label = "Volum_up"; - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - }; -}; - -&i2c_tunnel { - battery: bq27500@55 { - compatible = "ti,bq27500"; - reg = <0x55>; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio2>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - vcc33-supply = <&vcc33_touch>; - vccio-supply = <&vcc33_touch>; - }; -}; - -&panel { - compatible = "auo,b101ean01", "simple-panel"; - power-supply= <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; - - regulators { - vcc33_touch: LDO_REG2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v_touch: SWITCH_REG2 { - regulator-name = "vcc5v_touch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - volum_down_l: volum-down-l { - rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - volum_up_l: volum-up-l { - rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - prochot { - gpio_prochot: gpio-prochot { - rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touchscreen { - touch_int: touch-int { - rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - touch_rst: touch-rst { - rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts deleted file mode 100644 index 58c1fe96eea..00000000000 --- a/arch/arm/dts/rk3288-veyron-speedy.dts +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Veyron Speedy Rev 1+ board device tree source - * - * Copyright 2015 Google, Inc - */ - -/dts-v1/; -#include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" -#include "rk3288-veyron-speedy-u-boot.dtsi" - -/ { - model = "Google Speedy"; - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - - panel_regulator: panel-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_h>; - regulator-name = "panel_regulator"; - startup-delay-us = <100000>; - vin-supply = <&vcc33_sys>; - }; - - vcc18_lcd: vcc18-lcd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_1v8_disp_en>; - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc18_wl>; - }; - - backlight_regulator: backlight-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_pwr_en>; - regulator-name = "backlight_regulator"; - vin-supply = <&vcc33_sys>; - startup-delay-us = <15000>; - }; -}; - -&backlight { - power-supply = <&backlight_regulator>; -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_alert1 { - temperature = <70000>; -}; - -&edp { - /delete-property/pinctrl-names; - /delete-property/pinctrl-0; - - force-hpd; -}; - -&panel { - power-supply = <&panel_regulator>; -}; - -&rk808 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; -}; - -&sdmmc { - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio - &sdmmc_bus4>; -}; - -&vcc_5v { - enable-active-high; - gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&drv_5v>; -}; - -&vcc50_hdmi { - enable-active-high; - gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; -}; - -&pinctrl { - backlight { - bl_pwr_en: bl_pwr_en { - rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buck-5v { - drv_5v: drv-5v { - rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_enable_h: lcd-en { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - avdd_1v8_disp_en: avdd-1v8-disp-en { - rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dvs_1: dvs-1 { - rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - dvs_2: dvs-2 { - rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi deleted file mode 100644 index 99406151bf5..00000000000 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ /dev/null @@ -1,795 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Google Veyron (and derivatives) board device tree source - * - * Copyright 2014 Google, Inc - */ - -#include -#include -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - chosen { - stdout-path = &uart2; - }; - - firmware { - chromeos { - pinctrl-names = "default"; - pinctrl-0 = <&fw_wp_ap>; - write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <128>; - enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - backlight-boot-off; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwms = <&pwm0 0 1000000 0>; - }; - - panel: panel { - compatible ="cnm,n116bgeea2","simple-panel"; - status = "okay"; - power-supply = <&vcc33_lcd>; - backlight = <&backlight>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_h>; - power { - label = "Power"; - gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <100>; - gpio-key,wakeup; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_warm_reset_h>; - priority = /bits/ 8 <200>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "rockchip,rockchip-audio-max98090"; - rockchip,model = "ROCKCHIP-I2S"; - rockchip,i2s-controller = <&i2s>; - rockchip,audio-codec = <&max98090>; - rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; - rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - rockchip,headset-codec = <&headsetcodec>; - pinctrl-names = "default"; - pinctrl-0 = <&mic_det>, <&hp_det>; - }; - - vdd_logic: pwm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 2000 0>; - - voltage-table = <1350000 0>, - <1300000 10>, - <1250000 20>, - <1200000 31>, - <1150000 41>, - <1100000 52>, - <1050000 62>, - <1000000 72>, - < 950000 83>; - - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_logic"; - regulator-ramp-delay = <4000>; - }; - - vcc33_sys: vcc33-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc33_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vccsys>; - }; - - vcc_5v: vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_5v>; - }; - - bt_regulator: bt-regulator { - /* - * On the module itself this is one of these (depending - * on the actual card pouplated): - * - BT_I2S_WS_BT_RFDISABLE_L - * - No connect - */ - - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_enable_l>; - regulator-name = "bt_regulator"; - }; - - wifi_regulator: wifi-regulator { - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - regulator-name = "wifi_regulator"; - - /* Faux input supply. See bt_regulator description. */ - vin-supply = <&bt_regulator>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&efuse { - status = "okay"; -}; - -&emmc { - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; - status = "okay"; -}; - -&sdio0 { - broken-cd; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - cap-sdio-irq; - card-external-vcc-supply = <&wifi_regulator>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, - <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock"; - keep-power-in-suspend; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; - status = "okay"; - vmmc-supply = <&vcc33_sys>; - vqmmc-supply = <&vcc18_wl>; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - card-detect-delay = <200>; - cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - num-slots = <1>; - status = "okay"; - vmmc-supply = <&vcc33_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&spi2 { - status = "okay"; - - spi_flash: spiflash@0 { - compatible = "spidev", "jedec,spi-nor"; - spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - clock-output-names = "xin32k", "wifibt_32kin"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - reg = <0x1b>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc33_sys>; - vcc2-supply = <&vcc33_sys>; - vcc3-supply = <&vcc33_sys>; - vcc4-supply = <&vcc33_sys>; - vcc6-supply = <&vcc_5v>; - vcc7-supply = <&vcc33_sys>; - vcc8-supply = <&vcc33_sys>; - vcc9-supply = <&vcc_5v>; - vcc10-supply = <&vcc33_sys>; - vcc11-supply = <&vcc_5v>; - vcc12-supply = <&vcc_18>; - - vddio-supply = <&vcc33_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd_arm"; - regulator-ramp-delay = <6001>; - regulator-suspend-mem-disabled; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <6001>; - regulator-suspend-mem-disabled; - }; - - vcc135_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc135_ddr"; - regulator-suspend-mem-enabled; - }; - - /* - * vcc_18 has several aliases. (vcc18_flashio and - * vcc18_wl). We'll add those aliases here just to - * make it easier to follow the schematic. The signals - * are actually hooked together and only separated for - * power measurement purposes). - */ - vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-suspend-mem-microvolt = <1800000>; - }; - - /* - * Note that both vcc33_io and vcc33_pmuio are always - * powered together. To simplify the logic in the dts - * we just refer to vcc33_io every time something is - * powered from vcc33_pmuio. In fact, on later boards - * (such as danger) they're the same net. - */ - vcc33_io: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_io"; - regulator-suspend-mem-microvolt = <3300000>; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-suspend-mem-microvolt = <1000000>; - }; - - vccio_sd: LDO_REG4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-suspend-mem-disabled; - }; - - vcc33_sd: LDO_REG5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_sd"; - regulator-suspend-mem-disabled; - }; - - vcc18_codec: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_codec"; - regulator-suspend-mem-disabled; - }; - - vdd10_lcd_pwren_h: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vdd10_lcd_pwren_h"; - regulator-suspend-mem-disabled; - }; - - vcc33_lcd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lcd"; - regulator-suspend-mem-disabled; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ - i2c-scl-rising-time-ns = <100>; /* 40ns measured */ - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&i2c2 { - status = "okay"; - - /* 100kHz since 4.7k resistors don't rise fast enough */ - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <50>; /* 10ns measured */ - i2c-scl-rising-time-ns = <800>; /* 600ns measured */ - - max98090: max98090@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - #sound-dai-cells = <0>; - interrupt-parent = <&gpio6>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&int_codec>; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; -}; - -&i2c4 { - status = "okay"; - - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <50>; /* 11ns measured */ - i2c-scl-rising-time-ns = <300>; /* 225ns measured */ - - headsetcodec: ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ts3a227e_int_l>; - ti,micbias = <7>; /* MICBIAS = 2.8V */ - }; -}; - -&i2c5 { - status = "okay"; - - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <300>; - i2c-scl-rising-time-ns = <1000>; -}; - -&i2s { - status = "okay"; - clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; -}; - -&io_domains { - audio-supply = <&vcc18_codec>; - bb-supply = <&vcc33_io>; - dvp-supply = <&vcc_18>; - flash0-supply = <&vcc18_flashio>; - gpio1830-supply = <&vcc33_io>; - gpio30-supply = <&vcc33_io>; - lcdc-supply = <&vcc33_lcd>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc18_wl>; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - - /* Pins don't include flow control by default; add that in */ - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - /* We need to go faster than 24MHz, so adjust clock parents / rates */ - assigned-clocks = <&cru SCLK_UART0>; - assigned-clock-rates = <48000000>; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; - reg-shift = <2>; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&edp { - status = "okay"; - rockchip,panel = <&panel>; -}; - -&hdmi { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&tsadc { - tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default", "sleep"; - pinctrl-0 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Wake only */ - &bt_dev_wake_awake - >; - pinctrl-1 = < - /* Common for sleep and wake, but no owners */ - &ddr0_retention - &ddrio_pwroff - &global_pwroff - - /* Sleep only */ - &bt_dev_wake_sleep - >; - - /* Add this for sdmmc pins to SD card */ - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwr_key_h: pwr-key-h { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - codec { - hp_det: hp-det { - rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - int_codec: int-codec { - rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - mic_det: mic-det { - rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, - <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - }; - - headset { - ts3a227e_int_l: ts3a227e-int-l { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - /* - * Causes jerry to hang when probing bus 0 - * rockchip,pins = ; - */ - }; - }; - - reboot { - ap_warm_reset_h: ap-warm-reset-h { - rockchip,pins = ; - }; - }; - - sdio0 { - wifi_enable_h: wifienable-h { - rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* NOTE: mislabelled on schematic; should be bt_enable_h */ - bt_enable_l: bt-enable-l { - rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* - * We run sdio0 at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * These pins are only present on very new veyron boards; on - * older boards bt_dev_wake is simply always high. Note that - * gpio4_26 is a NC on old veyron boards, so it doesn't hurt - * to map this pin everywhere - */ - bt_dev_wake_sleep: bt-dev-wake-sleep { - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>; - }; - - bt_dev_wake_awake: bt-dev-wake-awake { - rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - sdmmc { - /* - * We run sdmmc at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - /* - * Builtin CD line is hooked to ground to prevent JTAG at boot - * (and also to get the voltage rail correct). Make we - * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't - * think there's a card inserted - */ - sdmmc_cd_disabled: sdmmc-cd-disabled { - rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* This is where we actually hook up CD */ - sdmmc_cd_gpio: sdmmc-cd-gpio { - rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tpm { - tpm_int_h: tpm-int-h { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - write-protect { - fw_wp_ap: fw-wp-ap { - rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; - needs-reset-on-resume; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; - assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; - assigned-clock-parents = <&cru SCLK_OTGPHY0>; -}; diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi deleted file mode 100644 index 793951655b7..00000000000 --- a/arch/arm/dts/rk3288-vmarc-som.dtsi +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include -#include - -/ { - compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; - - vccio_flash: vccio-flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vccio_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_tp: LDO_REG1 { - regulator-name = "vcc_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_codec: LDO_REG2 { - regulator-name = "vcca_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_wl: LDO_REG4 { - regulator-name = "vcc_wl"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-name = "vcc18_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-name = "vcc_lcd"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio5>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - bb-supply = <&vcc_io>; - flash0-supply = <&vccio_flash>; - gpio1830-supply = <&vcc_18>; - gpio30-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_wl>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; - }; - }; - - vbus_host { - usb1_en_oc: usb1-en-oc { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - vbus_typec { - usb0_en_oc: usb0-en-oc { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdio_pwrseq { - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vbus_host { - enable-active-high; - gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ -}; - -&vbus_typec { - enable-active-high; - gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ -}; diff --git a/arch/arm/dts/rk3288-vyasa.dts b/arch/arm/dts/rk3288-vyasa.dts deleted file mode 100644 index 4193f7208cd..00000000000 --- a/arch/arm/dts/rk3288-vyasa.dts +++ /dev/null @@ -1,473 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Jagan Teki - */ - -/dts-v1/; -#include "rk3288.dtsi" - -/ { - model = "Amarula Vyasa-RK3288"; - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; - - memory { - reg = <0x0 0x0 0x0 0x80000000>; - device_type = "memory"; - }; - - dc12_vbat: dc12-vbat { - compatible = "regulator-fixed"; - regulator-name = "dc12_vbat"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vboot_3v3: vboot-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vboot_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vboot_5v: vboot-5v { - compatible = "regulator-fixed"; - regulator-name = "vboot_sv"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - v3g_3v3: v3g-3v3 { - compatible = "regulator-fixed"; - regulator-name = "v3g_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc12_vbat>; - }; - - vsus_5v: vsus-5v { - compatible = "regulator-fixed"; - regulator-name = "vsus_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc50_hdmi: vcc50-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vcc50_hdmi"; - enable-active-high; - gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */ - pinctrl-names = "default"; - pinctrl-0 = <&vcc50_hdmi_en>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - vusb1_5v: vusb1-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb1_5v"; - enable-active-high; - gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */ - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - vusb2_5v: vusb2-5v { - compatible = "regulator-fixed"; - regulator-name = "vusb2_5v"; - enable-active-high; - gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */ - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pwr_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsus_5v>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_io>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_tp: LDO_REG1 { - regulator-name = "vcc_tp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_codec: LDO_REG2 { - regulator-name = "vcc_codec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_gps: LDO_REG4 { - regulator-name = "vcc_gps"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: SWITCH_REG1 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_lan: SWITCH_REG2 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&phy_pwr_en>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hdmi { - vcc50_hdmi_en: vcc50-hdmi-en { - rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb_host { - phy_pwr_en: phy-pwr-en { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; - }; - - usb2_pwr_en: usb2-pwr-en { - rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - - }; - }; -}; diff --git a/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi b/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi new file mode 100644 index 00000000000..3e2fbd81da1 --- /dev/null +++ b/arch/arm/dts/rk3528-nanopi-zero2-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index dc3771b556a..018c9cc8d69 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -118,13 +118,11 @@ &sdhci { bootph-pre-ram; bootph-some-ram; - u-boot,spl-fifo-mode; }; &sdmmc { bootph-pre-ram; bootph-some-ram; - u-boot,spl-fifo-mode; }; &sdmmc0_bus4 { @@ -154,12 +152,10 @@ &sfc0 { bootph-some-ram; - u-boot,spl-sfc-no-dma; }; &sfc1 { bootph-some-ram; - u-boot,spl-sfc-no-dma; }; &sys_grf { diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index 6740f9866f1..04144e2ad12 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -1,13 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled + * Minimal generic DT for RK3582/RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled */ /dts-v1/; #include "rk3588s.dtsi" / { - model = "Generic RK3588S/RK3588"; + model = "Generic RK3582/RK3588S/RK3588"; compatible = "rockchip,rk3588"; aliases { diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi deleted file mode 100644 index da1d548b733..00000000000 --- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include - -/ { - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vbus_host: vbus-host { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_en_oc>; - regulator-name = "vbus_host"; /* HOST-5V */ - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_en_oc>; - regulator-name = "vbus_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&gmac { - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index 71d7623fe2c..4ba6a87e78a 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -246,16 +246,18 @@ pad-byte = <0x00>; u-boot-spl { - no-write-symbols; }; + payload { + type = "section"; + align = ; #ifdef HAS_FIT fit { insert-template = <&fit_template>; #else u-boot-img { #endif - offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>; + }; }; }; #endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */ diff --git a/arch/arm/dts/sc594-som-ezkit.dts b/arch/arm/dts/sc594-som-ezkit.dts index afc16df577a..dea9a6e27f2 100644 --- a/arch/arm/dts/sc594-som-ezkit.dts +++ b/arch/arm/dts/sc594-som-ezkit.dts @@ -22,7 +22,7 @@ eeprom { gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; + gpios = <0 GPIO_ACTIVE_LOW>; output-low; line-name = "eeprom-en"; bootph-pre-ram; @@ -30,7 +30,7 @@ pushbutton { gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; + gpios = <1 GPIO_ACTIVE_LOW>; output-low; line-name = "pushbutton-en"; bootph-pre-ram; @@ -70,7 +70,7 @@ octal { gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; + gpios = <8 GPIO_ACTIVE_LOW>; output-low; line-name = "octal-spi-cs-en"; bootph-pre-ram; diff --git a/arch/arm/dts/smbios_generic.dtsi b/arch/arm/dts/smbios_generic.dtsi index fc168317c9e..fe16037fc20 100644 --- a/arch/arm/dts/smbios_generic.dtsi +++ b/arch/arm/dts/smbios_generic.dtsi @@ -77,6 +77,18 @@ SMBIOS_CACHE_OP_WB)>; }; }; + + system-slot { + }; + + memory-array { + }; + + memory-device { + }; + + memory-array-mapped-address { + }; }; }; }; diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi index 695242bec21..ddef9a2896d 100644 --- a/arch/arm/dts/socfpga-common-u-boot.dtsi +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2019 Simon Goldschmidt */ /{ - memory { + memory@0 { bootph-all; }; diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 770f6cad292..c0f932d0e11 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -264,7 +264,7 @@ }; #endif -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M &sdr { compatible = "intel,sdr-ctl-agilex7m"; reg = <0xf8020000 0x100>; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 5a7aa5841e3..c03f78b2fdf 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -110,26 +110,49 @@ status = "okay"; no-mmc; - no-1-8-v; disable-wp; cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; vmmc-supply = <&sd_emmc_power>; vqmmc-supply = <&sd_io_1v8_reg>; max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0000c800>; + sdhci-caps-mask = <0x00002000 0x0000ff00>; /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; - cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; /* SD card high speed and UHS-I SDR25 mode timing configuration */ cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; - cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>; cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + /* SD card UHS-I SDR50 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>; + cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>; + cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>; + cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>; + + /* SD card UHS-I SDR104 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>; + cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>; + cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>; + bootph-all; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts index f6848c373cd..c06781064ca 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts @@ -25,11 +25,14 @@ disable-wp; non-removable; cap-mmc-highspeed; - + mmc-hs200-1_8v; + mmc-hs400-1_8v; bus-width = <8>; vmmc-supply = <&sd_emmc_power>; vqmmc-supply = <&emmc_io_1v8_reg>; max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0004c800>; /* SDHCI_CAN_DO_8BIT */ + sdhci-caps-mask = <0x00000000 0x0000ff00>; /* eMMC legacy mode timing configuration */ cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; @@ -46,4 +49,26 @@ cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>; cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>; + + /* eMMC HS200 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>; + cdns,phy-dq-timing-delay-emmc-hs200 = <0x10000001>; + cdns,phy-dll-master-ctrl-emmc-hs200 = <0x4>; + cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>; + + /* eMMC HS400 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-hs400 = <0x680004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs400 = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-hs400 = <0x4d4b40>; + cdns,phy-dq-timing-delay-emmc-hs400 = <0x10000001>; + cdns,phy-dll-master-ctrl-emmc-hs400 = <0x4>; + cdns,ctrl-hrs09-timing-delay-emmc-hs400 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400 = <0x80000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs400 = <0x11000001>; + cdns,ctrl-hrs07-timing-delay-emmc-hs400 = <0x90001>; }; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 6f2fe7bf746..f2150b7eb7b 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -8,7 +8,7 @@ #include "socfpga_agilex-u-boot.dtsi" -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX /{ chosen { stdout-path = "serial0:115200n8"; @@ -27,7 +27,7 @@ }; #endif -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M /{ model = "SoCFPGA Agilex7-M SoCDK"; chosen { @@ -181,3 +181,41 @@ }; }; }; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&fdt_0_blob { + filename = "dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dtb"; +}; + +&images { + fdt-1 { + description = "socfpga_socdk_nand"; + type = "flat_dt"; + compression = "none"; + fdt_1_blob: blob-ext { + filename = "dts/upstream/src/arm64/intel/socfpga_agilex_socdk_nand.dtb"; + }; + hash { + algo = "crc32"; + }; + }; +}; + +&board_config { + board-1 { + description = "board_1"; + firmware = "atf"; + loadables = "uboot"; + fdt = "fdt-1"; + signature { + algo = "crc32"; + key-name-hint = "dev"; + sign-images = "atf", "uboot", "fdt-1"; + }; + }; +}; + +&binman { + /delete-node/ kernel; +}; +#endif diff --git a/arch/arm/dts/socfpga_arria5_secu1.dts b/arch/arm/dts/socfpga_arria5_secu1.dts index 8e9c3bbdf9d..dfc04cc2d7a 100644 --- a/arch/arm/dts/socfpga_arria5_secu1.dts +++ b/arch/arm/dts/socfpga_arria5_secu1.dts @@ -16,7 +16,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x20000000>; /* 512MB */ diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi new file mode 100644 index 00000000000..8d2caf69dd1 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +#include "socfpga-common-u-boot.dtsi" + +/{ + aliases { + udc0 = &usb1; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + bootph-all; +}; + +&uart0 { + clock-frequency = <100000000>; + bootph-all; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc.dts b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts new file mode 100644 index 00000000000..6b02fa63c7c --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025, Brian Sune + * + * based on socfpga_cyclone5_socdk.dts + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "CoreCourse AC501SoC"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi new file mode 100644 index 00000000000..8d2caf69dd1 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +#include "socfpga-common-u-boot.dtsi" + +/{ + aliases { + udc0 = &usb1; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + bootph-all; +}; + +&uart0 { + clock-frequency = <100000000>; + bootph-all; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc.dts b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts new file mode 100644 index 00000000000..cc841e85560 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025, Brian Sune + * + * based on socfpga_cyclone5_socdk.dts + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "CoreCourse AC550SoC,AC802-CVA6"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 6 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&porta 9 1>; + }; + }; + + buttons { + compatible = "gpio-keys"; + hps0 { + label = "HPS GPIO0"; + gpios = <&porta 0 0>; + }; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <100000>; + + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index ca030c8c41b..094db1cb7d4 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -20,7 +20,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index 34886ec1ad8..346b2ef9e2d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -22,7 +22,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts index b38f0723823..37203b63410 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts @@ -22,7 +22,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index e9de72429f2..264ca3dd53f 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -20,7 +20,7 @@ udc0 = &usb1; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 58a5faf6ea2..b26248b023e 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x0 0x10000000>; diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 93a8e0697d6..88f0154463d 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -28,7 +28,7 @@ os = "U-Boot"; arch = "arm64"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x80200000>; #else load = <0x00200000>; @@ -47,7 +47,7 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x80000000>; entry = <0x80000000>; #else @@ -106,7 +106,7 @@ arch = "arm64"; os = "linux"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x86000000>; entry = <0x86000000>; #else diff --git a/arch/arm/dts/tegra114-asus-tf701t.dts b/arch/arm/dts/tegra114-asus-tf701t.dts index 2505b9bb726..bd43a80a208 100644 --- a/arch/arm/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/dts/tegra114-asus-tf701t.dts @@ -1151,7 +1151,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; @@ -1165,7 +1165,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts index 18bcb75fafa..48708f37246 100644 --- a/arch/arm/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000400"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000400"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; }; @@ -57,13 +57,13 @@ spi-max-frequency = <25000000>; }; - sdhci@78000400 { + mmc@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; bus-width = <4>; status = "okay"; }; - sdhci@78000600 { + mmc@78000600 { bus-width = <8>; status = "okay"; non-removable; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi index f8f71262538..f735f5060ce 100644 --- a/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi +++ b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi @@ -35,7 +35,7 @@ compatible = "samsung,ltl106hl02-001"; reg = <0>; - vdd-supply = <&tps65090_fet4>; + power-supply = <&tps65090_fet4>; backlight = <&backlight>; }; @@ -814,7 +814,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; @@ -827,7 +827,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra114-nvidia-tegratab.dts b/arch/arm/dts/tegra114-nvidia-tegratab.dts index f65772a8e01..6ff2850b911 100644 --- a/arch/arm/dts/tegra114-nvidia-tegratab.dts +++ b/arch/arm/dts/tegra114-nvidia-tegratab.dts @@ -953,7 +953,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; @@ -967,7 +967,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 250d692f6bf..0a783fbc95d 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -631,7 +631,7 @@ #nvidia,mipi-calibrate-cells = <1>; }; - sdhci@78000000 { + mmc@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = ; @@ -641,7 +641,7 @@ status = "disabled"; }; - sdhci@78000200 { + mmc@78000200 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; interrupts = ; @@ -651,7 +651,7 @@ status = "disabled"; }; - sdhci@78000400 { + mmc@78000400 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; interrupts = ; @@ -661,7 +661,7 @@ status = "disabled"; }; - sdhci@78000600 { + mmc@78000600 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; interrupts = ; diff --git a/arch/arm/dts/tegra124-apalis.dts b/arch/arm/dts/tegra124-apalis.dts index 08184ab3ac2..5ac08037a92 100644 --- a/arch/arm/dts/tegra124-apalis.dts +++ b/arch/arm/dts/tegra124-apalis.dts @@ -54,9 +54,9 @@ i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; - mmc2 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; + mmc2 = "/mmc@700b0400"; rtc0 = "/i2c@7000c000/rtc@68"; rtc1 = "/i2c@7000d000/pmic@40"; rtc2 = "/rtc@7000e000"; @@ -1958,7 +1958,7 @@ }; /* Apalis MMC1 */ - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; /* MMC1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; @@ -1967,7 +1967,7 @@ }; /* Apalis SD1 */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; /* SD1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; @@ -1976,7 +1976,7 @@ }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124-cei-tk1-som.dts b/arch/arm/dts/tegra124-cei-tk1-som.dts index e5b41f3183c..59901a3439b 100644 --- a/arch/arm/dts/tegra124-cei-tk1-som.dts +++ b/arch/arm/dts/tegra124-cei-tk1-som.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -297,7 +297,7 @@ }; }; - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -305,7 +305,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; }; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index 59e080a8af6..7d19a25e278 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -301,7 +301,7 @@ }; }; - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -309,7 +309,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index f1c97052a84..b942d92e900 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -16,8 +16,8 @@ i2c5 = "/i2c@7000d100"; rtc0 = "/i2c@7000d000/pmic@40"; rtc1 = "/rtc@7000e000"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -59,7 +59,7 @@ ddc-i2c-bus = <&dpaux>; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi index 2b28fe14970..7b465c601af 100644 --- a/arch/arm/dts/tegra124-nyan.dtsi +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -370,7 +370,7 @@ reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - sdhci@700b0000 { /* WiFi/BT on this bus */ + mmc@700b0000 { /* WiFi/BT on this bus */ status = "okay"; power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; bus-width = <4>; @@ -382,7 +382,7 @@ keep-power-in-suspend; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -392,7 +392,7 @@ vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { /* eMMC on this bus */ + mmc@700b0600 { /* eMMC on this bus */ status = "okay"; bus-width = <8>; no-1-8-v; diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts index 7e9c6aa1839..0e855d8bc30 100644 --- a/arch/arm/dts/tegra124-venice2.dts +++ b/arch/arm/dts/tegra124-venice2.dts @@ -17,8 +17,8 @@ i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; i2c5 = "/i2c@7000d100"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0400"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0400"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; @@ -70,7 +70,7 @@ spi-max-frequency = <25000000>; }; - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -78,7 +78,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124-xiaomi-mocha.dts b/arch/arm/dts/tegra124-xiaomi-mocha.dts index 64386f2b7b7..09b5c1eea05 100644 --- a/arch/arm/dts/tegra124-xiaomi-mocha.dts +++ b/arch/arm/dts/tegra124-xiaomi-mocha.dts @@ -476,7 +476,7 @@ }; }; - sdmmc3: sdhci@700b0400 { + sdmmc3: mmc@700b0400 { status = "okay"; bus-width = <4>; @@ -487,7 +487,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@700b0600 { + sdmmc4: mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index cac9b112302..1c62d1f6e7b 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -717,7 +717,7 @@ #phy-cells = <1>; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0000 0x200>; interrupts = ; @@ -727,7 +727,7 @@ status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0200 0x200>; interrupts = ; @@ -737,7 +737,7 @@ status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0400 0x200>; interrupts = ; @@ -747,7 +747,7 @@ status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra124-sdhci"; reg = <0x700b0600 0x200>; interrupts = ; diff --git a/arch/arm/dts/tegra186-p2771-0000-000.dts b/arch/arm/dts/tegra186-p2771-0000-000.dts index 84e850d6fca..39076058bfb 100644 --- a/arch/arm/dts/tegra186-p2771-0000-000.dts +++ b/arch/arm/dts/tegra186-p2771-0000-000.dts @@ -6,7 +6,7 @@ model = "NVIDIA P2771-0000-000"; compatible = "nvidia,p2771-0000-000", "nvidia,p2771-0000", "nvidia,tegra186"; - sdhci@3400000 { + mmc@3400000 { cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>; power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/tegra186-p2771-0000-500.dts b/arch/arm/dts/tegra186-p2771-0000-500.dts index 1ac8ab431e9..cb36dae80e5 100644 --- a/arch/arm/dts/tegra186-p2771-0000-500.dts +++ b/arch/arm/dts/tegra186-p2771-0000-500.dts @@ -6,7 +6,7 @@ model = "NVIDIA P2771-0000-500"; compatible = "nvidia,p2771-0000-500", "nvidia,p2771-0000", "nvidia,tegra186"; - sdhci@3400000 { + mmc@3400000 { cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi index 7cda0b41f74..7bbf81fe2bf 100644 --- a/arch/arm/dts/tegra186-p2771-0000.dtsi +++ b/arch/arm/dts/tegra186-p2771-0000.dtsi @@ -10,8 +10,8 @@ aliases { ethernet = "/ethernet@2490000"; - mmc0 = "/sdhci@3460000"; - mmc1 = "/sdhci@3400000"; + mmc0 = "/mmc@3460000"; + mmc1 = "/mmc@3400000"; i2c0 = "/bpmp/i2c"; i2c1 = "/i2c@3160000"; i2c2 = "/i2c@c240000"; @@ -48,13 +48,13 @@ status = "okay"; }; - sdhci@3400000 { + mmc@3400000 { status = "okay"; wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@3460000 { + mmc@3460000 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index edcb7aacb8e..0cabf608a9e 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -136,7 +136,7 @@ status = "disabled"; }; - sdhci@3400000 { + mmc@3400000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03400000 0x0 0x200>; resets = <&bpmp TEGRA186_RESET_SDMMC1>; @@ -146,7 +146,7 @@ status = "disabled"; }; - sdhci@3460000 { + mmc@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x200>; resets = <&bpmp TEGRA186_RESET_SDMMC4>; diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts index 4afde766330..d8d2d10a48a 100644 --- a/arch/arm/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts @@ -400,7 +400,7 @@ nvidia,xcvr-lsrslew = <2>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -412,7 +412,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-asus-transformer.dtsi b/arch/arm/dts/tegra20-asus-transformer.dtsi index df078a6fcdc..db6bed3e5d2 100644 --- a/arch/arm/dts/tegra20-asus-transformer.dtsi +++ b/arch/arm/dts/tegra20-asus-transformer.dtsi @@ -437,7 +437,7 @@ status = "okay"; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -449,7 +449,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index 11023968f41..776491a515e 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -14,7 +14,7 @@ i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; /* On-module only, for ASIX */ usb2 = "/usb@c5008000"; @@ -106,7 +106,7 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index 7fe7d52096c..60cc7b32bb0 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -18,8 +18,8 @@ usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; usb2 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000200"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000200"; }; memory { @@ -645,7 +645,7 @@ status = "okay"; }; - sdhci@c8000200 { + mmc@c8000200 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -653,7 +653,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra20-lg-star.dts b/arch/arm/dts/tegra20-lg-star.dts index 083598b1b92..912c0b6051b 100644 --- a/arch/arm/dts/tegra20-lg-star.dts +++ b/arch/arm/dts/tegra20-lg-star.dts @@ -327,13 +327,7 @@ pmic: max8907@3c { compatible = "maxim,max8907"; reg = <0x3c>; - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; maxim,system-power-controller; @@ -419,7 +413,7 @@ vbus-supply = <&avdd_3v3_usb>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -429,7 +423,7 @@ vqmmc-supply = <&vdd_1v8_vio>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts index 1c79d757467..00e9272541a 100644 --- a/arch/arm/dts/tegra20-medcom-wide.dts +++ b/arch/arm/dts/tegra20-medcom-wide.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi index db2cce1cc0d..b3c0e36340d 100644 --- a/arch/arm/dts/tegra20-motorola-mot.dtsi +++ b/arch/arm/dts/tegra20-motorola-mot.dtsi @@ -330,7 +330,7 @@ backlight_led: led@0 { reg = <0>; - led-sources = <2>; + led-sources = <0>; led-max-microamp = <26600>; ti,led-mode = <0>; @@ -425,7 +425,7 @@ vbus-supply = <&avdd_3v3_periph>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -435,7 +435,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index f851767a55f..91799518412 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -19,8 +19,8 @@ usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; usb2 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000000"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000000"; }; memory { @@ -485,7 +485,7 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -493,7 +493,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts index 1b642be9928..8d8672da23d 100644 --- a/arch/arm/dts/tegra20-plutux.dts +++ b/arch/arm/dts/tegra20-plutux.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-samsung-bose.dts b/arch/arm/dts/tegra20-samsung-bose.dts index 5bb9a33adf2..64cf8489707 100644 --- a/arch/arm/dts/tegra20-samsung-bose.dts +++ b/arch/arm/dts/tegra20-samsung-bose.dts @@ -92,7 +92,7 @@ }; }; - sdhci@c8000400 { + mmc@c8000400 { broken-cd; }; diff --git a/arch/arm/dts/tegra20-samsung-n1-common.dtsi b/arch/arm/dts/tegra20-samsung-n1-common.dtsi index 8223c5ece54..b82e6464248 100644 --- a/arch/arm/dts/tegra20-samsung-n1-common.dtsi +++ b/arch/arm/dts/tegra20-samsung-n1-common.dtsi @@ -319,13 +319,7 @@ pmic: max8907@3c { compatible = "maxim,max8907"; reg = <0x3c>; - interrupts = ; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; maxim,system-power-controller; @@ -371,7 +365,7 @@ vbus-supply = <&usb_phy_reg>; }; - sdmmc3: sdhci@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; @@ -379,7 +373,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - sdmmc4: sdhci@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-samsung-n1.dts b/arch/arm/dts/tegra20-samsung-n1.dts index 930a3195aa0..82b337973b9 100644 --- a/arch/arm/dts/tegra20-samsung-n1.dts +++ b/arch/arm/dts/tegra20-samsung-n1.dts @@ -151,7 +151,7 @@ }; }; - sdhci@c8000400 { + mmc@c8000400 { /* battery blocks the sdcard slot and the device lacks CD pin */ non-removable; }; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 341c7f35836..dbb2e49962e 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -19,8 +19,8 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000400"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000400"; }; chosen { @@ -803,14 +803,14 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -818,7 +818,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi index f13ef4d05a8..98fa51bed30 100644 --- a/arch/arm/dts/tegra20-tamonten.dtsi +++ b/arch/arm/dts/tegra20-tamonten.dtsi @@ -476,7 +476,7 @@ status = "okay"; }; - sdhci@c8000600 { + mmc@c8000600 { cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts index 4733c813490..b26979496c6 100644 --- a/arch/arm/dts/tegra20-tec.dts +++ b/arch/arm/dts/tegra20-tec.dts @@ -12,7 +12,7 @@ aliases { usb0 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; + mmc0 = "/mmc@c8000600"; }; memory { diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index fa942d26078..9542eb6c41b 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -12,8 +12,8 @@ aliases { usb0 = "/usb@c5000000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000000"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000000"; spi0 = "/spi@7000c380"; }; @@ -55,12 +55,12 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 85cd1e39bda..50cf78e4170 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -18,8 +18,8 @@ usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; usb2 = "/usb@c5008000"; - mmc0 = "/sdhci@c8000600"; - mmc1 = "/sdhci@c8000400"; + mmc0 = "/mmc@c8000600"; + mmc1 = "/mmc@c8000400"; }; memory { @@ -576,14 +576,14 @@ status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -591,7 +591,7 @@ bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 4a40edfdfbe..430df19b8b7 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -766,7 +766,7 @@ status = "disabled"; }; - sdhci@c8000000 { + mmc@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; interrupts = ; @@ -776,7 +776,7 @@ status = "disabled"; }; - sdhci@c8000200 { + mmc@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; interrupts = ; @@ -786,7 +786,7 @@ status = "disabled"; }; - sdhci@c8000400 { + mmc@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; interrupts = ; @@ -796,7 +796,7 @@ status = "disabled"; }; - sdhci@c8000600 { + mmc@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; interrupts = ; diff --git a/arch/arm/dts/tegra210-p2371-0000.dts b/arch/arm/dts/tegra210-p2371-0000.dts index 539e7cef93b..e5e9d68651a 100644 --- a/arch/arm/dts/tegra210-p2371-0000.dts +++ b/arch/arm/dts/tegra210-p2371-0000.dts @@ -12,8 +12,8 @@ aliases { i2c0 = "/i2c@7000d000"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; usb0 = "/usb@7d000000"; }; @@ -21,14 +21,14 @@ reg = <0x0 0x80000000 0x0 0xc0000000>; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts index 649c163152e..a619b2475eb 100644 --- a/arch/arm/dts/tegra210-p2371-2180.dts +++ b/arch/arm/dts/tegra210-p2371-2180.dts @@ -14,8 +14,8 @@ i2c0 = "/i2c@7000d000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; usb0 = "/usb@7d000000"; }; @@ -73,7 +73,7 @@ }; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; @@ -81,7 +81,7 @@ bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210-p2571.dts b/arch/arm/dts/tegra210-p2571.dts index 16370c596e0..f48ce4d662f 100644 --- a/arch/arm/dts/tegra210-p2571.dts +++ b/arch/arm/dts/tegra210-p2571.dts @@ -17,8 +17,8 @@ i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; i2c5 = "/i2c@7000d100"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; spi2 = "/spi@70410000"; @@ -74,14 +74,14 @@ spi-max-frequency = <24000000>; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts index ddeeb232de2..333060a4ec7 100644 --- a/arch/arm/dts/tegra210-p3450-0000.dts +++ b/arch/arm/dts/tegra210-p3450-0000.dts @@ -20,8 +20,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@700b0600"; - mmc1 = "/sdhci@700b0000"; + mmc0 = "/mmc@700b0600"; + mmc1 = "/mmc@700b0000"; spi0 = "/spi@70410000"; usb0 = "/usb@7d000000"; }; @@ -89,14 +89,14 @@ }; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index 92eb4f67bf5..45b1ca9a041 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -696,7 +696,7 @@ #phy-cells = <1>; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; @@ -709,7 +709,7 @@ status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; @@ -722,7 +722,7 @@ status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; @@ -735,7 +735,7 @@ status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 77502dfdb47..19553d14fb1 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -15,9 +15,9 @@ i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c500"; i2c3 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000400"; - mmc2 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000400"; + mmc2 = "/mmc@78000000"; spi0 = "/spi@7000d400"; spi1 = "/spi@7000dc00"; spi2 = "/spi@7000de00"; @@ -246,21 +246,21 @@ spi-max-frequency = <25000000>; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; bus-width = <4>; /* SD1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; }; - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <8>; /* MMC1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index ddacdbb85c8..8eb36eb8164 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -773,7 +773,7 @@ clock-frequency = <400000>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 31cbef1b93c..2d6b4aba016 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -1100,7 +1100,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1111,7 +1111,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index 5135b8c666c..498c398baad 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -1065,7 +1065,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1076,7 +1076,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index 47a44fbc9dd..e58414dc4b0 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -1093,7 +1093,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1104,7 +1104,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index 9bb097b0813..b78982edd1a 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000000"; spi0 = "/spi@7000da00"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d008000"; @@ -191,7 +191,7 @@ }; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; @@ -199,7 +199,7 @@ bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts index 7534861e40d..299ba7ef371 100644 --- a/arch/arm/dts/tegra30-cardhu.dts +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -16,8 +16,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000000"; spi0 = "/spi@7000da00"; usb0 = "/usb@7d008000"; }; @@ -183,7 +183,7 @@ spi-max-frequency = <25000000>; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; @@ -191,7 +191,7 @@ bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-colibri.dts b/arch/arm/dts/tegra30-colibri.dts index 38afe7819c7..075a35f1c9a 100644 --- a/arch/arm/dts/tegra30-colibri.dts +++ b/arch/arm/dts/tegra30-colibri.dts @@ -14,8 +14,8 @@ i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c700"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000200"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000200"; spi0 = "/spi@7000d400"; usb0 = "/usb@7d000000"; usb1 = "/usb@7d004000"; /* on module only, for ASIX */ @@ -61,13 +61,13 @@ spi-max-frequency = <25000000>; }; - sdhci@78000200 { + mmc@78000200 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index 79f423bd22a..e67d335f73c 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -1246,7 +1246,7 @@ }; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts index 53f42089d30..2d96d6867e6 100644 --- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts +++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts @@ -1119,7 +1119,7 @@ >; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1129,7 +1129,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts index ab5993150b2..84b6dc1f95a 100644 --- a/arch/arm/dts/tegra30-lg-p880.dts +++ b/arch/arm/dts/tegra30-lg-p880.dts @@ -126,7 +126,7 @@ }; }; - sdmmc3: sdhci@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; bus-width = <4>; diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts index 988e772172c..a45d57b3e71 100644 --- a/arch/arm/dts/tegra30-lg-p895.dts +++ b/arch/arm/dts/tegra30-lg-p895.dts @@ -120,7 +120,7 @@ reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; renesas,gamma = <3>; - renesas,inversion; + renesas,column-inversion; renesas,contrast; vcc-supply = <&vcc_3v0_lcd>; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 09c5d04a225..9c074f3c553 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -1031,7 +1031,7 @@ }; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-microsoft-surface-rt.dts b/arch/arm/dts/tegra30-microsoft-surface-rt.dts index 2d22d3e0bb1..77cd79cb0d6 100644 --- a/arch/arm/dts/tegra30-microsoft-surface-rt.dts +++ b/arch/arm/dts/tegra30-microsoft-surface-rt.dts @@ -946,7 +946,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -956,7 +956,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts index e6b2824d783..4911c802a51 100644 --- a/arch/arm/dts/tegra30-ouya.dts +++ b/arch/arm/dts/tegra30-ouya.dts @@ -1970,7 +1970,7 @@ }; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-pegatron-chagall.dts b/arch/arm/dts/tegra30-pegatron-chagall.dts index 98eb369f7a8..1ff53b7c54b 100644 --- a/arch/arm/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/dts/tegra30-pegatron-chagall.dts @@ -1121,7 +1121,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -1131,7 +1131,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi index 33da1754d30..0240568cd94 100644 --- a/arch/arm/dts/tegra30-tamonten.dtsi +++ b/arch/arm/dts/tegra30-tamonten.dtsi @@ -18,9 +18,9 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000d000"; - mmc0 = "/sdhci@78000600"; - mmc1 = "/sdhci@78000400"; - mmc2 = "/sdhci@78000000"; + mmc0 = "/mmc@78000600"; + mmc1 = "/mmc@78000400"; + mmc2 = "/mmc@78000000"; usb0 = "/usb@7d008000"; }; @@ -54,14 +54,14 @@ }; /* SD slot on the base board */ - sdhci@78000400 { + mmc@78000400 { cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; /* EMMC on the COM module */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30-tec-ng.dts b/arch/arm/dts/tegra30-tec-ng.dts index f2a49b8cbe2..444a390ba58 100644 --- a/arch/arm/dts/tegra30-tec-ng.dts +++ b/arch/arm/dts/tegra30-tec-ng.dts @@ -16,7 +16,7 @@ }; /* SD card slot */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; }; }; diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts index ededbf579fd..c310a22f56f 100644 --- a/arch/arm/dts/tegra30-wexler-qc750.dts +++ b/arch/arm/dts/tegra30-wexler-qc750.dts @@ -985,7 +985,7 @@ }; }; - sdmmc1: sdhci@78000000 { + sdmmc1: mmc@78000000 { status = "okay"; bus-width = <4>; @@ -996,7 +996,7 @@ vqmmc-supply = <&vddio_usd>; }; - sdmmc4: sdhci@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 82e843d05be..cf772338b55 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -803,7 +803,7 @@ }; }; - sdhci@78000000 { + mmc@78000000 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; interrupts = ; @@ -813,7 +813,7 @@ status = "disabled"; }; - sdhci@78000200 { + mmc@78000200 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; interrupts = ; @@ -823,7 +823,7 @@ status = "disabled"; }; - sdhci@78000400 { + mmc@78000400 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; interrupts = ; @@ -833,7 +833,7 @@ status = "disabled"; }; - sdhci@78000600 { + mmc@78000600 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; interrupts = ; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 832dc5ab245..8342479b108 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -3,7 +3,7 @@ * dts file for KD240 revA Carrier Card * * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -43,6 +43,13 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; }; &can0 { @@ -116,7 +123,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -125,7 +132,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 532f6bf92bc..db042ffb4f3 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -77,6 +77,14 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, + <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -187,7 +195,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -196,7 +204,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; @@ -224,7 +232,7 @@ reg = <1>; peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -233,7 +241,7 @@ reg = <2>; peer-hub = <&hub1_2_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 458d79e8119..e3567d0abfe 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -78,6 +78,14 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, + <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -188,7 +196,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -197,7 +205,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub_1>; - reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; @@ -225,7 +233,7 @@ reg = <1>; peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -234,7 +242,7 @@ reg = <2>; peer-hub = <&hub1_2_0>; i2c-bus = <&hub_2>; - reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 1 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index e7417af8ae0..f93c7460a55 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -3,7 +3,7 @@ * dts file for KV260 revA Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * SD level shifter: * "A" - A01 board un-modified (NXP) @@ -78,6 +78,13 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -161,7 +168,7 @@ compatible = "usb424,2744"; reg = <1>; peer-hub = <&hub_3_0>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -169,7 +176,7 @@ compatible = "usb424,5744"; reg = <2>; peer-hub = <&hub_2_0>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 7a05180e58b..70de6933600 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -74,6 +74,13 @@ }; }; }; + + slg_delay: enable-delay { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -148,7 +155,7 @@ reg = <1>; peer-hub = <&hub_3_0>; i2c-bus = <&hub>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; /* 3.0 hub on port 2 */ @@ -157,7 +164,7 @@ reg = <2>; peer-hub = <&hub_2_0>; i2c-bus = <&hub>; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + reset-gpios = <&slg_delay 0 10000 10000>; }; }; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 1af9778f8ce..25d0f205fde 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -79,6 +79,7 @@ #define MXC_CPU_IMX95 0x1C1 /* dummy ID */ #define MXC_CPU_IMX94 0x1C2 /* dummy ID */ +#define MXC_CPU_IMX952 0x1C3 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 diff --git a/arch/arm/include/asm/arch-rk3506/boot0.h b/arch/arm/include/asm/arch-rk3506/boot0.h new file mode 100644 index 00000000000..8ae46f25a87 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3506/boot0.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3506/gpio.h b/arch/arm/include/asm/arch-rk3506/gpio.h new file mode 100644 index 00000000000..5516e649b80 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3506/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 3c204501f70..95b08bfd046 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -214,6 +214,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); */ int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table, u32 reg_offset, u32 reg_number); +/* + * rk3506_reset_bind_lut() - Bind soft reset device as child of clock device + * using dedicated RK3506 lookup table + * + * @pdev: clock udevice + * @reg_offset: the first offset in cru for softreset registers + * @reg_number: the reg numbers of softreset registers + * Return: 0 success, or error value + */ +int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number); /* * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device * using dedicated RK3528 lookup table diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3506.h b/arch/arm/include/asm/arch-rockchip/cru_rk3506.h new file mode 100644 index 00000000000..2f79e5eaf09 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3506.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#ifndef _ASM_ARCH_CRU_RK3506_H +#define _ASM_ARCH_CRU_RK3506_H + +#include +#include + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +/* RK3506 pll id */ +enum rk3506_pll_id { + GPLL, + V0PLL, + V1PLL, + PLL_COUNT, +}; + +struct rk3506_clk_priv { + unsigned long gpll_hz; + unsigned long gpll_div_hz; + unsigned long gpll_div_100mhz; + unsigned long v0pll_hz; + unsigned long v0pll_div_hz; + unsigned long v1pll_hz; + unsigned long v1pll_div_hz; +}; + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +#define RK3506_CRU_BASE 0xff9a0000 +#define RK3506_MODE_CON 0x0280 +#define RK3506_CLKSEL_CON(x) (RK3506_CRU_BASE + 0x0300 + (x) * 0x4) +#define RK3506_SOFTRST_CON0 0x0a00 +#define RK3506_GLB_SRST_FST 0x0c08 +#define RK3506_GLB_SRST_SND 0x0c0c +#define RK3506_PLL_CON(x) (0x10000 + (x) * 0x4) +#define RK3506_SCRU_BASE 0xff9a8000 +#define RK3506_PMU_CRU_BASE 0xff9b0000 +#define RK3506_PMU_CLKSEL_CON(x) (RK3506_PMU_CRU_BASE + 0x0300 + (x) * 0x4) + +enum { + /* CRU_CLKSEL_CON00 */ + CLK_GPLL_DIV_MASK = GENMASK(9, 6), + CLK_GPLL_DIV_100M_MASK = GENMASK(13, 10), + + /* CRU_CLKSEL_CON01 */ + CLK_V0PLL_DIV_MASK = GENMASK(3, 0), + CLK_V1PLL_DIV_MASK = GENMASK(7, 4), + + /* CRU_CLKSEL_CON15 */ + CLK_CORE_SRC_DIV_MASK = GENMASK(4, 0), + CLK_CORE_SRC_SEL_MASK = GENMASK(6, 5), + CLK_CORE_SEL_GPLL = 0, + CLK_CORE_SEL_V0PLL, + CLK_CORE_SEL_V1PLL, + + ACLK_CORE_DIV_MASK = GENMASK(12, 9), + + /* CRU_CLKSEL_CON16 */ + PCLK_CORE_DIV_MASK = GENMASK(3, 0), + + /* CRU_CLKSEL_CON21 */ + ACLK_BUS_DIV_MASK = GENMASK(4, 0), + ACLK_BUS_SEL_MASK = GENMASK(6, 5), + ACLK_BUS_SEL_GPLL_DIV = 0, + ACLK_BUS_SEL_V0PLL_DIV, + ACLK_BUS_SEL_V1PLL_DIV, + + HCLK_BUS_DIV_MASK = GENMASK(11, 7), + HCLK_BUS_SEL_MASK = GENMASK(13, 12), + + /* CRU_CLKSEL_CON22 */ + PCLK_BUS_DIV_MASK = GENMASK(4, 0), + PCLK_BUS_SEL_MASK = GENMASK(6, 5), + + /* CRU_CLKSEL_CON29 */ + HCLK_LSPERI_DIV_MASK = GENMASK(4, 0), + HCLK_LSPERI_SEL_MASK = GENMASK(6, 5), + + /* CRU_CLKSEL_CON32 */ + CLK_I2C0_DIV_MASK = GENMASK(3, 0), + CLK_I2C0_SEL_MASK = GENMASK(5, 4), + CLK_I2C_SEL_GPLL = 0, + CLK_I2C_SEL_V0PLL, + CLK_I2C_SEL_V1PLL, + CLK_I2C1_DIV_MASK = GENMASK(9, 6), + CLK_I2C1_SEL_MASK = GENMASK(11, 10), + + /* CRU_CLKSEL_CON33 */ + CLK_I2C2_DIV_MASK = GENMASK(3, 0), + CLK_I2C2_SEL_MASK = GENMASK(5, 4), + CLK_PWM1_DIV_MASK = GENMASK(9, 6), + CLK_PWM1_SEL_MASK = GENMASK(11, 10), + CLK_PWM1_SEL_GPLL_DIV = 0, + CLK_PWM1_SEL_V0PLL_DIV, + CLK_PWM1_SEL_V1PLL_DIV, + + /* CRU_CLKSEL_CON34 */ + CLK_SPI0_DIV_MASK = GENMASK(7, 4), + CLK_SPI0_SEL_MASK = GENMASK(9, 8), + CLK_SPI_SEL_24M = 0, + CLK_SPI_SEL_GPLL_DIV, + CLK_SPI_SEL_V0PLL_DIV, + CLK_SPI_SEL_V1PLL_DIV, + CLK_SPI1_DIV_MASK = GENMASK(13, 10), + CLK_SPI1_SEL_MASK = GENMASK(15, 14), + + /* CRU_CLKSEL_CON49 */ + ACLK_HSPERI_DIV_MASK = GENMASK(4, 0), + ACLK_HSPERI_SEL_MASK = GENMASK(6, 5), + ACLK_HSPERI_SEL_GPLL_DIV = 0, + ACLK_HSPERI_SEL_V0PLL_DIV, + ACLK_HSPERI_SEL_V1PLL_DIV, + + CCLK_SDMMC_DIV_MASK = GENMASK(12, 7), + CCLK_SDMMC_SEL_MASK = GENMASK(14, 13), + CCLK_SDMMC_SEL_24M = 0, + CCLK_SDMMC_SEL_GPLL, + CCLK_SDMMC_SEL_V0PLL, + CCLK_SDMMC_SEL_V1PLL, + + /* CRU_CLKSEL_CON50 */ + SCLK_FSPI_DIV_MASK = GENMASK(4, 0), + SCLK_FSPI_SEL_MASK = GENMASK(6, 5), + SCLK_FSPI_SEL_24M = 0, + SCLK_FSPI_SEL_GPLL, + SCLK_FSPI_SEL_V0PLL, + SCLK_FSPI_SEL_V1PLL, + CLK_MAC_DIV_MASK = GENMASK(11, 7), + + /* CRU_CLKSEL_CON54 */ + CLK_SARADC_DIV_MASK = GENMASK(3, 0), + CLK_SARADC_SEL_MASK = GENMASK(5, 4), + CLK_SARADC_SEL_24M = 0, + CLK_SARADC_SEL_400K, + CLK_SARADC_SEL_32K, + + /* CRU_CLKSEL_CON60 */ + DCLK_VOP_DIV_MASK = GENMASK(7, 0), + DCLK_VOP_SEL_MASK = GENMASK(10, 8), + DCLK_VOP_SEL_24M = 0, + DCLK_VOP_SEL_GPLL, + DCLK_VOP_SEL_V0PLL, + DCLK_VOP_SEL_V1PLL, + DCLK_VOP_SEL_FRAC_VOIC1, + DCLK_VOP_SEL_FRAC_COMMON0, + DCLK_VOP_SEL_FRAC_COMMON1, + DCLK_VOP_SEL_FRAC_COMMON2, + + /* CRU_CLKSEL_CON61 */ + CLK_TSADC_DIV_MASK = GENMASK(7, 0), + CLK_TSADC_TSEN_DIV_MASK = GENMASK(10, 8), + + /* PMUCRU_CLKSEL_CON00 */ + CLK_PWM0_DIV_MASK = GENMASK(9, 6), + CLK_MAC_OUT_DIV_MASK = GENMASK(15, 10), + + /* SCRU_CLKSEL_CON104 */ + CLK_PKA_CRYPTO_DIV_MASK = GENMASK(11, 7), + CLK_PKA_CRYPTO_SEL_MASK = GENMASK(13, 12), + CLK_PKA_CRYPTO_SEL_GPLL = 0, + CLK_PKA_CRYPTO_SEL_V0PLL, + CLK_PKA_CRYPTO_SEL_V1PLL, +}; + +#endif /* _ASM_ARCH_CRU_RK3506_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h index a5fc6ad3656..01f2214cd15 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h @@ -205,6 +205,8 @@ struct dram_para { uint32_t mr12; uint32_t mr13; uint32_t mr14; + uint32_t mr22; + uint32_t tpr0; uint32_t tpr1; uint32_t tpr2; uint32_t tpr3; diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index a399c94213b..8c38c71c93a 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -68,6 +68,7 @@ struct timerus { /* These are the available SKUs (product types) for Tegra */ enum { + SKU_ID_T20_A04 = 0x4, /* Sony Tablet P value */ SKU_ID_AP20 = 0x7, SKU_ID_T20 = 0x8, SKU_ID_AP20H = 0xf, diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index 439e43c2d01..762f00e6900 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -8,8 +8,6 @@ #ifndef ARM_BOOTM_H #define ARM_BOOTM_H -extern void udc_disconnect(void); - #ifdef CONFIG_SUPPORT_PASSING_ATAGS # define BOOTM_ENABLE_TAGS 1 #else diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 4e1afc42bd8..04e7f20a2a6 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -49,6 +49,7 @@ #define ELE_ATTEST_REQ (0xDB) #define ELE_RELEASE_PATCH_REQ (0xDC) #define ELE_OTP_SEQ_SWITH_REQ (0xDD) +#define ELE_SET_GMID_REQ (0xE4) #define ELE_WRITE_SHADOW_REQ (0xF2) #define ELE_READ_SHADOW_REQ (0xF3) @@ -162,6 +163,7 @@ int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); int ele_start_rng(void); int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response); int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); +int ele_set_gmid(u32 *response); int ele_volt_change_start_req(void); int ele_volt_change_finish_req(void); #endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 46da7a1eff5..ab573413128 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -99,6 +99,7 @@ struct bd_info; #define is_imx94() (is_cpu_type(MXC_CPU_IMX94)) #define is_imx95() (is_cpu_type(MXC_CPU_IMX95)) +#define is_imx952() (is_cpu_type(MXC_CPU_IMX952)) #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121)) #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111)) @@ -254,6 +255,43 @@ struct scmi_rom_passover_get_out { u32 passover[(sizeof(rom_passover_t) + 8) / 4]; }; +/** + * struct scmi_ddr_info_out - Get DDR memory region info + * @status: Error code + * @attributes: Region attributes: + * Bit[31] ECC enable. + * Set to 1 if ECC enabled. + * Set to 0 if ECC disabled or not configured. + * Bits[30:18] Reserved, must be zero. + * Bits[17:16] Number of DDR memory regions. + * Bits[15:11] Reserved, must be zero. + * Bits[10:8] Width. + * Bus width is 16 << this field. + * So 0=16, 1=32, 2=64, etc. + * Bits[7:5] Reserved, must be zero. + * Bits[4:0] DDR type. + * Set to 0 if LPDDR5. + * Set to 1 if LPDDR5X. + * Set to 2 if LPDDR4. + * Set to 3 if LPDDR4X + * @mts: DDR speed in megatransfers per second + * @startlow: The lower 32 bits of the physical start address of the region + * @starthigh: The upper 32 bits of the physical start address of the region + * @endlow: The lower 32 bits of the physical end address of the region. This + * excludes any DDR used to store ECC data + * @endhigh: The upper 32 bits of the physical end address of the region. This + * excludes any DDR used to store ECC data + */ +struct scmi_ddr_info_out { + s32 status; + u32 attributes; + u32 mts; + u32 startlow; + u32 starthigh; + u32 endlow; + u32 endhigh; +}; + #endif /* For i.MX ULP */ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index ee79a19c05c..dd462ea6ad8 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -30,6 +30,7 @@ enum { BOOT_DEVICE_XIP, BOOT_DEVICE_BOOTROM, BOOT_DEVICE_SMH, + BOOT_DEVICE_UFS, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4c1b81483c9..9e3ad57073d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -171,6 +171,12 @@ static inline unsigned int current_el(void) return 3 & (el >> 2); } +static inline unsigned int current_pl(void) +{ + /* Aarch32 compatibility */ + return current_el(); +}; + static inline unsigned long get_sctlr(void) { unsigned int el; @@ -466,6 +472,39 @@ static inline int is_hyp(void) #endif } +static inline int is_usr(void) +{ + return (get_cpsr() & 0x1f) == 0x10; +} + +static inline unsigned int current_pl(void) +{ + /* + * ARM DDI 0406C.d ID040418 , page 140 chapter A3.6.1 "Processor + * privilege levels, execution privilege, and access privilege", + * clarifies the PLx levels as follows (abbreviated): + * The characteristics of the privilege levels are: + * - PL0 - The privilege level of application software, that + * executes in User mode. + * - PL1 - Software execution in all modes other than User mode + * and Hyp mode is at PL1. + * - PL2 - Software executing in Hyp mode executes at PL2. + */ + if (is_hyp()) /* HYP */ + return 2; + + if (is_usr()) /* USR */ + return 0; + + return 1; /* The rest */ +} + +static inline unsigned int current_el(void) +{ + /* Aarch64 compatibility */ + return current_pl(); +}; + static inline unsigned int get_cr(void) { unsigned int val; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 019eca95780..727b9c5ca5b 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -42,42 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; -__weak void board_quiesce_devices(void) -{ -} - -/** - * announce_and_cleanup() - Print message and prepare for kernel boot - * - * @fake: non-zero to do everything except actually boot - */ -static void announce_and_cleanup(int fake) -{ - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_FDT - bootstage_fdt_add_report(); -#endif - bootstage_stash_default(); -#ifdef CONFIG_BOOTSTAGE_REPORT - bootstage_report(); -#endif - - board_quiesce_devices(); - - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - /* - * Call remove function of all devices with a removal flag set. - * This may be useful for last-stage operations, like cancelling - * of DMA operation or releasing device internal buffers. - * dm_remove_devices_active() ensures that vital devices are removed in - * a second round. - */ - dm_remove_devices_active(); - - cleanup_before_linux(); -} - static void setup_start_tag (struct bd_info *bd) { params = (struct tag *)bd->bi_boot_params; @@ -294,8 +258,6 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*kernel_entry)(void *fdt_addr, void *res0, void *res1, void *res2); - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - kernel_entry = (void (*)(void *fdt_addr, void *res0, void *res1, void *res2))images->ep; @@ -303,9 +265,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) (ulong) kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - announce_and_cleanup(fake); + bootm_final(flag); + cleanup_before_linux(); - if (!fake) { + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) { #ifdef CONFIG_ARMV8_PSCI armv8_setup_psci(); #endif @@ -340,8 +303,6 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) char *s; void (*kernel_entry)(int zero, int arch, uint params); unsigned long r2; - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - kernel_entry = (void (*)(int, int, uint))images->ep; #ifdef CONFIG_CPU_V7M ulong addr = (ulong)kernel_entry | 1; @@ -366,14 +327,15 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) debug("## Transferring control to Linux (at address %08lx)" \ "...\n", (ulong) kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - announce_and_cleanup(fake); + bootm_final(flag); + cleanup_before_linux(); if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) r2 = (unsigned long)images->ft_addr; else r2 = gd->bd->bi_boot_params; - if (fake) + if (flag & BOOTM_STATE_OS_FAKE_GO) return; #ifdef CONFIG_ARMV7_NONSEC diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index d10c129705d..f2c5aa37a8f 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -157,7 +157,11 @@ ENTRY(_main) orr lr, #1 /* As required by Thumb-only */ #endif ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ +#if defined(CONFIG_SKIP_RELOCATE_CODE) + bl relocate_code +#else b relocate_code +#endif here: /* * now relocate vectors diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index bffadfecba1..b6a648708f4 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -79,6 +79,15 @@ ENDPROC(relocate_vectors) ENTRY(relocate_code) relocate_base: adr r3, relocate_base + +#ifdef CONFIG_SKIP_RELOCATE_CODE + mov r4, #CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET + + ldr r1, _data_start_ofs + add r5, r1, r3 /* r5 <- Run &__data_start */ + ldr r1, _data_end_ofs + add r6, r1, r3 /* r6 <- Run &__data_end */ +#else ldr r1, _image_copy_start_ofs add r1, r3 /* r1 <- Run &__image_copy_start */ subs r4, r0, r1 /* r4 <- Run to copy offset */ @@ -90,6 +99,7 @@ copy_loop: stmia r0!, {r10-r11} /* copy to target address [r0] */ cmp r1, r2 /* until source end address [r2] */ blo copy_loop +#endif /* * fix .rel.dyn relocations @@ -107,6 +117,15 @@ fixloop: /* relative fix: increase location by offset */ add r0, r0, r4 ldr r1, [r0] + +#ifdef CONFIG_SKIP_RELOCATE_CODE + /* Test whether this is data, if not, do not relocate. */ + cmp r1, r5 + blt fixnext + cmp r1, r6 + bgt fixnext +#endif + add r1, r1, r4 str r1, [r0] fixnext: @@ -114,16 +133,6 @@ fixnext: blo fixloop relocate_done: - -#ifdef __XSCALE__ - /* - * On xscale, icache must be invalidated and write buffers drained, - * even with cache disabled - 4.2.7 of xscale core developer's manual - */ - mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ -#endif - ret lr ENDPROC(relocate_code) @@ -136,3 +145,9 @@ _rel_dyn_start_ofs: .word __rel_dyn_start - relocate_code _rel_dyn_end_ofs: .word __rel_dyn_end - relocate_code +#ifdef CONFIG_SKIP_RELOCATE_CODE +_data_start_ofs: + .word __data_start - relocate_code +_data_end_ofs: + .word __data_end - relocate_code +#endif diff --git a/arch/arm/mach-airoha/Kconfig b/arch/arm/mach-airoha/Kconfig index b9cd0a413e1..4b0374001d0 100644 --- a/arch/arm/mach-airoha/Kconfig +++ b/arch/arm/mach-airoha/Kconfig @@ -10,6 +10,7 @@ config TARGET_EN7523 bool "Airoha EN7523 SoC" select CPU_V7A select ARMV7_SET_CORTEX_SMPEN + select REGMAP help The Airoha EN7523 family (en7523/en7529/en7562) is an ARM-based SoCs with a dual-core CPU. It comes with Wi-Fi 5/6 support and diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index 9cf60378c11..c88b1e59366 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -18,6 +18,7 @@ config ASPEED_AST2500 bool "Support Aspeed AST2500 SoC" select CPU_ARM1176 select DM_RESET + select REGMAP help The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. It is used as Board Management Controller on many server boards, diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 0c5a82ed094..60f2c5d291e 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -9,9 +9,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong dummy) { diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 0f6e737c0b9..bf6820de655 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,7 +223,7 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) -ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),) +ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94),$(CONFIG_IMX952))),) SPL: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 20c741283cd..8af45e14707 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -310,7 +310,8 @@ void arch_preboot_os(void) /* disable video before launching O/S */ rc = uclass_find_first_device(UCLASS_VIDEO, &dev); while (!rc && dev) { - ipuv3_fb_shutdown(dev); + if (device_active(dev)) + ipuv3_fb_shutdown(dev); uclass_find_next_device(&dev); } #endif diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 4d4620dcafd..9794391fb35 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -412,7 +412,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } -#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) +#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) || IS_ENABLED(CONFIG_IMX952) #define FSB_LC_OFFSET 0x414 #define LC_OEM_OPEN 0x10 static void display_life_cycle(u32 lc) diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 78f2488cf6d..7bfcc9d7e9d 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -297,7 +297,7 @@ static ulong get_imageset_end(void *dev, int dev_type) debug("seco container size 0x%x\n", value_container[0]); - if (is_imx95() || is_imx94()) { + if (is_imx95() || is_imx94() || is_imx952()) { offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw); @@ -321,7 +321,7 @@ static ulong get_imageset_end(void *dev, int dev_type) value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL); if (value_container[2] < 0) { debug("Parse scu container image failed %d, only seco container\n", value_container[2]); - if (is_imx95() || is_imx94()) + if (is_imx95() || is_imx94() || is_imx952()) return value_container[1] + offset[1]; /* return seco + v2x container total size */ else return value_container[0] + offset[0]; /* return seco container total size */ diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 4e49b5bf375..e37d3bf31e4 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -3,12 +3,9 @@ * Copyright 2018 NXP */ -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 0e112af661c..f4738e3fda8 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -899,3 +899,24 @@ bool m4_parts_booted(void) return false; } + +#ifdef CONFIG_IMX8QXP +#include + +/* + * On B0 revision SoCs the bootloader is on 32k offset + * and at offset 0x0 is the U-Boot Environment stored + * + * So we cannot flash bootloader images to offset 0x0 + * + * On C0 revisions of the SoC bootloader image starts + * at offset 0x0 ... + */ +lbaint_t fb_mmc_get_boot_offset(void) +{ + if ((get_cpu_rev() & 0xF) < CHIP_REV_C) + return 0x40; + + return 0; +} +#endif diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index ce78c8ce919..8337edc2f62 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -14,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static bool check_owned_resource(sc_rsrc_t rsrc_id) { bool owned; diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c index 3e27d75827a..b6175a50226 100644 --- a/arch/arm/mach-imx/imx8/iomux.c +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -4,13 +4,10 @@ */ #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * configures a single pad in the iomuxer */ diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index c77104d0338..22d6959f74f 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include +#include #include #include #include @@ -62,3 +64,34 @@ void build_info(void) printf("Build: SCFW %08x, SECO-FW %08x, ATF %s\n", sc_commit, seco_commit, (char *)&atf_commit); } + +int do_boottype(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + sc_misc_bt_t boot_type; + + if (argc > 2) + return CMD_RET_USAGE; + + if (sc_misc_get_boot_type(-1, &boot_type) != 0) { + puts("boottype cannot be retrieved\n"); + return CMD_RET_FAILURE; + } + + if (argc > 1) + printf("Boottype: %d\n", boot_type); + + env_set_ulong("boottype", boot_type); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(boottype, CONFIG_SYS_MAXARGS, 2, do_boottype, + "save current boot-container in env variable 'boottype'", + "possible values for boottype:\n" + "0: SC_MISC_BT_PRIMARY\n" + "1: SC_MISC_BT_SECONDARY\n" + "2: SC_MISC_BT_RECOVERY\n" + "3: SC_MISC_BT_MANUFACTURE\n" + "4: SC_MISC_BT_SERIAL\n" + "[print] - print current boottype" +); diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 77c8efc7899..b7b3702041e 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; static u32 get_root_clk(enum clk_root_index clock_id); diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index f9d8ed5b048..69585a3605b 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct cgc1_regs *cgc1_regs = (struct cgc1_regs *)0x292C0000UL; static struct cgc2_regs *cgc2_regs = (struct cgc2_regs *)0x2da60000UL; diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index c390f20d769..1b5cbd56f50 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -12,11 +12,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) #define PLL_USB_PWR_MASK (0x01 << 12) #define PLL_USB_ENABLE_MASK (0x01 << 13) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index d9f97e4328c..2308457df23 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -47,6 +47,15 @@ config IMX94 select SCMI_FIRMWARE select SPL_IMX_CONTAINER_USE_TRAMPOLINE +config IMX952 + bool + select ARMV8_SPL_EXCEPTION_VECTORS + select DM_MAILBOX + select IMX9 + select IMX_PQC_SUPPORT + select SCMI_FIRMWARE + select SPL_IMX_CONTAINER_USE_TRAMPOLINE + config SYS_SOC default "imx9" @@ -120,6 +129,14 @@ config TARGET_KONTRON_MX93 Kontron Electronics BL i.MX93 using SoM module conformant to OSM standard 1.1 size S. +config TARGET_PHYCORE_IMX91 + bool "phycore_imx91" + select IMX91 + select IMX9_LPDDR4X + imply OF_UPSTREAM + select OF_BOARD_FIXUP + select OF_BOARD_SETUP + config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 @@ -152,6 +169,18 @@ config TARGET_IMX943_EVK config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 + imply OF_UPSTREAM + +config TARGET_IMX952_EVK + bool "imx952_evk" + select IMX_SM_CPU + select IMX_SM_LMM + select IMX952 + select REGMAP + select SYSCON + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM endchoice @@ -161,10 +190,11 @@ source "board/nxp/imx93_evk/Kconfig" source "board/nxp/imx93_frdm/Kconfig" source "board/nxp/imx93_qsb/Kconfig" source "board/kontron/osm-s-mx93/Kconfig" -source "board/phytec/phycore_imx93/Kconfig" +source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" source "board/toradex/smarc-imx95/Kconfig" +source "board/nxp/imx952_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index e65cabef2c9..14a2bdf5762 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; static struct imx_intpll_rate_table imx9_intpll_tbl[] = { diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 5dbc398e97f..acf79a40584 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -11,11 +11,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; static enum ccm_clk_src clk_root_mux[][4] = { diff --git a/arch/arm/mach-imx/imx9/scmi/common.h b/arch/arm/mach-imx/imx9/scmi/common.h index dd4675402c7..c3610127dce 100644 --- a/arch/arm/mach-imx/imx9/scmi/common.h +++ b/arch/arm/mach-imx/imx9/scmi/common.h @@ -21,6 +21,16 @@ #define IMX95_PD_M70 IMX95_PD_M7 #endif +#ifdef CONFIG_IMX952 +#define IMX_PLAT 952 +#include +#include + +#define IMX952_CLK_SEL_A55C0 IMX952_CLK_GPR_SEL_A55C0 +#define IMX952_PD_M70 IMX952_PD_M7 +#define IMX952_CLK_FLEXSPI1 IMX952_CLK_XSPI1 +#define IMX952_CLK_24M IMX952_CLK_OSC24M +#endif #define IMX_PLAT_STR__(plat) # plat #define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT) diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index c1458ccca3c..fbee435786c 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -58,6 +58,34 @@ uint32_t scmi_get_rom_data(rom_passover_t *rom_data) return 0; } +int scmi_misc_ddrinfo(u32 ddrc_id, struct scmi_ddr_info_out *out) +{ + u32 in = ddrc_id; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_MISC_DDR_INFO_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)out, + .out_msg_sz = sizeof(*out), + }; + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret != 0 || out->status != 0) { + printf("Failed to get ddr cfg, scmi_err = %d\n", + out->status); + return -EINVAL; + } + + return 0; +} + #if IS_ENABLED(CONFIG_ENV_IS_IN_MMC) __weak int board_mmc_get_env_dev(int devno) { @@ -125,6 +153,8 @@ u32 get_cpu_speed_grade_hz(void) if (is_imx95()) max_speed = 2000000000; + if (is_imx952()) + max_speed = 1700000000; /* In case the fuse of speed grade not programmed */ if (speed > max_speed) @@ -335,25 +365,44 @@ void enable_caches(void) __weak int board_phys_sdram_size(phys_size_t *size) { + struct scmi_ddr_info_out ddr_info = {0}; + int ret; + u32 ddrc_id = 0, ddrc_num = 1; phys_size_t start, end; - phys_size_t val; if (!size) return -EINVAL; - val = readl(REG_DDR_CS0_BNDS); - start = (val >> 16) << 24; - end = (val & 0xFFFF); - end = end ? end + 1 : 0; - end = end << 24; - *size = end - start; + *size = 0; + do { + ret = scmi_misc_ddrinfo(ddrc_id++, &ddr_info); + if (ret) { + /* if get DDR info failed, fall to default config */ + *size = PHYS_SDRAM_SIZE; +#ifdef PHYS_SDRAM_2_SIZE + *size += PHYS_SDRAM_2_SIZE; +#endif + return 0; + } else { + ddrc_num = ((ddr_info.attributes >> 16) & 0x3); + start = ddr_info.starthigh; + start <<= 32; + start += ddr_info.startlow; - val = readl(REG_DDR_CS1_BNDS); - start = (val >> 16) << 24; - end = (val & 0xFFFF); - end = end ? end + 1 : 0; - end = end << 24; - *size += end - start; + end = ddr_info.endhigh; + end <<= 32; + end += ddr_info.endlow; + + *size += end + 1 - start; + + debug("ddr info attr 0x%x, start 0x%x 0x%x, end 0x%x 0x%x, mts %u\n", + ddr_info.attributes, ddr_info.starthigh, ddr_info.startlow, + ddr_info.endhigh, ddr_info.endlow, ddr_info.mts); + } + } while (ddrc_id < ddrc_num); + + /* SM reports total DDR size, need remove secure memory */ + *size -= PHYS_SDRAM - 0x80000000; return 0; } @@ -737,8 +786,10 @@ static void gpio_reset(ulong gpio_base) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { - disable_wdog((void __iomem *)WDG3_BASE_ADDR); - disable_wdog((void __iomem *)WDG4_BASE_ADDR); + if (!IS_ENABLED(CONFIG_IMX952)) { + disable_wdog((void __iomem *)WDG3_BASE_ADDR); + disable_wdog((void __iomem *)WDG4_BASE_ADDR); + } gpio_reset(GPIO2_BASE_ADDR); gpio_reset(GPIO3_BASE_ADDR); @@ -820,7 +871,7 @@ int timer_init(void) return 0; } -enum env_location env_get_location(enum env_operation op, int prio) +enum env_location arch_env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); enum env_location env_loc = ENVL_UNKNOWN; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 583c3a5a464..44b3e0f5310 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -664,7 +664,8 @@ int low_drive_freq_update(void *blob) return 0; } -#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) +#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) && \ + !defined(CONFIG_TARGET_PHYCORE_IMX91) #ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index 7452b82f110..90d91b2300a 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -6,14 +6,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* 1 second delay should be plenty of time for block reset. */ #define RESET_MAX_TIMEOUT 1000000 diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index f64bebfc14b..d198d9932f4 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -120,7 +120,7 @@ config TARGET_APALIS_IMX6 select DM_THERMAL select SUPPORT_SPL imply CMD_DM - imply CMD_SATA + imply SATA config TARGET_ARISTAINETOS2C bool "Support aristainetos2-revC" @@ -130,7 +130,7 @@ config TARGET_ARISTAINETOS2C select MXC_UART select FEC_MXC select DM - imply CMD_SATA + imply SATA imply CMD_DM config TARGET_ARISTAINETOS2CCSLB @@ -141,7 +141,7 @@ config TARGET_ARISTAINETOS2CCSLB select MXC_UART select FEC_MXC select DM - imply CMD_SATA + imply SATA imply CMD_DM config TARGET_CM_FX6 @@ -230,7 +230,7 @@ config TARGET_GW_VENTANA select SUPPORT_SPL select GATEWORKS_SC select MISC - imply CMD_SATA + imply SATA imply CMD_SPL config TARGET_KONTRON_MX6UL @@ -419,7 +419,6 @@ config TARGET_MX6SXSABRESD config TARGET_MX6SXSABREAUTO bool "mx6sxsabreauto" depends on MX6SX - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM select DM_THERMAL diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index b7008df8e35..d36536e600e 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -7,13 +7,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Caller need ensure the offset and size to align with page size */ ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf) { diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 1b8c0b1eb96..a32ed3a9683 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -130,6 +130,15 @@ config K3_ATF_LOAD_ADDR The load address for the ATF image. This value is used to build the FIT image header that places ATF in memory where it will run. +config K3_ATF_RESERVED_SIZE + hex "Reserved memory size for ATF" + default 0x80000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S) + default 0x20000 + help + The runtime memory size reserved for ATF. This value is used to fixup the + kernel device-tree's reserved-memory node for ATF and configure the + firewall. + config K3_OPTEE_LOAD_ADDR hex "Load address of OPTEE image" default 0x9e800000 @@ -137,6 +146,14 @@ config K3_OPTEE_LOAD_ADDR The load address for the OPTEE image. This value defaults to 0x9e800000 if not provided in the board defconfig file. +config K3_OPTEE_RESERVED_SIZE + hex "Reserved memory size for OPTEE" + default 0x1800000 + help + The runtime memory size reserved for OPTEE. This value is used to fixup + the kernel device-tree's reserved-memory node for OPTEE and configure the + firewall. + config K3_DM_FW bool "Separate DM firmware image" depends on CPU_V7R && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 2f3df5519c5..b0a75988714 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -457,6 +457,83 @@ static __maybe_unused void k3_dma_remove(void) pr_warn("DMA Device not found (err=%d)\n", rc); } +static int k3_falcon_fdt_add_bootargs(void *fdt) +{ + struct disk_partition info; + struct blk_desc *dev_desc; + char bootmedia[32]; + char bootpart[32]; + char str[256]; + int ret; + + strlcpy(bootmedia, env_get("boot"), sizeof(bootmedia)); + strlcpy(bootpart, env_get("bootpart"), sizeof(bootpart)); + ret = blk_get_device_part_str(bootmedia, bootpart, &dev_desc, &info, 0); + if (ret < 0) { + printf("%s: Failed to get part details for %s %s [%d]\n", + __func__, bootmedia, bootpart, ret); + return ret; + } + + if (!CONFIG_IS_ENABLED(PARTITION_UUIDS)) { + printf("ERROR: Failed to find rootfs PARTUUID\n"); + printf("%s: CONFIG_SPL_PARTITION_UUIDS not enabled\n", + __func__); + return -EOPNOTSUPP; + } + + snprintf(str, sizeof(str), "console=%s root=PARTUUID=%s rootwait", + env_get("console"), disk_partition_uuid(&info)); + + ret = fdt_find_and_setprop(fdt, "/chosen", "bootargs", str, + strlen(str) + 1, 1); + if (ret) { + printf("%s: Could not set bootargs: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + + debug("%s: Set bootargs to: %s\n", __func__, str); + return 0; +} + +int k3_falcon_fdt_fixup(void *fdt) +{ + int ret; + + if (!fdt) + return -EINVAL; + + fdt_set_totalsize(fdt, fdt_totalsize(fdt) + CONFIG_SYS_FDT_PAD); + + if (fdt_path_offset(fdt, "/chosen/bootargs") < 0) { + ret = k3_falcon_fdt_add_bootargs(fdt); + + if (ret) + return ret; + } + + if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) { + ret = ft_board_setup(fdt, gd->bd); + if (ret) { + printf("%s: Failed in board setup: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + } + + if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) { + ret = ft_system_setup(fdt, gd->bd); + if (ret) { + printf("%s: Failed in system setup: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + } + + return 0; +} + void spl_perform_arch_fixups(struct spl_image_info *spl_image) { void *fdt = spl_image_fdt_addr(spl_image); @@ -465,6 +542,9 @@ void spl_perform_arch_fixups(struct spl_image_info *spl_image) return; fdt_fixup_reserved(fdt); + + if (IS_ENABLED(CONFIG_SPL_OS_BOOT)) + k3_falcon_fdt_fixup(fdt); } void spl_board_prepare_for_boot(void) diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index e970076d08e..466ad22f895 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -61,10 +61,13 @@ void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); int shutdown_mcu_r5_core1(void); -#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) +int k3_falcon_fdt_fixup(void *fdt); +#if !IS_ENABLED(CONFIG_ARM64) int k3_r5_falcon_bootmode(void); int k3_r5_falcon_prep(void); #endif +#endif #if (IS_ENABLED(CONFIG_K3_QOS)) void setup_qos(void); diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index cb0fb8274a5..39cb00c3f43 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -173,12 +173,13 @@ int fdt_fixup_reserved(void *blob) int ret; ret = fdt_fixup_reserved_memory(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, - 0x80000); + CONFIG_K3_ATF_RESERVED_SIZE); if (ret) return ret; return fdt_fixup_reserved_memory(blob, "optee", - CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); + CONFIG_K3_OPTEE_LOAD_ADDR, + CONFIG_K3_OPTEE_RESERVED_SIZE); } static int fdt_fixup_critical_trips(void *blob, int zoneoffset, int maxc) diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 03638366046..484d96f9536 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -406,83 +406,6 @@ int k3_r5_falcon_bootmode(void) return BOOT_DEVICE_NOBOOT; } -static int k3_falcon_fdt_add_bootargs(void *fdt) -{ - struct disk_partition info; - struct blk_desc *dev_desc; - char bootmedia[32]; - char bootpart[32]; - char str[256]; - int ret; - - strlcpy(bootmedia, env_get("boot"), sizeof(bootmedia)); - strlcpy(bootpart, env_get("bootpart"), sizeof(bootpart)); - ret = blk_get_device_part_str(bootmedia, bootpart, &dev_desc, &info, 0); - if (ret < 0) { - printf("%s: Failed to get part details for %s %s [%d]\n", - __func__, bootmedia, bootpart, ret); - return ret; - } - - if (!CONFIG_IS_ENABLED(PARTITION_UUIDS)) { - printf("ERROR: Failed to find rootfs PARTUUID\n"); - printf("%s: CONFIG_SPL_PARTITION_UUIDS not enabled\n", - __func__); - return -EOPNOTSUPP; - } - - snprintf(str, sizeof(str), "console=%s root=PARTUUID=%s rootwait", - env_get("console"), disk_partition_uuid(&info)); - - ret = fdt_find_and_setprop(fdt, "/chosen", "bootargs", str, - strlen(str) + 1, 1); - if (ret) { - printf("%s: Could not set bootargs: %s\n", __func__, - fdt_strerror(ret)); - return ret; - } - - debug("%s: Set bootargs to: %s\n", __func__, str); - return 0; -} - -static int k3_falcon_fdt_fixup(void *fdt) -{ - int ret; - - if (!fdt) - return -EINVAL; - - fdt_set_totalsize(fdt, fdt_totalsize(fdt) + CONFIG_SYS_FDT_PAD); - - if (fdt_path_offset(fdt, "/chosen/bootargs") < 0) { - ret = k3_falcon_fdt_add_bootargs(fdt); - - if (ret) - return ret; - } - - if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) { - ret = ft_board_setup(fdt, gd->bd); - if (ret) { - printf("%s: Failed in board setup: %s\n", __func__, - fdt_strerror(ret)); - return ret; - } - } - - if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) { - ret = ft_system_setup(fdt, gd->bd); - if (ret) { - printf("%s: Failed in system setup: %s\n", __func__, - fdt_strerror(ret)); - return ret; - } - } - - return 0; -} - int k3_r5_falcon_prep(void) { struct spl_image_loader *loader, *drv; diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 24780eb6562..228b424d3f2 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -64,13 +64,13 @@ static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { "board_0_cpts0_rft_clk_out", "board_0_mcu_ext_refclk0_out", "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", NULL, NULL, - NULL, - NULL, - NULL, - NULL, - NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", NULL, "hsdiv4_16fft_mcu_2_hsdivout1_clk", "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", @@ -166,6 +166,31 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { "board_0_mmc1_clk_out", }; +static const char * const usb0_serdes_refclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_refclk", + NULL, +}; + +static const char * const usb0_serdes_rxclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_rxclk", + NULL, +}; + +static const char * const usb0_serdes_rxfclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_rxfclk", + NULL, +}; + +static const char * const usb0_serdes_txfclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_txfclk", + NULL, +}; + +static const char * const usb0_serdes_txmclk_mux_out0_parents[] = { + "wiz16b8m4ct3_main_0_ip3_ln3_txmclk", + NULL, +}; + static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "main_pll_hfosc_sel_out0", "hsdiv4_16fft_main_0_hsdivout0_clk", @@ -197,18 +222,44 @@ static const char * const gtc_clk_mux_out0_parents[] = { "board_0_cpts0_rft_clk_out", "board_0_mcu_ext_refclk0_out", "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", NULL, NULL, - NULL, - NULL, - NULL, - NULL, - NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", NULL, "hsdiv4_16fft_mcu_2_hsdivout1_clk", "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; +static const char * const pcien_cpts_rclk_mux_out1_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "wiz16b8m4ct3_main_0_ip2_ln0_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln1_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln2_txmclk", + "wiz16b8m4ct3_main_0_ip2_ln3_txmclk", + NULL, + NULL, + "wiz16b8m4ct3_main_0_ip1_ln2_txmclk", + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const serdes0_core_refclk_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", + "hsdiv4_16fft_main_3_hsdivout4_clk", + "hsdiv4_16fft_main_2_hsdivout4_clk", +}; + static const struct clk_data clk_list[] = { CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), @@ -270,11 +321,17 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_serdes0_refclk_n_out", 0, 0), + CLK_FIXED_RATE("board_0_serdes0_refclk_p_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane0_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane1_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane2_txclk", 0, 0), + CLK_FIXED_RATE("pcie_g3x4_128_main_1_pcie_lane3_txclk", 0, 0), CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0, 2000000000), CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), @@ -294,8 +351,42 @@ static const struct clk_data clk_list[] = { CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), + CLK_FIXED_RATE("usb3p0ss_16ffc_main_0_pipe_txclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_cmn_refclk_m", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_cmn_refclk_p", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip1_ln2_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln0_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln1_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln2_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip2_ln3_txmclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_refclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_rxclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_rxfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_txfclk", 0, 0), + CLK_FIXED_RATE("wiz16b8m4ct3_main_0_ip3_ln3_txmclk", 0, 0), CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_MUX("usb0_serdes_refclk_mux_out0", usb0_serdes_refclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_rxclk_mux_out0", usb0_serdes_rxclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_rxfclk_mux_out0", usb0_serdes_rxfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_txfclk_mux_out0", usb0_serdes_txfclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), + CLK_MUX("usb0_serdes_txmclk_mux_out0", usb0_serdes_txmclk_mux_out0_parents, 2, 0x104000, 27, 1, 0), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_27_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_27_foutvcop_clk", 0x69b080, 0, 7, 0, 0), @@ -310,14 +401,18 @@ static const struct clk_data clk_list[] = { CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682090, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683090, 0, 7, 0, 0), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0), CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_MUX("pcien_cpts_rclk_mux_out1", pcien_cpts_rclk_mux_out1_parents, 16, 0x108084, 0, 4, 0), + CLK_MUX("serdes0_core_refclk_out0", serdes0_core_refclk_out0_parents, 4, 0x108400, 0, 2, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), @@ -338,6 +433,11 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(61, 4, "board_0_cpts0_rft_clk_out"), DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(61, 8, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(61, 9, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(61, 10, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(61, 13, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -349,6 +449,11 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"), DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"), DEV_CLK(63, 9, "board_0_ext_refclk1_out"), + DEV_CLK(63, 10, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(63, 11, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(63, 12, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(63, 13, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(63, 16, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), @@ -404,6 +509,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 324, "wiz16b8m4ct3_main_0_cmn_refclk_m"), + DEV_CLK(157, 326, "wiz16b8m4ct3_main_0_cmn_refclk_p"), DEV_CLK(157, 354, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 359, "dpi0_ext_clksel_out0"), DEV_CLK(157, 360, "mshsi2c_wkup_0_porscl"), @@ -461,6 +568,42 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(279, 2, "wkup_i2c_mcupll_bypass_out0"), DEV_CLK(279, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), DEV_CLK(279, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(333, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(333, 2, "pcien_cpts_rclk_mux_out1"), + DEV_CLK(333, 3, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(333, 4, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(333, 5, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(333, 6, "board_0_cpts0_rft_clk_out"), + DEV_CLK(333, 7, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(333, 8, "board_0_ext_refclk1_out"), + DEV_CLK(333, 9, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(333, 10, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(333, 11, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(333, 12, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(333, 15, "wiz16b8m4ct3_main_0_ip1_ln2_txmclk"), + DEV_CLK(333, 17, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(333, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(333, 19, "wiz16b8m4ct3_main_0_ip2_ln0_refclk"), + DEV_CLK(333, 20, "wiz16b8m4ct3_main_0_ip2_ln0_rxclk"), + DEV_CLK(333, 21, "wiz16b8m4ct3_main_0_ip2_ln0_rxfclk"), + DEV_CLK(333, 23, "wiz16b8m4ct3_main_0_ip2_ln0_txfclk"), + DEV_CLK(333, 24, "wiz16b8m4ct3_main_0_ip2_ln0_txmclk"), + DEV_CLK(333, 25, "wiz16b8m4ct3_main_0_ip2_ln1_refclk"), + DEV_CLK(333, 26, "wiz16b8m4ct3_main_0_ip2_ln1_rxclk"), + DEV_CLK(333, 27, "wiz16b8m4ct3_main_0_ip2_ln1_rxfclk"), + DEV_CLK(333, 29, "wiz16b8m4ct3_main_0_ip2_ln1_txfclk"), + DEV_CLK(333, 30, "wiz16b8m4ct3_main_0_ip2_ln1_txmclk"), + DEV_CLK(333, 31, "wiz16b8m4ct3_main_0_ip2_ln2_refclk"), + DEV_CLK(333, 32, "wiz16b8m4ct3_main_0_ip2_ln2_rxclk"), + DEV_CLK(333, 33, "wiz16b8m4ct3_main_0_ip2_ln2_rxfclk"), + DEV_CLK(333, 35, "wiz16b8m4ct3_main_0_ip2_ln2_txfclk"), + DEV_CLK(333, 36, "wiz16b8m4ct3_main_0_ip2_ln2_txmclk"), + DEV_CLK(333, 37, "wiz16b8m4ct3_main_0_ip2_ln3_refclk"), + DEV_CLK(333, 38, "wiz16b8m4ct3_main_0_ip2_ln3_rxclk"), + DEV_CLK(333, 39, "wiz16b8m4ct3_main_0_ip2_ln3_rxfclk"), + DEV_CLK(333, 41, "wiz16b8m4ct3_main_0_ip2_ln3_txfclk"), + DEV_CLK(333, 42, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), + DEV_CLK(333, 43, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"), DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"), @@ -473,11 +616,36 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"), DEV_CLK(398, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(398, 4, "usb0_serdes_refclk_mux_out0"), + DEV_CLK(398, 5, "wiz16b8m4ct3_main_0_ip3_ln3_refclk"), + DEV_CLK(398, 7, "usb0_serdes_rxclk_mux_out0"), + DEV_CLK(398, 8, "wiz16b8m4ct3_main_0_ip3_ln3_rxclk"), + DEV_CLK(398, 10, "usb0_serdes_rxfclk_mux_out0"), + DEV_CLK(398, 11, "wiz16b8m4ct3_main_0_ip3_ln3_rxfclk"), + DEV_CLK(398, 14, "usb0_serdes_txfclk_mux_out0"), + DEV_CLK(398, 15, "wiz16b8m4ct3_main_0_ip3_ln3_txfclk"), + DEV_CLK(398, 17, "usb0_serdes_txmclk_mux_out0"), + DEV_CLK(398, 18, "wiz16b8m4ct3_main_0_ip3_ln3_txmclk"), DEV_CLK(398, 20, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 21, "usb0_refclk_sel_out0"), DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"), DEV_CLK(398, 23, "board_0_hfosc1_clk_out"), DEV_CLK(398, 28, "board_0_tck_out"), + DEV_CLK(404, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(404, 3, "board_0_serdes0_refclk_n_out"), + DEV_CLK(404, 4, "board_0_serdes0_refclk_p_out"), + DEV_CLK(404, 5, "hsdiv4_16fft_main_3_hsdivout4_clk"), + DEV_CLK(404, 6, "serdes0_core_refclk_out0"), + DEV_CLK(404, 7, "gluelogic_hfosc0_clkout"), + DEV_CLK(404, 8, "board_0_hfosc1_clk_out"), + DEV_CLK(404, 9, "hsdiv4_16fft_main_3_hsdivout4_clk"), + DEV_CLK(404, 10, "hsdiv4_16fft_main_2_hsdivout4_clk"), + DEV_CLK(404, 39, "pcie_g3x4_128_main_1_pcie_lane0_txclk"), + DEV_CLK(404, 45, "pcie_g3x4_128_main_1_pcie_lane1_txclk"), + DEV_CLK(404, 51, "pcie_g3x4_128_main_1_pcie_lane2_txclk"), + DEV_CLK(404, 57, "pcie_g3x4_128_main_1_pcie_lane3_txclk"), + DEV_CLK(404, 81, "usb3p0ss_16ffc_main_0_pipe_txclk"), + DEV_CLK(404, 129, "board_0_tck_out"), }; const struct ti_k3_clk_platdata j784s4_clk_platdata = { diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index 19901821225..2bb1a88ab3b 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof . * - * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -21,10 +21,11 @@ static struct ti_pd soc_pd_list[] = { [1] = PSC_PD(3, &soc_psc_list[1], NULL), [2] = PSC_PD(0, &soc_psc_list[2], NULL), [3] = PSC_PD(1, &soc_psc_list[2], &soc_pd_list[2]), - [4] = PSC_PD(14, &soc_psc_list[2], NULL), - [5] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[4]), - [6] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[4]), - [7] = PSC_PD(38, &soc_psc_list[2], NULL), + [4] = PSC_PD(5, &soc_psc_list[2], NULL), + [5] = PSC_PD(14, &soc_psc_list[2], NULL), + [6] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[5]), + [7] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[5]), + [8] = PSC_PD(38, &soc_psc_list[2], NULL), }; static struct ti_lpsc soc_lpsc_list[] = { @@ -44,13 +45,15 @@ static struct ti_lpsc soc_lpsc_list[] = { [13] = PSC_LPSC(20, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [14] = PSC_LPSC(23, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [15] = PSC_LPSC(25, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), - [16] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), - [17] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), - [18] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[4], NULL), - [19] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[5], &soc_lpsc_list[18]), - [20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]), - [21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]), - [22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL), + [16] = PSC_LPSC(29, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), + [17] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), + [18] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), + [19] = PSC_LPSC(64, &soc_psc_list[2], &soc_pd_list[4], NULL), + [20] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[5], NULL), + [21] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[20]), + [22] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[20]), + [23] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[8], &soc_lpsc_list[24]), + [24] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[8], NULL), }; static struct ti_dev soc_dev_list[] = { @@ -78,14 +81,16 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(398, &soc_lpsc_list[13]), PSC_DEV(141, &soc_lpsc_list[14]), PSC_DEV(140, &soc_lpsc_list[15]), - PSC_DEV(146, &soc_lpsc_list[16]), - PSC_DEV(392, &soc_lpsc_list[17]), - PSC_DEV(395, &soc_lpsc_list[17]), - PSC_DEV(198, &soc_lpsc_list[18]), - PSC_DEV(202, &soc_lpsc_list[19]), - PSC_DEV(203, &soc_lpsc_list[20]), - PSC_DEV(133, &soc_lpsc_list[21]), - PSC_DEV(193, &soc_lpsc_list[22]), + PSC_DEV(333, &soc_lpsc_list[16]), + PSC_DEV(146, &soc_lpsc_list[17]), + PSC_DEV(392, &soc_lpsc_list[18]), + PSC_DEV(395, &soc_lpsc_list[18]), + PSC_DEV(404, &soc_lpsc_list[19]), + PSC_DEV(198, &soc_lpsc_list[20]), + PSC_DEV(202, &soc_lpsc_list[21]), + PSC_DEV(203, &soc_lpsc_list[22]), + PSC_DEV(133, &soc_lpsc_list[23]), + PSC_DEV(193, &soc_lpsc_list[24]), }; const struct ti_k3_pd_platdata j784s4_pd_platdata = { diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index d1d2605b2cc..671a6cb1cad 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -93,6 +93,15 @@ config TARGET_MT8188 USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. +config TARGET_MT8195 + bool "MediaTek MT8195 SoC" + select ARM64 + help + The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and + a quad-core Cortex-A53. It is including UART, SPI, USB3.0 dual role, + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 + and LPDDR4 options. + config TARGET_MT8365 bool "MediaTek MT8365 SoC" select ARM64 @@ -130,6 +139,33 @@ config TARGET_MT8518 endchoice +if ARM64 + +config MTK_MEM_MAP_DDR_BASE_PHY + hex "DDR physical base address" + default 0x40000000 + help + Target-specific DDR physical base address. + +config MTK_MEM_MAP_DDR_SIZE + hex "DDR .size in mem_map" + default 0x200000000 if TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8188 || TARGET_MT8195 + default 0xc0000000 if TARGET_MT8365 + default 0x80000000 if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT8183 + default 0x40000000 if TARGET_MT7622 || TARGET_MT8512 + default 0x20000000 + help + Target-specific DDR region size in mem_map. + +config MTK_MEM_MAP_MMIO_SIZE + hex "MMIO .size in mem_map" + default 0x40000000 if TARGET_MT7622 || TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8512 + default 0x20000000 + help + Target-specific MMIO region size in mem_map. + +endif + config SYS_BOARD string "Board name" default "mt7622" if TARGET_MT7622 @@ -165,7 +201,7 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8195 default "lk=1" if TARGET_MT7623 config MTK_TZ_MOVABLE diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 44591bed6fa..d1f64d61ab9 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_ARM64) += armv8-mem-map.o obj-y += cpu.o obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o obj-$(CONFIG_XPL_BUILD) += spl.o @@ -13,6 +14,7 @@ obj-$(CONFIG_TARGET_MT7987) += mt7987/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8188) += mt8188/ +obj-$(CONFIG_TARGET_MT8195) += mt8195/ obj-$(CONFIG_TARGET_MT8365) += mt8365/ obj-$(CONFIG_TARGET_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ diff --git a/arch/arm/mach-mediatek/armv8-mem-map.c b/arch/arm/mach-mediatek/armv8-mem-map.c new file mode 100644 index 00000000000..cbaa9b4c267 --- /dev/null +++ b/arch/arm/mach-mediatek/armv8-mem-map.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +static struct mm_region mediatek_mem_map[] = { + { + /* DDR */ + .virt = CONFIG_MTK_MEM_MAP_DDR_BASE_PHY, + .phys = CONFIG_MTK_MEM_MAP_DDR_BASE_PHY, + .size = CONFIG_MTK_MEM_MAP_DDR_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = CONFIG_MTK_MEM_MAP_MMIO_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + } +}; + +struct mm_region *mem_map = mediatek_mem_map; diff --git a/arch/arm/mach-mediatek/init.h b/arch/arm/mach-mediatek/init.h deleted file mode 100644 index 1d896fbbf7e..00000000000 --- a/arch/arm/mach-mediatek/init.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef __MEDIATEK_INIT_H_ -#define __MEDIATEK_INIT_H_ - -extern int mtk_soc_early_init(void); - -#endif /* __MEDIATEK_INIT_H_ */ diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 368f2916224..a043ca87398 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -36,23 +36,3 @@ void reset_cpu(void) { psci_system_reset(); } - -static struct mm_region mt7622_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; -struct mm_region *mem_map = mt7622_mem_map; diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 3d6ba3f383c..8713889b92d 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -16,11 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; struct boot_argument *preloader_param; -int mtk_soc_early_init(void) -{ - return 0; -} - int dram_init(void) { u32 i; diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c index 7cb8b72c364..ff027ed03ef 100644 --- a/arch/arm/mach-mediatek/mt7629/init.c +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -int mtk_pll_early_init(void) +static int mtk_pll_early_init(void) { unsigned long pll_rates[] = { [CLK_APMIXED_ARMPLL] = 1250000000, diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index 07da5897190..79afd6ce6be 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -30,24 +30,3 @@ void reset_cpu(void) { psci_system_reset(); } - -static struct mm_region mt7981_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7981_mem_map; diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index a521c95bd9d..1fe56b3f145 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -30,24 +30,3 @@ void reset_cpu(void) { psci_system_reset(); } - -static struct mm_region mt7986_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7986_mem_map; diff --git a/arch/arm/mach-mediatek/mt7987/init.c b/arch/arm/mach-mediatek/mt7987/init.c index 8b268297809..6364ab497f7 100644 --- a/arch/arm/mach-mediatek/mt7987/init.c +++ b/arch/arm/mach-mediatek/mt7987/init.c @@ -39,24 +39,3 @@ void reset_cpu(ulong addr) { psci_system_reset(); } - -static struct mm_region mt7987_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x200000000ULL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7987_mem_map; diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 8bdd3848d26..7ff843585ec 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -38,24 +38,3 @@ void reset_cpu(ulong addr) { psci_system_reset(); } - -static struct mm_region mt7988_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x200000000ULL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt7988_mem_map; diff --git a/arch/arm/mach-mediatek/mt8183/init.c b/arch/arm/mach-mediatek/mt8183/init.c index 37243547da8..8dbf9c3df7e 100644 --- a/arch/arm/mach-mediatek/mt8183/init.c +++ b/arch/arm/mach-mediatek/mt8183/init.c @@ -37,16 +37,6 @@ int dram_init_banksize(void) return 0; } -int mtk_pll_early_init(void) -{ - return 0; -} - -int mtk_soc_early_init(void) -{ - return 0; -} - void reset_cpu(void) { psci_system_reset(); @@ -57,23 +47,3 @@ int print_cpuinfo(void) printf("CPU: MediaTek MT8183\n"); return 0; } - -static struct mm_region mt8183_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; -struct mm_region *mem_map = mt8183_mem_map; diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c index ed67150e611..9743e39d582 100644 --- a/arch/arm/mach-mediatek/mt8188/init.c +++ b/arch/arm/mach-mediatek/mt8188/init.c @@ -45,11 +45,6 @@ int dram_init_banksize(void) return 0; } -int mtk_soc_early_init(void) -{ - return 0; -} - void reset_cpu(void) { struct udevice *wdt; diff --git a/board/mediatek/mt8365_evk/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile similarity index 62% rename from board/mediatek/mt8365_evk/Makefile rename to arch/arm/mach-mediatek/mt8195/Makefile index 90fc92b28c5..886ab7e4eb9 100644 --- a/board/mediatek/mt8365_evk/Makefile +++ b/arch/arm/mach-mediatek/mt8195/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y += mt8365_evk.o +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c new file mode 100644 index 00000000000..0f68c589e9a --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 MediaTek Inc. + * Copyright (C) 2026 BayLibre, SAS + * Author: Julien Stephan + * Chris-QJ Chen + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + fdtdec_setup_mem_size_base(); + + /* + * Limit gd->ram_top not exceeding SZ_4G. Some periphals like mmc + * requires DMA buffer allocated below SZ_4G. + * + * Note: SZ_1M is for adjusting gd->relocaddr, the reserved memory for + * u-boot itself. + */ + if (gd->ram_base + gd->ram_size >= SZ_4G) + gd->mon_len = (gd->ram_base + gd->ram_size + SZ_1M) - SZ_4G; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_soc_early_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct udevice *wdt; + + if (IS_ENABLED(CONFIG_PSCI_RESET)) { + psci_system_reset(); + } else { + uclass_first_device(UCLASS_WDT, &wdt); + if (wdt) + wdt_expire_now(wdt, 0); + } +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8195\n"); + return 0; +} diff --git a/arch/arm/mach-mediatek/mt8365/init.c b/arch/arm/mach-mediatek/mt8365/init.c index 8f03ed28763..fb14a5a1902 100644 --- a/arch/arm/mach-mediatek/mt8365/init.c +++ b/arch/arm/mach-mediatek/mt8365/init.c @@ -26,11 +26,6 @@ int dram_init_banksize(void) return 0; } -int mtk_soc_early_init(void) -{ - return 0; -} - void reset_cpu(void) { struct udevice *wdt; diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index 3b48caf5196..361c589cbc2 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -59,24 +59,3 @@ int print_cpuinfo(void) debug("CPU: MediaTek MT8512\n"); return 0; } - -static struct mm_region mt8512_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x40000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8512_mem_map; diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 892bd441a33..1d925dd478a 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -40,7 +40,7 @@ int dram_init_banksize(void) return 0; } -int mtk_pll_early_init(void) +static int mtk_pll_early_init(void) { unsigned long pll_rates[] = { [CLK_APMIXED_ARMPLL] = 1300000000, @@ -94,23 +94,3 @@ int print_cpuinfo(void) printf("CPU: MediaTek MT8516\n"); return 0; } - -static struct mm_region mt8516_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; -struct mm_region *mem_map = mt8516_mem_map; diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index c04bcb63517..8fa1346021a 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -51,24 +51,3 @@ int print_cpuinfo(void) printf("CPU: MediaTek MT8518\n"); return 0; } - -static struct mm_region mt8518_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8518_mem_map; diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c index 247d7ee6f1d..6f1ec052b95 100644 --- a/arch/arm/mach-mediatek/spl.c +++ b/arch/arm/mach-mediatek/spl.c @@ -9,7 +9,10 @@ #include #include -#include "init.h" +__weak int mtk_soc_early_init(void) +{ + return 0; +} void board_init_f(ulong dummy) { diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index 6535539184c..542792cad1b 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -10,13 +10,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index dc4abe1e107..17722cb897d 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -12,13 +12,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index 0370ed57e20..d5c506df22b 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index b76510ab452..4afaee234ea 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -74,7 +74,7 @@ config MV78230 config MV78260 bool select ARMADA_XP - imply CMD_SATA + imply SATA config MV78460 bool @@ -204,7 +204,7 @@ config TARGET_THEADORABLE bool "Support theadorable Armada XP" select BOARD_LATE_INIT if USB select MV78260 - imply CMD_SATA + imply SATA config TARGET_CONTROLCENTERDC bool "Support CONTROLCENTERDC" diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index c07dd68e6ce..1e989ac48ac 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -156,6 +156,43 @@ config SYS_DEFAULT_LPDDR2_TIMINGS endchoice +config SPL_AM33XX_MMCSD_MULTIPLE + bool "Support multiple locations of next boot phase" + depends on AM33XX + depends on SPL_SYS_MMCSD_RAW_MODE + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + help + The boot ROM on the am33xx looks for the first stage + bootloader at several hard-coded offsets in the mmc device + (0, 128K, 256K, 384K) and uses the first location which has + a valid header. This can be used to implement failsafe + update of that first stage (SPL). But in order for the + update of the whole bootloader to be failsafe, SPL must load + U-Boot proper from a location dependent on where SPL itself + was loaded from. This option allows you to specify four + different offsets corresponding to the different places + where SPL could have been loaded from. + +if SPL_AM33XX_MMCSD_MULTIPLE + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_0K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 0K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_128K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 128K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_256K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 256K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_384K + hex "Address on the MMC to load U-Boot from when SPL was loaded from offset 384K" + default SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + +endif + source "arch/arm/mach-omap2/omap3/Kconfig" source "arch/arm/mach-omap2/omap5/Kconfig" diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 95b44c8b1e5..88fa59feaf1 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -318,3 +318,34 @@ static void tee_image_process(ulong tee_image, size_t tee_size) } U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, tee_image_process); #endif + +#ifdef CONFIG_SPL_AM33XX_MMCSD_MULTIPLE + +#define AM335X_TRACE_VECTOR2 0x4030CE44 + +unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) +{ + u32 bits = *(u32 *)AM335X_TRACE_VECTOR2; + + bits &= 0xf000; + + /* + * The ROM code sets the "trial bit 3", bit 15, first, when + * attempting offset 0, then "trial bit 2", bit 14, when + * attempting offset 128K, and so on. If the tracing vector + * has completely unexpected contents, fall back to the + * raw_sect we were given. + */ + switch (bits) { + case 0x8000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_0K; break; + case 0xc000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_128K; break; + case 0xe000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_256K; break; + case 0xf000: raw_sect = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_384K; break; + default: + printf("Warning: Unexpected trial bits 0x%04x in trace vector 2, falling back to 0x%lx\n", + bits, raw_sect); + } + + return raw_sect; +} +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 92bb4aa62f1..108713488af 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -8,7 +8,6 @@ config ROCKCHIP_PX30 select SUPPORT_TPL select SPL select TPL - select TPL_TINY_FRAMEWORK if TPL select TPL_HAVE_INIT_STACK if TPL imply SPL_SEPARATE_BSS imply SPL_SERIAL @@ -132,6 +131,7 @@ config ROCKCHIP_RK3288 select SPL select SUPPORT_TPL select FDT_64BIT + imply OF_UPSTREAM imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD @@ -284,7 +284,7 @@ config ROCKCHIP_RK3399 imply OF_LIBFDT_OVERLAY imply OF_LIVE imply OF_UPSTREAM - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply PHY_GIGE if GMAC_ROCKCHIP imply PRE_CONSOLE_BUFFER imply RNG_ROCKCHIP @@ -317,6 +317,49 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3506 + bool "Support Rockchip RK3506" + select CPU_V7A + select SUPPORT_SPL + select SPL + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + select DM_REGULATOR_FIXED + select DM_RESET + imply BOOTSTD_FULL + imply DM_RNG + imply ENV_RELOC_GD_ENV_ADDR + imply FIT + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL + imply ROCKCHIP_OTP + imply SPL_ARMV7_SET_CORTEX_SMPEN + imply SPL_CLK + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_LOAD_FIT + imply SPL_OF_CONTROL + imply SPL_PINCTRL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_SERIAL + imply SPL_SYSCON + imply SYS_ARCH_TIMER + imply SYSRESET + help + The Rockchip RK3506 is a ARM-based SoC with a tri-core Cortex-A7. + config ROCKCHIP_RK3528 bool "Support Rockchip RK3528" select ARM64 @@ -745,6 +788,7 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rk3506/Kconfig" source "arch/arm/mach-rockchip/rk3528/Kconfig" source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rk3576/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 06fb527b21a..d3bc0689f89 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RK3506) += rk3506/ obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/ obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/ diff --git a/arch/arm/mach-rockchip/rk3506/Kconfig b/arch/arm/mach-rockchip/rk3506/Kconfig new file mode 100644 index 00000000000..92f187458c6 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/Kconfig @@ -0,0 +1,15 @@ +if ROCKCHIP_RK3506 + +config ROCKCHIP_BOOT_MODE_REG + default 0xff910200 + +config ROCKCHIP_STIMER_BASE + default 0xff980000 + +config SYS_SOC + default "rk3506" + +config SYS_CONFIG_NAME + default "rk3506_common" + +endif diff --git a/arch/arm/mach-rockchip/rk3506/Makefile b/arch/arm/mach-rockchip/rk3506/Makefile new file mode 100644 index 00000000000..a1760bd0f0a --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += rk3506.o +obj-y += clk_rk3506.o +obj-y += syscon_rk3506.o diff --git a/arch/arm/mach-rockchip/rk3506/clk_rk3506.c b/arch/arm/mach-rockchip/rk3506/clk_rk3506.c new file mode 100644 index 00000000000..96723f403cf --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/clk_rk3506.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3506_cru), devp); +} + +void *rockchip_get_cru(void) +{ + return (void *)RK3506_CRU_BASE; +} diff --git a/arch/arm/mach-rockchip/rk3506/rk3506.c b/arch/arm/mach-rockchip/rk3506/rk3506.c new file mode 100644 index 00000000000..2ed1dcc128e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/rk3506.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include + +#define SGRF_BASE 0xff210000 + +#define FIREWALL_DDR_BASE 0xff5f0000 +#define FW_DDR_MST1_REG 0x24 +#define FW_DDR_MST2_REG 0x28 +#define FW_DDR_MST3_REG 0x2c + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ff480000", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@ff480000", +}; + +void board_debug_uart_init(void) +{ +} + +int arch_cpu_init(void) +{ + u32 val; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return 0; + + /* Select non-secure OTPC */ + rk_clrreg(SGRF_BASE + 0x100, BIT(1)); + + /* Set the sdmmc/emmc to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xffff00ff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the fspi to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xff00ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the mac0 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xf0ffffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the mac1 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST2_REG); + writel(val & 0xfffffff0, FIREWALL_DDR_BASE + FW_DDR_MST2_REG); + + /* Set the otg1 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST3_REG); + writel(val & 0xfff0ffff, FIREWALL_DDR_BASE + FW_DDR_MST3_REG); + + return 0; +} + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + +void rockchip_stimer_init(void) +{ + u32 reg; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return; + + reg = readl(HP_TIMER_BASE + HP_CTRL_REG); + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); +} + +#define RK3506_OTP_CPU_CODE_OFFSET 0x02 +#define RK3506_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x06 */ + ret = misc_read(dev, RK3506_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3506J */ + ret = misc_read(dev, RK3506_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3506J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c b/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c new file mode 100644 index 00000000000..2548b0fa2d3 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include +#include + +static const struct udevice_id rk3506_syscon_ids[] = { + { .compatible = "rockchip,rk3506-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_syscon) = { + .name = "rockchip_rk3506_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3506_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS index ee840396e8b..111fe0270df 100644 --- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS @@ -4,6 +4,12 @@ S: Maintained F: arch/arm/dts/rk3528-generic* F: configs/generic-rk3528_defconfig +NANOPI-ZERO2-RK3528 +M: Jonas Karlman +S: Maintained +F: arch/arm/dts/rk3528-nanopi-zero2* +F: configs/nanopi-zero2-rk3528_defconfig + RADXA-E20C M: Jonas Karlman S: Maintained diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index 57ead0006f1..f9bfc445b85 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -49,21 +49,6 @@ void board_debug_uart_init(void) { } -u32 read_brom_bootsource_id(void) -{ - u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); - - /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE - * enum value to avoid having to create a larger boot_devices table. - */ - if (bootsource_id == 0x81) - return BROM_BOOTSOURCE_USB; - else if (bootsource_id > BROM_LAST_BOOTSOURCE) - log_debug("Unknown bootsource %x\n", bootsource_id); - - return bootsource_id; -} - int arch_cpu_init(void) { u32 val; diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index c2b96902d2d..2b1eafee37c 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -72,9 +72,15 @@ static struct mm_region rk3568_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0x300000000, - .phys = 0x300000000, - .size = 0x0c0c00000, + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x300000000UL, + .phys = 0x300000000UL, + .size = 0x0c0c00000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index a1e8a7572fa..c17ba418ced 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -26,6 +26,9 @@ #define SYS_SGRF_SOC_CON15 0x005C #define SYS_SGRF_SOC_CON20 0x0070 +#define FW_PMU1SGRF_BASE 0x26003000 +#define PMU1SGRF_SLV_LOOKUP0 0x80 + #define FW_SYS_SGRF_BASE 0x26005000 #define SGRF_DOMAIN_CON1 0x4 #define SGRF_DOMAIN_CON2 0x8 @@ -140,6 +143,9 @@ int arch_cpu_init(void) if (!IS_ENABLED(CONFIG_SPL_BUILD)) return 0; + /* Allow pmu sram access for non-secure masters */ + writel(0xffff3fff, FW_PMU1SGRF_BASE + PMU1SGRF_SLV_LOOKUP0); + /* Set the emmc to access ddr memory */ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2); diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 60c16d2f32d..675f13ab66d 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -286,14 +286,15 @@ config TARGET_ROCK_5_ITX_RK3588 Powered by either 12V, ATX power-supply or PoE config TARGET_ROCK_5C_RK3588S - bool "Radxa ROCK 5C RK3588S2 board" + bool "Radxa ROCK 5C/5C Lite" help - Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer. + Radxa ROCK 5C/5C Lite is a Rockchip RK3588S2/RK3582 based SBC (Single + Board Computer) by Radxa. Specification: - Quad A76 and Quad A55 CPU - 6 TOPS NPU + Quad/Dual A76 and Quad A55 CPU + 6/5 TOPS NPU up to 32GB LPDDR4x RAM eMMC / SPI flash connector Micro SD Card slot diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 55d2caab4fe..eedce7b9b08 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY LOGC_ARCH #include +#include #include #include #include @@ -87,6 +88,24 @@ static struct mm_region rk3588_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x2fc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x3fc500000UL, + .phys = 0x3fc500000UL, + .size = 0x3a00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { .virt = 0x900000000, .phys = 0x900000000, .size = 0x150000000, @@ -211,8 +230,45 @@ int arch_cpu_init(void) } #endif +/* + * RK3588 has two known memory gaps when using 16+ GiB DRAM, + * [0x3fc000000, 0x3fc500000) and [0x3fff00000, 0x400000000). + * + * Remove the [0x3fc000000, 0x400000000) range to ensure OS does not + * use memory from these gaps when a DDR_MEM tag cannot be found. + */ + +#define DRAM_GAP_START 0x3FC000000 +#define DRAM_GAP_END 0x400000000 + +int rockchip_dram_init_banksize_fixup(struct bd_info *bd) +{ + size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size; + + if (ram_top > DRAM_GAP_START) { + bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start; + + if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) { + bd->bi_dram[2].start = DRAM_GAP_END; + bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start; + } + } + + return 0; +} + #define RK3588_OTP_CPU_CODE_OFFSET 0x02 #define RK3588_OTP_SPECIFICATION_OFFSET 0x06 +#define RK3588_OTP_IP_STATE_OFFSET 0x1d + +#define FAIL_CPU_CLUSTER0 GENMASK(3, 0) +#define FAIL_CPU_CLUSTER1 GENMASK(5, 4) +#define FAIL_CPU_CLUSTER2 GENMASK(7, 6) +#define FAIL_GPU GENMASK(4, 1) +#define FAIL_RKVDEC0 BIT(6) +#define FAIL_RKVDEC1 BIT(7) +#define FAIL_RKVENC0 BIT(0) +#define FAIL_RKVENC1 BIT(2) int checkboard(void) { @@ -258,3 +314,207 @@ int checkboard(void) return 0; } + +static int fdt_path_del_node(void *fdt, const char *path) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(fdt, path); + if (nodeoffset < 0) + return nodeoffset; + + return fdt_del_node(fdt, nodeoffset); +} + +static int fdt_path_set_name(void *fdt, const char *path, const char *name) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(fdt, path); + if (nodeoffset < 0) + return nodeoffset; + + return fdt_set_name(fdt, nodeoffset, name); +} + +/* + * RK3582 is a variant of the RK3588S with some IP blocks disabled. What blocks + * are disabled/non-working is indicated by ip-state in OTP. ft_system_setup() + * is used to mark any cpu, gpu and/or vdec/venc node with status=fail as + * indicated by ip-state. Apply same policy as vendor U-Boot for RK3582, i.e. + * two big cpu cores, the gpu and one vdec/venc core is always failed. Enable + * OF_SYSTEM_SETUP to use the required DT fixups for RK3582 board variants. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + static const char * const cpu_node_names[] = { + "cpu@0", "cpu@100", "cpu@200", "cpu@300", + "cpu@400", "cpu@500", "cpu@600", "cpu@700", + }; + int parent, node, i, comp_len, len, ret; + bool cluster1_removed = false; + u8 cpu_code[2], ip_state[3]; + struct udevice *dev; + char soc_comp[16]; + const char *comp; + void *data; + + if (!IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) + return 0; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return -ENOSYS; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return ret; + } + + /* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */ + ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return ret; + } + + log_debug("cpu-code: %02x %02x\n", cpu_code[0], cpu_code[1]); + + /* only fail cores on rk3582 */ + if (!(cpu_code[0] == 0x35 && cpu_code[1] == 0x82)) + return 0; + + ret = misc_read(dev, RK3588_OTP_IP_STATE_OFFSET, &ip_state, 3); + if (ret < 0) { + log_err("Could not read ip-state, ret=%d\n", ret); + return ret; + } + + log_debug("ip-state: %02x %02x %02x (otp)\n", + ip_state[0], ip_state[1], ip_state[2]); + + /* policy: fail entire big core cluster when one or more core is bad */ + if (ip_state[0] & FAIL_CPU_CLUSTER1) + ip_state[0] |= FAIL_CPU_CLUSTER1; + if (ip_state[0] & FAIL_CPU_CLUSTER2) + ip_state[0] |= FAIL_CPU_CLUSTER2; + + /* policy: always fail one big core cluster on rk3582 */ + if (!(ip_state[0] & (FAIL_CPU_CLUSTER1 | FAIL_CPU_CLUSTER2))) + ip_state[0] |= FAIL_CPU_CLUSTER2; + + /* policy: always fail gpu on rk3582 */ + ip_state[1] |= FAIL_GPU; + + /* policy: always fail one rkvdec core on rk3582 */ + if (!(ip_state[1] & (FAIL_RKVDEC0 | FAIL_RKVDEC1))) + ip_state[1] |= FAIL_RKVDEC1; + + /* policy: always fail one rkvenc core on rk3582 */ + if (!(ip_state[2] & (FAIL_RKVENC0 | FAIL_RKVENC1))) + ip_state[2] |= FAIL_RKVENC1; + + log_debug("ip-state: %02x %02x %02x (policy)\n", + ip_state[0], ip_state[1], ip_state[2]); + + /* cpu cluster1: ip_state[0]: bit4~5 */ + if ((ip_state[0] & FAIL_CPU_CLUSTER1) == FAIL_CPU_CLUSTER1) { + log_debug("remove cpu-map cluster1\n"); + fdt_path_del_node(blob, "/cpus/cpu-map/cluster1"); + cluster1_removed = true; + } + + /* cpu cluster2: ip_state[0]: bit6~7 */ + if ((ip_state[0] & FAIL_CPU_CLUSTER2) == FAIL_CPU_CLUSTER2) { + log_debug("remove cpu-map cluster2\n"); + fdt_path_del_node(blob, "/cpus/cpu-map/cluster2"); + } else if (cluster1_removed) { + /* cluster nodes must be named in a continuous series */ + log_debug("rename cpu-map cluster2\n"); + fdt_path_set_name(blob, "/cpus/cpu-map/cluster2", "cluster1"); + } + + /* gpu: ip_state[1]: bit1~4 */ + if (ip_state[1] & FAIL_GPU) { + log_debug("fail gpu\n"); + fdt_status_fail_by_pathf(blob, "/gpu@fb000000"); + } + + /* rkvdec: ip_state[1]: bit6,7 */ + if (ip_state[1] & FAIL_RKVDEC0) { + log_debug("fail rkvdec0\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdc38000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdc38700"); + } + if (ip_state[1] & FAIL_RKVDEC1) { + log_debug("fail rkvdec1\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdc40000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdc40700"); + } + + /* rkvenc: ip_state[2]: bit0,2 */ + if (ip_state[2] & FAIL_RKVENC0) { + log_debug("fail rkvenc0\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdbd0000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdbdf000"); + } + if (ip_state[2] & FAIL_RKVENC1) { + log_debug("fail rkvenc1\n"); + fdt_status_fail_by_pathf(blob, "/video-codec@fdbe0000"); + fdt_status_fail_by_pathf(blob, "/iommu@fdbef000"); + } + + parent = fdt_path_offset(blob, "/cpus"); + if (parent < 0) { + log_err("Could not find /cpus, parent=%d\n", parent); + return parent; + } + + /* cpu: ip_state[0]: bit0~7 */ + for (i = 0; i < 8; i++) { + /* fail any bad cpu core */ + if (!(ip_state[0] & BIT(i))) + continue; + + node = fdt_subnode_offset(blob, parent, cpu_node_names[i]); + if (node >= 0) { + log_debug("fail cpu %s\n", cpu_node_names[i]); + fdt_status_fail(blob, node); + } else { + log_err("Could not find %s, node=%d\n", + cpu_node_names[i], node); + return node; + } + } + + node = fdt_path_offset(blob, "/"); + if (node < 0) { + log_err("Could not find /, node=%d\n", node); + return node; + } + + snprintf(soc_comp, sizeof(soc_comp), "rockchip,rk35%x", cpu_code[1]); + + for (i = 0, comp_len = 0; + (comp = fdt_stringlist_get(blob, node, "compatible", i, &len)); + i++) { + /* stop at soc compatible */ + if (!strcmp(comp, soc_comp) || + !strcmp(comp, "rockchip,rk3588s") || + !strcmp(comp, "rockchip,rk3588")) + break; + + log_debug("compatible[%d]: %s\n", i, comp); + comp_len += len + 1; + } + + /* truncate to only include board compatible */ + fdt_setprop_placeholder(blob, node, "compatible", comp_len, &data); + + /* append soc compatible */ + fdt_appendprop_string(blob, node, "compatible", soc_comp); + fdt_appendprop_string(blob, node, "compatible", "rockchip,rk3588s"); + + return 0; +} diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index d560f90e873..ea0e3621af7 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -289,6 +289,11 @@ static int rockchip_dram_init_banksize(void) } #endif +__weak int rockchip_dram_init_banksize_fixup(struct bd_info *bd) +{ + return 0; +} + int dram_init_banksize(void) { size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE); @@ -342,7 +347,7 @@ int dram_init_banksize(void) #endif #endif - return 0; + return rockchip_dram_init_banksize_fixup(gd->bd); } u8 rockchip_sdram_type(phys_addr_t reg) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 1ce3a3b0554..e989c148079 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include @@ -10,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +35,17 @@ __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { __weak u32 read_brom_bootsource_id(void) { - return readl(BROM_BOOTSOURCE_ID_ADDR); + u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); + + /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE + * enum value to avoid having to create a larger boot_devices table. + */ + if (bootsource_id == 0x81) + return BROM_BOOTSOURCE_USB; + else if (bootsource_id > BROM_LAST_BOOTSOURCE) + log_debug("Unknown bootsource %x\n", bootsource_id); + + return bootsource_id; } const char *board_spl_was_booted_from(void) @@ -140,3 +152,52 @@ void spl_board_prepare_for_boot(void) cleanup_before_linux(); } + +#if CONFIG_IS_ENABLED(RAM_DEVICE) && IS_ENABLED(CONFIG_SPL_LOAD_FIT) +binman_sym_declare_optional(ulong, payload, image_pos); +binman_sym_declare_optional(ulong, payload, size); + +static ulong ramboot_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + ulong addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT, + CONFIG_SPL_LOAD_FIT_ADDRESS); + + memcpy(buf, map_sysmem(addr + sector, 0), count); + return count; +} + +static int ramboot_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + struct legacy_img_hdr *header; + ulong addr = IF_ENABLED_INT(CONFIG_SPL_LOAD_FIT, + CONFIG_SPL_LOAD_FIT_ADDRESS); + ulong image_pos = binman_sym(ulong, payload, image_pos); + ulong size = binman_sym(ulong, payload, size); + + if (addr == CFG_SYS_SDRAM_BASE || addr == CONFIG_SPL_TEXT_BASE) + return -ENODEV; + + if (image_pos != BINMAN_SYM_MISSING && size != BINMAN_SYM_MISSING) { + header = map_sysmem(image_pos, 0); + if (image_get_magic(header) == FDT_MAGIC) { + memmove(map_sysmem(addr, 0), header, size); + memset(header, 0, sizeof(*header)); + } + } + + header = map_sysmem(addr, 0); + if (image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + spl_load_init(&load, ramboot_load_read, NULL, 1); + return spl_load_simple_fit(spl_image, &load, 0, header); + } + + return -ENODEV; +} + +/* Use priority and method name that sort before default spl_ram_load_image */ +SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, ramboot_load_image); +#endif diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index 1486656b36b..774c69091ee 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -41,7 +41,6 @@ config SC59X_64 select COMMON_CLK_ADI_SC598 select GICV3 select GICV3_SUPPORT_GIC600 - select GIC_600_CLEAR_RDPD select MMC_SDHCI_ADMA_FORCE_32BIT select NOP_PHY if PHY diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f2e959b5662..aec0fb7b1c8 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,15 +1,15 @@ if ARCH_SOCFPGA config ERR_PTR_OFFSET - default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range + default 0xfffec000 if ARCH_SOCFPGA_GEN5 # Boot ROM range config NR_DRAM_BANKS default 1 config SOCFPGA_SECURE_VAB_AUTH bool "Enable boot image authentication with Secure Device Manager" - depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \ - TARGET_SOCFPGA_AGILEX5 + depends on ARCH_SOCFPGA_AGILEX || ARCH_SOCFPGA_N5X || \ + ARCH_SOCFPGA_AGILEX5 select FIT_IMAGE_POST_PROCESS select SHA384 select SHA512 @@ -23,32 +23,32 @@ config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE depends on SOCFPGA_SECURE_VAB_AUTH config SPL_SIZE_LIMIT - default 0x10000 if TARGET_SOCFPGA_GEN5 + default 0x10000 if ARCH_SOCFPGA_GEN5 config SPL_SIZE_LIMIT_PROVIDE_STACK - default 0x200 if TARGET_SOCFPGA_GEN5 + default 0x200 if ARCH_SOCFPGA_GEN5 config SPL_STACK_R_ADDR - default 0x00800000 if TARGET_SOCFPGA_GEN5 + default 0x00800000 if ARCH_SOCFPGA_GEN5 config SPL_SYS_MALLOC_F - default y if TARGET_SOCFPGA_GEN5 + default y if ARCH_SOCFPGA_GEN5 config SPL_SYS_MALLOC_F_LEN - default 0x800 if TARGET_SOCFPGA_GEN5 + default 0x800 if ARCH_SOCFPGA_GEN5 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 config SYS_MALLOC_F_LEN - default 0x2000 if TARGET_SOCFPGA_ARRIA10 - default 0x2000 if TARGET_SOCFPGA_GEN5 + default 0x2000 if ARCH_SOCFPGA_ARRIA10 + default 0x2000 if ARCH_SOCFPGA_GEN5 config TEXT_BASE - default 0x01000040 if TARGET_SOCFPGA_ARRIA10 - default 0x01000040 if TARGET_SOCFPGA_GEN5 + default 0x01000040 if ARCH_SOCFPGA_ARRIA10 + default 0x01000040 if ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_AGILEX +config ARCH_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -58,9 +58,9 @@ config TARGET_SOCFPGA_AGILEX select GICV2 select NCORE_CACHE select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_AGILEX7M +config ARCH_SOCFPGA_AGILEX7M bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -70,21 +70,21 @@ config TARGET_SOCFPGA_AGILEX7M select GICV2 select NCORE_CACHE select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_AGILEX5 +config ARCH_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_ARRIA5 +config ARCH_SOCFPGA_ARRIA5 bool - select TARGET_SOCFPGA_GEN5 + select ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_ARRIA10 +config ARCH_SOCFPGA_ARRIA10 bool select GICV2 select SPL_ALTERA_SDRAM @@ -105,17 +105,17 @@ config TARGET_SOCFPGA_ARRIA10 config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM bool "Always reprogram Arria 10 FPGA" - depends on TARGET_SOCFPGA_ARRIA10 + depends on ARCH_SOCFPGA_ARRIA10 help Arria 10 FPGA is only programmed during the cold boot. This option forces the FPGA to be reprogrammed every reboot, allowing to change the bitstream and apply it with warm reboot. -config TARGET_SOCFPGA_CYCLONE5 +config ARCH_SOCFPGA_CYCLONE5 bool - select TARGET_SOCFPGA_GEN5 + select ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_GEN5 +config ARCH_SOCFPGA_GEN5 bool select SPL_ALTERA_SDRAM imply FPGA_SOCFPGA @@ -125,7 +125,7 @@ config TARGET_SOCFPGA_GEN5 imply SPL_SYS_MALLOC_SIMPLE imply SPL_USE_TINY_PRINTF -config TARGET_SOCFPGA_N5X +config ARCH_SOCFPGA_N5X bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -135,23 +135,23 @@ config TARGET_SOCFPGA_N5X select NCORE_CACHE select SPL_ALTERA_SDRAM select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 config TARGET_SOCFPGA_N5X_SOCDK bool "Intel eASIC SoCDK (N5X)" - select TARGET_SOCFPGA_N5X + select ARCH_SOCFPGA_N5X -config TARGET_SOCFPGA_SOC64 +config ARCH_SOCFPGA_SOC64 bool -config TARGET_SOCFPGA_STRATIX10 +config ARCH_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX select GICV2 - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 choice prompt "Altera SOCFPGA board select" @@ -159,85 +159,93 @@ choice config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" - select TARGET_SOCFPGA_AGILEX + select ARCH_SOCFPGA_AGILEX config TARGET_SOCFPGA_AGILEX7M_SOCDK bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" - select TARGET_SOCFPGA_AGILEX7M + select ARCH_SOCFPGA_AGILEX7M config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" - select TARGET_SOCFPGA_AGILEX5 + select ARCH_SOCFPGA_AGILEX5 config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_ARRIA10_SOCDK bool "Altera SOCFPGA SoCDK (Arria 10)" - select TARGET_SOCFPGA_ARRIA10 + select ARCH_SOCFPGA_ARRIA10 config TARGET_SOCFPGA_ARRIA5_SECU1 bool "ABB SECU1 (Arria V)" - select TARGET_SOCFPGA_ARRIA5 + select ARCH_SOCFPGA_ARRIA5 select VENDOR_KM config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" - select TARGET_SOCFPGA_ARRIA5 + select ARCH_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_CHAMELEONV3 bool "Google Chameleon v3 (Arria 10)" - select TARGET_SOCFPGA_ARRIA10 + select ARCH_SOCFPGA_ARRIA10 config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 bool "Devboards DBM-SoC1 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_EBV_SOCRATES bool "EBV SoCrates (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_IS1 bool "IS1 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_SOFTING_VINING_FPGA bool "Softing VIN|ING FPGA (Cyclone V)" select BOARD_LATE_INIT - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_SR1500 bool "SR1500 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_STRATIX10_SOCDK bool "Intel SOCFPGA SoCDK (Stratix 10)" - select TARGET_SOCFPGA_STRATIX10 + select ARCH_SOCFPGA_STRATIX10 config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE10_NANO bool "Terasic DE10-Nano (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE10_STANDARD bool "Terasic DE10-Standard (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE1_SOC bool "Terasic DE1-SoC (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_CORECOURSE_AC501SOC + bool "CoreCourse AC501SoC (Cyclone V)" + select ARCH_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_CORECOURSE_AC550SOC + bool "CoreCourse AC550SoC (Cyclone V)" + select ARCH_SOCFPGA_CYCLONE5 endchoice @@ -263,6 +271,8 @@ config SYS_BOARD default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK @@ -284,6 +294,8 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_SOC default "socfpga" @@ -310,5 +322,7 @@ config SYS_CONFIG_NAME default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "socfpga_ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 4e85bfb00d4..b6f35ddacc4 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,7 +10,7 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o obj-y += misc_gen5.o obj-y += reset_manager_gen5.o @@ -21,14 +21,14 @@ obj-y += wrap_pll_config.o obj-y += fpga_manager.o endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o endif -ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -41,7 +41,7 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX +ifdef CONFIG_ARCH_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -57,7 +57,7 @@ obj-y += wrap_pll_config_soc64.o obj-y += altera-sysmgr.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +ifdef CONFIG_ARCH_SOCFPGA_AGILEX5 obj-y += clock_manager_agilex5.o obj-y += mailbox_s10.o obj-y += misc_soc64.o @@ -73,7 +73,7 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M obj-y += clock_manager_agilex.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -89,7 +89,7 @@ obj-y += wrap_pll_config_soc64.o obj-y += altera-sysmgr.o endif -ifdef CONFIG_TARGET_SOCFPGA_N5X +ifdef CONFIG_ARCH_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -105,34 +105,34 @@ obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_XPL_BUILD -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 obj-y += spl_gen5.o obj-y += freeze_controller.o obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif -ifdef CONFIG_TARGET_SOCFPGA_SOC64 +ifdef CONFIG_ARCH_SOCFPGA_SOC64 obj-y += firewall.o obj-y += spl_soc64.o endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif -ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 obj-y += spl_s10.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX +ifdef CONFIG_ARCH_SOCFPGA_AGILEX obj-y += spl_agilex.o endif -ifdef CONFIG_TARGET_SOCFPGA_N5X +ifdef CONFIG_ARCH_SOCFPGA_N5X obj-y += spl_n5x.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +ifdef CONFIG_ARCH_SOCFPGA_AGILEX5 obj-y += spl_soc64.o obj-y += spl_agilex5.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M obj-y += spl_agilex7m.o endif else @@ -140,7 +140,7 @@ obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o endif -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 # QTS-generated config file wrappers CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7f65aed4540..4d7f0b9a79c 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -61,7 +61,7 @@ int board_init(void) int dram_init_banksize(void) { -#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #ifndef CONFIG_SPL_BUILD struct spl_handoff *ho; @@ -72,7 +72,7 @@ int dram_init_banksize(void) #endif #else fdtdec_setup_memory_banksize(); -#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ +#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */ return 0; } @@ -145,7 +145,7 @@ u8 socfpga_get_board_id(void) return board_id; } -#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64) int board_fit_config_name_match(const char *name) { char board_name[10]; diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 134eaf08e0a..da71f5759db 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -18,7 +18,7 @@ void cm_wait_for_lock(u32 mask) u32 inter_val; u32 retry = 0; do { -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) inter_val = readl(socfpga_get_clkmgr_addr() + CLKMGR_INTER) & mask; #else @@ -45,7 +45,7 @@ int cm_wait_for_fsm(void) int set_cpu_clk_info(void) { -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) /* Calculate the clock frequencies required for drivers */ cm_get_l4_sp_clk_hz(); cm_get_mmc_controller_clk_hz(); @@ -54,7 +54,7 @@ int set_cpu_clk_info(void) gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; #else gd->bd->bi_ddr_freq = 0; @@ -63,7 +63,7 @@ int set_cpu_clk_info(void) return 0; } -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64) int cm_set_qspi_controller_clk_hz(u32 clk_hz) { u32 reg; diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 9987d5bcee6..95c7f044952 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c index 7ec28d91ef3..fa068a9eeb1 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex5.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_n5x.c b/arch/arm/mach-socfpga/clock_manager_n5x.c index c4c071330fc..8e47b4b8f5b 100644 --- a/arch/arm/mach-socfpga/clock_manager_n5x.c +++ b/arch/arm/mach-socfpga/clock_manager_n5x.c @@ -6,15 +6,12 @@ #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 1e148947a33..fd27470f967 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -4,15 +4,14 @@ * */ +#include +#include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * function to write the bypass register which requires a poll of the * busy bit diff --git a/arch/arm/mach-socfpga/config.mk b/arch/arm/mach-socfpga/config.mk index 2290118f747..1ca1d33cb16 100644 --- a/arch/arm/mach-socfpga/config.mk +++ b/arch/arm/mach-socfpga/config.mk @@ -2,9 +2,9 @@ # # Brian Sune -ifeq ($(CONFIG_TARGET_SOCFPGA_CYCLONE5),y) +ifeq ($(CONFIG_ARCH_SOCFPGA_CYCLONE5),y) archprepare: socfpga_g5_handoff_prepare -else ifeq ($(CONFIG_TARGET_SOCFPGA_ARRIA5),y) +else ifeq ($(CONFIG_ARCH_SOCFPGA_ARRIA5),y) archprepare: socfpga_g5_handoff_prepare endif @@ -23,7 +23,7 @@ socfpga_g5_handoff_prepare: if [ -z "$$VENDOR" ] || [ -z "$$BOARD" ]; then \ exit 0; \ fi; \ - BOARD_DIR=$(src)/board/$$VENDOR/$$BOARD; \ + BOARD_DIR=$(srctree)/board/$$VENDOR/$$BOARD; \ if [ "$$HANDOFF_PATH" ]; then \ echo "[INFO] Using manually specified handoff folder: $$HANDOFF_PATH"; \ else \ @@ -44,5 +44,5 @@ socfpga_g5_handoff_prepare: fi; \ echo "[INFO] Found hiof file: $$HIOF_FILE"; \ echo "[INFO] Running BSP generator..."; \ - python3 $(src)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \ + python3 $(srctree)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \ echo "[DONE] SoCFPGA QTS handoff conversion complete." diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 074b9691af8..61982c2d508 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -7,7 +7,7 @@ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ #define _SOCFPGA_SOC64_BASE_HARDWARE_H_ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOCFPGA_CCU_ADDRESS 0x1c000000 #define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000 #define SOCFPGA_SMMU_ADDRESS 0x16000000 @@ -47,9 +47,9 @@ #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 #define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 @@ -84,6 +84,6 @@ #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 #define GICD_BASE 0xfffc1000 #define GICC_BASE 0xfffc2000 -#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */ +#endif /* IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) */ #endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index f0431c081d8..48001dbff21 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -17,22 +17,22 @@ void cm_print_clock_quick_summary(void); unsigned long cm_get_mpu_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); -#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +#if defined(CONFIG_ARCH_SOCFPGA_SOC64) int cm_set_qspi_controller_clk_hz(u32 clk_hz); #endif #endif -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include -#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#elif defined(CONFIG_ARCH_SOCFPGA_STRATIX10) #include -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #include -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #include -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 2b436b64816..b47b577ae75 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -138,7 +138,7 @@ struct socfpga_firwall_l4_sys { #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index 481b66bbd86..fc084823b51 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -9,9 +9,9 @@ #include -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index b8f2f73e283..ae5af1f0100 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -19,7 +19,7 @@ #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 #define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524D -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 #else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 @@ -29,11 +29,11 @@ #define SOC64_HANDOFF_OFFSET_DATA 0x10 #define SOC64_HANDOFF_SIZE 4096 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x634) /* DDR handoff */ #define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) @@ -43,9 +43,9 @@ #else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) #endif -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SOC64_HANDOFF_BASE 0xFFE5F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630) @@ -76,17 +76,17 @@ #define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) #define SOC64_HANDOFF_PERI_LEN 1 #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) #define SOC64_HANDOFF_SDRAM_LEN 5 #endif -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c) #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610) #else @@ -96,9 +96,9 @@ #define SOC64_HANDOFF_MUX_LEN 96 #define SOC64_HANDOFF_IOCTL_LEN 96 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_FPGA_LEN 42 -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_FPGA_LEN 44 #else #define SOC64_HANDOFF_FPGA_LEN 40 diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 0b80e952131..5a6a76b5ace 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -24,7 +24,7 @@ void socfpga_fpga_add(void *fpga_desc); static inline void socfpga_fpga_add(void *fpga_desc) {} #endif -#ifdef CONFIG_TARGET_SOCFPGA_GEN5 +#ifdef CONFIG_ARCH_SOCFPGA_GEN5 void socfpga_sdram_remap_zero(void); static inline bool socfpga_is_booting_from_fpga(void) { @@ -35,14 +35,14 @@ static inline bool socfpga_is_booting_from_fpga(void) } #endif -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if defined(CONFIG_ARCH_SOCFPGA_STRATIX10) || \ + defined(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + defined(CONFIG_ARCH_SOCFPGA_AGILEX7M) int is_fpga_config_ready(void); #endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 1d68034cb55..97bb48474f3 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -39,11 +39,11 @@ void socfpga_per_reset_all(void); /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include -#elif defined(CONFIG_TARGET_SOCFPGA_SOC64) +#elif defined(CONFIG_ARCH_SOCFPGA_SOC64) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 4b010be9ee8..5d72480dc13 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -39,7 +39,7 @@ void socfpga_bridges_reset(int enable, unsigned int mask); #define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ RSTMGR_STAT_L4WD0RST_BIT) diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 79cb9e6064a..9a261eb9383 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -7,9 +7,9 @@ #ifndef __ASSEMBLY__ -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 5603eaa3d02..3d5bd81e1b5 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -8,7 +8,7 @@ phys_addr_t socfpga_get_sysmgr_addr(void); -#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +#if defined(CONFIG_ARCH_SOCFPGA_SOC64) #include #else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) @@ -85,9 +85,9 @@ phys_addr_t socfpga_get_sysmgr_addr(void); #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1) #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1) -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index f768a3a55cb..8be98d0ee46 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -12,7 +12,7 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SYSMGR_SOC64_SILICONID_1 0x00 #define SYSMGR_SOC64_SILICONID_2 0x04 #define SYSMGR_SOC64_MPU_STATUS 0x10 @@ -62,7 +62,7 @@ void populate_sysmgr_pinmux(void); #else #define SYSMGR_SOC64_NAND_AXUSER 0x5c #define SYSMGR_SOC64_DMA_L3MASTER 0x74 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE 0xb8 #else #define SYSMGR_SOC64_HMC_CLK 0xb4 @@ -73,7 +73,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 #define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) -#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/ +#endif /*CONFIG_ARCH_SOCFPGA_AGILEX5*/ #define SYSMGR_SOC64_DMA 0x20 #define SYSMGR_SOC64_DMA_PERIPH 0x24 @@ -218,7 +218,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_WDDBG_PAUSE_ALL_CPU 0xFF0F0F0F -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE_MSK BIT(0) #endif diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index f9c34e85711..5e8768168d3 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -8,15 +8,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define MBOX_READL(reg) \ readl(SOCFPGA_MAILBOX_ADDRESS + (reg)) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 07694107c8a..1eef7893e54 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,7 +54,7 @@ struct bsel bsel_str[] = { int dram_init(void) { -#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) struct spl_handoff *ho; ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); @@ -65,7 +65,7 @@ int dram_init(void) #else if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; -#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ +#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */ return 0; } @@ -261,21 +261,21 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) { ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); if (ret) hang(); } - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); - else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + else if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 5259ef54d73..ae33051c00f 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -28,8 +27,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - static struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static struct nic301_registers *nic301_regs = diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 5222b384434..84f10844ee3 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -17,11 +17,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - /* Agilex5 Sub Device Jtag ID List */ #define A3690_JTAG_ID 0x036090DD #define A3694_JTAG_ID 0x436090DD @@ -94,7 +91,7 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, int print_cpuinfo(void) { printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; } diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index 1dc44ab4797..9f68d12351f 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -5,11 +5,8 @@ */ #include -#include -DECLARE_GLOBAL_DATA_PTR; - -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) static struct mm_region socfpga_agilex5_mem_map[] = { { /* OCRAM 512KB */ diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index abb62a9b49f..b2b4077fd4b 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define TIMEOUT_300MS 300 /* F2S manager registers */ @@ -79,7 +76,7 @@ static void socfpga_f2s_bridges_reset(int enable, unsigned int mask) u32 flaginstatus_idleack = 0; u32 flaginstatus_respempty = 0; - if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + if (CONFIG_IS_ENABLED(ARCH_SOCFPGA_STRATIX10)) { /* Support fpga2soc and f2sdram */ brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | RSTMGR_BRGMODRST_F2SDRAM0_MASK | diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 48f258a37b4..53a9aa55f80 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 1be347360f5..2c3e40b664a 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ diff --git a/arch/arm/mach-socfpga/spl_agilex7m.c b/arch/arm/mach-socfpga/spl_agilex7m.c index 90065ccee6f..7371202a712 100644 --- a/arch/arm/mach-socfpga/spl_agilex7m.c +++ b/arch/arm/mach-socfpga/spl_agilex7m.c @@ -15,14 +15,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index df79cfe0f7f..08b756db2ca 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -25,8 +24,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 81283ef7162..a49be837921 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index fa83ff96adc..a0d3c96d456 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 913f93c8f94..2f2ac9330ee 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -6,13 +6,11 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) /* * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse * generation and setting PORT_OVERCURRENT bit so that until we turn on the @@ -39,7 +37,7 @@ void sysmgr_pinmux_init(void) populate_sysmgr_pinmux(); populate_sysmgr_fpgaintf_module(); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) sysmgr_config_usb3(); #endif } diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 7105cdc4905..ecde90f76f4 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -29,13 +29,13 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: case SOC64_HANDOFF_MAGIC_SDRAM: -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) case SOC64_HANDOFF_MAGIC_PERI: #else case SOC64_HANDOFF_MAGIC_MISC: #endif return BIG_ENDIAN; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: debug("%s: umctl2 handoff data\n", __func__); return LITTLE_ENDIAN; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 490097e98be..647e0a4c2bf 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -3,6 +3,7 @@ config CMD_STM32PROG select DFU select DFU_RAM select DFU_VIRT + select EFI_PARTITION select PARTITION_TYPE_GUID imply CMD_GPT if MMC imply CMD_MTD if MTD diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index e979ee4a2cc..89f0e77bcdb 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -118,6 +118,13 @@ config DRAM_SUNXI_MR14 help MR14 value from vendor DRAM settings. +config DRAM_SUNXI_MR22 + hex "DRAM MR22 parameter" + depends on DRAM_SUN50I_A133 + default 0x0 + help + MR22 value from vendor DRAM settings. + config DRAM_SUNXI_TPR0 hex "DRAM TPR0 parameter" default 0x0 @@ -1232,6 +1239,24 @@ config CHIP_DIP_SCAN select W1_EEPROM_DS24XXX select CMD_EXTENSION +config SPL_SUNXI_LED_STATUS + bool "Control GPIO status LED within SPL" + depends on SPL_GPIO && SUNXI_GPIO + +if SPL_SUNXI_LED_STATUS + +config SPL_SUNXI_LED_STATUS_BIT + int "GPIO number for GPIO status LED" + help + GPIO number for the GPIO controlling the GPIO status LED in SPL. + +config SPL_SUNXI_LED_STATUS_STATE + bool "GPIO status LED initial state is on" + help + Whether the initial state of the status LED in SPL must be on or off. + +endif # SPL_SUNXI_LED_STATUS + source "board/sunxi/Kconfig" endif diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c index 1496f99624d..ca3e2513c69 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_a133.c +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c @@ -426,8 +426,8 @@ static void mctl_drive_odt_config(const struct dram_para *para) writel_relaxed(val, base); if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { - if (para->tpr3 & 0x1f1f1f1f) - val = (para->tpr3 >> (i * 8)) & 0x1f; + if (para->tpr1 & 0x1f1f1f1f) + val = (para->tpr1 >> (i * 8)) & 0x1f; else val = 4; } @@ -468,7 +468,7 @@ static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para) u32 *ptr; if (para->tpr10 & BIT(31)) { - val = para->tpr2; + val = para->tpr0; } else { val = ((para->tpr10 << 1) & 0x1e) | ((para->tpr10 << 5) & 0x1e00) | @@ -781,7 +781,7 @@ static void mctl_dfi_init(const struct dram_para *para) mctl_mr_write_lpddr4(12, para->mr12); mctl_mr_write_lpddr4(13, para->mr13); mctl_mr_write_lpddr4(14, para->mr14); - mctl_mr_write_lpddr4(22, para->tpr1); + mctl_mr_write_lpddr4(22, para->mr22); break; } @@ -871,7 +871,24 @@ static inline void mctl_phy_dx_delay1_inner(u32 *base, u32 val1, u32 val2) writel_relaxed(val2, ptr + 48); } -static inline void mctl_phy_dx_delay0_inner(u32 *base1, u32 *base2, u32 val1, +static inline void mctl_phy_dx_delay0_inner0(u32 *base1, u32 *base2, u32 val1, + u32 val2) +{ + u32 *ptr = base1; + + for (int i = 0; i < 9; i++) { + writel_relaxed(val1, ptr); + writel_relaxed(val1, ptr + 0x30); + ptr += 2; + } + + writel_relaxed(val2, base2); + writel_relaxed(val2, base2 + 48); + writel_relaxed(val2, ptr); + writel_relaxed(val2, base2 + 24); +} + +static inline void mctl_phy_dx_delay0_inner1(u32 *base1, u32 *base2, u32 val1, u32 val2) { u32 *ptr = base1; @@ -915,6 +932,8 @@ static void mctl_phy_dx_delay_compensation(const struct dram_para *para) (para->tpr11 >> 24) & 0x3f, (para->para0 >> 24) & 0x3f); + dmb(); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); } @@ -922,25 +941,27 @@ static void mctl_phy_dx_delay_compensation(const struct dram_para *para) clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, BIT(7)); clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, BIT(2)); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), - para->tpr12 & 0x3f, - para->tpr14 & 0x3f); + mctl_phy_dx_delay0_inner0((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), + para->tpr12 & 0x3f, + para->tpr14 & 0x3f); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x52c), - (para->tpr12 >> 8) & 0x3f, - (para->tpr14 >> 8) & 0x3f); + mctl_phy_dx_delay0_inner1((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x52c), + (para->tpr12 >> 8) & 0x3f, + (para->tpr14 >> 8) & 0x3f); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6a8), - (para->tpr12 >> 16) & 0x3f, - (para->tpr14 >> 16) & 0x3f); + mctl_phy_dx_delay0_inner0((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6a8), + (para->tpr12 >> 16) & 0x3f, + (para->tpr14 >> 16) & 0x3f); - mctl_phy_dx_delay0_inner((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6ac), - (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x528), - (para->tpr12 >> 24) & 0x3f, - (para->tpr14 >> 24) & 0x3f); + mctl_phy_dx_delay0_inner1((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654), + (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x6ac), + (para->tpr12 >> 24) & 0x3f, + (para->tpr14 >> 24) & 0x3f); + + dmb(); setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, BIT(7)); } @@ -1161,7 +1182,6 @@ static const struct dram_para para = { #elif defined(CONFIG_SUNXI_DRAM_LPDDR4) .type = SUNXI_DRAM_TYPE_LPDDR4, #endif - /* TODO: Populate from config */ .dx_odt = CONFIG_DRAM_SUNXI_DX_ODT, .dx_dri = CONFIG_DRAM_SUNXI_DX_DRI, .ca_dri = CONFIG_DRAM_SUNXI_CA_DRI, @@ -1170,9 +1190,10 @@ static const struct dram_para para = { .mr12 = CONFIG_DRAM_SUNXI_MR12, .mr13 = CONFIG_DRAM_SUNXI_MR13, .mr14 = CONFIG_DRAM_SUNXI_MR14, + .mr22 = CONFIG_DRAM_SUNXI_MR22, + .tpr0 = CONFIG_DRAM_SUNXI_TPR0, .tpr1 = CONFIG_DRAM_SUNXI_TPR1, .tpr2 = CONFIG_DRAM_SUNXI_TPR2, - .tpr3 = CONFIG_DRAM_SUNXI_TPR3, .tpr6 = CONFIG_DRAM_SUNXI_TPR6, .tpr10 = CONFIG_DRAM_SUNXI_TPR10, .tpr11 = CONFIG_DRAM_SUNXI_TPR11, diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a7938ed7910..48617f3ea93 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -66,6 +66,7 @@ int tegra_get_chip_sku(void) switch (chip_id) { case CHIPID_TEGRA20: switch (sku_id) { + case SKU_ID_T20_A04: case SKU_ID_AP20: case SKU_ID_T20: case SKU_ID_AP20H: @@ -76,6 +77,9 @@ int tegra_get_chip_sku(void) case SKU_ID_AP25E: case SKU_ID_T25E: return TEGRA_SOC_T25; + default: + debug("%s: UNKNOWN Tegra20 SKU ID (0x%02x)\n", __func__, sku_id); + return TEGRA_SOC_T20; } break; case CHIPID_TEGRA30: @@ -83,7 +87,9 @@ int tegra_get_chip_sku(void) case SKU_ID_T33: case SKU_ID_T30: case SKU_ID_TM30MQS_P_A3: + return TEGRA_SOC_T30; default: + debug("%s: UNKNOWN Tegra30 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T30; } break; @@ -91,21 +97,27 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T114_ENG: case SKU_ID_T114_1: + return TEGRA_SOC_T114; default: + debug("%s: UNKNOWN Tegra114 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T114; } break; case CHIPID_TEGRA124: switch (sku_id) { case SKU_ID_T124_ENG: + return TEGRA_SOC_T124; default: + debug("%s: UNKNOWN Tegra124 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T124; } break; case CHIPID_TEGRA210: switch (sku_id) { case SKU_ID_T210_ENG: + return TEGRA_SOC_T210; default: + debug("%s: UNKNOWN Tegra210 SKU ID (0x%02x)\n", __func__, sku_id); return TEGRA_SOC_T210; } break; diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 3f968d4aeae..019c4b0b21f 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -5,14 +5,12 @@ #include #include -#include #include #include #include - -DECLARE_GLOBAL_DATA_PTR; +#include #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE) static bool tegra_pmc_detect_tz_only(void) diff --git a/arch/arm/mach-versal2/Kconfig b/arch/arm/mach-versal2/Kconfig index 2a595151d6f..d1d8cbb815f 100644 --- a/arch/arm/mach-versal2/Kconfig +++ b/arch/arm/mach-versal2/Kconfig @@ -43,6 +43,9 @@ config SYS_MEM_RSVD_FOR_MMU config GICV3 def_bool y +config GICV3_SUPPORT_GIC600 + def_bool y + config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 2dfcadb369e..9a02fe40733 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -63,30 +63,69 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { } }; -void mem_map_fill(void) +/** + * mem_map_fill() - Populate global memory map with DRAM banks + * @bank_info: Array of memory regions parsed from device tree + * @num_banks: Number of valid DRAM banks in bank_info array + * + * Copies DRAM bank information into the global versal2_mem_map[] array + * starting at index VERSAL2_MEM_MAP_USED (5), which is after the fixed + * device mappings. This must be called early in boot before MMU + * initialization so that get_page_table_size() can calculate the + * required page table size based on actual memory configuration. + */ +void mem_map_fill(struct mm_region *bank_info, u32 num_banks) { int banks = VERSAL2_MEM_MAP_USED; - for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) - break; + for (int i = 0; i < num_banks; i++) { + if (banks > VERSAL2_MEM_MAP_MAX) + return; - versal2_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal2_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal2_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal2_mem_map[banks].virt = bank_info[i].phys; + versal2_mem_map[banks].phys = bank_info[i].phys; + versal2_mem_map[banks].size = bank_info[i].size; versal2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; } } +/** + * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info + * + * Transfers DRAM bank information from the global versal2_mem_map[] + * array to bd->bi_dram[] for passing memory configuration to the + * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical + * address and size are copied. + * + * This is called during dram_init_banksize() after the memory map + * has been populated by mem_map_fill() in dram_init(). Called after + * dram_init() but before kernel handoff. + */ +void fill_bd_mem_info(void) +{ + struct bd_info *bd = gd->bd; + int banks = VERSAL2_MEM_MAP_USED; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (!versal2_mem_map[banks].size) + break; + + bd->bi_dram[i].start = versal2_mem_map[banks].phys; + bd->bi_dram[i].size = versal2_mem_map[banks].size; + banks++; + } +} + struct mm_region *mem_map = versal2_mem_map; +#if CONFIG_IS_ENABLED(SYS_MEM_RSVD_FOR_MMU) u64 get_page_table_size(void) { return 0x14000; } +#endif U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index 7b1726a7ef4..cee13488620 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -5,5 +5,7 @@ */ #include +#include -void mem_map_fill(void); +void mem_map_fill(struct mm_region *bank_info, u32 num_banks); +void fill_bd_mem_info(void); diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 3dcff8076e3..7d65f3ea1a8 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -15,9 +15,6 @@ #include #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -#endif DECLARE_GLOBAL_DATA_PTR; @@ -65,6 +62,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) bootstage_mark(BOOTSTAGE_ID_RUN_OS); + bootm_final(0); + /* * Linux Kernel Parameters (passing board info data): * sp+00: Ignore, side effect of using jsr to jump to kernel diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 4261e5009fd..16c55ddfd95 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -7,12 +7,8 @@ config SYS_ARCH config STATIC_RELA def_bool y -choice - prompt "Target select" - optional - config TARGET_MICROBLAZE_GENERIC - bool "Support microblaze-generic" + def_bool y select BOARD_LATE_INIT select DM select DM_SERIAL @@ -26,8 +22,8 @@ config TARGET_MICROBLAZE_GENERIC select MTD select SPI imply CMD_DM - -endchoice + help + Support microblaze-generic source "board/xilinx/Kconfig" source "board/xilinx/microblaze-generic/Kconfig" diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 4879a41aab3..b54c902602f 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -17,20 +17,15 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*thekernel)(char *cmdline, ulong rd, ulong dt); ulong dt = (ulong)images->ft_addr; ulong rd_start = images->initrd_start; ulong cmdline = images->cmdline_start; - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - thekernel = (void (*)(char *, ulong, ulong))images->ep; debug("## Transferring control to Linux (at address 0x%08lx) ", @@ -39,13 +34,11 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) cmdline, rd_start, dt); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + bootm_final(flag); flush_cache_all(); - if (!fake) { + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) { /* * Linux Kernel Parameters (passing device tree): * r5: pointer to command line diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 87195100023..066c830f3fa 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -268,12 +268,7 @@ static void boot_jump_linux(struct bootm_headers *images) if (CONFIG_IS_ENABLED(MALTA)) linux_extra = gd->ram_size; -#if IS_ENABLED(CONFIG_BOOTSTAGE_FDT) - bootstage_fdt_add_report(); -#endif -#if IS_ENABLED(CONFIG_BOOTSTAGE_REPORT) - bootstage_report(); -#endif + bootm_final(0); if (CONFIG_IS_ENABLED(RESTORE_EXCEPTION_VECTOR_BASE)) trap_restore(); diff --git a/arch/mips/mach-ath79/qca956x/ddr.c b/arch/mips/mach-ath79/qca956x/ddr.c index 2e46e24f483..754e2573e37 100644 --- a/arch/mips/mach-ath79/qca956x/ddr.c +++ b/arch/mips/mach-ath79/qca956x/ddr.c @@ -5,7 +5,6 @@ * Based on QSDK */ -#include #include #include #include @@ -182,8 +181,6 @@ DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(0x1) | \ DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(0x1) -DECLARE_GLOBAL_DATA_PTR; - void qca956x_ddr_init(void) { u32 ddr_config, ddr_config2, ddr_config3, mod_val, \ diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 22b1b98e0ef..8ae6fb9437a 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -4,7 +4,6 @@ */ #include -#include #include #include @@ -14,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c index e2e1760a646..5fc4e0c49e8 100644 --- a/arch/mips/mach-mtmips/ddr_cal.c +++ b/arch/mips/mach-mtmips/ddr_cal.c @@ -7,13 +7,10 @@ #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define COARSE_MIN_START 6 #define FINE_MIN_START 15 #define COARSE_MAX_START 7 diff --git a/arch/mips/mach-octeon/cvmx-pko.c b/arch/mips/mach-octeon/cvmx-pko.c index 8a9181362bd..432488f7815 100644 --- a/arch/mips/mach-octeon/cvmx-pko.c +++ b/arch/mips/mach-octeon/cvmx-pko.c @@ -52,8 +52,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define CVMX_PKO_NQ_PER_PORT_MAX 32 static cvmx_pko_return_value_t cvmx_pko2_config_port(short ipd_port, diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 71319839ba2..6004e83bf0c 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ @@ -44,6 +41,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; + bootm_final(0); + /* flushes data and instruction caches before calling the kernel */ disable_interrupts(); flush_dcache_all(); diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 8ac83420ee2..0dc72c87423 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -73,6 +73,7 @@ config TARGET_KMTEPR2 config TARGET_GAZERBEAM bool "Support gazerbeam" select ARCH_MPC8308 + select REGMAP select SYS_FSL_ERRATUM_ESDHC111 imply ENV_IS_IN_FLASH help diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c5c2220593f..55152ab227e 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -93,7 +93,7 @@ config TARGET_P3041DS select ARCH_P3041 select BOARD_LATE_INIT if CHAIN_OF_TRUST select FSL_NGPIXIS - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P4080DS @@ -102,7 +102,7 @@ config TARGET_P4080DS select ARCH_P4080 select BOARD_LATE_INIT if CHAIN_OF_TRUST select FSL_NGPIXIS - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P5040DS @@ -112,7 +112,7 @@ config TARGET_P5040DS select BOARD_LATE_INIT if CHAIN_OF_TRUST select FSL_NGPIXIS select SYS_FSL_RAID_ENGINE - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_MPC8548CDS @@ -129,7 +129,7 @@ config TARGET_P1010RDB_PA select SUPPORT_TPL select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P1010RDB_PB @@ -140,7 +140,7 @@ config TARGET_P1010RDB_PB select SUPPORT_TPL select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P1020RDB_PC @@ -150,7 +150,7 @@ config TARGET_P1020RDB_PC select ARCH_P1020 select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P1020RDB_PD @@ -160,7 +160,7 @@ config TARGET_P1020RDB_PD select ARCH_P1020 select SYS_L2_SIZE_256KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_P2020RDB @@ -170,7 +170,7 @@ config TARGET_P2020RDB select ARCH_P2020 select SYS_L2_SIZE_512KB imply CMD_EEPROM - imply CMD_SATA + imply SATA imply SATA_SIL config TARGET_TURRIS_1X @@ -190,7 +190,7 @@ config TARGET_P2041RDB select FSL_CORENET select PHYS_64BIT select SYS_L3_SIZE_1024KB - imply CMD_SATA + imply SATA imply FSL_SATA config TARGET_QEMU_PPCE500 @@ -229,7 +229,7 @@ config TARGET_T2080QDS select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select FSL_DDR_INTERACTIVE select SYS_L3_SIZE_512KB - imply CMD_SATA + imply SATA config TARGET_T2080RDB bool "Support T2080RDB" @@ -238,7 +238,7 @@ config TARGET_T2080RDB select SUPPORT_SPL select PHYS_64BIT select SYS_L3_SIZE_512KB - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_T4240RDB @@ -248,7 +248,7 @@ config TARGET_T4240RDB select PHYS_64BIT select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select SYS_L3_SIZE_512KB - imply CMD_SATA + imply SATA imply PANIC_HANG config TARGET_KMP204X @@ -405,7 +405,7 @@ config ARCH_MPC8536 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_REGINFO config ARCH_MPC8540 @@ -482,7 +482,7 @@ config ARCH_P1010 imply CMD_EEPROM imply CMD_MTDPARTS imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_PCI imply CMD_REGINFO imply FSL_SATA @@ -521,7 +521,7 @@ config ARCH_P1020 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_PCI imply CMD_REGINFO imply SATA_SIL @@ -543,7 +543,7 @@ config ARCH_P1021 select FSL_ELBC imply CMD_REGINFO imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_REGINFO imply SATA_SIL @@ -579,7 +579,7 @@ config ARCH_P1024 select FSL_ELBC imply CMD_EEPROM imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_PCI imply CMD_REGINFO imply SATA_SIL @@ -599,7 +599,7 @@ config ARCH_P1025 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC - imply CMD_SATA + imply SATA imply CMD_REGINFO config ARCH_P2020 @@ -687,7 +687,7 @@ config ARCH_P3041 select SYS_FSL_USB2_PHY_ENABLE select FSL_ELBC imply CMD_NAND - imply CMD_SATA + imply SATA imply CMD_REGINFO imply FSL_SATA @@ -730,7 +730,7 @@ config ARCH_P4080 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC - imply CMD_SATA + imply SATA imply CMD_REGINFO imply SATA_SIL @@ -761,7 +761,7 @@ config ARCH_P5040 select SYS_FSL_USB2_PHY_ENABLE select SYS_PPC64 select FSL_ELBC - imply CMD_SATA + imply SATA imply CMD_REGINFO imply FSL_SATA @@ -903,7 +903,7 @@ config ARCH_T2080 select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC - imply CMD_SATA + imply SATA imply CMD_NAND imply CMD_REGINFO imply FSL_SATA @@ -946,7 +946,7 @@ config ARCH_T4240 select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC - imply CMD_SATA + imply SATA imply CMD_NAND imply CMD_REGINFO imply FSL_SATA diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index dc44bf3ab3a..f9351a17a48 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -54,12 +54,7 @@ static void boot_jump_linux(struct bootm_headers *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); -#ifdef CONFIG_BOOTSTAGE_FDT - bootstage_fdt_add_report(); -#endif -#ifdef CONFIG_BOOTSTAGE_REPORT - bootstage_report(); -#endif + bootm_final(0); #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 79867656b15..ad7589123c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -17,6 +17,9 @@ config TARGET_ANDES_VOYAGER config TARGET_BANANAPI_F3 bool "Support BananaPi F3 Board" +config TARGET_BEAGLEBOARD_BEAGLEVFIRE + bool "Support BeagleBoard BeagleV-Fire Board (based on Microchip MPFS)" + config TARGET_K230_CANMV bool "Support K230 CanMV Board" @@ -106,6 +109,7 @@ config SPL_ZERO_MEM_BEFORE_USE source "board/andestech/ae350/Kconfig" source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" +source "board/beagle/beaglev_fire/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_generic/Kconfig" diff --git a/arch/riscv/cpu/andes/spl.c b/arch/riscv/cpu/andes/spl.c index a13dc4095a4..1e19fad9288 100644 --- a/arch/riscv/cpu/andes/spl.c +++ b/arch/riscv/cpu/andes/spl.c @@ -8,11 +8,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(RAM_SUPPORT) struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) { diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c index 91007c0a3d3..5d7659887b9 100644 --- a/arch/riscv/cpu/cv1800b/dram.c +++ b/arch/riscv/cpu/cv1800b/dram.c @@ -5,11 +5,8 @@ #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index c68209d8fb2..f2934cb33e7 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -39,6 +39,7 @@ config SIFIVE_FU540 imply PWM_SIFIVE imply DM_I2C imply SYS_I2C_OCORES + imply OF_UPSTREAM if ENV_IS_IN_SPI_FLASH diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index d7ca9687171..66f9a8d5fa5 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -40,6 +40,7 @@ config SIFIVE_FU740 imply DM_I2C imply SYS_I2C_OCORES imply SPL_I2C + imply OF_UPSTREAM if ENV_IS_IN_SPI_FLASH diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 91007c0a3d3..5d7659887b9 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -5,11 +5,8 @@ #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 87aaf865246..3aece7d995b 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -41,7 +41,7 @@ int spl_dram_init(void) /* Read the definition of the DDR size from eeprom, and if not, * use the definition in DT */ - size = (get_ddr_size_from_eeprom() >> 16) & 0xFF; + size = get_ddr_size_from_eeprom(); if (check_ddr_size(size)) gd->ram_size = size << 30; diff --git a/arch/riscv/cpu/k230/dram.c b/arch/riscv/cpu/k230/dram.c index b2d3e4fd6a9..5d7659887b9 100644 --- a/arch/riscv/cpu/k230/dram.c +++ b/arch/riscv/cpu/k230/dram.c @@ -3,13 +3,10 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig index bcf1ede818b..8054313d182 100644 --- a/arch/riscv/cpu/mpfs/Kconfig +++ b/arch/riscv/cpu/mpfs/Kconfig @@ -6,8 +6,6 @@ config MICROCHIP_MPFS imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CLINT if RISCV_MMODE - imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c index b95470485f6..ceb934021d9 100644 --- a/arch/riscv/cpu/th1520/spl.c +++ b/arch/riscv/cpu/th1520/spl.c @@ -10,8 +10,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220) #define TH1520_SUBSYS_CLK_VO_EN BIT(2) #define TH1520_SUBSYS_CLK_VI_EN BIT(1) diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 9b347fc3b50..8e591cb7aa9 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,8 +9,6 @@ dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb -dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb -dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 360679a1781..19c7d6ccaca 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -7,11 +7,11 @@ / { cpus { - assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_COREPLL>; assigned-clock-rates = <1000000000>; bootph-pre-ram; cpu0: cpu@0 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; status = "okay"; cpu0_intc: interrupt-controller { @@ -19,28 +19,28 @@ }; }; cpu1: cpu@1 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu1_intc: interrupt-controller { bootph-pre-ram; }; }; cpu2: cpu@2 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu2_intc: interrupt-controller { bootph-pre-ram; }; }; cpu3: cpu@3 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu3_intc: interrupt-controller { bootph-pre-ram; }; }; cpu4: cpu@4 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu4_intc: interrupt-controller { bootph-pre-ram; @@ -80,7 +80,7 @@ reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 0x0 0x100b8000 0x0 0x1000>; - clocks = <&prci PRCI_CLK_DDRPLL>; + clocks = <&prci FU540_PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; bootph-pre-ram; }; @@ -100,7 +100,7 @@ }; ð0 { - assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125000000>; }; diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi deleted file mode 100644 index 7db86105348..00000000000 --- a/arch/riscv/dts/fu540-c000.dtsi +++ /dev/null @@ -1,286 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -/dts-v1/; - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = ð0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,e51", "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <1>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <2>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <3>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <4>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <4>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - dma: dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; - #dma-cells = <1>; - }; - uart1: serial@10011000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <5>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <50>; - clocks = <&prci PRCI_CLK_TLCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <51>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi2: spi@10050000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <6>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - l2cache: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, - <14>, <15>, <16>, <17>, <18>, <19>, <20>, - <21>, <22>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - }; -}; diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi deleted file mode 100644 index 7b77c13496d..00000000000 --- a/arch/riscv/dts/fu740-c000.dtsi +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 SiFive, Inc */ - -/dts-v1/; - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu740-c000", "sifive,fu740"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = ð0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,bullet0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&ccache>; - reg = <0x0>; - riscv,isa = "rv64imac"; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x1>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x2>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x3>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x4>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - #address-cells = <0>; - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <69>; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 0xffffffff>, - <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, - <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, - <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, - <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu740-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <39>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - uart1: serial@10011000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <40>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c1: i2c@10031000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10031000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <53>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000>, - <0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <41>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000>, - <0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <42>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - spi0: spi@10050000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <43>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <55>; - reg = <0x0 0x10090000 0x0 0x2000>, - <0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, - <&prci FU740_PRCI_CLK_GEMGXLPLL>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <44>, <45>, <46>, <47>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <48>, <49>, <50>, <51>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - ccache: cache-controller@2010000 { - compatible = "sifive,fu740-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <19>, <21>, <22>, <20>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>, <31>, <32>, <33>, <34>, <35>, <36>, - <37>, <38>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - pcie@e00000000 { - compatible = "sifive,fu740-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - reg = <0xe 0x00000000 0x0 0x80000000>, - <0xd 0xf0000000 0x0 0x10000000>, - <0x0 0x100d0000 0x0 0x1000>; - reg-names = "dbi", "config", "mgmt"; - device_type = "pci"; - dma-coherent; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ - <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ - <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ - num-lanes = <0x8>; - interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; - interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-parent = <&plic0>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, - <0x0 0x0 0x0 0x2 &plic0 58>, - <0x0 0x0 0x0 0x3 &plic0 59>, - <0x0 0x0 0x0 0x4 &plic0 60>; - clock-names = "pcie_aux"; - clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; - pwren-gpios = <&gpio 5 0>; - reset-gpios = <&gpio 8 0>; - resets = <&prci 4>; - status = "okay"; - }; - }; -}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts deleted file mode 100644 index 4a2729f5ca3..00000000000 --- a/arch/riscv/dts/hifive-unleashed-a00.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -#include "fu540-c000.dtsi" -#include - -/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "SiFive HiFive Unleashed A00"; - compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; - - chosen { - stdout-path = "serial0"; - }; - - cpus { - timebase-frequency = ; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - - soc { - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = ; - clock-output-names = "rtcclk"; - }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "issi,is25wp256", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&qspi2 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - }; -}; - -ð0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts deleted file mode 100644 index c4ed9efdff0..00000000000 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 SiFive, Inc */ - -#include "fu740-c000.dtsi" -#include -#include - -/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - model = "SiFive HiFive Unmatched A00"; - compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", - "sifive,fu740"; - - chosen { - stdout-path = "serial0"; - }; - - cpus { - timebase-frequency = ; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x4 0x00000000>; - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = ; - clock-output-names = "rtcclk"; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - vcc-supply = <&vdd_bpro>; - interrupt-parent = <&gpio>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - }; - - eeprom@54 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x54>; - vcc-supply = <&vdd_bpro>; - label = "board-id"; - pagesize = <16>; - read-only; - size = <256>; - }; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - - regulators { - vdd_bcore: bcores-merged { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-min-microamp = <4800000>; - regulator-max-microamp = <4800000>; - regulator-always-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2400000>; - regulator-max-microamp = <2400000>; - regulator-always-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1060000>; - regulator-min-microamp = <1500000>; - regulator-max-microamp = <1500000>; - regulator-always-on; - }; - - vdd_bmem_bio: bmem-bio-merged { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <3000000>; - regulator-always-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ld09: ldo9 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&spi0 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; -}; - -ð0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; - gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", - "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", - "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", - "EN_VDD_SD", "SD_CD"; -}; diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h index 45ad2a5f7bc..8b689a75013 100644 --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h @@ -9,8 +9,19 @@ #include +/** + * get_pcb_revision_from_eeprom() - get the PCB revision + * + * @return: the PCB revision or 0 on error. + */ u8 get_pcb_revision_from_eeprom(void); -u32 get_ddr_size_from_eeprom(void); + +/** + * get_ddr_size_from_eeprom() - read DDR size from EEPROM + * + * @return: size in GiB or 0 on error. + */ +u8 get_ddr_size_from_eeprom(void); /** * get_mmc_size_from_eeprom() - read eMMC size from EEPROM diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h index 543a1688db8..3a8fdb57136 100644 --- a/arch/riscv/include/asm/u-boot-riscv.h +++ b/arch/riscv/include/asm/u-boot-riscv.h @@ -16,7 +16,6 @@ int cleanup_before_linux(void); /* board/.../... */ int board_init(void); -void board_quiesce_devices(void); int riscv_board_reserved_mem_fixup(void *fdt); int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt); diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 9544907ab1e..69c9ca5c487 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -25,39 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -__weak void board_quiesce_devices(void) -{ -} - -/** - * announce_and_cleanup() - Print message and prepare for kernel boot - * - * @fake: non-zero to do everything except actually boot - */ -static void announce_and_cleanup(int fake) -{ - printf("\nStarting kernel ...%s\n\n", fake ? - "(fake run for tracing)" : ""); - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#ifdef CONFIG_BOOTSTAGE_FDT - bootstage_fdt_add_report(); -#endif -#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT) - bootstage_report(); -#endif - - board_quiesce_devices(); - - /* - * Call remove function of all devices with a removal flag set. - * This may be useful for last-stage operations, like cancelling - * of DMA operation or releasing device internal buffers. - */ - dm_remove_devices_active(); - - cleanup_before_linux(); -} - static void boot_prep_linux(struct bootm_headers *images) { if (CONFIG_IS_ENABLED(OF_LIBFDT) && IS_ENABLED(CONFIG_LMB) && images->ft_len) { @@ -75,7 +42,6 @@ static void boot_prep_linux(struct bootm_headers *images) static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*kernel)(ulong hart, void *dtb); - int fake = (flag & BOOTM_STATE_OS_FAKE_GO); #ifdef CONFIG_SMP int ret; #endif @@ -87,9 +53,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) debug("## Transferring control to kernel (at address %08lx) ...\n", (ulong)kernel); - announce_and_cleanup(fake); + bootm_final(flag); + cleanup_before_linux(); - if (!fake) { + if (!(flag & BOOTM_STATE_OS_FAKE_GO)) { if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_SMP ret = smp_call_function(images->ep, diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index d74544b93d8..9a0519af494 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -41,8 +41,5 @@ static inline void probe_cache_device(struct driver *driver, struct udevice *dev void enable_caches(void) { - struct udevice *dev = NULL; - - probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev); } #endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 762c1d9bbe2..ac92ebf1afd 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -46,6 +46,8 @@ mmc6 = "/mmc6"; mmc7 = "/mmc7"; mmc8 = "/mmc8"; + mmc9 = "/mmc9"; + mmc10 = "/mmc10"; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; @@ -1279,6 +1281,13 @@ filename = "mmc9.img"; }; + /* This is used for RAUC boot tests */ + mmc10 { + status = "disabled"; + compatible = "sandbox,mmc"; + filename = "mmc10.img"; + }; + pch { compatible = "sandbox,pch"; }; diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index 44ba8b52e13..7a5f6f7d36e 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -73,6 +73,7 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { bootstage_mark(BOOTSTAGE_ID_RUN_OS); + bootm_final(flag); printf("## Transferring control to Linux (at address %08lx)...\n", images->ep); printf("sandbox: continuing, as we cannot run Linux\n"); diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index bb0f59e0aa2..81d5957edaa 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -13,11 +13,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SH_SDRAM_OFFSET #define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET) #else @@ -95,6 +92,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) images->rd_end - images->rd_start); } + bootm_final(0); + /* Boot kernel */ kernel(); diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 48b033e7e27..8bf5a300d1f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -130,9 +130,6 @@ source "arch/x86/cpu/tangier/Kconfig" # architecture-specific options below -config AHCI - default y - config RAMBASE hex default 0x100000 diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index b72de96a277..ed0ad686b3f 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void enable_vmx(void) { struct cpuid_result regs; diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 7a94dc877e3..cde4fbf3557 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -34,22 +34,10 @@ DECLARE_GLOBAL_DATA_PTR; void bootm_announce_and_cleanup(void) { - printf("\nStarting kernel ...\n\n"); - #ifdef CONFIG_SYS_COREBOOT timestamp_add_now(TS_START_KERNEL); #endif - bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); -#if IS_ENABLED(CONFIG_BOOTSTAGE_REPORT) - bootstage_report(); -#endif - - /* - * Call remove function of all devices with a removal flag set. - * This may be useful for last-stage operations, like cancelling - * of DMA operation or releasing device internal buffers. - */ - dm_remove_devices_active(); + bootm_final(0); } #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index bd0efde00c1..96943cb8c46 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -5,13 +5,10 @@ */ #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int init_cache_f_r(void) { bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) || diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 2ea9bcf59c2..a5f2231aa52 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -30,7 +30,6 @@ #include #include #include -#include #ifdef CONFIG_SYS_COREBOOT #include #endif @@ -38,8 +37,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * Memory lay-out: * diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 2958f207397..c19ac9d1f9a 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -178,6 +178,8 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) printf("Transferring Control to Linux @0x%08lx ...\n\n", (ulong)images->ep); + bootm_final(flag); + flush_dcache_range((unsigned long)params_start, (unsigned long)params); if (flag & BOOTM_STATE_OS_FAKE_GO) diff --git a/arch/xtensa/lib/relocate.c b/arch/xtensa/lib/relocate.c index a499590c75b..d3d317edf88 100644 --- a/arch/xtensa/lib/relocate.c +++ b/arch/xtensa/lib/relocate.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index 319635c6b09..1fe33a4c62b 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -5,12 +5,9 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - #if XCHAL_HAVE_CCOUNT static ulong get_ccount(void) { diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c index c05eec6b35e..01d7a8c39e2 100644 --- a/board/BuR/brsmarc1/board.c +++ b/board/BuR/brsmarc1/board.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -30,8 +29,6 @@ /* -- defines for used GPIO Hardware -- */ #define PER_RESET (2 * 32 + 0) -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_XPL_BUILD) static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 3513f43a9f5..bbafecd7909 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -13,12 +13,9 @@ #include #include #include -#include #include #include "bur_common.h" -DECLARE_GLOBAL_DATA_PTR; - /* --------------------------------------------------------------------------*/ int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/BuR/zynq/Kconfig b/board/BuR/zynq/Kconfig index b450a21bd98..c7010fb26b3 100644 --- a/board/BuR/zynq/Kconfig +++ b/board/BuR/zynq/Kconfig @@ -7,7 +7,6 @@ config TARGET_ZYNQ_BR bool "Support BR Zynq builds" depends on SYS_VENDOR = "BuR" select BINMAN - select SPL_BINMAN_FDT endif diff --git a/board/Marvell/octeontx/smc.c b/board/Marvell/octeontx/smc.c index 8df32049bda..ab6284a732c 100644 --- a/board/Marvell/octeontx/smc.c +++ b/board/Marvell/octeontx/smc.c @@ -5,13 +5,10 @@ * https://spdx.org/licenses */ -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - ssize_t smc_dram_size(unsigned int node) { struct pt_regs regs; diff --git a/board/Marvell/octeontx2/smc.c b/board/Marvell/octeontx2/smc.c index 9e3169576c6..10645a74f69 100644 --- a/board/Marvell/octeontx2/smc.c +++ b/board/Marvell/octeontx2/smc.c @@ -5,15 +5,12 @@ * https://spdx.org/licenses */ -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - ssize_t smc_dram_size(unsigned int node) { struct pt_regs regs; diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index 8c9e9830876..a9a12a4f659 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -26,8 +26,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_NAND_MXS static void setup_gpmi_nand(void) { diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c index 1f7c1f25adc..fb8e8437759 100644 --- a/board/advantech/imx8mp_rsb3720a1/spl.c +++ b/board/advantech/imx8mp_rsb3720a1/spl.c @@ -29,8 +29,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { #ifdef CONFIG_SPL_BOOTROM_SUPPORT diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index accd300df04..fbe8b247e69 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -16,8 +16,6 @@ #include /* #include */ -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index 3def182f296..8214e627768 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/amarula/vyasa-rk3288/MAINTAINERS b/board/amarula/vyasa-rk3288/MAINTAINERS index 08ea208004a..d9cf639a31d 100644 --- a/board/amarula/vyasa-rk3288/MAINTAINERS +++ b/board/amarula/vyasa-rk3288/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/amarula/vyasa-rk3288 F: include/configs/vyasa-rk3288.h F: configs/vyasa-rk3288_defconfig -F: arch/arm/dts/rk3288-vyasa.dts F: arch/arm/dts/rk3288-vyasa-u-boot.dtsi diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index d8079c1cee0..d94c1494d53 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -367,28 +369,71 @@ int board_late_init(void) int dram_init_banksize(void) { - int ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - return ret; - - mem_map_fill(); - + fill_bd_mem_info(); return 0; } int dram_init(void) { - int ret; + struct mm_region bank_info[CONFIG_NR_DRAM_BANKS]; + ofnode mem = ofnode_null(); + struct resource res; + int ret, i, reg = 0; + u32 num_banks, reloc_use = 0; + u64 text = (u64)_start; - if (IS_ENABLED(CONFIG_SYS_MEM_RSVD_FOR_MMU)) - ret = fdtdec_setup_mem_size_base(); - else - ret = fdtdec_setup_mem_size_base_lowest(); + gd->ram_base = (unsigned long)~0; - if (ret) + mem = fdtdec_get_next_memory_node(mem); + if (!ofnode_valid(mem)) { + printf("%s: Missing /memory node\n", __func__); return -EINVAL; + } + + debug("%s: Text base = 0x%llx\n", __func__, text); + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + reloc_use = 0; + ret = ofnode_read_resource(mem, reg++, &res); + if (ret < 0) { + reg = 0; + mem = fdtdec_get_next_memory_node(mem); + if (!ofnode_valid(mem)) + break; + + ret = ofnode_read_resource(mem, reg++, &res); + if (ret < 0) + break; + } + + if (ret != 0) + return -EINVAL; + + bank_info[i].phys = (phys_addr_t)res.start; + bank_info[i].size = (phys_size_t)(res.end - res.start + 1); + + if (bank_info[i].size == 0) + break; + + if (text >= bank_info[i].phys && + text < (bank_info[i].phys + bank_info[i].size)) { + gd->ram_base = bank_info[i].phys; + gd->ram_size = bank_info[i].size; + reloc_use = 1; + } + + debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx %s", + __func__, i, (unsigned long long)bank_info[i].phys, + (unsigned long long)bank_info[i].size, + (reloc_use ? " - USED for RELOCATION\n" : "\n")); + + num_banks++; + } + + mem_map_fill(bank_info, num_banks); + + debug("%s: Initial DRAM: start = 0x%lx, size = 0x%lx\n", __func__, + gd->ram_base, (unsigned long)gd->ram_size); return 0; } diff --git a/board/andestech/voyager/voyager.c b/board/andestech/voyager/voyager.c index dc8f1347775..23fd0910ef8 100644 --- a/board/andestech/voyager/voyager.c +++ b/board/andestech/voyager/voyager.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 9ef3fa1b379..49c7fda0b83 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -41,7 +41,8 @@ config TARGET_VEXPRESS64_BASER_FVP config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select PCIE_ECAM_GENERIC if PCI - select SATA_SIL + select SATA if PCI + select SATA_SIL if PCI select SMC911X if DM_ETH select SMC911X_32_BIT if SMC911X select CMD_USB if USB diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index e8f1c2fe9fe..d68da0e3d65 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include #endif -DECLARE_GLOBAL_DATA_PTR; - static const struct pl01x_serial_plat serial_plat = { .base = V2M_UART0, .type = TYPE_PL011, diff --git a/board/beacon/imx8mm/Makefile b/board/beacon/imx8mm/Makefile index 8484b85ae12..eb762504266 100644 --- a/board/beacon/imx8mm/Makefile +++ b/board/beacon/imx8mm/Makefile @@ -4,7 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += imx8mm_beacon.o obj-y += ../../nxp/common/ ifdef CONFIG_XPL_BUILD diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c deleted file mode 100644 index 6459a99cb9d..00000000000 --- a/board/beacon/imx8mm/imx8mm_beacon.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks - */ - -#include - -DECLARE_GLOBAL_DATA_PTR; diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 93ee5b7ee0c..1e5935788ff 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/beacon/imx8mn/Makefile b/board/beacon/imx8mn/Makefile index 54735792b93..e8fe9f1822e 100644 --- a/board/beacon/imx8mn/Makefile +++ b/board/beacon/imx8mn/Makefile @@ -4,7 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += imx8mn_beacon.o obj-y += ../../nxp/common/ ifdef CONFIG_XPL_BUILD obj-y += spl.o diff --git a/board/beacon/imx8mn/imx8mn_beacon.c b/board/beacon/imx8mn/imx8mn_beacon.c deleted file mode 100644 index 6459a99cb9d..00000000000 --- a/board/beacon/imx8mn/imx8mn_beacon.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Logic PD, Inc. dba Beacon EmbeddedWorks - */ - -#include - -DECLARE_GLOBAL_DATA_PTR; diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index e91d3fdcf5e..46db42ec921 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -32,8 +31,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c index 027fae38278..e82e385b774 100644 --- a/board/beacon/imx8mp/spl.c +++ b/board/beacon/imx8mp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index 500fcc58ed8..27b1f22562c 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -13,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID, diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 9bc9ca30e95..70d296de9f8 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -14,8 +14,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID, diff --git a/board/beagle/beagleplay/rm-cfg.yaml b/board/beagle/beagleplay/rm-cfg.yaml index e4221f82f92..aa999c2ef67 100644 --- a/board/beagle/beagleplay/rm-cfg.yaml +++ b/board/beagle/beagleplay/rm-cfg.yaml @@ -513,7 +513,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -543,7 +543,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 627 + num_resource: 626 type: 1805 host_id: 128 reserved: 0 diff --git a/board/beagle/beaglev_fire/Kconfig b/board/beagle/beaglev_fire/Kconfig new file mode 100644 index 00000000000..7a8ecac8703 --- /dev/null +++ b/board/beagle/beaglev_fire/Kconfig @@ -0,0 +1,43 @@ +if TARGET_BEAGLEBOARD_BEAGLEVFIRE + +config SYS_BOARD + default "beaglev_fire" + +config SYS_VENDOR + default "beagle" + +config SYS_CPU + default "mpfs" + +config SYS_CONFIG_NAME + default "beaglev_fire" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select MICROCHIP_MPFS + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply SMP + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply PHY_LIB + imply PHY_VITESSE + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER +endif diff --git a/board/beagle/beaglev_fire/MAINTAINERS b/board/beagle/beaglev_fire/MAINTAINERS new file mode 100644 index 00000000000..a5dad93ee99 --- /dev/null +++ b/board/beagle/beaglev_fire/MAINTAINERS @@ -0,0 +1,7 @@ +BeagleBoard MPFS BeagleV-Fire +M: Cyril Jean +M: Jamie Gibbons +S: Maintained +F: board/beagle/beaglev_fire/ +F: include/configs/beaglev_fire.h +F: configs/beaglev_fire_defconfig \ No newline at end of file diff --git a/board/beagle/beaglev_fire/Makefile b/board/beagle/beaglev_fire/Makefile new file mode 100644 index 00000000000..a4109a8aad4 --- /dev/null +++ b/board/beagle/beaglev_fire/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Microchip Technology Inc. +# + +obj-y += beaglev_fire.o \ No newline at end of file diff --git a/board/beagle/beaglev_fire/beaglev_fire.c b/board/beagle/beaglev_fire/beaglev_fire.c new file mode 100644 index 00000000000..b2f18c455b7 --- /dev/null +++ b/board/beagle/beaglev_fire/beaglev_fire.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2023 Microchip Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define PERIPH_RESET_VALUE 0x800001e8u + +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) +static unsigned char mac_addr[6]; +#endif + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart, mmc peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(PERIPH_RESET_VALUE)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} + +int board_late_init(void) +{ +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) + u32 ret; + int node; + u8 device_serial_number[16] = {0}; + void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = devm_kzalloc(dev, sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; + + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mpfs_syscontroller_process_dtbo(sys_serv_priv); +#endif + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) + u32 ret; + int node; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } +#endif + + return 0; +} \ No newline at end of file diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 47a01227a35..cb53ec68cf8 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -9,12 +9,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/chipspark/popmetal_rk3288/MAINTAINERS b/board/chipspark/popmetal_rk3288/MAINTAINERS index e12f128dcd7..c81905453f2 100644 --- a/board/chipspark/popmetal_rk3288/MAINTAINERS +++ b/board/chipspark/popmetal_rk3288/MAINTAINERS @@ -1,7 +1,6 @@ POPMETAL-RK3288 M: Lin Huang S: Maintained -F: arch/arm/dts/rk3288-popmetal.dts F: arch/arm/dts/rk3288-popmetal-u-boot.dtsi F: board/chipspark/popmetal_rk3288 F: include/configs/popmetal_rk3288.h diff --git a/board/cloos/imx8mm_phg/imx8mm_phg.c b/board/cloos/imx8mm_phg/imx8mm_phg.c index 091c9a59a52..1ca1c07e08e 100644 --- a/board/cloos/imx8mm_phg/imx8mm_phg.c +++ b/board/cloos/imx8mm_phg/imx8mm_phg.c @@ -7,14 +7,11 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c index b8892ed2fcc..b2340a0ded3 100644 --- a/board/cloos/imx8mm_phg/spl.c +++ b/board/cloos/imx8mm_phg/spl.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -28,8 +27,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 6d9af2538b6..daac6dca4ce 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -32,8 +32,6 @@ #include "ddr/ddr.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index f2ca1076768..d0e8db6cdfe 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int board_early_init_r(void) { diff --git a/board/corecourse/ac501soc/MAINTAINERS b/board/corecourse/ac501soc/MAINTAINERS new file mode 100644 index 00000000000..1feac0c0584 --- /dev/null +++ b/board/corecourse/ac501soc/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA BOARD +M: Brian Sune +S: Maintained +F: board/corecourse/ac501soc/ +F: include/configs/socfpga_ac501soc.h +F: configs/socfpga_ac501soc_defconfig diff --git a/board/corecourse/ac501soc/qts/iocsr_config.h b/board/corecourse/ac501soc/qts/iocsr_config.h new file mode 100644 index 00000000000..cce43c54377 --- /dev/null +++ b/board/corecourse/ac501soc/qts/iocsr_config.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x000C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x80008000, + 0x0000007F, + 0x0001FE00, + 0x07F80000, + 0xE0000000, + 0x0000001F, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x00007F80, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x00000000, + 0x00000010, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x10018060, + 0x00000000, + 0x06000000, + 0x00010018, + 0x01806018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x41034030, + 0x02081A00, + 0x80A280D0, + 0x34030C06, + 0x01A02490, + 0x280D0000, + 0x30C0680A, + 0x00410340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x69A47A05, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A028A, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1EF228A3, + 0x48F4D145, + 0x000352D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0xFE120800, + 0x00000001, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xF228A3D5, + 0xF4D1451E, + 0x03429248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x00FF090C, + 0x00000000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x69A47A05, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0xC0000004, + 0x0000003F, + 0x0000FF00, + 0x03FC0000, + 0xF0000000, + 0x0000000F, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0xE0000002, + 0x0000001F, + 0x00007F80, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0xF0000001, + 0x0000000F, + 0x00003FC0, + 0x00FF0000, + 0xFC000000, + 0x00000003, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x0001FE00, + 0x07F80000, + 0xE0000000, + 0x0000001F, + 0x00004000, +}; + + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/pinmux_config.h b/board/corecourse/ac501soc/qts/pinmux_config.h new file mode 100644 index 00000000000..462cde84565 --- /dev/null +++ b/board/corecourse/ac501soc/qts/pinmux_config.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 1, /* GENERALIO5 */ + 1, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/pll_config.h b/board/corecourse/ac501soc/qts/pll_config.h new file mode 100644 index 00000000000..88e0b2a3776 --- /dev/null +++ b/board/corecourse/ac501soc/qts/pll_config.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CFG_HPS_DBCTRL_STAYOSC1 1 + +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 + +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/sdram_config.h b/board/corecourse/ac501soc/qts/sdram_config.h new file mode 100644 index 00000000000..43cf307847e --- /dev/null +++ b/board/corecourse/ac501soc/qts/sdram_config.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 401 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 12 +#define CALIB_VFIFO_OFFSET 10 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b5 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080471, + 0x10080570, + 0x10090006, + 0x100a0218, + 0x100b0000, + 0x10380400, + 0x10080469, + 0x100804e8, + 0x100a0006, + 0x10090218, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/MAINTAINERS b/board/corecourse/ac550soc/MAINTAINERS new file mode 100644 index 00000000000..c46d8c70702 --- /dev/null +++ b/board/corecourse/ac550soc/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA BOARD +M: Brian Sune +S: Maintained +F: board/corecourse/ac550soc/ +F: include/configs/socfpga_ac550soc.h +F: configs/socfpga_ac550soc_defconfig diff --git a/board/corecourse/ac550soc/qts/iocsr_config.h b/board/corecourse/ac550soc/qts/iocsr_config.h new file mode 100644 index 00000000000..710ab602de6 --- /dev/null +++ b/board/corecourse/ac550soc/qts/iocsr_config.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x000C0300, + 0x300C0000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x20000000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C820D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x802080D0, + 0x34051406, + 0x01A02490, + 0x280D0000, + 0x30C0680A, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x41034051, + 0x02081A00, + 0x80A280D0, + 0x34051406, + 0x01A00040, + 0x080D0002, + 0x51406802, + 0x02490340, + 0xD012481A, + 0x06802080, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0xD9647A05, + 0xBB2CA3D0, + 0xF711451E, + 0x035E9248, + 0x821A0000, + 0x0000D000, + 0x01040680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035ED3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA24, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0xD9647A05, + 0xDA28A3D0, + 0xF711451E, + 0x0340D348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035ED3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA24, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xBB2CA3DF, + 0xF51E791E, + 0x0340D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035E92, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x69A47A06, + 0xDA28A3DF, + 0xF51E791E, + 0x034E9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDF69A47A, + 0x1EDA28A3, + 0x48F51E79, + 0x00034E92, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/pinmux_config.h b/board/corecourse/ac550soc/qts/pinmux_config.h new file mode 100644 index 00000000000..2e8df563141 --- /dev/null +++ b/board/corecourse/ac550soc/qts/pinmux_config.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 0, /* GENERALIO3 */ + 0, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 1, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 1, /* UART1USEFPGA */ + 1, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 1, /* I2C3USEFPGA */ + 1, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/pll_config.h b/board/corecourse/ac550soc/qts/pll_config.h new file mode 100644 index 00000000000..673b9de864f --- /dev/null +++ b/board/corecourse/ac550soc/qts/pll_config.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CFG_HPS_DBCTRL_STAYOSC1 1 + +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 71 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 17 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1800000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 1066666667 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 360000000 +#define CFG_HPS_CLK_SPIM_HZ 12500000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 + +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/sdram_config.h b/board/corecourse/ac550soc/qts/sdram_config.h new file mode 100644 index 00000000000..eae9f57dd9c --- /dev/null +++ b/board/corecourse/ac550soc/qts/sdram_config.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 27 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 187 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 27 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x3FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 534 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 234 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 15 +#define IO_DQS_EN_DELAY_OFFSET 16 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b5 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 132 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 132 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080831, + 0x10080930, + 0x10090006, + 0x100a0208, + 0x100b0000, + 0x10380400, + 0x10080849, + 0x100808c8, + 0x100a0006, + 0x10090210, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 49c13056edc..552349d104a 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -26,8 +26,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - #define ADDR_CPLD_R_RESET ((unsigned short __iomem *)CONFIG_CPLD_BASE) #define ADDR_CPLD_R_ETAT ((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2)) #define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)(CONFIG_CPLD_BASE + 3)) diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index e271d060efa..ab4a484d393 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -14,8 +14,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int board_late_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index a9ef049652a..c6a5740c7a7 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -27,8 +27,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int data_modul_imx_edm_sbc_board_power_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index d6f0a917023..5c319df1cde 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -17,8 +17,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - static void dmo_setup_second_mac_address(void) { u8 enetaddr[6]; diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index f81b7274556..314f7e87a9d 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -28,8 +28,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int data_modul_imx_edm_sbc_board_power_init(void) { struct udevice *dev; diff --git a/board/dhelectronics/dh_imx8mp/Makefile b/board/dhelectronics/dh_imx8mp/Makefile index 7bc8dc21e64..12fb7b71ab6 100644 --- a/board/dhelectronics/dh_imx8mp/Makefile +++ b/board/dhelectronics/dh_imx8mp/Makefile @@ -5,7 +5,7 @@ # ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o +obj-y += spl.o lpddr4_timing_2G_32.o else obj-y += imx8mp_dhcom_pdk2.o endif diff --git a/board/dhelectronics/dh_imx8mp/common.c b/board/dhelectronics/dh_imx8mp/common.c index f6db9f67804..5d89c94970d 100644 --- a/board/dhelectronics/dh_imx8mp/common.c +++ b/board/dhelectronics/dh_imx8mp/common.c @@ -8,8 +8,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - u8 dh_get_memcfg(void) { struct gpio_desc gpio[4]; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 5c35a5bf447..3424be10936 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -20,8 +20,6 @@ #include "../common/dh_common.h" #include "../common/dh_imx.h" -DECLARE_GLOBAL_DATA_PTR; - int mach_cpu_init(void) { icache_enable(); @@ -30,12 +28,11 @@ int mach_cpu_init(void) int board_phys_sdram_size(phys_size_t *size) { - const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK; u8 memcfg = dh_get_memcfg(); /* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */ - *size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0)); + *size = (u64)dh_imx8mp_dhcom_dram_size[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0)); return 0; } diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h index c4d51174a33..5dc841a7f5a 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h @@ -6,12 +6,16 @@ #ifndef __LPDDR4_TIMING_H__ #define __LPDDR4_TIMING_H__ -extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32; -extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32; +static const u16 dh_imx8mp_dhcom_dram_size[] = { + 4096, 1024, 1536, 2048, 3072, 4096, 6144, 8192 +}; -typedef void (*scrub_func_t)(void); -extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void); -extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void); +extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32; +static __maybe_unused struct dram_timing_info *dh_imx8mp_dhcom_dram_timing = + &dh_imx8mp_dhcom_dram_timing_16g_x32; +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void); +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void); +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void); u8 dh_get_memcfg(void); diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c index add7a0bf23b..9574e920352 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c @@ -1854,16 +1854,197 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = { .fsp_table = { 3600, 400, 100, }, }; -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) -void dh_imx8mp_dhcom_dram_scrub_16g_x32(void) +/* + * Convert 2 GiB DRAM settings to 2 GiB DRAM settings. + * This does nothing and is only a placeholder to indicate + * that the 2 GiB DRAM settings are valid themselves. + */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void) { - ddrc_inline_ecc_scrub(0x0,0x3ffffff); - ddrc_inline_ecc_scrub(0x4000000,0x7ffffff); - ddrc_inline_ecc_scrub(0x8000000,0xbffffff); - ddrc_inline_ecc_scrub(0xc000000,0xfffffff); - ddrc_inline_ecc_scrub(0x10000000,0x13ffffff); - ddrc_inline_ecc_scrub(0x14000000,0x17ffffff); - ddrc_inline_ecc_scrub(0x18000000,0x1bffffff); - ddrc_inline_ecc_scrub_end(0x0,0x1fffffff); } + +/* Convert 2 GiB DRAM settings to 4 GiB 2-rank DRAM settings. */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) { + if (ddr_ddrc_cfg[i].reg == 0x3d400000) + ddr_ddrc_cfg[i].val = 0xa3080020; +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x14; + if (ddr_ddrc_cfg[i].reg == 0x3d40020c) + ddr_ddrc_cfg[i].val = 0x14141400; +#else + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x17; #endif + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp0_cfg); i++) { + if (ddr_fsp0_cfg[i].reg == 0x54012) + ddr_fsp0_cfg[i].val = 0x310; + if (ddr_fsp0_cfg[i].reg == 0x5402c) + ddr_fsp0_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) { + if (ddr_fsp1_cfg[i].reg == 0x54012) + ddr_fsp1_cfg[i].val = 0x310; + if (ddr_fsp1_cfg[i].reg == 0x5402c) + ddr_fsp1_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) { + if (ddr_fsp2_cfg[i].reg == 0x54012) + ddr_fsp2_cfg[i].val = 0x310; + if (ddr_fsp2_cfg[i].reg == 0x5402c) + ddr_fsp2_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp0_2d_cfg); i++) { + if (ddr_fsp0_2d_cfg[i].reg == 0x54012) + ddr_fsp0_2d_cfg[i].val = 0x310; + if (ddr_fsp0_2d_cfg[i].reg == 0x5402c) + ddr_fsp0_2d_cfg[i].val = 0x3; + } +}; + +/* Convert 2 GiB DRAM settings to 4 GiB 1-rank DRAM settings. */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) { + if (ddr_ddrc_cfg[i].reg == 0x3d400064) + ddr_ddrc_cfg[i].val = 0x6d0156; + if (ddr_ddrc_cfg[i].reg == 0x3d400138) + ddr_ddrc_cfg[i].val = 0x15d; +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x1f; + if (ddr_ddrc_cfg[i].reg == 0x3d40020c) + ddr_ddrc_cfg[i].val = 0x14141400; +#else + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x17; +#endif + if (ddr_ddrc_cfg[i].reg == 0x3d40021c) + ddr_ddrc_cfg[i].val = 0xf04; + if (ddr_ddrc_cfg[i].reg == 0x3d402024) + ddr_ddrc_cfg[i].val = 0x61a800; + if (ddr_ddrc_cfg[i].reg == 0x3d402064) + ddr_ddrc_cfg[i].val = 0x18004c; + if (ddr_ddrc_cfg[i].reg == 0x3d4020dc) + ddr_ddrc_cfg[i].val = 0x940009; + if (ddr_ddrc_cfg[i].reg == 0x3d402100) + ddr_ddrc_cfg[i].val = 0xc080609; + if (ddr_ddrc_cfg[i].reg == 0x3d402104) + ddr_ddrc_cfg[i].val = 0x3040d; + if (ddr_ddrc_cfg[i].reg == 0x3d402108) + ddr_ddrc_cfg[i].val = 0x3060a0c; + if (ddr_ddrc_cfg[i].reg == 0x3d402110) + ddr_ddrc_cfg[i].val = 0x4040204; + if (ddr_ddrc_cfg[i].reg == 0x3d402114) + ddr_ddrc_cfg[i].val = 0x2030303; + if (ddr_ddrc_cfg[i].reg == 0x3d402138) + ddr_ddrc_cfg[i].val = 0x4e; + if (ddr_ddrc_cfg[i].reg == 0x3d402144) + ddr_ddrc_cfg[i].val = 0x280014; + if (ddr_ddrc_cfg[i].reg == 0x3d402180) + ddr_ddrc_cfg[i].val = 0xc80006; + if (ddr_ddrc_cfg[i].reg == 0x3d402190) + ddr_ddrc_cfg[i].val = 0x3878202; + if (ddr_ddrc_cfg[i].reg == 0x3d4021b4) + ddr_ddrc_cfg[i].val = 0x702; + if (ddr_ddrc_cfg[i].reg == 0x3d403024) + ddr_ddrc_cfg[i].val = 0x493fe1; + if (ddr_ddrc_cfg[i].reg == 0x3d403064) + ddr_ddrc_cfg[i].val = 0x12003a; + if (ddr_ddrc_cfg[i].reg == 0x3d403100) + ddr_ddrc_cfg[i].val = 0xa070507; + if (ddr_ddrc_cfg[i].reg == 0x3d403104) + ddr_ddrc_cfg[i].val = 0x3040a; + if (ddr_ddrc_cfg[i].reg == 0x3d403108) + ddr_ddrc_cfg[i].val = 0x203070b; + if (ddr_ddrc_cfg[i].reg == 0x3d403110) + ddr_ddrc_cfg[i].val = 0x3040203; + if (ddr_ddrc_cfg[i].reg == 0x3d403114) + ddr_ddrc_cfg[i].val = 0x2030303; + if (ddr_ddrc_cfg[i].reg == 0x3d403138) + ddr_ddrc_cfg[i].val = 0x3b; + if (ddr_ddrc_cfg[i].reg == 0x3d403144) + ddr_ddrc_cfg[i].val = 0x1f0010; + if (ddr_ddrc_cfg[i].reg == 0x3d403180) + ddr_ddrc_cfg[i].val = 0x970005; + } + + for (i = 0; i < ARRAY_SIZE(ddr_ddrphy_cfg); i++) { + if (ddr_ddrphy_cfg[i].reg == 0x12002e) + ddr_ddrphy_cfg[i].val = 0x1; + if (ddr_ddrphy_cfg[i].reg == 0x22002e) + ddr_ddrphy_cfg[i].val = 0x1; + if (ddr_ddrphy_cfg[i].reg == 0x120008) + ddr_ddrphy_cfg[i].val = 0xc8; + if (ddr_ddrphy_cfg[i].reg == 0x220008) + ddr_ddrphy_cfg[i].val = 0x96; + if (ddr_ddrphy_cfg[i].reg == 0x200f0) + ddr_ddrphy_cfg[i].val = 0x500; + if (ddr_ddrphy_cfg[i].reg == 0x200f4) + ddr_ddrphy_cfg[i].val = 0x5555; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) { + if (ddr_fsp1_cfg[i].reg == 0x54002) + ddr_fsp1_cfg[i].val = 0x1; + if (ddr_fsp1_cfg[i].reg == 0x54003) + ddr_fsp1_cfg[i].val = 0x320; + if (ddr_fsp1_cfg[i].reg == 0x54019) + ddr_fsp1_cfg[i].val = 0x994; + if (ddr_fsp1_cfg[i].reg == 0x5401f) + ddr_fsp1_cfg[i].val = 0x994; + if (ddr_fsp1_cfg[i].reg == 0x54032) + ddr_fsp1_cfg[i].val = 0x9400; + if (ddr_fsp1_cfg[i].reg == 0x54033) + ddr_fsp1_cfg[i].val = 0xf309; + if (ddr_fsp1_cfg[i].reg == 0x54038) + ddr_fsp1_cfg[i].val = 0x9400; + if (ddr_fsp1_cfg[i].reg == 0x54039) + ddr_fsp1_cfg[i].val = 0xf309; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) { + if (ddr_fsp2_cfg[i].reg == 0x54002) + ddr_fsp2_cfg[i].val = 0x2; + if (ddr_fsp2_cfg[i].reg == 0x54003) + ddr_fsp2_cfg[i].val = 0x258; + if (ddr_fsp2_cfg[i].reg == 0x54019) + ddr_fsp2_cfg[i].val = 0x994; + if (ddr_fsp2_cfg[i].reg == 0x5401f) + ddr_fsp2_cfg[i].val = 0x994; + if (ddr_fsp2_cfg[i].reg == 0x54032) + ddr_fsp2_cfg[i].val = 0x9400; + if (ddr_fsp2_cfg[i].reg == 0x54033) + ddr_fsp2_cfg[i].val = 0xf309; + if (ddr_fsp2_cfg[i].reg == 0x54038) + ddr_fsp2_cfg[i].val = 0x9400; + if (ddr_fsp2_cfg[i].reg == 0x54039) + ddr_fsp2_cfg[i].val = 0xf309; + } + + for (i = 0; i < ARRAY_SIZE(ddr_phy_pie); i++) { + if (ddr_phy_pie[i].reg == 0x12000b) + ddr_phy_pie[i].val = 0xe1; + if (ddr_phy_pie[i].reg == 0x12000c) + ddr_phy_pie[i].val = 0x32; + if (ddr_phy_pie[i].reg == 0x12000d) + ddr_phy_pie[i].val = 0x1f4; + if (ddr_phy_pie[i].reg == 0x22000b) + ddr_phy_pie[i].val = 0xa8; + if (ddr_phy_pie[i].reg == 0x22000c) + ddr_phy_pie[i].val = 0x25; + if (ddr_phy_pie[i].reg == 0x22000d) + ddr_phy_pie[i].val = 0x177; + } +}; diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c deleted file mode 100644 index 41b078f6e9f..00000000000 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c +++ /dev/null @@ -1,1873 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Marek Vasut - * - * Generated code from MX8M_DDR_tool - */ - -#include -#include - -static struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa3080020 }, - { 0x3d400020, 0x1323 }, - { 0x3d400024, 0x1b77400 }, - { 0x3d400064, 0x6d00fc }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400070, 0x7027fd4 }, -#else - { 0x3d400070, 0x7027f90 }, -#endif - { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00306df }, - { 0x3d4000d4, 0xb10000 }, - { 0x3d4000dc, 0xe40036 }, - { 0x3d4000e0, 0xf30000 }, - { 0x3d4000e8, 0x660048 }, - { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x1d241e26 }, - { 0x3d400104, 0x70739 }, - { 0x3d40010c, 0xd0d000 }, - { 0x3d400110, 0x11040911 }, - { 0x3d400114, 0x2050e0e }, - { 0x3d400118, 0x1010008 }, - { 0x3d40011c, 0x502 }, - { 0x3d400130, 0x20700 }, - { 0x3d400134, 0xd100002 }, - { 0x3d400138, 0x103 }, - { 0x3d400144, 0xb4005a }, - { 0x3d400180, 0x384001b }, - { 0x3d400184, 0x2d06ddd }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820c }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0c }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x7 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0x799 }, - { 0x3d400108, 0x8121b1a }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400200, 0x14 }, -#else - { 0x3d400200, 0x17 }, -#endif - { 0x3d400208, 0x0 }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d40020c, 0x14141400 }, -#else - { 0x3d40020c, 0x0 }, -#endif - { 0x3d400210, 0x1f1f }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400204, 0x50505 }, - { 0x3d400214, 0x4040404 }, - { 0x3d400218, 0x4040404 }, -#else - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, -#endif - { 0x3d40021c, 0xf0f }, - { 0x3d400250, 0x1705 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1021 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0xf30000 }, - { 0x3d4020e8, 0x660048 }, - { 0x3d4020ec, 0x160048 }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x302 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0x599 }, - { 0x3d403020, 0x1021 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0xf30000 }, - { 0x3d4030e8, 0x660048 }, - { 0x3d4030ec, 0x160048 }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x302 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0x599 }, - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x1 }, - { 0x130a2, 0x2 }, - { 0x130a3, 0x3 }, - { 0x130a4, 0x4 }, - { 0x130a5, 0x5 }, - { 0x130a6, 0x6 }, - { 0x130a7, 0x7 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x20056, 0x3 }, - { 0x120056, 0x3 }, - { 0x220056, 0x3 }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x384 }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x1 }, - { 0x12002d, 0x1 }, - { 0x22002d, 0x1 }, - { 0x2007d, 0x212 }, - { 0x12007d, 0x212 }, - { 0x22007d, 0x212 }, - { 0x2007c, 0x61 }, - { 0x12007c, 0x61 }, - { 0x22007c, 0x61 }, - { 0x2002c, 0x0 }, -}; - -/* ddr phy trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -/* P0 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xe10 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0xf336 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0xf336 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0xf300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0xf300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0xf300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0xf300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xe10 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0xf336 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0xf336 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xb }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x633 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x633 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x633 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x633 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x633 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x633 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x633 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x633 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x633 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x633 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x633 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x633 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x633 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xb }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x1 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x625 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x625 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a4, 0x0 }, - { 0x900a5, 0x790 }, - { 0x900a6, 0x11a }, - { 0x900a7, 0x8 }, - { 0x900a8, 0x7aa }, - { 0x900a9, 0x2a }, - { 0x900aa, 0x10 }, - { 0x900ab, 0x7b2 }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x0 }, - { 0x900ae, 0x7c8 }, - { 0x900af, 0x109 }, - { 0x900b0, 0x10 }, - { 0x900b1, 0x10 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x1 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xd }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x8 }, - { 0x90159, 0xe8 }, - { 0x9015a, 0x109 }, - { 0x9015b, 0x0 }, - { 0x9015c, 0x8140 }, - { 0x9015d, 0x10c }, - { 0x9015e, 0x10 }, - { 0x9015f, 0x8138 }, - { 0x90160, 0x104 }, - { 0x90161, 0x8 }, - { 0x90162, 0x448 }, - { 0x90163, 0x109 }, - { 0x90164, 0xf }, - { 0x90165, 0x7c0 }, - { 0x90166, 0x109 }, - { 0x90167, 0x0 }, - { 0x90168, 0xe8 }, - { 0x90169, 0x109 }, - { 0x9016a, 0x47 }, - { 0x9016b, 0x630 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0x8 }, - { 0x9016e, 0x618 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x8 }, - { 0x90171, 0xe0 }, - { 0x90172, 0x109 }, - { 0x90173, 0x0 }, - { 0x90174, 0x7c8 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x8140 }, - { 0x90178, 0x10c }, - { 0x90179, 0x0 }, - { 0x9017a, 0x478 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x1 }, - { 0x9017e, 0x8 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x4 }, - { 0x90181, 0x0 }, - { 0x90006, 0x8 }, - { 0x90007, 0x7c8 }, - { 0x90008, 0x109 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x400 }, - { 0x9000b, 0x106 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x29 }, - { 0x90026, 0x68 }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x200be, 0x3 }, - { 0x2000b, 0x3f4 }, - { 0x2000c, 0xe1 }, - { 0x2000d, 0x8ca }, - { 0x2000e, 0x2c }, - { 0x12000b, 0x70 }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x1c }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x2060 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3600mts 1D */ - .drate = 3600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3600mts 2D */ - .drate = 3600, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3600, 400, 100, }, -}; - -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) -void dh_imx8mp_dhcom_dram_scrub_32g_x32(void) -{ - ddrc_inline_ecc_scrub(0x0,0x7ffffff); - ddrc_inline_ecc_scrub(0x8000000,0xfffffff); - ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); - ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); - ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); - ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); - ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); - ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); -} -#endif diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 714f846521e..aab8550023e 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -29,8 +29,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) @@ -106,34 +104,36 @@ static int dh_imx8mp_board_power_init(void) return 0; } -static struct dram_timing_info *dram_timing_info[8] = { - NULL, /* 512 MiB */ - NULL, /* 1024 MiB */ - NULL, /* 1536 MiB */ - &dh_imx8mp_dhcom_dram_timing_16g_x32, /* 2048 MiB */ - NULL, /* 3072 MiB */ - &dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */ - NULL, /* 6144 MiB */ - NULL, /* 8192 MiB */ +typedef void (*patch_func_t)(void); + +static const patch_func_t dram_patch_fn[8] = { + dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r, /* 4096 MiB 1-rank */ + NULL, /* 1024 MiB */ + NULL, /* 1536 MiB */ + dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32, /* 2048 MiB */ + NULL, /* 3072 MiB */ + dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r, /* 4096 MiB 2-rank */ + NULL, /* 6144 MiB */ + NULL, /* 8192 MiB */ }; static void spl_dram_init(void) { - const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; u8 memcfg = dh_get_memcfg(); int i; - printf("DDR: %d MiB [0x%x]\n", size[memcfg], memcfg); + printf("DDR: %d MiB [0x%x]\n", dh_imx8mp_dhcom_dram_size[memcfg], memcfg); - if (!dram_timing_info[memcfg]) { + if (!dram_patch_fn[memcfg]) { printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n", memcfg); - for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++) - if (dram_timing_info[i]) /* Configuration found */ + for (i = 0; i < ARRAY_SIZE(dram_patch_fn); i++) + if (dram_patch_fn[i]) /* Configuration found */ break; } - ddr_init(dram_timing_info[memcfg]); + dram_patch_fn[memcfg](); + ddr_init(dh_imx8mp_dhcom_dram_timing); printf("DDR: Inline ECC %sabled\n", (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ? @@ -141,13 +141,39 @@ static void spl_dram_init(void) } #if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) +static void dh_imx8mp_dhcom_dram_scrub_16g_x32(void) +{ + ddrc_inline_ecc_scrub(0x0,0x3ffffff); + ddrc_inline_ecc_scrub(0x4000000,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xbffffff); + ddrc_inline_ecc_scrub(0xc000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x13ffffff); + ddrc_inline_ecc_scrub(0x14000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1bffffff); + ddrc_inline_ecc_scrub_end(0x0,0x1fffffff); +} + +static void dh_imx8mp_dhcom_dram_scrub_32g_x32(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} + +typedef void (*scrub_func_t)(void); + static const scrub_func_t dram_scrub_fn[8] = { - NULL, /* 512 MiB */ + dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB 1-rank */ NULL, /* 1024 MiB */ NULL, /* 1536 MiB */ dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */ NULL, /* 3072 MiB */ - dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */ + dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB 2-rank */ NULL, /* 6144 MiB */ NULL, /* 8192 MiB */ }; diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.env b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env index c19fe08648a..326023274e9 100644 --- a/board/emcraft/imx8mp_navqp/imx8mp_navqp.env +++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.env @@ -11,7 +11,7 @@ image=Image console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 fdt_addr_r=0x43000000 boot_fdt=try -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE initrd_addr=0x43800000 bootm_size=0x10000000 mmcpart=1 diff --git a/board/emcraft/imx8mp_navqp/spl.c b/board/emcraft/imx8mp_navqp/spl.c index 7f30f3af742..5ee94d078f8 100644 --- a/board/emcraft/imx8mp_navqp/spl.c +++ b/board/emcraft/imx8mp_navqp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 97c8211c100..ce5bc34ca71 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -15,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_MTD_NOR_FLASH) int is_flash_available(void) { diff --git a/board/engicam/imx8mm/icore_mx8mm.c b/board/engicam/imx8mm/icore_mx8mm.c index 236337546ae..bb70e7d4ff8 100644 --- a/board/engicam/imx8mm/icore_mx8mm.c +++ b/board/engicam/imx8mm/icore_mx8mm.c @@ -19,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_FEC_MXC) #define FEC_RST_PAD IMX_GPIO_NR(3, 7) diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index d51ae241e85..702f0caafab 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -54,11 +52,6 @@ int board_fit_config_name_match(const char *name) } #endif -int board_early_init_f(void) -{ - return 0; -} - void board_init_f(ulong dummy) { int ret; @@ -67,8 +60,6 @@ void board_init_f(ulong dummy) init_uart_clk(1); - board_early_init_f(); - timer_init(); /* Clear the BSS. */ diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index bfdc447c478..864afa92aee 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c index cd31aa6041d..46c581ea51f 100644 --- a/board/engicam/imx8mp/spl.c +++ b/board/engicam/imx8mp/spl.c @@ -12,20 +12,14 @@ #include #include #include -#include #include #include #include #include -#include -#include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -36,36 +30,22 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); #ifdef CONFIG_IMX8M_LPDDR4 /* @@ -76,22 +56,22 @@ int power_init_board(void) */ #ifdef CONFIG_IMX8M_VDD_SOC_850MV /* set DVS0 to 0.85v for special case*/ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); #else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); #endif - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Kernel uses OD/OD freq for SOC */ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); #elif defined(CONFIG_IMX8M_DDR4) /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set NVCC_DRAM to 1.2v for DDR4 */ - pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18); + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18); #endif return 0; @@ -139,8 +119,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c index 05e4d84460a..123dda21423 100644 --- a/board/gdsys/mpc8308/gazerbeam.c +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -17,13 +17,10 @@ #include #include #include -#include #include "../common/ihs_mdio.h" #include "../../../drivers/sysinfo/gazerbeam.h" -DECLARE_GLOBAL_DATA_PTR; - struct ihs_mdio_info ihs_mdio_info[] = { { .fpga = NULL, .name = "ihs0", .base = 0x58 }, { .fpga = NULL, .name = "ihs1", .base = 0x58 }, diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c index 9544d6dd19a..2f16f1da26c 100644 --- a/board/google/imx8mq_phanbell/imx8mq_phanbell.c +++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS index 67341b5d556..382ad212569 100644 --- a/board/google/veyron/MAINTAINERS +++ b/board/google/veyron/MAINTAINERS @@ -1,7 +1,6 @@ CHROMEBOOK JERRY BOARD M: Simon Glass S: Maintained -F: arch/arm/dts/rk3288-veyron-jerry.dts F: arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -10,7 +9,6 @@ F: configs/chromebook_jerry_defconfig CHROMEBIT MICKEY BOARD M: Simon Glass S: Maintained -F: arch/arm/dts/rk3288-veyron-mickey.dts F: arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -19,7 +17,6 @@ F: configs/chromebit_mickey_defconfig CHROMEBOOK MINNIE BOARD M: Simon Glass S: Maintained -F: arch/arm/dts/rk3288-veyron-minnie.dts F: arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -28,7 +25,6 @@ F: configs/chromebook_minnie_defconfig CHROMEBOOK SPEEDY BOARD M: Simon Glass S: Maintained -F: arch/arm/dts/rk3288-veyron-speedy.dts F: arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi F: board/google/veyron/ F: include/configs/veyron.h @@ -37,8 +33,4 @@ F: configs/chromebook_speedy_defconfig CHROMEBOOK VEYRON COMMON FILES M: Simon Glass S: Maintained -F: arch/arm/dts/rk3288-veyron.dtsi -F: arch/arm/dts/rk3288-veyron-analog-audio.dtsi -F: arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi -F: arch/arm/dts/rk3288-veyron-chromebook.dtsi -F: arch/arm/dts/rk3288-veyron-edp.dtsi +F: arch/arm/dts/rk3288-veyron-u-boot.dtsi diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 0ec88447384..62a7b5b0420 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -37,8 +36,6 @@ #define HB_SCU_A9_PWR_DORMANT 2 #define HB_SCU_A9_PWR_OFF 3 -DECLARE_GLOBAL_DATA_PTR; - void cphy_disable_overrides(void); /* diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index c21b083b62a..4dc7b608f0f 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c b/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c index 3db7176f723..739a78d2c8b 100644 --- a/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c +++ b/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include "../common/hw-uid.h" -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_KONTRON_HW_UID) struct uid_otp_loc uid_otp_locations[] = { { diff --git a/board/kontron/osm-s-mx93/osm-s-mx93.c b/board/kontron/osm-s-mx93/osm-s-mx93.c index d4645285771..02bee34ac66 100644 --- a/board/kontron/osm-s-mx93/osm-s-mx93.c +++ b/board/kontron/osm-s-mx93/osm-s-mx93.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -23,13 +22,6 @@ #include "../common/hw-uid.h" -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - return 0; -} - #if IS_ENABLED(CONFIG_KONTRON_HW_UID) struct uid_otp_loc uid_otp_locations[] = { { diff --git a/board/kontron/osm-s-mx93/spl.c b/board/kontron/osm-s-mx93/spl.c index 23a90e351fe..a47fc43c6aa 100644 --- a/board/kontron/osm-s-mx93/spl.c +++ b/board/kontron/osm-s-mx93/spl.c @@ -132,8 +132,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - spl_early_init(); preloader_console_init(); diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c index 2ee97169c6f..f71fa57b808 100644 --- a/board/kontron/pitx_imx8m/pitx_imx8m.c +++ b/board/kontron/pitx_imx8m/pitx_imx8m.c @@ -15,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/lg/star/star.c b/board/lg/star/star.c index 0b4a433a5df..ab700cbe828 100644 --- a/board/lg/star/star.c +++ b/board/lg/star/star.c @@ -46,6 +46,8 @@ void pinmux_init(void) #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *fdt, struct bd_info *bd) { - return star_fix_panel(fdt); + star_fix_panel(fdt); + + return 0; } #endif diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c index c4b6c37e495..dc683bd082a 100644 --- a/board/liebherr/btt/btt.c +++ b/board/liebherr/btt/btt.c @@ -393,9 +393,9 @@ int board_fdt_blob_setup(void **fdtp) int board_fit_config_name_match(const char *name) { u8 rev_id = get_som_rev(); - char board[12]; + char board[15]; - sprintf(board, "imx28-btt3-%d", rev_id); + sprintf(board, "imx28-btt3-%u", rev_id); if (!strncmp(name, board, sizeof(board))) return 0; diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS new file mode 100644 index 00000000000..446a9e8e53c --- /dev/null +++ b/board/mediatek/MAINTAINERS @@ -0,0 +1,20 @@ +MT8365 EVK +M: Julien Masson +S: Maintained +F: configs/mt8365_evk_defconfig + +MT8370 EVK +M: Macpaul Lin +S: Maintained +F: configs/mt8370_evk_defconfig + +MT8390 EVK +M: Julien Masson +M: Macpaul Lin +S: Maintained +F: configs/mt8390_evk_defconfig + +MT8395 EVK +M: Macpaul Lin +S: Maintained +F: configs/mt8395_evk_defconfig diff --git a/board/mediatek/mt7622/Makefile b/board/mediatek/mt7622/Makefile index 64f101337bf..35f3136e833 100644 --- a/board/mediatek/mt7622/Makefile +++ b/board/mediatek/mt7622/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-y += mt7622_rfb.o +obj-y += diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c deleted file mode 100644 index 405f393aade..00000000000 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 MediaTek Inc. - * Author: Sam Shih - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; diff --git a/board/mediatek/mt8365_evk/MAINTAINERS b/board/mediatek/mt8365_evk/MAINTAINERS deleted file mode 100644 index e0d65efe812..00000000000 --- a/board/mediatek/mt8365_evk/MAINTAINERS +++ /dev/null @@ -1,5 +0,0 @@ -MT8365 EVK -M: Julien Masson -S: Maintained -F: board/mediatek/mt8365_evk/ -F: configs/mt8365_evk_defconfig diff --git a/board/mediatek/mt8365_evk/mt8365_evk.c b/board/mediatek/mt8365_evk/mt8365_evk.c deleted file mode 100644 index 41a6febf03d..00000000000 --- a/board/mediatek/mt8365_evk/mt8365_evk.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 BayLibre SAS - * Author: Julien Masson - */ - -#include - -static struct mm_region mt8365_evk_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0xc0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8365_evk_mem_map; diff --git a/board/mediatek/mt8390_evk/MAINTAINERS b/board/mediatek/mt8390_evk/MAINTAINERS deleted file mode 100644 index d46b8b2e156..00000000000 --- a/board/mediatek/mt8390_evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MT8390 EVK -M: Julien Masson -M: Macpaul Lin -S: Maintained -F: board/mediatek/mt8390_evk/ -F: configs/mt8390_evk_defconfig diff --git a/board/mediatek/mt8390_evk/Makefile b/board/mediatek/mt8390_evk/Makefile deleted file mode 100644 index a26d46838c4..00000000000 --- a/board/mediatek/mt8390_evk/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-y += mt8390_evk.o diff --git a/board/mediatek/mt8390_evk/mt8390_evk.c b/board/mediatek/mt8390_evk/mt8390_evk.c deleted file mode 100644 index 1ca40366a55..00000000000 --- a/board/mediatek/mt8390_evk/mt8390_evk.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2026 BayLibre SAS - * Author: Julien Masson - */ - -#include -#include - -int board_init(void) -{ - return 0; -} - -static struct mm_region mt8390_evk_mem_map[] = { - { - /* DDR */ - .virt = 0x40000000UL, - .phys = 0x40000000UL, - .size = 0x200000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, - }, { - .virt = 0x00000000UL, - .phys = 0x00000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - 0, - } -}; - -struct mm_region *mem_map = mt8390_evk_mem_map; diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig index d38e56c742d..3640cf69f3a 100644 --- a/board/microchip/mpfs_generic/Kconfig +++ b/board/microchip/mpfs_generic/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_MMC imply DOS_PARTITION imply EFI_PARTITION - imply IP_DYN imply ISO_PARTITION imply PHY_LIB imply PHY_VITESSE diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c index 6ee1c5c52a1..bcb31564a73 100644 --- a/board/mntre/imx8mq_reform2/imx8mq_reform2.c +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) static iomux_v3_cfg_t const wdog_pads[] = { diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c index b1ce014bd55..b2f763dcc02 100644 --- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -18,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c index b1b5561838d..902179aad29 100644 --- a/board/msc/sm2s_imx8mp/spl.c +++ b/board/msc/sm2s_imx8mp/spl.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -33,8 +32,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/nxp/common/emc2305.c b/board/nxp/common/emc2305.c index 50252bb5007..7e5151eaf5f 100644 --- a/board/nxp/common/emc2305.c +++ b/board/nxp/common/emc2305.c @@ -4,15 +4,13 @@ * */ +#include #include #include -#include #include #include "emc2305.h" -DECLARE_GLOBAL_DATA_PTR; - void set_fan_speed(u8 data, int chip_addr) { u8 index; diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env index 299b8472c74..d59bd6fd5ed 100644 --- a/board/nxp/imx8mm_evk/imx8mm_evk.env +++ b/board/nxp/imx8mm_evk/imx8mm_evk.env @@ -6,7 +6,7 @@ boot_targets=mmc1 mmc2 dhcp bootm_size=0x10000000 console=ttymxc1,115200 fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x49000000 initrd_addr=0x48080000 image=Image diff --git a/board/nxp/imx8mm_evk/spl.c b/board/nxp/imx8mm_evk/spl.c index cd251d274ff..50bae3a2bcc 100644 --- a/board/nxp/imx8mm_evk/spl.c +++ b/board/nxp/imx8mm_evk/spl.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -28,8 +27,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -109,8 +106,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); - timer_init(); /* Clear the BSS. */ diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env index 487893f9287..cffa83bf792 100644 --- a/board/nxp/imx8mn_evk/imx8mn_evk.env +++ b/board/nxp/imx8mn_evk/imx8mn_evk.env @@ -6,7 +6,7 @@ boot_targets=mmc1 mmc2 dhcp bootm_size=0x10000000 console=ttymxc1,115200 fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x49000000 initrd_addr=0x48080000 image=Image diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.c b/board/nxp/imx8mp_evk/imx8mp_evk.c index 489e5ad4d43..e17100e51ec 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.c +++ b/board/nxp/imx8mp_evk/imx8mp_evk.c @@ -28,6 +28,13 @@ struct efi_capsule_update_info update_info = { }; #endif /* EFI_HAVE_CAPSULE_SUPPORT */ +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) +int board_mmc_get_env_dev(int devno) +{ + return devno; +} +#endif + int board_late_init(void) { #if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env index 18cdf3da056..e994b93b168 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.env +++ b/board/nxp/imx8mp_evk/imx8mp_evk.env @@ -7,7 +7,7 @@ bootm_size=0x10000000 console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 fdt_addr_r=0x43000000 fdt_addr=0x43000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image ip_dyn=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c index 5b4aac42830..27cd82e745a 100644 --- a/board/nxp/imx8mp_evk/spl.c +++ b/board/nxp/imx8mp_evk/spl.c @@ -102,8 +102,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); - ret = spl_early_init(); if (ret) { debug("spl_init() failed: %d\n", ret); diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env index cab8c6b70bf..6575dd7cb07 100644 --- a/board/nxp/imx8mq_evk/imx8mq_evk.env +++ b/board/nxp/imx8mq_evk/imx8mq_evk.env @@ -5,7 +5,7 @@ boot_targets=mmc1 mmc2 dhcp bootm_size=0x10000000 console=ttymxc0,115200 fdt_addr_r=0x43000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE initrd_addr=0x43800000 image=Image ip_dyn=yes diff --git a/board/nxp/imx8qm_mek/imx8qm_mek.c b/board/nxp/imx8qm_mek/imx8qm_mek.c index 72527f774ca..56f577714e7 100644 --- a/board/nxp/imx8qm_mek/imx8qm_mek.c +++ b/board/nxp/imx8qm_mek/imx8qm_mek.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/nxp/imx8qxp_mek/imx8qxp_mek.c b/board/nxp/imx8qxp_mek/imx8qxp_mek.c index adb9556a021..4bf6645b893 100644 --- a/board/nxp/imx8qxp_mek/imx8qxp_mek.c +++ b/board/nxp/imx8qxp_mek/imx8qxp_mek.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.c b/board/nxp/imx8ulp_evk/imx8ulp_evk.c index cc34ecdec20..f4e85efb931 100644 --- a/board/nxp/imx8ulp_evk/imx8ulp_evk.c +++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.c @@ -101,11 +101,6 @@ int board_init(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_late_init(void) { ulong addr; diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.env b/board/nxp/imx8ulp_evk/imx8ulp_evk.env index 52d7f447029..da97631e03e 100644 --- a/board/nxp/imx8ulp_evk/imx8ulp_evk.env +++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.env @@ -23,7 +23,7 @@ mmcdev=CONFIG_SYS_MMC_ENV_DEV mmcpart=1 image=Image cntr_file=os_cntr_signed.bin -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE console=ttyLP1,115200 earlycon bootm_size=0x10000000 boot_fit=no diff --git a/board/nxp/imx8ulp_evk/spl.c b/board/nxp/imx8ulp_evk/spl.c index 162b3a1a2e0..2d52e16007d 100644 --- a/board/nxp/imx8ulp_evk/spl.c +++ b/board/nxp/imx8ulp_evk/spl.c @@ -74,8 +74,6 @@ void spl_board_init(void) if (ret) return; - board_early_init_f(); - preloader_console_init(); puts("Normal Boot\n"); diff --git a/board/nxp/imx91_evk/imx91_evk.env b/board/nxp/imx91_evk/imx91_evk.env index 6c10784cf61..d669c6e3133 100644 --- a/board/nxp/imx91_evk/imx91_evk.env +++ b/board/nxp/imx91_evk/imx91_evk.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx91_frdm/imx91_frdm.env b/board/nxp/imx91_frdm/imx91_frdm.env index b0450ff576c..557e508bd6a 100644 --- a/board/nxp/imx91_frdm/imx91_frdm.env +++ b/board/nxp/imx91_frdm/imx91_frdm.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env index d5ed216f54b..b2ed1901a2b 100644 --- a/board/nxp/imx93_evk/imx93_evk.env +++ b/board/nxp/imx93_evk/imx93_evk.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx93_frdm/imx93_frdm.c b/board/nxp/imx93_frdm/imx93_frdm.c index fb78a9bd036..e187de74a72 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.c +++ b/board/nxp/imx93_frdm/imx93_frdm.c @@ -90,11 +90,6 @@ static int clear_pd_alert(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { return 0; diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env index 111f38ed72a..9af3bdfd714 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.env +++ b/board/nxp/imx93_frdm/imx93_frdm.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=1 mmcpart=1 diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c index 006c752d071..068091ba0e9 100644 --- a/board/nxp/imx93_frdm/spl.c +++ b/board/nxp/imx93_frdm/spl.c @@ -156,8 +156,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - spl_early_init(); preloader_console_init(); diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env index 6c10784cf61..d669c6e3133 100644 --- a/board/nxp/imx93_qsb/imx93_qsb.env +++ b/board/nxp/imx93_qsb/imx93_qsb.env @@ -8,7 +8,7 @@ cntr_file=os_cntr_signed.bin console=ttyLP0,115200 earlycon fdt_addr_r=0x83000000 fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE image=Image mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c index 2aeb21c1de7..4731b79b55d 100644 --- a/board/nxp/imx94_evk/imx94_evk.c +++ b/board/nxp/imx94_evk/imx94_evk.c @@ -26,10 +26,3 @@ int board_late_init(void) return 0; } - -int board_phys_sdram_size(phys_size_t *size) -{ - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; - - return 0; -} diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env index 2baf1bbadcb..894f5975812 100644 --- a/board/nxp/imx94_evk/imx94_evk.env +++ b/board/nxp/imx94_evk/imx94_evk.env @@ -28,7 +28,7 @@ fdt_addr=0x93000000 cntr_addr=0xA8000000 cntr_file=os_cntr_signed.bin boot_fit=no -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE bootm_size=0x10000000 mmcdev=CONFIG_SYS_MMC_ENV_DEV mmcautodetect=yes diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c index cc5b7f9ef0f..6eb0fff99f4 100644 --- a/board/nxp/imx94_evk/spl.c +++ b/board/nxp/imx94_evk/spl.c @@ -46,6 +46,16 @@ void spl_board_init(void) printf("Fail to start RNG: %d\n", ret); } +static void xspi_nor_reset(void) +{ + int ret; + u32 resp = 0; + + ret = ele_set_gmid(&resp); + if (ret) + printf("Fail to set GMID: %d, resp 0x%x\n", ret, resp); +} + /* SCMI support by default */ void board_init_f(ulong dummy) { @@ -76,5 +86,7 @@ void board_init_f(ulong dummy) get_reset_reason(true, false); + xspi_nor_reset(); + board_init_r(NULL, 0); } diff --git a/board/nxp/imx952_evk/Kconfig b/board/nxp/imx952_evk/Kconfig new file mode 100644 index 00000000000..96f01323aca --- /dev/null +++ b/board/nxp/imx952_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX952_EVK + +config SYS_BOARD + default "imx952_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx952_evk" + +endif diff --git a/board/nxp/imx952_evk/MAINTAINERS b/board/nxp/imx952_evk/MAINTAINERS new file mode 100644 index 00000000000..cc004f9467e --- /dev/null +++ b/board/nxp/imx952_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX952 EVK BOARD +M: Alice Guo +S: Maintained +F: board/nxp/imx952_evk/ +F: include/configs/imx952_evk.h +F: configs/imx952_evk_defconfig diff --git a/board/nxp/imx952_evk/Makefile b/board/nxp/imx952_evk/Makefile new file mode 100644 index 00000000000..1581721dc78 --- /dev/null +++ b/board/nxp/imx952_evk/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2025-2026 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Add include path for NXP device tree header files from Linux. +ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/ + +obj-y += imx952_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c new file mode 100644 index 00000000000..2a61817939e --- /dev/null +++ b/board/nxp/imx952_evk/imx952_evk.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025-2026 NXP + */ + +#include +#include +#include + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env new file mode 100644 index 00000000000..6ecaf9724c1 --- /dev/null +++ b/board/nxp/imx952_evk/imx952_evk.env @@ -0,0 +1,137 @@ +#ifdef CONFIG_ANDROID_SUPPORT +splashpos=m,m +splashimage=0x9FFF0000 +emmc_dev=0 +sd_dev=1 +#else + +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_root_dtb=imx952-evk-root.dtb +jh_mmcboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; + setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000; + if run loadimage; then + run mmcboot; + else run jh_netboot; fi; +jh_netboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; + +domu-android-auto=no +xenhyper_bootargs=console=dtuart dom0_mem=4096M dom0_max_vcpus=2 pci-passthrough=on +xenlinux_bootargs= +xenlinux_console=hvc0 earlycon=xen +xenlinux_addr=0x9c000000 +dom0fdt_file=CONFIG_DEFAULT_FDT_FILE +xenboot_common=${get_cmd} ${loadaddr} xen; + ${get_cmd} ${fdt_addr} ${dom0fdt_file}; + ${get_cmd} ${xenlinux_addr} ${image}; + fdt addr ${fdt_addr}; + fdt resize 256; + fdt mknode /chosen module@0; + fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; + fdt set /chosen/module@0 bootargs "${bootargs} ${xenlinux_bootargs}"; + fdt set /soc/bus@49000000/iommu@490d0000 status disabled; + fdt set /chosen/module@0 compatible "xen,linux-zimage" "xen,multiboot-module"; + setenv bootargs ${xenhyper_bootargs}; + booti ${loadaddr} - ${fdt_addr}; +xennetboot=setenv get_cmd dhcp;setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run netargs;run xenboot_common; +xenmmcboot=setenv get_cmd "fatload mmc ${mmcdev}:${mmcpart}";setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run mmcargs;run xenboot_common; + +sr_ir_v2_cmd=cp.b ${fdtcontroladdr} ${fdt_addr_r} 0x10000; fdt addr ${fdt_addr_r}; + fdt set /soc/bus@44000000/mailbox@445b0000/sram@445b1000/scmi-sram-section@0 reg <0x00000000 0x00000080>; + fdt rm /soc/mailbox@47530000; + fdt rm /soc/usb@4c010010; + +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_args pd_ignore_unused; +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; + +#endif diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c new file mode 100644 index 00000000000..de9256dc267 --- /dev/null +++ b/board/nxp/imx952_evk/spl.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025-2026 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + case USB2_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +static void xspi_nor_reset(void) +{ + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("GPIO5_11", &desc); + if (ret) { + printf("%s lookup GPIO5_11 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "XSPI_RST_B"); + if (ret) { + printf("%s request XSPI_RST_B failed ret = %d\n", __func__, ret); + return; + } + + /* assert the XSPI_RST_B */ + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + udelay(200); /* 50 ns at least, so use 200ns */ + dm_gpio_set_value(&desc, 0); /* deassert the XSPI_RST_B */ +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_SPL_RECOVER_DATA_SECTION + if (IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); +#endif + + timer_init(); + + /* Need dm_init() to run before any SCMI calls can be made. */ + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + xspi_nor_reset(); + + board_init_r(NULL, 0); +} + +#ifdef CONFIG_ANDROID_SUPPORT +int board_get_emmc_id(void) +{ + return 0; +} +#endif diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c index 620a69b53e5..99a37e0593f 100644 --- a/board/nxp/imx95_evk/imx95_evk.c +++ b/board/nxp/imx95_evk/imx95_evk.c @@ -14,10 +14,3 @@ int board_late_init(void) return 0; } - -int board_phys_sdram_size(phys_size_t *size) -{ - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; - - return 0; -} diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env index a7309d734b0..19f9bd5c16e 100644 --- a/board/nxp/imx95_evk/imx95_evk.env +++ b/board/nxp/imx95_evk/imx95_evk.env @@ -12,7 +12,7 @@ fdt_addr=0x93000000 cntr_addr=0xA8000000 cntr_file=os_cntr_signed.bin boot_fit=no -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE bootm_size=0x10000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcautodetect=yes diff --git a/board/nxp/mx6sllevk/mx6sllevk.c b/board/nxp/mx6sllevk/mx6sllevk.c index 9e39e39ac90..3d2397c52c1 100644 --- a/board/nxp/mx6sllevk/mx6sllevk.c +++ b/board/nxp/mx6sllevk/mx6sllevk.c @@ -76,11 +76,6 @@ int power_init_board(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* Address of boot parameters */ diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c index d80cfd4ab27..ac91da3f4f6 100644 --- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -199,11 +199,6 @@ int board_ehci_hcd_init(int port) } #endif -int board_early_init_f(void) -{ - return 0; -} - #ifdef CONFIG_FSL_QSPI int board_qspi_init(void) { diff --git a/board/nxp/mx6ullevk/mx6ullevk.c b/board/nxp/mx6ullevk/mx6ullevk.c index 189eddefea3..7a02b571c56 100644 --- a/board/nxp/mx6ullevk/mx6ullevk.c +++ b/board/nxp/mx6ullevk/mx6ullevk.c @@ -41,11 +41,6 @@ int mmc_map_to_kernel_blk(int devno) return devno; } -int board_early_init_f(void) -{ - return 0; -} - #ifdef CONFIG_FEC_MXC static int setup_fec(int fec_id) { diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index b2bb6678c23..78136c1620a 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -13,9 +13,6 @@ #include #include #include -#ifdef CONFIG_LED_STATUS -#include -#endif #include DECLARE_GLOBAL_DATA_PTR; @@ -61,9 +58,5 @@ int board_init(void) /* Adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_STATE); -#endif - return 0; } diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig index e4bd8903aab..b646aa8cbb2 100644 --- a/board/openpiton/riscv64/Kconfig +++ b/board/openpiton/riscv64/Kconfig @@ -31,7 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply RISCV_TIMER imply SPL_RISCV_ACLINT imply CMD_CPU - imply SPL_CPU_SUPPORT + imply SPL_CPU imply SPL_SMP imply SPL_MMC imply SMP diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c index 10469aecd0b..b55e92fb051 100644 --- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -16,11 +16,6 @@ int dram_init(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - static int setup_fec_clock(void) { if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) { diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index a72f66ee3f5..6afd03086f7 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -19,13 +19,13 @@ config PHYTEC_IMX8M_SOM_DETECTION Support of I2C EEPROM based SoM detection. Supported for PHYTEC i.MX8MM/i.MX8MP boards -config PHYTEC_IMX93_SOM_DETECTION - bool "Support SoM detection for i.MX93 PHYTEC platforms" +config PHYTEC_IMX91_93_SOM_DETECTION + bool "Support SoM detection for i.MX91/93 PHYTEC platforms" depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION default y help Support of I2C EEPROM based SoM detection. Supported - for PHYTEC i.MX93 based boards + for PHYTEC i.MX91/93 based boards config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 948f9dab626..e09dea01d49 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -10,4 +10,4 @@ endif obj-y += phytec_som_detection.o phytec_som_detection_blocks.o obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o -obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o +obj-$(CONFIG_ARCH_IMX9) += imx91_93_som_detection.o diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx91_93_som_detection.c similarity index 56% rename from board/phytec/common/imx93_som_detection.c rename to board/phytec/common/imx91_93_som_detection.c index eb9574d43b5..bcc5500ae9f 100644 --- a/board/phytec/common/imx93_som_detection.c +++ b/board/phytec/common/imx91_93_som_detection.c @@ -10,18 +10,19 @@ #include #include -#include "imx93_som_detection.h" +#include "imx91_93_som_detection.h" extern struct phytec_eeprom_data eeprom_data; -#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) +#if IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) /* Check if the SoM is actually one of the following products: + * - i.MX91 * - i.MX93 * * Returns 0 in case it's a known SoM. Otherwise, returns 1. */ -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) { u8 som; @@ -35,7 +36,7 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) som = data->payload.data.data_api2.som_no; debug("%s: som id: %u\n", __func__, som); - if (som == PHYTEC_IMX93_SOM && is_imx93()) + if (som == PHYTEC_IMX91_93_SOM && (is_imx91() || is_imx93())) return 0; pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); @@ -43,15 +44,15 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) } /* - * Filter PHYTEC i.MX93 SoM options by option index + * Filter PHYTEC i.MX91/93 SoM options by option index * * Returns: * - option value * - PHYTEC_EEPROM_INVAL when the data is invalid * */ -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) { char *opt; u8 opt_id; @@ -73,39 +74,41 @@ u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, } /* - * Filter PHYTEC i.MX93 SoM voltage + * Filter PHYTEC i.MX91/93 SoM voltage * * Returns: - * - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3 + * - PHYTEC_IMX91_93_VOLTAGE_1V8 or PHYTEC_IMX91_93_VOLTAGE_3V3 * - PHYTEC_EEPROM_INVAL when the data is invalid * */ -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data) +enum phytec_imx91_93_voltage __maybe_unused +phytec_imx91_93_get_voltage(struct phytec_eeprom_data *data) { - u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT); + u8 option = phytec_imx91_93_get_opt(data, PHYTEC_IMX91_93_OPT_FEAT); if (option == PHYTEC_EEPROM_INVAL) - return PHYTEC_IMX93_VOLTAGE_INVALID; - return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3; + return PHYTEC_IMX91_93_VOLTAGE_INVALID; + return (option & 0x01) ? PHYTEC_IMX91_93_VOLTAGE_1V8 : + PHYTEC_IMX91_93_VOLTAGE_3V3; } #else -inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) { return 1; } -inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) +inline u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) { return PHYTEC_EEPROM_INVAL; } -inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage +inline enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage (struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */ +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) */ diff --git a/board/phytec/common/imx91_93_som_detection.h b/board/phytec/common/imx91_93_som_detection.h new file mode 100644 index 00000000000..05ea4cf0868 --- /dev/null +++ b/board/phytec/common/imx91_93_som_detection.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +#ifndef _PHYTEC_IMX91_93_SOM_DETECTION_H +#define _PHYTEC_IMX91_93_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX91_93_SOM 77 + +enum phytec_imx91_93_option_index { + PHYTEC_IMX91_93_OPT_DDR = 0, + PHYTEC_IMX91_93_OPT_EMMC = 1, + PHYTEC_IMX91_93_OPT_CPU = 2, + PHYTEC_IMX91_93_OPT_FREQ = 3, + PHYTEC_IMX91_93_OPT_NPU = 4, + PHYTEC_IMX91_93_OPT_DISP = 5, + PHYTEC_IMX91_93_OPT_ETH = 6, + PHYTEC_IMX91_93_OPT_FEAT = 7, + PHYTEC_IMX91_93_OPT_TEMP = 8, + PHYTEC_IMX91_93_OPT_BOOT = 9, + PHYTEC_IMX91_93_OPT_LED = 10, + PHYTEC_IMX91_93_OPT_EEPROM = 11, +}; + +enum phytec_imx91_93_voltage { + PHYTEC_IMX91_93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_VOLTAGE_3V3 = 0, + PHYTEC_IMX91_93_VOLTAGE_1V8 = 1, +}; + +enum phytec_imx91_93_ddr_eeprom_code { + PHYTEC_IMX91_93_DDR_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_LPDDR4X_512MB = 0, + PHYTEC_IMX91_93_LPDDR4X_1GB = 1, + PHYTEC_IMX91_93_LPDDR4X_2GB = 2, + PHYTEC_IMX91_93_LPDDR4_512MB = 3, + PHYTEC_IMX91_93_LPDDR4_1GB = 4, + PHYTEC_IMX91_93_LPDDR4_2GB = 5, +}; + +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx); +enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage + (struct phytec_eeprom_data *data); + +#endif /* _PHYTEC_IMX91_93_SOM_DETECTION_H */ diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h deleted file mode 100644 index a0803b47cbe..00000000000 --- a/board/phytec/common/imx93_som_detection.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - * Author: Primoz Fiser - */ - -#ifndef _PHYTEC_IMX93_SOM_DETECTION_H -#define _PHYTEC_IMX93_SOM_DETECTION_H - -#include "phytec_som_detection.h" - -#define PHYTEC_IMX93_SOM 77 - -enum phytec_imx93_option_index { - PHYTEC_IMX93_OPT_DDR = 0, - PHYTEC_IMX93_OPT_EMMC = 1, - PHYTEC_IMX93_OPT_CPU = 2, - PHYTEC_IMX93_OPT_FREQ = 3, - PHYTEC_IMX93_OPT_NPU = 4, - PHYTEC_IMX93_OPT_DISP = 5, - PHYTEC_IMX93_OPT_ETH = 6, - PHYTEC_IMX93_OPT_FEAT = 7, - PHYTEC_IMX93_OPT_TEMP = 8, - PHYTEC_IMX93_OPT_BOOT = 9, - PHYTEC_IMX93_OPT_LED = 10, - PHYTEC_IMX93_OPT_EEPROM = 11, -}; - -enum phytec_imx93_voltage { - PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_VOLTAGE_3V3 = 0, - PHYTEC_IMX93_VOLTAGE_1V8 = 1, -}; - -enum phytec_imx93_ddr_eeprom_code { - PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_LPDDR4X_512MB = 0, - PHYTEC_IMX93_LPDDR4X_1GB = 1, - PHYTEC_IMX93_LPDDR4X_2GB = 2, - PHYTEC_IMX93_LPDDR4_512MB = 3, - PHYTEC_IMX93_LPDDR4_1GB = 4, - PHYTEC_IMX93_LPDDR4_2GB = 5, -}; - -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data); -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx); -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage - (struct phytec_eeprom_data *data); - -#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */ diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env index f064bbe3d31..7ea7bde86a1 100644 --- a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env @@ -2,7 +2,7 @@ boot_script_dhcp=net_boot_fit.scr.uimg console=ttymxc3,CONFIG_BAUDRATE emmc_dev=2 /* This is needed by built-in uuu flash scripts */ fdt_addr_r=0x40480000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x404a0000 ip_dyn=yes kernel_addr_r=0x40a00000 diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c index d704d588579..aa22ad0030c 100644 --- a/board/phytec/imx8mp-libra-fpsc/spl.c +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -8,11 +8,7 @@ #include #include #include -#include #include -#include -#include -#include #include #include #include @@ -24,8 +20,6 @@ #include "../common/imx8m_som_detection.h" #endif -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 int spl_board_boot_device(enum boot_device boot_dev_spl) @@ -49,45 +43,32 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(0, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } @@ -123,8 +104,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index eeb7cd6899a..e7b9cc0791c 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -13,7 +13,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml index 0f34b8c1bc0..38bcd46e7e7 100644 --- a/board/phytec/phycore_am62ax/rm-cfg.yaml +++ b/board/phytec/phycore_am62ax/rm-cfg.yaml @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 1038 - num_resource: 497 + num_resource: 496 type: 1805 host_id: 128 reserved: 0 diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index eeb7cd6899a..e7b9cc0791c 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -13,7 +13,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_am62x/rm-cfg.yaml b/board/phytec/phycore_am62x/rm-cfg.yaml index 26d99b03b80..f800fb28a69 100644 --- a/board/phytec/phycore_am62x/rm-cfg.yaml +++ b/board/phytec/phycore_am62x/rm-cfg.yaml @@ -525,7 +525,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 67d2b87f144..6cfe64e676f 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -12,7 +12,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_am68x/phycore_am68x.env b/board/phytec/phycore_am68x/phycore_am68x.env index 4908055b542..0c61e645c88 100644 --- a/board/phytec/phycore_am68x/phycore_am68x.env +++ b/board/phytec/phycore_am68x/phycore_am68x.env @@ -7,7 +7,7 @@ ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 fit_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE mmcdev=1 mmcroot=2 mmcpart=1 diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index f6ae0bf0308..9f6a4ec704d 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -5,14 +5,11 @@ */ #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index f6d0c0553b5..7cd601f8cd5 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -2,7 +2,7 @@ boot_script_dhcp=net_boot_fit.scr.uimg console=ttymxc2,CONFIG_BAUDRATE emmc_dev=2 /* This is needed by built-in uuu flash scripts */ fdt_addr_r=0x40480000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x404a0000 ip_dyn=yes kernel_addr_r=0x40a00000 diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index faff064779c..e688793bc74 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index b345dc7c985..5f0a7ee6a94 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -17,8 +16,6 @@ #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index c339c315c30..652761d1f99 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -4,7 +4,7 @@ emmc_dev=2 /* This is needed by built-in uuu flash scripts */ fastboot_raw_partition_all=0 4194304 fastboot_raw_partition_bootloader=64 8128 fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x49000000 ip_dyn=yes kernel_addr_r=0x5A080000 diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index cb8e450b995..fc6f5104925 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 @@ -120,45 +117,32 @@ out: ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(0, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } @@ -196,8 +180,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/phytec/phycore_imx91_93/Kconfig b/board/phytec/phycore_imx91_93/Kconfig new file mode 100644 index 00000000000..87fd915e5a8 --- /dev/null +++ b/board/phytec/phycore_imx91_93/Kconfig @@ -0,0 +1,47 @@ + +if TARGET_PHYCORE_IMX91 || TARGET_PHYCORE_IMX93 + +config SYS_BOARD + default "phycore_imx91_93" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_imx91_93" + +config PHYCORE_IMX91_93_RAM_TYPE_FIX + bool "Set phyCORE-i.MX91/93 RAM type and size fix instead of detecting" + default false + help + RAM type and size is being automatically detected with the help + of the PHYTEC EEPROM introspection data. + Set RAM type to a fix value instead. + +choice + prompt "phyCORE-i.MX91/93 RAM type" + depends on PHYCORE_IMX91_93_RAM_TYPE_FIX + default PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB + bool "LPDDR4 1GB RAM" + help + Set RAM type fixed to LPDDR4 and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + bool "LPDDR4X 1GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB + bool "LPDDR4X 2GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB + for phyCORE-i.MX91/93. + +endchoice + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/phycore_imx91_93/MAINTAINERS b/board/phytec/phycore_imx91_93/MAINTAINERS new file mode 100644 index 00000000000..573d1c36a5e --- /dev/null +++ b/board/phytec/phycore_imx91_93/MAINTAINERS @@ -0,0 +1,16 @@ +phyCORE-i.MX91/93 +M: Mathieu Othacehe +R: Christoph Stoidner +L: upstream@lists.phytec.de +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ +S: Maintained +F: arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi +F: arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi +F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +F: board/phytec/phycore_imx91_93/ +F: board/phytec/common/imx91_93_som_detection.c +F: board/phytec/common/imx91_93_som_detection.h +F: configs/imx91-phycore_defconfig +F: configs/imx93-phycore_defconfig +F: include/configs/phycore_imx91_93.h +F: doc/board/phytec/imx91-93-phycore.rst diff --git a/board/phytec/phycore_imx93/Makefile b/board/phytec/phycore_imx91_93/Makefile similarity index 58% rename from board/phytec/phycore_imx93/Makefile rename to board/phytec/phycore_imx91_93/Makefile index dd5085e160f..976ecb306f7 100644 --- a/board/phytec/phycore_imx93/Makefile +++ b/board/phytec/phycore_imx91_93/Makefile @@ -7,8 +7,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += phycore-imx93.o +obj-y += phycore-imx91-93.o ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4_timing.o +obj-y += spl.o +ifdef CONFIG_IMX91 +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx91.o +else +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx93.o +endif endif diff --git a/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c new file mode 100644 index 00000000000..ddc8094f080 --- /dev/null +++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c @@ -0,0 +1,1998 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x13542110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E88CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00A000A0}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00A0180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010A1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABA0068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x004C004C}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0x61f}, + {0x10149, 0x61f}, + {0x11049, 0x61f}, + {0x11149, 0x61f}, + {0x110049, 0x61f}, + {0x110149, 0x61f}, + {0x111049, 0x61f}, + {0x111149, 0x61f}, + {0x210049, 0x61f}, + {0x210149, 0x61f}, + {0x211049, 0x61f}, + {0x211149, 0x61f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x104}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x104}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x104}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x2352}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x2352}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a00}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a00}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x2309}, + {0x54034, 0x4400}, + {0x54035, 0x49}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x2309}, + {0x5403a, 0x4400}, + {0x5403b, 0x49}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c similarity index 100% rename from board/phytec/phycore_imx93/lpddr4_timing.c rename to board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx91_93/phycore-imx91-93.c similarity index 80% rename from board/phytec/phycore_imx93/phycore-imx93.c rename to board/phytec/phycore_imx91_93/phycore-imx91-93.c index cfc6d91f20f..2605a3bd09e 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx91_93/phycore-imx91-93.c @@ -7,14 +7,11 @@ */ #include -#include #include #include #include -#include "../common/imx93_som_detection.h" - -DECLARE_GLOBAL_DATA_PTR; +#include "../common/imx91_93_som_detection.h" #define EEPROM_ADDR 0x50 @@ -44,6 +41,11 @@ int board_late_init(void) case MMC1_BOOT: env_set_ulong("mmcdev", 0); break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) + env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); + break; default: break; } @@ -53,13 +55,13 @@ int board_late_init(void) static void emmc_fixup(void *blob, struct phytec_eeprom_data *data) { - enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data); + enum phytec_imx91_93_voltage voltage = phytec_imx91_93_get_voltage(data); int offset; - if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID) + if (voltage == PHYTEC_IMX91_93_VOLTAGE_INVALID) goto err; - if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) { + if (voltage == PHYTEC_IMX91_93_VOLTAGE_1V8) { offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc", 0x42850000); if (offset) diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx91_93/phycore_imx91_93.env similarity index 89% rename from board/phytec/phycore_imx93/phycore_imx93.env rename to board/phytec/phycore_imx91_93/phycore_imx91_93.env index 4e89c4ae26c..a39359869d6 100644 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ b/board/phytec/phycore_imx91_93/phycore_imx91_93.env @@ -4,11 +4,13 @@ boot_script_dhcp=net_boot_fit.scr.uimg console=ttyLP0 emmc_dev=0 /* This is needed by built-in uuu flash scripts */ fdt_addr_r=0x90000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE fdtoverlay_addr_r=0x900c0000 ip_dyn=yes kernel_addr_r=0x88000000 nfsroot=/srv/nfs +#ifdef CONFIG_IMX93 prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" +#endif scriptaddr=0x83500000 sd_dev=1 /* This is needed by built-in uuu flash scripts */ diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx91_93/spl.c similarity index 75% rename from board/phytec/phycore_imx93/spl.c rename to board/phytec/phycore_imx91_93/spl.c index aa7d562911a..92441c5af32 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx91_93/spl.c @@ -19,7 +19,7 @@ #include #include -#include "../common/imx93_som_detection.h" +#include "../common/imx91_93_som_detection.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,32 +50,38 @@ void spl_board_init(void) void spl_dram_init(void) { int ret; - enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; + enum phytec_imx91_93_ddr_eeprom_code ddr_opt = PHYTEC_IMX91_93_DDR_INVALID; ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); - if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) goto out; - ret = phytec_imx93_detect(NULL); + ret = phytec_imx91_93_detect(NULL); if (!ret) phytec_print_som_info(NULL); - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) { - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB; - else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB; + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_2GB; } else { - ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR); + ddr_opt = phytec_imx91_93_get_opt(NULL, PHYTEC_IMX91_93_OPT_DDR); } switch (ddr_opt) { - case PHYTEC_IMX93_LPDDR4X_1GB: - if (is_voltage_mode(VOLT_LOW_DRIVE)) + case PHYTEC_IMX91_93_LPDDR4_1GB: + /* Timings statically set for i.MX91 LPDDR4 1GB. */ + break; + case PHYTEC_IMX91_93_LPDDR4X_1GB: + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); break; - case PHYTEC_IMX93_LPDDR4X_2GB: - set_dram_timings_2gb_lpddr4x(); + case PHYTEC_IMX91_93_LPDDR4X_2GB: + if (IS_ENABLED(CONFIG_IMX93)) + set_dram_timings_2gb_lpddr4x(); break; default: goto out; @@ -84,7 +90,7 @@ void spl_dram_init(void) return; out: puts("Could not detect correct RAM type and size. Fall back to default.\n"); - if (is_voltage_mode(VOLT_LOW_DRIVE)) + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); ddr_init(&dram_timing); } @@ -185,10 +191,12 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); - /* Put M33 into CPUWAIT for following kick */ - ret = m33_prepare(); - if (!ret) - printf("M33 prepare ok\n"); + if (IS_ENABLED(CONFIG_IMX93)) { + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + } board_init_r(NULL, 0); } diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig deleted file mode 100644 index 09f26e89e33..00000000000 --- a/board/phytec/phycore_imx93/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ - -if TARGET_PHYCORE_IMX93 - -config SYS_BOARD - default "phycore_imx93" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "phycore_imx93" - -config PHYCORE_IMX93_RAM_TYPE_FIX - bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting" - default false - help - RAM type and size is being automatically detected with the help - of the PHYTEC EEPROM introspection data. - Set RAM type to a fix value instead. - -choice - prompt "phyCORE-i.MX93 RAM type" - depends on PHYCORE_IMX93_RAM_TYPE_FIX - default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - bool "LPDDR4X 1GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB - for phyCORE-i.MX93. - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB - bool "LPDDR4X 2GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB - for phyCORE-i.MX93. - -endchoice - -source "board/phytec/common/Kconfig" -endif diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS deleted file mode 100644 index 0b087bf1ef2..00000000000 --- a/board/phytec/phycore_imx93/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -phyCORE-i.MX93 -M: Mathieu Othacehe -R: Christoph Stoidner -L: upstream@lists.phytec.de -W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ -S: Maintained -F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi -F: board/phytec/phycore_imx93/ -F: board/phytec/common/imx93_som_detection.c -F: board/phytec/common/imx93_som_detection.h -F: configs/imx93-phycore_defconfig -F: include/configs/phycore_imx93.h diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c index c709d017483..7f0925074fa 100644 --- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c index 6cbd1815cad..c154ad7a1ce 100644 --- a/board/polyhex/imx8mp_debix_model_a/spl.c +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 5178ee6929d..3640ef232c8 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -31,13 +31,6 @@ #include #include "librem5.h" -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - return 0; -} - #if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION) uint board_mmc_get_env_part(struct mmc *mmc) { diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index ed57554a2bc..a104ee5c2aa 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -29,8 +29,6 @@ #include #include "librem5.h" -DECLARE_GLOBAL_DATA_PTR; - void spl_dram_init(void) { /* ddr init */ @@ -549,8 +547,6 @@ void board_init_f(ulong dummy) gpio_direction_output(WIFI_EN, 1); #endif - board_early_init_f(); - timer_init(); preloader_console_init(); diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index 4698b9d5e3e..36e4d49046e 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -15,13 +15,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static u32 msm_board_serial(void) { struct mmc *mmc_dev; diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index 12a9273ec4b..236022a99f1 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ /* Strength (sdc1) */ #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) -DECLARE_GLOBAL_DATA_PTR; - static void sdhci_power_init(void) { const u32 TLMM_PULL_MASK = 0x3; diff --git a/board/renesas/common/gen3-common.c b/board/renesas/common/gen3-common.c index 94da00985d3..5c543807b64 100644 --- a/board/renesas/common/gen3-common.c +++ b/board/renesas/common/gen3-common.c @@ -12,14 +12,12 @@ #include #include #include -#include #include #include #include +#include #include -DECLARE_GLOBAL_DATA_PTR; - /* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ extern u64 rcar_atf_boot_args[]; diff --git a/board/renesas/common/gen4-common.c b/board/renesas/common/gen4-common.c index 38fba7a5ea7..ac87f2f08e3 100644 --- a/board/renesas/common/gen4-common.c +++ b/board/renesas/common/gen4-common.c @@ -8,16 +8,14 @@ #include #include #include -#include #include #include #include #include +#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static void init_generic_timer(void) { const u32 freq = CONFIG_SYS_CLK_FREQ; diff --git a/board/renesas/common/gen5-common.c b/board/renesas/common/gen5-common.c index a05a3e8abef..c60a76c5038 100644 --- a/board/renesas/common/gen5-common.c +++ b/board/renesas/common/gen5-common.c @@ -5,15 +5,13 @@ #include #include -#include #include #include #include #include +#include #include -DECLARE_GLOBAL_DATA_PTR; - static void init_generic_timer(void) { const u32 freq = CONFIG_SYS_CLK_FREQ; diff --git a/board/rockchip/evb_rk3288/MAINTAINERS b/board/rockchip/evb_rk3288/MAINTAINERS index 9857ae33575..60f97d7eb3b 100644 --- a/board/rockchip/evb_rk3288/MAINTAINERS +++ b/board/rockchip/evb_rk3288/MAINTAINERS @@ -1,12 +1,10 @@ EVB-RK3288 M: Lin Huang S: Maintained -F: arch/arm/dts/rk3288-evb.dts -F: arch/arm/dts/rk3288-evb.dtsi -F: arch/arm/dts/rk3288-evb-u-boot.dtsi +F: arch/arm/dts/rk3288-evb-rk808-u-boot.dtsi F: board/rockchip/evb_rk3288 F: include/configs/evb_rk3288.h -F: configs/evb-rk3288_defconfig +F: configs/evb-rk3288-rk808_defconfig ROCK-PI-N8 M: Jagan Teki diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c b/board/rockchip/evb_rk3308/evb_rk3308.c index c895da934a9..75536fe117d 100644 --- a/board/rockchip/evb_rk3308/evb_rk3308.c +++ b/board/rockchip/evb_rk3308/evb_rk3308.c @@ -4,9 +4,8 @@ */ #include -#include - -DECLARE_GLOBAL_DATA_PTR; +#include +#include #define KEY_DOWN_MIN_VAL 0 #define KEY_DOWN_MAX_VAL 30 diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index 602216854ba..e41cfefe375 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -10,8 +10,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 68edd1ec282..2ba2d6330fd 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -36,8 +35,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static int exynos_set_regulator(const char *name, uint uv) { struct udevice *dev; diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index c134a9d70e2..85e564f27ee 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -37,8 +36,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SET_DFU_ALT_INFO void set_dfu_alt_info(char *interface, char *devstr) { diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index fe230971e97..d6d1aad75b2 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -1,5 +1,7 @@ if TARGET_CAPRICORN +config HUSH_INIT_VAR + def_bool y config SYS_BOARD default "capricorn" diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 390a7b0d841..ba6c96a409c 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -5,6 +5,7 @@ * Copyright 2019 Siemens AG * */ +#include #include #include #include @@ -29,6 +30,7 @@ #include "../common/board.h" #include "../common/eeprom.h" #include "../common/factoryset.h" +#include #define GPIO_PAD_CTRL \ ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ @@ -355,16 +357,6 @@ int board_mmc_get_env_dev(int devno) return devno; } -static int check_mmc_autodetect(void) -{ - char *autodetect_str = env_get("mmcautodetect"); - - if (autodetect_str && (strcmp(autodetect_str, "yes") == 0)) - return 1; - - return 0; -} - /* This should be defined for each board */ __weak int mmc_map_to_kernel_blk(int dev_no) { @@ -373,24 +365,46 @@ __weak int mmc_map_to_kernel_blk(int dev_no) void board_late_mmc_env_init(void) { - char cmd[32]; - char mmcblk[32]; u32 dev_no = mmc_get_env_dev(); - if (!check_mmc_autodetect()) - return; - env_set_ulong("mmcdev", dev_no); - - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", - mmc_map_to_kernel_blk(dev_no)); - env_set("mmcroot", mmcblk); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); } +#if defined(CONFIG_HUSH_INIT_VAR) +int hush_init_var(void) +{ + sc_misc_bt_t boot_type; + + if (sc_misc_get_boot_type(-1, &boot_type) != 0) { + puts("boottype cannot be retrieved\n"); + return 0; + } + + /* + * Set here explicitly a hush shell variable, so if a saveenv + * happens, this variable is *not* saved in U-Boot environment. + * + * This is for devices which are already in the field essential, + * as if such a device breaks, the cutsomer gets a new device + * with a new U-Boot version (and so a new U-Boot environment). + * + * But the customer makes a downgrade to an older U-Boot version, + * which does not have this code in, and runs now with a new + * U-Boot Environment (yes, protected Environment is not enabled + * there) and the old U-Boot must still work with the new U-Boot + * Environment. So we cannot store this variable in U-Boot + * Environment as a stored value will in this case never be over- + * written. + */ + if (boot_type == 1) { + printf("boot-container fallback ocured\n"); + set_local_var("fallback=1", 0); + } + + return 0; +} +#endif + #ifndef CONFIG_XPL_BUILD static int load_parameters_from_factoryset(void) { diff --git a/board/siemens/capricorn/capricorn_default.env b/board/siemens/capricorn/capricorn_default.env index c8b5b3d7da3..10d612b04fe 100644 --- a/board/siemens/capricorn/capricorn_default.env +++ b/board/siemens/capricorn/capricorn_default.env @@ -1,17 +1,23 @@ -altbootcmd=run bootcmd +terminate_upgrade=bootcount reset; setenv upgrade_available 0 +altbootcmd=run terminate_upgrade; run toggle_partition baudrate=115200 bootcmd=run flash_self;reset; bootdelay=3 bootdir=targetdir/rootfs/boot bootlimit=3 -check_upgrade=if test ${upgrade_available} -eq 1; then echo upgrade_available is set; if test ${bootcount} -gt ${bootlimit}; then setenv upgrade_available 0;echo toggle partition;run toggle_partition;fi;fi; cntr_addr=0x88000000 cntr_file=os_cntr_signed.bin console=ttyLP2 dtb_name_default=default ethprime=eth1 fdt_addr=0x83000000 -flash_self=run mmc_boot +flash_self=if test -n "$fallback";then + echo "fallback: $fallback"; + run terminate_upgrade; + run toggle_partition; + else + run mmc_boot; + fi flash_self_test=setenv testargs test loglevel=3 systemd.unit=test.target; run mmc_boot hostname=capricorn initrd_addr=0x83100000 @@ -19,30 +25,88 @@ initrd_high=0xffffffffffffffff ip_method=none kernel_name=Image loadaddr=0x80400000 -mmc_boot=run set_bootargs;run check_upgrade; run set_partition;run set_bootargs_mmc;run mmc_load_bootfiles -mmc_boot_fit=ext4load mmc 0:${mmc_part_nr} 0x88000000 boot/fitImage;if test -n ${A};then setenv bootargs ${bootargs} rootfs_sig=${sig_a};fi;if test -n ${B};then setenv bootargs ${bootargs} rootfs_sig=${sig_b};fi;bootm 0x88000000#conf-${dtb_name}.dtb;bootm -mmc_boot_image=ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name}.dtb;if test $? -eq 1;then ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name_default}.dtb;fi; ext4load mmc 0:${mmc_part_nr} ${loadaddr} boot/${kernel_name}; booti ${loadaddr} - ${fdt_addr} -mmc_load_bootfiles=echo -n Loading from eMMC ...; if test -e mmc 0:${mmc_part_nr} boot/fitImage; then echo fit; setenv fdt_high; setenv initrd_high; run mmc_boot_fit; else echo image; run mmc_boot_image; fi -net_nfs=wdt dev scu-wdt; wdt stop; echo Booting from network ...; run set_bootargs_net; tftpboot ${loadaddr} ${bootdir}/${kernel_name}; printenv bootargs; if test ${kernel_name} = fitImage; then setenv fdt_high; setenv initrd_high; bootm ${loadaddr}#conf-${dtb_name}.dtb; else tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name}.dtb; if test $? -eq 1; then echo Loading default.dtb!; tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name_default}.dtb; fi; booti ${loadaddr} - ${fdt_addr}; fi -net_unfs=setenv nfsopts vers=3,udp,rsize=4096,wsize=4096,nolock,port=3049,mountport=3048 rw; run net_nfs -netdev=lan0 +mmc_boot=run set_bootargs; run set_partition;run set_bootargs_mmc;run mmc_load_bootfiles +mmc_boot_fit=ext4load mmc 0:${mmc_part_nr} 0x88000000 boot/fitImage; + if test -n ${A};then + setenv bootargs ${bootargs} rootfs_sig=${sig_a}; + fi; + if test -n ${B};then + setenv bootargs ${bootargs} rootfs_sig=${sig_b}; + fi; + bootm 0x88000000#conf-${dtb_name}.dtb;bootm 0x88000000 +mmc_boot_image=ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name}.dtb; + if test $? -eq 1;then + ext4load mmc 0:${mmc_part_nr} ${fdt_addr} boot/${dtb_name_default}.dtb; + fi; + ext4load mmc 0:${mmc_part_nr} ${loadaddr} boot/${kernel_name}; + booti ${loadaddr} - ${fdt_addr} +mmc_load_bootfiles=echo -n Loading from eMMC ...; + if test -e mmc 0:${mmc_part_nr} boot/fitImage; then + echo fit; setenv fdt_high; setenv initrd_high; run mmc_boot_fit; + else + echo image; run mmc_boot_image; + fi +net_nfs=wdt dev scu-wdt; wdt stop; echo Booting from network ...; + run set_bootargs_net; tftpboot ${loadaddr} ${bootdir}/${kernel_name}; + printenv bootargs; + if test ${kernel_name} = fitImage; then + setenv fdt_high; setenv initrd_high; + bootm ${loadaddr}#conf-${dtb_name}.dtb; + else + tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name}.dtb; + if test $? -eq 1; then + echo Loading default.dtb!; + tftpboot ${fdt_addr} ${serverip}:${bootdir}/${dtb_name_default}.dtb; + fi; + booti ${loadaddr} - ${fdt_addr}; + fi +net_unfs=setenv nfsopts vers=3,udp,rsize=4096,wsize=4096,nolock,port=3049,mountport=3048 rw; + run net_nfs +netdev=eth0 nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw partitionset_active=A rootfs_name=/dev/mmcblk0 rootpath=/home/projects/targetdir/rootfs script_file=u-boot-commands.img -set_bootargs_mmc=setenv bootargs ${bootargs} root=${mmc_active_vol} ro rootdelay=1 rootwait rootfstype=ext4 ip=${ip_method} -set_bootargs_net=run set_bootargs; if test ${kernel_name} = fitImage; then setenv loadaddr 0x88000000; fi; setenv bootargs ${bootargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off -set_bootargs=setenv bootargs console=${console},${baudrate} target_env=${target_env} ${testargs} ${optargs} -set_partition=setenv ${partitionset_active} true;if test -n ${A}; then setenv mmc_part_nr 1;fi;if test -n ${B}; then setenv mmc_part_nr 2;fi;setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} -tftp_run_script=tftpboot ${kernel_loadaddr} ${serverip}:${script_file};if test $? -eq 0;then source ${kernel_loadaddr};fi -toggle_partition=setenv ${partitionset_active} true; if test -n ${A}; then setenv partitionset_active B; mmc partconf 0 1 2 0; env delete A; fi; if test -n ${B}; then setenv partitionset_active A; mmc partconf 0 1 1 0; env delete B; fi;saveenv; reset +set_bootargs_mmc=setenv bootargs ${bootargs} root=${mmc_active_vol} ro rootdelay=1 + rootwait rootfstype=ext4 ip=${ip_method} +set_bootargs_net=run set_bootargs; + if test ${kernel_name} = fitImage; then + setenv loadaddr 0x88000000; + fi; + setenv bootargs ${bootargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} + ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off +set_bootargs=setenv bootargs console=${console},${baudrate} target_env=${target_env} ${testargs} + ${optargs} +set_partition=mmc partconf 0 v_mmc_part_nr; setenv mmc_part_nr $v_mmc_part_nr; + setenv mmc_active_vol ${rootfs_name}p$v_mmc_part_nr +tftp_run_script=tftpboot ${kernel_loadaddr} ${serverip}:${script_file}; + if test $? -eq 0;then + source ${kernel_loadaddr}; + fi +toggle_partition=mmc partconf 0 v_mmc_part_nr; + if test $v_mmc_part_nr -eq 1;then + mmc partconf 0 1 2 0; setenv partitionset_active B; + elif test $v_mmc_part_nr -eq 2;then + mmc partconf 0 1 1 0; setenv partitionset_active A; + else + echo error mmc_part_nr $v_mmc_part_nr; + fi; + saveenv;reset upgrade_available=0 emmc_dev=0 sd_dev=1 mfgtool_args=setenv bootargs console=${console},${baudrate} rdinit=/linuxrc clk_ignore_unused kboot=booti -bootcmd_mfg=run mfgtool_args; if iminfo ${initrd_addr}; then if test ${tee} = yes; then bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; else booti ${loadaddr} ${initrd_addr} ${fdt_addr}; fi; else echo "Run fastboot ..."; fastboot usb auto; fi; +bootcmd_mfg=run mfgtool_args; + if iminfo ${initrd_addr}; then + if test ${tee} = yes; then + bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; + else + booti ${loadaddr} ${initrd_addr} ${fdt_addr}; + fi; + else + echo "Run fastboot ..."; fastboot usb auto; + fi; fastboot_bytes=124c00 fastboot_dev=mmc -mmcautodetect=yes diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig index bf4a00d6f7f..36cf756e3f3 100644 --- a/board/sifive/unleashed/Kconfig +++ b/board/sifive/unleashed/Kconfig @@ -35,13 +35,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FAT imply CMD_FS_GENERIC imply CMD_GPT - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply CMD_NET imply CMD_PING imply CMD_SF imply DOS_PARTITION imply EFI_PARTITION - imply IP_DYN imply ISO_PARTITION imply PHY_LIB imply PHY_MSCC diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig index 991dd23f1d4..9245873927b 100644 --- a/board/sifive/unmatched/Kconfig +++ b/board/sifive/unmatched/Kconfig @@ -36,13 +36,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FAT imply CMD_FS_GENERIC imply CMD_GPT - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply CMD_NET imply CMD_PING imply CMD_SF imply DOS_PARTITION imply EFI_PARTITION - imply IP_DYN imply ISO_PARTITION imply PHY_LIB imply PHY_MSCC diff --git a/board/sifive/unmatched/unmatched.env b/board/sifive/unmatched/unmatched.env index 34425dc9efa..f309229481b 100644 --- a/board/sifive/unmatched/unmatched.env +++ b/board/sifive/unmatched/unmatched.env @@ -16,4 +16,4 @@ partitions= name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1}; name=loader2,size=4MB,type=${type_guid_gpt_loader2}; name=system,size=-,bootable,type=${type_guid_gpt_system}; -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=DEFAULT_FDT_FILE diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 4b0defda1ec..333b78c27f3 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 88c825334a8..feba46d38e4 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -8,13 +8,10 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 7aab7f71d0c..d153efdc2b4 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -8,13 +8,10 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 07bc8a5f0a2..4b1e443100d 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { #ifndef CONFIG_XPL_BUILD diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index d00f55379c5..6c5c6710926 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index d00f55379c5..6c5c6710926 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c index 645685a64f1..24a229bf0a2 100644 --- a/board/st/stm32h747-disco/stm32h747-disco.c +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -8,9 +8,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 31c85c6816e..244bb5eefb3 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig index 2186a939646..b4bf59676ac 100644 --- a/board/starfive/visionfive2/Kconfig +++ b/board/starfive/visionfive2/Kconfig @@ -44,9 +44,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply DOS_PARTITION imply EFI_PARTITION imply MII - imply IP_DYN imply ISO_PARTITION - imply PARTITION_TYPE_GUID + imply PARTITION_TYPE_GUID if EFI_PARTITION imply PHY_LIB imply PHY_MSCC diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 2d9431d2976..e231467f2a1 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -131,6 +131,9 @@ int board_fit_config_name_match(const char *name) !strncmp(get_product_id_from_eeprom(), "MARC", 4) && !get_mmc_size_from_eeprom()) { return 0; + } else if (!strcmp(name, "starfive/jh7110-orangepi-rv") && + !strncmp(get_product_id_from_eeprom(), "XOPIRV", 6)) { + return 0; } else if (!strcmp(name, "starfive/jh7110-pine64-star64") && !strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { return 0; @@ -140,6 +143,9 @@ int board_fit_config_name_match(const char *name) } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") && !strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { return 0; + } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-lite") && + !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { + return 0; } return -EINVAL; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 6c39fd4af35..1a76f745ec8 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -63,12 +63,16 @@ static void set_fdtfile(void) } else { fdtfile = "starfive/jh7110-milkv-marscm-lite.dtb"; } + } else if (!strncmp(get_product_id_from_eeprom(), "XOPIRV", 6)) { + fdtfile = "starfive/jh7110-orangepi-rv.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { fdtfile = "starfive/jh7110-pine64-star64.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "VF7110A", 7)) { fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; + } else if (!strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-lite.dtb"; } else { log_err("Unknown product\n"); return; diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index 17a44020bcf..b9197cdd34f 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -105,7 +105,8 @@ struct eeprom_atom4_data { u8 bom_revision; /* BOM version */ u8 mac0_addr[MAC_ADDR_BYTES]; /* Ethernet0 MAC */ u8 mac1_addr[MAC_ADDR_BYTES]; /* Ethernet1 MAC */ - u8 reserved[2]; + u8 onboard_module; /* Onboard module flag: bit7-1: reserved, bit0: WIFI/BT */ + u8 reserved; }; struct starfive_eeprom_atom4 { @@ -176,7 +177,7 @@ static void show_eeprom(void) printf("Vendor : %s\n", pbuf.eeprom.atom1.data.vstr); printf("Product full SN: %s\n", pbuf.eeprom.atom1.data.pstr); printf("data version: 0x%x\n", pbuf.eeprom.atom4.data.version); - if (pbuf.eeprom.atom4.data.version == 2) { + if (pbuf.eeprom.atom4.data.version == 2 || pbuf.eeprom.atom4.data.version == 3) { printf("PCB revision: 0x%x\n", pbuf.eeprom.atom4.data.pcb_revision); printf("BOM revision: %c\n", pbuf.eeprom.atom4.data.bom_revision); printf("Ethernet MAC0 address: %02x:%02x:%02x:%02x:%02x:%02x\n", @@ -187,6 +188,14 @@ static void show_eeprom(void) pbuf.eeprom.atom4.data.mac1_addr[0], pbuf.eeprom.atom4.data.mac1_addr[1], pbuf.eeprom.atom4.data.mac1_addr[2], pbuf.eeprom.atom4.data.mac1_addr[3], pbuf.eeprom.atom4.data.mac1_addr[4], pbuf.eeprom.atom4.data.mac1_addr[5]); + if (pbuf.eeprom.atom4.data.version == 3) { + char str[25] = "Onboard module: "; + + if (pbuf.eeprom.atom4.data.onboard_module & BIT(0)) + strcat(str, "WIFI/BT"); + + printf("%s\n", str); + } } else { printf("Custom data v%d is not Supported\n", pbuf.eeprom.atom4.data.version); dump_raw_eeprom(); @@ -260,6 +269,7 @@ static void init_local_copy(void) pbuf.eeprom.atom4.data.bom_revision = BOM_VERSION; set_mac_address(STARFIVE_DEFAULT_MAC0, 0); set_mac_address(STARFIVE_DEFAULT_MAC1, 1); + pbuf.eeprom.atom4.data.onboard_module = 0; } /** @@ -385,6 +395,23 @@ static void set_bom_revision(char *string) update_crc(); } +/** + * set_onboard_module() - stores a StarFive onboard module flag into the local EEPROM copy + * + * Takes a pointer to a string representing the numeric onboard module flag in + * Hexadecimal ("0" - "FF"), stores it in the onboard_module field of the + * EEPROM local copy, and updates the CRC of the local copy. + */ +static void set_onboard_module(char *string) +{ + u8 onboard_module; + + onboard_module = simple_strtoul(string, &string, 16); + pbuf.eeprom.atom4.data.onboard_module = onboard_module; + + update_crc(); +} + /** * set_product_id() - stores a StarFive product ID into the local EEPROM copy * @@ -478,6 +505,9 @@ int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } else if (!strcmp(cmd, "bom_revision")) { set_bom_revision(argv[2]); return 0; + } else if (!strcmp(cmd, "onboard_module")) { + set_onboard_module(argv[2]); + return 0; } else if (!strcmp(cmd, "product_id")) { set_product_id(argv[2]); return 0; @@ -535,38 +565,20 @@ int mac_read_from_eeprom(void) return 0; } -/** - * get_pcb_revision_from_eeprom - get the PCB revision - * - * 1.2A return 'A'/'a', 1.3B return 'B'/'b',other values are illegal - */ u8 get_pcb_revision_from_eeprom(void) { - u8 pv = 0xFF; - if (read_eeprom()) - return pv; + return 0; - return pbuf.eeprom.atom1.data.pstr[6]; + return pbuf.eeprom.atom4.data.pcb_revision; } -/** - * get_ddr_size_from_eeprom - get the DDR size - * pstr: VF7110A1-2228-D008E000-00000001 - * VF7110A1/VF7110B1 : VisionFive JH7110A /VisionFive JH7110B - * D008: 8GB LPDDR4 - * E000: No emmc device, ECxx: include emmc device, xx: Capacity size[GB] - * return: the field of 'D008E000' - */ - -u32 get_ddr_size_from_eeprom(void) +u8 get_ddr_size_from_eeprom(void) { - u32 pv = 0xFFFFFFFF; - if (read_eeprom()) - return pv; + return 0; - return hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL); + return (hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL) >> 16) & 0xFF; } u32 get_mmc_size_from_eeprom(void) @@ -603,6 +615,8 @@ U_BOOT_LONGHELP(mac, " - stores a StarFive PCB revision into the local EEPROM copy\n" "mac bom_revision \n" " - stores a StarFive BOM revision into the local EEPROM copy\n" + "mac onboard_module \n" + " - stores a StarFive onboard module flag into the local EEPROM copy\n" "mac product_id \n" " - stores a StarFive product ID into the local EEPROM copy\n" "mac vendor \n" diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 954a8715075..d7722d1858a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -50,7 +50,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -561,14 +560,23 @@ static void sunxi_spl_store_dram_size(phys_addr_t dram_size) spl->dram_size = dram_size >> 20; } +static void status_led_init(void) +{ +#if CONFIG_IS_ENABLED(SUNXI_LED_STATUS) + unsigned int state = CONFIG_SPL_SUNXI_LED_STATUS_STATE; + unsigned int gpio = CONFIG_SPL_SUNXI_LED_STATUS_BIT; + + gpio_request(gpio, "gpio_led"); + gpio_direction_output(gpio, state); +#endif +} + void sunxi_board_init(void) { int power_failed = 0; -#ifdef CONFIG_LED_STATUS - if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC)) + if (CONFIG_IS_ENABLED(SUNXI_LED_STATUS)) status_led_init(); -#endif #ifdef CONFIG_SY8106A_POWER power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 1659db112fa..5515fc09f99 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index cbd087de797..4e238883b96 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62A # @@ -16,14 +16,14 @@ rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - # 1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - # 2 + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 1038 - num_resource: 497 + num_resource: 496 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62ax/tifs-rm-cfg.yaml b/board/ti/am62ax/tifs-rm-cfg.yaml index 151cd599b1b..78bbab38bb6 100644 --- a/board/ti/am62ax/tifs-rm-cfg.yaml +++ b/board/ti/am62ax/tifs-rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62AX +# Resource management configuration for AM62A # --- @@ -24,26 +24,26 @@ tifs-rm-cfg: allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - # 2 - host_id: 30 + host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - # 3 - host_id: 36 + host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - # 4 - host_id: 0 - allowed_atype: 0 - allowed_qos: 0 - allowed_orderid: 0 - allowed_priority: 0 - allowed_sched_priority: 0 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA - # 5 host_id: 0 allowed_atype: 0 @@ -244,7 +244,7 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 872 + resasg_entries_size: 880 reserved: 0 resasg_entries: - @@ -257,7 +257,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1677 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 18 @@ -287,7 +287,7 @@ tifs-rm-cfg: start_resource: 72 num_resource: 6 type: 1678 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 72 @@ -317,7 +317,7 @@ tifs-rm-cfg: start_resource: 44 num_resource: 6 type: 1679 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 44 @@ -347,7 +347,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1696 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 18 @@ -377,7 +377,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1697 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 18 @@ -407,7 +407,7 @@ tifs-rm-cfg: start_resource: 12 num_resource: 6 type: 1698 - host_id: 35 + host_id: 20 reserved: 0 - start_resource: 12 @@ -429,19 +429,25 @@ tifs-rm-cfg: reserved: 0 - start_resource: 6 - num_resource: 34 + num_resource: 26 type: 1802 host_id: 12 reserved: 0 + - + start_resource: 32 + num_resource: 8 + type: 1802 + host_id: 20 + reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml index 73da85eeade..0db82fdaf79 100644 --- a/board/ti/am62px/rm-cfg.yaml +++ b/board/ti/am62px/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62px/tifs-rm-cfg.yaml b/board/ti/am62px/tifs-rm-cfg.yaml index 80269748057..73efceafc75 100644 --- a/board/ti/am62px/tifs-rm-cfg.yaml +++ b/board/ti/am62px/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -9,231 +9,231 @@ tifs-rm-cfg: rm_boardcfg: rev: - boardcfg_abi_maj : 0x0 - boardcfg_abi_min : 0x1 + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 host_cfg: subhdr: magic: 0x4C41 - size : 356 + size: 356 host_cfg_entries: - - #1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #2 + - # 2 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #3 + - # 3 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #4 + - # 4 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #5 + - # 5 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #6 + - # 6 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #7 + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #8 + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #9 + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #10 + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #11 + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #12 + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #13 + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #14 + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #15 + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #16 + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #17 + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #18 + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #19 + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #20 + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #21 + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #22 + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #23 + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #24 + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #25 + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #26 + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #27 + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #28 + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #29 + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #30 + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #31 + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #32 + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 @@ -244,684 +244,732 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 904 + resasg_entries_size: 968 reserved: 0 resasg_entries: - - start_resource: 0 - num_resource: 18 - type: 1677 - host_id: 12 - reserved: 0 - - - start_resource: 18 - num_resource: 6 - type: 1677 - host_id: 35 - reserved: 0 - - - start_resource: 18 - num_resource: 6 - type: 1677 - host_id: 36 - reserved: 0 - - - start_resource: 24 - num_resource: 2 - type: 1677 - host_id: 30 - reserved: 0 - - - start_resource: 26 - num_resource: 6 - type: 1677 - host_id: 128 - reserved: 0 - - - start_resource: 57 - num_resource: 18 - type: 1678 - host_id: 12 - reserved: 0 - - - start_resource: 75 - num_resource: 5 - type: 1678 - host_id: 35 - reserved: 0 - - - start_resource: 75 - num_resource: 5 - type: 1678 - host_id: 36 - reserved: 0 - - - start_resource: 80 - num_resource: 2 - type: 1678 - host_id: 30 - reserved: 0 - - - start_resource: 32 - num_resource: 12 - type: 1679 - host_id: 12 - reserved: 0 - - - start_resource: 44 - num_resource: 6 - type: 1679 - host_id: 35 - reserved: 0 - - - start_resource: 44 - num_resource: 6 - type: 1679 - host_id: 36 - reserved: 0 - - - start_resource: 50 - num_resource: 2 - type: 1679 - host_id: 30 - reserved: 0 - - - start_resource: 52 - num_resource: 5 - type: 1679 - host_id: 128 - reserved: 0 - - - start_resource: 0 - num_resource: 18 - type: 1696 - host_id: 12 - reserved: 0 - - - start_resource: 18 - num_resource: 6 - type: 1696 - host_id: 35 - reserved: 0 - - - start_resource: 18 - num_resource: 6 - type: 1696 - host_id: 36 - reserved: 0 - - - start_resource: 24 - num_resource: 2 - type: 1696 - host_id: 30 - reserved: 0 - - - start_resource: 26 - num_resource: 6 - type: 1696 - host_id: 128 - reserved: 0 - - - start_resource: 0 - num_resource: 18 - type: 1697 - host_id: 12 - reserved: 0 - - - start_resource: 18 - num_resource: 5 - type: 1697 - host_id: 35 - reserved: 0 - - - start_resource: 18 - num_resource: 5 - type: 1697 - host_id: 36 - reserved: 0 - - - start_resource: 23 - num_resource: 2 - type: 1697 - host_id: 30 - reserved: 0 - - - start_resource: 0 - num_resource: 12 - type: 1698 - host_id: 12 - reserved: 0 - - - start_resource: 12 - num_resource: 6 - type: 1698 - host_id: 35 - reserved: 0 - - - start_resource: 12 - num_resource: 6 - type: 1698 - host_id: 36 - reserved: 0 - - - start_resource: 18 - num_resource: 2 - type: 1698 - host_id: 30 - reserved: 0 - - - start_resource: 20 - num_resource: 5 - type: 1698 - host_id: 128 - reserved: 0 - - - start_resource: 5 - num_resource: 35 - type: 1802 - host_id: 12 - reserved: 0 - - - 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host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 2e8336900d1..49e58ad6d6c 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -32,8 +32,6 @@ #define board_is_am62x_lp_skevm() board_ti_k3_is("AM62-LP-SKEVM") #define board_is_am62x_sip_skevm() board_ti_k3_is("AM62SIP-SKEVM") -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(SPLASH_SCREEN) static struct splash_location default_splash_locations[] = { { diff --git a/board/ti/am62x/rm-cfg.yaml b/board/ti/am62x/rm-cfg.yaml index 26d99b03b80..a7035dc0bd9 100644 --- a/board/ti/am62x/rm-cfg.yaml +++ b/board/ti/am62x/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62X # @@ -525,7 +525,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/am62x/tifs-rm-cfg.yaml b/board/ti/am62x/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..8510fe9526e --- /dev/null +++ b/board/ti/am62x/tifs-rm-cfg.yaml @@ -0,0 +1,867 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62X +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 824 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1677 + host_id: 128 + reserved: 0 + - + start_resource: 54 + num_resource: 18 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 35 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 78 + num_resource: 2 + type: 1678 + host_id: 30 + reserved: 0 + - + start_resource: 80 + num_resource: 2 + type: 1678 + host_id: 128 + reserved: 0 + - + start_resource: 32 + num_resource: 12 + type: 1679 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 36 + reserved: 0 + - + start_resource: 50 + num_resource: 2 + type: 1679 + host_id: 30 + reserved: 0 + - + start_resource: 52 + num_resource: 2 + type: 1679 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1696 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1696 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1696 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1697 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1697 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 2 + type: 1697 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 12 + type: 1698 + host_id: 12 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 35 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 36 + reserved: 0 + - + start_resource: 18 + num_resource: 2 + type: 1698 + host_id: 30 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 1698 + host_id: 128 + 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16 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 36 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1944 + host_id: 12 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1945 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1946 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1947 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1955 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1955 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1955 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 36 + reserved: 0 + - + start_resource: 27 + num_resource: 1 + type: 1957 + host_id: 12 + reserved: 0 + - + start_resource: 28 + num_resource: 1 + type: 1958 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1961 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1961 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1961 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1962 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1962 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1962 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 36 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 36 + reserved: 0 + - + start_resource: 20 + num_resource: 1 + type: 1965 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1966 + host_id: 12 + reserved: 0 + - + start_resource: 21 + num_resource: 1 + type: 1967 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1968 + host_id: 12 + reserved: 0 + - + start_resource: 22 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index c6ddc44d14c..05c5ca8740f 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -27,8 +27,6 @@ #define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \ board_ti_k3_is("AM64B-SKEVM")) -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID, diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 409454813f3..149909093b3 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -61,4 +61,6 @@ config TI_COMMON_CMD_OPTIONS imply CMD_SPL imply CMD_TIME imply CMD_USB if USB + imply CMD_TPM if TPM + imply CMD_OPTEE_RPMB if OPTEE && SUPPORT_EMMC_RPMB diff --git a/board/ti/common/k3_bist.config b/board/ti/common/k3_bist.config new file mode 100644 index 00000000000..671dda1a9dc --- /dev/null +++ b/board/ti/common/k3_bist.config @@ -0,0 +1 @@ +CONFIG_K3_BIST=y diff --git a/board/ti/common/k3_inline_ecc.config b/board/ti/common/k3_inline_ecc.config new file mode 100644 index 00000000000..143c814b41c --- /dev/null +++ b/board/ti/common/k3_inline_ecc.config @@ -0,0 +1 @@ +CONFIG_K3_INLINE_ECC=y diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env index e22a954d8db..7bb63825c52 100644 --- a/board/ti/j7200/j7200.env +++ b/board/ti/j7200/j7200.env @@ -37,3 +37,11 @@ main_cpsw0_qsgmii_phyinit= #if CONFIG_TARGET_J7200_A72_EVM rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif + +#if CONFIG_CMD_REMOTEPROC +board_init= + if env exists do_main_cpsw0_qsgmii_phyinit; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; +#endif diff --git a/board/ti/j7200/rm-cfg.yaml b/board/ti/j7200/rm-cfg.yaml index 9da0ea91ada..e1973de821f 100644 --- a/board/ti/j7200/rm-cfg.yaml +++ b/board/ti/j7200/rm-cfg.yaml @@ -399,7 +399,7 @@ rm-cfg: reserved: 0 - start_resource: 224 - num_resource: 32 + num_resource: 30 type: 13386 host_id: 128 reserved: 0 @@ -441,7 +441,7 @@ rm-cfg: reserved: 0 - start_resource: 2578 - num_resource: 2030 + num_resource: 2028 type: 13389 host_id: 128 reserved: 0 @@ -1041,12 +1041,12 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 128 + num_resource: 126 type: 13632 host_id: 12 reserved: 0 - - start_resource: 138 + start_resource: 136 num_resource: 54 type: 13632 host_id: 13 diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 34f5f63d60a..9ecf7bfabde 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -37,3 +37,11 @@ main_cpsw0_qsgmii_phyinit= #if CONFIG_TARGET_J721E_A72_EVM rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif + +#if CONFIG_CMD_REMOTEPROC +board_init= + if env exists do_main_cpsw0_qsgmii_phyinit; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; +#endif diff --git a/board/ti/j721e/rm-cfg.yaml b/board/ti/j721e/rm-cfg.yaml index 88ec2026db0..86d30a96375 100644 --- a/board/ti/j721e/rm-cfg.yaml +++ b/board/ti/j721e/rm-cfg.yaml @@ -495,7 +495,7 @@ rm-cfg: reserved: 0 - start_resource: 252 - num_resource: 4 + num_resource: 2 type: 13386 host_id: 128 reserved: 0 @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 3686 - num_resource: 922 + num_resource: 920 type: 13389 host_id: 128 reserved: 0 @@ -1635,18 +1635,18 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 100 + num_resource: 98 type: 13632 host_id: 12 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 32 type: 13632 host_id: 13 reserved: 0 - - start_resource: 142 + start_resource: 140 num_resource: 46 type: 13632 host_id: 21 diff --git a/board/ti/j721s2/rm-cfg.yaml b/board/ti/j721s2/rm-cfg.yaml index 8796463129d..86d572b4b33 100644 --- a/board/ti/j721s2/rm-cfg.yaml +++ b/board/ti/j721s2/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J721S2 # @@ -429,24 +429,24 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 100 + num_resource: 98 type: 14528 host_id: 12 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 32 type: 14528 host_id: 13 reserved: 0 - - start_resource: 142 + start_resource: 140 num_resource: 21 type: 14528 host_id: 21 reserved: 0 - - start_resource: 163 + start_resource: 161 num_resource: 21 type: 14528 host_id: 23 @@ -1431,7 +1431,7 @@ rm-cfg: reserved: 0 - start_resource: 236 - num_resource: 20 + num_resource: 18 type: 16970 host_id: 128 reserved: 0 @@ -1497,7 +1497,7 @@ rm-cfg: reserved: 0 - start_resource: 3426 - num_resource: 1182 + num_resource: 1180 type: 16973 host_id: 128 reserved: 0 diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml index 62730adf216..e5f7b24c1d1 100644 --- a/board/ti/j722s/rm-cfg.yaml +++ b/board/ti/j722s/rm-cfg.yaml @@ -591,7 +591,7 @@ rm-cfg: reserved: 0 - start_resource: 1297 - num_resource: 239 + num_resource: 238 type: 1805 host_id: 128 reserved: 0 diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index cabb3017ee1..8a4d40a5a95 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -14,8 +14,6 @@ #include #include "../common/fdt_ops.h" -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = AM69_SK_TIBOOT3_IMAGE_GUID, diff --git a/board/ti/j784s4/rm-cfg.yaml b/board/ti/j784s4/rm-cfg.yaml index 6968d317522..6fb717e4808 100644 --- a/board/ti/j784s4/rm-cfg.yaml +++ b/board/ti/j784s4/rm-cfg.yaml @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J784S4 # @@ -454,36 +454,36 @@ rm-cfg: reserved: 0 - start_resource: 16 - num_resource: 80 + num_resource: 78 type: 18112 host_id: 12 reserved: 0 - - start_resource: 96 + start_resource: 94 num_resource: 14 type: 18112 host_id: 13 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 21 type: 18112 host_id: 21 reserved: 0 - - start_resource: 131 + start_resource: 129 num_resource: 21 type: 18112 host_id: 23 reserved: 0 - - start_resource: 152 + start_resource: 150 num_resource: 12 type: 18112 host_id: 25 reserved: 0 - - start_resource: 164 + start_resource: 162 num_resource: 12 type: 18112 host_id: 27 @@ -1720,72 +1720,72 @@ rm-cfg: reserved: 0 - start_resource: 56 - num_resource: 56 + num_resource: 54 type: 20554 host_id: 12 reserved: 0 - - start_resource: 112 + start_resource: 110 num_resource: 24 type: 20554 host_id: 13 reserved: 0 - - start_resource: 136 + start_resource: 134 num_resource: 12 type: 20554 host_id: 21 reserved: 0 - - start_resource: 148 + start_resource: 146 num_resource: 12 type: 20554 host_id: 23 reserved: 0 - - start_resource: 160 + start_resource: 158 num_resource: 10 type: 20554 host_id: 25 reserved: 0 - - start_resource: 170 + start_resource: 168 num_resource: 10 type: 20554 host_id: 27 reserved: 0 - - start_resource: 180 + start_resource: 178 num_resource: 28 type: 20554 host_id: 35 reserved: 0 - - start_resource: 208 + start_resource: 206 num_resource: 8 type: 20554 host_id: 37 reserved: 0 - - start_resource: 216 + start_resource: 214 num_resource: 12 type: 20554 host_id: 40 reserved: 0 - - start_resource: 228 + start_resource: 226 num_resource: 8 type: 20554 host_id: 42 reserved: 0 - - start_resource: 236 + start_resource: 234 num_resource: 10 type: 20554 host_id: 45 reserved: 0 - - start_resource: 246 + start_resource: 244 num_resource: 10 type: 20554 host_id: 47 @@ -1876,7 +1876,7 @@ rm-cfg: reserved: 0 - start_resource: 4472 - num_resource: 136 + num_resource: 134 type: 20557 host_id: 128 reserved: 0 diff --git a/board/ti/j784s4/tifs-rm-cfg.yaml b/board/ti/j784s4/tifs-rm-cfg.yaml index 992ea23155a..738fe0ea07d 100644 --- a/board/ti/j784s4/tifs-rm-cfg.yaml +++ b/board/ti/j784s4/tifs-rm-cfg.yaml @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later # -# Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J784S4 # @@ -1456,72 +1456,72 @@ tifs-rm-cfg: reserved: 0 - start_resource: 56 - num_resource: 56 + num_resource: 54 type: 20554 host_id: 12 reserved: 0 - - start_resource: 112 + start_resource: 110 num_resource: 24 type: 20554 host_id: 13 reserved: 0 - - start_resource: 136 + start_resource: 134 num_resource: 12 type: 20554 host_id: 21 reserved: 0 - - start_resource: 148 + start_resource: 146 num_resource: 12 type: 20554 host_id: 23 reserved: 0 - - start_resource: 160 + start_resource: 158 num_resource: 10 type: 20554 host_id: 25 reserved: 0 - - start_resource: 170 + start_resource: 168 num_resource: 10 type: 20554 host_id: 27 reserved: 0 - - start_resource: 180 + start_resource: 178 num_resource: 28 type: 20554 host_id: 35 reserved: 0 - - start_resource: 208 + start_resource: 206 num_resource: 8 type: 20554 host_id: 37 reserved: 0 - - start_resource: 216 + start_resource: 214 num_resource: 12 type: 20554 host_id: 40 reserved: 0 - - start_resource: 228 + start_resource: 226 num_resource: 8 type: 20554 host_id: 42 reserved: 0 - - start_resource: 236 + start_resource: 234 num_resource: 10 type: 20554 host_id: 45 reserved: 0 - - start_resource: 246 + start_resource: 244 num_resource: 10 type: 20554 host_id: 47 diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index a8c38208693..b915673d9e3 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -5,7 +5,6 @@ #include #include -#include #include #include @@ -24,8 +23,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 2c785da41ea..8dad41f4122 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include "pinmux-config-apalis_t30.h" -DECLARE_GLOBAL_DATA_PTR; - #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 diff --git a/board/toradex/aquila-am69/Makefile b/board/toradex/aquila-am69/Makefile index aa71c4bbb21..aa657ac8a42 100644 --- a/board/toradex/aquila-am69/Makefile +++ b/board/toradex/aquila-am69/Makefile @@ -6,4 +6,5 @@ obj-y += aquila-am69.o obj-y += ddrs_patch.o obj-y += aquila_ddrs_16GB.o +obj-y += aquila_ddrs_16GB_rank_2.o obj-y += aquila_ddrs_8GB.o diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c index e0975d5bc6f..0c7123a059e 100644 --- a/board/toradex/aquila-am69/aquila-am69.c +++ b/board/toradex/aquila-am69/aquila-am69.c @@ -17,26 +17,32 @@ #include #include "../common/tdx-common.h" -#include "aquila_ddrs_16GB.h" -#include "aquila_ddrs_8GB.h" +#include "aquila_ddrs.h" #include "ddrs_patch.h" #define CTRL_MMR_CFG0_MCU_ADC1_CTRL 0x40F040B4 #define HW_CFG_MEM_SZ_32GB 0x00 -#define HW_CFG_MEM_SZ_16GB 0x01 +#define HW_CFG_MEM_SZ_16GB_RANK_2 0x01 #define HW_CFG_MEM_SZ_8GB 0x02 +#define HW_CFG_MEM_SZ_16GB 0x03 -#define HW_CFG_MEM_SZ_MASK 0x03 +#define HW_CFG_MEM_CFG_MASK 0x03 DECLARE_GLOBAL_DATA_PTR; static u8 hw_cfg; +static u8 aquila_am69_memory_cfg(void) +{ + return hw_cfg & HW_CFG_MEM_CFG_MASK; +} + static u64 aquila_am69_memory_size(void) { - switch (hw_cfg & HW_CFG_MEM_SZ_MASK) { + switch (aquila_am69_memory_cfg()) { case HW_CFG_MEM_SZ_32GB: return SZ_32G; + case HW_CFG_MEM_SZ_16GB_RANK_2: case HW_CFG_MEM_SZ_16GB: return SZ_16G; case HW_CFG_MEM_SZ_8GB: @@ -79,12 +85,16 @@ static void update_ddr_timings(void) int ret = 0; void *fdt = (void *)gd->fdt_blob; - switch (aquila_am69_memory_size()) { - case SZ_8G: + switch (aquila_am69_memory_cfg()) { + case HW_CFG_MEM_SZ_8GB: ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB, MULTI_DDR_CFG_INTRLV_SIZE_8GB); break; - case SZ_16G: + case HW_CFG_MEM_SZ_16GB_RANK_2: + ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB_rank_2, + MULTI_DDR_CFG_INTRLV_SIZE_16GB); + break; + case HW_CFG_MEM_SZ_16GB: ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB, MULTI_DDR_CFG_INTRLV_SIZE_16GB); break; diff --git a/board/toradex/aquila-am69/aquila_ddrs.h b/board/toradex/aquila-am69/aquila_ddrs.h new file mode 100644 index 00000000000..7a58be3fd29 --- /dev/null +++ b/board/toradex/aquila-am69/aquila_ddrs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) Toradex - https://www.toradex.com/ + */ +#ifndef __AQUILA_DDRS_H +#define __AQUILA_DDRS_H + +#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9 +#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11 + +extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4]; +extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4]; +extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4]; + +#endif // __AQUILA_DDRS_H diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB.h b/board/toradex/aquila-am69/aquila_ddrs_16GB.h deleted file mode 100644 index 0740c0ef25c..00000000000 --- a/board/toradex/aquila-am69/aquila_ddrs_16GB.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2025 Toradex - https://www.toradex.com/ - */ -#ifndef __AQUILA_DDRS_16GB_H -#define __AQUILA_DDRS_16GB_H - -#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11 -extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4]; - -#endif // __AQUILA_DDRS_16GB_H diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c new file mode 100644 index 00000000000..c24e22b620b --- /dev/null +++ b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) Toradex - https://www.toradex.com/ + * This contains a diff against the 32GB register settings created from + * the 16GB dual rank tool output. + + * The 16GB dtsi file was generated with the following tool revisions: + * - SysConfig: Revision 1.26.2+4477 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Fri Mar 06 2026 10:39:50 GMT+0100 (Central European Standard Time) + */ + +#include +#include +#include "ddrs_patch.h" + +#define DDRSS_PLL_FHS_CNT 3 + +#define DDRSS_CTL_268_DATA 0x01010000 +#define DDRSS_CTL_270_DATA 0x00000FFF +#define DDRSS_CTL_271_DATA 0x1FFF1000 +#define DDRSS_CTL_272_DATA 0x01FF0000 +#define DDRSS_CTL_273_DATA 0x000101FF + +#define DDRSS_PI_73_DATA 0x00080100 + +static struct ddr_reg_patch ctl_patch[] = { + { 268, DDRSS_CTL_268_DATA}, + { 270, DDRSS_CTL_270_DATA}, + { 271, DDRSS_CTL_271_DATA}, + { 272, DDRSS_CTL_272_DATA}, + { 273, DDRSS_CTL_273_DATA} +}; + +static struct ddr_reg_patch pi_patch[] = { + { 73, DDRSS_PI_73_DATA}, +}; + +static struct ddrss_patch ddrss_ctrl_patch = { + .ddr_fhs_cnt = DDRSS_PLL_FHS_CNT, + .ctl_patch = ctl_patch, + .ctl_patch_num = ARRAY_SIZE(ctl_patch), + .pi_patch = pi_patch, + .pi_patch_num = ARRAY_SIZE(pi_patch), + .phy_patch = NULL, + .phy_patch_num = 0 +}; + +struct ddrss_patch *aquila_am69_ddrss_patch_16GB_rank_2[4] = { + &ddrss_ctrl_patch, + &ddrss_ctrl_patch, + &ddrss_ctrl_patch, + &ddrss_ctrl_patch +}; diff --git a/board/toradex/aquila-am69/aquila_ddrs_8GB.h b/board/toradex/aquila-am69/aquila_ddrs_8GB.h deleted file mode 100644 index c82f236d55f..00000000000 --- a/board/toradex/aquila-am69/aquila_ddrs_8GB.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2025 Toradex - https://www.toradex.com/ - */ -#ifndef __AQUILA_DDRS_8GB_H -#define __AQUILA_DDRS_8GB_H - -#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9 -extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4]; - -#endif // __AQUILA_DDRS_8GB_H diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 2a71e7b92de..0a86420700d 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -5,7 +5,6 @@ #include #include -#include #include #include @@ -21,8 +20,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 05c3377a60b..ccfe2c4933c 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include "../common/tdx-common.h" -DECLARE_GLOBAL_DATA_PTR; - #define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3 #define PMU_SUPPLYENE 0x14 diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 0fc3759695f..8c0278db0e2 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -4,7 +4,6 @@ */ #include -#include #include "tdx-cfg-block.h" #include "tdx-eeprom.h" @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define TAG_VALID 0xcf01 #define TAG_MAC 0x0000 #define TAG_CAR_SERIAL 0x0021 @@ -189,6 +186,7 @@ const struct toradex_som toradex_modules[] = { { OSM_IMX93D_2GB_IT, "OSM iMX93 Dual 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX93) }, { OSM_IMX91S_2GB_IT, "OSM iMX91 Solo 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX91) }, { VERDIN_AM62D_1G_ET_GPU_NODSI, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { AQUILA_TDA4O_16GB_IT, "Aquila TDA4 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index b28033d8332..3022ef615ad 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -6,6 +6,8 @@ #ifndef _TDX_CFG_BLOCK_H #define _TDX_CFG_BLOCK_H +#include + #include "tdx-common.h" struct toradex_hw { @@ -147,6 +149,7 @@ enum { OSM_IMX93D_2GB_IT, OSM_IMX91S_2GB_IT, /* 220 */ VERDIN_AM62D_1G_ET_GPU_NODSI, + AQUILA_TDA4O_16GB_IT = 223, }; enum { diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h index d446e9f1d5c..db3369a8f9e 100644 --- a/board/toradex/common/tdx-common.h +++ b/board/toradex/common/tdx-common.h @@ -6,6 +6,8 @@ #ifndef _TDX_COMMON_H #define _TDX_COMMON_H +#include + #define TORADEX_USB_PRODUCT_NUM_OFFSET 0x4000 #define TDX_USB_VID 0x1B67 diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.c b/board/toradex/smarc-imx8mp/smarc-imx8mp.c index 915b413b15e..38fb3d61f5b 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.c +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.c @@ -2,14 +2,11 @@ /* Copyright (C) 2024 Toradex */ #include -#include #include #include #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - int board_phys_sdram_size(phys_size_t *size) { if (!size) diff --git a/board/toradex/smarc-imx8mp/spl.c b/board/toradex/smarc-imx8mp/spl.c index 32233c0e1ab..511f62e871b 100644 --- a/board/toradex/smarc-imx8mp/spl.c +++ b/board/toradex/smarc-imx8mp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/toradex/smarc-imx95/MAINTAINERS b/board/toradex/smarc-imx95/MAINTAINERS index 73517d36f1f..96d349c06b2 100644 --- a/board/toradex/smarc-imx95/MAINTAINERS +++ b/board/toradex/smarc-imx95/MAINTAINERS @@ -1,6 +1,4 @@ Toradex SMARC iMX95 -F: arch/arm/dts/imx95-toradex-smarc.dtsi -F: arch/arm/dts/imx95-toradex-smarc-dev.dts F: arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi F: board/toradex/smarc-imx95/ F: configs/toradex-smarc-imx95_defconfig diff --git a/board/toradex/verdin-am62/rm-cfg.yaml b/board/toradex/verdin-am62/rm-cfg.yaml index ea5f2423cf3..8204031449e 100644 --- a/board/toradex/verdin-am62/rm-cfg.yaml +++ b/board/toradex/verdin-am62/rm-cfg.yaml @@ -525,7 +525,7 @@ rm-cfg: reserved: 0 - start_resource: 168 - num_resource: 8 + num_resource: 7 type: 1802 host_id: 30 reserved: 0 @@ -555,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/toradex/verdin-am62p/rm-cfg.yaml b/board/toradex/verdin-am62p/rm-cfg.yaml index 73da85eeade..bbbb208eb33 100644 --- a/board/toradex/verdin-am62p/rm-cfg.yaml +++ b/board/toradex/verdin-am62p/rm-cfg.yaml @@ -567,7 +567,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 626 + num_resource: 625 type: 1805 host_id: 128 reserved: 0 diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 3c2d0ba1dd4..10b9991e3bf 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -27,8 +26,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define I2C_PMIC_BUS_ID 1 int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index b4402415845..b56f5bf30a8 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -17,8 +16,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define I2C_PMIC 0 enum pcb_rev_t { diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 8628112a782..44678a976ca 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -7,14 +7,9 @@ #include #include #include -#include #include -#include #include #include -#include -#include -#include #include #include #include @@ -22,8 +17,6 @@ #include #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -71,36 +64,21 @@ void spl_board_init(void) puts("Normal Boot\n"); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed\n"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* * increase VDD_SOC to typical value 0.95V before first @@ -110,23 +88,22 @@ int power_init_board(void) */ if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) /* set DVS0 to 0.85v for special case */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1c); - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Kernel uses OD/OD freq for SoC */ /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); /* set LDO4 and CONFIG2 to enable the I2C level translator */ - pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59); - pmic_reg_write(p, PCA9450_CONFIG2, 0x1); + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); + pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); return 0; } -#endif #if IS_ENABLED(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) @@ -159,9 +136,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - /* Adjust PMIC voltage to 1.0V for 800 MHz */ - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - /* PMIC initialization */ power_init_board(); diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 34ce25512e8..59b4607f065 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) /* Verdin UART_3, Console/Debug UART */ diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS new file mode 100644 index 00000000000..e6f3dc4da21 --- /dev/null +++ b/board/tq/MAINTAINERS @@ -0,0 +1,8 @@ +TQMA6 +M: Max Merchel +L: u-boot@ew.tq-group.com +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: arch/arm/dts/*mba6*.dts* +F: arch/arm/dts/*tqma6*.dts* +F: configs/tqma6*config diff --git a/board/tq/common/Kconfig b/board/tq/common/Kconfig new file mode 100644 index 00000000000..a1896929ea3 --- /dev/null +++ b/board/tq/common/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2023-2026 TQ-Systems GmbH , +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Max Merchel +# + +config TQ_COMMON_BB + bool + default y + +config TQ_COMMON_SDMMC + bool diff --git a/board/tq/common/Makefile b/board/tq/common/Makefile new file mode 100644 index 00000000000..ac564a713fd --- /dev/null +++ b/board/tq/common/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH , +# D-82229 Seefeld, Germany. +# Author: Markus Niebel +# + +obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o +obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o diff --git a/board/tq/common/tq_bb.c b/board/tq/common/tq_bb.c new file mode 100644 index 00000000000..40cff6ab178 --- /dev/null +++ b/board/tq/common/tq_bb.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2022-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include + +#include "tq_bb.h" + +int __weak tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + return 0; +} + +int __weak tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + return 0; +} + +int __weak tq_bb_board_mmc_init(struct bd_info *bis) +{ + return 0; +} + +int __weak tq_bb_board_early_init_f(void) +{ + return 0; +} + +int __weak tq_bb_board_init(void) +{ + return 0; +} + +int __weak tq_bb_board_late_init(void) +{ + return 0; +} + +int __weak tq_bb_checkboard(void) +{ + return 0; +} + +void __weak tq_bb_board_quiesce_devices(void) +{ + ; +} + +const char * __weak tq_bb_get_boardname(void) +{ + return "INVALID"; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void __weak tq_bb_board_init_f(ulong dummy) +{ + ; +} + +void __weak tq_bb_spl_board_init(void) +{ + ; +} +#endif /* IS_ENABLED(CONFIG_SPL_BUILD) */ + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int __weak tq_bb_ft_board_setup(void *blob, struct bd_info *bis) +{ + return 0; +} + +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/common/tq_bb.h b/board/tq/common/tq_bb.h new file mode 100644 index 00000000000..5b1b3f62a8c --- /dev/null +++ b/board/tq/common/tq_bb.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2013-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#ifndef __TQ_BB_H +#define __TQ_BB_H + +struct mmc; +struct bd_info; +struct node_info; + +int tq_bb_board_mmc_getwp(struct mmc *mmc); +int tq_bb_board_mmc_getcd(struct mmc *mmc); +int tq_bb_board_mmc_init(struct bd_info *bis); + +int tq_bb_board_early_init_f(void); +int tq_bb_board_init(void); +int tq_bb_board_late_init(void); +int tq_bb_checkboard(void); +void tq_bb_board_quiesce_devices(void); + +const char *tq_bb_get_boardname(void); + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void tq_bb_board_init_f(ulong dummy); +void tq_bb_spl_board_init(void); +#endif + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int tq_bb_ft_board_setup(void *blob, struct bd_info *bis); +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ + +#endif /* __TQ_BB_H */ diff --git a/board/tq/common/tq_sdmmc.c b/board/tq/common/tq_sdmmc.c new file mode 100644 index 00000000000..b7336faa0c7 --- /dev/null +++ b/board/tq/common/tq_sdmmc.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2018-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tq_bb.h" + +static int check_mmc_autodetect(void) +{ + /* NO or unset: 0 / YES: 1 */ + return (env_get_yesno("mmcautodetect") > 0); +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + u32 dev_no; + + dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + env_set_ulong("mmcblkdev", mmc_map_to_kernel_blk(dev_no)); + + snprintf(cmd, ARRAY_SIZE(cmd), "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/board/tq/tqma6/Kconfig b/board/tq/tqma6/Kconfig index e62228d73d0..21bcb8e0cb3 100644 --- a/board/tq/tqma6/Kconfig +++ b/board/tq/tqma6/Kconfig @@ -7,7 +7,8 @@ config SYS_VENDOR default "tq" config SYS_CONFIG_NAME - default "tqma6" + default "tqma6_mba6" if MBA6 + default "tqma6_wru4" if WRU4 choice prompt "TQMa6 SoC variant" @@ -71,6 +72,8 @@ choice config MBA6 bool "TQMa6 on MBa6 Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SDMMC select USB select CMD_USB select USB_STORAGE @@ -91,6 +94,7 @@ config MBA6 config WRU4 bool "OHB WRU-IV" + select TQ_COMMON_BB help Select the OHB Systems AG WRU-IV baseboard. @@ -106,4 +110,6 @@ config IMX_CONFIG default "board/tq/tqma6/tqma6dl.cfg" if TQMA6DL default "board/tq/tqma6/tqma6s.cfg" if TQMA6S +source "board/tq/common/Kconfig" + endif diff --git a/board/tq/tqma6/MAINTAINERS b/board/tq/tqma6/MAINTAINERS deleted file mode 100644 index 1d3f7d2cf63..00000000000 --- a/board/tq/tqma6/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -TQ-SYSTEMS TQMA6 BOARD -M: Markus Niebel -L: TQ-Systems OSS Team -S: Maintained -F: board/tq/tqma6/ -F: include/configs/tqma6.h -F: configs/tqma6*_defconfig diff --git a/board/tq/tqma6/Makefile b/board/tq/tqma6/Makefile index f1b39844ac6..ecebc28315d 100644 --- a/board/tq/tqma6/Makefile +++ b/board/tq/tqma6/Makefile @@ -6,6 +6,7 @@ # obj-y := tqma6.o +obj-y += tqma6_emmc.o obj-$(CONFIG_MBA6) += tqma6_mba6.o obj-$(CONFIG_WRU4) += tqma6_wru4.o diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 75d36240a1e..005f08c4e5f 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -26,7 +26,8 @@ #include #include -#include "tqma6_bb.h" +#include "tqma6_emmc.h" +#include "../common/tq_bb.h" DECLARE_GLOBAL_DATA_PTR; @@ -37,19 +38,21 @@ int dram_init(void) return 0; } -static const uint16_t tqma6_emmc_dsr = 0x0100; - int board_early_init_f(void) { - return tqma6_bb_board_early_init_f(); + return tq_bb_board_early_init_f(); } int board_init(void) { + struct mmc *mmc = find_mmc_device(0); + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - tqma6_bb_board_init(); + tqma6_mmc_detect_card_type(mmc); + + tq_bb_board_init(); return 0; } @@ -96,11 +99,12 @@ int board_late_init(void) { env_set("board_name", tqma6_get_boardname()); - tqma6_bb_board_late_init(); + tq_bb_board_late_init(); printf("Board: %s on a %s\n", tqma6_get_boardname(), - tqma6_bb_get_boardname()); - return 0; + tq_bb_get_boardname()); + + return tq_bb_checkboard(); } /* @@ -110,17 +114,24 @@ int board_late_init(void) #define MODELSTRLEN 32u int ft_board_setup(void *blob, struct bd_info *bd) { + struct mmc *mmc = find_mmc_device(0); char modelstr[MODELSTRLEN]; snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), - tqma6_bb_get_boardname()); + tq_bb_get_boardname()); do_fixup_by_path_string(blob, "/", "model", modelstr); fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); - /* bring in eMMC dsr settings */ - do_fixup_by_path_u32(blob, - "/soc/aips-bus@02100000/usdhc@02198000", - "dsr", tqma6_emmc_dsr, 2); - tqma6_bb_ft_board_setup(blob, bd); + + /* bring in eMMC dsr settings if needed */ + if (mmc && (!mmc_init(mmc))) { + if (tqma6_emmc_need_dsr(mmc) > 0) { + tqma6_ft_fixup_emmc_dsr(blob, + "/soc/bus@2100000/mmc@2198000", + TQMA6_EMMC_DSR); + } + } else { + puts("eMMC: not present?\n"); + } return 0; } diff --git a/board/tq/tqma6/tqma6.env b/board/tq/tqma6/tqma6.env new file mode 100644 index 00000000000..b1d7e5cbbcf --- /dev/null +++ b/board/tq/tqma6/tqma6.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * TQMa6 environment + */ + +#include + +board=tqma6 +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA6_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA6_FDT_ADDRESS +fdtoverlay_addr_r=TQMA6_FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA6_INITRD_ADDRESS +mmcautodetect=yes +mmcblkdev=0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +netdev=eth0 +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA6_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA6_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA6_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA6_SPI_UBOOT_START +uboot_spi_size=TQMA6_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0 + +fastboot_raw_partition_bootloader= + TQMA6_MMC_UBOOT_SECTOR_START TQMA6_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" + +fastbootcmd=fastboot usb 0 + +#endif /* CONFIG_USB_FUNCTION_FASTBOOT */ diff --git a/board/tq/tqma6/tqma6_bb.h b/board/tq/tqma6/tqma6_bb.h deleted file mode 100644 index e17e6ad3f57..00000000000 --- a/board/tq/tqma6/tqma6_bb.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2013-2014 TQ-Systems GmbH , - * D-82229 Seefeld, Germany. - * Author: Markus Niebel - */ - -#ifndef __TQMA6_BB__ -#define __TQMA6_BB__ - -int tqma6_bb_board_mmc_getwp(struct mmc *mmc); -int tqma6_bb_board_mmc_getcd(struct mmc *mmc); -int tqma6_bb_board_mmc_init(struct bd_info *bis); - -int tqma6_bb_board_early_init_f(void); -int tqma6_bb_board_init(void); -int tqma6_bb_board_late_init(void); -int tqma6_bb_checkboard(void); - -const char *tqma6_bb_get_boardname(void); -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd); -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ - -#endif diff --git a/board/tq/tqma6/tqma6_emmc.c b/board/tq/tqma6/tqma6_emmc.c new file mode 100644 index 00000000000..dd7c4d45c5c --- /dev/null +++ b/board/tq/tqma6/tqma6_emmc.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2017-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include +#include + +#include "tqma6_emmc.h" + +struct emmc_dsr_lookup { + uint mfgid; + char *pnm; + int dsr_needed; +}; + +static const struct emmc_dsr_lookup dsr_tbl[] = { + /* Micron, eMMC 4.41 */ + { 0xfe, "MMC02G", 1 }, + { 0xfe, "MMC04G", 1 }, + { 0xfe, "MMC08G", 1 }, + /* Micron, eMMC 5.0 4 GB*/ + { 0x13, "Q1J54A", 1 }, + { 0x13, "Q2J54A", 1 }, + /* Micron, eMMC 5.0 8 GB*/ + { 0x13, "Q2J55L", 0 }, + /* Samsung, eMMC 5.0 */ + { 0x15, "8GSD3R", 0 }, + { 0x15, "AGSD3R", 0 }, + { 0x15, "BGSD3R", 0 }, + { 0x15, "CGSD3R", 0 }, + /* SanDisk, iNAND 7250 5.1 */ + { 0x45, "DG4008", 0 }, + { 0x45, "DG4016", 0 }, + { 0x45, "DG4032", 0 }, + { 0x45, "DG4064", 0 }, + /* Kingston */ + { 0x100, "?????", 0 }, +}; + +int tqma6_emmc_need_dsr(const struct mmc *mmc) +{ + uint mfgid = mmc->cid[0] >> 24; + char name[7]; + int ret = -1; + size_t i; + + if (IS_SD(mmc)) + return 0; + + sprintf(name, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, (mmc->cid[1] >> 24), + (mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff, + mmc->cid[1] & 0xff, (mmc->cid[2] >> 24)); + + for (i = 0; i < ARRAY_SIZE(dsr_tbl) && (ret < 0); ++i) { + if (dsr_tbl[i].mfgid == mfgid && + (!strncmp(name, dsr_tbl[i].pnm, 6))) { + ret = dsr_tbl[i].dsr_needed; + debug("MFG: %x PNM: %s\n", mfgid, name); + } + } + + if (ret < 0) { + printf("eMMC unknown: MFG: %x PNM: %s\n", mfgid, name); + /* request DSR, even if not known if supported to be safe */ + ret = 1; + } + + return ret; +} + +void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value) +{ + do_fixup_by_path_u32(blob, path, "dsr", value, 1); +} + +void tqma6_mmc_detect_card_type(struct mmc *mmc) +{ + struct mmc *emmc = find_mmc_device(0); + + if (emmc != mmc) + return; + + if (tqma6_emmc_need_dsr(mmc) > 0) + mmc_set_dsr(mmc, TQMA6_EMMC_DSR); +} diff --git a/board/tq/tqma6/tqma6_emmc.h b/board/tq/tqma6/tqma6_emmc.h new file mode 100644 index 00000000000..5ab6c3ac11d --- /dev/null +++ b/board/tq/tqma6/tqma6_emmc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2017-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#ifndef __TQMA6_EMMC_H__ +#define __TQMA6_EMMC_H__ + +#define TQMA6_EMMC_DSR 0x0100 + +struct mmc; + +int tqma6_emmc_need_dsr(const struct mmc *mmc); +void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value); +void tqma6_mmc_detect_card_type(struct mmc *mmc); + +#endif /* __TQMA6_EMMC_H__ */ diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 46989102fec..32aeb1b07c8 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -31,7 +31,7 @@ #include #include -#include "tqma6_bb.h" +#include "../common/tq_bb.h" #if defined(CONFIG_TQMA6Q) @@ -126,34 +126,20 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int tqma6_bb_board_early_init_f(void) -{ - return 0; -} - -int tqma6_bb_board_init(void) +int tq_bb_board_init(void) { mba6_setup_iomuxc_enet(); return 0; } -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) +const char *tq_bb_get_boardname(void) { return "MBa6x"; } -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) +int tq_bb_board_late_init(void) { - /* TBD */ + board_late_mmc_env_init(); + return 0; } -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/tqma6/tqma6_wru4.c b/board/tq/tqma6/tqma6_wru4.c index 7acefc7b064..a7dc8fca109 100644 --- a/board/tq/tqma6/tqma6_wru4.c +++ b/board/tq/tqma6/tqma6_wru4.c @@ -33,7 +33,7 @@ #include #include -#include "tqma6_bb.h" +#include "../common/tq_bb.h" /* UART */ #define UART4_PAD_CTRL ( \ @@ -95,7 +95,7 @@ static struct fsl_esdhc_cfg usdhc2_cfg = { .max_bus_width = 4, }; -int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +int tq_bb_board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; @@ -106,7 +106,7 @@ int tqma6_bb_board_mmc_getcd(struct mmc *mmc) return ret; } -int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +int tq_bb_board_mmc_getwp(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; @@ -117,7 +117,7 @@ int tqma6_bb_board_mmc_getwp(struct mmc *mmc) return ret; } -int tqma6_bb_board_mmc_init(struct bd_info *bis) +int tq_bb_board_mmc_init(struct bd_info *bis) { int ret; @@ -256,14 +256,14 @@ static void gpio_init(void) gpio_direction_output(GPIO_UART3_PWRON, 0); } -int tqma6_bb_board_early_init_f(void) +int tq_bb_board_early_init_f(void) { setup_iomuxc_uart4(); return 0; } -int tqma6_bb_board_init(void) +int tq_bb_board_init(void) { setup_iomuxc_enet(); @@ -279,12 +279,7 @@ int tqma6_bb_board_init(void) return 0; } -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) +const char *tq_bb_get_boardname(void) { return "WRU-IV"; } @@ -331,13 +326,3 @@ int board_ehci_power(int port, int on) return 0; } - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) -{ - /* TBD */ -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c index 9eb0735f55d..52400672799 100644 --- a/board/xilinx/zynq/bootimg.c +++ b/board/xilinx/zynq/bootimg.c @@ -5,15 +5,12 @@ #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define ZYNQ_IMAGE_PHDR_OFFSET 0x09C #define ZYNQ_IMAGE_FSBL_LEN_OFFSET 0x040 #define ZYNQ_PART_HDR_CHKSUM_WORD_COUNT 0x0F diff --git a/boot/Kconfig b/boot/Kconfig index ab31b8f40ed..982687621bd 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -183,6 +183,7 @@ config SPL_FIT bool "Support Flattened Image Tree within SPL" depends on SPL select SPL_HASH + select SPL_LIBGENERIC_SUPPORT select SPL_OF_LIBFDT config SPL_FIT_PRINT @@ -315,6 +316,7 @@ config TPL_FIT bool "Support Flattened Image Tree within TPL" depends on TPL select TPL_HASH + select TPL_LIBGENERIC_SUPPORT select TPL_OF_LIBFDT config TPL_LOAD_FIT @@ -386,7 +388,6 @@ config VPL_FIT_SIGNATURE default y select FIT_SIGNATURE select VPL_FIT - select VPL_CRYPTO select VPL_HASH imply VPL_RSA imply VPL_RSA_VERIFY @@ -430,12 +431,12 @@ config BOOT_DEFAULTS_CMDS select CMD_FAT select CMD_FS_GENERIC select CMD_PART if PARTITIONS - select CMD_DHCP if CMD_NET - select CMD_PING if CMD_NET - select CMD_PXE if CMD_NET + select CMD_DHCP if CMD_NET && !NO_NET + select CMD_PING if CMD_NET && !NO_NET + select CMD_PXE if CMD_NET && !NO_NET select CMD_BOOTI if ARM64 select CMD_BOOTZ if ARM && !ARM64 - imply CMD_MII if NET + imply CMD_MII if CMD_NET && !NO_NET config BOOT_DEFAULTS bool # Common defaults for standard boot and distroboot @@ -562,6 +563,7 @@ config BOOTMETH_ANDROID select CMD_BCB imply CMD_FASTBOOT imply FASTBOOT if !NET_LWIP + select EFI_PARTITION select PARTITION_TYPE_GUID select PARTITION_UUIDS help @@ -990,6 +992,7 @@ if SPL config SPL_UPL bool "Write a UPL handoff in SPL" + depends on SPL_LIBGENERIC_SUPPORT imply SPL_UPL_OUT help This tells SPL to write a UPL handoff and pass it to the next phase @@ -1007,6 +1010,7 @@ config SPL_UPL_WRITE config SPL_UPL_OUT bool "upl - Support writing a Universal Payload handoff in SPL" + depends on SPL_UPL select SPL_UPL_WRITE help Provides support for encoding a UPL-format payload and passing it to @@ -1160,7 +1164,6 @@ config SYS_BOOT_RAMDISK_HIGH depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ depends on !(NIOS2 || SANDBOX || SH || XTENSA) def_bool y - select LMB help Enable initrd_high functionality. If defined then the initrd_high feature is enabled and the boot* ramdisk subcommand is enabled. @@ -1810,7 +1813,7 @@ config SPL_IMAGE_PRE_LOAD config IMAGE_PRE_LOAD_SIG bool "Image pre-load signature support" depends on IMAGE_PRE_LOAD - select FIT_SIGNATURE + depends on FIT_SIGNATURE select RSA select RSA_VERIFY_WITH_PKEY help @@ -1827,7 +1830,7 @@ config IMAGE_PRE_LOAD_SIG config SPL_IMAGE_PRE_LOAD_SIG bool "Image pre-load signature support within SPL" depends on SPL_IMAGE_PRE_LOAD && IMAGE_PRE_LOAD_SIG - select SPL_FIT_SIGNATURE + depends on SPL_FIT_SIGNATURE select SPL_RSA select SPL_RSA_VERIFY_WITH_PKEY help @@ -2037,7 +2040,7 @@ menu "Configuration editor" config CEDIT bool "Configuration editor" - depends on EXPO + depends on EXPO && DM_RTC help Provides a way to deal with board configuration and present it to the user for adjustment. diff --git a/boot/bootm.c b/boot/bootm.c index 4bdca22ea8c..4836d6b2d41 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -7,6 +7,7 @@ #ifndef USE_HOSTCC #include #include +#include #include #include #include @@ -602,7 +603,7 @@ static int handle_decomp_error(int comp_type, size_t uncomp_size, #ifndef USE_HOSTCC static int bootm_load_os(struct bootm_headers *images, int boot_progress) { - struct image_info os = images->os; + const struct image_info os = images->os; ulong load = os.load; ulong load_end; ulong blob_start = os.start; @@ -631,7 +632,7 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) return 1; load = (ulong)addr; - os.load = (ulong)addr; + images->os.load = (ulong)addr; images->ep = (ulong)addr; debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n", req_size, load, image_len); @@ -1194,6 +1195,30 @@ void __weak switch_to_non_secure_mode(void) { } +void bootm_final(int flag) +{ + printf("\nStarting kernel ...%s\n\n", + (flag & BOOTM_STATE_OS_FAKE_GO) ? + " (fake run for tracing)" : ""); + + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + + if (IS_ENABLED(CONFIG_BOOTSTAGE_FDT) && IS_ENABLED(CONFIG_CMD_FDT)) + bootstage_fdt_add_report(); + bootstage_stash_default(); + if (IS_ENABLED(CONFIG_BOOTSTAGE_REPORT)) + bootstage_report(); + + board_quiesce_devices(); + + /* + * Call remove function of all devices with a removal flag set. + * This may be useful for last-stage operations, like cancelling + * of DMA operation or releasing device internal buffers. + */ + dm_remove_devices_active(); +} + #else /* USE_HOSTCC */ #if defined(CONFIG_FIT_SIGNATURE) diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c index a9709465f6e..c841dd0d6d4 100644 --- a/boot/bootmeth-uclass.c +++ b/boot/bootmeth-uclass.c @@ -19,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int bootmeth_get_state_desc(struct udevice *dev, char *buf, int maxsize) { const struct bootmeth_ops *ops = bootmeth_get_ops(dev); diff --git a/boot/fdt_simplefb.c b/boot/fdt_simplefb.c index 5822131767d..69c7c2e24c0 100644 --- a/boot/fdt_simplefb.c +++ b/boot/fdt_simplefb.c @@ -8,14 +8,11 @@ #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int fdt_simplefb_configure_node(void *blob, int off) { int xsize, ysize; diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c index f426ead13c0..433df20281f 100644 --- a/boot/image-fit-sig.c +++ b/boot/image-fit-sig.c @@ -476,6 +476,10 @@ static int fit_config_check_sig(const void *fit, int noffset, int conf_noffset, return -1; } + debug("Hash nodes (%d):\n", count); + for (int i = 0; i < count; ++i) + debug(" '%s'\n", node_inc[i]); + /* * Each node can generate one region for each sub-node. Allow for * 7 sub-nodes (hash-1, signature-1, etc.) and some extra. @@ -589,9 +593,8 @@ static int fit_config_verify_key(const void *fit, int conf_noffset, return 0; error: - printf(" error!\n%s for '%s' hash node in '%s' config node\n", - err_msg, fit_get_name(fit, noffset, NULL), - fit_get_name(fit, conf_noffset, NULL)); + printf(" error!\n%s for '%s' config node\n", + err_msg, fit_get_name(fit, conf_noffset, NULL)); return -EPERM; } diff --git a/boot/image-sig.c b/boot/image-sig.c index 6bc74866eae..4eab017bc2d 100644 --- a/boot/image-sig.c +++ b/boot/image-sig.c @@ -5,8 +5,6 @@ #include #include -#include -DECLARE_GLOBAL_DATA_PTR; #include #include #include diff --git a/boot/image.c b/boot/image.c index dd96f712b6f..185d52ba492 100644 --- a/boot/image.c +++ b/boot/image.c @@ -15,21 +15,14 @@ #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS -#include -#endif - #if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT) #include #include #endif -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Set this if we have less than 4 MB of malloc() space */ #if CONFIG_SYS_MALLOC_LEN < (4096 * 1024) #define CONSERVE_MEMORY true diff --git a/cmd/Kconfig b/cmd/Kconfig index 322ebe600c5..f47ce7f45ce 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -223,6 +223,7 @@ config CMD_LICENSE config CMD_PMC bool "pmc" + depends on ACPI_PMC help Provides access to the Intel Power-Management Controller (PMC) so that its state can be examined. This does not currently support @@ -298,6 +299,7 @@ config CMD_BOOTD config CMD_BOOTM bool "bootm" + depends on LMB default y select LIB_BOOTM help @@ -376,6 +378,7 @@ config BOOTM_ELF config CMD_BOOTZ bool "bootz" + depends on LMB select LIB_BOOTZ select LIB_BOOTM help @@ -384,6 +387,7 @@ config CMD_BOOTZ config CMD_BOOTI bool "booti" depends on ARM64 || RISCV || SANDBOX + depends on LMB default y select LIB_BOOTI select LIB_BOOTM @@ -1408,6 +1412,7 @@ config CMD_LOADM config CMD_LOADS bool "loads - Load a file over serial in S-Record format" + depends on LMB default y help Load an S-Record file over serial line @@ -1663,6 +1668,15 @@ config CMD_PART Read and display information about the partition table on various media. +config CMD_PART_DUPCHECK + bool "part dupcheck" + depends on CMD_PART && BLK + help + Adds the 'part dupcheck' subcommand, which scans all block devices + and reports any duplicate partition UUIDs (PARTUUIDs) or partition + labels (PARTLABELs). Returns failure if any duplicates are found, + making it suitable for use in boot scripts. + config CMD_PCI bool "pci - Access PCI devices" help @@ -1715,7 +1729,8 @@ config CMD_REMOTEPROC config CMD_SATA bool "sata - Access SATA subsystem" - select SATA + depends on SATA && AHCI + default y help SATA (Serial Advanced Technology Attachment) is a serial bus standard for connecting to hard drives and other storage devices. @@ -2186,6 +2201,7 @@ endif # if NET config CMD_DHCP bool "dhcp" select PROT_DHCP_LWIP if NET_LWIP + select CMD_BOOTP if NET help Boot image via network using DHCP/TFTP protocol @@ -2220,6 +2236,7 @@ config CMD_MDIO config CMD_NFS bool "nfs" + select PROT_UDP_LWIP if NET_LWIP help Boot image via network using NFS protocol. @@ -2304,7 +2321,7 @@ config WGET_BUILTIN_CACERT_PATH config CMD_PXE bool "pxe" select PXE_UTILS - imply CMD_TFTPBOOT + select CMD_TFTPBOOT help Boot image via network using PXE protocol diff --git a/cmd/Makefile b/cmd/Makefile index 4cd13d4fa6e..6b69da1f2b0 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -105,7 +105,6 @@ obj-$(CONFIG_CMD_IRQ) += irq.o obj-$(CONFIG_CMD_ITEST) += itest.o obj-$(CONFIG_CMD_JFFS2) += jffs2.o obj-$(CONFIG_CMD_CRAMFS) += cramfs.o -obj-$(CONFIG_LED_STATUS_CMD) += legacy_led.o obj-$(CONFIG_CMD_LED) += led.o obj-$(CONFIG_CMD_LICENSE) += license.o obj-y += load.o diff --git a/cmd/bloblist.c b/cmd/bloblist.c index 333ae558142..318a1af0220 100644 --- a/cmd/bloblist.c +++ b/cmd/bloblist.c @@ -8,9 +8,6 @@ #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int do_bloblist_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index b8f5bb35950..85f41c3b0a0 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -17,11 +17,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static struct efi_device_path *test_image_path; static struct efi_device_path *test_device_path; diff --git a/cmd/bootm.c b/cmd/bootm.c index 2c5aea26d98..ca7cec91fad 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -15,14 +15,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_CMD_IMI) static int image_info(unsigned long addr); #endif diff --git a/cmd/date.c b/cmd/date.c index 8614f022761..d047872289c 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -11,9 +11,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static const char * const weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 109496d9e95..7b733119c82 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -533,6 +533,47 @@ static int do_efi_show_defaults(struct cmd_tbl *cmdtp, int flag, return CMD_RET_SUCCESS; } +#if CONFIG_IS_ENABLED(EFI_ECPT) +/** + * do_efi_show_ecpt() - show UEFI conformance profiles in ECPT + * + * @cmdtp: Command table + * @flag: Command flag + * @argc: Number of arguments + * @argv: Argument array + * Return: CMD_RET_SUCCESS on success, + * CMD_RET_USAGE or CMD_RET_FAILURE on failure + * + * Implement efidebug "ecpt" sub-command. + * Show all the UEFI Conformance Profiles listed in the EFI Conformance Profiles + * Table (ECPT). + */ +static int do_efi_show_ecpt(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + const struct efi_conformance_profiles_table *ecpt; + u16 n; + + if (argc != 1) + return CMD_RET_USAGE; + + ecpt = efi_get_configuration_table(&efi_ecpt_guid); + if (!ecpt) { + log_err("ECPT table missing\n"); + return CMD_RET_FAILURE; + } + + for (n = 0; n < ecpt->number_of_profiles; n++) { + const efi_guid_t *guid = &ecpt->conformance_profiles[n]; + + printf("%pUl %s\n", guid->b, + uuid_guid_get_str(guid->b) ?: "(unknown)"); + } + + return CMD_RET_SUCCESS; +} +#endif /* CONFIG_IS_ENABLED(EFI_ECPT) */ + static const char * const efi_mem_type_string[] = { [EFI_RESERVED_MEMORY_TYPE] = "RESERVED", [EFI_LOADER_CODE] = "LOADER CODE", @@ -1586,6 +1627,10 @@ static struct cmd_tbl cmd_efidebug_sub[] = { "", ""), U_BOOT_CMD_MKENT(defaults, CONFIG_SYS_MAXARGS, 1, do_efi_show_defaults, "", ""), +#if CONFIG_IS_ENABLED(EFI_ECPT) + U_BOOT_CMD_MKENT(ecpt, CONFIG_SYS_MAXARGS, 1, do_efi_show_ecpt, + "", ""), +#endif U_BOOT_CMD_MKENT(images, CONFIG_SYS_MAXARGS, 1, do_efi_show_images, "", ""), U_BOOT_CMD_MKENT(memmap, CONFIG_SYS_MAXARGS, 1, do_efi_show_memmap, @@ -1680,6 +1725,10 @@ U_BOOT_LONGHELP(efidebug, " - show UEFI handles\n" "efidebug defaults\n" " - show default EFI filename and PXE architecture\n" +#if CONFIG_IS_ENABLED(EFI_ECPT) + "efidebug ecpt\n" + " - show conformance profiles in the ECPT\n" +#endif "efidebug images\n" " - show loaded images\n" "efidebug memmap\n" diff --git a/cmd/ide.c b/cmd/ide.c index ed30f946866..f99fb6f5824 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -21,10 +21,6 @@ #include -#ifdef CONFIG_LED_STATUS -# include -#endif - /* Current I/O Device */ static int curr_device; diff --git a/cmd/legacy_led.c b/cmd/legacy_led.c deleted file mode 100644 index 4e0d09522ad..00000000000 --- a/cmd/legacy_led.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Jason Kridner - * - * Based on cmd_led.c patch from: - * http://www.mail-archive.com/u-boot@lists.denx.de/msg06873.html - * (C) Copyright 2008 - * Ulf Samuelsson - */ - -#include -#include -#include -#include - -struct led_tbl_s { - char *string; /* String for use in the command */ - led_id_t mask; /* Mask used for calling __led_set() */ - void (*off)(void); /* Optional function for turning LED off */ - void (*on)(void); /* Optional function for turning LED on */ - void (*toggle)(void);/* Optional function for toggling LED */ -}; - -typedef struct led_tbl_s led_tbl_t; - -static const led_tbl_t led_commands[] = { -#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC -#ifdef CONFIG_LED_STATUS0 - { "0", CONFIG_LED_STATUS_BIT, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS1 - { "1", CONFIG_LED_STATUS_BIT1, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS2 - { "2", CONFIG_LED_STATUS_BIT2, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS3 - { "3", CONFIG_LED_STATUS_BIT3, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS4 - { "4", CONFIG_LED_STATUS_BIT4, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS5 - { "5", CONFIG_LED_STATUS_BIT5, NULL, NULL, NULL }, -#endif -#endif - { NULL, 0, NULL, NULL, NULL } -}; - -enum led_cmd { LED_ON, LED_OFF, LED_TOGGLE, LED_BLINK }; - -enum led_cmd get_led_cmd(char *var) -{ - if (strcmp(var, "off") == 0) - return LED_OFF; - if (strcmp(var, "on") == 0) - return LED_ON; - if (strcmp(var, "toggle") == 0) - return LED_TOGGLE; - if (strcmp(var, "blink") == 0) - return LED_BLINK; - - return -1; -} - -/* - * LED drivers providing a blinking LED functionality, like the - * PCA9551, can override this empty weak function - */ -void __weak __led_blink(led_id_t mask, int freq) -{ -} - -int do_legacy_led(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, match = 0; - enum led_cmd cmd; - int freq; - - /* Validate arguments */ - if ((argc < 3) || (argc > 4)) - return CMD_RET_USAGE; - - cmd = get_led_cmd(argv[2]); - if (cmd < 0) { - return CMD_RET_USAGE; - } - - for (i = 0; led_commands[i].string; i++) { - if ((strcmp("all", argv[1]) == 0) || - (strcmp(led_commands[i].string, argv[1]) == 0)) { - match = 1; - switch (cmd) { - case LED_ON: - if (led_commands[i].on) - led_commands[i].on(); - else - __led_set(led_commands[i].mask, - CONFIG_LED_STATUS_ON); - break; - case LED_OFF: - if (led_commands[i].off) - led_commands[i].off(); - else - __led_set(led_commands[i].mask, - CONFIG_LED_STATUS_OFF); - break; - case LED_TOGGLE: - if (led_commands[i].toggle) - led_commands[i].toggle(); - else - __led_toggle(led_commands[i].mask); - break; - case LED_BLINK: - if (argc != 4) - return CMD_RET_USAGE; - - freq = dectoul(argv[3], NULL); - __led_blink(led_commands[i].mask, freq); - } - /* Need to set only 1 led if led_name wasn't 'all' */ - if (strcmp("all", argv[1]) != 0) - break; - } - } - - /* If we ran out of matches, print Usage */ - if (!match) { - return CMD_RET_USAGE; - } - - return 0; -} - -U_BOOT_CMD( - led, 4, 1, do_legacy_led, - "[" -#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC -#ifdef CONFIG_LED_STATUS0 - "0|" -#endif -#ifdef CONFIG_LED_STATUS1 - "1|" -#endif -#ifdef CONFIG_LED_STATUS2 - "2|" -#endif -#ifdef CONFIG_LED_STATUS3 - "3|" -#endif -#ifdef CONFIG_LED_STATUS4 - "4|" -#endif -#ifdef CONFIG_LED_STATUS5 - "5|" -#endif -#endif - "all] [on|off|toggle|blink] [blink-freq in ms]", - "[led_name] [on|off|toggle|blink] sets or clears led(s)" -); diff --git a/cmd/mem.c b/cmd/mem.c index d5d7ca2790b..68eb6989b94 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -26,16 +26,14 @@ #include #include #include +#include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Create a compile-time value */ #if MEM_SUPPORT_64BIT_DATA #define HELP_Q ", .q" diff --git a/cmd/mmc.c b/cmd/mmc.c index 6cb1ef5dc23..81b1ca4ad84 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -29,12 +29,12 @@ static void print_mmcinfo(struct mmc *mmc) printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24); if (IS_SD(mmc)) { printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff); - printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff, + printf("Name: %c%c%c%c%c\n", mmc->cid[0] & 0xff, (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); } else { printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xff); - printf("Name: %c%c%c%c%c%c \n", mmc->cid[0] & 0xff, + printf("Name: %c%c%c%c%c%c\n", mmc->cid[0] & 0xff, (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, (mmc->cid[2] >> 24)); diff --git a/cmd/part.c b/cmd/part.c index 975a0a08a99..5e520d707f3 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -15,10 +15,15 @@ * Pavel Bartusek */ -#include +#include +#include #include +#include +#include #include +#include #include +#include #include #include @@ -246,6 +251,205 @@ static int do_part_type(int argc, char *const argv[]) } #endif +#if CONFIG_IS_ENABLED(CMD_PART_DUPCHECK) +struct part_seen { + char uuid[UUID_STR_LEN + 1]; + char name[PART_NAME_LEN + 1]; + struct udevice *dev; + int part; +}; + +static int compare_uuid(const void *a, const void *b) +{ + const struct part_seen *pa = a; + const struct part_seen *pb = b; + + /* Sort empty UUIDs to the end */ + if (!pa->uuid[0] && !pb->uuid[0]) + return 0; + if (!pa->uuid[0]) + return 1; + if (!pb->uuid[0]) + return -1; + + return strcmp(pa->uuid, pb->uuid); +} + +static int compare_name(const void *a, const void *b) +{ + const struct part_seen *pa = a; + const struct part_seen *pb = b; + + /* Sort empty names to the end */ + if (!pa->name[0] && !pb->name[0]) + return 0; + if (!pa->name[0]) + return 1; + if (!pb->name[0]) + return -1; + + return strcmp(pa->name, pb->name); +} + +/** + * detect_duplicates() - Sort and detect duplicate fields in the partition list + * + * Sorts the seen list using the given comparator, then performs a single + * linear pass to find and report consecutive duplicate entries. + * + * @seen: The list of collected partition entries + * @cmp: Comparator function for qsort (must sort empties to the end) + * @field_label: Human-readable label for reporting (e.g. "PARTUUID", "PARTLABEL") + * @field_off: Offset of the string field within struct part_seen + * @dup_groups: Output: number of distinct duplicate values found + * @total: Total number of partitions that have this field set + */ +static void detect_duplicates(struct alist *seen, + int (*cmp)(const void *, const void *), + const char *field_label, size_t field_off, + int *dup_groups, int total) +{ + const struct part_seen *pi; + const struct part_seen *pj; + const char *field_i; + const char *field_j; + int occurrences; + int count = seen->count; + int dup_parts = 0; + + *dup_groups = 0; + + qsort(seen->data, count, sizeof(struct part_seen), cmp); + + for (int i = 0; i < count; i++) { + pi = alist_get(seen, i, struct part_seen); + field_i = (const char *)pi + field_off; + occurrences = 1; + + if (!field_i[0]) + break; /* Reached empty fields at the end */ + + /* Count consecutive duplicates */ + while (i + occurrences < count) { + pj = alist_get(seen, i + occurrences, struct part_seen); + field_j = (const char *)pj + field_off; + + if (strcmp(field_i, field_j) != 0) + break; + occurrences++; + } + + if (occurrences > 1) { + printf("Warning: duplicate %s %s (%d copies)\n", + field_label, field_i, occurrences); + for (int j = 0; j < occurrences; j++) { + pj = alist_get(seen, i + j, struct part_seen); + printf(" found on %s:%d\n", + pj->dev->name, + pj->part); + } + + (*dup_groups)++; + dup_parts += occurrences; + i += occurrences - 1; + } + } + + if (*dup_groups) + printf("Found %d duplicate %s(s) (%d total copies) among %d partitions\n", + *dup_groups, field_label, dup_parts, total); +} + +static int do_part_dupcheck(int argc, char *const argv[]) +{ + struct alist seen; + int uuid_count = 0; + int label_count = 0; + int duplicate_uuids = 0; + int duplicate_labels = 0; + struct udevice *dev; + + if (argc) + return CMD_RET_USAGE; + + if (!blk_count_devices(BLKF_BOTH)) { + printf("No block devices found\n"); + return CMD_RET_SUCCESS; + } + + alist_init_struct(&seen, struct part_seen); + + /* First pass: collect all partitions with UUIDs or labels */ + blk_foreach_probe(BLKF_BOTH, dev) { + struct blk_desc *desc = dev_get_uclass_plat(dev); + + for (int part = 1; part <= MAX_SEARCH_PARTITIONS; part++) { + struct disk_partition info; + struct part_seen entry; + bool has_uuid; + bool has_label; + + if (part_get_info(desc, part, &info)) + continue; + has_uuid = disk_partition_uuid(&info)[0] != '\0'; + has_label = info.name[0] != '\0'; + if (!has_uuid && !has_label) + continue; + + memset(&entry, 0, sizeof(entry)); + if (has_uuid) + strlcpy(entry.uuid, disk_partition_uuid(&info), + sizeof(entry.uuid)); + if (has_label) + strlcpy(entry.name, (const char *)info.name, + sizeof(entry.name)); + entry.dev = dev; + entry.part = part; + + if (has_uuid) + uuid_count++; + if (has_label) + label_count++; + + if (!alist_add(&seen, entry)) { + printf("Unable to grow dupcheck list\n"); + alist_uninit(&seen); + return CMD_RET_FAILURE; + } + } + } + + if (!seen.count) { + printf("No partitions with UUID or label found\n"); + alist_uninit(&seen); + return CMD_RET_SUCCESS; + } + + /* Detect duplicate UUIDs */ + detect_duplicates(&seen, compare_uuid, "PARTUUID", + offsetof(struct part_seen, uuid), + &duplicate_uuids, uuid_count); + + /* Detect duplicate partition labels */ + detect_duplicates(&seen, compare_name, "PARTLABEL", + offsetof(struct part_seen, name), + &duplicate_labels, label_count); + + if (!duplicate_uuids && !duplicate_labels) + printf("No duplicate PARTUUIDs or PARTLABELs found (%d UUIDs, %d labels)\n", + uuid_count, label_count); + else if (!duplicate_uuids) + printf("No duplicate PARTUUIDs found (%d UUIDs)\n", uuid_count); + else if (!duplicate_labels) + printf("No duplicate PARTLABELs found (%d labels)\n", label_count); + + alist_uninit(&seen); + + return (duplicate_uuids || duplicate_labels) ? + CMD_RET_FAILURE : CMD_RET_SUCCESS; +} +#endif + static int do_part_types(int argc, char * const argv[]) { struct part_driver *drv = ll_entry_start(struct part_driver, @@ -291,6 +495,10 @@ static int do_part(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_PARTITION_TYPE_GUID else if (!strcmp(argv[1], "type")) return do_part_type(argc - 2, argv + 2); +#endif +#if CONFIG_IS_ENABLED(CMD_PART_DUPCHECK) + else if (!strcmp(argv[1], "dupcheck")) + return do_part_dupcheck(argc - 2, argv + 2); #endif return CMD_RET_USAGE; } @@ -329,4 +537,9 @@ U_BOOT_CMD( " - set partition type for a device\n" "part types\n" " - list supported partition table types" +#if CONFIG_IS_ENABLED(CMD_PART_DUPCHECK) + "\n" + "part dupcheck\n" + " - scan all block devices for duplicate partition UUIDs and labels" +#endif ); diff --git a/cmd/smbios.c b/cmd/smbios.c index ed419f19028..3fafa46d0a5 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -119,6 +119,149 @@ static const struct str_lookup_table associativity_strings[] = { }; +static const struct str_lookup_table slot_type_strings[] = { + { SMBIOS_SYSSLOT_TYPE_OTHER, "Other" }, + { SMBIOS_SYSSLOT_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_TYPE_ISA, "ISA" }, + { SMBIOS_SYSSLOT_TYPE_PCI, "PCI" }, + { SMBIOS_SYSSLOT_TYPE_PCMCIA, "PC Card (PCMCIA)" }, + { SMBIOS_SYSSLOT_TYPE_PCIE, "PCI Express" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN2, "PCI Express Gen 2" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN3, "PCI Express Gen 3" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16, "PCI Express Gen 3 x16" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN4, "PCI Express Gen 4" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8, "PCI Express Gen 4 x8" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16, "PCI Express Gen 4 x16" }, +}; + +static const struct str_lookup_table slot_bus_width_strings[] = { + { SMBIOS_SYSSLOT_WIDTH_OTHER, "Other" }, + { SMBIOS_SYSSLOT_WIDTH_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_WIDTH_8BIT, "8 bit" }, + { SMBIOS_SYSSLOT_WIDTH_16BIT, "16 bit" }, + { SMBIOS_SYSSLOT_WIDTH_32BIT, "32 bit" }, + { SMBIOS_SYSSLOT_WIDTH_64BIT, "64 bit" }, + { SMBIOS_SYSSLOT_WIDTH_128BIT, "128 bit " }, + { SMBIOS_SYSSLOT_WIDTH_1X, "1x or x1" }, + { SMBIOS_SYSSLOT_WIDTH_2X, "2x or x2" }, + { SMBIOS_SYSSLOT_WIDTH_4X, "4x or x4" }, + { SMBIOS_SYSSLOT_WIDTH_8X, "8x or x8" }, + { SMBIOS_SYSSLOT_WIDTH_12X, "12x or x12" }, + { SMBIOS_SYSSLOT_WIDTH_16X, "16x or x16" }, + { SMBIOS_SYSSLOT_WIDTH_32X, "32x or x32" }, +}; + +static const struct str_lookup_table slot_usage_strings[] = { + { SMBIOS_SYSSLOT_USAGE_OTHER, "Other" }, + { SMBIOS_SYSSLOT_USAGE_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_USAGE_AVAILABLE, "Available" }, + { SMBIOS_SYSSLOT_USAGE_INUSE, "In use" }, + { SMBIOS_SYSSLOT_USAGE_NA, "Unavailable" }, +}; + +static const struct str_lookup_table slot_length_strings[] = { + { SMBIOS_SYSSLOT_LENG_OTHER, "Other" }, + { SMBIOS_SYSSLOT_LENG_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_LENG_SHORT, "Short Length" }, + { SMBIOS_SYSSLOT_LENG_LONG, "Long Length" }, + { SMBIOS_SYSSLOT_LENG_2_5INDRV, "2.5 inch drive form factor" }, + { SMBIOS_SYSSLOT_LENG_3_5INDRV, "3.5 inch drive form factor" }, +}; + +static const struct str_lookup_table ma_location_strings[] = { + { SMBIOS_MA_LOCATION_OTHER, "Other" }, + { SMBIOS_MA_LOCATION_UNKNOWN, "Unknown" }, + { SMBIOS_MA_LOCATION_MOTHERBOARD, "System board or motherboard" }, +}; + +static const struct str_lookup_table ma_use_strings[] = { + { SMBIOS_MA_USE_OTHER, "Other" }, + { SMBIOS_MA_USE_UNKNOWN, "Unknown" }, + { SMBIOS_MA_USE_SYSTEM, "System memory" }, + { SMBIOS_MA_USE_VIDEO, "Video memory" }, + { SMBIOS_MA_USE_FLASH, "Flash memory" }, + { SMBIOS_MA_USE_NVRAM, "Non-volatile RAM" }, + { SMBIOS_MA_USE_CACHE, "Cache memory" }, +}; + +static const struct str_lookup_table ma_err_corr_strings[] = { + { SMBIOS_MA_ERRCORR_OTHER, "Other" }, + { SMBIOS_MA_ERRCORR_UNKNOWN, "Unknown" }, + { SMBIOS_MA_ERRCORR_NONE, "None" }, + { SMBIOS_MA_ERRCORR_PARITY, "Parity" }, + { SMBIOS_MA_ERRCORR_SBITECC, "Single-bit ECC" }, + { SMBIOS_MA_ERRCORR_MBITECC, "Multi-bit ECC" }, + { SMBIOS_MA_ERRCORR_CRC, "CRC" }, +}; + +static const struct str_lookup_table md_form_factor_strings[] = { + { SMBIOS_MD_FF_OTHER, "Other" }, + { SMBIOS_MD_FF_UNKNOWN, "Unknown" }, + { SMBIOS_MD_FF_SIMM, "SIMM" }, + { SMBIOS_MD_FF_SIP, "SIP" }, + { SMBIOS_MD_FF_CHIP, "Chip" }, + { SMBIOS_MD_FF_DIP, "DIP" }, + { SMBIOS_MD_FF_ZIP, "ZIP" }, + { SMBIOS_MD_FF_PROPCARD, "Proprietary Card" }, + { SMBIOS_MD_FF_DIMM, "DIMM" }, + { SMBIOS_MD_FF_TSOP, "TSOP" }, + { SMBIOS_MD_FF_ROC, "Row of chips" }, + { SMBIOS_MD_FF_RIMM, "RIMM" }, + { SMBIOS_MD_FF_SODIMM, "SODIMM" }, + { SMBIOS_MD_FF_SRIMM, "SRIMM" }, + { SMBIOS_MD_FF_FBDIMM, "FB-DIMM" }, + { SMBIOS_MD_FF_DIE, "Die" }, +}; + +static const struct str_lookup_table md_type_strings[] = { + { SMBIOS_MD_TYPE_OTHER, "Other" }, + { SMBIOS_MD_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_MD_TYPE_DRAM, "DRAM" }, + { SMBIOS_MD_TYPE_EDRAM, "EDRAM" }, + { SMBIOS_MD_TYPE_VRAM, "VRAM" }, + { SMBIOS_MD_TYPE_SRAM, "SRAM" }, + { SMBIOS_MD_TYPE_RAM, "RAM" }, + { SMBIOS_MD_TYPE_ROM, "ROM" }, + { SMBIOS_MD_TYPE_FLASH, "FLASH" }, + { SMBIOS_MD_TYPE_EEPROM, "EEPROM" }, + { SMBIOS_MD_TYPE_FEPROM, "FEPROM" }, + { SMBIOS_MD_TYPE_EPROM, "EPROM" }, + { SMBIOS_MD_TYPE_CDRAM, "CDRAM" }, + { SMBIOS_MD_TYPE_3DRAM, "3DRAM" }, + { SMBIOS_MD_TYPE_SDRAM, "SDRAM" }, + { SMBIOS_MD_TYPE_SGRAM, "SGRAM" }, + { SMBIOS_MD_TYPE_RDRAM, "RDRAM" }, + { SMBIOS_MD_TYPE_DDR, "DDR" }, + { SMBIOS_MD_TYPE_DDR2, "DDR2" }, + { SMBIOS_MD_TYPE_DDR2FBD, "DDR2 FB-DIMM" }, + { SMBIOS_MD_TYPE_RSVD1, "Reserved" }, + { SMBIOS_MD_TYPE_RSVD2, "Reserved" }, + { SMBIOS_MD_TYPE_DSVD3, "Reserved" }, + { SMBIOS_MD_TYPE_DDR3, "DDR3" }, + { SMBIOS_MD_TYPE_FBD2, "FBD2" }, + { SMBIOS_MD_TYPE_DDR4, "DDR4" }, + { SMBIOS_MD_TYPE_LPDDR, "LPDDR" }, + { SMBIOS_MD_TYPE_LPDDR2, "LPDDR2" }, + { SMBIOS_MD_TYPE_LPDDR3, "LPDDR3" }, + { SMBIOS_MD_TYPE_LPDDR4, "LPDDR4" }, + { SMBIOS_MD_TYPE_LNVD, "Logical non-volatile device" }, + { SMBIOS_MD_TYPE_HBM, "HBM" }, + { SMBIOS_MD_TYPE_HBM2, "HBM2" }, + { SMBIOS_MD_TYPE_DDR5, "DDR5" }, + { SMBIOS_MD_TYPE_LPDDR5, "LPDDR5" }, + { SMBIOS_MD_TYPE_HBM3, "HBM3" }, +}; + +static const struct str_lookup_table md_tech_strings[] = { + { SMBIOS_MD_TECH_OTHER, "Other" }, + { SMBIOS_MD_TECH_UNKNOWN, "Unknown" }, + { SMBIOS_MD_TECH_DRAM, "DRAM" }, + { SMBIOS_MD_TECH_NVDIMMN, "NVDIMM-N" }, + { SMBIOS_MD_TECH_NVDIMMF, "NVDIMM-F" }, + { SMBIOS_MD_TECH_NVDIMMP, "NVDIMM-P" }, + { SMBIOS_MD_TECH_OPTANE, "Intel Optane persistent memory" }, +}; + /** * smbios_get_string() - get SMBIOS string from table * @@ -205,6 +348,8 @@ static void smbios_print_type0(struct smbios_type0 *table) printf("\tBIOS ROM Size: 0x%02x\n", table->bios_rom_size); printf("\tBIOS Characteristics: 0x%016llx\n", table->bios_characteristics); + if (table->hdr.length < SMBIOS_TYPE0_LENGTH_V24) + return; printf("\tBIOS Characteristics Extension Byte 1: 0x%02x\n", table->bios_characteristics_ext1); printf("\tBIOS Characteristics Extension Byte 2: 0x%02x\n", @@ -217,6 +362,8 @@ static void smbios_print_type0(struct smbios_type0 *table) table->ec_major_release); printf("\tEmbedded Controller Firmware Minor Release: 0x%02x\n", table->ec_minor_release); + if (table->hdr.length < SMBIOS_TYPE0_LENGTH_V31) + return; printf("\tExtended BIOS ROM Size: 0x%04x\n", table->extended_bios_rom_size); } @@ -228,17 +375,16 @@ static void smbios_print_type1(struct smbios_type1 *table) smbios_print_str("Product Name", table, table->product_name); smbios_print_str("Version", table, table->version); smbios_print_str("Serial Number", table, table->serial_number); - if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V21) { - printf("\tUUID: %pUl\n", table->uuid); - smbios_print_lookup_str(wakeup_type_strings, - table->wakeup_type, - ARRAY_SIZE(wakeup_type_strings), - "Wake-up Type"); - } - if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V24) { - smbios_print_str("SKU Number", table, table->sku_number); - smbios_print_str("Family", table, table->family); - } + if (table->hdr.length < SMBIOS_TYPE1_LENGTH_V21) + return; + printf("\tUUID: %pUl\n", table->uuid); + smbios_print_lookup_str(wakeup_type_strings, table->wakeup_type, + ARRAY_SIZE(wakeup_type_strings), + "Wake-up Type"); + if (table->hdr.length < SMBIOS_TYPE1_LENGTH_V24) + return; + smbios_print_str("SKU Number", table, table->sku_number); + smbios_print_str("Family", table, table->family); } static void smbios_print_type2(struct smbios_type2 *table) @@ -358,21 +504,31 @@ static void smbios_print_type4(struct smbios_type4 *table) printf("\tL1 Cache Handle: 0x%04x\n", table->l1_cache_handle); printf("\tL2 Cache Handle: 0x%04x\n", table->l2_cache_handle); printf("\tL3 Cache Handle: 0x%04x\n", table->l3_cache_handle); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V23) + return; smbios_print_str("Serial Number", table, table->serial_number); smbios_print_str("Asset Tag", table, table->asset_tag); smbios_print_str("Part Number", table, table->part_number); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V25) + return; printf("\tCore Count: 0x%02x\n", table->core_count); printf("\tCore Enabled: 0x%02x\n", table->core_enabled); printf("\tThread Count: 0x%02x\n", table->thread_count); printf("\tProcessor Characteristics: 0x%04x\n", table->processor_characteristics); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V26) + return; smbios_print_lookup_str(processor_family_strings, table->processor_family2, ARRAY_SIZE(processor_family_strings), "Processor Family 2"); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V30) + return; printf("\tCore Count 2: 0x%04x\n", table->core_count2); printf("\tCore Enabled 2: 0x%04x\n", table->core_enabled2); printf("\tThread Count 2: 0x%04x\n", table->thread_count2); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V36) + return; printf("\tThread Enabled: 0x%04x\n", table->thread_enabled); } @@ -386,6 +542,8 @@ static void smbios_print_type7(struct smbios_type7 *table) printf("\tInstalled Size: 0x%04x\n", table->inst_size.data); printf("\tSupported SRAM Type: 0x%04x\n", table->supp_sram_type.data); printf("\tCurrent SRAM Type: 0x%04x\n", table->curr_sram_type.data); + if (table->hdr.length < SMBIOS_TYPE7_LENGTH_V21) + return; printf("\tCache Speed: 0x%02x\n", table->speed); smbios_print_lookup_str(err_corr_type_strings, table->err_corr_type, @@ -399,10 +557,183 @@ static void smbios_print_type7(struct smbios_type7 *table) table->associativity, ARRAY_SIZE(associativity_strings), "Associativity"); + if (table->hdr.length < SMBIOS_TYPE7_LENGTH_V31) + return; printf("\tMaximum Cache Size 2: 0x%08x\n", table->max_size2.data); printf("\tInstalled Cache Size 2: 0x%08x\n", table->inst_size2.data); } +static void smbios_print_type9(struct smbios_type9 *table) +{ + int i; + u8 *addr = (u8 *)table + + offsetof(struct smbios_type9, slot_information); + + printf("System Slots:\n"); + smbios_print_str("Socket Designation", table, + table->socket_design); + smbios_print_lookup_str(slot_type_strings, + table->slot_type, + ARRAY_SIZE(slot_type_strings), + "Slot Type"); + smbios_print_lookup_str(slot_bus_width_strings, + table->slot_data_bus_width, + ARRAY_SIZE(slot_bus_width_strings), + "Slot Data Bus Width"); + smbios_print_lookup_str(slot_usage_strings, + table->current_usage, + ARRAY_SIZE(slot_usage_strings), + "Current Usage"); + smbios_print_lookup_str(slot_length_strings, + table->slot_length, + ARRAY_SIZE(slot_length_strings), + "Slot Length"); + printf("\tSlot ID: 0x%04x\n", table->slot_id); + printf("\tSlot Characteristics 1: 0x%04x\n", + table->slot_characteristics_1); + if (table->hdr.length < SMBIOS_TYPE9_LENGTH_V21) + return; + printf("\tSlot Characteristics 2: 0x%04x\n", + table->slot_characteristics_2); + if (table->hdr.length < SMBIOS_TYPE9_LENGTH_V26) + return; + printf("\tSegment Group Number (Base): 0x%04x\n", + table->segment_group_number); + printf("\tBus Number (Base): 0x%04x\n", table->bus_number); + printf("\tDevice/Function Number (Base): 0x%04x\n", + table->device_function_number.data); + printf("\tData Bus Width (Base): 0x%04x\n", + table->electrical_bus_width); + printf("\tPeer (S/B/D/F/Width) grouping count: 0x%04x\n", + table->peer_grouping_count); + printf("\tPeer (S/B/D/F/Width) groups:\n"); + for (i = 0; i < table->peer_grouping_count; i++) { + printf("\t\tPeer group[%03d]:\n", i); + if (CONFIG_IS_ENABLED(HEXDUMP)) + print_hex_dump("\t\t", DUMP_PREFIX_OFFSET, 16, 1, addr, + SMBIOS_TYPE9_PGROUP_SIZE, false); + addr += SMBIOS_TYPE9_PGROUP_SIZE; + } + printf("\n"); + + /* table->slot_information */ + printf("\tSlot Information: 0x%04x\n", *addr); + /* table->slot_physical_width */ + addr += sizeof(table->slot_information); + printf("\tSlot Physical Width: 0x%04x\n", *addr); + /* table->slot_pitch */ + addr += sizeof(table->slot_physical_width); + printf("\tSlot Pitch: 0x%04x\n", *(u16 *)addr); + /* table->slot_height */ + addr += sizeof(table->slot_pitch); + printf("\tSlot Height: 0x%04x\n", *addr); +} + +static void smbios_print_type16(struct smbios_type16 *table) +{ + printf("Physical Memory Array:\n"); + if (table->hdr.length < SMBIOS_TYPE16_LENGTH_V21) + return; + smbios_print_lookup_str(ma_location_strings, table->location, + ARRAY_SIZE(ma_location_strings), "Location"); + smbios_print_lookup_str(ma_use_strings, table->use, + ARRAY_SIZE(ma_use_strings), "Use"); + smbios_print_lookup_str(ma_err_corr_strings, table->mem_err_corr, + ARRAY_SIZE(ma_err_corr_strings), + "Memory Error Correction"); + printf("\tMaximum Capacity: 0x%08x\n", table->max_cap); + printf("\tMemory Error Information Handle: 0x%04x\n", + table->mem_err_info_hdl); + printf("\tNumber of Memory Devices: 0x%04x\n", table->num_of_mem_dev); + if (table->hdr.length < SMBIOS_TYPE16_LENGTH_V27) + return; + printf("\tExtended Maximum Capacity: 0x%016llx\n", table->ext_max_cap); +} + +static void smbios_print_type17(struct smbios_type17 *table) +{ + printf("Memory Device:\n"); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V21) + return; + printf("\tPhysical Memory Array Handle: 0x%04x\n", + table->phy_mem_array_hdl); + printf("\tMemory Error Information Handle: 0x%04x\n", + table->mem_err_info_hdl); + printf("\tTotal Width: 0x%04x\n", table->total_width); + printf("\tData Width: 0x%04x\n", table->data_width); + printf("\tSize: 0x%04x\n", table->size); + smbios_print_lookup_str(md_form_factor_strings, table->form_factor, + ARRAY_SIZE(md_form_factor_strings), + "Form Factor"); + printf("\tDevice Set: 0x%04x\n", table->dev_set); + smbios_print_str("Device Locator", table, table->dev_locator); + smbios_print_str("Bank Locator", table, table->bank_locator); + smbios_print_lookup_str(md_type_strings, table->mem_type, + ARRAY_SIZE(md_type_strings), "Memory Type"); + printf("\tType Detail: 0x%04x\n", table->type_detail); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V23) + return; + printf("\tSpeed: 0x%04x\n", table->speed); + smbios_print_str("Manufacturer", table, table->manufacturer); + smbios_print_str("Serial Number", table, table->serial_number); + smbios_print_str("Asset Tag", table, table->asset_tag); + smbios_print_str("Part Number", table, table->part_number); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V26) + return; + printf("\tAttributes: 0x%04x\n", table->attributes); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V27) + return; + printf("\tExtended Size: 0x%08x\n", table->ext_size); + printf("\tConfigured Memory Speed: 0x%04x\n", table->config_mem_speed); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V28) + return; + printf("\tMinimum voltage: 0x%04x\n", table->min_voltage); + printf("\tMaximum voltage: 0x%04x\n", table->max_voltage); + printf("\tConfigured voltage: 0x%04x\n", table->config_voltage); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V32) + return; + smbios_print_lookup_str(md_tech_strings, table->mem_tech, + ARRAY_SIZE(md_tech_strings), + "Memory Technology"); + printf("\tMemory Operating Mode Capability: 0x%04x\n", + table->mem_op_mode_cap); + smbios_print_str("Firmware Version", table, table->fw_ver); + printf("\tModule Manufacturer ID: 0x%04x\n", table->module_man_id); + printf("\tModule Product ID: 0x%04x\n", table->module_prod_id); + printf("\tMemory Subsystem Controller Manufacturer ID: 0x%04x\n", + table->mem_subsys_con_man_id); + printf("\tMemory Subsystem Controller Product ID: 0x%04x\n", + table->mem_subsys_con_prod_id); + printf("\tNon-volatile Size: 0x%016llx\n", table->nonvolatile_size); + printf("\tVolatile Size: 0x%016llx\n", table->volatile_size); + printf("\tCache Size: 0x%016llx\n", table->cache_size); + printf("\tLogical Size: 0x%016llx\n", table->logical_size); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V33) + return; + printf("\tExtended Speed: 0x%04x\n", table->ext_speed); + printf("\tExtended Configured Memory Speed: 0x%04x\n", + table->ext_config_mem_speed); + printf("\tPMIC0 Manufacturer ID: 0x%04x\n", table->pmic0_man_id); + printf("\tPMIC0 Revision Number: 0x%04x\n", table->pmic0_rev_num); + printf("\tRCD Manufacturer ID: 0x%04x\n", table->rcd_man_id); + printf("\tRCD Revision Number: 0x%04x\n", table->rcd_rev_num); +} + +static void smbios_print_type19(struct smbios_type19 *table) +{ + printf("Memory Array Mapped Address:\n"); + if (table->hdr.length < SMBIOS_TYPE19_LENGTH_V21) + return; + printf("\tStarting Address: 0x%08x\n", table->start_addr); + printf("\tEnding Address: 0x%08x\n", table->end_addr); + printf("\tMemory Array Handle: 0x%04x\n", table->mem_array_hdl); + printf("\tPartition Width: 0x%04x\n", table->partition_wid); + if (table->hdr.length < SMBIOS_TYPE19_LENGTH_V27) + return; + printf("\tExtended Starting Address: 0x%016llx\n", table->ext_start_addr); + printf("\tExtended Ending Address: 0x%016llx\n", table->ext_end_addr); +} + static void smbios_print_type127(struct smbios_type127 *table) { printf("End Of Table\n"); @@ -482,6 +813,18 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int argc, case SMBIOS_CACHE_INFORMATION: smbios_print_type7((struct smbios_type7 *)pos); break; + case SMBIOS_SYSTEM_SLOTS: + smbios_print_type9((struct smbios_type9 *)pos); + break; + case SMBIOS_PHYS_MEMORY_ARRAY: + smbios_print_type16((struct smbios_type16 *)pos); + break; + case SMBIOS_MEMORY_DEVICE: + smbios_print_type17((struct smbios_type17 *)pos); + break; + case SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS: + smbios_print_type19((struct smbios_type19 *)pos); + break; case SMBIOS_END_OF_TABLE: smbios_print_type127((struct smbios_type127 *)pos); break; diff --git a/cmd/sound.c b/cmd/sound.c index 8f67cbd96e1..7546059022f 100644 --- a/cmd/sound.c +++ b/cmd/sound.c @@ -8,9 +8,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; /* Initilaise sound subsystem */ static int do_init(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/spl.c b/cmd/spl.c index f591dc07fb6..ddbbd4a8172 100644 --- a/cmd/spl.c +++ b/cmd/spl.c @@ -9,11 +9,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static const char **subcmd_list[] = { [SPL_EXPORT_FDT] = (const char * []) { diff --git a/cmd/test.c b/cmd/test.c index a9ac07e6143..c76ebf800ee 100644 --- a/cmd/test.c +++ b/cmd/test.c @@ -63,10 +63,38 @@ static int do_test(struct cmd_tbl *cmdtp, int flag, int argc, char * const *ap; int i, op, left, adv, expr, last_expr, last_unop, last_binop; - /* args? */ - if (argc < 3) + if (!strcmp(argv[0], "[")) { + if (strcmp(argv[argc - 1], "]")) { + printf("[: missing terminating ]\n"); + return 1; + } + argc--; + } + + /* + * Per POSIX, 'test' with 0 arguments should return 1, while + * 'test ' should be equivalent to 'test -n ', + * i.e. true if and only if is not empty. + * + * However, due to previous versions of U-Boot unconditionally + * returning false when 'test' was given less than two + * arguments, there are existing scripts that do + * + * test -n $somevar + * + * (i.e. without properly quoting $somevar) and expecting that + * to return false when $somevar expands to nothing. It is + * quite unlikely that anyone would use the single-argument + * form to test a string for being empty and a possible + * non-empty value for that string to be exactly "-n". So we + * interpret 'test -n' as if it was 'test -n ""'. + */ + if (argc < 2) return 1; + if (argc == 2) + return !strcmp(argv[1], "") || !strcmp(argv[1], "-n"); + #ifdef DEBUG { debug("test(%d):", argc); @@ -212,6 +240,17 @@ U_BOOT_CMD( "[args..]" ); +/* + * This does not use the U_BOOT_CMD macro as [ can't be used in symbol names + */ +ll_entry_declare(struct cmd_tbl, lbracket, cmd) = { + "[", CONFIG_SYS_MAXARGS, cmd_always_repeatable, do_test, + "alias for 'test'", +#ifdef CONFIG_SYS_LONGHELP + " ]" +#endif /* CONFIG_SYS_LONGHELP */ +}; + static int do_false(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/common/Kconfig b/common/Kconfig index 63448bdc13b..2a167ec3ad3 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -55,7 +55,7 @@ config CONSOLE_RECORD_IN_SIZE config SYS_CBSIZE int "Console input buffer size" default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \ - RCAR_GEN3 || TARGET_SOCFPGA_SOC64 + RCAR_GEN3 || ARCH_SOCFPGA_SOC64 default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \ FSL_LSCH3 || X86 default 256 if M68K || PPC diff --git a/common/board_f.c b/common/board_f.c index df2b0dc899b..11ad5779115 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include @@ -463,7 +462,7 @@ static int reserve_uboot(void) if (CONFIG_IS_ENABLED(SKIP_RELOCATE)) gd->flags |= GD_FLG_SKIP_RELOC; - if (!(gd->flags & GD_FLG_SKIP_RELOC)) { + if (!(gd->flags & GD_FLG_SKIP_RELOC) && !CONFIG_IS_ENABLED(SKIP_RELOCATE_CODE)) { /* * reserve memory for U-Boot code, data & bss * round down to next 4 kB limit diff --git a/common/board_r.c b/common/board_r.c index 76f9fc090fb..8cf0e14679c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -52,7 +52,6 @@ #include #include #include -#include #include #include #include @@ -482,17 +481,8 @@ static int initr_malloc_bootparams(void) } #endif -static int initr_status_led(void) -{ - status_led_init(); - - return 0; -} - static int initr_boot_led_blink(void) { - status_led_boot_blink(); - led_boot_blink(); return 0; @@ -758,7 +748,6 @@ static void initcall_run_r(void) #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K) INITCALL(timer_init); /* initialize timer */ #endif - INITCALL(initr_status_led); INITCALL(initr_boot_led_blink); /* PPC has a udelay(20) here dating from 2002. Why? */ #if CONFIG_IS_ENABLED(BOARD_LATE_INIT) diff --git a/common/cli_hush.c b/common/cli_hush.c index 7bd6943d3ed..fe8fe93bd54 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -83,7 +83,7 @@ #include #include #include /* find_cmd */ -#include +#include #endif #ifndef __U_BOOT__ #include /* isalpha, isdigit */ @@ -124,8 +124,6 @@ #endif #ifdef __U_BOOT__ -DECLARE_GLOBAL_DATA_PTR; - #define EXIT_SUCCESS 0 #define EOF -1 #define syntax() syntax_err() diff --git a/common/console.c b/common/console.c index 48586fd2166..22e554cf203 100644 --- a/common/console.c +++ b/common/console.c @@ -1212,13 +1212,16 @@ int console_init_r(void) list_for_each(pos, list) { dev = list_entry(pos, struct stdio_dev, list); - if ((dev->flags & DEV_FLAGS_INPUT) && (inputdev == NULL)) { + if ((dev->flags & DEV_FLAGS_INPUT) && + (dev->priv == gd->cur_serial_dev || !inputdev)) inputdev = dev; - } - if ((dev->flags & DEV_FLAGS_OUTPUT) && (outputdev == NULL)) { + + if ((dev->flags & DEV_FLAGS_OUTPUT) && + (dev->priv == gd->cur_serial_dev || !outputdev)) outputdev = dev; - } - if(inputdev && outputdev) + + /* The current serial console is the preferred stdio. */ + if (dev->priv == gd->cur_serial_dev && inputdev && outputdev) break; } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2998b7acb75..d1a85f50209 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -548,7 +548,7 @@ config SPL_SYS_MMCSD_RAW_MODE depends on SPL_DM_MMC || SPL_MMC default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \ ARCH_MX6 || ARCH_MX7 || \ - ARCH_ROCKCHIP || ARCH_MVEBU || TARGET_SOCFPGA_GEN5 || \ + ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA_GEN5 || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP54XX || AM33XX || AM43XX || \ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED @@ -593,7 +593,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR default 0x8a if ARCH_MX6 || ARCH_MX7 default 0x100 if ARCH_UNIPHIER default 0x0 if ARCH_MVEBU - default 0x200 if TARGET_SOCFPGA_GEN5 || ARCH_AT91 + default 0x200 if ARCH_SOCFPGA_GEN5 || ARCH_AT91 default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP54XX || AM33XX || AM43XX || ARCH_K3 default 0x4000 if ARCH_ROCKCHIP @@ -707,6 +707,13 @@ config SPL_DRIVERS_MISC option to build the drivers in drivers/misc as part of an SPL build, for those that support building in SPL (not all drivers do). +config SPL_REMAKE_ELF + bool "Recreate an ELF image from raw SPL binary" + help + Enable this to recreate an ELF image (spl/u-boot-spl.elf) from the raw + SPL binary (spl/u-boot-spl.bin), which may already have been statically + relocated and may already have a device-tree appended to it. + config SPL_ENV_SUPPORT bool "Support an environment" help @@ -1490,7 +1497,6 @@ config SPL_SATA_RAW_U_BOOT_SECTOR config SPL_NVME bool "NVM Express device support" depends on SPL_BLK - select FS_LOADER select SPL_BLK_FS help This option enables support for NVM Express devices. @@ -1613,6 +1619,36 @@ config SPL_THERMAL automatic power-off when the temperature gets too high or low. Other devices may be discrete but connected on a suitable bus. +config SPL_UFS_SUPPORT + bool "Support loading from UFS" + depends on UFS + select SPL_LOAD_BLOCK + help + Enable support for UFS in SPL. This allows + use of UFS devices such as hard drives and flash drivers for + loading U-Boot. + +config SPL_UFS_RAW_U_BOOT_DEVNUM + int "SCSI device number of the UFS device to load U-Boot from" + depends on SPL_UFS_SUPPORT + default 0 + help + UFS devices are usually configured with multiple LUNs, which present + themselves as sequentially numbered SCSI devices. Usually one would + get a default LUN 0 taking up most of the space on the device, with + a number of smaller LUNs following it. This option controls which of + them the SPL will attempt to load U-Boot from. Note that this is the + SCSI device number, which might differ from the UFS LUN if you have + multiple SCSI devices attached and recognized by the SPL. + +config SPL_UFS_RAW_U_BOOT_SECTOR + hex "Address on the UFS to load U-Boot from" + depends on SPL_UFS_SUPPORT + default 0x800 if ARCH_ROCKCHIP + help + Address on the block device to load U-Boot from. + Units: UFS sectors (1 sector = 4096 bytes). + config SPL_WATCHDOG bool "Support watchdog drivers" imply SPL_WDT if !HW_WATCHDOG diff --git a/common/spl/Makefile b/common/spl/Makefile index 4c9482bd309..9c94e8f143e 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_$(PHASE_)OPENSBI) += spl_opensbi.o obj-$(CONFIG_$(PHASE_)USB_STORAGE) += spl_usb.o obj-$(CONFIG_$(PHASE_)FS_FAT) += spl_fat.o obj-$(CONFIG_$(PHASE_)FS_EXT4) += spl_ext.o +obj-$(CONFIG_$(PHASE_)FS_SQUASHFS) += spl_squashfs.o obj-$(CONFIG_$(PHASE_)LOAD_IMX_CONTAINER) += spl_imx_container.o obj-$(CONFIG_$(PHASE_)SATA) += spl_sata.o obj-$(CONFIG_$(PHASE_)NVME) += spl_nvme.o @@ -37,6 +38,7 @@ obj-$(CONFIG_$(PHASE_)DFU) += spl_dfu.o obj-$(CONFIG_$(PHASE_)SPI_LOAD) += spl_spi.o obj-$(CONFIG_$(PHASE_)RAM_SUPPORT) += spl_ram.o obj-$(CONFIG_$(PHASE_)USB_SDP_SUPPORT) += spl_sdp.o +obj-$(CONFIG_$(PHASE_)UFS_SUPPORT) += spl_ufs.o endif obj-$(CONFIG_$(PHASE_)UPL) += spl_upl.o diff --git a/common/spl/spl.c b/common/spl/spl.c index fd915d9564b..8256fa97862 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -954,7 +954,7 @@ ulong spl_relocate_stack_gd(void) } #endif /* Get stack position: use 8-byte alignment for ABI compliance */ - ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16); + ptr -= roundup(sizeof(gd_t), 16); gd->start_addr_sp = ptr; new_gd = (gd_t *)ptr; memcpy(new_gd, (void *)gd, sizeof(gd_t)); diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c index b09f82790c9..7d21bb4d16a 100644 --- a/common/spl/spl_dfu.c +++ b/common/spl/spl_dfu.c @@ -64,7 +64,7 @@ static int dfu_over_pcie(void) hdr.deviceid = CONFIG_SPL_PCI_DFU_DEVICE_ID; hdr.vendorid = CONFIG_SPL_PCI_DFU_VENDOR_ID; hdr.baseclass_code = PCI_BASE_CLASS_MEMORY; - hdr.subclass_code = PCI_CLASS_MEMORY_RAM; + hdr.subclass_code = PCI_CLASS_MEMORY_RAM & 0xff; ret = pci_ep_write_header(dev, fn, &hdr); if (ret) { diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 47cfe4aef58..cc16709dc9b 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -226,6 +226,11 @@ static int __maybe_unused spl_mmc_fs_load(struct spl_image_info *spl_image, if (!err) return 0; } + if (CONFIG_IS_ENABLED(FS_SQUASHFS)) { + err = spl_load_image_sqfs(spl_image, bootdev, blk_dev, part, file); + if (!err) + return 0; + } return err; } @@ -284,13 +289,15 @@ static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, u32 __weak spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#elif defined(CONFIG_SUPPORT_EMMC_BOOT) - return MMCSD_MODE_EMMCBOOT; -#else + if (CONFIG_IS_ENABLED(FS_FAT) || + CONFIG_IS_ENABLED(FS_EXT4) || + CONFIG_IS_ENABLED(FS_SQUASHFS)) + return MMCSD_MODE_FS; + + if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + return MMCSD_MODE_RAW; -#endif } #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index e8e62d5f9fb..3d4b70f7c33 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -124,8 +124,16 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, } err = spl_load(spl_image, bootdev, &load, 0, payload_offs); - if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) - err = spi_nor_remove(flash); + if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) { + int ret = spi_nor_remove(flash); + + if (ret) { + printf("%s: Failed to remove SPI NOR flash: %d\n", + __func__, ret); + if (!err) + err = ret; + } + } return err; } /* Use priorty 1 so that boards can override this */ diff --git a/common/spl/spl_squashfs.c b/common/spl/spl_squashfs.c new file mode 100644 index 00000000000..d3b1c70bfc4 --- /dev/null +++ b/common/spl/spl_squashfs.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Paratronic + * Copyright (C) 2026 Bootlin + * + * Author: Richard Genoud + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, + ulong size, void *buf) +{ + struct legacy_img_hdr *header; + char *filename = load->priv; + loff_t actread; + int ret; + + ret = sqfs_read(filename, buf, file_offset, size, &actread); + if (ret) + return ret; + + if (CONFIG_IS_ENABLED(OS_BOOT)) { + header = (struct legacy_img_hdr *)buf; + if (image_get_magic(header) != FDT_MAGIC) + return size; + } + + return actread; +} + +int spl_load_image_sqfs(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + struct blk_desc *block_dev, int partition, + const char *filename) +{ + int err; + loff_t size = 0; + struct spl_load_info load; + struct disk_partition part_info = {}; + + err = part_get_info(block_dev, partition, &part_info); + if (err) { + printf("spl: no partition table found\n"); + goto end; + } + + err = sqfs_probe(block_dev, &part_info); + if (err) { + printf("spl: sqfs probe err part_name:%s type=%s err=%d\n", + part_info.name, part_info.type, err); + goto end; + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + err = sqfs_size(filename, &size); + if (err) + goto end; + } + + spl_load_init(&load, spl_fit_read, (void *)filename, 1); + + err = spl_load(spl_image, bootdev, &load, size, 0); + +end: + if (err < 0) + printf("%s: error reading image %s, err - %d\n", + __func__, filename, err); + + return err; +} diff --git a/common/spl/spl_ufs.c b/common/spl/spl_ufs.c new file mode 100644 index 00000000000..cef1843f40f --- /dev/null +++ b/common/spl/spl_ufs.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2025 Alexey Charkov + */ + +#include +#include +#include +#include +#include +#include +#include + +static ulong spl_ufs_load_read(struct spl_load_info *load, ulong off, ulong size, void *buf) +{ + struct blk_desc *bd = load->priv; + lbaint_t sector = off >> bd->log2blksz; + lbaint_t count = size >> bd->log2blksz; + + return blk_dread(bd, sector, count, buf) << bd->log2blksz; +} + +static int spl_ufs_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + unsigned long sector = CONFIG_SPL_UFS_RAW_U_BOOT_SECTOR; + int devnum = CONFIG_SPL_UFS_RAW_U_BOOT_DEVNUM; + struct spl_load_info load; + struct blk_desc *bd; + int err; + + /* try to recognize storage devices immediately */ + scsi_scan(false); + bd = blk_get_devnum_by_uclass_id(UCLASS_SCSI, devnum); + if (!bd) + return -ENODEV; + + spl_load_init(&load, spl_ufs_load_read, bd, bd->blksz); + err = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz); + if (err) { + puts("spl_ufs_load_image: ufs block read error\n"); + log_debug("(error=%d)\n", err); + return err; + } + + return 0; +} + +SPL_LOAD_IMAGE_METHOD("UFS", 0, BOOT_DEVICE_UFS, spl_ufs_load_image); diff --git a/common/stdio.c b/common/stdio.c index 3eeb289dd8b..fc965944209 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -18,11 +18,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static struct stdio_dev devs; struct stdio_dev *stdio_devices[] = { NULL, NULL, NULL }; char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" }; diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index dd30e8d30da..243484852c3 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -133,7 +133,7 @@ CONFIG_LOADS_ECHO=y CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/am62dx_evm_a53_defconfig b/configs/am62dx_evm_a53_defconfig index 302f8c5e936..d323a060d55 100644 --- a/configs/am62dx_evm_a53_defconfig +++ b/configs/am62dx_evm_a53_defconfig @@ -6,17 +6,26 @@ CONFIG_SOC_K3_AM62A7=y CONFIG_TARGET_AM62D2_A53_EVM=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62d2-evm" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPL_DMA=y +CONFIG_SPL_DM_SPI=y CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y # CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_DFU_SF=y +CONFIG_MTD=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y diff --git a/configs/am62dx_evm_r5_defconfig b/configs/am62dx_evm_r5_defconfig index 7a3ecee7ec1..90d6650fedf 100644 --- a/configs/am62dx_evm_r5_defconfig +++ b/configs/am62dx_evm_r5_defconfig @@ -5,16 +5,20 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_AM62A7=y CONFIG_TARGET_AM62D2_R5_EVM=y CONFIG_DEFAULT_DEVICE_TREE="k3-am62d2-r5-evm" -# CONFIG_SPL_DMA is not set CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI=y # CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y diff --git a/configs/am69_sk_a72_defconfig b/configs/am69_sk_a72_defconfig index 746b36a34ed..cf2881258e1 100644 --- a/configs/am69_sk_a72_defconfig +++ b/configs/am69_sk_a72_defconfig @@ -9,6 +9,9 @@ CONFIG_CMD_UFS=n CONFIG_UFS=n CONFIG_UFS_CADENCE=n CONFIG_UFS_TI_J721E=n +CONFIG_PCI_ENDPOINT=n +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am69-sk" CONFIG_OF_LIST="ti/k3-am69-sk" diff --git a/configs/am69_sk_r5_defconfig b/configs/am69_sk_r5_defconfig index 2186b9a0490..166f774aade 100644 --- a/configs/am69_sk_r5_defconfig +++ b/configs/am69_sk_r5_defconfig @@ -5,6 +5,12 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J784S4_R5_EVM=y +CONFIG_MULTIPLEXER=n +CONFIG_SPL_MUX_MMIO=n +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n +CONFIG_SPL_PHY=n + CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-sk" CONFIG_SPL_OF_LIST="k3-am69-r5-sk" CONFIG_OF_LIST="k3-am69-r5-sk" diff --git a/configs/am6x_a53_snagfactory.config b/configs/am6x_a53_snagfactory.config new file mode 100644 index 00000000000..ed136407afb --- /dev/null +++ b/configs/am6x_a53_snagfactory.config @@ -0,0 +1,22 @@ +CONFIG_BOOTCOMMAND="fastboot usb 0;" +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC=y +CONFIG_FASTBOOT_OEM_RUN=y +CONFIG_CMD_PART=y +CONFIG_CMD_GPT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x7000000 +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_RANDOM_UUID=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_BOOTDELAY=0 +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc0boot0" +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc0boot1" +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_CMD_MTD=y +CONFIG_CMD_MTDPARTS=y diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 0344089030c..0f4b75c72e1 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y +CONFIG_CMD_NFS=y CONFIG_CMD_SNTP=y CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y @@ -79,8 +80,10 @@ CONFIG_CLK_SCMI=y CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_SCMI_FIRMWARE=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_VERSALPL=y +CONFIG_GPIO_DELAY=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig index 7c1c6cf45e1..a94730cf564 100644 --- a/configs/an7581_evb_defconfig +++ b/configs/an7581_evb_defconfig @@ -68,6 +68,8 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_MDIO=y CONFIG_AIROHA_ETH=y +CONFIG_PCS_AIROHA_AN7581=y +CONFIG_PHYLIB=y CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCONF=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 6d59ccfb15b..6923d27f79a 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set +# CONFIG_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index cd67ed1c46d..3ffebb15375 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set +# CONFIG_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 0a459141373..f62aece626f 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -15,7 +15,6 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" diff --git a/configs/beaglev_fire_defconfig b/configs/beaglev_fire_defconfig new file mode 100644 index 00000000000..9ebb08abbfe --- /dev/null +++ b/configs/beaglev_fire_defconfig @@ -0,0 +1,29 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2800 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-beaglev-fire" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_TARGET_BEAGLEBOARD_BEAGLEVFIRE=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-beaglev-fire.dtb" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_GPIO=y +CONFIG_OF_UPSTREAM=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_MPFS_GPIO=y +CONFIG_MMC_SPI=y +CONFIG_SYSRESET=y diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index 7774f7b2388..305b5a40c0e 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -8,7 +8,6 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 CONFIG_ENV_SECT_SIZE=0x10000 diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 02f7876f2dc..60ceae8f153 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-mickey" CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y @@ -29,7 +29,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-mickey.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 6bfcda1d6a3..c90a9d6159c 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_READ=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 928a713cd1f..5e89311affe 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-jerry" CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y @@ -28,7 +28,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-jerry.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 7a875d42c3f..6e0158fd4a9 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-minnie" CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y @@ -29,7 +29,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-minnie.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index ed1c62330c9..07f318386ba 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_PART=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index dbc8be49ee7..52fb471c97e 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_PART=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index d890a344f52..86f1399c0e3 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-veyron-speedy" CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y @@ -29,7 +29,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-veyron-speedy.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_LOG=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 4eb86fee70b..e042364de9c 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/configs/coreboot64-no-spl_defconfig b/configs/coreboot64-no-spl_defconfig index aadf11e9867..5e71ce83920 100644 --- a/configs/coreboot64-no-spl_defconfig +++ b/configs/coreboot64-no-spl_defconfig @@ -24,7 +24,7 @@ CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 719b2f02c1e..8261c39d87b 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -28,7 +28,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index b49fc80167b..c7520def6dc 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -27,7 +27,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_PCI_INIT_R=y CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 55977e896b1..cfb44a41812 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -32,7 +32,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 5162f70ab9e..d6b773b0f97 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -38,7 +38,7 @@ CONFIG_SPL_I2C=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/dh_imx6.config b/configs/dh_imx6.config index b1eeb8901f4..c9165b28e8b 100644 --- a/configs/dh_imx6.config +++ b/configs/dh_imx6.config @@ -28,7 +28,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTDELAY=3 CONFIG_BZIP2=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_UNZIP=y CONFIG_CMD_WDT=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index bd0e07bba08..31fb4ffa449 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -25,7 +25,7 @@ CONFIG_USE_PREBOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_IDE=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index e7a78b656a0..64e0267af91 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -44,6 +44,6 @@ CONFIG_SYS_MAX_FLASH_SECT=128 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_DM_RTC=y -CONFIG_RTC_DS1338=y +CONFIG_RTC_DS1307=y CONFIG_MCFUART=y CONFIG_WDT=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 137b346e569..cf25d24bf9d 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -42,6 +42,6 @@ CONFIG_SYS_MAX_FLASH_SECT=128 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_DM_RTC=y -CONFIG_RTC_DS1338=y +CONFIG_RTC_DS1307=y CONFIG_MCFUART=y CONFIG_WDT=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288-rk808_defconfig similarity index 95% rename from configs/evb-rk3288_defconfig rename to configs/evb-rk3288-rk808_defconfig index 02347b58c22..2112e475ad3 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288-rk808_defconfig @@ -9,7 +9,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-evb-rk808" CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y @@ -29,7 +29,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-evb-rk808.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_NO_BSS_LIMIT=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index d7b01e67db9..54e3c41f3cc 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index dfa8efabe6b..7a8c176912e 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_BOOTMETH_VBE is not set CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index ab58edb605f..e6fbd7e4865 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -26,7 +26,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_PROMPT="GoFlexHome> " CONFIG_SYS_MAXARGS=32 CONFIG_CMD_NAND=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config index 4634a0972f0..18c7bb536fa 100644 --- a/configs/imx8m_data_modul.config +++ b/configs/imx8m_data_modul.config @@ -149,7 +149,6 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_POWER_DOMAIN=y CONFIG_PROT_TCP_SACK=y -CONFIG_REGMAP=y CONFIG_RGMII=y CONFIG_RTC_M41T62=y CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index 0649d746907..ee55d804980 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2" CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y @@ -78,8 +75,6 @@ CONFIG_CLK_IMX8MP=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -98,12 +93,13 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig index a23e604425d..4a8938d3e43 100644 --- a/configs/imx8mp-libra-fpsc_defconfig +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -9,7 +9,6 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc" CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 @@ -105,8 +104,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -138,15 +135,16 @@ CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 5c3c8a2ca57..d5b01939f2d 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -87,6 +87,7 @@ CONFIG_ETHPRIME="eth1" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config index 62babf2626f..2bae5b1a862 100644 --- a/configs/imx8qxp_capricorn.config +++ b/configs/imx8qxp_capricorn.config @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_REDUNDANT=y CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 +CONFIG_ENV_WRITEABLE_LIST=y CONFIG_DM_GPIO=y CONFIG_AHAB_BOOT=y @@ -73,6 +74,8 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_BIND is not set CONFIG_CMD_WDT=y +CONFIG_CMD_WGET=y +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index ff6cd8e6c98..41025dc1142 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -32,7 +32,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2068 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx91-phycore_defconfig b/configs/imx91-phycore_defconfig new file mode 100644 index 00000000000..b1e13bade84 --- /dev/null +++ b/configs/imx91-phycore_defconfig @@ -0,0 +1,167 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="phycore_imx91_93" +CONFIG_NR_DRAM_BANKS=2 +CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_PHYTEC_EEPROM_BUS=2 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-phyboard-segin" +CONFIG_TARGET_PHYCORE_IMX91=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204E0000 +CONFIG_SPL_TEXT_BASE=0x204A0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20498000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x720000 +CONFIG_CMD_DEKBLOB=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_BOOTDEV is not set +# CONFIG_CMD_BOOTMETH is not set +# CONFIG_CMD_BOOTSTD is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK_IMX93=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000 +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_GPIO_HOG=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_ULP_WATCHDOG=y +# CONFIG_RSA is not set +# CONFIG_SPL_SHA256 is not set +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index ac719372b41..6ae6e405fbf 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x20000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SOURCE_FILE="phycore_imx93" +CONFIG_ENV_SOURCE_FILE="phycore_imx91_93" CONFIG_NR_DRAM_BANKS=2 CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_PHYTEC_EEPROM_BUS=2 @@ -76,6 +76,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_SNTP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig index c35ebc3b492..adcf2125c73 100644 --- a/configs/imx93_frdm_defconfig +++ b/configs/imx93_frdm_defconfig @@ -35,7 +35,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx943_evk_defconfig b/configs/imx943_evk_defconfig index ef4f9a8fcbc..6acb49e47e2 100644 --- a/configs/imx943_evk_defconfig +++ b/configs/imx943_evk_defconfig @@ -107,6 +107,12 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_IMX_MU_MBOX=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_PHYLIB=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y @@ -127,6 +133,9 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_XSPI=y CONFIG_USB=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/imx952_evk_defconfig b/configs/imx952_evk_defconfig new file mode 100644 index 00000000000..a700aea67a1 --- /dev/null +++ b/configs/imx952_evk_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="imx952_evk" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SF_DEFAULT_SPEED=200000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx952-evk" +CONFIG_TARGET_IMX952_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_SPL_OF_LIBFDT_ASSUME_MASK=0x0 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="freescale/imx952-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_CMD_OPTEE=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +# CONFIG_BOOTDEV_ETH is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_RX_ETH_BUFFER=8 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +# CONFIG_SCMI_AGENT_SMCCC is not set +# CONFIG_SCMI_AGENT_OPTEE is not set +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_ADP5585_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_IMX_MU_MBOX=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_FSL_ENETC=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_SDP_LOADADDR=0x90400000 +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/configs/imx95_evk.config b/configs/imx95_evk.config index 3db583cce59..e7832d86fe9 100644 --- a/configs/imx95_evk.config +++ b/configs/imx95_evk.config @@ -92,7 +92,6 @@ CONFIG_ETHPRIME="eth0" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SPL_DM=y -CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y diff --git a/configs/imx_dhsom.config b/configs/imx_dhsom.config index 4a3ddc7e90b..a0d67c8a068 100644 --- a/configs/imx_dhsom.config +++ b/configs/imx_dhsom.config @@ -28,7 +28,6 @@ CONFIG_ENV_SECT_SIZE_AUTO=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_DM_GPIO=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 04ce0b8f0af..5c44ba63ce0 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -32,7 +32,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/configs/j742s2_evm_a72_defconfig b/configs/j742s2_evm_a72_defconfig index e534ce4c2e3..8263ab0bc4a 100644 --- a/configs/j742s2_evm_a72_defconfig +++ b/configs/j742s2_evm_a72_defconfig @@ -5,5 +5,9 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J742S2_A72_EVM=y +CONFIG_PCI_ENDPOINT=n +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n + CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j742s2-evm" CONFIG_SPL_OF_LIST="ti/k3-j742s2-evm" diff --git a/configs/j742s2_evm_r5_defconfig b/configs/j742s2_evm_r5_defconfig index 2be6318df76..036954b4085 100644 --- a/configs/j742s2_evm_r5_defconfig +++ b/configs/j742s2_evm_r5_defconfig @@ -5,5 +5,11 @@ CONFIG_ARCH_K3=y CONFIG_SOC_K3_J784S4=y CONFIG_TARGET_J742S2_R5_EVM=y +CONFIG_SPL_PCI_ENDPOINT=n +CONFIG_SPL_PCI_DFU=n +CONFIG_MULTIPLEXER=n +CONFIG_SPL_MUX_MMIO=n +CONFIG_SPL_PHY=n + CONFIG_DEFAULT_DEVICE_TREE="k3-j742s2-r5-evm" CONFIG_SPL_OF_LIST="k3-j742s2-r5-evm" diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 1d2043aeba0..c374024b0dd 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -46,9 +46,16 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_PCI_ENDPOINT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_PCI_DFU=y +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_SPL_PCI_DFU_BAR_SIZE=0x400000 +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x104c +CONFIG_SPL_PCI_DFU_DEVICE_ID=0xb012 +CONFIG_SPL_PCI_DFU_BOOT_PHASE="tispl.bin" # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 25ab6f17d17..4462e7530e4 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -50,9 +50,16 @@ CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_PCI_ENDPOINT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_PCI_DFU=y +CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x80800000 +CONFIG_SPL_PCI_DFU_BAR_SIZE=0x400000 +CONFIG_SPL_PCI_DFU_VENDOR_ID=0x104c +CONFIG_SPL_PCI_DFU_DEVICE_ID=0xb012 +CONFIG_SPL_PCI_DFU_BOOT_PHASE="tiboot3.bin" # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -120,6 +127,12 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y +CONFIG_MULTIPLEXER=y +CONFIG_SPL_MUX_MMIO=y +CONFIG_PCIE_CDNS_TI_EP=y +CONFIG_SPL_PHY=y +CONFIG_SPL_PHY_CADENCE_TORRENT=y +CONFIG_SPL_PHY_J721E_WIZ=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y diff --git a/configs/kontron-osm-s-mx8mp.config b/configs/kontron-osm-s-mx8mp.config index a8881726e07..786fd3e7a6d 100644 --- a/configs/kontron-osm-s-mx8mp.config +++ b/configs/kontron-osm-s-mx8mp.config @@ -117,7 +117,6 @@ CONFIG_TFTP_TSIZE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/kontron-osm-s-mx93.config b/configs/kontron-osm-s-mx93.config index a6d316de3d8..c2d4de4efa8 100644 --- a/configs/kontron-osm-s-mx93.config +++ b/configs/kontron-osm-s-mx93.config @@ -115,7 +115,6 @@ CONFIG_TFTP_TSIZE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_ADC=y CONFIG_ADC_IMX93=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index e97534ecc0a..4a97c51e88c 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -71,6 +71,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_WDT=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index e6ad27ed1bf..d9d32bf5a50 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -36,7 +36,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_SYS_DEVICE_NULLDEV is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/liontron-h-a133l_defconfig b/configs/liontron-h-a133l_defconfig index 56c5262f267..831d5b56e3a 100644 --- a/configs/liontron-h-a133l_defconfig +++ b/configs/liontron-h-a133l_defconfig @@ -10,9 +10,9 @@ CONFIG_DRAM_SUNXI_PARA0=0xd0a050c CONFIG_DRAM_SUNXI_MR11=0x4 CONFIG_DRAM_SUNXI_MR12=0x72 CONFIG_DRAM_SUNXI_MR14=0x7 -CONFIG_DRAM_SUNXI_TPR1=0x26 -CONFIG_DRAM_SUNXI_TPR2=0x6060606 -CONFIG_DRAM_SUNXI_TPR3=0x84040404 +CONFIG_DRAM_SUNXI_MR22=0x26 +CONFIG_DRAM_SUNXI_TPR0=0x6060606 +CONFIG_DRAM_SUNXI_TPR1=0x84040404 CONFIG_DRAM_SUNXI_TPR6=0x48000000 CONFIG_DRAM_SUNXI_TPR10=0x273333 CONFIG_DRAM_SUNXI_TPR11=0x231d151c diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 660dcffca72..bdad4fb0b01 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 24ddbf783b2..236de528260 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 985d3e2b8f0..19b902c5671 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 2fd6dff8452..de1dff54ae9 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_SPI=y CONFIG_DEFAULT_SPI_BUS=1 CONFIG_CMD_USB=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index f0ec4cb3afc..7a29f924f62 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index c147f3a2b31..11ed69be492 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 8907227448a..5c0020a5ac7 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index c631590df1e..334993ed596 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -62,6 +62,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 4bea39a636f..18e60a09225 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index f897e41e444..04248c67fb3 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index d606a4ff002..55c8fee4f54 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -77,6 +77,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 12b6e2e0e53..9cdf2b6c08e 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 8fa9bb60238..87de073ddc3 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 881fe3dabae..2d863a6c7a6 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 6306d04c43f..e968ce9e1a7 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -46,6 +46,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 098c62db51d..edd49197a5e 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -77,6 +77,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index ce0b190de3c..317f5de92a6 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -74,6 +74,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 09924a5a08b..fa3f8052295 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index ffaecb5c90c..433bd2cad94 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index f666f477727..8db7633d1b7 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 5527659ef78..8a7702a0bfb 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index a6041337800..c68ee9d5d2e 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -76,6 +76,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index d3194ffdbcd..daea2823566 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -76,6 +76,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 97eb7d9dca4..ebe4b02a5db 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index cc53c17f543..19bbb07a81f 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig index 8da7271c7f8..32634a572a7 100644 --- a/configs/ls1028aqds_tfa_lpuart_defconfig +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 3f71a37559b..6d79e47ada1 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -42,6 +42,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 89e452bdb1a..19d0416ef91 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 7384eb490f5..0129ac3ddae 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -54,6 +54,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 7a6a8c3fe2a..515773e82cc 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -55,6 +55,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 6efe356e842..8c47112fbd0 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 1282cb355d3..6043454e782 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index ff59d504dde..7da430ff7fd 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -55,6 +55,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 77f8d6b53d4..1c07e70e663 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 8a8a4e1c8d6..b151cbee22f 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -42,6 +42,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 62c4a6a66ea..28af48d1660 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index dafbe9b3b2b..06ec7e04c4b 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -50,6 +50,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index df472eeb404..dd19b9f8127 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 46390a05adb..7116b4101ba 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -50,6 +50,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 77f5a7ac708..8fe6a398fa7 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 9141340b163..5f33643c64f 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 8c623d6a8e5..0cee45b8f9f 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -66,6 +66,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 51475f2733f..01f5aff7efc 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 3fd1de96789..7f339da1bb3 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index f053044fa56..c42cb2b9ddc 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -51,6 +51,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 65a55b40e01..68c89e23eb6 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -31,7 +31,7 @@ CONFIG_DEFAULT_FDT_FILE="kirkwood-lschlv2.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index c537d6d0ca6..c3514934021 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -32,7 +32,7 @@ CONFIG_DEFAULT_FDT_FILE="kirkwood-lsxhl.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 321ed71993b..39d4469c2b7 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 465f07ee7f8..4f20c9bd105 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -51,6 +51,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 478a01b566c..ab69287f2ca 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 8fd18825569..eebc1426621 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index cf65897af89..0da49cb7564 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -53,6 +53,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 46b6085a52f..eeb24616fe8 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 41e0262f3ca..3330f6e2fd9 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -53,6 +53,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 7abfdbafbdf..a409f5becd7 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -54,6 +54,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_OPTEE_RPMB=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index a4d24c11fe8..4cbd4b97172 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/mt8365_evk_defconfig b/configs/mt8365_evk_defconfig index f1e7d7fc58a..9b403cd7aab 100644 --- a/configs/mt8365_evk_defconfig +++ b/configs/mt8365_evk_defconfig @@ -15,12 +15,18 @@ CONFIG_CMD_CLK=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_OF_UPSTREAM=y CONFIG_CLK=y CONFIG_MMC_MTK=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_PINCTRL_MT8365=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MTK_PWRAP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MT6357=y CONFIG_BAUDRATE=921600 CONFIG_DM_SERIAL=y CONFIG_MTK_SERIAL=y diff --git a/configs/mt8370_evk_defconfig b/configs/mt8370_evk_defconfig new file mode 100644 index 00000000000..48d3f64a42e --- /dev/null +++ b/configs/mt8370_evk_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=13000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x4c000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8370-genio-510-evk" +CONFIG_TARGET_MT8188=y +CONFIG_MTK_MEM_MAP_DDR_SIZE=0x100000000 +CONFIG_SYS_LOAD_ADDR=0x4c000000 +CONFIG_IDENT_STRING="mt8370-evk" +# CONFIG_BOARD_INIT is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_OF_UPSTREAM=y +CONFIG_CLK=y +CONFIG_MMC_MTK=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT8188=y +CONFIG_BAUDRATE=921600 +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_WDT=y +CONFIG_WDT_MTK=y +# CONFIG_RANDOM_UUID is not set diff --git a/configs/mt8390_evk_defconfig b/configs/mt8390_evk_defconfig index 9bc1d922587..06437be625e 100644 --- a/configs/mt8390_evk_defconfig +++ b/configs/mt8390_evk_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8390-genio-700-evk" CONFIG_TARGET_MT8188=y CONFIG_SYS_LOAD_ADDR=0x4c000000 CONFIG_IDENT_STRING="mt8390-evk" +# CONFIG_BOARD_INIT is not set CONFIG_CMD_CLK=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/mt8395_evk_defconfig b/configs/mt8395_evk_defconfig new file mode 100644 index 00000000000..2edf3cb3e35 --- /dev/null +++ b/configs/mt8395_evk_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=13000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x4c000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mediatek/mt8395-genio-1200-evk" +CONFIG_TARGET_MT8195=y +CONFIG_SYS_LOAD_ADDR=0x60000000 +CONFIG_IDENT_STRING=" mt8395-evk" +# CONFIG_BOARD_INIT is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_OF_UPSTREAM=y +CONFIG_CLK=y +CONFIG_MMC_MTK=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT8195=y +CONFIG_BAUDRATE=921600 +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_WDT=y +CONFIG_WDT_MTK=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index f3222e89b91..af3bf1a04fc 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 1da18f31344..3df1c8d007d 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x40000 CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino" CONFIG_TARGET_MX23_OLINUXINO=y CONFIG_SPL_SERIAL=y @@ -38,14 +39,9 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y CONFIG_MXS_GPIO=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=778 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -CONFIG_LED_STATUS_CMD=y +CONFIG_LED=y +CONFIG_LED_BOOT=y +CONFIG_LED_GPIO=y CONFIG_MMC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_DM_SERIAL=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 6a7c8d414e1..b0ae9316271 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -37,7 +37,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y # CONFIG_CMD_VIDCONSOLE is not set diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index da07b38b4bc..816b9a50358 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BMP=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index f126c6e1e79..06474cb94e8 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 134475d24d8..b340d9c9f95 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 36c342bcfe2..983b8aeb407 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 28961f5a13f..c88d18dbf9b 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 9db0251a8a0..8f4a92e4a5f 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/nanopi-zero2-rk3528_defconfig b/configs/nanopi-zero2-rk3528_defconfig new file mode 100644 index 00000000000..2e54c0ff20a --- /dev/null +++ b/configs/nanopi-zero2-rk3528_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-nanopi-zero2" +CONFIG_ROCKCHIP_RK3528=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFF9F0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-nanopi-zero2.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 0b65a3f99cc..a24df5f478d 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index cee6449babc..2860c166fb6 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 6ba7eb51c40..3eda61c0f34 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index ad9f3361baa..16ff0313a8c 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_DHCP=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 73e3616acbb..85cd5c96087 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -33,7 +33,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 CONFIG_CMD_I2C=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index a3126140687..4d18ec25211 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -34,7 +34,7 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index f9018f12aac..59942f20eca 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -34,7 +34,7 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 4fd29ef8564..2da31a26d5d 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -45,7 +45,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y # CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 3a6c996a1df..ceae9b06360 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -27,7 +27,7 @@ CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_PROMPT="NSA310s> " CONFIG_SYS_MAXARGS=32 CONFIG_CMD_NAND=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MTDPARTS=y diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig index 284a74d08d8..418cc4d51da 100644 --- a/configs/nsa325_defconfig +++ b/configs/nsa325_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_DNS=y CONFIG_CMD_SNTP=y diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig index 06fe9f78591..42f5f05cccd 100644 --- a/configs/octeon_nic23_defconfig +++ b/configs/octeon_nic23_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig index eaa54a42557..e8fc4703983 100644 --- a/configs/odroid-hc4_defconfig +++ b/configs/odroid-hc4_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 2fcf7db9e5c..51d9737afb3 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -10,7 +10,6 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk" CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 @@ -113,8 +112,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -144,15 +141,16 @@ CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index ee9cc2bd822..a374f90982e 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -26,7 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_LTO=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-phycore-rdk.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -48,7 +48,6 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index afed0bfafc6..5ea352a6370 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -76,6 +76,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/phycore_am68x_r5_defconfig b/configs/phycore_am68x_r5_defconfig index a503bd27441..f0bf98bf44b 100644 --- a/configs/phycore_am68x_r5_defconfig +++ b/configs/phycore_am68x_r5_defconfig @@ -105,7 +105,9 @@ CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y +CONFIG_ESM_K3=y CONFIG_K3_AVS0=y +CONFIG_ESM_PMIC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y @@ -139,6 +141,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_TPS65941=y CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_TPS6287X=y CONFIG_DM_REGULATOR_TPS65941=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_RESET_TI_SCI=y diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index 8a9916c7978..ed7dbc1852b 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -2,20 +2,17 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2" CONFIG_DRAM_CLK=552 -CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_PINEPHONE_DT_SELECTION=y +CONFIG_SPL_SUNXI_LED_STATUS=y +CONFIG_SPL_SUNXI_LED_STATUS_BIT=114 +CONFIG_SPL_SUNXI_LED_STATUS_STATE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CMD_PSTORE=y CONFIG_CMD_PSTORE_MEM_ADDR=0x61000000 CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" CONFIG_SYS_I2C_MVTWSI=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=114 -CONFIG_LED_STATUS_STATE=2 diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index faeaf07df80..711e128d38e 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_DNS=y CONFIG_CMD_SNTP=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 95c1097bc93..52d38f4108c 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-popmetal" CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y @@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-popmetal.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index fe5880de1fd..baad5f09455 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -147,3 +147,4 @@ CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y CONFIG_WDT=y CONFIG_WDT_QCOM=y +CONFIG_FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH=y diff --git a/configs/qnap-ts433-rk3568_defconfig b/configs/qnap-ts433-rk3568_defconfig index e2923233980..e36f7b8037a 100644 --- a/configs/qnap-ts433-rk3568_defconfig +++ b/configs/qnap-ts433-rk3568_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y diff --git a/configs/r8a78000_ironhide_defconfig b/configs/r8a78000_ironhide_defconfig index 180704e75af..64e2c278a7e 100644 --- a/configs/r8a78000_ironhide_defconfig +++ b/configs/r8a78000_ironhide_defconfig @@ -29,6 +29,7 @@ CONFIG_FIRMWARE=y CONFIG_NR_DRAM_BANKS=16 CONFIG_POWER_DOMAIN=y CONFIG_RCAR_MFIS_MBOX=y +CONFIG_SCMI_FIRMWARE=y CONFIG_RESET_SCMI=y CONFIG_SCMI_AGENT_MAILBOX=y CONFIG_SCMI_FIRMWARE=y diff --git a/configs/renesas_rcar64.config b/configs/renesas_rcar64.config index c2cb88dc157..da4b262fc6a 100644 --- a/configs/renesas_rcar64.config +++ b/configs/renesas_rcar64.config @@ -6,7 +6,6 @@ CONFIG_CMD_TEMPERATURE=y CONFIG_DM_THERMAL=y CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_RCAR_GEN3_THERMAL=y -CONFIG_REGMAP=y CONFIG_REMAKE_ELF=y CONFIG_RENESAS_RPC_SPI=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig index 2748fb488c2..f83d3f6d6c9 100644 --- a/configs/rock-5c-rk3588s_defconfig +++ b/configs/rock-5c-rk3588s_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 0a88037cefd..242aa89bcce 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock-pi-n8" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-rock-pi-n8" CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 35f449ab567..025b55e2171 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-rock2-square" CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y @@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-rock2-square.dtb" CONFIG_SILENT_CONSOLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 24b81f794c3..6a42aeadb61 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_POWEROFF=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 280f9c9cfe7..b681b91c3f9 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -24,6 +24,7 @@ CONFIG_FIT=y CONFIG_FIT_CIPHER=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTMETH_ANDROID=y +CONFIG_BOOTMETH_RAUC=y CONFIG_UPL=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_MEASURED_BOOT=y @@ -208,6 +209,7 @@ CONFIG_SANDBOX_DMA=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_SCMI_FIRMWARE=y CONFIG_FPGA_ALTERA=y CONFIG_FPGA_STRATIX_II=y CONFIG_FPGA_STRATIX_V=y diff --git a/configs/sc573-ezkit_defconfig b/configs/sc573-ezkit_defconfig index 1d2112c3f52..fc4ce13cc70 100644 --- a/configs/sc573-ezkit_defconfig +++ b/configs/sc573-ezkit_defconfig @@ -31,8 +31,10 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -42,6 +44,7 @@ CONFIG_CMD_DNS=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sc584-ezkit_defconfig b/configs/sc584-ezkit_defconfig index b7116bb5c8f..a8c6b9f1224 100644 --- a/configs/sc584-ezkit_defconfig +++ b/configs/sc584-ezkit_defconfig @@ -37,7 +37,9 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -47,6 +49,7 @@ CONFIG_CMD_DNS=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sc589-ezkit_defconfig b/configs/sc589-ezkit_defconfig index 74305765ed5..9cd204e40ab 100644 --- a/configs/sc589-ezkit_defconfig +++ b/configs/sc589-ezkit_defconfig @@ -40,8 +40,10 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -51,6 +53,7 @@ CONFIG_CMD_DNS=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sc589-mini_defconfig b/configs/sc589-mini_defconfig index 1141237d58b..0908ab1708b 100644 --- a/configs/sc589-mini_defconfig +++ b/configs/sc589-mini_defconfig @@ -37,8 +37,10 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -48,6 +50,7 @@ CONFIG_CMD_DNS=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sc594-som-ezkit-spl_defconfig b/configs/sc594-som-ezkit-spl_defconfig index a9f06d603f8..c62097a2ac9 100644 --- a/configs/sc594-som-ezkit-spl_defconfig +++ b/configs/sc594-som-ezkit-spl_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MTD=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -33,6 +35,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_EMBED=y diff --git a/configs/sc594-som-ezlite-spl_defconfig b/configs/sc594-som-ezlite-spl_defconfig index 58392dc0ac5..39481351102 100644 --- a/configs/sc594-som-ezlite-spl_defconfig +++ b/configs/sc594-som-ezlite-spl_defconfig @@ -29,6 +29,8 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MTD=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -37,6 +39,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/sc598-som-ezlite-spl_defconfig b/configs/sc598-som-ezlite-spl_defconfig index 739a774a918..34dbedf12b4 100644 --- a/configs/sc598-som-ezlite-spl_defconfig +++ b/configs/sc598-som-ezlite-spl_defconfig @@ -43,7 +43,9 @@ CONFIG_CYCLIC_MAX_CPU_TIME_US=1000 CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y @@ -55,6 +57,7 @@ CONFIG_CMD_DNS=y CONFIG_CMD_MII=y # CONFIG_CMD_MDIO is not set CONFIG_CMD_PING=y +CONFIG_CMD_WGET=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_EMBED=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index e26f8c0a961..8efe405d98a 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -31,7 +31,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_XIMG is not set CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 59e58fcb6dd..e89d391b3d2 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" +CONFIG_DEFAULT_DEVICE_TREE="sifive/hifive-unleashed-a00" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe70 diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 25c07d1e1ca..9e01a3e4608 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" +CONFIG_DEFAULT_DEVICE_TREE="sifive/hifive-unmatched-a00" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe60 diff --git a/configs/socfpga_ac501soc_defconfig b/configs/socfpga_ac501soc_defconfig new file mode 100644 index 00000000000..3d584a6a8a9 --- /dev/null +++ b/configs/socfpga_ac501soc_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_ac501soc" +CONFIG_DM_RESET=y +CONFIG_SPL_STACK=0x0 +CONFIG_SPL_TEXT_BASE=0xFFFF0000 +CONFIG_TARGET_SOCFPGA_CORECOURSE_AC501SOC=y +CONFIG_SPL_FS_FAT=y +# CONFIG_SPL_SPI is not set +CONFIG_TIMESTAMP=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run fatscript;bridge enable; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_ac501soc.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="corecourse" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_TOOLS_MKEFICAPSULE is not set +CONFIG_CMD_C5_PL330_DMA=y +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/socfpga_ac550soc_defconfig b/configs/socfpga_ac550soc_defconfig new file mode 100644 index 00000000000..143f5d0a043 --- /dev/null +++ b/configs/socfpga_ac550soc_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_ac550soc" +CONFIG_DM_RESET=y +CONFIG_SPL_STACK=0x0 +CONFIG_SPL_TEXT_BASE=0xFFFF0000 +CONFIG_TARGET_SOCFPGA_CORECOURSE_AC550SOC=y +CONFIG_SPL_FS_FAT=y +# CONFIG_SPL_SPI is not set +CONFIG_TIMESTAMP=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run fatscript;bridge enable; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_ac550soc.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="corecourse" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_TOOLS_MKEFICAPSULE is not set +CONFIG_CMD_C5_PL330_DMA=y +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 5fbc49b2307..8a3f9563af2 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -87,6 +87,8 @@ CONFIG_DW_I3C_MASTER=y CONFIG_MISC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y diff --git a/configs/socfpga_agilex5_emmc_defconfig b/configs/socfpga_agilex5_emmc_defconfig index 9254ab92e0c..47d345be97c 100644 --- a/configs/socfpga_agilex5_emmc_defconfig +++ b/configs/socfpga_agilex5_emmc_defconfig @@ -4,3 +4,5 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc" # CONFIG_SPL_DM_REGULATOR_GPIO is not set # CONFIG_DM_REGULATOR_GPIO is not set # CONFIG_SPL_DWAPB_GPIO is not set +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y diff --git a/configs/socfpga_agilex7m_defconfig b/configs/socfpga_agilex7m_defconfig index 0a8c58234b9..d3ecca436ef 100644 --- a/configs/socfpga_agilex7m_defconfig +++ b/configs/socfpga_agilex7m_defconfig @@ -1,7 +1,6 @@ #include CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" # CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK is not set # CONFIG_IDENT_STRING is not set CONFIG_SPL_BSS_START_ADDR=0x1ff00000 diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index eb99392f0ea..b2c7b30d546 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -58,7 +58,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_SMC=y CONFIG_CMD_UBI=y CONFIG_OF_UPSTREAM=y -CONFIG_OF_LIST="" +CONFIG_OF_LIST="intel/socfpga_agilex_socdk intel/socfpga_agilex_socdk_nand" CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_UBI=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 1ef20ba97a8..bb8f1eb7264 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -4,7 +4,6 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index a4798e2f953..78fe42e107c 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -4,7 +4,6 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 63ea467baef..206343885d9 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -4,7 +4,6 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x200000 CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index a754134a313..74a24dfd074 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -80,7 +80,7 @@ CONFIG_WGET_HTTPS=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y CONFIG_DEVICE_TREE_INCLUDES="starfive-visionfive2-u-boot.dtsi" -CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-milkv-marscm-emmc starfive/jh7110-milkv-marscm-lite starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" +CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-milkv-marscm-emmc starfive/jh7110-milkv-marscm-lite starfive/jh7110-orangepi-rv starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b starfive/jh7110-starfive-visionfive-2-lite" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 6bd13944112..620a6da2efe 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -70,6 +70,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y diff --git a/configs/stm32mp15-odyssey_defconfig b/configs/stm32mp15-odyssey_defconfig index 868ba1915f7..5d1c01c99fb 100644 --- a/configs/stm32mp15-odyssey_defconfig +++ b/configs/stm32mp15-odyssey_defconfig @@ -86,6 +86,7 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index af2efc7bceb..c26602b63b6 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -88,6 +88,7 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 226d8335784..d7501612a79 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -89,6 +89,7 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y diff --git a/configs/stm32mp21_defconfig b/configs/stm32mp21_defconfig index 8ad31292579..6a74a435f8d 100644 --- a/configs/stm32mp21_defconfig +++ b/configs/stm32mp21_defconfig @@ -51,6 +51,7 @@ CONFIG_NO_NET=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y diff --git a/configs/stm32mp23_defconfig b/configs/stm32mp23_defconfig index 49f47becba6..ed6fdd9662e 100644 --- a/configs/stm32mp23_defconfig +++ b/configs/stm32mp23_defconfig @@ -51,6 +51,7 @@ CONFIG_NO_NET=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 99b22a68fda..42335aafeaf 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -58,6 +58,7 @@ CONFIG_NO_NET=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 26c00ef594d..27d4ef1121e 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_MTD=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 524a8901454..2779ad21b94 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds" CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index ef7d5ca3e2c..5236aff54da 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig index df063bf2ab2..8432e58e6d3 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -75,10 +75,6 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_SPL_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_SPL_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_ES_SUPPORT=y -CONFIG_SPL_MMC_HS400_ES_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index afbb394228f..2e701a5ff72 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 876086573d3..816903c8430 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index 42ec5957510..3b7eea55f77 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -9,6 +9,7 @@ CONFIG_EFI_LOADER=n CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_TIMESTAMP=y CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTD_FULL=n CONFIG_BOOTMETH_CROS=n CONFIG_BOOTMETH_VBE=n diff --git a/configs/toradex-smarc-imx95_defconfig b/configs/toradex-smarc-imx95_defconfig index 77b355c12d6..61abeff1afb 100644 --- a/configs/toradex-smarc-imx95_defconfig +++ b/configs/toradex-smarc-imx95_defconfig @@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx95-toradex-smarc-dev" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx95-toradex-smarc-dev" CONFIG_TARGET_TORADEX_SMARC_IMX95=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_MONITOR_LEN=524288 @@ -74,6 +74,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -122,6 +123,9 @@ CONFIG_FASTBOOT_UUU_SUPPORT=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_SPL_FIRMWARE=y # CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_SM_CPU=y +CONFIG_IMX_SM_LMM=y +CONFIG_GPIO_HOG=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_SPL_DM_PCA953X=y @@ -152,6 +156,7 @@ CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_IMX=y CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index 999d9088bf8..18caf12686a 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 7ecab30b624..ef848c13427 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index de39e19ec6d..c1f5c1177fa 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -70,7 +70,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index db0d9e2c789..a17f4b0a0b0 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -31,7 +31,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set -CONFIG_CMD_SATA=y +CONFIG_SATA=y # CONFIG_CMD_SCSI is not set CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 99749c50194..455a601b07d 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-verdin-wifi-dev" CONFIG_TARGET_VERDIN_IMX8MP=y @@ -119,8 +115,6 @@ CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_I2C_EEPROM=y @@ -152,14 +146,15 @@ CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 7ac70edc2ea..5cb2f328bb9 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -22,7 +22,7 @@ CONFIG_SYS_PROMPT="VExpress64# " CONFIG_CMD_MEMTEST=y CONFIG_CMD_ARMFLASH=y CONFIG_CMD_PCI=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_CACHE=y CONFIG_CMD_UBI=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index c9de6f8ad26..1d7e2265360 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -11,7 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-vyasa" CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y @@ -26,7 +26,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-vyasa.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_NO_BSS_LIMIT=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 06f8f1ec4d2..e29f0c51d7e 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -42,7 +42,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_SATA=y +CONFIG_SATA=y # CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_BMP=y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 42dc5fb282a..4ff3bd6b687 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_XILINX_MBV=y # CONFIG_RISCV_ISA_F is not set # CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y +# CONFIG_EFI_LOADER is not set CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 323b5606566..3410b874a04 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -46,6 +46,7 @@ CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y +CONFIG_CMD_NFS=y CONFIG_CMD_SNTP=y CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 652121e27a0..d5d60d7f87d 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -52,6 +52,7 @@ CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y +CONFIG_CMD_NFS=y CONFIG_CMD_SNTP=y CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y @@ -86,6 +87,7 @@ CONFIG_ZYNQMP_FIRMWARE=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_VERSALPL=y +CONFIG_GPIO_DELAY=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 8ad05e37189..72a4668b448 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -78,6 +78,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_POWEROFF=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_SDRAM=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y @@ -136,6 +137,7 @@ CONFIG_XILINX_DPDMA=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y +CONFIG_GPIO_DELAY=y CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y CONFIG_DM_PCA953X=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index bb79ddf989e..1433b63979a 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -79,10 +79,12 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_PCI=y CONFIG_CMD_POWEROFF=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_SDRAM=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_NFS=y CONFIG_CMD_SNTP=y CONFIG_WGET_HTTPS=y CONFIG_CMD_BMP=y diff --git a/disk/Kconfig b/disk/Kconfig index a58717bda30..937ae1da61d 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -60,9 +60,9 @@ config TEGRA_PARTITION If unsure, say N. config DOS_PARTITION - bool "Enable MS Dos partition table" + bool "Enable Master Boot Record (MBR) partition table" default y if BOOT_DEFAULTS - default y if x86 || CMD_FAT || USB_STORAGE + default y if X86 || CMD_FAT || USB_STORAGE select PARTITIONS help traditional on the Intel architecture, USB sticks, etc. diff --git a/disk/part_dos.c b/disk/part_dos.c index 18dd35c9b98..4e1d01b2f21 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -19,7 +19,7 @@ #include #include #include -#include "part_dos.h" +#include #include #define DOS_PART_DEFAULT_SECTOR 512 @@ -49,8 +49,8 @@ static int get_bootable(dos_partition_t *p) static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector, int part_num, unsigned int disksig) { - lbaint_t lba_start = ext_part_sector + get_unaligned_le32(p->start4); - lbaint_t lba_size = get_unaligned_le32(p->size4); + lbaint_t lba_start = ext_part_sector + get_unaligned_le32(&p->start_sect); + lbaint_t lba_size = get_unaligned_le32(&p->nr_sects); printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength "u\t%08x-%02x\t%02x%s%s\n", @@ -185,7 +185,7 @@ static void print_partition_extended(struct blk_desc *desc, for (i = 0; i < 4; i++, pt++) { if (is_extended (pt->sys_ind)) { lbaint_t lba_start - = get_unaligned_le32 (pt->start4) + relative; + = get_unaligned_le32 (&pt->start_sect) + relative; print_partition_extended(desc, lba_start, !ext_part_sector ? lba_start : @@ -196,12 +196,26 @@ static void print_partition_extended(struct blk_desc *desc, return; } -/* Print a partition that is relative to its Extended partition table +/** + * part_get_info_extended() - get partition info for a DOS partition + * + * @desc: Block device descriptor + * @ext_part_sector: Partition table sector + * @relative: Relative offset for the partition + * @part_num: Current partition number + * @which_part: Target partition number + * @info: Returns partition information (optional) + * @mbr: Returns MBR partition entry (optional) + * @disksig: Disk signature + * + * Return: 0 on success, negative on error */ static int part_get_info_extended(struct blk_desc *desc, lbaint_t ext_part_sector, lbaint_t relative, int part_num, int which_part, - struct disk_partition *info, uint disksig) + struct disk_partition *info, + dos_partition_t *mbr, + uint disksig) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz); struct disk_partition wdinfo = { 0 }; @@ -232,9 +246,11 @@ static int part_get_info_extended(struct blk_desc *desc, if (CONFIG_IS_ENABLED(PARTITION_UUIDS) && !ext_part_sector) disksig = get_unaligned_le32(&buffer[DOS_PART_DISKSIG_OFFSET]); - ret = part_get_info_whole_disk(desc, &wdinfo); - if (ret) - return ret; + if (info) { + ret = part_get_info_whole_disk(desc, &wdinfo); + if (ret) + return ret; + } /* Print all primary/logical partitions */ pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); @@ -247,25 +263,29 @@ static int part_get_info_extended(struct blk_desc *desc, (pt->sys_ind != 0) && (part_num == which_part) && (ext_part_sector == 0 || is_extended(pt->sys_ind) == 0)) { - if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) - info->blksz = wdinfo.blksz; - else - info->blksz = DOS_PART_DEFAULT_SECTOR; - info->start = (lbaint_t)(ext_part_sector + - get_unaligned_le32(pt->start4)); - info->size = (lbaint_t)get_unaligned_le32(pt->size4); - part_set_generic_name(desc, part_num, - (char *)info->name); - /* sprintf(info->type, "%d, pt->sys_ind); */ - strcpy((char *)info->type, "U-Boot"); - info->bootable = get_bootable(pt); - if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { - char str[12]; + if (info) { + if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) + info->blksz = wdinfo.blksz; + else + info->blksz = DOS_PART_DEFAULT_SECTOR; + info->start = (lbaint_t)(ext_part_sector + + get_unaligned_le32(&pt->start_sect)); + info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); + part_set_generic_name(desc, part_num, + (char *)info->name); + /* sprintf(info->type, "%d, pt->sys_ind); */ + strcpy((char *)info->type, "U-Boot"); + info->bootable = get_bootable(pt); + if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { + char str[12]; - sprintf(str, "%08x-%02x", disksig, part_num); - disk_partition_set_uuid(info, str); + sprintf(str, "%08x-%02x", disksig, part_num); + disk_partition_set_uuid(info, str); + } + info->sys_ind = pt->sys_ind; } - info->sys_ind = pt->sys_ind; + if (mbr) + memcpy(mbr, pt, sizeof(*mbr)); return 0; } @@ -281,11 +301,12 @@ static int part_get_info_extended(struct blk_desc *desc, for (i = 0; i < 4; i++, pt++) { if (is_extended (pt->sys_ind)) { lbaint_t lba_start - = get_unaligned_le32 (pt->start4) + relative; + = get_unaligned_le32 (&pt->start_sect) + relative; return part_get_info_extended(desc, lba_start, ext_part_sector == 0 ? lba_start : relative, - part_num, which_part, info, disksig); + part_num, which_part, info, + mbr, disksig); } } @@ -317,7 +338,13 @@ static void __maybe_unused part_print_dos(struct blk_desc *desc) static int __maybe_unused part_get_info_dos(struct blk_desc *desc, int part, struct disk_partition *info) { - return part_get_info_extended(desc, 0, 0, 1, part, info, 0); + return part_get_info_extended(desc, 0, 0, 1, part, info, NULL, 0); +} + +int __maybe_unused part_get_mbr(struct blk_desc *desc, int part, + dos_partition_t *mbr) +{ + return part_get_info_extended(desc, 0, 0, 1, part, NULL, mbr, 0); } int is_valid_dos_buf(void *buf) @@ -356,8 +383,8 @@ static void mbr_fill_pt_entry(dos_partition_t *pt, lbaint_t start, pt->sys_ind = sys_ind; lba_to_chs(start, &pt->cyl, &pt->head, &pt->sector); lba_to_chs(start + size - 1, &pt->end_cyl, &pt->end_head, &pt->end_sector); - put_unaligned_le32(relative, &pt->start4); - put_unaligned_le32(size, &pt->size4); + put_unaligned_le32(relative, &pt->start_sect); + put_unaligned_le32(size, &pt->nr_sects); } int write_mbr_partitions(struct blk_desc *dev, diff --git a/disk/part_efi.c b/disk/part_efi.c index fb1ed534f86..d8b17ec2e91 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -51,7 +51,7 @@ static inline u32 efi_crc32(const void *buf, u32 len) * Private function prototypes */ -static int pmbr_part_valid(struct partition *part); +static int pmbr_part_valid(dos_partition_t *part); static int is_pmbr_valid(legacy_mbr * mbr); static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head, gpt_entry **pgpt_pte); @@ -990,7 +990,7 @@ int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf) * * Returns: 1 if EFI GPT partition type is found. */ -static int pmbr_part_valid(struct partition *part) +static int pmbr_part_valid(dos_partition_t *part) { if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && get_unaligned_le32(&part->start_sect) == 1UL) { diff --git a/doc/api/led.rst b/doc/api/led.rst index 9ae3f5fe252..fe1904aea0d 100644 --- a/doc/api/led.rst +++ b/doc/api/led.rst @@ -8,66 +8,3 @@ LED .. kernel-doc:: include/led.h :internal: - -Legacy LED -========== - -Please use the new LED API as defined above. This section is only for reference -for currently supported devices and to aid for migration to the new API. - -Status LED ----------- - -This README describes the status LED API. - -The API is defined by the include file include/status_led.h - -The first step is to enable CONFIG_LED_STATUS in menuconfig:: - - > Device Drivers > LED Support. - -If the LED support is only for specific board, enable -CONFIG_LED_STATUS_BOARD_SPECIFIC in the menuconfig. - -Status LEDS 0 to 5 are enabled by the following configurations at menuconfig: -CONFIG_STATUS_LED0, CONFIG_STATUS_LED1, ... CONFIG_STATUS_LED5 - -The following should be configured for each of the enabled LEDs: - -- CONFIG_STATUS_LED_BIT -- CONFIG_STATUS_LED_STATE -- CONFIG_STATUS_LED_FREQ - -Where is an integer 1 through 5 (empty for 0). - -CONFIG_STATUS_LED_BIT is passed into the __led_* functions to identify which LED -is being acted on. As such, the value choose must be unique with respect to -the other CONFIG_STATUS_LED_BIT's. Mapping the value to a physical LED is the -reponsiblity of the __led_* function. - -CONFIG_STATUS_LED_STATE is the initial state of the LED. It should be set to one -of these values: CONFIG_LED_STATUS_OFF or CONFIG_LED_STATUS_ON. - -CONFIG_STATUS_LED_FREQ determines the LED blink frequency. -Values range from 2 to 10. - -Some other LED macros -~~~~~~~~~~~~~~~~~~~~~ - -CONFIG_STATUS_LED_BOOT is the LED to light when the board is booting. -This must be a valid LED number (0-5). - -General LED functions -~~~~~~~~~~~~~~~~~~~~~ -The following functions should be defined: - -__led_init is called once to initialize the LED to CONFIG_STATUS_LED_STATE. -One time start up code should be placed here. - -__led_set is called to change the state of the LED. - -__led_toggle is called to toggle the current state of the LED. - -TBD : Describe older board dependent macros similar to what is done for - -TBD : Describe general support via asm/status_led.h diff --git a/doc/board/acer/picasso.rst b/doc/board/acer/picasso.rst index b1d360defd8..47c6f7f00c5 100644 --- a/doc/board/acer/picasso.rst +++ b/doc/board/acer/picasso.rst @@ -5,7 +5,8 @@ U-Boot for the Acer Iconia Tab A500 ``DISCLAMER!`` Moving your Acer Iconia Tab A500 to use U-Boot assumes replacement of the vendor Acer bootloader. Vendor Android firmwares will no -longer be able to run on the device. This replacement IS reversible. +longer be able to run on the device. This replacement IS reversible if you have +backups. Quick Start ----------- @@ -13,6 +14,7 @@ Quick Start - Build U-Boot - Process U-Boot - Flashing U-Boot into the eMMC +- Flashing U-Boot into the eMMC with NvFlash - Boot - Self Upgrading @@ -36,61 +38,45 @@ in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +to recover the device in case of a failed update. You need to know your device +individual SBK to continue. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev a500 + $ ./re-crypt.py --dev a500 --sbk --split -The script will produce a ``repart-block.bin`` ready to flash. +where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by pre-loading vendor bootloader into RAM with the nvflash. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ nvflash --setbct --bct picasso.bct --configfile flash.cfg --bl bootloader.bin - --sbk 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX --sync # replace with your SBK - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin - -When flashing is done, reboot the device. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered by holding ``power`` and ``volume up`` buttons on +turned off tablet connected to the host PC. Host PC should detect APX USB +device in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./utils/nvflash_t20 --setbct --bct ./bct/picasso.bct --configfile ./utils/flash.cfg + --bl u-boot-dtb-tegra.bin --sbk --sync While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -104,6 +90,37 @@ After, on host PC, do: Device will reboot. +Flashing U-Boot into the eMMC with NvFlash +------------------------------------------ + +``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! + +This method is discouraged and is used only if fastboot commands from previous +chapter failed with ``Writing '0.1' FAILED (remote: 'too large for partition')`` +error. This error means that your tablet has 512 Kb boot0/boot1 partitons which +is too small to contain U-Boot image as the minimum boot partition size must +me 1 MB. This situation can be workarounded but self-update will not work and +flashing to eMMC will wipe U-Boot. This should not be a big issue since installing +OS on microSD is a preferred method anyway. + +This method involves use of Nv3p. Nv3p is a custom Nvidia protocol used to +recover bricked devices. Devices can enter it by pre-loading vendor bootloader +into RAM with the nvflash. + +With Nv3p, ``repart-block.bin`` is used (produced by re-crypt without ``--split`` +key). It contains BCT and a bootloader in encrypted state in form, which can just +be written RAW at the start of eMMC. Place your ``repart-block.bin`` and vendor +bootloader with name ``bootloader.bin`` into fusee-tools folder and run: + +.. code-block:: bash + + $ ./utils/nvflash_t20 --setbct --bct ./bct/picasso.bct --configfile ./utils/flash.cfg + --bl ./bootloader.bin --sbk --sync + $ ./utils/nvflash_t20 --resume --rawdevicewrite 0 512 ./repart-block.bin + +When flashing is done, reboot the device. + Boot ---- @@ -113,8 +130,8 @@ device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/asus/grouper.rst b/doc/board/asus/grouper.rst index 14469582907..78183482a00 100644 --- a/doc/board/asus/grouper.rst +++ b/doc/board/asus/grouper.rst @@ -5,7 +5,8 @@ U-Boot for the ASUS/Google Nexus 7 (2012) ``DISCLAMER!`` Moving your ASUS/Google Nexus 7 (2012) to use U-Boot assumes replacement of the vendor ASUS bootloader. Vendor android firmwares will no -longer be able to run on the device. This replacement IS reversible. +longer be able to run on the device. This replacement IS reversible if you +have backups. Quick Start ----------- @@ -39,65 +40,45 @@ Process U-Boot in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form -usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. You need to know your -tablet's individual SBK to continue. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. You need to know your device +individual SBK to continue. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev grouper --sbk + $ ./re-crypt.py --dev grouper --sbk --split # or --dev tilapia where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` -The script will produce a ``repart-block.bin`` ready to flash. - -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it by pre-loading vendor bootloader with the Fusée Gelée. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct -b android_bootloader.bin - $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin - -When flashing is done, reboot the device. Note that if you have cellular version, -use ``tilapia.bct``. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered by holding ``power`` and ``volume up`` buttons on +turned off tablet connected to the host PC. Host PC should detect APX USB +device in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct --b u-boot-dtb-tegra.bin # or tilapia.bct While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -120,8 +101,8 @@ bootmenu. Bootmenu contains entries to mount eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/asus/transformer_t20.rst b/doc/board/asus/transformer_t20.rst index 4f4f893c3a8..2b721b4c076 100644 --- a/doc/board/asus/transformer_t20.rst +++ b/doc/board/asus/transformer_t20.rst @@ -5,7 +5,8 @@ U-Boot for the ASUS Eee Pad Transformer device family ``DISCLAMER!`` Moving your ASUS Eee Pad Transformer/Slider to use U-Boot assumes replacement of the vendor ASUS bootloader. Vendor Android firmwares -will no longer be able to run on the device. This replacement IS reversible. +will no longer be able to run on the device. This replacement IS reversible +if you have backups. Quick Start ----------- @@ -40,61 +41,46 @@ in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +to recover the device in case of a failed update. You need to know your device +individual SBK to continue. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev tf101 + $ ./re-crypt.py --dev tf101v1 --split # or tf101v2 or sl101 as --dev -The script will produce a ``repart-block.bin`` ready to flash. - -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ wheelie -1 --bl bootloader.bin --bct tf101.bct --odm 0x300d8011 || break - $ nvflash --resume --rawdevicewrite 0 2048 repart-block.bin - -When flashing is done, reboot the device. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered by holding ``power`` and ``volume up`` buttons on +turned off tablet connected to the host PC. Host PC should detect APX USB +device in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./utils/nvflash_t20 --setbct --bct ./bct/.bct --configfile ./utils/flash.cfg + --bl u-boot-dtb-tegra.bin --sbk --sync + +Where is your devie codename, either ``tf101`` or ``sl101`` and is SBK +of your device in the form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -117,8 +103,8 @@ device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst index 012a38251aa..cab8b32f97e 100644 --- a/doc/board/asus/transformer_t30.rst +++ b/doc/board/asus/transformer_t30.rst @@ -5,7 +5,7 @@ U-Boot for the ASUS Transformer device family ``DISCLAMER!`` Moving your ASUS Transformer to use U-Boot assumes replacement of the vendor ASUS bootloader. Vendor Android firmwares will no longer be -able to run on the device. This replacement IS reversible. +able to run on the device. This replacement IS reversible if you have backups. Quick Start ----------- @@ -45,65 +45,51 @@ Process U-Boot in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form -usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. You need to know your -tablet's individual SBK to continue. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. You need to know your device +individual SBK to continue. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev tf201 --sbk + $ ./re-crypt.py --dev tf201 --sbk --split where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` -The script will produce a ``repart-block.bin`` ready to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +``NOTE!`` If you have TF700T it may have different sizes of boot0/boot1 partitions, +re-crypt sets default boot partition size to 2MB and if you have different size +add ``--bootsize`` key with yout boot partition size in bytes to the command. Flashing U-Boot into the eMMC ----------------------------- -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it by pre-loading vendor bootloader with the Fusée Gelée. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ ./run_bootloader.sh -s T30 -t ./bct/tf201.bct -b android_bootloader.bin - $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin - -When flashing is done, reboot the device. Note that you should adjust bct file -name according to your device. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered by holding ``power`` and ``volume up`` buttons on +turned off tablet connected to the host PC. Host PC should detect APX USB +device in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/.bct --b u-boot-dtb-tegra.bin + +Where is your devie codename (``tf201``, ``tf300t``, ``tf700t`` etc.). While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -124,6 +110,14 @@ Some of Transformers use a separate 4 MB SPI flash, which contains all data required for boot. It is flashed from within U-Boot itself, preloaded into RAM using Fusée Gelée. +Create ``repart-block.bin`` using re-crypt without ``--split`` key: + +.. code-block:: bash + + $ git clone https://gitlab.com/grate-driver/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-tegra.bin here + $ ./re-crypt.py --dev tf600t --sbk + After creating your ``repart-block.bin`` you have to place it on a 1st partition of microSD card formated in fat. Then insert this microSD card into your tablet and boot it using Fusée Gelée and U-Boot, which was included into @@ -147,8 +141,8 @@ device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst index 53df2d09a6f..415356da4e5 100644 --- a/doc/board/htc/endeavoru.rst +++ b/doc/board/htc/endeavoru.rst @@ -3,9 +3,9 @@ U-Boot for the HTC One X (endeavoru) ==================================== -``DISCLAMER!`` Moving your HTC ONe X to use U-Boot assumes replacement of the +``DISCLAMER!`` Moving your HTC One X to use U-Boot assumes replacement of the vendor hboot. Vendor android firmwares will no longer be able to run on the -device. This replacement IS reversible. +device. This replacement IS reversible if you have backups. Quick Start ----------- @@ -35,61 +35,42 @@ Process U-Boot in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form -usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev endeavoru + $ ./re-crypt.py --dev endeavoru --split -The script will produce a ``repart-block.bin`` ready to flash. - -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it by pre-loading vendor bootloader with the Fusée Gelée. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct -b android_bootloader.bin - $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin - -When flashing is done, reboot the device. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. For HTC One X (endeavoru) this mode can be entered using ``fastboot oem rcm`` +command from modified S-OFF bootloader or using testpad on motherboard. Host PC +should detect APX USB device in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct --b u-boot-dtb-tegra.bin While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -112,8 +93,8 @@ bootmenu. Bootmenu contains entries to mount eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/lg/star.rst b/doc/board/lg/star.rst index 9e480929182..580a6ee9468 100644 --- a/doc/board/lg/star.rst +++ b/doc/board/lg/star.rst @@ -5,7 +5,7 @@ U-Boot for the LG Optimus 2X P990 ``DISCLAMER!`` Moving your device to use U-Boot assumes replacement of the vendor bootloader. Vendor Android firmwares will no longer be able to run on -the device. This replacement IS reversible. +the device. This replacement IS reversible if you have backups. Quick Start ----------- @@ -35,62 +35,42 @@ Process U-Boot in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form -usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev star + $ ./re-crypt.py --dev star --split -The script will produce a ``repart-block.bin`` ready to flash. - -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. Additionally you must install ``tegrarcm``. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it by pre-loading vendor bootloader with nvflash. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ ./nvflash_v1.13.87205 --bct star.bct --setbct --odmdata 0xC8000 - --configfile flash.cfg --bl android_bootloader.bin --sync - $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 2048 repart-block.bin - -When flashing is done, reboot the device. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered by holding ``power`` and both volume buttons on +turned off phone connected to the host PC. Host PC should detect APX USB device +in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ tegrarcm --bct ./bct/star.bct --bootloader u-boot-dtb-tegra.bin --loadaddr 0x108000 While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -113,8 +93,8 @@ device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst index 9ff75034b72..45a75f6d57f 100644 --- a/doc/board/lg/x3_t30.rst +++ b/doc/board/lg/x3_t30.rst @@ -5,7 +5,7 @@ U-Boot for the LG X3 T30 device family ``DISCLAMER!`` Moving your LG P880 or P895 to use U-Boot assumes replacement of the vendor LG bootloader. Vendor android firmwares will no longer be able -to run on the device. This replacement IS reversible. +to run on the device. This replacement IS reversible if you have backups. Quick Start ----------- @@ -38,62 +38,42 @@ Process U-Boot in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form -usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev p895 + $ ./re-crypt.py --dev p895 --split # or --dev p880 -The script will produce a ``repart-block.bin`` ready to flash. - -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it by pre-loading vendor bootloader with the Fusée Gelée. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct -b android_bootloader.bin - $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin - -When flashing is done, reboot the device. Note that if you have Optimus 4x HD, -use ``p880.bct``. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered by holding ``power`` and both buttons on turned +off phone connected to the host PC. Host PC should detect APX USB device in +``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct --b u-boot-dtb-tegra.bin # or p880.bct While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -116,8 +96,8 @@ bootmenu. Bootmenu contains entries to mount eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/microsoft/surface-2.rst b/doc/board/microsoft/surface-2.rst index 8185c6f5ae4..93d9d613cdb 100644 --- a/doc/board/microsoft/surface-2.rst +++ b/doc/board/microsoft/surface-2.rst @@ -33,7 +33,7 @@ directory with .. code-block:: bash - $ ./run_bootloader.sh -s T30 -t ./bct/surface-2.bct + $ ./run_bootloader.sh -s T114 -t ./bct/surface-2.bct To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on eMMC. Additionally, if the Volume Down button is pressed while loading, the diff --git a/doc/board/motorola/mot.rst b/doc/board/motorola/mot.rst index d0f89bcd357..80f85ec9dfd 100644 --- a/doc/board/motorola/mot.rst +++ b/doc/board/motorola/mot.rst @@ -67,9 +67,26 @@ Flashing U-Boot into the eMMC ``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. + +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. + +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. For Motorola Atrix 4G (MB860) and Droid X2 (MB870) this mode can be entered +from vendor bootloader menu and with special cable from prerequisites chapter. +Host PC should detect APX USB device in ``lsusb``. + U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./utils/nvflash_t20 --setbct --bct ./bct/olympus.bct --configfile ./utils/flash.cfg + --bl u-boot-dtb-tegra.bin --sbk --sync While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -92,8 +109,8 @@ device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/nxp/imx952_evk.rst b/doc/board/nxp/imx952_evk.rst new file mode 100644 index 00000000000..f5f4d8d4b0c --- /dev/null +++ b/doc/board/nxp/imx952_evk.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx952_evk +========== + +U-Boot for the NXP i.MX952 15x15 LPDDR4X EVK board + +Quick Start +----------- + +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Get ahab-container.img +---------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://nl2-nxrm.sw.nxp.com/repository/IMX_Yocto_Internal_Mirror_Recent/firmware-ele-imx-2.0.5-50c4793.bin + $ sh firmware-ele-imx-2.0.5-50c4793.bin --auto-accept + $ cp firmware-ele-imx-2.0.5-50c4793/mx952a0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://nl2-nxrm.sw.nxp.com/repository/IMX_Yocto_Internal_Mirror_Recent/firmware-imx-8.32-c0491e4.bin + $ sh firmware-imx-8.32-c0491e4.bin --auto-accept + $ cp firmware-imx-8.32-c0491e4/firmware/ddr/synopsys/lpddr4x*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: srctree is U-Boot source directory +Get OEI from: https://github.com/nxp-imx/imx-oei +branch: lf-6.18.2-imx952-er1 + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone https://github.com/nxp-imx/imx-oei/ -b lf-6.18.2-imx952-er1 + $ cd imx-oei + $ make board=mx952lp4x-15 oei=ddr DEBUG=1 all + $ cp build/mx952lp4x-15/ddr/oei-m33-ddr.bin $(srctree) + +Get and Build System Manager Image +---------------------------------- + +Note: srctree is U-Boot source directory +Get System Manager from: https://github.com/nxp-imx/imx-sm +branch: lf-6.18.2-imx952-er1 + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone https://github.com/nxp-imx/imx-sm/ -b lf-6.18.2-imx952-er1 + $ cd imx-sm + $ make config=mx952evk all + $ cp build/mx952evk/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf-6.18.2-imx952-er1 + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ unset LDFLAGS + $ unset AS + $ git clone https://github.com/nxp-imx/imx-atf/ -b lf-6.18.2-imx952-er1 + $ cd imx-atf + $ make PLAT=imx952 bl31 + $ cp build/imx952/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx952_evk_defconfig + $ make + +Copy flash.bin to the MicroSD card: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +---- + +Set i.MX952 boot device to MicroSD card diff --git a/doc/board/nxp/imx95_evk.rst b/doc/board/nxp/imx95_evk.rst index b8c3f4bed50..593981e6a65 100644 --- a/doc/board/nxp/imx95_evk.rst +++ b/doc/board/nxp/imx95_evk.rst @@ -60,8 +60,8 @@ branch: master .. code-block:: bash $ sudo apt -y install make gcc g++-multilib srecord - $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz - $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz $ export TOOLS=$PWD $ git clone -b master https://github.com/nxp-imx/imx-oei.git $ cd imx-oei @@ -100,8 +100,8 @@ branch: master .. code-block:: bash $ sudo apt -y install make gcc g++-multilib srecord - $ wget https://developer.arm.com/-/media/Files/downloads/gnu/13.3.rel1/binrel/arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz - $ tar xvf arm-gnu-toolchain-13.3.rel1-x86_64-arm-none-eabi.tar.xz + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz $ export TOOLS=$PWD $ git clone -b master https://github.com/nxp-imx/imx-sm.git $ cd imx-sm @@ -152,7 +152,7 @@ i.MX95 B0 silicon version on 15x15 LPDDR4X EVK $ make imx95_15x15_evk_defconfig $ make -Copy imx-boot-imx95.bin to the MicroSD card: +Copy flash.bin to the MicroSD card: .. code-block:: bash diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 01d3468a47d..8cd24aecf33 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -19,6 +19,7 @@ NXP Semiconductors imx93_frdm imx943_evk imx95_evk + imx952_evk imxrt1020-evk imxrt1050-evk imxrt1170-evk diff --git a/doc/board/ouya/ouya.rst b/doc/board/ouya/ouya.rst index 641affc6294..6cc68b01f90 100644 --- a/doc/board/ouya/ouya.rst +++ b/doc/board/ouya/ouya.rst @@ -5,7 +5,7 @@ U-Boot for the Ouya Game Console (ouya) ``DISCLAMER!`` Moving your Ouya to use U-Boot assumes replacement of the vendor bootloader. Vendor android firmwares will no longer be able to run on the -device. This replacement IS reversible. +device. This replacement IS reversible if you have backups. Quick Start ----------- @@ -35,62 +35,44 @@ Process U-Boot in re-crypt repo issues. NOT HERE! re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form -usable by device. This process is required only on the first installation or -to recover the device in case of a failed update. - -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. You need to know your device +individual SBK to continue. .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev ouya + $ ./re-crypt.py --dev ouya --sbk --split -The script will produce a ``repart-block.bin`` ready to flash. +where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. Regardless of the method bct and bootloader -will end up in boot0 and boot1 partitions of eMMC. - -Flashing with the NV3P protocol -******************************* - -``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it by pre-loading vendor bootloader with the Fusée Gelée. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. -.. code-block:: bash - - $ ./run_bootloader.sh -s T30 -t ./bct/ouya.bct -b android_bootloader.bin - $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin - -When flashing is done, reboot the device. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered from testpad on motherboard with device connected +to the host PC. Host PC should detect APX USB device in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +fusee-tools: + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/ouya.bct --b u-boot-dtb-tegra.bin While pre-loading U-Boot, interrupt bootflow by pressing ``CTRL + C`` (USB keyboard must be plugged in before U-Boot is preloaded, else it will not work), input @@ -113,8 +95,8 @@ bootmenu provides entries to mount eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/phytec/imx93-phycore.rst b/doc/board/phytec/imx91-93-phycore.rst similarity index 52% rename from doc/board/phytec/imx93-phycore.rst rename to doc/board/phytec/imx91-93-phycore.rst index bd110a3ebee..42bcda100e0 100644 --- a/doc/board/phytec/imx93-phycore.rst +++ b/doc/board/phytec/imx91-93-phycore.rst @@ -1,9 +1,11 @@ .. SPDX-License-Identifier: GPL-2.0+ -phyCORE-i.MX 93 -=============== +phyCORE-i.MX 91/93 +================== -U-Boot for the phyCORE-i.MX 93. +U-Boot for the phyCORE-i.MX 91/93. Both SoC variants, that is i.MX 91 and i.MX 93, +are supported by same board code, however each variant uses different defconfig +and ATF/ELE firmware blobs. Please follow the correct steps for the populated SoC. Quick Start ----------- @@ -18,7 +20,17 @@ Get and Build the ARM Trusted firmware Note: srctree is U-Boot source directory Get ATF from: https://github.com/nxp-imx/imx-atf/ -branch: lf_v2.8 +branch: lf_v2.12 + +For phyCORE-i.MX 91 variant: + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx91 bl31 + $ cp build/imx91/release/bl31.bin $(srctree) + +For phyCORE-i.MX 93 variant: .. code-block:: bash @@ -41,14 +53,24 @@ Get ahab-container.img .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin - $ chmod +x firmware-sentinel-0.11.bin - $ ./firmware-sentinel-0.11.bin - $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin + $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin + $ ./firmware-ele-imx-1.3.0-17945fc.bin + $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree) + $ cp firmware-ele-imx-1.3.0-17945fc/mx93a1-ahab-container.img $(srctree) Build U-Boot ------------ +For phyCORE-i.MX 91 variant: + +.. code-block:: bash + + $ make imx91-phycore_defconfig + $ make + +For phyCORE-i.MX 93 variant: + .. code-block:: bash $ make imx93-phycore_defconfig diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index dd9edd792f4..4519079ab3d 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -8,7 +8,7 @@ PHYTEC imx8mp-libra-fpsc imx8mm-phygate-tauri-l - imx93-phycore + imx91-93-phycore phycore-am62x phycore-am62ax phycore-am64x diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 6ae4d4371ff..141071f528a 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -40,15 +40,17 @@ List of mainline supported Rockchip boards: * rk3229 - Rockchip Evb-RK3229 (evb-rk3229) * rk3288 - - Rockchip Evb-RK3288 (evb-rk3288) + - Rockchip Evb-RK3288-rk808 (evb-rk3288-rk808) - Firefly-RK3288 (firefly-rk3288) - MQmaker MiQi (miqi-rk3288) - Phytec RK3288 PCM-947 (phycore-rk3288) - PopMetal-RK3288 (popmetal-rk3288) - Radxa Rock 2 Square (rock2) + - Radxa Rock Pi N8 (rock-pi-n8-rk3288) - Tinker-RK3288 (tinker-rk3288) + - Tinker-S-RK3288 (tinker-s-rk3288) - Google Jerry (chromebook_jerry) - - Google Mickey (chromebook_mickey) + - Google Mickey (chromebit_mickey) - Google Minnie (chromebook_minnie) - Google Speedy (chromebook_speedy) - Amarula Vyasa-RK3288 (vyasa-rk3288) @@ -101,6 +103,7 @@ List of mainline supported Rockchip boards: * rk3528 - ArmSoM Sige1 (sige1-rk3528) + - FriendlyElec NanoPi Zero2 (nanopi-zero2-rk3528) - Generic RK3528 (generic-rk3528) - Radxa E20C (radxa-e20c-rk3528) - Radxa ROCK 2A/2F (rock-2-rk3528) @@ -154,7 +157,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s) - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s) - GameForce Ace (gameforce-ace-rk3588s) - - Generic RK3588S/RK3588 (generic-rk3588) + - Generic RK3582/RK3588S/RK3588 (generic-rk3588) - Hardkernel ODROID-M2 (odroid-m2-rk3588s) - Indiedroid Nova (nova-rk3588s) - Khadas Edge2 (khadas-edge2-rk3588s) @@ -163,7 +166,7 @@ List of mainline supported Rockchip boards: - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B/5B+/5T (rock5b-rk3588) - - Radxa ROCK 5C (rock-5c-rk3588s) + - Radxa ROCK 5C/5C Lite (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588) @@ -244,7 +247,7 @@ To build rk3288 boards: .. code-block:: bash - make evb-rk3288_defconfig + make evb-rk3288-mk808_defconfig make CROSS_COMPILE=arm-linux-gnueabihf- To build rk3308 boards: diff --git a/doc/board/samsung/n1.rst b/doc/board/samsung/n1.rst index 4dbb3141774..89bd2c8d6d1 100644 --- a/doc/board/samsung/n1.rst +++ b/doc/board/samsung/n1.rst @@ -5,7 +5,8 @@ U-Boot for the Samsung N1 device family ``DISCLAMER!`` Moving your Samsung Galaxy R (GT-I9103) or Samsung Captivate Glide (SGH-i927) to use U-Boot assumes replacement of the sboot. Vendor android firmwares -will no longer be able to run on the device. This replacement IS reversible. +will no longer be able to run on the device. This replacement IS reversible if you +have backups. Quick Start ----------- diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst index f85d7376b44..0996e0a68aa 100644 --- a/doc/board/starfive/index.rst +++ b/doc/board/starfive/index.rst @@ -10,5 +10,6 @@ StarFive milk-v_mars milkv_marscm_emmc milkv_marscm_lite + orangepi_rv pine64_star64 visionfive2 diff --git a/doc/board/starfive/jh7110_common.rst b/doc/board/starfive/jh7110_common.rst index 77102fcc189..e9c0ed5b022 100644 --- a/doc/board/starfive/jh7110_common.rst +++ b/doc/board/starfive/jh7110_common.rst @@ -162,8 +162,8 @@ Build U-Boot git -C opensbi.git checkout v1.7 # always clean build directory when building OpenSBI due to incomplete # dependency tracking - make -C opensbi.git -O opensbi clean - make -C opensbi.git -O opensbi PLATFORM=generic + make -C opensbi.git O=opensbi clean + make -C opensbi.git O=opensbi PLATFORM=generic 4. Now build the First Stage BootLoader (U-Boot Secondary Program Loader) and Second Boot Loader (OpenSBI + U-Boot Main): @@ -171,9 +171,8 @@ Build U-Boot .. code-block:: console git clone https://source.denx.de/u-boot/u-boot.git u-boot.git - make -C u-boot.git -O u-boot starfive_visionfive2_defconfig - export OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin - make -C u-boot.git -O u-boot + make -C u-boot.git O=u-boot starfive_visionfive2_defconfig + make -C u-boot.git O=u-boot OPENSBI=opensbi/platform/generic/firmware/fw_dynamic.bin This will generate the U-Boot SPL image object post-processed with StarFive SPL headers (u-boot/spl/u-boot-spl.bin.normal.out) as well as the FIT image @@ -191,7 +190,7 @@ Build U-Boot --set-val SPL_DEBUG_UART_BASE 0x10000000 \ --set-val DEBUG_UART_SHIFT 2 - make -C u-boot.git -O u-boot olddefconfig + make -C u-boot.git O=u-boot olddefconfig Boot description ---------------- diff --git a/doc/board/starfive/orangepi_rv.rst b/doc/board/starfive/orangepi_rv.rst new file mode 100644 index 00000000000..29cc58a1e2b --- /dev/null +++ b/doc/board/starfive/orangepi_rv.rst @@ -0,0 +1,35 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Xunlong OrangePi RV +=================== + +U-Boot for the OrangePi RV uses the same U-Boot binaries as the VisionFive 2 +board. In U-Boot SPL the actual board is detected as a VisionFive2 1.3b due to +a manufacturer problem and having the same EEPROM data as VisionFive2 1.3b. + +Device-tree selection +--------------------- + +U-Boot will set variable $fdtfile to starfive/jh7110-starfive-visionfive-2-v1.3b.dtb + +This is sufficient for U-Boot however fails to work correctly with the Linux Kernel. + +To overrule this selection the variable can be set manually and saved in the +environment + +:: + + env set fdtfile starfive/jh7110-orangepi-rv.dtb + env save + +EEPROM modification +------------------- + +For advanced users and developers an EEPROM identifier product serial number +beginning with "XOPIRV" will match the OrangePi RV and automatically set the +correct device-tree at U-Boot SPL phase. The procedure for writing EEPROM data +is not detailed here however is similar to that of the Pine64 Star64 and Milk-V +Mars CM. The write-protect disable pads on the Orange Pi RV circuit board +bottom are labeled WP and GND near the M.2 connector. + +.. include:: jh7110_common.rst diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst index b14ba41917e..904881b4146 100644 --- a/doc/board/ti/am335x_evm.rst +++ b/doc/board/ti/am335x_evm.rst @@ -481,3 +481,83 @@ bind with it: misc 0 [ + ] ti-musb-wrapper | |-- usb@47400000 usb 0 [ ] ti-musb-peripheral | | |-- usb@47401000 usb 0 [ ] ti-musb-host | | `-- usb@47401800 + +Failsafe bootloader update +-------------------------- + +As indicated above, the ROM code on the AM335x supports loading SPL +from one of several different locations. It looks at offsets 0, +128KiB, 256KiB and 384KiB (sectors 0, 0x100, 0x200, 0x300) for a +sector containing a valid "TOC structure" (see the reference manual +for details). + +This can be used to implement a scheme for updating SPL which is +robust against power failure or other interruptions: Suppose we store +copies of SPL (wrapped in the "MLO" image, which is what includes that +TOC structure) at offsets 128KiB and 256KiB, and let us refer to those +two locations as slot 1 and slot 2. + +The whole procedure maintains the invariant that at any time, at +least one of the slots contains a complete and valid MLO image. In +order to update SPL: + +(1) Determine a slot X containing a valid image (by having a proper + TOC structure in the first sector). Designate the other + slot Y. Since the TOC is always the same 512 bytes (see section + 26.1.11 in the reference manual), checking for a valid image can + be done using something like + +.. code-block:: bash + + if cmp -s -n 512 MLO /path/to/SPL-1 ; then + X=1 + Y=2 + elif cmp -s -n 512 MLO /path/to/SPL-2 ; then + X=2 + Y=1 + else + # invariant broken, fatal error, refuse update... + fi + +(2) Ensure Y will be deemed invalid by the ROM code by writing all + zeroes to the first sector of Y, for example using + +.. code-block:: bash + + dd if=/dev/zero of=/path/to/SPL-Y bs=512 count=1 conv=fsync + +(3) Write everything but the first sector of the MLO image to slot Y: + +.. code-block:: bash + + dd if=MLO of=/path/to/SPL-Y bs=512 skip=1 seek=1 conv=fsync + +(4) Write the TOC structure to slot Y: + +.. code-block:: bash + + dd if=MLO of=/path/to/SPL-Y bs=512 count=1 conv=fsync + +(5) Repeat steps (2)--(4) for slot X. + +Now, this procedure only accounts for safely updating SPL. If U-Boot +proper is only stored in a single location, there is no way to update +that which is safe against powercut during the update. However, by +selecting the configuration option CONFIG_SPL_AM33XX_MMCSD_MULTIPLE, +you can tell SPL to load U-Boot proper from a location which depends on +where SPL itself was loaded from. Hence, one can for example put +copies of u-boot.img at offsets 512KiB and 1536KiB, and set + +:: + + CONFIG_SPL_AM33XX_MMCSD_MULTIPLE=y + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_128K=0x400 + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_256K=0xc00 + +and amend the step (3) above by + + Write U-Boot proper to the location corresponding to slot Y: + +.. code-block:: bash + + dd if=u-boot.img of=/path/to/U-BOOT-Y bs=512 conv=fsync diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst index d858dc7cdbb..fb767bedbf6 100644 --- a/doc/board/ti/j784s4_evm.rst +++ b/doc/board/ti/j784s4_evm.rst @@ -299,6 +299,10 @@ http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section. - 00000000 - 01110000 + * - PCIe + - 10001000 + - 01010000 + For SW7 and SW11, the switch state in the "ON" position = 1. Boot Mode Pins for AM69-SK @@ -330,6 +334,307 @@ section. For SW2, the switch state in the "ON" position = 1. +PCIe Boot +--------- + +The J784S4 SoC supports booting over PCIe, allowing the device to function +as a PCIe endpoint and receive boot loader images from a PCIe Root Complex. +The PCIe1 instance of PCIe is configured by Boot ROM for Endpoint Mode of +operation. Hence, the PCIe Connector on the EVM corresponding to PCIe1 +should be utilized for PCIe Boot. + +Hardware Setup +^^^^^^^^^^^^^^ + +To boot the J784S4 EVM via PCIe, the following hardware setup is required: + +1. Configure the boot mode switches on J784S4-EVM for PCIe boot: + + .. code-block:: text + + SW7: 01010000 + SW11: 10001000 + +2. Connect the J784S4-EVM (endpoint) to a PCIe Root Complex (e.g., x86 host) + using a PCIe cable. Both boards should be powered off before making the + connection. + +Endpoint Configuration +^^^^^^^^^^^^^^^^^^^^^^ + +The following configuration options are enabled by default in +``j784s4_evm_r5_defconfig`` and ``j784s4_evm_a72_defconfig``: + +- ``CONFIG_SPL_PCI_DFU_BAR_SIZE``: Size of the PCIe BAR for DFU/boot image download +- ``CONFIG_SPL_PCI_DFU_VENDOR_ID``: PCIe vendor ID advertised by the endpoint +- ``CONFIG_SPL_PCI_DFU_DEVICE_ID``: PCIe device ID advertised by the endpoint +- ``CONFIG_SPL_PCI_DFU_MAGIC_WORD``: Magic word written by Root Complex to signal image transfer completion +- ``CONFIG_SPL_PCI_DFU_BOOT_PHASE``: Current boot phase indicator for Root Complex + +By default, PCIe Root Complex mode is enabled in the device tree. For PCIe Boot, +build the Bootloaders with the following content added to k3-j784s4-evm-u-boot.dtsi: + +.. code-block:: devicetree + + &serdes0 { + /delete-property/ serdes0_usb_link; + }; + + &serdes_refclk { + bootph-all; + }; + + &serdes0_pcie1_link { + bootph-all; + }; + + &serdes_ln_ctrl { + bootph-all; + }; + + &pcie1_ctrl { + bootph-all; + }; + + &pcie1_rc { + status = "disabled"; + }; + + &cbass_main { + pcie1_ep: pcie-ep@2910000 { + compatible = "ti,j784s4-pcie-ep"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = ; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 333 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <6>; + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys = <&serdes0_pcie1_link>; + phy-names = "pcie-phy"; + bootph-all; + }; + }; + +PCIe Boot Procedure +^^^^^^^^^^^^^^^^^^^ + +The following steps describe the process of booting J784S4-EVM over PCIe: + +1. Compile the sample host program (provided after this section): + + .. prompt:: bash + + gcc -o pcie_boot_util pcie_boot_util.c + +2. Power on the J784S4-EVM (endpoint) after configuring boot mode switches + for PCIe Boot. + +3. Copy the compiled sample host program (pcie_boot_util) and the bootloader + images to the Root Complex. Check PCIe enumeration on Root Complex to ensure + that the J784S4 EVM shows up as the PCIe Endpoint: + + .. prompt:: bash + + lspci + + The endpoint will appear as a RAM device or with multiple functions: + + .. code-block:: text + + 0000:00:00.0 PCI bridge: Texas Instruments Device b012 + 0000:01:00.0 RAM memory: Texas Instruments Device b012 + 0000:01:00.1 Non-VGA unclassified device: Texas Instruments Device 0100 + 0000:01:00.2 Non-VGA unclassified device: Texas Instruments Device 0100 + +4. Copy ``tiboot3.bin`` to the endpoint. Use ``lspci -vv`` to identify the BAR + address: + + .. prompt:: bash + + sudo ./pcie_boot_util 0x4007100000 tiboot3.bin + + The sample program automatically writes the image start address to + ``0x41CF3FE0`` and the magic word ``0xB17CEAD9`` to ``0x41CF3FE4``. + +5. After ``tiboot3.bin`` is processed, the PCIe link will go down briefly. + Remove the PCIe device and rescan the bus: + + .. prompt:: bash + + echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/remove + echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/rescan + lspci + + The enumeration will change to something similar: + + .. code-block:: text + + 0000:00:00.0 PCI bridge: Texas Instruments Device b012 + 0000:01:00.0 RAM memory: Texas Instruments Device b010 (rev dc) + + .. note:: + + When the Root-Complex enumerates the PCIe Endpoint after a 'remove-rescan' sequence, + it is possible that the 'BAR' appears 'disabled'. If so, writing to the BAR via the + 'pcie_boot_util' to transfer the bootloader image will have no effect. In such cases, + run 'setpci -s 0000:01:00.0 COMMAND=0x02' on the Root-Complex after enumeration + (with appropriate DOMAIN:BUS:DEVICE.FUNCTION corresponding to the Endpoint) to enable + the BAR. + +6. Copy ``tispl.bin`` to the new BAR address (use ``lspci -vv`` to find): + + .. prompt:: bash + + sudo ./pcie_boot_util 0x4000400000 tispl.bin + +7. After ``tispl.bin`` is processed, the PCIe link will go down again. Remove + and rescan the PCIe device: + + .. prompt:: bash + + echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/remove + echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/rescan + +8. Copy ``u-boot.img``: + + .. prompt:: bash + + sudo ./pcie_boot_util 0x4000400000 u-boot.img + +9. After ``u-boot.img`` is successfully loaded, the boot process is complete + and endpoint should boot till U-Boot prompt. + +.. note:: + + During the boot process, "PCIe LINK DOWN" messages might appear in kernel + logs. This is expected as the endpoint resets and re-initializes the PCIe + link after processing each boot stage. + +Sample Host Program +^^^^^^^^^^^^^^^^^^^ + +The following C program can be used on the Root Complex to copy bootloader images +to the J784S4 endpoint: + +.. code-block:: c + + #include + #include + #include + #include + #include + #include + + #define MAP_SIZE 0x400000 + + /* + * bootloader_file: Path to the bootloader image (tiboot3.bin, tispl.bin and u-boot.img) + * bootloader_mem: Memory allocated in RAM for reading the bootloader image file + * bar_address: Address of BAR to which bootloader image will be written + * bar_map_base: Mapping of the BAR Base Address for the program + * load_address: Address in BAR region where bootloader is being transferred + * transfer_completion_offset: Offset in BAR region to write to notify completion of transfer + * fd_mem: File descriptor for opening /dev/mem + * fptr: File pointer for bootloader image in filesystem + * magic_word: Magic word to notify completion of tiboot3.bin transfer to Boot ROM + * use_magic_word: Flag to indicate if Magic Word has to be written + * file_size: Size of bootloader image + * i: Iterator used during bootloader image transfer + */ + int main(int argc, char *argv[]) + { + off_t bar_address, load_address, transfer_completion_offset; + unsigned char *bootloader_mem; + const char *bootloader_file; + int fd_mem, i, use_magic_word; + unsigned int magic_word; + void *bar_map_base; + long file_size; + FILE * fptr; + + if (argc != 3) { + printf("Usage: %s \n", argv[0]); + return 0; + } + + bar_address = strtoul(argv[1], NULL, 16); + bootloader_file = argv[2]; + + printf("Bootloader File: %s\n", bootloader_file); + printf("BAR Address: 0x%lx\n", bar_address); + + if(!strcmp(bootloader_file,"tiboot3.bin")) { + transfer_completion_offset = 0xF3FE0; + load_address = 0x41C00000; + magic_word = 0xB17CEAD9; + use_magic_word = 1; + } else { + transfer_completion_offset = MAP_SIZE - 0x4; + load_address = 0xDEADBEEF; + use_magic_word = 0; + } + + fd_mem = open("/dev/mem", O_RDWR | O_SYNC); + if(fd_mem == -1) { + printf("failed to open /dev/mem\n"); + return -1; + } + + bar_map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, bar_address); + if(bar_map_base == (void *)-1) { + printf("failed to map BAR\n"); + return -1; + } + + fptr = fopen(bootloader_file, "rb"); + if (!fptr) { + printf("failed to read bootloader file\n"); + return -1; + } + + fseek(fptr, 0, SEEK_END); + file_size = ftell(fptr); + rewind(fptr); + + bootloader_mem = (unsigned char *)malloc(sizeof(char) * file_size); + if(!bootloader_mem) { + printf("failed to allocate local memory for bootloader file\n"); + return -1; + } + + if (fread(bootloader_mem, 1, file_size, fptr) != file_size) { + printf("failed to read bootloader file into local memory\n"); + return -1; + } + + for(i = 0; i < file_size; i++) { + *((char *)(bar_map_base) + i) = bootloader_mem[i]; + } + + *(unsigned int *)(bar_map_base + transfer_completion_offset) = (unsigned int)(load_address); + + if(use_magic_word) { + *(unsigned int *)(bar_map_base + transfer_completion_offset + 4) = magic_word; + printf("Magic word written for Boot ROM\n"); + } + + printf("Transferred %s to Endpoint\n", bootloader_file); + return 0; + } + +This program copies the boot image to the PCIe endpoint's memory region and +writes the necessary control words to signal image transfer completion. + Debugging U-Boot ---------------- diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index ed04a57c167..74ece0c9acf 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -678,6 +678,72 @@ filesystem and then imported fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile} env import -t ${loadaddr} ${filesize} +Built-in Self-Test (BIST) +-------------------------- + +Built-in Self-test (BIST) is a feature that allows self testing of the memory +areas and logic circuitry in an Integrated Circuit (IC) without any external +test equipment. In an embedded system, these tests are typically used during +boot time or shutdown of the system to check the health of an SoC. PBIST is used +to test the memory regions in the SoC and provides detection for permanent +faults. The primary use case for PBIST is when it is invoked at start-up +providing valuable information on any stuck-at bits in the memory. LBIST is used +to test the logic circuitry in an SoC associated with the CPU cores. There are +multiple LBIST instances in the SoC, and each has a different processor core +associated with it. There are LBIST tests that can be software-initiated. + +Current implementation triggers the BIST tests on the MAIN_R5_2_x cores and is +supported only on J784S4-EVM. + +LBIST/PBIST checks of the WKUP_DMSC0 and MCU_R5FSS0 cores and memories are run +in the WKUP/MCU domain; this check is part of HW POST. HW POST runs in hardware, +before the ROM code starts and can be selected by MCU_BOOTMODE[09:08] pins. + +Enable BIST in (:ref:`A72 SPL build `) +by including its config fragment. + +.. prompt:: bash $ + + make $UBOOT_CFG_CORTEXA k3_bist.config + +K3 DDR Subsystem (DDRSS) with Inline ECC +---------------------------------------- + +For SDRAM data integrity, the DDRSS bridge supports inline ECC on the data +written to or read from the SDRAM. ECC is stored together with the data so that +a dedicated SDRAM device for ECC is not required. The 8-bit single error +correction double error detection (SECDED) ECC data is calculated over 64-bit +data quanta. For every 256-byte data block 32 bytes of ECC is stored inline. +Thus, 1/9th of the total SDRAM space is used for ECC storage and the remaining +8/9th of the SDRAM data space are seen as consecutive byte addresses. Even if +there are non-ECC protected regions the previously described 1/9th-8/9th rule +still applies and consecutive byte addresses are seen from system point of view. + +ECC is calculated for all accesses that are within the address ranges protected +by it. 1-bit error is correctable by ECC, but multi-bit and multiple 1-bit +errors are not correctable and will be treated as an uncorrectable error. Any +uncorrectable error will cause a bus abort. + +Enable inline ECC in (:ref:`R5 SPL build `) +by including its config fragment: + +.. prompt:: bash $ + + make $UBOOT_CFG_CORTEXR k3_inline_ecc.config + +This enables inline ECC for the entire region. Instead of defaulting for the +entire DDR region, a partial range can also be selected. In this case, the DDRSS +driver expects such a node within the memory node, in the absence of which it +resorts to enabling for the entire DDR region: + +.. code-block:: dts + + inline_ecc: protected@9e780000 { + device_type = "ecc"; + reg = <0x9e780000 0x0080000>; + bootph-all; + }; + .. _k3_rst_refer_openocd: Common Debugging environment - OpenOCD diff --git a/doc/board/wexler/qc750.rst b/doc/board/wexler/qc750.rst index 169629c7e47..8cf118032cf 100644 --- a/doc/board/wexler/qc750.rst +++ b/doc/board/wexler/qc750.rst @@ -5,7 +5,7 @@ U-Boot for the WEXLER QC750 tablet ``DISCLAMER!`` Moving your WEXLER QC750 to use U-Boot assumes replacement of the vendor bootloader. Vendor Android firmwares will no longer be able -to run on the device. This replacement IS reversible. +to run on the device. This replacement IS reversible if you have backups. Quick Start ----------- @@ -38,26 +38,13 @@ re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form usable by device. This process is required only on the first installation or to recover the device in case of a failed update. -Permanent installation can be performed either by using the tegrarcm or by -pre-loading just built U-Boot into RAM. - -Processing for the NV3P protocol -******************************** - .. code-block:: bash $ git clone https://gitlab.com/grate-driver/re-crypt.git $ cd re-crypt # place your u-boot-dtb-tegra.bin here - $ ./re-crypt.py --dev qc750 + $ ./re-crypt.py --dev qc750 --split -The script will produce a ``repart-block.bin`` ready to flash. - -Processing for pre-loaded U-Boot -******************************** - -The procedure is the same, but the ``--split`` argument is used with the -``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready -to flash. +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. Flashing U-Boot into the eMMC ----------------------------- @@ -65,31 +52,24 @@ Flashing U-Boot into the eMMC ``DISCLAMER!`` All questions related to tegrarcm should be asked in the proper place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! -Permanent installation can be performed either by using the nv3p protocol or by -pre-loading just built U-Boot into RAM. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. -Flashing with the NV3P protocol -******************************* +You have to clone and prepare fusee-tools from here: https://gitlab.com/grate-driver/fusee-tools +according to fusee-tools README to continue. Additionally you must install ``tegrarcm``. -Nv3p is a custom Nvidia protocol used to recover bricked devices. Tegrarcm is -used to handle such state. - -With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in -encrypted state in form, which can just be written RAW at the start of eMMC. - -.. code-block:: bash - - $ tegrarcm --bct qc750.bct --bootloader android_bootloader.bin --loadaddr 0x80108000 - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin - -When flashing is done, reboot the device. - -Flashing with a pre-loaded U-Boot -********************************* +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered via testpad on unpopulated RCM button on motherboard +on device connected to the host PC. Host PC should detect APX USB device in ``lsusb``. U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently U-Boot supports bootmenu entry fastboot, which allows to write a processed copy -of U-Boot permanently into eMMC. +of U-Boot permanently into eMMC. This is how U-Boot can be preloaded using +tegrarcm: + +.. code-block:: bash + + $ tegrarcm --bct ./bct/qc750.bct --bootloader u-boot-dtb-tegra.bin --loadaddr 0x80108000 While pre-loading U-Boot, hold the ``volume down`` button which will trigger the bootmenu. There, select ``fastboot`` using the volume and power buttons. @@ -112,8 +92,8 @@ device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console and update bootloader (check the next chapter). -Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows -the user to use/partition it in any way the user desires. +Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and +allows the user to use/partition it in any way the user desires. Self Upgrading -------------- diff --git a/doc/board/xiaomi/mocha.rst b/doc/board/xiaomi/mocha.rst index 230081e3287..6339e4eb574 100644 --- a/doc/board/xiaomi/mocha.rst +++ b/doc/board/xiaomi/mocha.rst @@ -60,11 +60,15 @@ installation or to recover the device in case of a failed update. The script will produce ``bct.img`` and ``ebt.img`` ready to flash. -Permanent installation can be performed by pre-loading just built U-Boot -into RAM via tegrarcm. While pre-loading U-Boot, hold the ``volume down`` -button which will trigger the bootmenu. There, select ``fastboot`` using -the volume and power buttons. +Permanent installation can be performed by pre-loading just built U-Boot into RAM. +Bct and bootloader will end up in boot0 and boot1 partitions of eMMC. +Bootloader preloading is performed to device in APX/RCM mode connected to host +PC. This mode can be entered via testad on motherboard on turned off device +connected to the host PC. Host PC should detect APX USB device in ``lsusb``. + +While pre-loading U-Boot, hold the ``volume down`` button which will trigger +the bootmenu. There, select ``fastboot`` using the volume and power buttons. After, on host PC, do: .. code-block:: bash diff --git a/doc/develop/binman_tests.rst b/doc/develop/binman_tests.rst index 5e44686b8ad..40865912911 100644 --- a/doc/develop/binman_tests.rst +++ b/doc/develop/binman_tests.rst @@ -331,7 +331,7 @@ Here is a simple test: def testSimple(self): """Test a simple binman with a single file""" - data = self._DoReadFile('005_simple.dts') + data = self._DoReadFile('pack/simple.dts') self.assertEqual(U_BOOT_DATA, data) This test tells Binman to build an image using the description. Then it checks @@ -402,7 +402,7 @@ Another type of test is one which checks error-handling, for example: def testFillNoSize(self): """Test for an fill entry type with no size""" with self.assertRaises(ValueError) as e: - self._DoReadFile('070_fill_no_size.dts') + self._DoReadFile('entry/fill_no_size.dts') self.assertIn("'fill' entry is missing properties: size", str(e.exception)) @@ -436,7 +436,7 @@ correct. You can to this with ``terminal.capture()``, for example: .. code-block:: python with terminal.capture() as (_, stderr): - self._DoTestFile('071_gbb.dts', force_missing_bintools='futility', + self._DoTestFile('cros/gbb.dts', force_missing_bintools='futility', entry_args=entry_args) err = stderr.getvalue() self.assertRegex(err, "Image 'image'.*missing bintools.*: futility") @@ -453,31 +453,15 @@ help with this, but your code will be different. Generally you are adding a test because you are adding a new entry type ('etype'). So start by creating the shortest and simplest image-description you -can, which contains the new etype. Put it in a numbered file in -``tool/binman/test`` so that it comes last. All the numbers are unique and there -are no gaps. +can, which contains the new etype. Put it under ``tools/binman/test`` in the +appropriate subdirectory (e.g. ``fit/`` for FIT image tests, ``vendor/`` for +vendor-specific tests, ``entry/`` for general entry types) with a descriptive +filename. -Example from ``tools/binman/test/339_nxp_imx8.dts``: +Example from ``tools/binman/test/vendor/nxp_imx8.dts``: -.. code-block:: devicetree - - // SPDX-License-Identifier: GPL-2.0+ - - /dts-v1/; - - / { - #address-cells = <1>; - #size-cells = <1>; - - binman { - nxp-imx8mimage { - args; /* TODO: Needed by mkimage etype superclass */ - nxp,boot-from = "sd"; - nxp,rom-version = <1>; - nxp,loader-address = <0x10>; - }; - }; - }; +.. literalinclude:: ../../tools/binman/test/vendor/nxp_imx8.dts + :language: devicetree Note that you should use tabs in the file, not spaces. You can see that this has been cut down to the bare minimum, just enough to include the etype and the @@ -493,7 +477,7 @@ Then create your test by adding a new function at the end of ``ftest.py``: def testNxpImx8Image(self): """Test that binman can produce an iMX8 image""" - self._DoTestFile('339_nxp_imx8.dts') + self._DoTestFile('vendor/nxp_imx8.dts') This uses the test file that you created. It doesn't check anything, it just runs the image description through binman. @@ -517,7 +501,7 @@ The next step is to update it to actually check the output: def testNxpImx8Image(self): """Test that binman can produce an iMX8 image""" - data = self._DoReadFile('339_nxp_imx8.dts') + data = self._DoReadFile('vendor/nxp_imx8.dts') print('data', len(data)) The ``_DoReadFile()`` function is documented in the code. It returns the image @@ -573,7 +557,7 @@ In the above example, here are some possible steps: def testNxpImx8ImageMkimageMissing(self): """Test that binman can produce an iMX8 image""" with terminal.capture() as (_, stderr): - self._DoTestFile('339_nxp_imx8.dts', + self._DoTestFile('vendor/nxp_imx8.dts', force_missing_bintools='mkimage') err = stderr.getvalue() self.assertRegex(err, "Image 'image'.*missing bintools.*: mkimage") @@ -610,7 +594,7 @@ In the above example, here are some possible steps: Entry_section.SetImagePos(self, image_pos) - The solution is to add an entry, e.g. in ``340_nxp_imx8_non_empty.dts``: + The solution is to add an entry, e.g. in ``vendor/nxp_imx8_non_empty.dts``: .. code-block:: devicetree @@ -641,7 +625,7 @@ In the above example, here are some possible steps: def testNxpImx8ImageNonEmpty(self): """Test that binman can produce an iMX8 image with something in it""" - data = self._DoReadFile('340_nxp_imx8_non_empty.dts') + data = self._DoReadFile('vendor/nxp_imx8_non_empty.dts') # check data here With that, the second red bit goes away, because the for() loop is now used. diff --git a/doc/develop/uefi/fwu_updates.rst b/doc/develop/uefi/fwu_updates.rst index 84713581459..c592106f8a8 100644 --- a/doc/develop/uefi/fwu_updates.rst +++ b/doc/develop/uefi/fwu_updates.rst @@ -66,7 +66,9 @@ FWU Metadata U-Boot supports both versions(1 and 2) of the FWU metadata defined in the two revisions of the specification. Support can be enabled for either of the two versions through a config flag. The mkfwumdata tool -can generate metadata for both the supported versions. +can generate metadata for both the supported versions. On the target side, +the fwumdata tool can read and update FWU metadata located in memory, +similarly to how fw_printenv/fw_setenv works. Setting up the device for GPT partitioned storage ------------------------------------------------- diff --git a/doc/fwumdata.1 b/doc/fwumdata.1 new file mode 100644 index 00000000000..66a53fc9403 --- /dev/null +++ b/doc/fwumdata.1 @@ -0,0 +1,222 @@ +.\" SPDX-License-Identifier: GPL-2.0-or-later +.\" Copyright (C) 2025 Kory Maincent +.TH FWUMDATA 1 2025 U-Boot +.SH NAME +fwumdata \- read, display, and modify FWU metadata +. +.SH SYNOPSIS +.SY fwumdata +.OP \-c config +.OP \-l +.OP \-u +.OP \-a bankid +.OP \-p bankid +.RB [ \-s +.IR bankid " " state ] +.OP \-i imageid +.OP \-b bankid +.OP \-A +.OP \-C +.OP \-B num_banks +.OP \-I num_images +.YS +.SY fwumdata +.B \-h +.YS +. +.SH DESCRIPTION +.B fwumdata +reads, displays, and modifies FWU (Firmware Update) metadata from Linux +userspace. +.PP +The tool operates on FWU metadata stored on block or MTD devices, allowing +userspace manipulation of firmware update state including active bank +selection, image acceptance, and bank state management. +. +.SH OPTIONS +.TP +.BR \-c ", " \-\-config " \fIfile\fR" +Use custom configuration file. By default, the tool searches for +.I ./fwumdata.config +then +.IR /etc/fwumdata.config . +. +.TP +.BR \-l ", " \-\-list +Display detailed metadata information including all GUIDs, image entries, +and bank information. Without this option, only a summary is shown. +. +.TP +.BR \-u ", " \-\-update +Update metadata if CRC validation fails. Useful for recovering from corrupted +metadata. +. +.TP +.BR \-a ", " \-\-active " \fIbankid\fR" +Set the active bank index to +.IR bank . +. +.TP +.BR \-p ", " \-\-previous " \fIbankid\fR" +Set the previous active bank index to +.IR bank . +. +.TP +.BR \-s ", " \-\-state " \fIbankid state\fR" +Set bank index +.I bankid +to the specified +.IR state . +Valid states are: +.BR accepted , +.BR valid , +or +.BR invalid . +Supported only with version 2 metadata. When setting a bank to accepted state, +all firmware images in that bank are automatically marked as accepted. +. +.TP +.BR \-i ", " \-\-image " \fIimageid\fR" +Specify image number (used with +.B \-A +or +.BR \-C ). +. +.TP +.BR \-b ", " \-\-bank " \fIbankid\fR" +Specify bank number (used with +.B \-A +or +.BR \-C ). +. +.TP +.BR \-A ", " \-\-accept +Accept the image specified by +.B \-i +in the bank specified by +.BR \-b . +Sets the FWU_IMAGE_ACCEPTED flag for the image. +. +.TP +.BR \-C ", " \-\-clear +Clear the acceptance flag for the image specified by +.B \-i +in the bank specified by +.BR \-b . +According to the FWU specification, the bank state is automatically set to +invalid before clearing the acceptance flag. +. +.TP +.BR \-B ", " \-\-nbanks " \fInum_banks\fR" +Specify total number of banks (required for V1 metadata). +. +.TP +.BR \-I ", " \-\-nimages " \fInum_images\fR" +Specify total number of images (required for V1 metadata). +. +.TP +.BR \-h ", " \-\-help +Print usage information and exit. +. +.SH CONFIGURATION FILE +The configuration file specifies the location of FWU metadata on storage +devices. The format is: +.PP +.EX +.in +4 +# Device Name Device Offset Metadata Size Erase Size +/dev/mtd0 0x0 0x78 0x1000 +/dev/mtd1 0x0 0x78 0x1000 +.in +.EE +.PP +Lines starting with +.B # +are comments. +.I Erase Size +is optional and only applies to MTD devices; if omitted, it defaults to the +metadata size. +.PP +Specifying two devices enables redundant metadata support. +. +.SH BUGS +Please report bugs to the +.UR https://\:source\:.denx\:.de/\:u-boot/\:u-boot/\:issues +U-Boot bug tracker +.UE . +. +.SH EXAMPLES +Display FWU metadata summary: +.PP +.EX +.in +4 +$ \c +.B fwumdata +.in +.EE +.PP +Display detailed metadata with all GUIDs: +.PP +.EX +.in +4 +$ \c +.B fwumdata \-l +.in +.EE +.PP +Set active bank to 1: +.PP +.EX +.in +4 +$ \c +.B fwumdata \-a 1 +.in +.EE +.PP +Set bank 1 to accepted state (automatically accepts all images in that bank): +.PP +.EX +.in +4 +$ \c +.B fwumdata \-s 1 accepted +.in +.EE +.PP +Accept image 0 in bank 0: +.PP +.EX +.in +4 +$ \c +.B fwumdata \-i 0 \-b 0 \-A \-l +.in +.EE +.PP +Clear acceptance for image 0 in bank 1: +.PP +.EX +.in +4 +$ \c +.B fwumdata \-i 0 \-b 1 \-C \-l +.in +.EE +.PP +Clear acceptance for image 1 in bank 1 with metadata V1: +.PP +.EX +.in +4 +$ \c +.B fwumdata \-B 2 \-I 2 \-i 1 \-b 1 \-C \-l +.in +.EE +.PP +Use custom configuration file: +.PP +.EX +.in +4 +$ \c +.B fwumdata \-c /path/to/custom.config +.in +.EE +. +.SH SEE ALSO +.BR mkfwumdata (1) diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 index a726149ba2c..d6653ec4247 100644 --- a/doc/mkeficapsule.1 +++ b/doc/mkeficapsule.1 @@ -121,8 +121,8 @@ Specify a monotonic count which is set to be monotonically incremented at every firmware update. .TP -.B "-d\fR,\fB --dump_sig" -Dump signature data into *.p7 file +.B "-d\fR,\fB --dump-sig" +Dump signature data into .p7 file .SH "GUIDGEN OPTIONS" diff --git a/doc/usage/cmd/test.rst b/doc/usage/cmd/test.rst index d1379117fca..037a9ee1774 100644 --- a/doc/usage/cmd/test.rst +++ b/doc/usage/cmd/test.rst @@ -20,11 +20,14 @@ Synopsis test -e test =~ + [ ] + Description ----------- The ``test`` command is similar to the ordinary shell built-in by the -same name. Unlike in ordinary shells, it cannot be spelled ``[``. +same name. Like in ordinary shells, it can also be spelled ``[``, +provided the test expression is followed by a separate ``]`` argument. Strings ~~~~~~~ diff --git a/drivers/Makefile b/drivers/Makefile index de993ae42ac..43d0ba33281 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ +obj-$(CONFIG_SPL_UFS_SUPPORT) += scsi/ ufs/ endif endif diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 461b5a9fc83..adf338ab00c 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -106,8 +106,9 @@ config EFI_MEDIA For sandbox there is a test driver. config SPL_BLK_FS - bool "Load images from filesystems on block devices" - depends on SPL_BLK && SPL_FS_LOADER + bool + depends on SPL_BLK + select SPL_FS_LOADER help Use generic support to load images from fat/ext filesystems on different types of block devices such as NVMe. diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 9cb27561a97..4b3de0529ce 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -10,13 +10,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static unsigned long host_block_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *buffer) diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index 343b8a34414..2c0114d9705 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -19,7 +19,8 @@ __weak void bootcount_store(ulong a) uintptr_t flush_end; #if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) - raw_bootcount_store(reg, (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | a); + raw_bootcount_store(reg, (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) + | (a & BOOTCOUNT_COUNT_MASK)); flush_end = roundup(CONFIG_SYS_BOOTCOUNT_ADDR + 4, CONFIG_SYS_CACHELINE_SIZE); @@ -40,10 +41,10 @@ __weak ulong bootcount_load(void) #if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) u32 tmp = raw_bootcount_load(reg); - if ((tmp & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((tmp & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return (tmp & 0x0000ffff); + return (tmp & BOOTCOUNT_COUNT_MASK); #else if (raw_bootcount_load(reg + 4) != CONFIG_SYS_BOOTCOUNT_MAGIC) return 0; @@ -74,10 +75,10 @@ static int bootcount_mem_get(struct udevice *dev, u32 *a) if (priv->singleword) { u32 tmp = raw_bootcount_load(reg); - if ((tmp & 0xffff0000) != (magic & 0xffff0000)) + if ((tmp & BOOTCOUNT_MAGIC_MASK) != (magic & BOOTCOUNT_MAGIC_MASK)) return -ENODEV; - *a = (tmp & 0x0000ffff); + *a = (tmp & BOOTCOUNT_COUNT_MASK); } else { if (raw_bootcount_load(reg + 4) != magic) return -ENODEV; @@ -98,7 +99,8 @@ static int bootcount_mem_set(struct udevice *dev, const u32 a) uintptr_t flush_end; if (priv->singleword) { - raw_bootcount_store(reg, (magic & 0xffff0000) | a); + raw_bootcount_store(reg, (magic & BOOTCOUNT_MAGIC_MASK) + | (a & BOOTCOUNT_COUNT_MASK)); flush_end = roundup(priv->base + 4, CONFIG_SYS_CACHELINE_SIZE); } else { diff --git a/drivers/bootcount/bootcount_at91.c b/drivers/bootcount/bootcount_at91.c index 1a06db1fb74..1322abe921e 100644 --- a/drivers/bootcount/bootcount_at91.c +++ b/drivers/bootcount/bootcount_at91.c @@ -3,6 +3,7 @@ #include #include #include +#include /* * We combine the CONFIG_SYS_BOOTCOUNT_MAGIC and bootcount in one 32-bit @@ -13,7 +14,7 @@ void bootcount_store(ulong a) { at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - writel((CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff), + writel((CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) | (a & BOOTCOUNT_COUNT_MASK), &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); } @@ -22,8 +23,8 @@ ulong bootcount_load(void) at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); - if ((val & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((val & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return val & 0x0000ffff; + return val & BOOTCOUNT_COUNT_MASK; } diff --git a/drivers/bootcount/bootcount_davinci.c b/drivers/bootcount/bootcount_davinci.c index 6326957d7b0..a03d160a4cd 100644 --- a/drivers/bootcount/bootcount_davinci.c +++ b/drivers/bootcount/bootcount_davinci.c @@ -24,7 +24,7 @@ void bootcount_store(ulong a) writel(RTC_KICK0R_WE, ®->kick0r); writel(RTC_KICK1R_WE, ®->kick1r); raw_bootcount_store(®->scratch2, - (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff)); + (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) | (a & BOOTCOUNT_COUNT_MASK)); } ulong bootcount_load(void) @@ -34,8 +34,8 @@ ulong bootcount_load(void) (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; val = raw_bootcount_load(®->scratch2); - if ((val & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((val & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return val & 0x0000ffff; + return val & BOOTCOUNT_COUNT_MASK; } diff --git a/drivers/bootcount/bootcount_dm_i2c.c b/drivers/bootcount/bootcount_dm_i2c.c index e27034cbeb0..07359ecfa6c 100644 --- a/drivers/bootcount/bootcount_dm_i2c.c +++ b/drivers/bootcount/bootcount_dm_i2c.c @@ -15,6 +15,7 @@ struct bootcount_i2c_priv { struct udevice *bcdev; unsigned int offset; + unsigned int size; }; static int bootcount_i2c_set(struct udevice *dev, const u32 val) @@ -22,13 +23,22 @@ static int bootcount_i2c_set(struct udevice *dev, const u32 val) int ret; struct bootcount_i2c_priv *priv = dev_get_priv(dev); - ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC); - if (ret < 0) - goto err_exit; + if (priv->size == 4) { + u32 bc = (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) + | (val & BOOTCOUNT_COUNT_MASK); - ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff); - if (ret < 0) - goto err_exit; + ret = dm_i2c_write(priv->bcdev, priv->offset, (uint8_t *)&bc, sizeof(bc)); + if (ret < 0) + goto err_exit; + } else { + ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC); + if (ret < 0) + goto err_exit; + + ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff); + if (ret < 0) + goto err_exit; + } return 0; @@ -42,21 +52,39 @@ static int bootcount_i2c_get(struct udevice *dev, u32 *val) int ret; struct bootcount_i2c_priv *priv = dev_get_priv(dev); - ret = dm_i2c_reg_read(priv->bcdev, priv->offset); - if (ret < 0) - goto err_exit; + if (priv->size == 4) { + u32 bc; - if ((ret & 0xff) != BC_MAGIC) { - log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__); - *val = 0; - return bootcount_i2c_set(dev, 0); + ret = dm_i2c_read(priv->bcdev, priv->offset, (uint8_t *)&bc, sizeof(bc)); + if (ret < 0) + goto err_exit; + + if ((bc & BOOTCOUNT_MAGIC_MASK) != + (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) { + log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__); + *val = 0; + return bootcount_i2c_set(dev, 0); + } + + *val = (bc & BOOTCOUNT_COUNT_MASK); + } else { + ret = dm_i2c_reg_read(priv->bcdev, priv->offset); + if (ret < 0) + goto err_exit; + + if ((ret & 0xff) != BC_MAGIC) { + log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__); + *val = 0; + return bootcount_i2c_set(dev, 0); + } + + ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1); + if (ret < 0) + goto err_exit; + + *val = ret; } - ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1); - if (ret < 0) - goto err_exit; - - *val = ret; return 0; err_exit: @@ -73,6 +101,12 @@ static int bootcount_i2c_probe(struct udevice *dev) if (ret) goto exit; + priv->size = dev_read_u32_default(dev, "size", 2); + if (priv->size != 2 && priv->size != 4) { + ret = -EINVAL; + goto exit; + } + ret = i2c_get_chip_by_phandle(dev, "i2cbcdev", &priv->bcdev); exit: diff --git a/drivers/bootcount/i2c-eeprom.c b/drivers/bootcount/i2c-eeprom.c index 12c430465c9..f54515f451e 100644 --- a/drivers/bootcount/i2c-eeprom.c +++ b/drivers/bootcount/i2c-eeprom.c @@ -85,7 +85,7 @@ static const struct udevice_id bootcount_i2c_eeprom_ids[] = { { } }; -U_BOOT_DRIVER(bootcount_spi_flash) = { +U_BOOT_DRIVER(bootcount_i2c_eeprom) = { .name = "bootcount-i2c-eeprom", .id = UCLASS_BOOTCOUNT, .priv_auto = sizeof(struct bootcount_i2c_eeprom_priv), diff --git a/drivers/bootcount/pmic_pfuze100.c b/drivers/bootcount/pmic_pfuze100.c index 8c529f5592b..dd11344322b 100644 --- a/drivers/bootcount/pmic_pfuze100.c +++ b/drivers/bootcount/pmic_pfuze100.c @@ -13,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define PFUZE_BC_MAGIC 0xdead struct bootcount_pmic_priv { diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index f5bcd406a50..3bf5c7f5dbf 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -46,11 +46,5 @@ config SIFIVE_CCACHE This driver is for SiFive Composable L2/L3 cache. It enables cache ways of composable cache. -config SIFIVE_PL2 - bool "SiFive private L2 cache" - select CACHE - help - This driver is for SiFive Private L2 cache. It configures registers - to enable the clock gating feature. endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 2f683866b87..05ad7d8a33e 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -5,4 +5,3 @@ obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o -obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c index 375892fafb0..b27960f1bfa 100644 --- a/drivers/cache/sandbox_cache.c +++ b/drivers/cache/sandbox_cache.c @@ -6,9 +6,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int sandbox_get_info(struct udevice *dev, struct cache_info *info) { diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c88931c8ec4..c2da7b3938b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -185,6 +185,7 @@ config SANDBOX_CLK_CCF bool "Sandbox Common Clock Framework [CCF] support" depends on SANDBOX select CLK_CCF + select CLK_COMPOSITE_CCF help Enable this option if you want to test the Linux kernel's Common Clock Framework [CCF] code in U-Boot's Sandbox clock driver. diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 858f828e537..693446b3d89 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -3,9 +3,9 @@ # Copyright (C) 2018-2021 Marek Vasut # -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index fdbf834bb2f..b793dbf6a42 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_clk_plat { void __iomem *regs; int pllgrp; @@ -657,6 +654,7 @@ static int bitmask_from_clk_id(struct clk *clk) plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK; break; case AGILEX_L4_MP_CLK: + case AGILEX_NAND_X_CLK: plat->pllgrp = CLKMGR_MAINPLL_EN; plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK; break; @@ -728,6 +726,8 @@ static int bitmask_from_clk_id(struct clk *clk) plat->pllgrp = CLKMGR_PERPLL_EN; plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK; break; + case AGILEX_L4_SYS_FREE_CLK: + return -EOPNOTSUPP; default: return -ENXIO; } @@ -742,6 +742,9 @@ static int socfpga_clk_enable(struct clk *clk) int ret; ret = bitmask_from_clk_id(clk); + if (ret == -EOPNOTSUPP) + return 0; + if (ret) return ret; @@ -757,6 +760,9 @@ static int socfpga_clk_disable(struct clk *clk) int ret; ret = bitmask_from_clk_id(clk); + if (ret == -EOPNOTSUPP) + return 0; + if (ret) return ret; diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index fb1e72ffc5c..92b91a9dfc8 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define CLKMGR_CTRL_SWCTRLBTCLKEN_MASK BIT(8) #define CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK BIT(9) diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index b75f52d203b..ac59571a853 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -4,7 +4,6 @@ */ #include -#include #include #include "clk-mem-n5x.h" #include @@ -13,8 +12,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_mem_clk_plat { void __iomem *regs; }; diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 9e4e7a1d908..185c9028a78 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include @@ -12,8 +11,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_clk_plat { void __iomem *regs; }; diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index b69355cefc7..f57ac79f8ca 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -13,6 +13,21 @@ #include "clk.h" +#define SET_CLK_RATE(id, rate) \ + do { \ + struct clk *clk; \ + clk_get_by_id(id, &clk); \ + clk_set_rate(clk, rate); \ + } while (0) + +#define SET_CLK_PARENT(child_id, parent_id) \ + do { \ + struct clk *clk, *clk_parent; \ + clk_get_by_id(parent_id, &clk_parent); \ + clk_get_by_id(child_id, &clk); \ + clk_set_parent(clk, clk_parent); \ + } while (0) + static int imx6q_clk_request(struct clk *clk) { if (clk->id < IMX6QDL_CLK_DUMMY || clk->id >= IMX6QDL_CLK_END) { @@ -31,12 +46,72 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; -static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; -static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", - "pll2_pfd0_352m", "pll2_198m", }; -static const char *const uart_sels[] = { "pll3_80m", "osc", }; -static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; +static const char *const usdhc_sels[] = { + "pll2_pfd2_396m", + "pll2_pfd0_352m", +}; +static const char *const periph_sels[] = { + "periph_pre", + "periph_clk2", +}; +static const char *periph2_sels[] = { + "periph2_pre", + "periph2_clk2", +}; +static const char *const periph_pre_sels[] = { + "pll2_bus", + "pll2_pfd2_396m", + "pll2_pfd0_352m", + "pll2_198m", +}; +static const char *const uart_sels[] = { + "pll3_80m", + "osc", +}; +static const char *const ecspi_sels[] = { + "pll3_60m", + "osc", +}; +static const char *const ipu_sels[] = { + "mmdc_ch0_axi", + "pll2_pfd2_396m", + "pll3_120m", + "pll3_pfd1_540m", +}; +static const char *const ldb_di_sels[] = { + "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", + "mmdc_ch1_axi", "pll3_usb_otg", +}; +static const char *const ipu_di_pre_sels[] = { + "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", + "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", +}; +static const char *const ipu1_di0_sels[] = { + "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *const ipu1_di1_sels[] = { + "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *const ipu2_di0_sels[] = { + "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *const ipu2_di1_sels[] = { + "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", +}; +static const char *ipu1_di0_sels_2[] = { + "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; +static const char *ipu1_di1_sels_2[] = { + "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; +static const char *ipu2_di0_sels_2[] = { + "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; +static const char *ipu2_di1_sels_2[] = { + "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", +}; + +static unsigned int share_count_mipi_core_cfg; static int imx6q_clk_probe(struct udevice *dev) { @@ -52,15 +127,37 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL3_60M, - imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); + imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); + clk_dm(IMX6QDL_CLK_PLL3_80M, + imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); + clk_dm(IMX6QDL_CLK_PLL3_120M, + imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); + clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", + base + 0xa0, 0x7f)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO, + imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); - clk_dm(IMX6QDL_CLK_PLL6, - imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); - clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL3_PFD1_540M, + imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1)); + + clk_dm(IMX6QDL_CLK_PLL2_198M, + imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2)); + clk_dm(IMX6QDL_CLK_PLL5_POST_DIV, + imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV, + imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1, + 1)); + clk_dm(IMX6QDL_CLK_VIDEO_27M, + imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1, + 20)); /* CCM clocks */ base = dev_read_addr_ptr(dev); @@ -68,50 +165,253 @@ static int imx6q_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX6QDL_CLK_USDHC1_SEL, - imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC2_SEL, - imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC3_SEL, - imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC4_SEL, - imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SEL, - imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels, - ARRAY_SIZE(uart_sels))); + imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, + uart_sels, ARRAY_SIZE(uart_sels))); clk_dm(IMX6QDL_CLK_ECSPI_SEL, - imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels, - ARRAY_SIZE(ecspi_sels))); + imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, + ecspi_sels, ARRAY_SIZE(ecspi_sels))); } + clk_dm(IMX6QDL_CLK_PERIPH_PRE, + imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, + periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); + clk_dm(IMX6QDL_CLK_PERIPH2_PRE, + imx_clk_mux(dev, "periph2_pre", base + 0x18, 21, 2, + periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); + clk_dm(IMX6QDL_CLK_PERIPH, + imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, + 5, periph_sels, ARRAY_SIZE(periph_sels))); + clk_dm(IMX6QDL_CLK_PERIPH2, + imx_clk_busy_mux(dev, "periph2", base + 0x14, 26, 1, base + 0x48, + 3, periph2_sels, ARRAY_SIZE(periph2_sels))); + clk_dm(IMX6QDL_CLK_USDHC1_PODF, - imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", - base + 0x24, 11, 3)); + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, + 11, 3)); clk_dm(IMX6QDL_CLK_USDHC2_PODF, - imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", - base + 0x24, 16, 3)); + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, + 16, 3)); clk_dm(IMX6QDL_CLK_USDHC3_PODF, - imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", - base + 0x24, 19, 3)); + imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", base + 0x24, + 19, 3)); clk_dm(IMX6QDL_CLK_USDHC4_PODF, - imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", - base + 0x24, 22, 3)); + imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", base + 0x24, + 22, 3)); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "uart_sel", + base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "ecspi_sel", + base + 0x38, 19, 6)); } else { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", + base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "pll3_60m", + base + 0x38, 19, 6)); + } + + clk_dm(IMX6QDL_CLK_AHB, + imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, + base + 0x48, 1)); + clk_dm(IMX6QDL_CLK_IPG, + imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); + clk_dm(IMX6QDL_CLK_IPG_PER, + imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6)); + clk_dm(IMX6QDL_CLK_UART_IPG, + imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24)); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_CG, + imx_clk_gate2(dev, "mmdc_ch1_axi_cg", "periph2", + base + 0x4, 18)); + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_PODF, + imx_clk_busy_divider(dev, "mmdc_ch1_axi_podf", + "mmdc_ch1_axi_cg", base + 0x14, 3, + 3, base + 0x48, 2)); + } else { + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_PODF, + imx_clk_busy_divider(dev, "mmdc_ch1_axi_podf", "periph2", + base + 0x14, 3, 3, base + 0x48, 2)); + } + + clk_dm(IMX6QDL_CLK_MMDC_CH0_AXI_PODF, + imx_clk_busy_divider(dev, "mmdc_ch0_axi_podf", "periph", + base + 0x14, 19, 3, base + 0x48, 4)); + + clk_dm(IMX6QDL_CLK_MMDC_CH0_AXI, + imx_clk_gate2_flags(dev, "mmdc_ch0_axi", "mmdc_ch0_axi_podf", + base + 0x74, 20, CLK_IS_CRITICAL)); + clk_dm(IMX6QDL_CLK_MMDC_CH1_AXI, + imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf", + base + 0x74, 22)); + + clk_dm(IMX6QDL_CLK_IPU1_SEL, + imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels, + ARRAY_SIZE(ipu_sels))); + clk_dm(IMX6QDL_CLK_IPU2_SEL, + imx_clk_mux(dev, "ipu2_sel", base + 0x3c, 14, 2, ipu_sels, + ARRAY_SIZE(ipu_sels))); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, + imx_clk_mux(dev, "ldb_di0_sel", base + 0x2c, 9, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); + clk_dm(IMX6QDL_CLK_LDB_DI1_SEL, + imx_clk_mux(dev, "ldb_di1_sel", base + 0x2c, 12, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); + } else { + /* + * Need to set these as read-only due to a hardware bug. + * Keeping default mux values. Fixed on the i.MX6 QuadPlus + */ + clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, + imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels), + CLK_SET_RATE_PARENT | + CLK_MUX_READ_ONLY)); + clk_dm(IMX6QDL_CLK_LDB_DI1_SEL, + imx_clk_mux_flags(dev, "ldb_di1_sel", base + 0x2c, 12, 3, + ldb_di_sels, ARRAY_SIZE(ldb_di_sels), + CLK_SET_RATE_PARENT | + CLK_MUX_READ_ONLY)); + } + + clk_dm(IMX6QDL_CLK_IPU1_DI0_PRE_SEL, + imx_clk_mux_flags(dev, "ipu1_di0_pre_sel", base + 0x34, 6, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_PRE_SEL, + imx_clk_mux_flags(dev, "ipu1_di1_pre_sel", base + 0x34, 15, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_PRE_SEL, + imx_clk_mux_flags(dev, "ipu2_di0_pre_sel", base + 0x38, 6, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_PRE_SEL, + imx_clk_mux_flags(dev, "ipu2_di1_pre_sel", base + 0x38, 15, 3, + ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), + CLK_SET_RATE_PARENT)); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_LDB_DI0, + imx_clk_gate2(dev, "ldb_di0", "ldb_di0_sel", base + 0x74, + 12)); + clk_dm(IMX6QDL_CLK_LDB_DI1, + imx_clk_gate2(dev, "ldb_di1", "ldb_di1_sel", base + 0x74, + 14)); + clk_dm(IMX6QDL_CLK_LDB_DI0_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di0_div_3_5", "ldb_di0", + 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI1_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di1_div_3_5", "ldb_di1", + 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI0_PODF, + imx_clk_divider(dev, "ldb_di0_podf", "ldb_di0_div_3_5", + base + 0x20, 10, 1)); + clk_dm(IMX6QDL_CLK_LDB_DI1_PODF, + imx_clk_divider(dev, "ldb_di1_podf", "ldb_di1_div_3_5", + base + 0x20, 11, 1)); + } else { + clk_dm(IMX6QDL_CLK_LDB_DI0_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di0_div_3_5", + "ldb_di0_sel", 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI1_DIV_3_5, + imx_clk_fixed_factor(dev, "ldb_di1_div_3_5", + "ldb_di1_sel", 2, 7)); + clk_dm(IMX6QDL_CLK_LDB_DI0_PODF, + imx_clk_divider(dev, "ldb_di0_podf", "ldb_di0_div_3_5", + base + 0x20, 10, 1)); + clk_dm(IMX6QDL_CLK_LDB_DI1_PODF, + imx_clk_divider(dev, "ldb_di1_podf", "ldb_di1_div_3_5", + base + 0x20, 11, 1)); + clk_dm(IMX6QDL_CLK_LDB_DI0, + imx_clk_gate2(dev, "ldb_di0", "ldb_di0_podf", + base + 0x74, 12)); + clk_dm(IMX6QDL_CLK_LDB_DI1, + imx_clk_gate2(dev, "ldb_di1", "ldb_di1_podf", + base + 0x74, 14)); + } + + clk_dm(IMX6QDL_CLK_IPU1_PODF, + imx_clk_divider(dev, "ipu1_podf", "ipu1_sel", base + 0x3c, 11, + 3)); + clk_dm(IMX6QDL_CLK_IPU2_PODF, + imx_clk_divider(dev, "ipu2_podf", "ipu2_sel", base + 0x3c, 16, + 3)); + clk_dm(IMX6QDL_CLK_IPU1_DI0_PRE, + imx_clk_divider(dev, "ipu1_di0_pre", "ipu1_di0_pre_sel", + base + 0x34, 3, 3)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_PRE, + imx_clk_divider(dev, "ipu1_di1_pre", "ipu1_di1_pre_sel", + base + 0x34, 12, 3)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_PRE, + imx_clk_divider(dev, "ipu2_di0_pre", "ipu2_di0_pre_sel", + base + 0x38, 3, 3)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_PRE, + imx_clk_divider(dev, "ipu2_di1_pre", "ipu2_di1_pre_sel", + base + 0x38, 12, 3)); + + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_IPU1_DI0_SEL, + imx_clk_mux_flags(dev, "ipu1_di0_sel", base + 0x34, 0, 3, + ipu1_di0_sels_2, + ARRAY_SIZE(ipu1_di0_sels_2), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_SEL, + imx_clk_mux_flags(dev, "ipu1_di1_sel", base + 0x34, 9, 3, + ipu1_di1_sels_2, + ARRAY_SIZE(ipu1_di1_sels_2), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_SEL, + imx_clk_mux_flags(dev, "ipu2_di0_sel", base + 0x38, 0, 3, + ipu2_di0_sels_2, + ARRAY_SIZE(ipu2_di0_sels_2), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_SEL, + imx_clk_mux_flags(dev, "ipu2_di1_sel", base + 0x38, 9, 3, + ipu2_di1_sels_2, + ARRAY_SIZE(ipu2_di1_sels_2), + CLK_SET_RATE_PARENT)); + } else { + clk_dm(IMX6QDL_CLK_IPU1_DI0_SEL, + imx_clk_mux_flags(dev, "ipu1_di0_sel", base + 0x34, 0, 3, + ipu1_di0_sels, + ARRAY_SIZE(ipu1_di0_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU1_DI1_SEL, + imx_clk_mux_flags(dev, "ipu1_di1_sel", base + 0x34, 9, 3, + ipu1_di1_sels, + ARRAY_SIZE(ipu1_di1_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI0_SEL, + imx_clk_mux_flags(dev, "ipu2_di0_sel", base + 0x38, 0, 3, + ipu2_di0_sels, + ARRAY_SIZE(ipu2_di0_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_CLK_IPU2_DI1_SEL, + imx_clk_mux_flags(dev, "ipu2_di1_sel", base + 0x38, 9, 3, + ipu2_di1_sels, + ARRAY_SIZE(ipu2_di1_sels), + CLK_SET_RATE_PARENT)); } clk_dm(IMX6QDL_CLK_ECSPI1, @@ -122,10 +422,11 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "ecspi3", "ecspi_root", base + 0x6c, 4)); clk_dm(IMX6QDL_CLK_ECSPI4, imx_clk_gate2(dev, "ecspi4", "ecspi_root", base + 0x6c, 6)); - clk_dm(IMX6QDL_CLK_UART_IPG, - imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24)); clk_dm(IMX6QDL_CLK_UART_SERIAL, - imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", base + 0x7c, 26)); + imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", + base + 0x7c, 26)); + clk_dm(IMX6QDL_CLK_USBOH3, + imx_clk_gate2(dev, "usboh3", "ipg", base + 0x80, 0)); clk_dm(IMX6QDL_CLK_USDHC1, imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMX6QDL_CLK_USDHC2, @@ -134,20 +435,6 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "usdhc3", "usdhc3_podf", base + 0x80, 6)); clk_dm(IMX6QDL_CLK_USDHC4, imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8)); - - clk_dm(IMX6QDL_CLK_PERIPH_PRE, - imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels, - ARRAY_SIZE(periph_pre_sels))); - clk_dm(IMX6QDL_CLK_PERIPH, - imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, - 5, periph_sels, ARRAY_SIZE(periph_sels))); - clk_dm(IMX6QDL_CLK_AHB, - imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, - base + 0x48, 1)); - clk_dm(IMX6QDL_CLK_IPG, - imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); - clk_dm(IMX6QDL_CLK_IPG_PER, - imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6)); clk_dm(IMX6QDL_CLK_I2C1, imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6)); clk_dm(IMX6QDL_CLK_I2C2, @@ -162,17 +449,44 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "pwm3", "ipg_per", base + 0x78, 20)); clk_dm(IMX6QDL_CLK_PWM4, imx_clk_gate2(dev, "pwm4", "ipg_per", base + 0x78, 22)); - - clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6QDL_CLK_ENET, + imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG, + imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m", + base + 0x74, 16, + &share_count_mipi_core_cfg)); + clk_dm(IMX6QDL_CLK_HDMI_IAHB, + imx_clk_gate2(dev, "hdmi_iahb", "ahb", base + 0x70, 0)); + clk_dm(IMX6QDL_CLK_HDMI_ISFR, + imx_clk_gate2(dev, "hdmi_isfr", "mipi_core_cfg", base + 0x70, + 4)); + clk_dm(IMX6QDL_CLK_IPU1, + imx_clk_gate2(dev, "ipu1", "ipu1_podf", base + 0x74, 0)); + clk_dm(IMX6QDL_CLK_IPU2, + imx_clk_gate2(dev, "ipu2", "ipu2_podf", base + 0x74, 6)); + clk_dm(IMX6QDL_CLK_IPU1_DI0, + imx_clk_gate2(dev, "ipu1_di0", "ipu1_di0_sel", base + 0x74, 2)); + clk_dm(IMX6QDL_CLK_IPU1_DI1, + imx_clk_gate2(dev, "ipu1_di1", "ipu1_di1_sel", base + 0x74, 4)); + clk_dm(IMX6QDL_CLK_IPU2_DI0, + imx_clk_gate2(dev, "ipu2_di0", "ipu2_di0_sel", base + 0x74, 8)); + clk_dm(IMX6QDL_CLK_IPU2_DI1, + imx_clk_gate2(dev, "ipu2_di1", "ipu2_di1_sel", base + 0x74, 10)); + + if (of_machine_is_compatible("fsl,imx6dl")) { + SET_CLK_RATE(IMX6QDL_CLK_PLL3_PFD1_540M, 540000000UL); + SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL, + IMX6QDL_CLK_PLL3_PFD1_540M); + } return 0; } static const struct udevice_id imx6q_clk_ids[] = { { .compatible = "fsl,imx6q-ccm" }, - { }, + {}, }; U_BOOT_DRIVER(imx6q_clk) = { diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 7d14dbc395f..b53f35df84f 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -95,6 +95,15 @@ static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name, shift, 0x3, 0, NULL); } +static inline struct clk * +imx_clk_gate2_flags(struct udevice *dev, const char *name, const char *parent, + void __iomem *reg, u8 shift, unsigned long flags) +{ + return clk_register_gate2(dev, name, parent, + flags | CLK_SET_RATE_PARENT, reg, shift, 0x3, + 0, NULL); +} + static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name, const char *parent, void __iomem *reg, u8 shift, diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 68b3d6e9610..d4cac6aaf52 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -12,6 +12,8 @@ obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8188) += clk-mt8188.o +obj-$(CONFIG_TARGET_MT8189) += clk-mt8189.o +obj-$(CONFIG_TARGET_MT8195) += clk-mt8195.o obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index f73bd254579..79315912fd4 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -28,6 +28,14 @@ #define MCU_BUS_MSK GENMASK(10, 9) #define MCU_BUS_SEL(x) ((x) << 9) +enum { + CLK_PAD_CLK25M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK25M] = 25 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -48,9 +56,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR, 21, 0x214, 24, 0x214, 0), - PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR, 7, 0x224, 24, 0x224, 14), PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 21, 0x300, 1, 0x304, 0), @@ -86,7 +94,7 @@ static const struct mtk_gate apmixed_cgs[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK25M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -95,7 +103,7 @@ static const struct mtk_gate apmixed_cgs[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -116,8 +124,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), - FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), - FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK25M, 1, 1024), + FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK25M, 32, 1), FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), @@ -159,173 +167,173 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent ddrphycfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int eth_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - -1, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent eth_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int f10m_ref_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL4_D16 +static const struct mtk_parent f10m_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; -static const int nfi_infra_parents[] = { - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D4 +static const struct mtk_parent nfi_infra_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; -static const int flash_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D80_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent flash_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi0_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int spi1_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int msdc30_0_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M +static const struct mtk_parent msdc30_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), }; -static const int a1sys_hp_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL, - CLK_TOP_AUD2PLL, - CLK_XTAL +static const struct mtk_parent a1sys_hp_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_AUD1PLL), + TOP_PARENT(CLK_TOP_AUD2PLL), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int intdir_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_SGMIIPLL +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_SGMIIPLL), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL3_D2 +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), }; -static const int pmicspi_parents[] = { - CLK_XTAL, - -1, - -1, - -1, - -1, - CLK_TOP_UNIVPLL2_D16 +static const struct mtk_parent pmicspi_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + VOID_PARENT, + VOID_PARENT, + VOID_PARENT, + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), }; -static const int atb_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int audio_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_UNIVPLL1_D16 +static const struct mtk_parent audio_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D16), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_XTAL +static const struct mtk_parent usb20_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + EXT_PARENT(CLK_PAD_CLK25M), }; -static const int aud1_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL +static const struct mtk_parent aud1_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_AUD1PLL), }; -static const int asm_l_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent asm_l_parents[] = { + EXT_PARENT(CLK_PAD_CLK25M), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int apll1_ck_parents[] = { - CLK_TOP_AUD1_SEL, - CLK_TOP_AUD2_SEL +static const struct mtk_parent apll1_ck_parents[] = { + TOP_PARENT(CLK_TOP_AUD1_SEL), + TOP_PARENT(CLK_TOP_AUD2_SEL), }; static const struct mtk_composite top_muxes[] = { @@ -361,8 +369,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_5 */ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), @@ -387,18 +394,16 @@ static const struct mtk_composite top_muxes[] = { }; /* infracfg */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) static const struct mtk_parent infra_mux1_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK25M), APMIXED_PARENT(CLK_APMIXED_MAINPLL), APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN), APMIXED_PARENT(CLK_APMIXED_MAINPLL), }; static const struct mtk_composite infra_muxes[] = { - MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), + MUX(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), }; static const struct mtk_gate_regs infra_cg_regs = { @@ -425,16 +430,13 @@ static const struct mtk_gate infra_cgs[] = { }; /* pericfg */ -static const int peribus_ck_parents[] = { - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL1_D4, +static const struct mtk_parent peribus_ck_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; -#define PERI_MUX(_id, _parents, _reg, _shift, _width) \ - MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN) - static const struct mtk_composite peri_muxes[] = { - PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), + MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), }; static const struct mtk_gate_regs peri0_cg_regs = { @@ -458,8 +460,8 @@ static const struct mtk_gate_regs peri1_cg_regs = { } #define GATE_PERI0(_id, _parent, _shift) \ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_PERI0_XTAL(_id, _parent, _shift) \ - GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_PERI0_EXT(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -472,14 +474,14 @@ static const struct mtk_gate_regs peri1_cg_regs = { static const struct mtk_gate peri_cgs[] = { /* PERI0 */ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), - GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2), - GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3), - GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4), - GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5), - GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6), - GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7), - GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8), - GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0_EXT(CLK_PERI_PWM1_PD, CLK_PAD_CLK25M, 2), + GATE_PERI0_EXT(CLK_PERI_PWM2_PD, CLK_PAD_CLK25M, 3), + GATE_PERI0_EXT(CLK_PERI_PWM3_PD, CLK_PAD_CLK25M, 4), + GATE_PERI0_EXT(CLK_PERI_PWM4_PD, CLK_PAD_CLK25M, 5), + GATE_PERI0_EXT(CLK_PERI_PWM5_PD, CLK_PAD_CLK25M, 6), + GATE_PERI0_EXT(CLK_PERI_PWM6_PD, CLK_PAD_CLK25M, 7), + GATE_PERI0_EXT(CLK_PERI_PWM7_PD, CLK_PAD_CLK25M, 8), + GATE_PERI0_EXT(CLK_PERI_PWM_PD, CLK_PAD_CLK25M, 9), GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), @@ -493,7 +495,7 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), - GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0_EXT(CLK_PERI_AUXADC_PD, CLK_PAD_CLK25M, 27), GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), @@ -603,7 +605,9 @@ static const struct mtk_gate ssusb_cgs[] = { }; static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { - .xtal2_rate = 25 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK25M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .gates_offs = CLK_APMIXED_MAIN_CORE_EN, .gates = apmixed_cgs, @@ -612,7 +616,8 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { }; static const struct mtk_clk_tree mt7622_infra_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX1_SEL, .gates_offs = CLK_INFRA_DBGCLK_PD, .muxes = infra_muxes, @@ -622,7 +627,8 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = { }; static const struct mtk_clk_tree mt7622_peri_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_PERIBUS_SEL, .gates_offs = CLK_PERI_THERM_PD, .muxes = peri_muxes, @@ -632,7 +638,8 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = { }; static const struct mtk_clk_tree mt7622_clk_tree = { - .xtal_rate = 25 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .fclks = top_fixed_clks, diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 071c4cf8a84..0a302b405e2 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -24,6 +24,14 @@ #define AXI_DIV_MSK GENMASK(4, 0) #define AXI_DIV_SEL(x) (x) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ static const int pll_id_offs_map[] = { [0 ... CLK_APMIXED_NR - 1] = -1, @@ -61,9 +69,9 @@ static const int pll_id_offs_map[] = { static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, CLK_PLL_HAVE_RST_BAR, 21, 0x210, 4, 0x214, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, CLK_PLL_HAVE_RST_BAR, 7, 0x220, 4, 0x224, 14), PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0, 21, 0x230, 4, 0x234, 0), @@ -260,7 +268,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -269,7 +277,7 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_DPI, 108 * MHZ), @@ -369,344 +377,342 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3), FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1), FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), - FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793), + FACTOR2(CLK_TOP_CLK26M_D8, CLK_PAD_CLK26M, 1, 8), + FACTOR2(CLK_TOP_32K_INTERNAL, CLK_PAD_CLK26M, 1, 793), FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4), FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_MMPLL_D2, - CLK_TOP_DMPLL_D2 +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D2), }; -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent ddrphycfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int mm_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL +static const struct mtk_parent mm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int vdec_parents[] = { - CLK_XTAL, - CLK_TOP_VDECPLL, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_VENCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VDECPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int mfg_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_DMPLL_X2, - CLK_TOP_MSDCPLL, - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2 +static const struct mtk_parent mfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_DMPLL_X2), + TOP_PARENT(CLK_TOP_MSDCPLL), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), }; -static const int camtg_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_MMPLL_D2 +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8 +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_UNIVPLL3_D4 +static const struct mtk_parent usb20_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), }; -static const int msdc30_parents[] = { - CLK_XTAL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D4, +static const struct mtk_parent msdc30_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 +static const struct mtk_parent pmicspi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), }; -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_DMPLL_D2, - CLK_TOP_DMPLL_D4 +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_DMPLL_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), }; -static const int dpi0_tve_parents[] = { - CLK_XTAL, - CLK_TOP_MIPIPLL, - CLK_TOP_MIPIPLL_D2, - CLK_TOP_MIPIPLL_D4, - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 +static const struct mtk_parent dpi0_tve_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MIPIPLL), + TOP_PARENT(CLK_TOP_MIPIPLL_D2), + TOP_PARENT(CLK_TOP_MIPIPLL_D4), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), }; -static const int dpi1_parents[] = { - CLK_XTAL, - CLK_TOP_TVDPLL, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4 +static const struct mtk_parent dpi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), }; -static const int hdmi_parents[] = { - CLK_XTAL, - CLK_TOP_HDMIPLL, - CLK_TOP_HDMIPLL_D2, - CLK_TOP_HDMIPLL_D3 +static const struct mtk_parent hdmi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_HDMIPLL), + TOP_PARENT(CLK_TOP_HDMIPLL_D2), + TOP_PARENT(CLK_TOP_HDMIPLL_D3), }; -static const int apll_parents[] = { - CLK_XTAL, - CLK_TOP_AUDPLL, - CLK_TOP_AUDPLL_D4, - CLK_TOP_AUDPLL_D8, - CLK_TOP_AUDPLL_D16, - CLK_TOP_AUDPLL_D24, - CLK_XTAL, - CLK_XTAL +static const struct mtk_parent apll_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_AUDPLL), + TOP_PARENT(CLK_TOP_AUDPLL_D4), + TOP_PARENT(CLK_TOP_AUDPLL_D8), + TOP_PARENT(CLK_TOP_AUDPLL_D16), + TOP_PARENT(CLK_TOP_AUDPLL_D24), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; -static const int rtc_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_32K_EXTERNAL, - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8 +static const struct mtk_parent rtc_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_32K_EXTERNAL), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), }; -static const int nfi2x_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_XTAL +static const struct mtk_parent nfi2x_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + EXT_PARENT(CLK_PAD_CLK26M), }; -static const int emmc_hclk_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent emmc_hclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int flash_parents[] = { - CLK_TOP_CLK26M_D8, - CLK_XTAL, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent flash_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D8), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int di_parents[] = { - CLK_XTAL, - CLK_TOP_TVD2PLL, - CLK_TOP_TVD2PLL_D2, - CLK_XTAL +static const struct mtk_parent di_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVD2PLL), + TOP_PARENT(CLK_TOP_TVD2PLL_D2), + EXT_PARENT(CLK_PAD_CLK26M), }; -static const int nr_osd_parents[] = { - CLK_XTAL, - CLK_TOP_VENCPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_DMPLL +static const struct mtk_parent nr_osd_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VENCPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int hdmirx_bist_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL_D3, - CLK_XTAL, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_VENCPLL, - CLK_XTAL +static const struct mtk_parent hdmirx_bist_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_VENCPLL), + EXT_PARENT(CLK_PAD_CLK26M), }; -static const int intdir_parents[] = { - CLK_XTAL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D2, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int asm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent asm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int ms_card_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D8, - CLK_TOP_SYSPLL4_D4 +static const struct mtk_parent ms_card_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), }; -static const int ethif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_DMPLL, - CLK_TOP_DMPLL_D2 +static const struct mtk_parent ethif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_DMPLL), + TOP_PARENT(CLK_TOP_DMPLL_D2), }; -static const int hdmirx_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D52 +static const struct mtk_parent hdmirx_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), }; -static const int cmsys_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL1_D8, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL +static const struct mtk_parent cmsys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; -static const int clk_8bdac_parents[] = { - CLK_TOP_32K_INTERNAL, - CLK_TOP_8BDAC, - CLK_XTAL, - CLK_XTAL +static const struct mtk_parent clk_8bdac_parents[] = { + TOP_PARENT(CLK_TOP_32K_INTERNAL), + TOP_PARENT(CLK_TOP_8BDAC), + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK26M), }; -static const int aud2dvd_parents[] = { - CLK_TOP_AUD_48K_TIMING, - CLK_TOP_AUD_44K_TIMING +static const struct mtk_parent aud2dvd_parents[] = { + TOP_PARENT(CLK_TOP_AUD_48K_TIMING), + TOP_PARENT(CLK_TOP_AUD_44K_TIMING), }; -static const int padmclk_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D26, - CLK_TOP_UNIVPLL_D52, - CLK_TOP_UNIVPLL_D108, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIVPLL2_D32 +static const struct mtk_parent padmclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D26), + TOP_PARENT(CLK_TOP_UNIVPLL_D52), + TOP_PARENT(CLK_TOP_UNIVPLL_D108), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), }; -static const int aud_mux_parents[] = { - CLK_XTAL, - CLK_TOP_AUD1PLL_98M, - CLK_TOP_AUD2PLL_90M, - CLK_TOP_HADDS2PLL_98M, - CLK_TOP_AUD_EXTCK1_DIV, - CLK_TOP_AUD_EXTCK2_DIV +static const struct mtk_parent aud_mux_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_AUD1PLL_98M), + TOP_PARENT(CLK_TOP_AUD2PLL_90M), + TOP_PARENT(CLK_TOP_HADDS2PLL_98M), + TOP_PARENT(CLK_TOP_AUD_EXTCK1_DIV), + TOP_PARENT(CLK_TOP_AUD_EXTCK2_DIV), }; -static const int aud_src_parents[] = { - CLK_TOP_AUD_MUX1_SEL, - CLK_TOP_AUD_MUX2_SEL +static const struct mtk_parent aud_src_parents[] = { + TOP_PARENT(CLK_TOP_AUD_MUX1_SEL), + TOP_PARENT(CLK_TOP_AUD_MUX2_SEL), }; static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), - MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), - MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), @@ -744,8 +750,7 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), - MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), @@ -786,8 +791,8 @@ static const struct mtk_gate_regs infra_cg_regs = { } #define GATE_INFRA(_id, _parent, _shift) \ GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA_XTAL(_id, _parent, _shift) \ - GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA_EXT(_id, _parent, _shift) \ + GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) static const struct mtk_gate infra_cgs[] = { @@ -795,8 +800,8 @@ static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1), GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4), - GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5), - GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6), + GATE_INFRA_EXT(CLK_INFRA_AUDIO, CLK_PAD_CLK26M, 5), + GATE_INFRA_EXT(CLK_INFRA_EFUSE, CLK_PAD_CLK26M, 6), GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7), GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8), GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12), @@ -866,19 +871,16 @@ static const int peri_id_offs_map[] = { [CLK_PERI_FCI] = 48, }; -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) - static const struct mtk_parent uart_ck_sel_parents[] = { - XTAL_PARENT(CLK_XTAL), + EXT_PARENT(CLK_PAD_CLK26M), TOP_PARENT(CLK_TOP_UART_SEL), }; static const struct mtk_composite peri_muxes[] = { - MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), - MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), - MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), - MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), + MUX(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), + MUX(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), + MUX(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), + MUX(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), }; static const struct mtk_gate_regs peri0_cg_regs = { @@ -902,8 +904,8 @@ static const struct mtk_gate_regs peri1_cg_regs = { } #define GATE_PERI0(_id, _parent, _shift) \ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_PERI0_XTAL(_id, _parent, _shift) \ - GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_PERI0_EXT(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -941,10 +943,10 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26), - GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27), - GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28), + GATE_PERI0_EXT(CLK_PERI_I2C3, CLK_PAD_CLK26M, 27), + GATE_PERI0_EXT(CLK_PERI_AUXADC, CLK_PAD_CLK26M, 28), GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29), - GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30), + GATE_PERI0_EXT(CLK_PERI_ETH, CLK_PAD_CLK26M, 30), GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31), GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0), @@ -1000,7 +1002,9 @@ static const struct mtk_gate hif_cgs[] = { }; static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = pll_id_offs_map, .id_offs_map_size = ARRAY_SIZE(pll_id_offs_map), .plls = apmixed_plls, @@ -1008,7 +1012,8 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { }; static const struct mtk_clk_tree mt7623_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = top_id_offs_map, .id_offs_map_size = ARRAY_SIZE(top_id_offs_map), .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL], @@ -1058,7 +1063,8 @@ static int mt7623_topckgen_probe(struct udevice *dev) } static const struct mtk_clk_tree mt7623_clk_gate_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt7623_infracfg_probe(struct udevice *dev) @@ -1068,6 +1074,8 @@ static int mt7623_infracfg_probe(struct udevice *dev) } static const struct mtk_clk_tree mt7623_clk_peri_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .id_offs_map = peri_id_offs_map, .id_offs_map_size = ARRAY_SIZE(peri_id_offs_map), .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL], @@ -1076,7 +1084,6 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = { .gates = peri_cgs, .num_muxes = ARRAY_SIZE(peri_muxes), .num_gates = ARRAY_SIZE(peri_cgs), - .xtal_rate = 26 * MHZ, }; static int mt7623_pericfg_probe(struct udevice *dev) @@ -1187,7 +1194,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .id = UCLASS_CLK, .of_match = mt7623_pericfg_compat, .probe = mt7623_pericfg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), + .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 582394f594b..74510ee36a9 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -28,6 +28,16 @@ #define MCU_BUS_MSK GENMASK(10, 9) #define MCU_BUS_SEL(x) ((x) << 9) +enum { + CLK_PAD_CLK40M, + CLK_PAD_CLK20M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, + [CLK_PAD_CLK20M] = 20 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -48,9 +58,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 21, 0x204, 24, 0x204, 0), - PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, CLK_PLL_HAVE_RST_BAR, 21, 0x214, 24, 0x214, 0), - PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, CLK_PLL_HAVE_RST_BAR, 7, 0x224, 24, 0x224, 14), PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 21, 0x300, 1, 0x304, 0), @@ -62,7 +72,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -71,7 +81,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000), @@ -93,11 +103,11 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), - FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), - FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK40M, 1, 1024), + FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_PAD_CLK40M, 1, 1), + FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK40M, 32, 1), FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4), FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8), @@ -133,7 +143,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), - FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4), + FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_PAD_CLK40M, 1, 4), FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1), @@ -152,215 +162,215 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), }; -static const int axi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int mem_parents[] = { - CLK_XTAL, - CLK_TOP_DMPLL +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int ddrphycfg_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent ddrphycfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int eth_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SGMIIPLL_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_DMPLL +static const struct mtk_parent eth_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int pwm_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int sgmii_ref_1_parents[] = { - CLK_XTAL, - CLK_TOP_SGMIIPLL_D2 +static const struct mtk_parent sgmii_ref_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SGMIIPLL_D2), }; -static const int nfi_infra_parents[] = { - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL_D7 +static const struct mtk_parent nfi_infra_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), }; -static const int flash_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D80_D4, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent flash_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int uart_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi0_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK40M), }; -static const int spi1_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D2, - CLK_XTAL, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_XTAL +static const struct mtk_parent spi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + EXT_PARENT(CLK_PAD_CLK40M), }; -static const int msdc30_0_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M +static const struct mtk_parent msdc30_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), }; -static const int msdc30_1_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D16, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D16), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int ap2wbmcu_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIV48M, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent ap2wbmcu_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIV48M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int audio_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_DMPLL_D4 +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_DMPLL_D4), }; -static const int pmicspi_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_UNIVPLL3_D4, - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_DMPLL_D8 +static const struct mtk_parent pmicspi_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_DMPLL_D8), }; -static const int scp_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int atb_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int hif_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - -1, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent hif_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + VOID_PARENT, + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int sata_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent sata_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int usb20_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent usb20_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int aud1_parents[] = { - CLK_XTAL +static const struct mtk_parent aud1_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), }; -static const int irrx_parents[] = { - CLK_XTAL, - CLK_TOP_SYSPLL4_D16 +static const struct mtk_parent irrx_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_SYSPLL4_D16), }; -static const int crypto_parents[] = { - CLK_XTAL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL_D5, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent crypto_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int gpt10m_parents[] = { - CLK_XTAL, - CLK_TOP_CLKXTAL_D4 +static const struct mtk_parent gpt10m_parents[] = { + EXT_PARENT(CLK_PAD_CLK40M), + TOP_PARENT(CLK_TOP_CLKXTAL_D4), }; static const struct mtk_composite top_muxes[] = { @@ -396,8 +406,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_5 */ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), - MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, - CLK_DOMAIN_SCPSYS), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, CLK_MUX_DOMAIN_SCPSYS), MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), @@ -567,8 +576,9 @@ static const struct mtk_gate ssusb_cgs[] = { }; static const struct mtk_clk_tree mt7629_clk_tree = { - .xtal_rate = 40 * MHZ, - .xtal2_rate = 20 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, @@ -582,8 +592,9 @@ static const struct mtk_clk_tree mt7629_clk_tree = { }; static const struct mtk_clk_tree mt7629_peri_clk_tree = { - .xtal_rate = 40 * MHZ, - .xtal2_rate = 20 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK20M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 09ed4d8a97f..8c2944b7fb3 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -18,8 +18,16 @@ #define MT7981_CLK_PDN 0x250 #define MT7981_CLK_PDN_EN_WRITE BIT(31) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -139,97 +147,194 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { }; /* TOPCKGEN MUX PARENTS */ -static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4, - CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6, - CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8, - CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 }; - -static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4, - CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 }; - -static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, - CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, - CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4, - CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; - -static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8, - CLK_TOP_M_D8_D2 }; - -static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K }; - -static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4, - CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; - -static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, - CLK_TOP_CB_RTC_32K }; - -static const int emmc_208m_parents[] = { - CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4, - CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, - CLK_TOP_CB_MM_D6 +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_MM_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_CB_M_D8), }; -static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2, - CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 }; +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_MM_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_MM_D6_D2), + TOP_PARENT(CLK_TOP_CB_M_D8), +}; -static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 }; +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, - CLK_TOP_CB_WEDMCU_208M }; +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D8), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 }; +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K), +}; -static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 }; +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET2_D6 }; +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_CB_RTC_32K), +}; -static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_NET1_D8_D4 }; +static const struct mtk_parent emmc_208m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D4), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), + TOP_PARENT(CLK_TOP_CB_MM_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_MM_D6), +}; -static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 }; +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D2), + TOP_PARENT(CLK_TOP_CB_MM_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D2), +}; -static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET1_D5 }; +static const struct mtk_parent csw_f26m_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; -static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M, - CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5, - CLK_TOP_CB_M_416M }; +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_CB_WEDMCU_208M), +}; -static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_NET2_800M, - CLK_TOP_CB_MM_720M }; +static const struct mtk_parent sysaxi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), +}; -static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_SGM_325M }; +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D3_D2), +}; -static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 }; +static const struct mtk_parent arm_db_main_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D6), +}; -static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5, - CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2, - CLK_TOP_NET1_D5_D2 }; +static const struct mtk_parent ap2cnn_host_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D4), +}; -static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M }; +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D2), +}; -static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 }; +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), +}; -static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent netsys_mcu_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_720M), + TOP_PARENT(CLK_TOP_CB_NET1_D4), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_CB_M_416M), +}; -static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4, - CLK_TOP_M_D8_D2 }; +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_800M), + TOP_PARENT(CLK_TOP_CB_MM_720M), +}; -static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 }; +static const struct mtk_parent sgm_325m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_SGM_325M), +}; -static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 }; +static const struct mtk_parent sgm_reg_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D4), +}; -static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, - CLK_TOP_CB_MM_D3_D5 }; +static const struct mtk_parent eip97b_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_CB_M_416M), + TOP_PARENT(CLK_TOP_CB_MM_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D2), +}; + +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), +}; + +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_196M), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; + +static const struct mtk_parent a_tuner_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; + +static const struct mtk_parent u2u3_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D8_D2), +}; + +static const struct mtk_parent u2u3_sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), +}; + +static const struct mtk_parent usb_frmcnt_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_MM_D3_D5), +}; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -238,9 +343,10 @@ static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -319,9 +425,6 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { }; /* INFRASYS MUX PARENTS */ -#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define VOID_PARENT PARENT(-1, 0) static const struct mtk_parent infra_uart0_parents[] = { TOP_PARENT(CLK_TOP_F26M_SEL), @@ -363,8 +466,9 @@ static const struct mtk_parent infra_pcie_parents[] = { .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -513,13 +617,16 @@ static const struct mtk_gate infracfg_gates[] = { }; static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_APMIXED_NR_CLK, - .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, .num_fclks = ARRAY_SIZE(fixed_pll_clks), }; static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CB_M_416M, .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, @@ -528,10 +635,12 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_INFRA_66M_MCK, .muxes_offs = CLK_INFRA_UART0_SEL, .gates_offs = CLK_INFRA_GPT_STA, diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index 79efbf43bc4..9c6514120a6 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -18,13 +18,16 @@ #define MT7986_CLK_PDN 0x250 #define MT7986_CLK_PDN_EN_WRITE BIT(31) -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -#define VOID_PARENT PARENT(-1, 0) +enum { + CLK_PAD_CLK40M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -234,9 +237,10 @@ static const struct mtk_parent da_u2_refsel_parents[] = { .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent_flags = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -370,8 +374,9 @@ static const struct mtk_parent infra_pcie_parents[] = { .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -519,14 +524,17 @@ static const struct mtk_gate infracfg_gates[] = { }; static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_APMIXED_NR_CLK, - .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, .num_fclks = ARRAY_SIZE(fixed_pll_clks), .flags = CLK_PARENT_APMIXED, }; static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_XTAL_D2, .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, @@ -535,10 +543,12 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_INFRA_SYSAXI_D2, .muxes_offs = CLK_INFRA_UART0_SEL, .gates_offs = CLK_INFRA_GPT_STA, diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 959b1c9cff6..5f102636079 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -15,15 +15,22 @@ #include "clk-mtk.h" -#define MT7987_XTAL_RATE (40 * MHZ) #define MT7987_CLK_PDN 0x250 #define MT7987_CLK_PDN_EN_WRITE BIT(31) -#define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) +enum { + CLK_PAD_CLK40M, +}; -#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) + +#define EXT_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -47,11 +54,12 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { }; static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, - .xtal_rate = 40 * MHZ, }; static const struct udevice_id mt7987_fixed_pll_compat[] = { @@ -104,15 +112,13 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14), PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8), PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2), - XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), + EXT_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_PAD_CLK40M, 1, 1), TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221), }; /* TOPCKGEN MUX PARENTS */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) /* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */ static const struct mtk_parent netsys_parents[] = { @@ -341,9 +347,9 @@ static const struct mtk_parent emmc_200m_parents[] = { .upd_reg = (_upd_ofs), .upd_shift = (_upd), \ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ .gate_reg = (_mux_ofs), .gate_shift = (_gate), \ - .parent_flags = (_parents), \ + .parent = (_parents), \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -443,13 +449,14 @@ static const struct mtk_composite topckgen_mtk_muxes[] = { }; static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_TOP_NETSYS_SEL, .fdivs = topckgen_mtk_fixed_factors, .muxes = topckgen_mtk_muxes, .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, - .xtal_rate = MT7987_XTAL_RATE, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct udevice_id mt7987_topckgen_compat[] = { @@ -482,63 +489,63 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { /* INFRASYS MUX PARENTS */ /* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */ -static const int infra_mux_uart0_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart0_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */ -static const int infra_mux_uart1_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart1_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */ -static const int infra_mux_uart2_parents[] = { - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL +static const struct mtk_parent infra_mux_uart2_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; /* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */ -static const int infra_mux_spi0_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPI_SEL +static const struct mtk_parent infra_mux_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), }; /* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */ -static const int infra_mux_spi1_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPIM_MST_SEL +static const struct mtk_parent infra_mux_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL), }; /* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */ -static const int infra_mux_spi2_bck_parents[] = { - CLK_TOP_I2C_SEL, - CLK_TOP_SPI_SEL +static const struct mtk_parent infra_mux_spi2_bck_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), }; /* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */ -static const int infra_pwm_bck_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_SYSAXI_SEL, - CLK_TOP_PWM_SEL +static const struct mtk_parent infra_pwm_bck_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_SYSAXI_SEL), + TOP_PARENT(CLK_TOP_PWM_SEL), }; /* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */ -static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL), }; /* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */ -static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CLK_TOP_CB_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P1_SEL +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P1_SEL), }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ @@ -547,8 +554,9 @@ static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ .gate_shift = -1, .upd_shift = -1, \ - .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + .parent = (_parents), \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -640,8 +648,8 @@ static const struct mtk_gate_regs infra_3_cg_regs = { GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ - GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA3_EXT(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { @@ -742,20 +750,20 @@ static const struct mtk_gate infracfg_mtk_gates[] = { CLK_TOP_CB_CKSQ_40M, 7), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, - "infra_usb_pipe_ck_p1", CLK_XTAL, 11), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, - "infra_usb_utmi_ck_p1", CLK_XTAL, 13), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE_CK_P1, + "infra_usb_pipe_ck_p1", CLK_PAD_CLK40M, 11), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI_CK_P1, + "infra_usb_utmi_ck_p1", CLK_PAD_CLK40M, 13), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, - "infra_pcie_pipe_ck_p0", CLK_XTAL, 24), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, - "infra_pcie_pipe_ck_p1", CLK_XTAL, 25), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P0, + "infra_pcie_pipe_ck_p0", CLK_PAD_CLK40M, 24), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P1, + "infra_pcie_pipe_ck_p1", CLK_PAD_CLK40M, 25), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, @@ -767,14 +775,14 @@ static const struct mtk_gate infracfg_mtk_gates[] = { }; static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX_UART0_SEL, .gates_offs = CLK_INFRA_66M_GPT_BCK, .muxes = infracfg_mtk_mux, .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .flags = CLK_BYPASS_XTAL, - .xtal_rate = MT7987_XTAL_RATE, }; static const struct udevice_id mt7987_infracfg_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index cd8726852d7..4e19f285da0 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -21,11 +21,19 @@ #define MT7988_ETHDMA_RST_CTRL_OFS 0x34 #define MT7988_ETHWARP_RST_CTRL_OFS 0x8 -#define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) +enum { + CLK_PAD_CLK40M, +}; -#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK40M] = 40 * MHZ, +}; + +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_PAD_CLK40M, CLK_PARENT_EXT, _rate) + +#define EXT_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -94,8 +102,6 @@ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { }; /* TOPCKGEN MUX PARENTS */ -#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) -#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) static const struct mtk_parent netsys_parents[] = { TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2), @@ -283,9 +289,10 @@ static const struct mtk_parent eth_mii_parents[] = { .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent_flags = _parents, \ + .gate_shift = _gate, \ + .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* TOPCKGEN MUX_GATE */ @@ -446,51 +453,75 @@ static const struct mtk_composite topckgen_mtk_muxes[] = { }; /* INFRASYS MUX PARENTS */ -static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; - -static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; - -static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_UART_SEL }; - -static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL }; - -static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL }; - -static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K, - CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL, - CLK_TOP_PWM_SEL }; - -static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_SEL +static const struct mtk_parent infra_mux_uart0_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P1_SEL +static const struct mtk_parent infra_mux_uart1_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P2_SEL +static const struct mtk_parent infra_mux_uart2_parents[] = { + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL), }; -static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { - CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, - CLK_TOP_PEXTP_TL_P3_SEL +static const struct mtk_parent infra_mux_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL), +}; + +static const struct mtk_parent infra_mux_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL), +}; + +static const struct mtk_parent infra_pwm_bck_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_SYSAXI_SEL), + TOP_PARENT(CLK_TOP_PWM_SEL), +}; + +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL), +}; + +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P1_SEL), +}; + +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p2_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P2_SEL), +}; + +static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p3_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_INFRA_F26M_SEL), + TOP_PARENT(CLK_TOP_PEXTP_TL_P3_SEL), }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ { \ .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, .parent = _parents, \ + .mux_mask = BIT(_width) - 1, \ + .parent = _parents, \ .gate_shift = -1, .upd_shift = -1, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + .flags = CLK_MUX_SETCLR_UPD, \ } /* INFRA MUX */ @@ -606,8 +637,8 @@ static const struct mtk_gate_regs infra_3_cg_regs = { GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ - GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) +#define GATE_INFRA3_EXT(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { @@ -728,21 +759,18 @@ static const struct mtk_gate infracfg_mtk_gates[] = { GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4), GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5), - GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6), - GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL, - 7), + GATE_INFRA3_EXT(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_PAD_CLK40M, 6), + GATE_INFRA3_EXT(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_PAD_CLK40M, 7), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 8), GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", CLK_TOP_USB_FRMCNT_P1_SEL, 9), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL, - 10), - GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - CLK_XTAL, 11), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL, - 12), - GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - CLK_XTAL, 13), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_PAD_CLK40M, 10), + GATE_INFRA3_EXT(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", + CLK_PAD_CLK40M, 11), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_PAD_CLK40M, 12), + GATE_INFRA3_EXT(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", + CLK_PAD_CLK40M, 13), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL, 14), GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", @@ -755,14 +783,14 @@ static const struct mtk_gate infracfg_mtk_gates[] = { CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - CLK_XTAL, 24), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - CLK_XTAL, 25), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - CLK_XTAL, 26), - GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - CLK_XTAL, 27), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", + CLK_PAD_CLK40M, 24), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", + CLK_PAD_CLK40M, 25), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", + CLK_PAD_CLK40M, 26), + GATE_INFRA3_EXT(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", + CLK_PAD_CLK40M, 27), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", @@ -774,14 +802,17 @@ static const struct mtk_gate infracfg_mtk_gates[] = { }; static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, - .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_XTAL_D2, .muxes_offs = CLK_TOP_NETSYS_SEL, .fclks = topckgen_mtk_fixed_clks, @@ -790,19 +821,18 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { .num_fclks = ARRAY_SIZE(topckgen_mtk_fixed_clks), .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), - .flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN, - .xtal_rate = 40 * MHZ, + .flags = CLK_PARENT_TOPCKGEN, }; static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .muxes_offs = CLK_INFRA_MUX_UART0_SEL, .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0, .muxes = infracfg_mtk_mux, .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), - .flags = CLK_BYPASS_XTAL, - .xtal_rate = 40 * MHZ, }; static const struct udevice_id mt7988_fixed_pll_compat[] = { diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 9d9d00622db..7b2d796bc6c 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -17,6 +17,14 @@ #define MT8183_PLL_FMAX (3800UL * MHZ) #define MT8183_PLL_FMIN (1500UL * MHZ) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \ _pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -38,24 +46,24 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24, 0x0204, 0), PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24, 0x0214, 0), PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24, 0x0294, 0), PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0224, 0), PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, + CLK_PLL_HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0234, 0), PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001, 0, 0, 22, 8, 0x0254, 24, 0x0254, 0), PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001, - HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, + CLK_PLL_HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0274, 0), PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001, 0, 0, 22, 8, 0x0244, 24, 0x0244, 0), @@ -68,7 +76,7 @@ static const struct mtk_pll_data apmixed_plls[] = { }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_UNIVPLL, CLK_PARENT_TOPCKGEN, _rate) @@ -197,347 +205,347 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { 16, CLK_PARENT_TOPCKGEN), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_OSC_D4 +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_OSC_D4), }; -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; -static const int img_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent img_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; -static const int cam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2, - CLK_TOP_MMPLL_D6, - CLK_TOP_SYSPLL_D3, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_UNIVPLL_D3_D2 +static const struct mtk_parent cam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), }; -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; -static const int dsp1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent dsp1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; -static const int dsp2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent dsp2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; -static const int ipu_if_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent ipu_if_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MFGPLL_CK, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3 +static const struct mtk_parent mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MFGPLL_CK), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), }; -static const int f52m_mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D3_D8 +static const struct mtk_parent f52m_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), }; -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 +static const struct mtk_parent camtg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), }; -static const int camtg2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 +static const struct mtk_parent camtg2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), }; -static const int camtg3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 +static const struct mtk_parent camtg3_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), }; -static const int camtg4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVP_192M_D8, - CLK_TOP_UNIVPLL_D3_D8, - CLK_TOP_UNIVP_192M_D4, - CLK_TOP_UNIVPLL_D3_D16, - CLK_TOP_F26M_CK_D2, - CLK_TOP_UNIVP_192M_D16, - CLK_TOP_UNIVP_192M_D32 +static const struct mtk_parent camtg4_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVP_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), + TOP_PARENT(CLK_TOP_UNIVP_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVP_192M_D16), + TOP_PARENT(CLK_TOP_UNIVP_192M_D32), }; -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D8 +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D2, - CLK_TOP_SYSPLL_D3_D4, - CLK_TOP_MSDCPLL_D4 +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), }; -static const int msdc50_hclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3_D2 +static const struct mtk_parent msdc50_hclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_CK, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL_D2_D4, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_UNIVPLL_D2_D2 +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_CK), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int msdc30_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_SYSPLL_D3_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D4, - CLK_TOP_SYSPLL_D7_D4, - CLK_TOP_SYSPLL_D2_D16 +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D16), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D7_D2 +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7_D2), }; -static const int pmicspi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_OSC_D8 +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_OSC_D8), }; -static const int fpwrap_ulposc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_OSC_D16, - CLK_TOP_OSC_D4, - CLK_TOP_OSC_D8 +static const struct mtk_parent fpwrap_ulposc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D8), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent atb_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int sspm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D3 +static const struct mtk_parent sspm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4, - CLK_TOP_TVDPLL_D8, - CLK_TOP_TVDPLL_D16, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_SYSPLL_D3_D4, - CLK_TOP_UNIVPLL_D3_D8 +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_TVDPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D8), }; -static const int scam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5_D2 +static const struct mtk_parent scam_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5_D2), }; -static const int disppwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_OSC_D2, - CLK_TOP_OSC_D4, - CLK_TOP_OSC_D16 +static const struct mtk_parent disppwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D16), }; -static const int usb_top_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent usb_top_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int ssusb_top_xhci_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D3_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent ssusb_top_xhci_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8 +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D8, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent scp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D8), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int seninf_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2_D2, - CLK_TOP_UNIVPLL_D3_D2, - CLK_TOP_UNIVPLL_D2_D4 +static const struct mtk_parent seninf_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D2_D4), }; -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D8 +static const struct mtk_parent dxcc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8 +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8 +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int faes_ufsfde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2, - CLK_TOP_SYSPLL_D2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent faes_ufsfde_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int fufs_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D2_D4, - CLK_TOP_SYSPLL_D2_D8, - CLK_TOP_SYSPLL_D2_D16 +static const struct mtk_parent fufs_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D8), + TOP_PARENT(CLK_TOP_SYSPLL_D2_D16), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_CK +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_CK), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_CK +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_CK), }; static const struct mtk_composite top_muxes[] = { @@ -597,8 +605,9 @@ static const struct mtk_composite top_muxes[] = { }; static const struct mtk_clk_tree mt8183_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_CLK13M, .muxes_offs = CLK_TOP_MUX_AXI, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 64aeaa5949f..3e413e111f1 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -19,15 +19,17 @@ #define MT8188_PLL_FMAX (3800UL * MHZ) #define MT8188_PLL_FMIN (1500UL * MHZ) -/* Missing topckgen clocks definition in dt-bindings */ -#define CLK_TOP_ADSPPLL 206 -#define CLK_TOP_CLK13M 207 -#define CLK_TOP_CLK26M 208 -#define CLK_TOP_CLK32K 209 -#define CLK_TOP_IMGPLL 210 -#define CLK_TOP_MSDCPLL 211 -#define CLK_TOP_ULPOSC1_CK1 212 -#define CLK_TOP_ULPOSC_CK1 213 +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, + CLK_PAD_CLK13M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_CLK13M] = 13 * MHZ, +}; /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ @@ -57,13 +59,13 @@ static const struct mtk_pll_data apmixed_plls[] = { 0x0528, 0), PLL(CLK_APMIXED_TVDPLL2, 0x0534, 0x0540, 0, 0, 22, 0x0538, 24, 0x0538, 0), - PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MMPLL, 0x0544, 0x0550, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0548, 24, 0x0548, 0), - PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_MAINPLL, 0x045C, 0x0468, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0460, 24, 0x0460, 0), PLL(CLK_APMIXED_IMGPLL, 0x0554, 0x0560, 0, 0, 22, 0x0558, 24, 0x0558, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, HAVE_RST_BAR, + PLL(CLK_APMIXED_UNIVPLL, 0x0504, 0x0510, 0xff000000, CLK_PLL_HAVE_RST_BAR, 22, 0x0508, 24, 0x0508, 0), PLL(CLK_APMIXED_ADSPPLL, 0x042C, 0x0438, 0, 0, 22, 0x0430, 24, 0x0430, 0), @@ -82,14 +84,15 @@ static const struct mtk_pll_data apmixed_plls[] = { }; static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_ULPOSC1, 260000000), @@ -98,8 +101,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000), FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000), - FIXED_CLK0(CLK_TOP_CLK26M, 260000000), - FIXED_CLK0(CLK_TOP_CLK32K, 32000), }; #define FACTOR0(_id, _parent, _mult, _div) \ @@ -148,13 +149,13 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_UNIVPLL_192M_D10, CLK_TOP_UNIVPLL_192M, 1, 10), FACTOR1(CLK_TOP_UNIVPLL_192M_D16, CLK_TOP_UNIVPLL_192M, 1, 16), FACTOR1(CLK_TOP_UNIVPLL_192M_D32, CLK_TOP_UNIVPLL_192M, 1, 32), - FACTOR1(CLK_TOP_APLL1_D3, CLK_TOP_APLL1, 1, 3), - FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4), - FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3), - FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4), - FACTOR1(CLK_TOP_APLL3_D4, CLK_TOP_APLL3, 1, 4), - FACTOR1(CLK_TOP_APLL4_D4, CLK_TOP_APLL4, 1, 4), - FACTOR1(CLK_TOP_APLL5_D4, CLK_TOP_APLL5, 1, 4), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4), + FACTOR0(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4), + FACTOR0(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4), FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), FACTOR1(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, 2), FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), @@ -164,21 +165,20 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_MMPLL_D6_D2, CLK_TOP_MMPLL_D6, 1, 2), FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), - FACTOR1(CLK_TOP_TVDPLL1_D2, CLK_TOP_TVDPLL1, 1, 2), - FACTOR1(CLK_TOP_TVDPLL1_D4, CLK_TOP_TVDPLL1, 1, 4), - FACTOR1(CLK_TOP_TVDPLL1_D8, CLK_TOP_TVDPLL1, 1, 8), - FACTOR1(CLK_TOP_TVDPLL1_D16, CLK_TOP_TVDPLL1, 1, 16), - FACTOR1(CLK_TOP_TVDPLL2_D2, CLK_TOP_TVDPLL2, 1, 2), - FACTOR1(CLK_TOP_TVDPLL2_D4, CLK_TOP_TVDPLL2, 1, 4), - FACTOR1(CLK_TOP_TVDPLL2_D8, CLK_TOP_TVDPLL2, 1, 8), - FACTOR1(CLK_TOP_TVDPLL2_D16, CLK_TOP_TVDPLL2, 1, 16), - FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 1, 16), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16), FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16), - FACTOR1(CLK_TOP_ETHPLL_D2, CLK_TOP_ETHPLL, 1, 2), - FACTOR1(CLK_TOP_ETHPLL_D4, CLK_TOP_ETHPLL, 1, 4), - FACTOR1(CLK_TOP_ETHPLL_D8, CLK_TOP_ETHPLL, 1, 8), - FACTOR1(CLK_TOP_ETHPLL_D10, CLK_TOP_ETHPLL, 1, 10), + FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), + FACTOR0(CLK_TOP_ETHPLL_D4, CLK_APMIXED_ETHPLL, 1, 4), + FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), + FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), FACTOR0(CLK_TOP_ADSPPLL_D2, CLK_APMIXED_ADSPPLL, 1, 2), FACTOR0(CLK_TOP_ADSPPLL_D4, CLK_APMIXED_ADSPPLL, 1, 4), FACTOR0(CLK_TOP_ADSPPLL_D8, CLK_APMIXED_ADSPPLL, 1, 8), @@ -190,375 +190,375 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_ULPOSC1_D16, CLK_TOP_ULPOSC1, 1, 16), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_ULPOSC1_D4 +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_MAINPLL_D7_D4, - CLK_TOP_CLK32K +static const struct mtk_parent spm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + EXT_PARENT(CLK_PAD_CLK32K), }; -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_MAINPLL_D3 +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_MAINPLL_D3), }; -static const int bus_aximem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6 +static const struct mtk_parent bus_aximem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), }; -static const int vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 +static const struct mtk_parent vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), }; -static const int ethdr_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D5_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4 +static const struct mtk_parent ethdr_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), }; -static const int ipe_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D7 +static const struct mtk_parent ipe_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), }; -static const int cam_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_IMGPLL +static const struct mtk_parent cam_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), }; -static const int ccu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent ccu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int ccu_ahb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent ccu_ahb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int img_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_IMGPLL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent img_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int camtm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D6_D4 +static const struct mtk_parent camtm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dsp1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dsp2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dsp3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dsp4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dsp5_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dsp6_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp6_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dsp7_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MMPLL_D4, - CLK_TOP_MAINPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent dsp7_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int mfg_core_tmp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_UNIVPLL_D7 +static const struct mtk_parent mfg_core_tmp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), }; -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; -static const int camtg2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 +static const struct mtk_parent camtg2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; -static const int camtg3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D10, - CLK_TOP_CLK13M, - CLK_TOP_UNIVPLL_192M_D16, - CLK_TOP_UNIVPLL_192M_D32 +static const struct mtk_parent camtg3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), }; -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D4, - CLK_TOP_MAINPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D5_D4 +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), }; -static const int msdc5hclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6_D2 +static const struct mtk_parent msdc5hclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_UNIVPLL_D4_D2 +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int msdc30_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent msdc30_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int intdir_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4 +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D4 +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; -static const int audio_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_APLL1, - CLK_TOP_APLL2 +static const struct mtk_parent audio_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int pwrap_ulposc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D8, - CLK_TOP_TVDPLL1_D16 +static const struct mtk_parent pwrap_ulposc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int sspm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D9, - CLK_TOP_MAINPLL_D4_D2 +static const struct mtk_parent sspm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), }; /* @@ -566,463 +566,463 @@ static const int sspm_parents[] = { * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate * in dual output case, which would lead to corruption of functionality loss. */ -static const int dp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL2_D2, - CLK_TOP_TVDPLL2_D4, - CLK_TOP_TVDPLL2_D8, - CLK_TOP_TVDPLL2_D16 +static const struct mtk_parent dp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), }; -static const int edp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1_D2, - CLK_TOP_TVDPLL1_D4, - CLK_TOP_TVDPLL1_D8, - CLK_TOP_TVDPLL1_D16 +static const struct mtk_parent edp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), }; -static const int dpi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL1_D2, - CLK_TOP_TVDPLL2_D2, - CLK_TOP_TVDPLL1_D4, - CLK_TOP_TVDPLL2_D4, - CLK_TOP_TVDPLL1_D8, - CLK_TOP_TVDPLL2_D8, - CLK_TOP_TVDPLL1_D16, - CLK_TOP_TVDPLL2_D16 +static const struct mtk_parent dpi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), }; -static const int disp_pwm0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ETHPLL_D4 +static const struct mtk_parent disp_pwm0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ETHPLL_D4), }; -static const int disp_pwm1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D16 +static const struct mtk_parent disp_pwm1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), }; -static const int usb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent usb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int ssusb_xhci_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent ssusb_xhci_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int usb_2p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent usb_2p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int ssusb_xhci_2p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent ssusb_xhci_2p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int usb_3p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent usb_3p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int ssusb_xhci_3p_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent ssusb_xhci_3p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D8, - CLK_TOP_UNIVPLL_D5_D4 +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), }; -static const int seninf_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent seninf_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int seninf1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent seninf1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D5_D2, - CLK_TOP_UNIVPLL_D5_D2 +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), }; -static const int venc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MMPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MMPLL_D9, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D5 +static const struct mtk_parent venc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), }; -static const int vdec_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MMPLL_D6, - CLK_TOP_MAINPLL_D4, - CLK_TOP_TVDPLL2, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_IMGPLL, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MMPLL_D9 +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), }; -static const int pwm_parents[] = { - CLK_TOP_CLK32K, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_UNIVPLL_D6_D4 +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK32K), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; -static const int mcupm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6_D2, - CLK_TOP_MAINPLL_D7_D4 +static const struct mtk_parent mcupm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), }; -static const int spmi_p_mst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_CLK32K, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_MAINPLL_D6_D8, - CLK_TOP_MAINPLL_D5_D8 +static const struct mtk_parent spmi_p_mst_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), }; -static const int spmi_m_mst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_ULPOSC1_D8, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_ULPOSC1_D16, - CLK_TOP_ULPOSC1_D7, - CLK_TOP_CLK32K, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_MAINPLL_D6_D8, - CLK_TOP_MAINPLL_D5_D8 +static const struct mtk_parent spmi_m_mst_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), }; -static const int dvfsrc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ULPOSC1_D10, - CLK_TOP_UNIVPLL_D6_D8, - CLK_TOP_MSDCPLL_D16 +static const struct mtk_parent dvfsrc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), }; -static const int tl_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5_D4, - CLK_TOP_MAINPLL_D4_D4 +static const struct mtk_parent tl_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), }; -static const int aes_msdcfde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent aes_msdcfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int dsi_occ_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D2 +static const struct mtk_parent dsi_occ_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), }; -static const int wpe_vpp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MMPLL_D6_D2, - CLK_TOP_UNIVPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_UNIVPLL_D4_D2, - CLK_TOP_MMPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MMPLL_D7, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_MAINPLL_D4, - CLK_TOP_TVDPLL1, - CLK_TOP_UNIVPLL_D4 +static const struct mtk_parent wpe_vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL1), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), }; -static const int hdcp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D4_D8, - CLK_TOP_MAINPLL_D5_D8, - CLK_TOP_UNIVPLL_D6_D4 +static const struct mtk_parent hdcp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), }; -static const int hdcp_24m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_192M_D4, - CLK_TOP_UNIVPLL_192M_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent hdcp_24m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int hdmi_apb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent hdmi_apb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int snps_eth_250m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D2 +static const struct mtk_parent snps_eth_250m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), }; -static const int snps_eth_62p4m_ptp_parents[] = { - CLK_TOP_APLL2_D3, - CLK_TOP_APLL1_D3, - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D8 +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL1_D3), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), }; -static const int snps_eth_50m_rmii_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int adsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_UNIVPLL_D4_D4, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_ULPOSC1_D2, - CLK_TOP_ULPOSC1_CK1, - CLK_TOP_ADSPPLL, - CLK_TOP_ADSPPLL_D2, - CLK_TOP_ADSPPLL_D4, - CLK_TOP_ADSPPLL_D8 +static const struct mtk_parent adsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1), + APMIXED_PARENT(CLK_APMIXED_ADSPPLL), + TOP_PARENT(CLK_TOP_ADSPPLL_D2), + TOP_PARENT(CLK_TOP_ADSPPLL_D4), + TOP_PARENT(CLK_TOP_ADSPPLL_D8), }; -static const int audio_local_bus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D7_D2, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_ULPOSC1_CK1, - CLK_TOP_ULPOSC1_D4, - CLK_TOP_ULPOSC1_D2 +static const struct mtk_parent audio_local_bus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), }; -static const int asm_h_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent asm_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int asm_l_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6_D4, - CLK_TOP_UNIVPLL_D6_D2, - CLK_TOP_MAINPLL_D5_D2 +static const struct mtk_parent asm_l_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), }; -static const int apll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent apll1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int apll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent apll2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int apll3_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4 +static const struct mtk_parent apll3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), }; -static const int apll4_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL4_D4 +static const struct mtk_parent apll4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL4_D4), }; -static const int apll5_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL5_D4 +static const struct mtk_parent apll5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int i2so1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2so1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2so2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2so2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2si1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2si1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int i2si2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent i2si2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int dptx_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent dptx_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int aud_iec_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_APLL3, - CLK_TOP_APLL4, - CLK_TOP_APLL5 +static const struct mtk_parent aud_iec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), }; -static const int a1sys_hp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D4 +static const struct mtk_parent a1sys_hp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), }; -static const int a2sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D4 +static const struct mtk_parent a2sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int a3sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4, - CLK_TOP_APLL4_D4, - CLK_TOP_APLL5_D4 +static const struct mtk_parent a3sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int a4sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL3_D4, - CLK_TOP_APLL4_D4, - CLK_TOP_APLL5_D4 +static const struct mtk_parent a4sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4_D4, - CLK_TOP_MAINPLL_D5_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int spinor_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK13M, - CLK_TOP_MAINPLL_D7_D8, - CLK_TOP_UNIVPLL_D6_D8 +static const struct mtk_parent spinor_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + EXT_PARENT(CLK_PAD_CLK13M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), }; -static const int ulposc_parents[] = { - CLK_TOP_ULPOSC_CK1, - CLK_TOP_ETHPLL_D2, - CLK_TOP_MAINPLL_D4_D2, - CLK_TOP_ETHPLL_D10 +static const struct mtk_parent ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ETHPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_ETHPLL_D10), }; -static const int srck_parents[] = { - CLK_TOP_ULPOSC1_D10, - CLK_TOP_CLK26M +static const struct mtk_parent srck_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + EXT_PARENT(CLK_PAD_CLK26M), }; static const struct mtk_composite top_muxes[] = { @@ -1142,236 +1142,286 @@ static const struct mtk_composite top_muxes[] = { MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x0128, 16, 4, 23), }; -static const int mt8188_id_offs_map[] = { - 87, /* CLK_TOP_AXI */ - 88, /* CLK_TOP_SPM */ - 89, /* CLK_TOP_SCP */ - 90, /* CLK_TOP_BUS_AXIMEM */ - 91, /* CLK_TOP_VPP */ - 92, /* CLK_TOP_ETHDR */ - 93, /* CLK_TOP_IPE */ - 94, /* CLK_TOP_CAM */ - 95, /* CLK_TOP_CCU */ - 96, /* CLK_TOP_CCU_AHB */ - 97, /* CLK_TOP_IMG */ - 98, /* CLK_TOP_CAMTM */ - 99, /* CLK_TOP_DSP */ - 100, /* CLK_TOP_DSP1 */ - 101, /* CLK_TOP_DSP2 */ - 102, /* CLK_TOP_DSP3 */ - 103, /* CLK_TOP_DSP4 */ - 104, /* CLK_TOP_DSP5 */ - 105, /* CLK_TOP_DSP6 */ - 106, /* CLK_TOP_DSP7 */ - 107, /* CLK_TOP_MFG_CORE_TMP */ - 108, /* CLK_TOP_CAMTG */ - 109, /* CLK_TOP_CAMTG2 */ - 110, /* CLK_TOP_CAMTG3 */ - 111, /* CLK_TOP_UART */ - 112, /* CLK_TOP_SPI */ - 113, /* CLK_TOP_MSDC50_0_HCLK */ - 114, /* CLK_TOP_MSDC50_0 */ - 115, /* CLK_TOP_MSDC30_1 */ - 116, /* CLK_TOP_MSDC30_2 */ - 117, /* CLK_TOP_INTDIR */ - 118, /* CLK_TOP_AUD_INTBUS */ - 119, /* CLK_TOP_AUDIO_H */ - 120, /* CLK_TOP_PWRAP_ULPOSC */ - 121, /* CLK_TOP_ATB */ - 122, /* CLK_TOP_SSPM */ - 123, /* CLK_TOP_DP */ - 124, /* CLK_TOP_EDP */ - 125, /* CLK_TOP_DPI */ - 126, /* CLK_TOP_DISP_PWM0 */ - 127, /* CLK_TOP_DISP_PWM1 */ - 128, /* CLK_TOP_USB_TOP */ - 129, /* CLK_TOP_SSUSB_XHCI */ - 130, /* CLK_TOP_USB_TOP_2P */ - 131, /* CLK_TOP_SSUSB_XHCI_2P */ - 132, /* CLK_TOP_USB_TOP_3P */ - 133, /* CLK_TOP_SSUSB_XHCI_3P */ - 134, /* CLK_TOP_I2C */ - 135, /* CLK_TOP_SENINF */ - 136, /* CLK_TOP_SENINF1 */ - 137, /* CLK_TOP_GCPU */ - 138, /* CLK_TOP_VENC */ - 139, /* CLK_TOP_VDEC */ - 140, /* CLK_TOP_PWM */ - 141, /* CLK_TOP_MCUPM */ - 142, /* CLK_TOP_SPMI_P_MST */ - 143, /* CLK_TOP_SPMI_M_MST */ - 144, /* CLK_TOP_DVFSRC */ - 145, /* CLK_TOP_TL */ - 146, /* CLK_TOP_AES_MSDCFDE */ - 147, /* CLK_TOP_DSI_OCC */ - 148, /* CLK_TOP_WPE_VPP */ - 149, /* CLK_TOP_HDCP */ - 150, /* CLK_TOP_HDCP_24M */ - 151, /* CLK_TOP_HDMI_APB */ - 152, /* CLK_TOP_SNPS_ETH_250M */ - 153, /* CLK_TOP_SNPS_ETH_62P4M_PTP */ - 154, /* CLK_TOP_SNPS_ETH_50M_RMII */ - 155, /* CLK_TOP_ADSP */ - 156, /* CLK_TOP_AUDIO_LOCAL_BUS */ - 157, /* CLK_TOP_ASM_H */ - 158, /* CLK_TOP_ASM_L */ - 159, /* CLK_TOP_APLL1 */ - 160, /* CLK_TOP_APLL2 */ - 161, /* CLK_TOP_APLL3 */ - 162, /* CLK_TOP_APLL4 */ - 163, /* CLK_TOP_APLL5 */ - 164, /* CLK_TOP_I2SO1 */ - 165, /* CLK_TOP_I2SO2 */ - 166, /* CLK_TOP_I2SI1 */ - 167, /* CLK_TOP_I2SI2 */ - 168, /* CLK_TOP_DPTX */ - 169, /* CLK_TOP_AUD_IEC */ - 170, /* CLK_TOP_A1SYS_HP */ - 171, /* CLK_TOP_A2SYS */ - 172, /* CLK_TOP_A3SYS */ - 173, /* CLK_TOP_A4SYS */ - 174, /* CLK_TOP_ECC */ - 175, /* CLK_TOP_SPINOR */ - 176, /* CLK_TOP_ULPOSC */ - 177, /* CLK_TOP_SRCK */ - -1, /* CLK_TOP_MFG_CK_FAST_REF */ - 8, /* CLK_TOP_MAINPLL_D3 */ - 9, /* CLK_TOP_MAINPLL_D4 */ - 10, /* CLK_TOP_MAINPLL_D4_D2 */ - 11, /* CLK_TOP_MAINPLL_D4_D4 */ - 12, /* CLK_TOP_MAINPLL_D4_D8 */ - 13, /* CLK_TOP_MAINPLL_D5 */ - 14, /* CLK_TOP_MAINPLL_D5_D2 */ - 15, /* CLK_TOP_MAINPLL_D5_D4 */ - 16, /* CLK_TOP_MAINPLL_D5_D8 */ - 17, /* CLK_TOP_MAINPLL_D6 */ - 18, /* CLK_TOP_MAINPLL_D6_D2 */ - 19, /* CLK_TOP_MAINPLL_D6_D4 */ - 20, /* CLK_TOP_MAINPLL_D6_D8 */ - 21, /* CLK_TOP_MAINPLL_D7 */ - 22, /* CLK_TOP_MAINPLL_D7_D2 */ - 23, /* CLK_TOP_MAINPLL_D7_D4 */ - 24, /* CLK_TOP_MAINPLL_D7_D8 */ - 25, /* CLK_TOP_MAINPLL_D9 */ - 26, /* CLK_TOP_UNIVPLL_D2 */ - 27, /* CLK_TOP_UNIVPLL_D3 */ - 28, /* CLK_TOP_UNIVPLL_D4 */ - 29, /* CLK_TOP_UNIVPLL_D4_D2 */ - 30, /* CLK_TOP_UNIVPLL_D4_D4 */ - 31, /* CLK_TOP_UNIVPLL_D4_D8 */ - 32, /* CLK_TOP_UNIVPLL_D5 */ - 33, /* CLK_TOP_UNIVPLL_D5_D2 */ - 34, /* CLK_TOP_UNIVPLL_D5_D4 */ - 35, /* CLK_TOP_UNIVPLL_D5_D8 */ - 36, /* CLK_TOP_UNIVPLL_D6 */ - 37, /* CLK_TOP_UNIVPLL_D6_D2 */ - 38, /* CLK_TOP_UNIVPLL_D6_D4 */ - 39, /* CLK_TOP_UNIVPLL_D6_D8 */ - 40, /* CLK_TOP_UNIVPLL_D7 */ - 41, /* CLK_TOP_UNIVPLL_192M */ - 42, /* CLK_TOP_UNIVPLL_192M_D4 */ - 43, /* CLK_TOP_UNIVPLL_192M_D8 */ - 44, /* CLK_TOP_UNIVPLL_192M_D10 */ - 45, /* CLK_TOP_UNIVPLL_192M_D16 */ - 46, /* CLK_TOP_UNIVPLL_192M_D32 */ - 47, /* CLK_TOP_APLL1_D3 */ - 48, /* CLK_TOP_APLL1_D4 */ - 49, /* CLK_TOP_APLL2_D3 */ - 50, /* CLK_TOP_APLL2_D4 */ - 51, /* CLK_TOP_APLL3_D4 */ - 52, /* CLK_TOP_APLL4_D4 */ - 53, /* CLK_TOP_APLL5_D4 */ - 54, /* CLK_TOP_MMPLL_D4 */ - 55, /* CLK_TOP_MMPLL_D4_D2 */ - 56, /* CLK_TOP_MMPLL_D5 */ - 57, /* CLK_TOP_MMPLL_D5_D2 */ - 58, /* CLK_TOP_MMPLL_D5_D4 */ - 59, /* CLK_TOP_MMPLL_D6 */ - 60, /* CLK_TOP_MMPLL_D6_D2 */ - 61, /* CLK_TOP_MMPLL_D7 */ - 62, /* CLK_TOP_MMPLL_D9 */ - -1, /* CLK_TOP_TVDPLL1 */ - 63, /* CLK_TOP_TVDPLL1_D2 */ - 64, /* CLK_TOP_TVDPLL1_D4 */ - 65, /* CLK_TOP_TVDPLL1_D8 */ - 66, /* CLK_TOP_TVDPLL1_D16 */ - -1, /* CLK_TOP_TVDPLL2 */ - 67, /* CLK_TOP_TVDPLL2_D2 */ - 68, /* CLK_TOP_TVDPLL2_D4 */ - 69, /* CLK_TOP_TVDPLL2_D8 */ - 70, /* CLK_TOP_TVDPLL2_D16 */ - 72, /* CLK_TOP_MSDCPLL_D2 */ - 73, /* CLK_TOP_MSDCPLL_D16 */ - -1, /* CLK_TOP_ETHPLL */ - 74, /* CLK_TOP_ETHPLL_D2 */ - 75, /* CLK_TOP_ETHPLL_D4 */ - 76, /* CLK_TOP_ETHPLL_D8 */ - 77, /* CLK_TOP_ETHPLL_D10 */ - 78, /* CLK_TOP_ADSPPLL_D2 */ - 79, /* CLK_TOP_ADSPPLL_D4 */ - 80, /* CLK_TOP_ADSPPLL_D8 */ - 0, /* CLK_TOP_ULPOSC1 */ - 81, /* CLK_TOP_ULPOSC1_D2 */ - 82, /* CLK_TOP_ULPOSC1_D4 */ - 83, /* CLK_TOP_ULPOSC1_D8 */ - 84, /* CLK_TOP_ULPOSC1_D7 */ - 85, /* CLK_TOP_ULPOSC1_D10 */ - 86, /* CLK_TOP_ULPOSC1_D16 */ - 1, /* CLK_TOP_MPHONE_SLAVE_BCK */ - 2, /* CLK_TOP_PAD_FPC */ - 3, /* CLK_TOP_466M_FMEM */ - 4, /* CLK_TOP_PEXTP_PIPE */ - 5, /* CLK_TOP_DSI_PHY */ - -1, /* CLK_TOP_APLL12_CK_DIV0 */ - -1, /* CLK_TOP_APLL12_CK_DIV1 */ - -1, /* CLK_TOP_APLL12_CK_DIV2 */ - -1, /* CLK_TOP_APLL12_CK_DIV3 */ - -1, /* CLK_TOP_APLL12_CK_DIV4 */ - -1, /* CLK_TOP_APLL12_CK_DIV9 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VPP1 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VDO0 */ - -1, /* CLK_TOP_CFGREG_CLOCK_EN_VDO1 */ - -1, /* CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS */ - -1, /* CLK_TOP_CFGREG_F26M_VPP0 */ - -1, /* CLK_TOP_CFGREG_F26M_VPP1 */ - -1, /* CLK_TOP_CFGREG_F26M_VDO0 */ - -1, /* CLK_TOP_CFGREG_F26M_VDO1 */ - -1, /* CLK_TOP_CFGREG_AUD_F26M_AUD */ - -1, /* CLK_TOP_CFGREG_UNIPLL_SES */ - -1, /* CLK_TOP_CFGREG_F_PCIE_PHY_REF */ - -1, /* CLK_TOP_SSUSB_TOP_REF */ - -1, /* CLK_TOP_SSUSB_PHY_REF */ - -1, /* CLK_TOP_SSUSB_TOP_P1_REF */ - -1, /* CLK_TOP_SSUSB_PHY_P1_REF */ - -1, /* CLK_TOP_SSUSB_TOP_P2_REF */ - -1, /* CLK_TOP_SSUSB_PHY_P2_REF */ - -1, /* CLK_TOP_SSUSB_TOP_P3_REF */ - -1, /* CLK_TOP_SSUSB_PHY_P3_REF */ - -1, /* CLK_TOP_NR_CLK */ - -1, /* CLK_TOP_ADSPPLL */ - -1, /* CLK_TOP_CLK13M */ - 6, /* CLK_TOP_CLK26M */ - 7, /* CLK_TOP_CLK32K */ - -1, /* CLK_TOP_IMGPLL */ - 71, /* CLK_TOP_MSDCPLL */ - -1, /* CLK_TOP_ULPOSC1_CK1 */ - -1, /* CLK_TOP_ULPOSC_CK1 */ +static const int mt8188_id_top_offs_map[] = { + [0 ... CLK_TOP_NR_CLK - 1] = -1, + /* FIXED */ + [CLK_TOP_ULPOSC1] = 0, + [CLK_TOP_MPHONE_SLAVE_BCK] = 1, + [CLK_TOP_PAD_FPC] = 2, + [CLK_TOP_466M_FMEM] = 3, + [CLK_TOP_PEXTP_PIPE] = 4, + [CLK_TOP_DSI_PHY] = 5, + /* FACTOR */ + [CLK_TOP_MAINPLL_D3] = 6, + [CLK_TOP_MAINPLL_D4] = 7, + [CLK_TOP_MAINPLL_D4_D2] = 8, + [CLK_TOP_MAINPLL_D4_D4] = 9, + [CLK_TOP_MAINPLL_D4_D8] = 10, + [CLK_TOP_MAINPLL_D5] = 11, + [CLK_TOP_MAINPLL_D5_D2] = 12, + [CLK_TOP_MAINPLL_D5_D4] = 13, + [CLK_TOP_MAINPLL_D5_D8] = 14, + [CLK_TOP_MAINPLL_D6] = 15, + [CLK_TOP_MAINPLL_D6_D2] = 16, + [CLK_TOP_MAINPLL_D6_D4] = 17, + [CLK_TOP_MAINPLL_D6_D8] = 18, + [CLK_TOP_MAINPLL_D7] = 19, + [CLK_TOP_MAINPLL_D7_D2] = 20, + [CLK_TOP_MAINPLL_D7_D4] = 21, + [CLK_TOP_MAINPLL_D7_D8] = 22, + [CLK_TOP_MAINPLL_D9] = 23, + [CLK_TOP_UNIVPLL_D2] = 24, + [CLK_TOP_UNIVPLL_D3] = 25, + [CLK_TOP_UNIVPLL_D4] = 26, + [CLK_TOP_UNIVPLL_D4_D2] = 27, + [CLK_TOP_UNIVPLL_D4_D4] = 28, + [CLK_TOP_UNIVPLL_D4_D8] = 29, + [CLK_TOP_UNIVPLL_D5] = 30, + [CLK_TOP_UNIVPLL_D5_D2] = 31, + [CLK_TOP_UNIVPLL_D5_D4] = 32, + [CLK_TOP_UNIVPLL_D5_D8] = 33, + [CLK_TOP_UNIVPLL_D6] = 34, + [CLK_TOP_UNIVPLL_D6_D2] = 35, + [CLK_TOP_UNIVPLL_D6_D4] = 36, + [CLK_TOP_UNIVPLL_D6_D8] = 37, + [CLK_TOP_UNIVPLL_D7] = 38, + [CLK_TOP_UNIVPLL_192M] = 39, + [CLK_TOP_UNIVPLL_192M_D4] = 40, + [CLK_TOP_UNIVPLL_192M_D8] = 41, + [CLK_TOP_UNIVPLL_192M_D10] = 42, + [CLK_TOP_UNIVPLL_192M_D16] = 43, + [CLK_TOP_UNIVPLL_192M_D32] = 44, + [CLK_TOP_APLL1_D3] = 45, + [CLK_TOP_APLL1_D4] = 46, + [CLK_TOP_APLL2_D3] = 47, + [CLK_TOP_APLL2_D4] = 48, + [CLK_TOP_APLL3_D4] = 49, + [CLK_TOP_APLL4_D4] = 50, + [CLK_TOP_APLL5_D4] = 51, + [CLK_TOP_MMPLL_D4] = 52, + [CLK_TOP_MMPLL_D4_D2] = 53, + [CLK_TOP_MMPLL_D5] = 54, + [CLK_TOP_MMPLL_D5_D2] = 55, + [CLK_TOP_MMPLL_D5_D4] = 56, + [CLK_TOP_MMPLL_D6] = 57, + [CLK_TOP_MMPLL_D6_D2] = 58, + [CLK_TOP_MMPLL_D7] = 59, + [CLK_TOP_MMPLL_D9] = 60, + [CLK_TOP_TVDPLL1_D2] = 61, + [CLK_TOP_TVDPLL1_D4] = 62, + [CLK_TOP_TVDPLL1_D8] = 63, + [CLK_TOP_TVDPLL1_D16] = 64, + [CLK_TOP_TVDPLL2_D2] = 65, + [CLK_TOP_TVDPLL2_D4] = 66, + [CLK_TOP_TVDPLL2_D8] = 67, + [CLK_TOP_TVDPLL2_D16] = 68, + [CLK_TOP_MSDCPLL_D2] = 69, + [CLK_TOP_MSDCPLL_D16] = 70, + [CLK_TOP_ETHPLL_D2] = 71, + [CLK_TOP_ETHPLL_D4] = 72, + [CLK_TOP_ETHPLL_D8] = 73, + [CLK_TOP_ETHPLL_D10] = 74, + [CLK_TOP_ADSPPLL_D2] = 75, + [CLK_TOP_ADSPPLL_D4] = 76, + [CLK_TOP_ADSPPLL_D8] = 77, + [CLK_TOP_ULPOSC1_D2] = 78, + [CLK_TOP_ULPOSC1_D4] = 79, + [CLK_TOP_ULPOSC1_D8] = 80, + [CLK_TOP_ULPOSC1_D7] = 81, + [CLK_TOP_ULPOSC1_D10] = 82, + [CLK_TOP_ULPOSC1_D16] = 83, + /* MUX */ + [CLK_TOP_AXI] = 84, + [CLK_TOP_SPM] = 85, + [CLK_TOP_SCP] = 86, + [CLK_TOP_BUS_AXIMEM] = 87, + [CLK_TOP_VPP] = 88, + [CLK_TOP_ETHDR] = 89, + [CLK_TOP_IPE] = 90, + [CLK_TOP_CAM] = 91, + [CLK_TOP_CCU] = 92, + [CLK_TOP_CCU_AHB] = 93, + [CLK_TOP_IMG] = 94, + [CLK_TOP_CAMTM] = 95, + [CLK_TOP_DSP] = 96, + [CLK_TOP_DSP1] = 97, + [CLK_TOP_DSP2] = 98, + [CLK_TOP_DSP3] = 99, + [CLK_TOP_DSP4] = 100, + [CLK_TOP_DSP5] = 101, + [CLK_TOP_DSP6] = 102, + [CLK_TOP_DSP7] = 103, + [CLK_TOP_MFG_CORE_TMP] = 104, + [CLK_TOP_CAMTG] = 105, + [CLK_TOP_CAMTG2] = 106, + [CLK_TOP_CAMTG3] = 107, + [CLK_TOP_UART] = 108, + [CLK_TOP_SPI] = 109, + [CLK_TOP_MSDC50_0_HCLK] = 110, + [CLK_TOP_MSDC50_0] = 111, + [CLK_TOP_MSDC30_1] = 112, + [CLK_TOP_MSDC30_2] = 113, + [CLK_TOP_INTDIR] = 114, + [CLK_TOP_AUD_INTBUS] = 115, + [CLK_TOP_AUDIO_H] = 116, + [CLK_TOP_PWRAP_ULPOSC] = 117, + [CLK_TOP_ATB] = 118, + [CLK_TOP_SSPM] = 119, + [CLK_TOP_DP] = 120, + [CLK_TOP_EDP] = 121, + [CLK_TOP_DPI] = 122, + [CLK_TOP_DISP_PWM0] = 123, + [CLK_TOP_DISP_PWM1] = 124, + [CLK_TOP_USB_TOP] = 125, + [CLK_TOP_SSUSB_XHCI] = 126, + [CLK_TOP_USB_TOP_2P] = 127, + [CLK_TOP_SSUSB_XHCI_2P] = 128, + [CLK_TOP_USB_TOP_3P] = 129, + [CLK_TOP_SSUSB_XHCI_3P] = 130, + [CLK_TOP_I2C] = 131, + [CLK_TOP_SENINF] = 132, + [CLK_TOP_SENINF1] = 133, + [CLK_TOP_GCPU] = 134, + [CLK_TOP_VENC] = 135, + [CLK_TOP_VDEC] = 136, + [CLK_TOP_PWM] = 137, + [CLK_TOP_MCUPM] = 138, + [CLK_TOP_SPMI_P_MST] = 139, + [CLK_TOP_SPMI_M_MST] = 140, + [CLK_TOP_DVFSRC] = 141, + [CLK_TOP_TL] = 142, + [CLK_TOP_AES_MSDCFDE] = 143, + [CLK_TOP_DSI_OCC] = 144, + [CLK_TOP_WPE_VPP] = 145, + [CLK_TOP_HDCP] = 146, + [CLK_TOP_HDCP_24M] = 147, + [CLK_TOP_HDMI_APB] = 148, + [CLK_TOP_SNPS_ETH_250M] = 149, + [CLK_TOP_SNPS_ETH_62P4M_PTP] = 150, + [CLK_TOP_SNPS_ETH_50M_RMII] = 151, + [CLK_TOP_ADSP] = 152, + [CLK_TOP_AUDIO_LOCAL_BUS] = 153, + [CLK_TOP_ASM_H] = 154, + [CLK_TOP_ASM_L] = 155, + [CLK_TOP_APLL1] = 156, + [CLK_TOP_APLL2] = 157, + [CLK_TOP_APLL3] = 158, + [CLK_TOP_APLL4] = 159, + [CLK_TOP_APLL5] = 160, + [CLK_TOP_I2SO1] = 161, + [CLK_TOP_I2SO2] = 162, + [CLK_TOP_I2SI1] = 163, + [CLK_TOP_I2SI2] = 164, + [CLK_TOP_DPTX] = 165, + [CLK_TOP_AUD_IEC] = 166, + [CLK_TOP_A1SYS_HP] = 167, + [CLK_TOP_A2SYS] = 168, + [CLK_TOP_A3SYS] = 169, + [CLK_TOP_A4SYS] = 170, + [CLK_TOP_ECC] = 171, + [CLK_TOP_SPINOR] = 172, + [CLK_TOP_ULPOSC] = 173, + [CLK_TOP_SRCK] = 174, + /* GATE */ + [CLK_TOP_CFGREG_CLOCK_EN_VPP0] = 175, + [CLK_TOP_CFGREG_CLOCK_EN_VPP1] = 176, + [CLK_TOP_CFGREG_CLOCK_EN_VDO0] = 177, + [CLK_TOP_CFGREG_CLOCK_EN_VDO1] = 178, + [CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS] = 179, + [CLK_TOP_CFGREG_F26M_VPP0] = 180, + [CLK_TOP_CFGREG_F26M_VPP1] = 181, + [CLK_TOP_CFGREG_F26M_VDO0] = 182, + [CLK_TOP_CFGREG_F26M_VDO1] = 183, + [CLK_TOP_CFGREG_AUD_F26M_AUD] = 184, + [CLK_TOP_CFGREG_UNIPLL_SES] = 185, + [CLK_TOP_CFGREG_F_PCIE_PHY_REF] = 186, + [CLK_TOP_SSUSB_TOP_REF] = 187, + [CLK_TOP_SSUSB_PHY_REF] = 188, + [CLK_TOP_SSUSB_TOP_P1_REF] = 189, + [CLK_TOP_SSUSB_PHY_P1_REF] = 190, + [CLK_TOP_SSUSB_TOP_P2_REF] = 191, + [CLK_TOP_SSUSB_PHY_P2_REF] = 192, + [CLK_TOP_SSUSB_TOP_P3_REF] = 193, + [CLK_TOP_SSUSB_PHY_P3_REF] = 194, +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x238, + .clr_ofs = 0x238, + .sta_ofs = 0x238, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x250, + .clr_ofs = 0x250, + .sta_ofs = 0x250, +}; + +#define GATE_TOP0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_TOP0E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ + } + +#define GATE_TOP1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT, \ + } + +static const struct mtk_gate topckgen_cg_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, CLK_TOP_VPP, 0), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, CLK_TOP_VPP, 1), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, CLK_TOP_VPP, 2), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, CLK_TOP_VPP, 3), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, CLK_TOP_VPP, 4), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP0, CLK_PAD_CLK26M, 5), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VPP1, CLK_PAD_CLK26M, 6), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO0, CLK_PAD_CLK26M, 7), + GATE_TOP0E(CLK_TOP_CFGREG_F26M_VDO1, CLK_PAD_CLK26M, 8), + GATE_TOP0E(CLK_TOP_CFGREG_AUD_F26M_AUD, CLK_PAD_CLK26M, 9), + GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 15), + GATE_TOP0E(CLK_TOP_CFGREG_F_PCIE_PHY_REF, CLK_PAD_CLK26M, 18), + /* TOP1 */ + GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, CLK_PAD_CLK26M, 0), + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_PAD_CLK26M, 1), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, CLK_PAD_CLK26M, 2), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_PAD_CLK26M, 3), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, CLK_PAD_CLK26M, 4), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_PAD_CLK26M, 5), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, CLK_PAD_CLK26M, 6), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_PAD_CLK26M, 7), }; static const struct mtk_clk_tree mt8188_topckgen_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, - .id_offs_map = mt8188_id_offs_map, - .id_offs_map_size = ARRAY_SIZE(mt8188_id_offs_map), - .fdivs_offs = 8, /* CLK_TOP_MAINPLL_D3 */ - .muxes_offs = 87, /* CLK_TOP_AXI */ + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .id_offs_map = mt8188_id_top_offs_map, + .id_offs_map_size = ARRAY_SIZE(mt8188_id_top_offs_map), + .fdivs_offs = mt8188_id_top_offs_map[CLK_TOP_MAINPLL_D3], + .muxes_offs = mt8188_id_top_offs_map[CLK_TOP_AXI], + .gates_offs = mt8188_id_top_offs_map[CLK_TOP_CFGREG_CLOCK_EN_VPP0], .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, + .gates = topckgen_cg_clks, .num_fclks = ARRAY_SIZE(top_fixed_clks), .num_fdivs = ARRAY_SIZE(top_fixed_divs), .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(topckgen_cg_clks), }; static const struct mtk_gate_regs infra_ao0_cg_regs = { @@ -1412,6 +1462,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO0E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO1(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1420,6 +1478,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO1E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO2(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1428,6 +1494,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO2E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO3(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1436,6 +1510,14 @@ static const struct mtk_gate_regs infra_ao4_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_INFRA_AO3E(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_ao3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + #define GATE_INFRA_AO4(_id, _parent, _shift) { \ .id = _id, \ .parent = _parent, \ @@ -1467,24 +1549,24 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO0(CLK_INFRA_AO_UART2, CLK_TOP_UART, 24), GATE_INFRA_AO0(CLK_INFRA_AO_UART3, CLK_TOP_UART, 25), GATE_INFRA_AO0(CLK_INFRA_AO_UART4, CLK_TOP_UART, 26), - GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_INFRA_AO0E(CLK_INFRA_AO_GCE_26M, CLK_PAD_CLK26M, 27), GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, CLK_TOP_PAD_FPC, 28), GATE_INFRA_AO0(CLK_INFRA_AO_UART5, CLK_TOP_UART, 29), /* INFRA_AO1 */ - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, CLK_TOP_CLK26M, 0), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_26M, CLK_PAD_CLK26M, 0), GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, CLK_TOP_SPI, 1), - GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, CLK_TOP_CLK26M, 2), + GATE_INFRA_AO1E(CLK_INFRA_AO_MSDC0, CLK_PAD_CLK26M, 2), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, CLK_TOP_AXI, 4), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, CLK_TOP_AXI, 5), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, CLK_TOP_MSDC50_0, 6), /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ - GATE_INFRA_AO1(CLK_INFRA_AO_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA_AO1E(CLK_INFRA_AO_DVFSRC, CLK_PAD_CLK26M, 7), GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, CLK_TOP_AXI, 9), - GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA_AO1E(CLK_INFRA_AO_AUXADC, CLK_PAD_CLK26M, 10), GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, CLK_TOP_AXI, 11), - GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, CLK_TOP_CLK32K, 12), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_32K, CLK_PAD_CLK32K, 12), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, CLK_TOP_AXI, 13), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, CLK_TOP_MSDC30_1, 16), GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, CLK_TOP_TL, 18), @@ -1493,14 +1575,14 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, CLK_TOP_AXI, 23), GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, CLK_TOP_AXI, 24), GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, CLK_TOP_AXI, 25), - GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, CLK_TOP_CLK32K, 26), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_32K, CLK_PAD_CLK32K, 26), GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, CLK_TOP_AXI, 29), - GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, CLK_TOP_CLK26M, 31), + GATE_INFRA_AO1E(CLK_INFRA_AO_DRAMC_F26M, CLK_PAD_CLK26M, 31), /* INFRA_AO2 */ GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, CLK_TOP_AXI, 0), GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, CLK_TOP_DISP_PWM0, 2), GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, CLK_TOP_AXI, 3), - GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4), + GATE_INFRA_AO2E(CLK_INFRA_AO_AUDIO_26M_BCLK, CLK_PAD_CLK26M, 4), GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, CLK_TOP_SPI, 6), GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, CLK_TOP_SPI, 9), GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, CLK_TOP_SPI, 10), @@ -1519,14 +1601,14 @@ static const struct mtk_gate infracfg_ao_clks[] = { GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, CLK_TOP_MSDC50_0, 8), GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, CLK_TOP_MSDC30_2, 9), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, CLK_TOP_GCPU, 10), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, CLK_TOP_CLK26M, 15), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_PERI_26M, CLK_PAD_CLK26M, 15), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, CLK_TOP_AXI, 16), GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, CLK_TOP_AXI, 17), GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, CLK_TOP_DISP_PWM1, 20), GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, CLK_TOP_MSDC50_0, 24), /* infra_ao_dapc_sync is for device access permission control module */ GATE_INFRA_AO3(CLK_INFRA_AO_DEVICE_APC_SYNC, CLK_TOP_AXI, 25), - GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_TOP_CLK26M, 26), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_PAD_CLK26M, 26), /* INFRA_AO4 */ /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ GATE_INFRA_AO4(CLK_INFRA_AO_133M_MCLK_CK, CLK_TOP_AXI, 0), @@ -1536,8 +1618,8 @@ static const struct mtk_gate infracfg_ao_clks[] = { }; static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs peri_ao_cg_regs = { @@ -1554,11 +1636,19 @@ static const struct mtk_gate_regs peri_ao_cg_regs = { .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ } +#define GATE_PERI_AOE(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri_ao_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + static const struct mtk_gate pericfg_ao_clks[] = { GATE_PERI_AO(CLK_PERI_AO_ETHERNET, CLK_TOP_AXI, 0), GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, CLK_TOP_AXI, 1), GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, CLK_TOP_AXI, 3), - GATE_PERI_AO(CLK_PERI_AO_FLASHIF_26M, CLK_TOP_CLK26M, 4), + GATE_PERI_AOE(CLK_PERI_AO_FLASHIF_26M, CLK_PAD_CLK26M, 4), GATE_PERI_AO(CLK_PERI_AO_FLASHIFLASHCK, CLK_TOP_SPINOR, 5), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, CLK_TOP_USB_TOP_2P, 9), GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, CLK_TOP_SSUSB_XHCI_2P, 10), @@ -1570,66 +1660,8 @@ static const struct mtk_gate pericfg_ao_clks[] = { }; static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, -}; - -static const struct mtk_gate_regs top0_cg_regs = { - .set_ofs = 0x238, - .clr_ofs = 0x238, - .sta_ofs = 0x238, -}; - -static const struct mtk_gate_regs top1_cg_regs = { - .set_ofs = 0x250, - .clr_ofs = 0x250, - .sta_ofs = 0x250, -}; - -#define GATE_TOP0(_id, _parent, _shift) { \ - .id = _id, \ - .parent = _parent, \ - .regs = &top0_cg_regs, \ - .shift = _shift, \ - .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ - } - -#define GATE_TOP1(_id, _parent, _shift) { \ - .id = _id, \ - .parent = _parent, \ - .regs = &top1_cg_regs, \ - .shift = _shift, \ - .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ - } - -static const struct mtk_gate topckgen_cg_clks[] = { - /* TOP0 */ - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, CLK_TOP_VPP, 0), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, CLK_TOP_VPP, 1), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, CLK_TOP_VPP, 2), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, CLK_TOP_VPP, 3), - GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, CLK_TOP_VPP, 4), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, CLK_TOP_CLK26M, 5), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, CLK_TOP_CLK26M, 6), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, CLK_TOP_CLK26M, 7), - GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, CLK_TOP_CLK26M, 8), - GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, CLK_TOP_CLK26M, 9), - GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 15), - GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, CLK_TOP_CLK26M, 18), - /* TOP1 */ - GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, CLK_TOP_CLK26M, 0), - GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_TOP_CLK26M, 1), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, CLK_TOP_CLK26M, 2), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_TOP_CLK26M, 3), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, CLK_TOP_CLK26M, 4), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_TOP_CLK26M, 5), - GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, CLK_TOP_CLK26M, 6), - GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_TOP_CLK26M, 7), -}; - -static const struct mtk_clk_tree mt8188_topckgen_cg_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { @@ -1663,18 +1695,18 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = { }; const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8188_apmixedsys_probe(struct udevice *dev) @@ -1687,14 +1719,6 @@ static int mt8188_topckgen_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt8188_topckgen_clk_tree); } -static int mt8188_topckgen_cg_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt8188_topckgen_cg_clk_tree, - topckgen_cg_clks, - ARRAY_SIZE(topckgen_cg_clks), - CLK_TOP_CFGREG_CLOCK_EN_VPP0); -} - static int mt8188_infracfg_ao_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt8188_infracfg_ao_clk_tree, @@ -1740,11 +1764,6 @@ static const struct udevice_id mt8188_topckgen_compat[] = { { } }; -static const struct udevice_id mt8188_topckgen_cg_compat[] = { - { .compatible = "mediatek,mt8188-topckgen-cg", }, - { } -}; - static const struct udevice_id mt8188_infracfg_ao_compat[] = { { .compatible = "mediatek,mt8188-infracfg-ao", }, { } @@ -1790,16 +1809,6 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { - .name = "mt8188-topckgen-cg", - .id = UCLASS_CLK, - .of_match = mt8188_topckgen_cg_compat, - .probe = mt8188_topckgen_cg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { .name = "mt8188-infracfg-ao", .id = UCLASS_CLK, diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c new file mode 100644 index 00000000000..fec908728c0 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -0,0 +1,1744 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 MediaTek Inc. + * Author: Chris Chen + * Author: David Lechner + */ + +#include +#include +#include + +#include "clk-mtk.h" + +/* TOPCK MUX SEL REG */ +#define CLK_CFG_UPDATE 0x0004 +#define CLK_CFG_UPDATE1 0x0008 +#define CLK_CFG_UPDATE2 0x000c +#define VLP_CLK_CFG_UPDATE 0x0004 +#define CLK_CFG_0 0x0010 +#define CLK_CFG_0_SET 0x0014 +#define CLK_CFG_0_CLR 0x0018 +#define CLK_CFG_1 0x0020 +#define CLK_CFG_1_SET 0x0024 +#define CLK_CFG_1_CLR 0x0028 +#define CLK_CFG_2 0x0030 +#define CLK_CFG_2_SET 0x0034 +#define CLK_CFG_2_CLR 0x0038 +#define CLK_CFG_3 0x0040 +#define CLK_CFG_3_SET 0x0044 +#define CLK_CFG_3_CLR 0x0048 +#define CLK_CFG_4 0x0050 +#define CLK_CFG_4_SET 0x0054 +#define CLK_CFG_4_CLR 0x0058 +#define CLK_CFG_5 0x0060 +#define CLK_CFG_5_SET 0x0064 +#define CLK_CFG_5_CLR 0x0068 +#define CLK_CFG_6 0x0070 +#define CLK_CFG_6_SET 0x0074 +#define CLK_CFG_6_CLR 0x0078 +#define CLK_CFG_7 0x0080 +#define CLK_CFG_7_SET 0x0084 +#define CLK_CFG_7_CLR 0x0088 +#define CLK_CFG_8 0x0090 +#define CLK_CFG_8_SET 0x0094 +#define CLK_CFG_8_CLR 0x0098 +#define CLK_CFG_9 0x00A0 +#define CLK_CFG_9_SET 0x00A4 +#define CLK_CFG_9_CLR 0x00A8 +#define CLK_CFG_10 0x00B0 +#define CLK_CFG_10_SET 0x00B4 +#define CLK_CFG_10_CLR 0x00B8 +#define CLK_CFG_11 0x00C0 +#define CLK_CFG_11_SET 0x00C4 +#define CLK_CFG_11_CLR 0x00C8 +#define CLK_CFG_12 0x00D0 +#define CLK_CFG_12_SET 0x00D4 +#define CLK_CFG_12_CLR 0x00D8 +#define CLK_CFG_13 0x00E0 +#define CLK_CFG_13_SET 0x00E4 +#define CLK_CFG_13_CLR 0x00E8 +#define CLK_CFG_14 0x00F0 +#define CLK_CFG_14_SET 0x00F4 +#define CLK_CFG_14_CLR 0x00F8 +#define CLK_CFG_15 0x0100 +#define CLK_CFG_15_SET 0x0104 +#define CLK_CFG_15_CLR 0x0108 +#define CLK_CFG_16 0x0110 +#define CLK_CFG_16_SET 0x0114 +#define CLK_CFG_16_CLR 0x0118 +#define CLK_CFG_17 0x0180 +#define CLK_CFG_17_SET 0x0184 +#define CLK_CFG_17_CLR 0x0188 +#define CLK_CFG_18 0x0190 +#define CLK_CFG_18_SET 0x0194 +#define CLK_CFG_18_CLR 0x0198 +#define CLK_CFG_19 0x0240 +#define CLK_CFG_19_SET 0x0244 +#define CLK_CFG_19_CLR 0x0248 +#define CLK_AUDDIV_0 0x0320 +#define CLK_MISC_CFG_3 0x0510 +#define CLK_MISC_CFG_3_SET 0x0514 +#define CLK_MISC_CFG_3_CLR 0x0518 +#define VLP_CLK_CFG_0 0x0008 +#define VLP_CLK_CFG_0_SET 0x000C +#define VLP_CLK_CFG_0_CLR 0x0010 +#define VLP_CLK_CFG_1 0x0014 +#define VLP_CLK_CFG_1_SET 0x0018 +#define VLP_CLK_CFG_1_CLR 0x001C +#define VLP_CLK_CFG_2 0x0020 +#define VLP_CLK_CFG_2_SET 0x0024 +#define VLP_CLK_CFG_2_CLR 0x0028 +#define VLP_CLK_CFG_3 0x002C +#define VLP_CLK_CFG_3_SET 0x0030 +#define VLP_CLK_CFG_3_CLR 0x0034 +#define VLP_CLK_CFG_4 0x0038 +#define VLP_CLK_CFG_4_SET 0x003C +#define VLP_CLK_CFG_4_CLR 0x0040 +#define VLP_CLK_CFG_5 0x0044 +#define VLP_CLK_CFG_5_SET 0x0048 +#define VLP_CLK_CFG_5_CLR 0x004C + +/* TOPCK MUX SHIFT */ +#define TOP_MUX_AXI_SHIFT 0 +#define TOP_MUX_AXI_PERI_SHIFT 1 +#define TOP_MUX_AXI_UFS_SHIFT 2 +#define TOP_MUX_BUS_AXIMEM_SHIFT 3 +#define TOP_MUX_DISP0_SHIFT 4 +#define TOP_MUX_MMINFRA_SHIFT 5 +#define TOP_MUX_UART_SHIFT 6 +#define TOP_MUX_SPI0_SHIFT 7 +#define TOP_MUX_SPI1_SHIFT 8 +#define TOP_MUX_SPI2_SHIFT 9 +#define TOP_MUX_SPI3_SHIFT 10 +#define TOP_MUX_SPI4_SHIFT 11 +#define TOP_MUX_SPI5_SHIFT 12 +#define TOP_MUX_MSDC_MACRO_0P_SHIFT 13 +#define TOP_MUX_MSDC50_0_HCLK_SHIFT 14 +#define TOP_MUX_MSDC50_0_SHIFT 15 +#define TOP_MUX_AES_MSDCFDE_SHIFT 16 +#define TOP_MUX_MSDC_MACRO_1P_SHIFT 17 +#define TOP_MUX_MSDC30_1_SHIFT 18 +#define TOP_MUX_MSDC30_1_HCLK_SHIFT 19 +#define TOP_MUX_MSDC_MACRO_2P_SHIFT 20 +#define TOP_MUX_MSDC30_2_SHIFT 21 +#define TOP_MUX_MSDC30_2_HCLK_SHIFT 22 +#define TOP_MUX_AUD_INTBUS_SHIFT 23 +#define TOP_MUX_ATB_SHIFT 24 +#define TOP_MUX_DISP_PWM_SHIFT 25 +#define TOP_MUX_USB_TOP_P0_SHIFT 26 +#define TOP_MUX_SSUSB_XHCI_P0_SHIFT 27 +#define TOP_MUX_USB_TOP_P1_SHIFT 28 +#define TOP_MUX_SSUSB_XHCI_P1_SHIFT 29 +#define TOP_MUX_USB_TOP_P2_SHIFT 30 +#define TOP_MUX_SSUSB_XHCI_P2_SHIFT 0 +#define TOP_MUX_USB_TOP_P3_SHIFT 1 +#define TOP_MUX_SSUSB_XHCI_P3_SHIFT 2 +#define TOP_MUX_USB_TOP_P4_SHIFT 3 +#define TOP_MUX_SSUSB_XHCI_P4_SHIFT 4 +#define TOP_MUX_I2C_SHIFT 5 +#define TOP_MUX_SENINF_SHIFT 6 +#define TOP_MUX_SENINF1_SHIFT 7 +#define TOP_MUX_AUD_ENGEN1_SHIFT 8 +#define TOP_MUX_AUD_ENGEN2_SHIFT 9 +#define TOP_MUX_AES_UFSFDE_SHIFT 10 +#define TOP_MUX_UFS_SHIFT 11 +#define TOP_MUX_UFS_MBIST_SHIFT 12 +#define TOP_MUX_AUD_1_SHIFT 13 +#define TOP_MUX_AUD_2_SHIFT 14 +#define TOP_MUX_VENC_SHIFT 15 +#define TOP_MUX_VDEC_SHIFT 16 +#define TOP_MUX_PWM_SHIFT 17 +#define TOP_MUX_AUDIO_H_SHIFT 18 +#define TOP_MUX_MCUPM_SHIFT 19 +#define TOP_MUX_MEM_SUB_SHIFT 20 +#define TOP_MUX_MEM_SUB_PERI_SHIFT 21 +#define TOP_MUX_MEM_SUB_UFS_SHIFT 22 +#define TOP_MUX_EMI_N_SHIFT 23 +#define TOP_MUX_DSI_OCC_SHIFT 24 +#define TOP_MUX_AP2CONN_HOST_SHIFT 25 +#define TOP_MUX_IMG1_SHIFT 26 +#define TOP_MUX_IPE_SHIFT 27 +#define TOP_MUX_CAM_SHIFT 28 +#define TOP_MUX_CAMTM_SHIFT 29 +#define TOP_MUX_DSP_SHIFT 30 +#define TOP_MUX_SR_PKA_SHIFT 0 +#define TOP_MUX_DXCC_SHIFT 1 +#define TOP_MUX_MFG_REF_SHIFT 2 +#define TOP_MUX_MDP0_SHIFT 3 +#define TOP_MUX_DP_SHIFT 4 +#define TOP_MUX_EDP_SHIFT 5 +#define TOP_MUX_EDP_FAVT_SHIFT 6 +#define TOP_MUX_SNPS_ETH_250M_SHIFT 7 +#define TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT 8 +#define TOP_MUX_SNPS_ETH_50M_RMII_SHIFT 9 +#define TOP_MUX_SFLASH_SHIFT 10 +#define TOP_MUX_GCPU_SHIFT 11 +#define TOP_MUX_PCIE_MAC_TL_SHIFT 12 +#define TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT 13 +#define TOP_MUX_PLL_DPIX_SHIFT 14 +#define TOP_MUX_ECC_SHIFT 15 +#define TOP_MUX_SCP_SHIFT 0 +#define TOP_MUX_PWRAP_ULPOSC_SHIFT 1 +#define TOP_MUX_SPMI_P_MST_SHIFT 2 +#define TOP_MUX_DVFSRC_SHIFT 3 +#define TOP_MUX_PWM_VLP_SHIFT 4 +#define TOP_MUX_AXI_VLP_SHIFT 5 +#define TOP_MUX_SYSTIMER_26M_SHIFT 6 +#define TOP_MUX_SSPM_SHIFT 7 +#define TOP_MUX_SSPM_F26M_SHIFT 8 +#define TOP_MUX_SRCK_SHIFT 9 +#define TOP_MUX_SCP_SPI_SHIFT 10 +#define TOP_MUX_SCP_IIC_SHIFT 11 +#define TOP_MUX_SCP_SPI_HIGH_SPD_SHIFT 12 +#define TOP_MUX_SCP_IIC_HIGH_SPD_SHIFT 13 +#define TOP_MUX_SSPM_ULPOSC_SHIFT 14 +#define TOP_MUX_APXGPT_26M_SHIFT 15 +#define TOP_MUX_VADSP_SHIFT 16 +#define TOP_MUX_VADSP_VOWPLL_SHIFT 17 +#define TOP_MUX_VADSP_UARTHUB_BCLK_SHIFT 18 +#define TOP_MUX_CAMTG0_SHIFT 19 +#define TOP_MUX_CAMTG1_SHIFT 20 +#define TOP_MUX_CAMTG2_SHIFT 21 +#define TOP_MUX_AUD_ADC_SHIFT 22 +#define TOP_MUX_KP_IRQ_GEN_SHIFT 23 + +/* TOPCK DIVIDER REG */ +#define CLK_AUDDIV_2 0x0328 +#define CLK_AUDDIV_3 0x0334 +#define CLK_AUDDIV_5 0x033C + +/* APMIXED PLL REG */ +#define AP_PLL_CON3 0x00C +#define APLL1_TUNER_CON0 0x040 +#define APLL2_TUNER_CON0 0x044 +#define ARMPLL_LL_CON0 0x204 +#define ARMPLL_LL_CON1 0x208 +#define ARMPLL_LL_CON2 0x20C +#define ARMPLL_LL_CON3 0x210 +#define ARMPLL_BL_CON0 0x214 +#define ARMPLL_BL_CON1 0x218 +#define ARMPLL_BL_CON2 0x21C +#define ARMPLL_BL_CON3 0x220 +#define CCIPLL_CON0 0x224 +#define CCIPLL_CON1 0x228 +#define CCIPLL_CON2 0x22C +#define CCIPLL_CON3 0x230 +#define MAINPLL_CON0 0x304 +#define MAINPLL_CON1 0x308 +#define MAINPLL_CON2 0x30C +#define MAINPLL_CON3 0x310 +#define UNIVPLL_CON0 0x314 +#define UNIVPLL_CON1 0x318 +#define UNIVPLL_CON2 0x31C +#define UNIVPLL_CON3 0x320 +#define MMPLL_CON0 0x324 +#define MMPLL_CON1 0x328 +#define MMPLL_CON2 0x32C +#define MMPLL_CON3 0x330 +#define MFGPLL_CON0 0x504 +#define MFGPLL_CON1 0x508 +#define MFGPLL_CON2 0x50C +#define MFGPLL_CON3 0x510 +#define APLL1_CON0 0x404 +#define APLL1_CON1 0x408 +#define APLL1_CON2 0x40C +#define APLL1_CON3 0x410 +#define APLL1_CON4 0x414 +#define APLL2_CON0 0x418 +#define APLL2_CON1 0x41C +#define APLL2_CON2 0x420 +#define APLL2_CON3 0x424 +#define APLL2_CON4 0x428 +#define EMIPLL_CON0 0x334 +#define EMIPLL_CON1 0x338 +#define EMIPLL_CON2 0x33C +#define EMIPLL_CON3 0x340 +#define APUPLL2_CON0 0x614 +#define APUPLL2_CON1 0x618 +#define APUPLL2_CON2 0x61C +#define APUPLL2_CON3 0x620 +#define APUPLL_CON0 0x604 +#define APUPLL_CON1 0x608 +#define APUPLL_CON2 0x60C +#define APUPLL_CON3 0x610 +#define TVDPLL1_CON0 0x42C +#define TVDPLL1_CON1 0x430 +#define TVDPLL1_CON2 0x434 +#define TVDPLL1_CON3 0x438 +#define TVDPLL2_CON0 0x43C +#define TVDPLL2_CON1 0x440 +#define TVDPLL2_CON2 0x444 +#define TVDPLL2_CON3 0x448 +#define ETHPLL_CON0 0x514 +#define ETHPLL_CON1 0x518 +#define ETHPLL_CON2 0x51C +#define ETHPLL_CON3 0x520 +#define MSDCPLL_CON0 0x524 +#define MSDCPLL_CON1 0x528 +#define MSDCPLL_CON2 0x52C +#define MSDCPLL_CON3 0x530 +#define UFSPLL_CON0 0x534 +#define UFSPLL_CON1 0x538 +#define UFSPLL_CON2 0x53C +#define UFSPLL_CON3 0x540 + +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, + CLK_PAD_ULPOSC, +}; + +static ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_ULPOSC] = 260 * MHZ, +}; + +#define MT8189_PLL_FMAX (3800UL * MHZ) +#define MT8189_PLL_FMIN (1500UL * MHZ) + +#define PLL(_id, _reg, _flags, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift, _pcwbits) \ + { \ + .id = _id, \ + .reg = _reg, \ + .flags = (_flags), \ + .fmax = MT8189_PLL_FMAX, \ + .fmin = MT8189_PLL_FMIN, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL_LL, ARMPLL_LL_CON0, 0, ARMPLL_LL_CON1, 24, ARMPLL_LL_CON1, 0, 22), + PLL(CLK_APMIXED_ARMPLL_BL, ARMPLL_BL_CON0, 0, ARMPLL_BL_CON1, 24, ARMPLL_BL_CON1, 0, 22), + PLL(CLK_APMIXED_CCIPLL, CCIPLL_CON0, 0, CCIPLL_CON1, 24, CCIPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MAINPLL, MAINPLL_CON0, 0, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22), + PLL(CLK_APMIXED_UNIVPLL, UNIVPLL_CON0, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MMPLL, MMPLL_CON0, 0, MMPLL_CON1, 24, MMPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MFGPLL, MFGPLL_CON0, 0, MFGPLL_CON1, 24, MFGPLL_CON1, 0, 22), + PLL(CLK_APMIXED_APLL1, APLL1_CON0, 0, APLL1_CON1, 24, APLL1_CON2, 0, 32), + PLL(CLK_APMIXED_APLL2, APLL2_CON0, 0, APLL2_CON1, 24, APLL2_CON2, 0, 32), + PLL(CLK_APMIXED_EMIPLL, EMIPLL_CON0, 0, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22), + PLL(CLK_APMIXED_APUPLL2, APUPLL2_CON0, 0, APUPLL2_CON1, 24, APUPLL2_CON1, 0, 22), + PLL(CLK_APMIXED_APUPLL, APUPLL_CON0, 0, APUPLL_CON1, 24, APUPLL_CON1, 0, 22), + PLL(CLK_APMIXED_TVDPLL1, TVDPLL1_CON0, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22), + PLL(CLK_APMIXED_TVDPLL2, TVDPLL2_CON0, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22), + PLL(CLK_APMIXED_ETHPLL, ETHPLL_CON0, 0, ETHPLL_CON1, 24, ETHPLL_CON1, 0, 22), + PLL(CLK_APMIXED_MSDCPLL, MSDCPLL_CON0, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22), + PLL(CLK_APMIXED_UFSPLL, UFSPLL_CON0, 0, UFSPLL_CON1, 24, UFSPLL_CON1, 0, 22), +}; + +#define FACTOR0(id, parent, mult, div) \ + FACTOR(id, parent, mult, div, CLK_PARENT_APMIXED) + +#define FACTOR1(id, parent, mult, div) \ + FACTOR(id, parent, mult, div, CLK_PARENT_EXT) + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_MAINPLL_D4_D2, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D4_D4, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_MAINPLL_D4_D8, CLK_APMIXED_MAINPLL, 43, 1375), + FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_MAINPLL_D5_D2, CLK_APMIXED_MAINPLL, 1, 10), + FACTOR0(CLK_TOP_MAINPLL_D5_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_MAINPLL_D5_D8, CLK_APMIXED_MAINPLL, 1, 40), + FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR0(CLK_TOP_MAINPLL_D6_D2, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_MAINPLL_D6_D4, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_MAINPLL_D6_D8, CLK_APMIXED_MAINPLL, 1, 48), + FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR0(CLK_TOP_MAINPLL_D7_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_MAINPLL_D7_D4, CLK_APMIXED_MAINPLL, 1, 28), + FACTOR0(CLK_TOP_MAINPLL_D7_D8, CLK_APMIXED_MAINPLL, 1, 56), + FACTOR0(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), + FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4), + FACTOR0(CLK_TOP_UNIVPLL_D4_D2, CLK_APMIXED_UNIVPLL, 1, 8), + FACTOR0(CLK_TOP_UNIVPLL_D4_D4, CLK_APMIXED_UNIVPLL, 1, 16), + FACTOR0(CLK_TOP_UNIVPLL_D4_D8, CLK_APMIXED_UNIVPLL, 1, 32), + FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), + FACTOR0(CLK_TOP_UNIVPLL_D5_D2, CLK_APMIXED_UNIVPLL, 1, 10), + FACTOR0(CLK_TOP_UNIVPLL_D5_D4, CLK_APMIXED_UNIVPLL, 1, 20), + FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6), + FACTOR0(CLK_TOP_UNIVPLL_D6_D2, CLK_APMIXED_UNIVPLL, 1, 12), + FACTOR0(CLK_TOP_UNIVPLL_D6_D4, CLK_APMIXED_UNIVPLL, 1, 24), + FACTOR0(CLK_TOP_UNIVPLL_D6_D8, CLK_APMIXED_UNIVPLL, 1, 48), + FACTOR0(CLK_TOP_UNIVPLL_D6_D16, CLK_APMIXED_UNIVPLL, 1, 96), + FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), + FACTOR0(CLK_TOP_UNIVPLL_D7_D2, CLK_APMIXED_UNIVPLL, 1, 14), + FACTOR0(CLK_TOP_UNIVPLL_D7_D3, CLK_APMIXED_UNIVPLL, 1, 21), + FACTOR0(CLK_TOP_LVDSTX_DG_CTS, CLK_APMIXED_UNIVPLL, 1, 21), + FACTOR0(CLK_TOP_UNIVPLL_192M, CLK_APMIXED_UNIVPLL, 1, 13), + FACTOR0(CLK_TOP_UNIVPLL_192M_D2, CLK_APMIXED_UNIVPLL, 1, 26), + FACTOR0(CLK_TOP_UNIVPLL_192M_D4, CLK_APMIXED_UNIVPLL, 1, 52), + FACTOR0(CLK_TOP_UNIVPLL_192M_D8, CLK_APMIXED_UNIVPLL, 1, 104), + FACTOR0(CLK_TOP_UNIVPLL_192M_D10, CLK_APMIXED_UNIVPLL, 1, 130), + FACTOR0(CLK_TOP_UNIVPLL_192M_D16, CLK_APMIXED_UNIVPLL, 1, 208), + FACTOR0(CLK_TOP_UNIVPLL_192M_D32, CLK_APMIXED_UNIVPLL, 1, 416), + FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), + FACTOR0(CLK_TOP_MMPLL_D4_D2, CLK_APMIXED_MMPLL, 1, 8), + FACTOR0(CLK_TOP_MMPLL_D4_D4, CLK_APMIXED_MMPLL, 1, 16), + FACTOR0(CLK_TOP_VPLL_DPIX, CLK_APMIXED_MMPLL, 1, 16), + FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), + FACTOR0(CLK_TOP_MMPLL_D5_D2, CLK_APMIXED_MMPLL, 1, 10), + FACTOR0(CLK_TOP_MMPLL_D5_D4, CLK_APMIXED_MMPLL, 1, 20), + FACTOR0(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6), + FACTOR0(CLK_TOP_MMPLL_D6_D2, CLK_APMIXED_MMPLL, 1, 12), + FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), + FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 92, 1473), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 92, 1473), + FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), + FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), + FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR1(CLK_TOP_VOWPLL, CLK_PAD_CLK26M, 1, 1), + FACTOR0(CLK_TOP_UFSPLL_D2, CLK_APMIXED_UFSPLL, 1, 2), + FACTOR1(CLK_TOP_F26M_CK_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR1(CLK_TOP_OSC_D2, CLK_PAD_ULPOSC, 1, 2), + FACTOR1(CLK_TOP_OSC_D4, CLK_PAD_ULPOSC, 1, 4), + FACTOR1(CLK_TOP_OSC_D8, CLK_PAD_ULPOSC, 1, 8), + FACTOR1(CLK_TOP_OSC_D16, CLK_PAD_ULPOSC, 61, 973), + FACTOR1(CLK_TOP_OSC_D3, CLK_PAD_ULPOSC, 1, 3), + FACTOR1(CLK_TOP_OSC_D7, CLK_PAD_ULPOSC, 1, 7), + FACTOR1(CLK_TOP_OSC_D10, CLK_PAD_ULPOSC, 1, 10), + FACTOR1(CLK_TOP_OSC_D20, CLK_PAD_ULPOSC, 1, 20), +}; + +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent axi_peri_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_OSC_D4), +}; + +static const struct mtk_parent axi_u_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_OSC_D8), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent disp0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent mminfra_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + APMIXED_PARENT(CLK_APMIXED_EMIPLL), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent spi5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent msdc_macro_0p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc5hclk_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), +}; + +static const struct mtk_parent aes_msdcfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), +}; + +static const struct mtk_parent msdc_macro_1p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_1_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), +}; + +static const struct mtk_parent msdc_macro_2p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent msdc30_2_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent disp_pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent usb_p0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent usb_p4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent ssusb_xhci_p4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent seninf1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent aud_engen1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), +}; + +static const struct mtk_parent aud_engen2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), +}; + +static const struct mtk_parent aes_ufsfde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent ufs_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ufs_mbist_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UFSPLL_D2), +}; + +static const struct mtk_parent aud_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_APLL1), +}; + +static const struct mtk_parent aud_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_APLL2), +}; + +static const struct mtk_parent venc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent audio_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2), + APMIXED_PARENT(CLK_APMIXED_APLL1), + APMIXED_PARENT(CLK_APMIXED_APLL2), +}; + +static const struct mtk_parent mcupm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent mem_sub_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent mem_sub_peri_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent mem_sub_u_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent emi_n_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + APMIXED_PARENT(CLK_APMIXED_EMIPLL), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent ap2conn_host_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent img1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent ipe_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), +}; + +static const struct mtk_parent cam_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_OSC_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D4), + TOP_PARENT(CLK_TOP_OSC_D3), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent sr_pka_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent dxcc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), +}; + +static const struct mtk_parent mfg_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent mdp0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent dp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), +}; + +static const struct mtk_parent edp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent edp_favt_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent snps_eth_250m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), +}; + +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_APLL2_D3), +}; + +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent sflash_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent pcie_mac_tl_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent vdstx_dg_cts_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_LVDSTX_DG_CTS), + TOP_PARENT(CLK_TOP_UNIVPLL_D7_D3), +}; + +static const struct mtk_parent pll_dpix_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VPLL_DPIX), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), +}; + +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +#define MUX_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _upd_ofs, _upd) \ + MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, -1, _upd_ofs, \ + _upd, CLK_MUX_SETCLR_UPD) + +#define MUX_GATE_CLR_SET_UPD(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, \ + _upd) \ + MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, \ + _upd_ofs, _upd, CLK_MUX_SETCLR_UPD) + +const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, axi_parents, CLK_CFG_0, CLK_CFG_0_SET, + CLK_CFG_0_CLR, 0, 3, CLK_CFG_UPDATE, TOP_MUX_AXI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_AXI_PERI_SEL, axi_peri_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 2, CLK_CFG_UPDATE, + TOP_MUX_AXI_PERI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_AXI_U_SEL, axi_u_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 2, CLK_CFG_UPDATE, + TOP_MUX_AXI_UFS_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL, bus_aximem_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, CLK_CFG_UPDATE, + TOP_MUX_BUS_AXIMEM_SHIFT), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP0_SEL, disp0_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 4, 7, + CLK_CFG_UPDATE, TOP_MUX_DISP0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MMINFRA_SEL, mminfra_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 4, 15, + CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, uart_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 1, 23, + CLK_CFG_UPDATE, TOP_MUX_UART_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI0_SEL, spi0_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_SPI0_SHIFT), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI1_SEL, spi1_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_SPI1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI2_SEL, spi2_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_SPI2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI3_SEL, spi3_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 3, 23, + CLK_CFG_UPDATE, TOP_MUX_SPI3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI4_SEL, spi4_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_SPI4_SHIFT), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI5_SEL, spi5_parents, CLK_CFG_3, + CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_SPI5_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, msdc_macro_0p_parents, + CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_0P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, msdc5hclk_parents, + CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_HCLK_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, CLK_CFG_3, + CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 3, 31, + CLK_CFG_UPDATE, TOP_MUX_MSDC50_0_SHIFT), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, aes_msdcfde_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 3, 7, + CLK_CFG_UPDATE, TOP_MUX_AES_MSDCFDE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, msdc_macro_1p_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_1P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, CLK_CFG_4, + CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, msdc30_1_h_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_1_HCLK_SHIFT), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, msdc_macro_2p_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, + CLK_CFG_UPDATE, TOP_MUX_MSDC_MACRO_2P_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, msdc30_2_parents, CLK_CFG_5, + CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, msdc30_2_h_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_MSDC30_2_HCLK_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_AUD_INTBUS_SHIFT), + /* CLK_CFG_6 */ + MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL, atb_parents, CLK_CFG_6, CLK_CFG_6_SET, + CLK_CFG_6_CLR, 0, 2, CLK_CFG_UPDATE, TOP_MUX_ATB_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, disp_pwm_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 3, 15, + CLK_CFG_UPDATE, TOP_MUX_DISP_PWM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P0_SEL, usb_p0_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P0_SEL, ssusb_xhci_p0_parents, + CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 2, 31, + CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P0_SHIFT), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P1_SEL, usb_p1_parents, CLK_CFG_7, + CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, ssusb_xhci_p1_parents, + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15, + CLK_CFG_UPDATE, TOP_MUX_SSUSB_XHCI_P1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P2_SEL, usb_p2_parents, CLK_CFG_7, + CLK_CFG_7_SET, CLK_CFG_7_CLR, 16, 2, 23, + CLK_CFG_UPDATE, TOP_MUX_USB_TOP_P2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P2_SEL, ssusb_xhci_p2_parents, + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P2_SHIFT), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P3_SEL, usb_p3_parents, CLK_CFG_8, + CLK_CFG_8_SET, CLK_CFG_8_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P3_SEL, ssusb_xhci_p3_parents, + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 8, 2, 15, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P3_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P4_SEL, usb_p4_parents, CLK_CFG_8, + CLK_CFG_8_SET, CLK_CFG_8_CLR, 16, 2, 23, + CLK_CFG_UPDATE1, TOP_MUX_USB_TOP_P4_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P4_SEL, ssusb_xhci_p4_parents, + CLK_CFG_8, CLK_CFG_8_SET, CLK_CFG_8_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_SSUSB_XHCI_P4_SHIFT), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, i2c_parents, CLK_CFG_9, + CLK_CFG_9_SET, CLK_CFG_9_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_I2C_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, seninf_parents, + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_SENINF_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, seninf1_parents, CLK_CFG_9, + CLK_CFG_9_SET, CLK_CFG_9_CLR, 16, 3, 23, + CLK_CFG_UPDATE1, TOP_MUX_SENINF1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, + CLK_CFG_9, CLK_CFG_9_SET, CLK_CFG_9_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN1_SHIFT), + /* CLK_CFG_10 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_AUD_ENGEN2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, aes_ufsfde_parents, + CLK_CFG_10, CLK_CFG_10_SET, CLK_CFG_10_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_AES_UFSFDE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U_SEL, ufs_parents, CLK_CFG_10, + CLK_CFG_10_SET, CLK_CFG_10_CLR, 16, 3, 23, + CLK_CFG_UPDATE1, TOP_MUX_UFS_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_U_MBIST_SEL, ufs_mbist_parents, CLK_CFG_10, + CLK_CFG_10_SET, CLK_CFG_10_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_UFS_MBIST_SHIFT), + /* CLK_CFG_11 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, aud_1_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 0, 1, 7, + CLK_CFG_UPDATE1, TOP_MUX_AUD_1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, aud_2_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 8, 1, 15, + CLK_CFG_UPDATE1, TOP_MUX_AUD_2_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, venc_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 16, 4, 23, + CLK_CFG_UPDATE1, TOP_MUX_VENC_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, vdec_parents, CLK_CFG_11, + CLK_CFG_11_SET, CLK_CFG_11_CLR, 24, 4, 31, + CLK_CFG_UPDATE1, TOP_MUX_VDEC_SHIFT), + /* CLK_CFG_12 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, pwm_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 0, 1, 7, + CLK_CFG_UPDATE1, TOP_MUX_PWM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, audio_h_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 8, 2, 15, + CLK_CFG_UPDATE1, TOP_MUX_AUDIO_H_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, mcupm_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 16, 2, CLK_CFG_UPDATE1, + TOP_MUX_MCUPM_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_SEL, mem_sub_parents, CLK_CFG_12, + CLK_CFG_12_SET, CLK_CFG_12_CLR, 24, 4, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_SHIFT), + /* CLK_CFG_13 */ + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_PERI_SEL, mem_sub_peri_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 0, 3, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_PERI_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_U_SEL, mem_sub_u_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 8, 3, CLK_CFG_UPDATE1, + TOP_MUX_MEM_SUB_UFS_SHIFT), + MUX_CLR_SET_UPD(CLK_TOP_EMI_N_SEL, emi_n_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 16, 3, CLK_CFG_UPDATE1, + TOP_MUX_EMI_N_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, dsi_occ_parents, CLK_CFG_13, + CLK_CFG_13_SET, CLK_CFG_13_CLR, 24, 2, 31, + CLK_CFG_UPDATE1, TOP_MUX_DSI_OCC_SHIFT), + /* CLK_CFG_14 */ + MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST_SEL, ap2conn_host_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 0, 1, CLK_CFG_UPDATE1, + TOP_MUX_AP2CONN_HOST_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, img1_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 8, 4, 15, + CLK_CFG_UPDATE1, TOP_MUX_IMG1_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, ipe_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 16, 4, 23, + CLK_CFG_UPDATE1, TOP_MUX_IPE_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, cam_parents, CLK_CFG_14, + CLK_CFG_14_SET, CLK_CFG_14_CLR, 24, 4, 31, + CLK_CFG_UPDATE1, TOP_MUX_CAM_SHIFT), + /* CLK_CFG_15 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, camtm_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 0, 2, 7, + CLK_CFG_UPDATE1, TOP_MUX_CAMTM_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, dsp_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 8, 3, 15, + CLK_CFG_UPDATE1, TOP_MUX_DSP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SR_PKA_SEL, sr_pka_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 16, 3, 23, + CLK_CFG_UPDATE2, TOP_MUX_SR_PKA_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, dxcc_parents, CLK_CFG_15, + CLK_CFG_15_SET, CLK_CFG_15_CLR, 24, 2, 31, + CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT), + /* CLK_CFG_16 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, mfg_ref_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 0, 2, 7, + CLK_CFG_UPDATE2, TOP_MUX_MFG_REF_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP0_SEL, mdp0_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 8, 4, 15, + CLK_CFG_UPDATE2, TOP_MUX_MDP0_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, dp_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 16, 3, 23, + CLK_CFG_UPDATE2, TOP_MUX_DP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_SEL, edp_parents, CLK_CFG_16, + CLK_CFG_16_SET, CLK_CFG_16_CLR, 24, 3, 31, + CLK_CFG_UPDATE2, TOP_MUX_EDP_SHIFT), + /* CLK_CFG_17 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_FAVT_SEL, edp_favt_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 0, 3, 7, + CLK_CFG_UPDATE2, TOP_MUX_EDP_FAVT_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_250M_SEL, snps_eth_250m_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 8, 1, 15, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_250M_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_62P4M_PTP_SEL, + snps_eth_62p4m_ptp_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 16, 2, 23, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_62P4M_PTP_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_50M_RMII_SEL, + snps_eth_50m_rmii_parents, CLK_CFG_17, + CLK_CFG_17_SET, CLK_CFG_17_CLR, 24, 1, 31, + CLK_CFG_UPDATE2, TOP_MUX_SNPS_ETH_50M_RMII_SHIFT), + /* CLK_CFG_18 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, sflash_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 0, 3, 7, + CLK_CFG_UPDATE2, TOP_MUX_SFLASH_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, gcpu_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 8, 3, 15, + CLK_CFG_UPDATE2, TOP_MUX_GCPU_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MAC_TL_SEL, pcie_mac_tl_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 16, 2, 23, + CLK_CFG_UPDATE2, TOP_MUX_PCIE_MAC_TL_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDSTX_DG_CTS_SEL, vdstx_dg_cts_parents, CLK_CFG_18, + CLK_CFG_18_SET, CLK_CFG_18_CLR, 24, 2, 31, + CLK_CFG_UPDATE2, TOP_MUX_VDSTX_CLKDIG_CTS_SHIFT), + /* CLK_CFG_19 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PLL_DPIX_SEL, pll_dpix_parents, CLK_CFG_19, + CLK_CFG_19_SET, CLK_CFG_19_CLR, 0, 2, 7, + CLK_CFG_UPDATE2, TOP_MUX_PLL_DPIX_SHIFT), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, ecc_parents, CLK_CFG_19, + CLK_CFG_19_SET, CLK_CFG_19_CLR, 8, 3, 15, + CLK_CFG_UPDATE2, TOP_MUX_ECC_SHIFT), +}; + +static const struct mtk_gate_regs top_cg_regs = { + .set_ofs = 0x514, + .clr_ofs = 0x518, + .sta_ofs = 0x510, +}; + +#define GATE_TOP(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + +static const struct mtk_gate top_gates[] = { + GATE_TOP(CLK_TOP_USB2_PHY_RF_P0_EN, CLK_PAD_CLK26M, 7), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P1_EN, CLK_PAD_CLK26M, 10), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P2_EN, CLK_PAD_CLK26M, 11), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P3_EN, CLK_PAD_CLK26M, 12), + GATE_TOP(CLK_TOP_USB2_PHY_RF_P4_EN, CLK_PAD_CLK26M, 13), +}; + +static const struct mtk_gate_regs perao0_cg_regs = { + .set_ofs = 0x24, + .clr_ofs = 0x28, + .sta_ofs = 0x10, +}; + +static const struct mtk_gate_regs perao1_cg_regs = { + .set_ofs = 0x2C, + .clr_ofs = 0x30, + .sta_ofs = 0x14, +}; + +static const struct mtk_gate_regs perao2_cg_regs = { + .set_ofs = 0x34, + .clr_ofs = 0x38, + .sta_ofs = 0x18, +}; + +#define GATE_PERAO0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO0P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +#define GATE_PERAO1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO1P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +#define GATE_PERAO2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_PERAO2P(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &perao2_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +static const struct mtk_gate perao_clks[] = { + /* PERAO0 */ + GATE_PERAO0(CLK_PERAO_UART0, CLK_TOP_UART_SEL, 0), + GATE_PERAO0(CLK_PERAO_UART1, CLK_TOP_UART_SEL, 1), + GATE_PERAO0(CLK_PERAO_UART2, CLK_TOP_UART_SEL, 2), + GATE_PERAO0(CLK_PERAO_UART3, CLK_TOP_UART_SEL, 3), + GATE_PERAO0(CLK_PERAO_PWM_H, CLK_TOP_AXI_PERI_SEL, 4), + GATE_PERAO0(CLK_PERAO_PWM_B, CLK_TOP_PWM_SEL, 5), + GATE_PERAO0(CLK_PERAO_PWM_FB1, CLK_TOP_PWM_SEL, 6), + GATE_PERAO0(CLK_PERAO_PWM_FB2, CLK_TOP_PWM_SEL, 7), + GATE_PERAO0(CLK_PERAO_PWM_FB3, CLK_TOP_PWM_SEL, 8), + GATE_PERAO0(CLK_PERAO_PWM_FB4, CLK_TOP_PWM_SEL, 9), + GATE_PERAO0(CLK_PERAO_DISP_PWM0, CLK_TOP_DISP_PWM_SEL, 10), + GATE_PERAO0(CLK_PERAO_DISP_PWM1, CLK_TOP_DISP_PWM_SEL, 11), + GATE_PERAO0(CLK_PERAO_SPI0_B, CLK_TOP_SPI0_SEL, 12), + GATE_PERAO0(CLK_PERAO_SPI1_B, CLK_TOP_SPI1_SEL, 13), + GATE_PERAO0(CLK_PERAO_SPI2_B, CLK_TOP_SPI2_SEL, 14), + GATE_PERAO0(CLK_PERAO_SPI3_B, CLK_TOP_SPI3_SEL, 15), + GATE_PERAO0(CLK_PERAO_SPI4_B, CLK_TOP_SPI4_SEL, 16), + GATE_PERAO0(CLK_PERAO_SPI5_B, CLK_TOP_SPI5_SEL, 17), + GATE_PERAO0(CLK_PERAO_SPI0_H, CLK_TOP_AXI_PERI_SEL, 18), + GATE_PERAO0(CLK_PERAO_SPI1_H, CLK_TOP_AXI_PERI_SEL, 19), + GATE_PERAO0(CLK_PERAO_SPI2_H, CLK_TOP_AXI_PERI_SEL, 20), + GATE_PERAO0(CLK_PERAO_SPI3_H, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO0(CLK_PERAO_SPI4_H, CLK_TOP_AXI_PERI_SEL, 22), + GATE_PERAO0(CLK_PERAO_SPI5_H, CLK_TOP_AXI_PERI_SEL, 23), + GATE_PERAO0(CLK_PERAO_AXI, CLK_TOP_MEM_SUB_PERI_SEL, 24), + GATE_PERAO0(CLK_PERAO_AHB_APB, CLK_TOP_AXI_PERI_SEL, 25), + GATE_PERAO0(CLK_PERAO_TL, CLK_TOP_MAC_TL_SEL, 26), + GATE_PERAO0P(CLK_PERAO_REF, CLK_PAD_CLK26M, 27), + GATE_PERAO0(CLK_PERAO_I2C, CLK_TOP_AXI_PERI_SEL, 28), + GATE_PERAO0(CLK_PERAO_DMA_B, CLK_TOP_AXI_PERI_SEL, 29), + /* PERAO1 */ + GATE_PERAO1P(CLK_PERAO_SSUSB0_REF, CLK_PAD_CLK26M, 1), + GATE_PERAO1(CLK_PERAO_SSUSB0_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 2), + GATE_PERAO1(CLK_PERAO_SSUSB0_SYS, CLK_TOP_USB_TOP_P0_SEL, 4), + GATE_PERAO1(CLK_PERAO_SSUSB0_XHCI, CLK_TOP_USB_XHCI_P0_SEL, 5), + GATE_PERAO1(CLK_PERAO_SSUSB0_F, CLK_TOP_AXI_PERI_SEL, 6), + GATE_PERAO1(CLK_PERAO_SSUSB0_H, CLK_TOP_AXI_PERI_SEL, 7), + GATE_PERAO1P(CLK_PERAO_SSUSB1_REF, CLK_PAD_CLK26M, 8), + GATE_PERAO1(CLK_PERAO_SSUSB1_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 9), + GATE_PERAO1(CLK_PERAO_SSUSB1_SYS, CLK_TOP_USB_TOP_P1_SEL, 11), + GATE_PERAO1(CLK_PERAO_SSUSB1_XHCI, CLK_TOP_USB_XHCI_P1_SEL, 12), + GATE_PERAO1(CLK_PERAO_SSUSB1_F, CLK_TOP_AXI_PERI_SEL, 13), + GATE_PERAO1(CLK_PERAO_SSUSB1_H, CLK_TOP_AXI_PERI_SEL, 14), + GATE_PERAO1P(CLK_PERAO_SSUSB2_REF, CLK_PAD_CLK26M, 15), + GATE_PERAO1(CLK_PERAO_SSUSB2_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 16), + GATE_PERAO1(CLK_PERAO_SSUSB2_SYS, CLK_TOP_USB_TOP_P2_SEL, 18), + GATE_PERAO1(CLK_PERAO_SSUSB2_XHCI, CLK_TOP_USB_XHCI_P2_SEL, 19), + GATE_PERAO1(CLK_PERAO_SSUSB2_F, CLK_TOP_AXI_PERI_SEL, 20), + GATE_PERAO1(CLK_PERAO_SSUSB2_H, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO1P(CLK_PERAO_SSUSB3_REF, CLK_PAD_CLK26M, 23), + GATE_PERAO1(CLK_PERAO_SSUSB3_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 24), + GATE_PERAO1(CLK_PERAO_SSUSB3_SYS, CLK_TOP_USB_TOP_P3_SEL, 26), + GATE_PERAO1(CLK_PERAO_SSUSB3_XHCI, CLK_TOP_USB_XHCI_P3_SEL, 27), + GATE_PERAO1(CLK_PERAO_SSUSB3_F, CLK_TOP_AXI_PERI_SEL, 28), + GATE_PERAO1(CLK_PERAO_SSUSB3_H, CLK_TOP_AXI_PERI_SEL, 29), + /* PERAO2 */ + GATE_PERAO2P(CLK_PERAO_SSUSB4_REF, CLK_PAD_CLK26M, 0), + GATE_PERAO2(CLK_PERAO_SSUSB4_FRMCNT, CLK_TOP_UNIVPLL_192M_D4, 1), + GATE_PERAO2(CLK_PERAO_SSUSB4_SYS, CLK_TOP_USB_TOP_P4_SEL, 3), + GATE_PERAO2(CLK_PERAO_SSUSB4_XHCI, CLK_TOP_USB_XHCI_P4_SEL, 4), + GATE_PERAO2(CLK_PERAO_SSUSB4_F, CLK_TOP_AXI_PERI_SEL, 5), + GATE_PERAO2(CLK_PERAO_SSUSB4_H, CLK_TOP_AXI_PERI_SEL, 6), + GATE_PERAO2(CLK_PERAO_MSDC0, CLK_TOP_MSDC50_0_SEL, 7), + GATE_PERAO2(CLK_PERAO_MSDC0_H, CLK_TOP_MSDC50_0_HCLK_SEL, 8), + GATE_PERAO2(CLK_PERAO_MSDC0_FAES, CLK_TOP_AES_MSDCFDE_SEL, 9), + GATE_PERAO2(CLK_PERAO_MSDC0_MST_F, CLK_TOP_AXI_PERI_SEL, 10), + GATE_PERAO2(CLK_PERAO_MSDC0_SLV_H, CLK_TOP_AXI_PERI_SEL, 11), + GATE_PERAO2(CLK_PERAO_MSDC1, CLK_TOP_MSDC30_1_SEL, 12), + GATE_PERAO2(CLK_PERAO_MSDC1_H, CLK_TOP_MSDC30_1_HCLK_SEL, 13), + GATE_PERAO2(CLK_PERAO_MSDC1_MST_F, CLK_TOP_AXI_PERI_SEL, 14), + GATE_PERAO2(CLK_PERAO_MSDC1_SLV_H, CLK_TOP_AXI_PERI_SEL, 15), + GATE_PERAO2(CLK_PERAO_MSDC2, CLK_TOP_MSDC30_2_SEL, 16), + GATE_PERAO2(CLK_PERAO_MSDC2_H, CLK_TOP_MSDC30_2_HCLK_SEL, 17), + GATE_PERAO2(CLK_PERAO_MSDC2_MST_F, CLK_TOP_AXI_PERI_SEL, 18), + GATE_PERAO2(CLK_PERAO_MSDC2_SLV_H, CLK_TOP_AXI_PERI_SEL, 19), + GATE_PERAO2(CLK_PERAO_SFLASH, CLK_TOP_SFLASH_SEL, 20), + GATE_PERAO2(CLK_PERAO_SFLASH_F, CLK_TOP_AXI_PERI_SEL, 21), + GATE_PERAO2(CLK_PERAO_SFLASH_H, CLK_TOP_AXI_PERI_SEL, 22), + GATE_PERAO2(CLK_PERAO_SFLASH_P, CLK_TOP_AXI_PERI_SEL, 23), + GATE_PERAO2(CLK_PERAO_AUDIO0, CLK_TOP_AXI_PERI_SEL, 24), + GATE_PERAO2(CLK_PERAO_AUDIO1, CLK_TOP_AXI_PERI_SEL, 25), + GATE_PERAO2(CLK_PERAO_AUDIO2, CLK_TOP_AUD_INTBUS_SEL, 26), + GATE_PERAO2P(CLK_PERAO_AUXADC_26M, CLK_PAD_CLK26M, 27), +}; + +static const struct mtk_gate_regs imp_cg_regs = { + .set_ofs = 0xE08, + .clr_ofs = 0xE04, + .sta_ofs = 0xE00, +}; + +#define GATE_IMP(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &imp_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate imp_clks[] = { + GATE_IMP(CLK_IMPE_I2C0, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPE_I2C1, CLK_TOP_I2C_SEL, 1), + GATE_IMP(CLK_IMPWS_I2C2, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPS_I2C3, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPS_I2C4, CLK_TOP_I2C_SEL, 1), + GATE_IMP(CLK_IMPS_I2C5, CLK_TOP_I2C_SEL, 2), + GATE_IMP(CLK_IMPS_I2C6, CLK_TOP_I2C_SEL, 3), + GATE_IMP(CLK_IMPEN_I2C7, CLK_TOP_I2C_SEL, 0), + GATE_IMP(CLK_IMPEN_I2C8, CLK_TOP_I2C_SEL, 1), +}; + +static const struct mtk_gate_regs mm0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mm1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MM0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mm0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_MM1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mm1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate mm_clks[] = { + /* MM0 */ + GATE_MM0(CLK_MM_DISP_OVL0_4L, CLK_TOP_DISP0_SEL, 0), + GATE_MM0(CLK_MM_DISP_OVL1_4L, CLK_TOP_DISP0_SEL, 1), + GATE_MM0(CLK_MM_VPP_RSZ0, CLK_TOP_DISP0_SEL, 2), + GATE_MM0(CLK_MM_VPP_RSZ1, CLK_TOP_DISP0_SEL, 3), + GATE_MM0(CLK_MM_DISP_RDMA0, CLK_TOP_DISP0_SEL, 4), + GATE_MM0(CLK_MM_DISP_RDMA1, CLK_TOP_DISP0_SEL, 5), + GATE_MM0(CLK_MM_DISP_COLOR0, CLK_TOP_DISP0_SEL, 6), + GATE_MM0(CLK_MM_DISP_COLOR1, CLK_TOP_DISP0_SEL, 7), + GATE_MM0(CLK_MM_DISP_CCORR0, CLK_TOP_DISP0_SEL, 8), + GATE_MM0(CLK_MM_DISP_CCORR1, CLK_TOP_DISP0_SEL, 9), + GATE_MM0(CLK_MM_DISP_CCORR2, CLK_TOP_DISP0_SEL, 10), + GATE_MM0(CLK_MM_DISP_CCORR3, CLK_TOP_DISP0_SEL, 11), + GATE_MM0(CLK_MM_DISP_AAL0, CLK_TOP_DISP0_SEL, 12), + GATE_MM0(CLK_MM_DISP_AAL1, CLK_TOP_DISP0_SEL, 13), + GATE_MM0(CLK_MM_DISP_GAMMA0, CLK_TOP_DISP0_SEL, 14), + GATE_MM0(CLK_MM_DISP_GAMMA1, CLK_TOP_DISP0_SEL, 15), + GATE_MM0(CLK_MM_DISP_DITHER0, CLK_TOP_DISP0_SEL, 16), + GATE_MM0(CLK_MM_DISP_DITHER1, CLK_TOP_DISP0_SEL, 17), + GATE_MM0(CLK_MM_DISP_DSC_WRAP0, CLK_TOP_DISP0_SEL, 18), + GATE_MM0(CLK_MM_VPP_MERGE0, CLK_TOP_DISP0_SEL, 19), + GATE_MM0(CLK_MMSYS_0_DISP_DVO, CLK_TOP_DISP0_SEL, 20), + GATE_MM0(CLK_MMSYS_0_DISP_DSI0, CLK_TOP_DISP0_SEL, 21), + GATE_MM0(CLK_MM_DP_INTF0, CLK_TOP_DISP0_SEL, 22), + GATE_MM0(CLK_MM_DPI0, CLK_TOP_DISP0_SEL, 23), + GATE_MM0(CLK_MM_DISP_WDMA0, CLK_TOP_DISP0_SEL, 24), + GATE_MM0(CLK_MM_DISP_WDMA1, CLK_TOP_DISP0_SEL, 25), + GATE_MM0(CLK_MM_DISP_FAKE_ENG0, CLK_TOP_DISP0_SEL, 26), + GATE_MM0(CLK_MM_DISP_FAKE_ENG1, CLK_TOP_DISP0_SEL, 27), + GATE_MM0(CLK_MM_SMI_LARB, CLK_TOP_DISP0_SEL, 28), + GATE_MM0(CLK_MM_DISP_MUTEX0, CLK_TOP_DISP0_SEL, 29), + GATE_MM0(CLK_MM_DIPSYS_CONFIG, CLK_TOP_DISP0_SEL, 30), + GATE_MM0(CLK_MM_DUMMY, CLK_TOP_DISP0_SEL, 31), + /* MM1 */ + GATE_MM1(CLK_MMSYS_1_DISP_DSI0, CLK_TOP_DSI_OCC_SEL, 0), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER, CLK_TOP_PLL_DPIX_SEL, 1), + GATE_MM1(CLK_MMSYS_1_DPI0, CLK_TOP_PLL_DPIX_SEL, 2), + GATE_MM1(CLK_MMSYS_1_DISP_DVO, CLK_TOP_EDP_SEL, 3), + GATE_MM1(CLK_MM_DP_INTF, CLK_TOP_DP_SEL, 4), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER_CTS, CLK_TOP_VDSTX_DG_CTS_SEL, 5), + GATE_MM1(CLK_MMSYS_1_DISP_DVO_AVT, CLK_TOP_EDP_FAVT_SEL, 6), +}; + +static const struct mtk_gate_regs mminfra_config0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mminfra_config1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MMINFRA_CONFIG0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mminfra_config0_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_MMINFRA_CONFIG1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &mminfra_config1_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate mminfra_config_clks[] = { + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_D, CLK_TOP_MMINFRA_SEL, 0), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_M, CLK_TOP_MMINFRA_SEL, 1), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_SMI, CLK_TOP_MMINFRA_SEL, 2), + GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17), +}; + +static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = { + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .plls = apmixed_plls, + .num_plls = ARRAY_SIZE(apmixed_plls), +}; + +static const struct mtk_clk_tree mt8189_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .fdivs_offs = CLK_TOP_MAINPLL_D3, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_USB2_PHY_RF_P0_EN, + .fdivs = top_fixed_divs, + .muxes = top_muxes, + .gates = top_gates, + .num_fdivs = ARRAY_SIZE(top_fixed_divs), + .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(top_gates), +}; + +static const struct udevice_id mt8189_apmixed[] = { + { .compatible = "mediatek,mt8189-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8189_topckgen_compat[] = { + { .compatible = "mediatek,mt8189-topckgen", }, + { } +}; + +struct mt8189_gate_clk_data { + const struct mtk_gate *gates; + int num_gates; +}; + +#define GATE_CLK_DATA(name) \ +static const struct mt8189_gate_clk_data name##_data = { \ + .gates = name, .num_gates = ARRAY_SIZE(name) \ +} + +GATE_CLK_DATA(perao_clks); +GATE_CLK_DATA(imp_clks); +GATE_CLK_DATA(mm_clks); +GATE_CLK_DATA(mminfra_config_clks); + +static const struct udevice_id of_match_mt8189_clk_gate[] = { + { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data }, + { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data }, + { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data }, + { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data }, + { } +}; + +static int mt8189_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8189_apmixedsys_clk_tree); +} + +static int mt8189_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree); +} + +static int mt8189_clk_gate_probe(struct udevice *dev) +{ + struct mt8189_gate_clk_data *data; + + data = (void *)dev_get_driver_data(dev); + + return mtk_common_clk_gate_init(dev, &mt8189_topckgen_clk_tree, + data->gates, data->num_gates, + data->gates[0].id); +} + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8189-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8189_apmixed, + .probe = mt8189_apmixedsys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8189-topckgen", + .id = UCLASS_CLK, + .of_match = mt8189_topckgen_compat, + .probe = mt8189_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_gate) = { + .name = "mt8189-gate-clk", + .id = UCLASS_CLK, + .of_match = of_match_mt8189_clk_gate, + .probe = mt8189_clk_gate_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c new file mode 100644 index 00000000000..37cceb5f32b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8195.c @@ -0,0 +1,1662 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 MediaTek Inc. + * Author: Chris-qj Chen + * Julien Stephan + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" + +#define MT8195_PLL_FMAX (3800UL * MHZ) +#define MT8195_PLL_FMIN (1500UL * MHZ) +#define MT8195_INTEGER_BITS 8 + +enum { + CLK_PAD_CLK26M, + CLK_PAD_CLK32K, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, + [CLK_PAD_CLK32K] = 32000, +}; + +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,\ + _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8195_PLL_FMAX, \ + .fmin = MT8195_PLL_FMIN, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pcwibits = MT8195_INTEGER_BITS, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_NNAPLL, 0x0390, 0x03a0, 0, 0, 0, 22, 0x0398, 24, + 0x0398, 0, 0x0398), + PLL(CLK_APMIXED_RESPLL, 0x0190, 0x0320, 0, 0, 0, 22, 0x0198, 24, + 0x0198, 0, 0x0198), + PLL(CLK_APMIXED_ETHPLL, 0x0360, 0x0370, 0, 0, 0, 22, 0x0368, 24, + 0x0368, 0, 0x0368), + PLL(CLK_APMIXED_MSDCPLL, 0x0710, 0x0720, 0, 0, 0, 22, 0x0718, 24, + 0x0718, 0, 0x0718), + PLL(CLK_APMIXED_TVDPLL1, 0x00a0, 0x00b0, 0, 0, 0, 22, 0x00a8, 24, + 0x00a8, 0, 0x00a8), + PLL(CLK_APMIXED_TVDPLL2, 0x00c0, 0x00d0, 0, 0, 0, 22, 0x00c8, 24, + 0x00c8, 0, 0x00c8), + PLL(CLK_APMIXED_MMPLL, 0x00e0, 0x00f0, 0xff000000, CLK_PLL_HAVE_RST_BAR, + BIT(23), 22, 0x00e8, 24, 0x00e8, 0, 0x00e8), + PLL(CLK_APMIXED_MAINPLL, 0x01d0, 0x01e0, 0xff000000, CLK_PLL_HAVE_RST_BAR, + BIT(23), 22, 0x01d8, 24, 0x01d8, 0, 0x01d8), + PLL(CLK_APMIXED_VDECPLL, 0x0890, 0x08a0, 0, 0, 0, 22, 0x0898, 24, + 0x0898, 0, 0x0898), + PLL(CLK_APMIXED_IMGPLL, 0x0100, 0x0110, 0, 0, 0, 22, 0x0108, 24, + 0x0108, 0, 0x0108), + PLL(CLK_APMIXED_UNIVPLL, 0x01f0, 0x0700, 0xff000000, CLK_PLL_HAVE_RST_BAR, + BIT(23), 22, 0x01f8, 24, 0x01f8, 0, 0x01f8), + PLL(CLK_APMIXED_HDMIPLL1, 0x08c0, 0x08d0, 0, 0, 0, 22, 0x08c8, 24, + 0x08c8, 0, 0x08c8), + PLL(CLK_APMIXED_HDMIPLL2, 0x0870, 0x0880, 0, 0, 0, 22, 0x0878, 24, + 0x0878, 0, 0x0878), + PLL(CLK_APMIXED_HDMIRX_APLL, 0x08e0, 0x0dd4, 0, 0, 0, 32, 0x08e8, 24, + 0x08ec, 0, 0x08e8), + PLL(CLK_APMIXED_USB1PLL, 0x01a0, 0x01b0, 0, 0, 0, 22, 0x01a8, 24, + 0x01a8, 0, 0x01a8), + PLL(CLK_APMIXED_ADSPPLL, 0x07e0, 0x07f0, 0, 0, 0, 22, 0x07e8, 24, + 0x07e8, 0, 0x07e8), + PLL(CLK_APMIXED_APLL1, 0x07c0, 0x0dc0, 0, 0, 0, 32, 0x07c8, 24, + 0x07cc, 0, 0x07c8), + PLL(CLK_APMIXED_APLL2, 0x0780, 0x0dc4, 0, 0, 0, 32, 0x0788, 24, + 0x078c, 0, 0x0788), + PLL(CLK_APMIXED_APLL3, 0x0760, 0x0dc8, 0, 0, 0, 32, 0x0768, 24, + 0x076c, 0, 0x0768), + PLL(CLK_APMIXED_APLL4, 0x0740, 0x0dcc, 0, 0, 0, 32, 0x0748, 24, + 0x074c, 0, 0x0748), + PLL(CLK_APMIXED_APLL5, 0x07a0, 0x0dd0, 0x100000, 0, 0, 32, 0x07a8, 24, + 0x07ac, 0, 0x07a8), + PLL(CLK_APMIXED_MFGPLL, 0x0340, 0x0350, 0, 0, 0, 22, 0x0348, 24, + 0x0348, 0, 0x0348), + PLL(CLK_APMIXED_DGIPLL, 0x0150, 0x0160, 0, 0, 0, 22, 0x0158, 24, + 0x0158, 0, 0x0158), +}; + +static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = { + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .plls = apmixed_plls, + .num_plls = ARRAY_SIZE(apmixed_plls), +}; + +#define FIXED_CLK0(_id, _rate) \ + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK0(CLK_TOP_IN_DGI, 165000000), + FIXED_CLK0(CLK_TOP_ULPOSC1, 248000000), + FIXED_CLK0(CLK_TOP_ULPOSC2, 326000000), + FIXED_CLK0(CLK_TOP_MEM_466M, 533000000), + FIXED_CLK0(CLK_TOP_MPHONE_SLAVE_B, 49152000), + FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000), + FIXED_CLK0(CLK_TOP_UFS_RX_SYMBOL, 166000000), + FIXED_CLK0(CLK_TOP_UFS_TX_SYMBOL, 166000000), + FIXED_CLK0(CLK_TOP_SSUSB_U3PHY_P1_P_P0, 131000000), + FIXED_CLK0(CLK_TOP_UFS_RX_SYMBOL1, 166000000), + FIXED_CLK0(CLK_TOP_FPC, 50000000), + FIXED_CLK0(CLK_TOP_HDMIRX_P, 594000000), +}; + +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR2(CLK_TOP_CLK26M_D52, CLK_PAD_CLK26M, 1, 52), + FACTOR1(CLK_TOP_IN_DGI_D2, CLK_TOP_IN_DGI, 1, 2), + FACTOR1(CLK_TOP_IN_DGI_D4, CLK_TOP_IN_DGI, 1, 4), + FACTOR1(CLK_TOP_IN_DGI_D6, CLK_TOP_IN_DGI, 1, 6), + FACTOR1(CLK_TOP_IN_DGI_D8, CLK_TOP_IN_DGI, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D4_D2, CLK_TOP_MAINPLL_D4, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D4_D4, CLK_TOP_MAINPLL_D4, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D4_D8, CLK_TOP_MAINPLL_D4, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR1(CLK_TOP_MAINPLL_D5_D2, CLK_TOP_MAINPLL_D5, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D5_D4, CLK_TOP_MAINPLL_D5, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D5_D8, CLK_TOP_MAINPLL_D5, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR1(CLK_TOP_MAINPLL_D6_D2, CLK_TOP_MAINPLL_D6, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D6_D4, CLK_TOP_MAINPLL_D6, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D6_D8, CLK_TOP_MAINPLL_D6, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR1(CLK_TOP_MAINPLL_D7_D2, CLK_TOP_MAINPLL_D7, 1, 2), + FACTOR1(CLK_TOP_MAINPLL_D7_D4, CLK_TOP_MAINPLL_D7, 1, 4), + FACTOR1(CLK_TOP_MAINPLL_D7_D8, CLK_TOP_MAINPLL_D7, 1, 8), + FACTOR0(CLK_TOP_MAINPLL_D9, CLK_APMIXED_MAINPLL, 1, 9), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), + FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D4_D2, CLK_TOP_UNIVPLL_D4, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D4_D4, CLK_TOP_UNIVPLL_D4, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D4_D8, CLK_TOP_UNIVPLL_D4, 1, 8), + FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1, 8), + FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL_D6_D2, CLK_TOP_UNIVPLL_D6, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D6_D4, CLK_TOP_UNIVPLL_D6, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_D6_D8, CLK_TOP_UNIVPLL_D6, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL_D6_D16, CLK_TOP_UNIVPLL_D6, 1, 16), + FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), + FACTOR0(CLK_TOP_UNIVPLL_192M, CLK_APMIXED_UNIVPLL, 1, 13), + FACTOR1(CLK_TOP_UNIVPLL_192M_D4, CLK_TOP_UNIVPLL_192M, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL_192M_D8, CLK_TOP_UNIVPLL_192M, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL_192M_D16, CLK_TOP_UNIVPLL_192M, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL_192M_D32, CLK_TOP_UNIVPLL_192M, 1, 32), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4), + FACTOR0(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4), + FACTOR0(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4), + FACTOR0(CLK_TOP_HDMIRX_APLL_D3, CLK_APMIXED_HDMIRX_APLL, 1, 3), + FACTOR0(CLK_TOP_HDMIRX_APLL_D4, CLK_APMIXED_HDMIRX_APLL, 1, 4), + FACTOR0(CLK_TOP_HDMIRX_APLL_D6, CLK_APMIXED_HDMIRX_APLL, 1, 6), + FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4), + FACTOR1(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, 2), + FACTOR1(CLK_TOP_MMPLL_D4_D4, CLK_TOP_MMPLL_D4, 1, 4), + FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5), + FACTOR1(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1, 2), + FACTOR1(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1, 4), + FACTOR0(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6), + FACTOR1(CLK_TOP_MMPLL_D6_D2, CLK_TOP_MMPLL_D6, 1, 2), + FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7), + FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9), + FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2), + FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4), + FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8), + FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 1, 16), + FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2), + FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4), + FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8), + FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4), + FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16), + FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2), + FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8), + FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10), + FACTOR0(CLK_TOP_DGIPLL_D2, CLK_APMIXED_DGIPLL, 1, 2), + FACTOR1(CLK_TOP_ULPOSC1_D2, CLK_TOP_ULPOSC1, 1, 2), + FACTOR1(CLK_TOP_ULPOSC1_D4, CLK_TOP_ULPOSC1, 1, 4), + FACTOR1(CLK_TOP_ULPOSC1_D7, CLK_TOP_ULPOSC1, 1, 7), + FACTOR1(CLK_TOP_ULPOSC1_D8, CLK_TOP_ULPOSC1, 1, 8), + FACTOR1(CLK_TOP_ULPOSC1_D10, CLK_TOP_ULPOSC1, 1, 10), + FACTOR1(CLK_TOP_ULPOSC1_D16, CLK_TOP_ULPOSC1, 1, 16), + FACTOR0(CLK_TOP_ADSPPLL_D2, CLK_APMIXED_ADSPPLL, 1, 2), + FACTOR0(CLK_TOP_ADSPPLL_D4, CLK_APMIXED_ADSPPLL, 1, 4), + FACTOR0(CLK_TOP_ADSPPLL_D8, CLK_APMIXED_ADSPPLL, 1, 8), +}; + +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), +}; + +static const struct mtk_parent spm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + EXT_PARENT(CLK_PAD_CLK32K), +}; + +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent bus_aximem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ethdr_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D5_D4), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + APMIXED_PARENT(CLK_APMIXED_TVDPLL2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent ipe_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent cam_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), +}; + +static const struct mtk_parent ccu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent img_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_IMGPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent camtm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent dsp2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), +}; + +static const struct mtk_parent ipu_if_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), +}; + +static const struct mtk_parent mfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), +}; + +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent spis_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent msdc50_0_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent msdc30_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent intdir_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent audio_h_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), +}; + +static const struct mtk_parent pwrap_ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), +}; + +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent pwrmcu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D9), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), +}; + +static const struct mtk_parent dp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL1_D2), + TOP_PARENT(CLK_TOP_TVDPLL2_D2), + TOP_PARENT(CLK_TOP_TVDPLL1_D4), + TOP_PARENT(CLK_TOP_TVDPLL2_D4), + TOP_PARENT(CLK_TOP_TVDPLL1_D8), + TOP_PARENT(CLK_TOP_TVDPLL2_D8), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_TVDPLL2_D16), +}; + +static const struct mtk_parent disp_pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), +}; + +static const struct mtk_parent usb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent seninf_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), +}; + +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), +}; + +static const struct mtk_parent dxcc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), +}; + +static const struct mtk_parent dpmaif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent aes_fde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent ufs_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent ufs_tick1us_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D52), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_parent ufs_mp_sap_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent venc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), +}; + +static const struct mtk_parent vdec_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D5), + APMIXED_PARENT(CLK_APMIXED_VDECPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MMPLL_D9), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), +}; + +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent mcupm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), +}; + +static const struct mtk_parent spmi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_ULPOSC1_D8), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_ULPOSC1_D16), + TOP_PARENT(CLK_TOP_ULPOSC1_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent dvfsrc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_MSDCPLL_D16), +}; + +static const struct mtk_parent tl_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), +}; + +static const struct mtk_parent dsi_occ_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), +}; + +static const struct mtk_parent wpe_vpp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + APMIXED_PARENT(CLK_APMIXED_TVDPLL1), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), +}; + +static const struct mtk_parent hdcp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), +}; + +static const struct mtk_parent hdcp_24m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent hd20_dacr_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), +}; + +static const struct mtk_parent hd20_hdcp_c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent hdmi_xtal_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), +}; + +static const struct mtk_parent hdmi_apb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), +}; + +static const struct mtk_parent snps_eth_250m_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D2), +}; + +static const struct mtk_parent snps_eth_62p4m_ptp_parents[] = { + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL1_D3), + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D8), +}; + +static const struct mtk_parent snps_eth_50m_rmii_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent dgi_out_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_DGIPLL), + TOP_PARENT(CLK_TOP_DGIPLL_D2), + TOP_PARENT(CLK_TOP_IN_DGI), + TOP_PARENT(CLK_TOP_IN_DGI_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), +}; + +static const struct mtk_parent nna_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + APMIXED_PARENT(CLK_APMIXED_NNAPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_MMPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), +}; + +static const struct mtk_parent adsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D4_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + APMIXED_PARENT(CLK_APMIXED_ADSPPLL), + TOP_PARENT(CLK_TOP_ADSPPLL_D2), + TOP_PARENT(CLK_TOP_ADSPPLL_D4), + TOP_PARENT(CLK_TOP_ADSPPLL_D8), +}; + +static const struct mtk_parent asm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), +}; + +static const struct mtk_parent apll1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), +}; + +static const struct mtk_parent apll2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent apll3_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), +}; + +static const struct mtk_parent apll4_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL4_D4), +}; + +static const struct mtk_parent apll5_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL5_D4), +}; + +static const struct mtk_parent i2s_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL3), + TOP_PARENT(CLK_TOP_APLL4), + TOP_PARENT(CLK_TOP_APLL5), + APMIXED_PARENT(CLK_APMIXED_HDMIRX_APLL), +}; + +static const struct mtk_parent a1sys_hp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D4), +}; + +static const struct mtk_parent a2sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent a3sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL3_D4), + TOP_PARENT(CLK_TOP_APLL4_D4), + TOP_PARENT(CLK_TOP_APLL5_D4), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D3), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D4), + TOP_PARENT(CLK_TOP_HDMIRX_APLL_D6), +}; + +static const struct mtk_parent spinfi_b_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), +}; + +static const struct mtk_parent nfi1x_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), +}; + +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), +}; + +static const struct mtk_parent audio_local_bus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ULPOSC1_D4), + TOP_PARENT(CLK_TOP_ULPOSC1_D2), +}; + +static const struct mtk_parent spinor_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), +}; + +static const struct mtk_parent dvio_dgi_ref_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_IN_DGI), + TOP_PARENT(CLK_TOP_IN_DGI_D2), + TOP_PARENT(CLK_TOP_IN_DGI_D4), + TOP_PARENT(CLK_TOP_IN_DGI_D6), + TOP_PARENT(CLK_TOP_IN_DGI_D8), + TOP_PARENT(CLK_TOP_MMPLL_D4_D4), +}; + +static const struct mtk_parent ulposc_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1), + TOP_PARENT(CLK_TOP_ETHPLL_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent ulposc_core_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC2), + TOP_PARENT(CLK_TOP_UNIVPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_ETHPLL_D10), +}; + +static const struct mtk_parent srck_parents[] = { + TOP_PARENT(CLK_TOP_ULPOSC1_D10), + EXT_PARENT(CLK_PAD_CLK26M), +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE(CLK_TOP_AXI, axi_parents, 0x020, 0, 3, 7), + MUX_GATE(CLK_TOP_SPM, spm_parents, 0x020, 8, 2, 15), + MUX_GATE(CLK_TOP_SCP, scp_parents, 0x020, 16, 3, 23), + MUX_GATE(CLK_TOP_BUS_AXIMEM, bus_aximem_parents, 0x020, 24, 3, 31), + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_VPP, vpp_parents, 0x02C, 0, 4, 7), + MUX_GATE(CLK_TOP_ETHDR, ethdr_parents, 0x02C, 8, 4, 15), + MUX_GATE(CLK_TOP_IPE, ipe_parents, 0x02C, 16, 4, 23), + MUX_GATE(CLK_TOP_CAM, cam_parents, 0x02C, 24, 4, 31), + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_CCU, ccu_parents, 0x038, 0, 4, 7), + MUX_GATE(CLK_TOP_IMG, img_parents, 0x038, 8, 4, 15), + MUX_GATE(CLK_TOP_CAMTM, camtm_parents, 0x038, 16, 2, 23), + MUX_GATE(CLK_TOP_DSP, dsp_parents, 0x038, 24, 3, 31), + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_DSP1, dsp1_parents, 0x044, 0, 3, 7), + MUX_GATE(CLK_TOP_DSP2, dsp1_parents, 0x044, 8, 3, 15), + MUX_GATE(CLK_TOP_DSP3, dsp1_parents, 0x044, 16, 3, 23), + MUX_GATE(CLK_TOP_DSP4, dsp2_parents, 0x044, 24, 3, 31), + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_DSP5, dsp2_parents, 0x050, 0, 3, 7), + MUX_GATE(CLK_TOP_DSP6, dsp2_parents, 0x050, 8, 3, 15), + MUX_GATE(CLK_TOP_DSP7, dsp_parents, 0x050, 16, 3, 23), + MUX_GATE(CLK_TOP_IPU_IF, ipu_if_parents, 0x050, 24, 3, 31), + /* CLK_CFG_5 */ + MUX_GATE(CLK_TOP_MFG_CORE_TMP, mfg_parents, 0x05C, 0, 2, 7), + MUX_GATE(CLK_TOP_CAMTG, camtg_parents, 0x05C, 8, 3, 15), + MUX_GATE(CLK_TOP_CAMTG2, camtg_parents, 0x05C, 16, 3, 23), + MUX_GATE(CLK_TOP_CAMTG3, camtg_parents, 0x05C, 24, 3, 31), + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_CAMTG4, camtg_parents, 0x068, 0, 3, 7), + MUX_GATE(CLK_TOP_CAMTG5, camtg_parents, 0x068, 8, 3, 15), + MUX_GATE(CLK_TOP_UART, uart_parents, 0x068, 16, 1, 23), + MUX_GATE(CLK_TOP_SPI, spi_parents, 0x068, 24, 3, 31), + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_SPIS, spis_parents, 0x074, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC50_0_HCLK, msdc50_0_h_parents, 0x074, 8, 2, 15), + MUX_GATE(CLK_TOP_MSDC50_0, msdc50_0_parents, 0x074, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC30_1, msdc30_parents, 0x074, 24, 3, 31), + /* CLK_CFG_8 */ + MUX_GATE(CLK_TOP_MSDC30_2, msdc30_parents, 0x080, 0, 3, 7), + MUX_GATE(CLK_TOP_INTDIR, intdir_parents, 0x080, 8, 2, 15), + MUX_GATE(CLK_TOP_AUD_INTBUS, aud_intbus_parents, 0x080, 16, 2, 23), + MUX_GATE(CLK_TOP_AUDIO_H, audio_h_parents, 0x080, 24, 2, 31), + /* CLK_CFG_9 */ + MUX_GATE(CLK_TOP_PWRAP_ULPOSC, pwrap_ulposc_parents, 0x08C, 0, 3, 7), + MUX_GATE(CLK_TOP_ATB, atb_parents, 0x08C, 8, 2, 15), + MUX_GATE(CLK_TOP_PWRMCU, pwrmcu_parents, 0x08C, 16, 3, 23), + MUX_GATE(CLK_TOP_DP, dp_parents, 0x08C, 24, 4, 31), + /* CLK_CFG_10 */ + MUX_GATE(CLK_TOP_EDP, dp_parents, 0x098, 0, 4, 7), + MUX_GATE(CLK_TOP_DPI, dp_parents, 0x098, 8, 4, 15), + MUX_GATE(CLK_TOP_DISP_PWM0, disp_pwm_parents, 0x098, 16, 3, 23), + MUX_GATE(CLK_TOP_DISP_PWM1, disp_pwm_parents, 0x098, 24, 3, 31), + /* CLK_CFG_11 */ + MUX_GATE(CLK_TOP_USB_TOP, usb_parents, 0x0A4, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_XHCI, usb_parents, 0x0A4, 8, 2, 15), + MUX_GATE(CLK_TOP_USB_TOP_1P, usb_parents, 0x0A4, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_XHCI_1P, usb_parents, 0x0A4, 24, 2, 31), + /* CLK_CFG_12 */ + MUX_GATE(CLK_TOP_USB_TOP_2P, usb_parents, 0x0B0, 0, 2, 7), + MUX_GATE(CLK_TOP_SSUSB_XHCI_2P, usb_parents, 0x0B0, 8, 2, 15), + MUX_GATE(CLK_TOP_USB_TOP_3P, usb_parents, 0x0B0, 16, 2, 23), + MUX_GATE(CLK_TOP_SSUSB_XHCI_3P, usb_parents, 0x0B0, 24, 2, 31), + /* CLK_CFG_13 */ + MUX_GATE(CLK_TOP_I2C, i2c_parents, 0x0BC, 0, 2, 7), + MUX_GATE(CLK_TOP_SENINF, seninf_parents, 0x0BC, 8, 3, 15), + MUX_GATE(CLK_TOP_SENINF1, seninf_parents, 0x0BC, 16, 3, 23), + MUX_GATE(CLK_TOP_SENINF2, seninf_parents, 0x0BC, 24, 3, 31), + /* CLK_CFG_14 */ + MUX_GATE(CLK_TOP_SENINF3, seninf_parents, 0x0C8, 0, 3, 7), + MUX_GATE(CLK_TOP_GCPU, gcpu_parents, 0x0C8, 8, 3, 15), + MUX_GATE(CLK_TOP_DXCC, dxcc_parents, 0x0C8, 16, 2, 23), + MUX_GATE(CLK_TOP_DPMAIF_MAIN, dpmaif_parents, 0x0C8, 24, 3, 31), + /* CLK_CFG_15 */ + MUX_GATE(CLK_TOP_AES_UFSFDE, aes_fde_parents, 0x0D4, 0, 3, 7), + MUX_GATE(CLK_TOP_UFS, ufs_parents, 0x0D4, 8, 3, 15), + MUX_GATE(CLK_TOP_UFS_TICK1US, ufs_tick1us_parents, 0x0D4, 16, 1, 23), + MUX_GATE(CLK_TOP_UFS_MP_SAP_CFG, ufs_mp_sap_parents, 0x0D4, 24, 1, 31), + /* CLK_CFG_16 */ + MUX_GATE(CLK_TOP_VENC, venc_parents, 0x0E0, 0, 4, 7), + MUX_GATE(CLK_TOP_VDEC, vdec_parents, 0x0E0, 8, 4, 15), + MUX_GATE(CLK_TOP_PWM, pwm_parents, 0x0E0, 16, 1, 23), + MUX_GATE(CLK_TOP_MCUPM, mcupm_parents, 0x0E0, 24, 2, 31), + /* CLK_CFG_17 */ + MUX_GATE(CLK_TOP_SPMI_P_MST, spmi_parents, 0x0EC, 0, 4, 7), + MUX_GATE(CLK_TOP_SPMI_M_MST, spmi_parents, 0x0EC, 8, 4, 15), + MUX_GATE(CLK_TOP_DVFSRC, dvfsrc_parents, 0x0EC, 16, 2, 23), + MUX_GATE(CLK_TOP_TL, tl_parents, 0x0EC, 24, 2, 31), + /* CLK_CFG_18 */ + MUX_GATE(CLK_TOP_TL_P1, tl_parents, 0x0F8, 0, 2, 7), + MUX_GATE(CLK_TOP_AES_MSDCFDE, aes_fde_parents, 0x0F8, 8, 3, 15), + MUX_GATE(CLK_TOP_DSI_OCC, dsi_occ_parents, 0x0F8, 16, 2, 23), + MUX_GATE(CLK_TOP_WPE_VPP, wpe_vpp_parents, 0x0F8, 24, 4, 31), + /* CLK_CFG_19 */ + MUX_GATE(CLK_TOP_HDCP, hdcp_parents, 0x0104, 0, 2, 7), + MUX_GATE(CLK_TOP_HDCP_24M, hdcp_24m_parents, 0x0104, 8, 2, 15), + MUX_GATE(CLK_TOP_HD20_DACR_REF_CLK, hd20_dacr_ref_parents, 0x0104, 16, 2, 23), + MUX_GATE(CLK_TOP_HD20_HDCP_CCLK, hd20_hdcp_c_parents, 0x0104, 24, 2, 31), + /* CLK_CFG_20 */ + MUX_GATE(CLK_TOP_HDMI_XTAL, hdmi_xtal_parents, 0x0110, 0, 1, 7), + MUX_GATE(CLK_TOP_HDMI_APB, hdmi_apb_parents, 0x0110, 8, 2, 15), + MUX_GATE(CLK_TOP_SNPS_ETH_250M, snps_eth_250m_parents, 0x0110, 16, 1, 23), + MUX_GATE(CLK_TOP_SNPS_ETH_62P4M_PTP, snps_eth_62p4m_ptp_parents, 0x0110, 24, 2, 31), + /* CLK_CFG_21 */ + MUX_GATE(CLK_TOP_SNPS_ETH_50M_RMII, snps_eth_50m_rmii_parents, 0x011C, 0, 1, 7), + MUX_GATE(CLK_TOP_DGI_OUT, dgi_out_parents, 0x011C, 8, 3, 15), + MUX_GATE(CLK_TOP_NNA0, nna_parents, 0x011C, 16, 4, 23), + MUX_GATE(CLK_TOP_NNA1, nna_parents, 0x011C, 24, 4, 31), + /* CLK_CFG_22 */ + MUX_GATE(CLK_TOP_ADSP, adsp_parents, 0x0128, 0, 4, 7), + MUX_GATE(CLK_TOP_ASM_H, asm_parents, 0x0128, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_M, asm_parents, 0x0128, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_L, asm_parents, 0x0128, 24, 2, 31), + /* CLK_CFG_23 */ + MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0134, 0, 1, 7), + MUX_GATE(CLK_TOP_APLL2, apll2_parents, 0x0134, 8, 1, 15), + MUX_GATE(CLK_TOP_APLL3, apll3_parents, 0x0134, 16, 1, 23), + MUX_GATE(CLK_TOP_APLL4, apll4_parents, 0x0134, 24, 1, 31), + /* + * CLK_CFG_24 + * i2so4_mck is not used in MT8195. + */ + MUX_GATE(CLK_TOP_APLL5, apll5_parents, 0x0140, 0, 1, 7), + MUX_GATE(CLK_TOP_I2SO1_MCK, i2s_parents, 0x0140, 8, 3, 15), + MUX_GATE(CLK_TOP_I2SO2_MCK, i2s_parents, 0x0140, 16, 3, 23), + /* + * CLK_CFG_25 + * i2so5_mck and i2si4_mck are not used in MT8195. + */ + MUX_GATE(CLK_TOP_I2SI1_MCK, i2s_parents, 0x014C, 8, 3, 15), + MUX_GATE(CLK_TOP_I2SI2_MCK, i2s_parents, 0x014C, 16, 3, 23), + /* + * CLK_CFG_26 + * i2si5_mck is not used in MT8195. + */ + MUX_GATE(CLK_TOP_DPTX_MCK, i2s_parents, 0x0158, 8, 3, 15), + MUX_GATE(CLK_TOP_AUD_IEC_CLK, i2s_parents, 0x0158, 16, 3, 23), + MUX_GATE(CLK_TOP_A1SYS_HP, a1sys_hp_parents, 0x0158, 24, 1, 31), + /* CLK_CFG_27 */ + MUX_GATE(CLK_TOP_A2SYS_HF, a2sys_parents, 0x0164, 0, 1, 7), + MUX_GATE(CLK_TOP_A3SYS_HF, a3sys_parents, 0x0164, 8, 3, 15), + MUX_GATE(CLK_TOP_A4SYS_HF, a3sys_parents, 0x0164, 16, 3, 23), + MUX_GATE(CLK_TOP_SPINFI_BCLK, spinfi_b_parents, 0x0164, 24, 3, 31), + /* CLK_CFG_28 */ + MUX_GATE(CLK_TOP_NFI1X, nfi1x_parents, 0x0170, 0, 3, 7), + MUX_GATE(CLK_TOP_ECC, ecc_parents, 0x0170, 8, 3, 15), + MUX_GATE(CLK_TOP_AUDIO_LOCAL_BUS, audio_local_bus_parents, 0x0170, 16, 4, 23), + MUX_GATE(CLK_TOP_SPINOR, spinor_parents, 0x0170, 24, 2, 31), + /* CLK_CFG_29 */ + MUX_GATE(CLK_TOP_DVIO_DGI_REF, dvio_dgi_ref_parents, 0x017C, 0, 3, 7), + MUX_GATE(CLK_TOP_ULPOSC, ulposc_parents, 0x017C, 8, 2, 15), + MUX_GATE(CLK_TOP_ULPOSC_CORE, ulposc_core_parents, 0x017C, 16, 2, 23), + MUX_GATE(CLK_TOP_SRCK, srck_parents, 0x017C, 24, 1, 31), +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x238, + .clr_ofs = 0x238, + .sta_ofs = 0x238, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x250, + .clr_ofs = 0x250, + .sta_ofs = 0x250, +}; + +#define GATE_TOP0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top0_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN) + +#define GATE_TOP0E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top0_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + +#define GATE_TOP1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &top1_cg_regs, _shift, \ + CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT) + +static const struct mtk_gate top_cg_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CFG_VPP0, CLK_TOP_VPP, 0), + GATE_TOP0(CLK_TOP_CFG_VPP1, CLK_TOP_VPP, 1), + GATE_TOP0(CLK_TOP_CFG_VDO0, CLK_TOP_VPP, 2), + GATE_TOP0(CLK_TOP_CFG_VDO1, CLK_TOP_VPP, 3), + GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, CLK_TOP_UNIVPLL_D2, 4), + GATE_TOP0E(CLK_TOP_CFG_26M_VPP0, CLK_PAD_CLK26M, 5), + GATE_TOP0E(CLK_TOP_CFG_26M_VPP1, CLK_PAD_CLK26M, 6), + GATE_TOP0E(CLK_TOP_CFG_26M_AUD, CLK_PAD_CLK26M, 9), + /* + * cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south + * are peripheral bus clock branches. + */ + GATE_TOP0(CLK_TOP_CFG_AXI_EAST, CLK_TOP_AXI, 10), + GATE_TOP0(CLK_TOP_CFG_AXI_EAST_NORTH, CLK_TOP_AXI, 11), + GATE_TOP0(CLK_TOP_CFG_AXI_NORTH, CLK_TOP_AXI, 12), + GATE_TOP0(CLK_TOP_CFG_AXI_SOUTH, CLK_TOP_AXI, 13), + GATE_TOP0(CLK_TOP_CFG_EXT_TEST, CLK_TOP_MSDCPLL_D2, 15), + /* TOP1 */ + GATE_TOP1(CLK_TOP_SSUSB_REF, CLK_PAD_CLK26M, 0), + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, CLK_PAD_CLK26M, 1), + GATE_TOP1(CLK_TOP_SSUSB_P1_REF, CLK_PAD_CLK26M, 2), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, CLK_PAD_CLK26M, 3), + GATE_TOP1(CLK_TOP_SSUSB_P2_REF, CLK_PAD_CLK26M, 4), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, CLK_PAD_CLK26M, 5), + GATE_TOP1(CLK_TOP_SSUSB_P3_REF, CLK_PAD_CLK26M, 6), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, CLK_PAD_CLK26M, 7), +}; + +static const int mt8195_id_top_offs_map[] = { + [0 ... CLK_TOP_NR_CLK - 1] = -1, + /* FIXED */ + [CLK_TOP_IN_DGI] = 0, + [CLK_TOP_ULPOSC1] = 1, + [CLK_TOP_ULPOSC2] = 2, + [CLK_TOP_MEM_466M] = 3, + [CLK_TOP_MPHONE_SLAVE_B] = 4, + [CLK_TOP_PEXTP_PIPE] = 5, + [CLK_TOP_UFS_RX_SYMBOL] = 6, + [CLK_TOP_UFS_TX_SYMBOL] = 7, + [CLK_TOP_SSUSB_U3PHY_P1_P_P0] = 8, + [CLK_TOP_UFS_RX_SYMBOL1] = 9, + [CLK_TOP_FPC] = 10, + [CLK_TOP_HDMIRX_P] = 11, + /* FACTOR */ + [CLK_TOP_CLK26M_D2] = 12, + [CLK_TOP_CLK26M_D52] = 13, + [CLK_TOP_IN_DGI_D2] = 14, + [CLK_TOP_IN_DGI_D4] = 15, + [CLK_TOP_IN_DGI_D6] = 16, + [CLK_TOP_IN_DGI_D8] = 17, + [CLK_TOP_MAINPLL_D3] = 18, + [CLK_TOP_MAINPLL_D4] = 19, + [CLK_TOP_MAINPLL_D4_D2] = 20, + [CLK_TOP_MAINPLL_D4_D4] = 21, + [CLK_TOP_MAINPLL_D4_D8] = 22, + [CLK_TOP_MAINPLL_D5] = 23, + [CLK_TOP_MAINPLL_D5_D2] = 24, + [CLK_TOP_MAINPLL_D5_D4] = 25, + [CLK_TOP_MAINPLL_D5_D8] = 26, + [CLK_TOP_MAINPLL_D6] = 27, + [CLK_TOP_MAINPLL_D6_D2] = 28, + [CLK_TOP_MAINPLL_D6_D4] = 29, + [CLK_TOP_MAINPLL_D6_D8] = 30, + [CLK_TOP_MAINPLL_D7] = 31, + [CLK_TOP_MAINPLL_D7_D2] = 32, + [CLK_TOP_MAINPLL_D7_D4] = 33, + [CLK_TOP_MAINPLL_D7_D8] = 34, + [CLK_TOP_MAINPLL_D9] = 35, + [CLK_TOP_UNIVPLL_D2] = 36, + [CLK_TOP_UNIVPLL_D3] = 37, + [CLK_TOP_UNIVPLL_D4] = 38, + [CLK_TOP_UNIVPLL_D4_D2] = 39, + [CLK_TOP_UNIVPLL_D4_D4] = 40, + [CLK_TOP_UNIVPLL_D4_D8] = 41, + [CLK_TOP_UNIVPLL_D5] = 42, + [CLK_TOP_UNIVPLL_D5_D2] = 43, + [CLK_TOP_UNIVPLL_D5_D4] = 44, + [CLK_TOP_UNIVPLL_D5_D8] = 45, + [CLK_TOP_UNIVPLL_D6] = 46, + [CLK_TOP_UNIVPLL_D6_D2] = 47, + [CLK_TOP_UNIVPLL_D6_D4] = 48, + [CLK_TOP_UNIVPLL_D6_D8] = 49, + [CLK_TOP_UNIVPLL_D6_D16] = 50, + [CLK_TOP_UNIVPLL_D7] = 51, + [CLK_TOP_UNIVPLL_192M] = 52, + [CLK_TOP_UNIVPLL_192M_D4] = 53, + [CLK_TOP_UNIVPLL_192M_D8] = 54, + [CLK_TOP_UNIVPLL_192M_D16] = 55, + [CLK_TOP_UNIVPLL_192M_D32] = 56, + [CLK_TOP_APLL1_D3] = 57, + [CLK_TOP_APLL1_D4] = 58, + [CLK_TOP_APLL2_D3] = 59, + [CLK_TOP_APLL2_D4] = 60, + [CLK_TOP_APLL3_D4] = 61, + [CLK_TOP_APLL4_D4] = 62, + [CLK_TOP_APLL5_D4] = 63, + [CLK_TOP_HDMIRX_APLL_D3] = 64, + [CLK_TOP_HDMIRX_APLL_D4] = 65, + [CLK_TOP_HDMIRX_APLL_D6] = 66, + [CLK_TOP_MMPLL_D4] = 67, + [CLK_TOP_MMPLL_D4_D2] = 68, + [CLK_TOP_MMPLL_D4_D4] = 69, + [CLK_TOP_MMPLL_D5] = 70, + [CLK_TOP_MMPLL_D5_D2] = 71, + [CLK_TOP_MMPLL_D5_D4] = 72, + [CLK_TOP_MMPLL_D6] = 73, + [CLK_TOP_MMPLL_D6_D2] = 74, + [CLK_TOP_MMPLL_D7] = 75, + [CLK_TOP_MMPLL_D9] = 76, + [CLK_TOP_TVDPLL1_D2] = 77, + [CLK_TOP_TVDPLL1_D4] = 78, + [CLK_TOP_TVDPLL1_D8] = 79, + [CLK_TOP_TVDPLL1_D16] = 80, + [CLK_TOP_TVDPLL2_D2] = 81, + [CLK_TOP_TVDPLL2_D4] = 82, + [CLK_TOP_TVDPLL2_D8] = 83, + [CLK_TOP_TVDPLL2_D16] = 84, + [CLK_TOP_MSDCPLL_D2] = 85, + [CLK_TOP_MSDCPLL_D4] = 86, + [CLK_TOP_MSDCPLL_D16] = 87, + [CLK_TOP_ETHPLL_D2] = 88, + [CLK_TOP_ETHPLL_D8] = 89, + [CLK_TOP_ETHPLL_D10] = 90, + [CLK_TOP_DGIPLL_D2] = 91, + [CLK_TOP_ULPOSC1_D2] = 92, + [CLK_TOP_ULPOSC1_D4] = 93, + [CLK_TOP_ULPOSC1_D7] = 94, + [CLK_TOP_ULPOSC1_D8] = 95, + [CLK_TOP_ULPOSC1_D10] = 96, + [CLK_TOP_ULPOSC1_D16] = 97, + [CLK_TOP_ADSPPLL_D2] = 98, + [CLK_TOP_ADSPPLL_D4] = 99, + [CLK_TOP_ADSPPLL_D8] = 100, + /* MUX */ + [CLK_TOP_AXI] = 101, + [CLK_TOP_SPM] = 102, + [CLK_TOP_SCP] = 103, + [CLK_TOP_BUS_AXIMEM] = 104, + [CLK_TOP_VPP] = 105, + [CLK_TOP_ETHDR] = 106, + [CLK_TOP_IPE] = 107, + [CLK_TOP_CAM] = 108, + [CLK_TOP_CCU] = 109, + [CLK_TOP_IMG] = 110, + [CLK_TOP_CAMTM] = 111, + [CLK_TOP_DSP] = 112, + [CLK_TOP_DSP1] = 113, + [CLK_TOP_DSP2] = 114, + [CLK_TOP_DSP3] = 115, + [CLK_TOP_DSP4] = 116, + [CLK_TOP_DSP5] = 117, + [CLK_TOP_DSP6] = 118, + [CLK_TOP_DSP7] = 119, + [CLK_TOP_IPU_IF] = 120, + [CLK_TOP_MFG_CORE_TMP] = 121, + [CLK_TOP_CAMTG] = 122, + [CLK_TOP_CAMTG2] = 123, + [CLK_TOP_CAMTG3] = 124, + [CLK_TOP_CAMTG4] = 125, + [CLK_TOP_CAMTG5] = 126, + [CLK_TOP_UART] = 127, + [CLK_TOP_SPI] = 128, + [CLK_TOP_SPIS] = 129, + [CLK_TOP_MSDC50_0_HCLK] = 130, + [CLK_TOP_MSDC50_0] = 131, + [CLK_TOP_MSDC30_1] = 132, + [CLK_TOP_MSDC30_2] = 133, + [CLK_TOP_INTDIR] = 134, + [CLK_TOP_AUD_INTBUS] = 135, + [CLK_TOP_AUDIO_H] = 136, + [CLK_TOP_PWRAP_ULPOSC] = 137, + [CLK_TOP_ATB] = 138, + [CLK_TOP_PWRMCU] = 139, + [CLK_TOP_DP] = 140, + [CLK_TOP_EDP] = 141, + [CLK_TOP_DPI] = 142, + [CLK_TOP_DISP_PWM0] = 143, + [CLK_TOP_DISP_PWM1] = 144, + [CLK_TOP_USB_TOP] = 145, + [CLK_TOP_SSUSB_XHCI] = 146, + [CLK_TOP_USB_TOP_1P] = 147, + [CLK_TOP_SSUSB_XHCI_1P] = 148, + [CLK_TOP_USB_TOP_2P] = 149, + [CLK_TOP_SSUSB_XHCI_2P] = 150, + [CLK_TOP_USB_TOP_3P] = 151, + [CLK_TOP_SSUSB_XHCI_3P] = 152, + [CLK_TOP_I2C] = 153, + [CLK_TOP_SENINF] = 154, + [CLK_TOP_SENINF1] = 155, + [CLK_TOP_SENINF2] = 156, + [CLK_TOP_SENINF3] = 157, + [CLK_TOP_GCPU] = 158, + [CLK_TOP_DXCC] = 159, + [CLK_TOP_DPMAIF_MAIN] = 160, + [CLK_TOP_AES_UFSFDE] = 161, + [CLK_TOP_UFS] = 162, + [CLK_TOP_UFS_TICK1US] = 163, + [CLK_TOP_UFS_MP_SAP_CFG] = 164, + [CLK_TOP_VENC] = 165, + [CLK_TOP_VDEC] = 166, + [CLK_TOP_PWM] = 167, + [CLK_TOP_MCUPM] = 168, + [CLK_TOP_SPMI_P_MST] = 169, + [CLK_TOP_SPMI_M_MST] = 170, + [CLK_TOP_DVFSRC] = 171, + [CLK_TOP_TL] = 172, + [CLK_TOP_TL_P1] = 173, + [CLK_TOP_AES_MSDCFDE] = 174, + [CLK_TOP_DSI_OCC] = 175, + [CLK_TOP_WPE_VPP] = 176, + [CLK_TOP_HDCP] = 177, + [CLK_TOP_HDCP_24M] = 178, + [CLK_TOP_HD20_DACR_REF_CLK] = 179, + [CLK_TOP_HD20_HDCP_CCLK] = 180, + [CLK_TOP_HDMI_XTAL] = 181, + [CLK_TOP_HDMI_APB] = 182, + [CLK_TOP_SNPS_ETH_250M] = 183, + [CLK_TOP_SNPS_ETH_62P4M_PTP] = 184, + [CLK_TOP_SNPS_ETH_50M_RMII] = 185, + [CLK_TOP_DGI_OUT] = 186, + [CLK_TOP_NNA0] = 187, + [CLK_TOP_NNA1] = 188, + [CLK_TOP_ADSP] = 189, + [CLK_TOP_ASM_H] = 190, + [CLK_TOP_ASM_M] = 191, + [CLK_TOP_ASM_L] = 192, + [CLK_TOP_APLL1] = 193, + [CLK_TOP_APLL2] = 194, + [CLK_TOP_APLL3] = 195, + [CLK_TOP_APLL4] = 196, + [CLK_TOP_APLL5] = 197, + [CLK_TOP_I2SO1_MCK] = 198, + [CLK_TOP_I2SO2_MCK] = 199, + [CLK_TOP_I2SI1_MCK] = 200, + [CLK_TOP_I2SI2_MCK] = 201, + [CLK_TOP_DPTX_MCK] = 202, + [CLK_TOP_AUD_IEC_CLK] = 203, + [CLK_TOP_A1SYS_HP] = 204, + [CLK_TOP_A2SYS_HF] = 205, + [CLK_TOP_A3SYS_HF] = 206, + [CLK_TOP_A4SYS_HF] = 207, + [CLK_TOP_SPINFI_BCLK] = 208, + [CLK_TOP_NFI1X] = 209, + [CLK_TOP_ECC] = 210, + [CLK_TOP_AUDIO_LOCAL_BUS] = 211, + [CLK_TOP_SPINOR] = 212, + [CLK_TOP_DVIO_DGI_REF] = 213, + [CLK_TOP_ULPOSC] = 214, + [CLK_TOP_ULPOSC_CORE] = 215, + [CLK_TOP_SRCK] = 216, + /* GATE */ + [CLK_TOP_CFG_VPP0] = 217, + [CLK_TOP_CFG_VPP1] = 218, + [CLK_TOP_CFG_VDO0] = 219, + [CLK_TOP_CFG_VDO1] = 220, + [CLK_TOP_CFG_UNIPLL_SES] = 221, + [CLK_TOP_CFG_26M_VPP0] = 222, + [CLK_TOP_CFG_26M_VPP1] = 223, + [CLK_TOP_CFG_26M_AUD] = 224, + [CLK_TOP_CFG_AXI_EAST] = 225, + [CLK_TOP_CFG_AXI_EAST_NORTH] = 226, + [CLK_TOP_CFG_AXI_NORTH] = 227, + [CLK_TOP_CFG_AXI_SOUTH] = 228, + [CLK_TOP_CFG_EXT_TEST] = 229, + [CLK_TOP_SSUSB_REF] = 230, + [CLK_TOP_SSUSB_PHY_REF] = 231, + [CLK_TOP_SSUSB_P1_REF] = 232, + [CLK_TOP_SSUSB_PHY_P1_REF] = 233, + [CLK_TOP_SSUSB_P2_REF] = 234, + [CLK_TOP_SSUSB_PHY_P2_REF] = 235, + [CLK_TOP_SSUSB_P3_REF] = 236, + [CLK_TOP_SSUSB_PHY_P3_REF] = 237, +}; + +static const struct mtk_clk_tree mt8195_topckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .id_offs_map = mt8195_id_top_offs_map, + .id_offs_map_size = ARRAY_SIZE(mt8195_id_top_offs_map), + .fdivs_offs = mt8195_id_top_offs_map[CLK_TOP_CLK26M_D2], + .muxes_offs = mt8195_id_top_offs_map[CLK_TOP_AXI], + .gates_offs = mt8195_id_top_offs_map[CLK_TOP_CFG_VPP0], + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, + .gates = top_cg_clks, + .num_fclks = ARRAY_SIZE(top_fixed_clks), + .num_fdivs = ARRAY_SIZE(top_fixed_divs), + .num_muxes = ARRAY_SIZE(top_muxes), + .num_gates = ARRAY_SIZE(top_cg_clks), +}; + +static const struct mtk_gate_regs infra_ao0_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra_ao1_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra_ao2_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra_ao3_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +static const struct mtk_gate_regs infra_ao4_cg_regs = { + .set_ofs = 0xe0, + .clr_ofs = 0xe4, + .sta_ofs = 0xe8, +}; + +#define GATE_INFRA_AO0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao0_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO0E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao0_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao1_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO1E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao1_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao2_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO2E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao2_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO3(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao3_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO3E(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao3_cg_regs, _shift,\ + CLK_PARENT_EXT | CLK_GATE_SETCLR) + +#define GATE_INFRA_AO4(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &infra_ao4_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +static const struct mtk_gate infra_ao_clks[] = { + /* INFRA_AO0 */ + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, CLK_TOP_PWRAP_ULPOSC, 0), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, CLK_TOP_PWRAP_ULPOSC, 1), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, CLK_TOP_PWRAP_ULPOSC, 2), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, CLK_TOP_PWRAP_ULPOSC, 3), + GATE_INFRA_AO0(CLK_INFRA_AO_SEJ, CLK_TOP_AXI, 5), + GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, CLK_TOP_AXI, 6), + GATE_INFRA_AO0(CLK_INFRA_AO_GCE, CLK_TOP_AXI, 8), + GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, CLK_TOP_AXI, 9), + GATE_INFRA_AO0(CLK_INFRA_AO_THERM, CLK_TOP_AXI, 10), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM_H, CLK_TOP_AXI, 15), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, CLK_TOP_PWM, 16), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, CLK_TOP_PWM, 17), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, CLK_TOP_PWM, 18), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, CLK_TOP_PWM, 19), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM, CLK_TOP_PWM, 21), + GATE_INFRA_AO0(CLK_INFRA_AO_UART0, CLK_TOP_UART, 22), + GATE_INFRA_AO0(CLK_INFRA_AO_UART1, CLK_TOP_UART, 23), + GATE_INFRA_AO0(CLK_INFRA_AO_UART2, CLK_TOP_UART, 24), + GATE_INFRA_AO0(CLK_INFRA_AO_UART3, CLK_TOP_UART, 25), + GATE_INFRA_AO0(CLK_INFRA_AO_UART4, CLK_TOP_UART, 26), + GATE_INFRA_AO0E(CLK_INFRA_AO_GCE_26M, CLK_PAD_CLK26M, 27), + GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, CLK_TOP_FPC, 28), + GATE_INFRA_AO0(CLK_INFRA_AO_UART5, CLK_TOP_UART, 29), + /* INFRA_AO1 */ + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_26M, CLK_PAD_CLK26M, 0), + GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, CLK_TOP_SPI, 1), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, CLK_TOP_MSDC50_0_HCLK, 2), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, CLK_TOP_AXI, 4), + GATE_INFRA_AO1(CLK_INFRA_AO_CG1_MSDC2, CLK_TOP_AXI, 5), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, CLK_TOP_MSDC50_0, 6), + GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, CLK_TOP_AXI, 9), + GATE_INFRA_AO1E(CLK_INFRA_AO_AUXADC, CLK_PAD_CLK26M, 10), + GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, CLK_TOP_AXI, 11), + GATE_INFRA_AO1E(CLK_INFRA_AO_HDMI_32K, CLK_PAD_CLK32K, 12), + GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_H, CLK_TOP_AXI, 13), + GATE_INFRA_AO1(CLK_INFRA_AO_IRRX, CLK_TOP_AXI, 14), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_26M, CLK_PAD_CLK26M, 15), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, CLK_TOP_MSDC30_1, 16), + GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_B, CLK_TOP_AXI, 17), + GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, CLK_TOP_TL, 18), + GATE_INFRA_AO1(CLK_INFRA_AO_DEVICE_APC, CLK_TOP_AXI, 20), + GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_H, CLK_TOP_AXI, 23), + GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, CLK_TOP_AXI, 24), + GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, CLK_TOP_AXI, 25), + GATE_INFRA_AO1E(CLK_INFRA_AO_PCIE_TL_32K, CLK_PAD_CLK32K, 26), + GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, CLK_TOP_AXI, 29), + GATE_INFRA_AO1E(CLK_INFRA_AO_DRAMC_F26M, CLK_PAD_CLK26M, 31), + /* INFRA_AO2 */ + GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, CLK_TOP_AXI, 0), + GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB, CLK_TOP_USB_TOP, 1), + GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, CLK_TOP_DISP_PWM0, 2), + GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_B, CLK_TOP_AXI, 3), + GATE_INFRA_AO2E(CLK_INFRA_AO_AUDIO_26M_B, CLK_PAD_CLK26M, 4), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, CLK_TOP_SPI, 6), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, CLK_TOP_SPI, 9), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, CLK_TOP_SPI, 10), + GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_SYS, CLK_TOP_UFS, 11), + GATE_INFRA_AO2(CLK_INFRA_AO_UNIPRO_TICK, CLK_TOP_UFS_TICK1US, 12), + GATE_INFRA_AO2(CLK_INFRA_AO_UFS_MP_SAP_B, CLK_TOP_UFS_MP_SAP_CFG, 13), + GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU, CLK_TOP_PWRMCU, 15), + GATE_INFRA_AO2(CLK_INFRA_AO_PWRMCU_BUS_H, CLK_TOP_AXI, 17), + GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_B, CLK_TOP_AXI, 18), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, CLK_TOP_SPI, 25), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, CLK_TOP_SPI, 26), + GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, CLK_TOP_AXI, 27), + GATE_INFRA_AO2(CLK_INFRA_AO_AES_UFSFDE, CLK_TOP_UFS, 28), + GATE_INFRA_AO2(CLK_INFRA_AO_AES, CLK_TOP_AES_UFSFDE, 29), + GATE_INFRA_AO2(CLK_INFRA_AO_UFS_TICK, CLK_TOP_UFS_TICK1US, 30), + GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI, 31), + /* INFRA_AO3 */ + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, CLK_TOP_MSDC50_0, 0), + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, CLK_TOP_MSDC50_0, 1), + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, CLK_TOP_MSDC50_0, 2), + GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, CLK_TOP_AXI, 5), + GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, CLK_TOP_MSDC50_0, 7), + GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, CLK_TOP_MSDC50_0, 8), + GATE_INFRA_AO3(CLK_INFRA_AO_CG3_MSDC2, CLK_TOP_MSDC30_2, 9), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, CLK_TOP_GCPU, 10), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_PERI_26M, CLK_PAD_CLK26M, 15), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_B, CLK_TOP_AXI, 16), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_B, CLK_TOP_AXI, 17), + GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, CLK_TOP_DISP_PWM1, 20), + GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, CLK_TOP_MSDC50_0, 24), + GATE_INFRA_AO3(CLK_INFRA_AO_DEVICE_APC_SYNC, CLK_TOP_AXI, 25), + GATE_INFRA_AO3E(CLK_INFRA_AO_PCIE_P1_PERI_26M, CLK_PAD_CLK26M, 26), + GATE_INFRA_AO3(CLK_INFRA_AO_SPIS0, CLK_TOP_SPIS, 28), + GATE_INFRA_AO3(CLK_INFRA_AO_SPIS1, CLK_TOP_SPIS, 29), + /* INFRA_AO4 */ + GATE_INFRA_AO4(CLK_INFRA_AO_133M_M_PERI, CLK_TOP_AXI, 0), + GATE_INFRA_AO4(CLK_INFRA_AO_66M_M_PERI, CLK_TOP_AXI, 1), + GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, CLK_TOP_PEXTP_PIPE, 7), + GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P1, + CLK_TOP_SSUSB_U3PHY_P1_P_P0, 8), + GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_P1_TL_96M, CLK_TOP_TL_P1, 17), + GATE_INFRA_AO4(CLK_INFRA_AO_AES_MSDCFDE_0P, CLK_TOP_AES_MSDCFDE, 18), + GATE_INFRA_AO4(CLK_INFRA_AO_UFS_TX_SYMBOL, CLK_TOP_UFS_TX_SYMBOL, 22), + GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL, CLK_TOP_UFS_RX_SYMBOL, 23), + GATE_INFRA_AO4(CLK_INFRA_AO_UFS_RX_SYMBOL1, CLK_TOP_UFS_RX_SYMBOL1, 24), + GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, CLK_TOP_MEM_466M, 31), +}; + +static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), +}; + +static int mt8195_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8195_apmixedsys_clk_tree); +} + +static int mt8195_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8195_topckgen_clk_tree); +} + +static int mt8195_infra_ao_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8195_infracfg_ao_clk_tree, + infra_ao_clks, + ARRAY_SIZE(infra_ao_clks), 0); +} + +static const struct udevice_id mt8195_apmixed[] = { + { .compatible = "mediatek,mt8195-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8195_topckgen_compat[] = { + { .compatible = "mediatek,mt8195-topckgen", }, + { } +}; + +static const struct udevice_id of_match_clk_mt8195_infra_ao[] = { + { .compatible = "mediatek,mt8195-infracfg_ao", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8195-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8195_apmixed, + .probe = mt8195_apmixedsys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8195-topckgen", + .id = UCLASS_CLK, + .of_match = mt8195_topckgen_compat, + .probe = mt8195_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infra_ao) = { + .name = "mt8195-infra_ao", + .id = UCLASS_CLK, + .of_match = of_match_clk_mt8195_infra_ao, + .probe = mt8195_infra_ao_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 6ba464097ae..eb94b86622c 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -13,9 +13,15 @@ #include #include "clk-mtk.h" -/* Missing topckgen clocks definition in dt-bindings */ -#define CLK_TOP_CLK26M 141 -#define CLK_TOP_CLK32K 142 +enum { + CLK_PAD_CLK32K, + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK32K] = 32000, + [CLK_PAD_CLK26M] = 26000000, +}; /* apmixedsys */ #define MT8365_PLL_FMAX (3800UL * MHZ) @@ -45,9 +51,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, PLL_AO, 22, 0x0310, 24, 0x0310, 0, 0, 0), - PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, HAVE_RST_BAR, 22, + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, CON0_MT8365_RST_BAR, 0), - PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, HAVE_RST_BAR, 22, + PLL(CLK_APMIXED_UNIVPLL, 0x0208, 0x0214, 0xFF000001, CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, CON0_MT8365_RST_BAR, 0), PLL(CLK_APMIXED_MFGPLL, 0x0218, 0x0224, 0x00000001, 0, 22, 0x021C, 24, 0x021C, 0, 0, 0), @@ -68,161 +74,22 @@ static const struct mtk_pll_data apmixed_plls[] = { }; static const struct mtk_clk_tree mt8365_apmixed_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .plls = apmixed_plls, .num_plls = ARRAY_SIZE(apmixed_plls), }; /* topckgen */ -/* - * The devicetree bindings missed a few clocks and can't be changed, so we need - * to provide a mapping to fix the omissions. - */ -static const int mt8365_topckgen_id_map[] = { - [0 ... CLK_TOP_NR_CLK - 1] = -1, - /* FIXED */ - /* Fixed 32K oscillator is not available in devicetree definitions */ - [CLK_TOP_CLK32K] = 0, - [CLK_TOP_CLK_NULL] = 1, - [CLK_TOP_I2S0_BCK] = 2, - [CLK_TOP_DSI0_LNTC_DSICK] = 3, - [CLK_TOP_VPLL_DPIX] = 4, - [CLK_TOP_LVDSTX_CLKDIG_CTS] = 5, - /* FACTOR */ - [CLK_TOP_MFGPLL] = 6, - [CLK_TOP_SYSPLL_D2] = 7, - [CLK_TOP_SYSPLL1_D2] = 8, - [CLK_TOP_SYSPLL1_D4] = 9, - [CLK_TOP_SYSPLL1_D8] = 10, - [CLK_TOP_SYSPLL1_D16] = 11, - [CLK_TOP_SYSPLL_D3] = 12, - [CLK_TOP_SYSPLL2_D2] = 13, - [CLK_TOP_SYSPLL2_D4] = 14, - [CLK_TOP_SYSPLL2_D8] = 15, - [CLK_TOP_SYSPLL_D5] = 16, - [CLK_TOP_SYSPLL3_D2] = 17, - [CLK_TOP_SYSPLL3_D4] = 18, - [CLK_TOP_SYSPLL_D7] = 19, - [CLK_TOP_SYSPLL4_D2] = 20, - [CLK_TOP_SYSPLL4_D4] = 21, - /* Skipping CLK_TOP_UNIVPLL since isn't a real clock. */ - [CLK_TOP_UNIVPLL_D2] = 22, - [CLK_TOP_UNIVPLL1_D2] = 23, - [CLK_TOP_UNIVPLL1_D4] = 24, - [CLK_TOP_UNIVPLL_D3] = 25, - [CLK_TOP_UNIVPLL2_D2] = 26, - [CLK_TOP_UNIVPLL2_D4] = 27, - [CLK_TOP_UNIVPLL2_D8] = 28, - [CLK_TOP_UNIVPLL2_D32] = 29, - [CLK_TOP_UNIVPLL_D5] = 30, - [CLK_TOP_UNIVPLL3_D2] = 31, - [CLK_TOP_UNIVPLL3_D4] = 32, - [CLK_TOP_MMPLL] = 33, - [CLK_TOP_MMPLL_D2] = 34, - [CLK_TOP_LVDSPLL_D2] = 35, - [CLK_TOP_LVDSPLL_D4] = 36, - [CLK_TOP_LVDSPLL_D8] = 37, - [CLK_TOP_LVDSPLL_D16] = 38, - [CLK_TOP_USB20_192M] = 39, - [CLK_TOP_USB20_192M_D4] = 40, - [CLK_TOP_USB20_192M_D8] = 41, - [CLK_TOP_USB20_192M_D16] = 42, - [CLK_TOP_USB20_192M_D32] = 43, - [CLK_TOP_APLL1] = 44, - [CLK_TOP_APLL1_D2] = 45, - [CLK_TOP_APLL1_D4] = 46, - [CLK_TOP_APLL1_D8] = 47, - [CLK_TOP_APLL2] = 48, - [CLK_TOP_APLL2_D2] = 49, - [CLK_TOP_APLL2_D4] = 50, - [CLK_TOP_APLL2_D8] = 51, - /* Fixed 26M oscillator is not available in devicetree definitions */ - [CLK_TOP_CLK26M] = 52, - [CLK_TOP_SYS_26M_D2] = 53, - [CLK_TOP_MSDCPLL] = 54, - [CLK_TOP_MSDCPLL_D2] = 55, - [CLK_TOP_DSPPLL] = 56, - [CLK_TOP_DSPPLL_D2] = 57, - [CLK_TOP_DSPPLL_D4] = 58, - [CLK_TOP_DSPPLL_D8] = 59, - [CLK_TOP_APUPLL] = 60, - [CLK_TOP_CLK26M_D52] = 61, - /* MUX */ - [CLK_TOP_AXI_SEL] = 62, - [CLK_TOP_MEM_SEL] = 63, - [CLK_TOP_MM_SEL] = 64, - [CLK_TOP_SCP_SEL] = 65, - [CLK_TOP_MFG_SEL] = 66, - [CLK_TOP_ATB_SEL] = 67, - [CLK_TOP_CAMTG_SEL] = 68, - [CLK_TOP_CAMTG1_SEL] = 69, - [CLK_TOP_UART_SEL] = 70, - [CLK_TOP_SPI_SEL] = 71, - [CLK_TOP_MSDC50_0_HC_SEL] = 72, - [CLK_TOP_MSDC2_2_HC_SEL] = 73, - [CLK_TOP_MSDC50_0_SEL] = 74, - [CLK_TOP_MSDC50_2_SEL] = 75, - [CLK_TOP_MSDC30_1_SEL] = 76, - [CLK_TOP_AUDIO_SEL] = 77, - [CLK_TOP_AUD_INTBUS_SEL] = 78, - [CLK_TOP_AUD_1_SEL] = 79, - [CLK_TOP_AUD_2_SEL] = 80, - [CLK_TOP_AUD_ENGEN1_SEL] = 81, - [CLK_TOP_AUD_ENGEN2_SEL] = 82, - [CLK_TOP_AUD_SPDIF_SEL] = 83, - [CLK_TOP_DISP_PWM_SEL] = 84, - [CLK_TOP_DXCC_SEL] = 85, - [CLK_TOP_SSUSB_SYS_SEL] = 86, - [CLK_TOP_SSUSB_XHCI_SEL] = 87, - [CLK_TOP_SPM_SEL] = 88, - [CLK_TOP_I2C_SEL] = 89, - [CLK_TOP_PWM_SEL] = 90, - [CLK_TOP_SENIF_SEL] = 91, - [CLK_TOP_AES_FDE_SEL] = 92, - [CLK_TOP_CAMTM_SEL] = 93, - [CLK_TOP_DPI0_SEL] = 94, - [CLK_TOP_DPI1_SEL] = 95, - [CLK_TOP_DSP_SEL] = 96, - [CLK_TOP_NFI2X_SEL] = 97, - [CLK_TOP_NFIECC_SEL] = 98, - [CLK_TOP_ECC_SEL] = 99, - [CLK_TOP_ETH_SEL] = 100, - [CLK_TOP_GCPU_SEL] = 101, - [CLK_TOP_GCPU_CPM_SEL] = 102, - [CLK_TOP_APU_SEL] = 103, - [CLK_TOP_APU_IF_SEL] = 104, - /* GATE */ - [CLK_TOP_AUD_I2S0_M] = 105, - [CLK_TOP_AUD_I2S1_M] = 106, - [CLK_TOP_AUD_I2S2_M] = 107, - [CLK_TOP_AUD_I2S3_M] = 108, - [CLK_TOP_AUD_TDMOUT_M] = 109, - [CLK_TOP_AUD_TDMOUT_B] = 110, - [CLK_TOP_AUD_TDMIN_M] = 111, - [CLK_TOP_AUD_TDMIN_B] = 112, - [CLK_TOP_AUD_SPDIF_M] = 113, - [CLK_TOP_USB20_48M_EN] = 114, - [CLK_TOP_UNIVPLL_48M_EN] = 115, - [CLK_TOP_LVDSTX_CLKDIG_EN] = 116, - [CLK_TOP_VPLL_DPIX_EN] = 117, - [CLK_TOP_SSUSB_TOP_CK_EN] = 118, - [CLK_TOP_SSUSB_PHY_CK_EN] = 119, - [CLK_TOP_CONN_32K] = 120, - [CLK_TOP_CONN_26M] = 121, - [CLK_TOP_DSP_32K] = 122, - [CLK_TOP_DSP_26M] = 123, -}; - #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK0(CLK_TOP_CLK32K, 32000), FIXED_CLK0(CLK_TOP_CLK_NULL, 0), FIXED_CLK1(CLK_TOP_I2S0_BCK, 26000000), FIXED_CLK0(CLK_TOP_DSI0_LNTC_DSICK, 75000000), @@ -237,7 +104,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define PLL_FACTOR2(_id, _name, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1), @@ -256,6 +123,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", CLK_APMIXED_MAINPLL, 1, 7), PLL_FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", CLK_APMIXED_MAINPLL, 1, 14), PLL_FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", CLK_APMIXED_MAINPLL, 1, 28), + PLL_FACTOR(CLK_TOP_UNIVPLL, "univpll", CLK_APMIXED_UNIVPLL, 1, 1), PLL_FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", CLK_APMIXED_UNIVPLL, 1, 2), PLL_FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", CLK_APMIXED_UNIVPLL, 1, 4), PLL_FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", CLK_APMIXED_UNIVPLL, 1, 8), @@ -286,8 +154,7 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR1(CLK_TOP_APLL2_D2, "apll2_d2", CLK_TOP_APLL2, 1, 2), PLL_FACTOR1(CLK_TOP_APLL2_D4, "apll2_d4", CLK_TOP_APLL2, 1, 4), PLL_FACTOR1(CLK_TOP_APLL2_D8, "apll2_d8", CLK_TOP_APLL2, 1, 8), - PLL_FACTOR2(CLK_TOP_CLK26M, "clk26m_ck", CLK_XTAL, 1, 1), - PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2), + PLL_FACTOR2(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_PAD_CLK26M, 1, 2), PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1), PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2), PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1), @@ -295,293 +162,293 @@ static const struct mtk_fixed_factor top_divs[] = { PLL_FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", CLK_APMIXED_DSPPLL, 1, 4), PLL_FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", CLK_APMIXED_DSPPLL, 1, 8), PLL_FACTOR(CLK_TOP_APUPLL, "apupll_ck", CLK_APMIXED_APUPLL, 1, 1), - PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_XTAL, 1, 52), + PLL_FACTOR2(CLK_TOP_CLK26M_D52, "clk26m_d52", CLK_PAD_CLK26M, 1, 52), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL3_D2 +static const struct mtk_parent axi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL3_D2), }; -static const int mem_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent mem_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_MMPLL_D2, +static const struct mtk_parent mm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int scp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MFGPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent mfg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MFGPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int atb_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent atb_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int camtg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_USB20_192M_D8, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_USB20_192M_D4, - CLK_TOP_UNIVPLL2_D32, - CLK_TOP_USB20_192M_D16, - CLK_TOP_USB20_192M_D32, +static const struct mtk_parent camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_USB20_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_USB20_192M_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D32), + TOP_PARENT(CLK_TOP_USB20_192M_D16), + TOP_PARENT(CLK_TOP_USB20_192M_D32), }; -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int msdc50_0_hc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent msdc50_0_hc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent msdc50_0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int msdc50_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent msdc50_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int msdc30_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent msdc30_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D16 +static const struct mtk_parent audio_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent aud_intbus_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 +static const struct mtk_parent aud_1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 +static const struct mtk_parent aud_2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8 +static const struct mtk_parent aud_engen1_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8, +static const struct mtk_parent aud_engen2_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int aud_spdif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent aud_spdif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int disp_pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent disp_pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int dxcc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent dxcc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int ssusb_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 +static const struct mtk_parent ssusb_sys_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent spm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D8 +static const struct mtk_parent i2c_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent pwm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int senif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent senif_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int aes_fde_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2 +static const struct mtk_parent aes_fde_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_LVDSPLL_D2, - CLK_TOP_LVDSPLL_D4, - CLK_TOP_LVDSPLL_D8, - CLK_TOP_LVDSPLL_D16 +static const struct mtk_parent dpi0_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_LVDSPLL_D2), + TOP_PARENT(CLK_TOP_LVDSPLL_D4), + TOP_PARENT(CLK_TOP_LVDSPLL_D8), + TOP_PARENT(CLK_TOP_LVDSPLL_D16), }; -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_DSPPLL_D8 +static const struct mtk_parent dsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_DSPPLL_D8), }; -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent nfi2x_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int nfiecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL_D7, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent nfiecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D2 +static const struct mtk_parent ecc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D2), }; -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_SYSPLL4_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent eth_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int gcpu_cpm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent gcpu_cpm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int apu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_APUPLL, - CLK_TOP_MMPLL, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL1_D4 +static const struct mtk_parent apu_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_APUPLL), + TOP_PARENT(CLK_TOP_MMPLL), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), }; static const struct mtk_composite top_muxes[] = { @@ -684,6 +551,14 @@ static const struct mtk_gate_regs top2_cg_regs = { .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ } +#define GATE_EXT(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ + } + static const struct mtk_gate top_clk_gates[] = { GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0), GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1), @@ -700,19 +575,18 @@ static const struct mtk_gate top_clk_gates[] = { GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21), GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), - GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), - GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), - GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), - GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), + GATE_EXT(CLK_TOP_CONN_32K, CLK_PAD_CLK32K, 10), + GATE_EXT(CLK_TOP_CONN_26M, CLK_PAD_CLK26M, 11), + GATE_EXT(CLK_TOP_DSP_32K, CLK_PAD_CLK32K, 16), + GATE_EXT(CLK_TOP_DSP_26M, CLK_PAD_CLK26M, 17), }; static const struct mtk_clk_tree mt8365_topckgen_tree = { - .xtal_rate = 26 * MHZ, - .id_offs_map = mt8365_topckgen_id_map, - .id_offs_map_size = ARRAY_SIZE(mt8365_topckgen_id_map), - .fdivs_offs = mt8365_topckgen_id_map[CLK_TOP_MFGPLL], - .muxes_offs = mt8365_topckgen_id_map[CLK_TOP_AXI_SEL], - .gates_offs = mt8365_topckgen_id_map[CLK_TOP_AUD_I2S0_M], + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .fdivs_offs = CLK_TOP_MFGPLL, + .muxes_offs = CLK_TOP_AXI_SEL, + .gates_offs = CLK_TOP_AUD_I2S0_M, .fclks = top_fixed_clks, .fdivs = top_divs, .muxes = top_muxes, @@ -778,12 +652,33 @@ static const struct mtk_gate_regs ifr6_cg_regs = { #define GATE_IFR6(_id, _parent, _shift) \ GATE_IFRX(_id, _parent, _shift, &ifr6_cg_regs) +#define GATE_IFRX_EXT(_id, _parent, _shift, _regs) \ + { \ + .id = _id, \ + .parent = _parent, \ + .regs = _regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_EXT, \ + } + +#define GATE_IFR2_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr2_cg_regs) + +#define GATE_IFR3_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr3_cg_regs) + +#define GATE_IFR4_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr4_cg_regs) + +#define GATE_IFR5_EXT(_id, _parent, _shift) \ + GATE_IFRX_EXT(_id, _parent, _shift, &ifr5_cg_regs) + static const struct mtk_gate ifr_clks[] = { /* IFR2 */ - GATE_IFR2(CLK_IFR_PMIC_TMR, CLK_TOP_CLK26M, 0), - GATE_IFR2(CLK_IFR_PMIC_AP, CLK_TOP_CLK26M, 1), - GATE_IFR2(CLK_IFR_PMIC_MD, CLK_TOP_CLK26M, 2), - GATE_IFR2(CLK_IFR_PMIC_CONN, CLK_TOP_CLK26M, 3), + GATE_IFR2_EXT(CLK_IFR_PMIC_TMR, CLK_PAD_CLK26M, 0), + GATE_IFR2_EXT(CLK_IFR_PMIC_AP, CLK_PAD_CLK26M, 1), + GATE_IFR2_EXT(CLK_IFR_PMIC_MD, CLK_PAD_CLK26M, 2), + GATE_IFR2_EXT(CLK_IFR_PMIC_CONN, CLK_PAD_CLK26M, 3), GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8), GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9), GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10), @@ -798,7 +693,7 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR2(CLK_IFR_UART1, CLK_TOP_UART_SEL, 23), GATE_IFR2(CLK_IFR_UART2, CLK_TOP_UART_SEL, 24), GATE_IFR2(CLK_IFR_DSP_UART, CLK_TOP_UART_SEL, 26), - GATE_IFR2(CLK_IFR_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_IFR2_EXT(CLK_IFR_GCE_26M, CLK_PAD_CLK26M, 27), GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28), GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31), /* IFR3 */ @@ -806,19 +701,19 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR3(CLK_IFR_MSDC0_HCLK, CLK_TOP_AXI_SEL, 2), GATE_IFR3(CLK_IFR_MSDC2_HCLK, CLK_TOP_AXI_SEL, 3), GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4), - GATE_IFR3(CLK_IFR_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_IFR3_EXT(CLK_IFR_DVFSRC, CLK_PAD_CLK26M, 7), GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8), GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9), - GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10), + GATE_IFR3_EXT(CLK_IFR_AUXADC, CLK_PAD_CLK26M, 10), GATE_IFR3(CLK_IFR_CPUM, CLK_TOP_AXI_SEL, 11), - GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_IFR3_EXT(CLK_IFR_AUXADC_MD, CLK_PAD_CLK26M, 14), GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18), GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24), GATE_IFR3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25), /* IFR4 */ GATE_IFR4(CLK_IFR_PWM_FBCLK6, CLK_TOP_PWM_SEL, 0), GATE_IFR4(CLK_IFR_DISP_PWM, CLK_TOP_DISP_PWM_SEL, 2), - GATE_IFR4(CLK_IFR_AUD_26M_BK, CLK_TOP_CLK26M, 4), + GATE_IFR4_EXT(CLK_IFR_AUD_26M_BK, CLK_PAD_CLK26M, 4), GATE_IFR4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27), /* IFR5 */ GATE_IFR5(CLK_IFR_MSDC0_SF, CLK_TOP_MSDC50_0_SEL, 0), @@ -829,12 +724,12 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR5(CLK_IFR_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9), GATE_IFR5(CLK_IFR_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10), GATE_IFR5(CLK_IFR_MSDC2_SRC, CLK_TOP_MSDC50_2_SEL, 11), - GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12), - GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13), - GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14), + GATE_IFR5_EXT(CLK_IFR_PWRAP_TMR, CLK_PAD_CLK26M, 12), + GATE_IFR5_EXT(CLK_IFR_PWRAP_SPI, CLK_PAD_CLK26M, 13), + GATE_IFR5_EXT(CLK_IFR_PWRAP_SYS, CLK_PAD_CLK26M, 14), GATE_IFR5(CLK_IFR_MCU_PM_BK, CLK_TOP_AXI_SEL, 16), - GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22), - GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23), + GATE_IFR5_EXT(CLK_IFR_IRRX_26M, CLK_PAD_CLK26M, 22), + GATE_IFR5_EXT(CLK_IFR_IRRX_32K, CLK_PAD_CLK32K, 23), GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24), GATE_IFR5(CLK_IFR_I2C1_AXI, CLK_TOP_I2C_SEL, 25), GATE_IFR5(CLK_IFR_I2C2_AXI, CLK_TOP_I2C_SEL, 26), @@ -858,7 +753,8 @@ static const struct mtk_gate ifr_clks[] = { }; static const struct mtk_clk_tree mt8365_infracfg_tree = { - .xtal_rate = 26 * MHZ, + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static int mt8365_apmixedsys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index e6ced91fd06..d6e58be8e22 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -17,6 +17,14 @@ #define MT8512_PLL_FMIN (1500UL * MHZ) #define MT8512_CON0_RST_BAR BIT(23) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ @@ -41,9 +49,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, 0, 22, 0x0310, 24, 0x0310, 0, 0), PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001, - HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), + CLK_PLL_HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001, - HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), + CLK_PLL_HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, 0, 22, 0x0354, 24, 0x0354, 0, 0), PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, @@ -60,7 +68,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -69,7 +77,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -122,8 +130,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_SYS_26M_D2, CLK_PAD_CLK26M, 1, 2), FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1), @@ -135,317 +143,317 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2), }; -static const int axi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K +static const struct mtk_parent axi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), }; -static const int mem_parents[] = { - CLK_TOP_DSPPLL, - CLK_TOP_IPPLL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent mem_parents[] = { + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int uart_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int spis_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYSPLL4_D2 +static const struct mtk_parent spis_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), }; -static const int msdc50_0_hc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL2_D2 +static const struct mtk_parent msdc50_0_hc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), }; -static const int msdc50_0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent msdc50_0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int msdc50_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MSDCPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent msdc50_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MSDCPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int audio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL2_D4 +static const struct mtk_parent audio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_APLL2_D8, - CLK_TOP_SYS_26M_D2, - CLK_TOP_APLL1_D8, - CLK_TOP_UNIVPLL3_D4 +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_APLL2_D8), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_APLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), }; -static const int hapll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1, - CLK_TOP_APLL1_D2, - CLK_TOP_APLL1_D3, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL1_D8, - CLK_TOP_APLL1_D16, - CLK_TOP_SYS_26M_D2 +static const struct mtk_parent hapll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL1_D2), + TOP_PARENT(CLK_TOP_APLL1_D3), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL1_D8), + TOP_PARENT(CLK_TOP_APLL1_D16), + TOP_PARENT(CLK_TOP_SYS_26M_D2), }; -static const int hapll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D3, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D8, - CLK_TOP_APLL2_D16, - CLK_TOP_SYS_26M_D2 +static const struct mtk_parent hapll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D3), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D8), + TOP_PARENT(CLK_TOP_APLL2_D16), + TOP_PARENT(CLK_TOP_SYS_26M_D2), }; -static const int asm_l_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL_D5 +static const struct mtk_parent asm_l_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), }; -static const int aud_spdif_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_DSPPLL +static const struct mtk_parent aud_spdif_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL), }; -static const int aud_1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 +static const struct mtk_parent aud_1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), }; -static const int aud_2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 +static const struct mtk_parent aud_2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int ssusb_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 +static const struct mtk_parent ssusb_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), }; -static const int spm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D8 +static const struct mtk_parent spm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL3_D2, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_CLK32K +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_CLK32K), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), }; -static const int dsp_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_DSPPLL_D8, - CLK_TOP_APLL2_D4, - CLK_TOP_SYS_26M_D2, - CLK_TOP_CLK32K +static const struct mtk_parent dsp_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_DSPPLL_D8), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_CLK32K), }; -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_SYSPLL_D7, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_MSDCPLL_D2, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D7), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int spinfi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D8, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_SYSPLL1_D8, - CLK_TOP_SYSPLL4_D2, - CLK_TOP_SYSPLL2_D4, - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL3_D2 +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_SYSPLL4_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D2), }; -static const int ecc_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent ecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_UNIVPLL2_D2 +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), }; -static const int gcpu_cpm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4 +static const struct mtk_parent gcpu_cpm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), }; -static const int mbist_diag_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYS_26M_D2 +static const struct mtk_parent mbist_diag_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYS_26M_D2), }; -static const int ip0_nna_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_DSPPLL_D2, - CLK_TOP_DSPPLL_D4, - CLK_TOP_IPPLL, - CLK_TOP_SYS_26M_D2, - CLK_TOP_IPPLL_D2, - CLK_TOP_MSDCPLL_D2 +static const struct mtk_parent ip0_nna_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_DSPPLL_D2), + TOP_PARENT(CLK_TOP_DSPPLL_D4), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_IPPLL_D2), + TOP_PARENT(CLK_TOP_MSDCPLL_D2), }; -static const int ip2_wfst_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL2_D2, - CLK_TOP_IPPLL, - CLK_TOP_IPPLL_D2, - CLK_TOP_SYS_26M_D2, - CLK_TOP_MSDCPLL +static const struct mtk_parent ip2_wfst_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D2), + TOP_PARENT(CLK_TOP_IPPLL), + TOP_PARENT(CLK_TOP_IPPLL_D2), + TOP_PARENT(CLK_TOP_SYS_26M_D2), + TOP_PARENT(CLK_TOP_MSDCPLL), }; -static const int sflash_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL1_D16, - CLK_TOP_SYSPLL2_D8, - CLK_TOP_SYSPLL3_D4, - CLK_TOP_UNIVPLL3_D4, - CLK_TOP_UNIVPLL1_D8, - CLK_TOP_USB20_192M_D2, - CLK_TOP_UNIVPLL2_D4 +static const struct mtk_parent sflash_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL1_D16), + TOP_PARENT(CLK_TOP_SYSPLL2_D8), + TOP_PARENT(CLK_TOP_SYSPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL3_D4), + TOP_PARENT(CLK_TOP_UNIVPLL1_D8), + TOP_PARENT(CLK_TOP_USB20_192M_D2), + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), }; -static const int sram_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DSPPLL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_APLL1, - CLK_TOP_APLL2, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_SYS_26M_D2 +static const struct mtk_parent sram_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DSPPLL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_SYS_26M_D2), }; -static const int mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_SYSPLL_D3, - CLK_TOP_SYSPLL1_D2, - CLK_TOP_SYSPLL_D5, - CLK_TOP_SYSPLL1_D4, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_SYSPLL_D3), + TOP_PARENT(CLK_TOP_SYSPLL1_D2), + TOP_PARENT(CLK_TOP_SYSPLL_D5), + TOP_PARENT(CLK_TOP_SYSPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int dpi0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_TCONPLL_D2, - CLK_TOP_TCONPLL_D4, - CLK_TOP_TCONPLL_D8, - CLK_TOP_TCONPLL_D16, - CLK_TOP_TCONPLL_D32, - CLK_TOP_TCONPLL_D64 +static const struct mtk_parent dpi0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TCONPLL_D2), + TOP_PARENT(CLK_TOP_TCONPLL_D4), + TOP_PARENT(CLK_TOP_TCONPLL_D8), + TOP_PARENT(CLK_TOP_TCONPLL_D16), + TOP_PARENT(CLK_TOP_TCONPLL_D32), + TOP_PARENT(CLK_TOP_TCONPLL_D64), }; -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL1_D2, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL1_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int occ_104m_parents[] = { - CLK_TOP_UNIVPLL2_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent occ_104m_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL2_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int occ_68m_parents[] = { - CLK_TOP_SYSPLL1_D8, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent occ_68m_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL1_D8), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; -static const int occ_182m_parents[] = { - CLK_TOP_SYSPLL2_D2, - CLK_TOP_UNIVPLL1_D4, - CLK_TOP_UNIVPLL2_D8 +static const struct mtk_parent occ_182m_parents[] = { + TOP_PARENT(CLK_TOP_SYSPLL2_D2), + TOP_PARENT(CLK_TOP_UNIVPLL1_D4), + TOP_PARENT(CLK_TOP_UNIVPLL2_D8), }; static const struct mtk_composite top_muxes[] = { @@ -785,8 +793,9 @@ static const struct mtk_gate infra_clks[] = { }; static const struct mtk_clk_tree mt8512_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_SYSPLL1_D2, .muxes_offs = CLK_TOP_AXI_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 4985ba3e5ce..1070dd1551b 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -16,6 +16,14 @@ #define MT8516_PLL_FMAX (1502UL * MHZ) #define MT8516_CON0_RST_BAR BIT(27) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -37,9 +45,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0, 21, 0x0104, 24, 0x0104, 0), PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001, - HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), + CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001, - HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), + CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0, 21, 0x0164, 24, 0x0164, 0), PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0, @@ -50,7 +58,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _parent, _rate) \ FIXED_CLK(_id, _parent, CLK_PARENT_TOPCKGEN, _rate) @@ -62,7 +70,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -109,388 +117,388 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2), FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2), FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2), FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2), FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2), }; -static const int uart0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, +static const struct mtk_parent uart0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int gfmux_emi1x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DMPLL, +static const struct mtk_parent gfmux_emi1x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int emi_ddrphy_parents[] = { - CLK_TOP_GFMUX_EMI1X_SEL, - CLK_TOP_GFMUX_EMI1X_SEL, +static const struct mtk_parent emi_ddrphy_parents[] = { + TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL), + TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL), }; -static const int ahb_infra_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D10, +static const struct mtk_parent ahb_infra_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D10), }; -static const int csw_mux_mfg_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MMPLL380M, +static const struct mtk_parent csw_mux_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MMPLL380M), }; -static const int msdc0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2, +static const struct mtk_parent msdc0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int pwm_mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, +static const struct mtk_parent pwm_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int uart1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, +static const struct mtk_parent uart1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int msdc1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2, +static const struct mtk_parent msdc1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int spm_52m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, +static const struct mtk_parent spm_52m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int pmicspi_parents[] = { - CLK_TOP_UNIVPLL_D20, - CLK_TOP_USB_PHY48M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK26M, +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_USB_PHY48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK26M), }; -static const int qaxi_aud26m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_AHB_INFRA_SEL, +static const struct mtk_parent qaxi_aud26m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_AHB_INFRA_SEL), }; -static const int aud_intbus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D22, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D11, +static const struct mtk_parent aud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D22), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D11), }; -static const int nfi2x_pad_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5 +static const struct mtk_parent nfi2x_pad_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), }; -static const int nfi1x_pad_parents[] = { - CLK_TOP_AHB_INFRA_SEL, - CLK_TOP_NFI1X, +static const struct mtk_parent nfi1x_pad_parents[] = { + TOP_PARENT(CLK_TOP_AHB_INFRA_SEL), + TOP_PARENT(CLK_TOP_NFI1X), }; -static const int mfg_mm_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CSW_MUX_MFG_SEL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D3, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D14 +static const struct mtk_parent mfg_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CSW_MUX_MFG_SEL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D14), }; -static const int ddrphycfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D16 +static const struct mtk_parent ddrphycfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D16), }; -static const int usb_78m_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D20, +static const struct mtk_parent usb_78m_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D20), }; -static const int spinor_parents[] = { - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int msdc2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D8, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D16, - CLK_TOP_MMPLL_200M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MMPLL_D2 +static const struct mtk_parent msdc2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_MMPLL_200M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20 +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), }; -static const int axi_mfg_in_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MMPLL380M, +static const struct mtk_parent axi_mfg_in_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MMPLL380M), }; -static const int slow_mfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D24 +static const struct mtk_parent slow_mfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int aud1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1 +static const struct mtk_parent aud1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1), }; -static const int aud2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2 +static const struct mtk_parent aud2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2), }; -static const int aud_engen1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_RG_APLL1_D2_EN, - CLK_TOP_RG_APLL1_D4_EN, - CLK_TOP_RG_APLL1_D8_EN +static const struct mtk_parent aud_engen1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_RG_APLL1_D2_EN), + TOP_PARENT(CLK_TOP_RG_APLL1_D4_EN), + TOP_PARENT(CLK_TOP_RG_APLL1_D8_EN), }; -static const int aud_engen2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_RG_APLL2_D2_EN, - CLK_TOP_RG_APLL2_D4_EN, - CLK_TOP_RG_APLL2_D8_EN +static const struct mtk_parent aud_engen2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_RG_APLL2_D2_EN), + TOP_PARENT(CLK_TOP_RG_APLL2_D4_EN), + TOP_PARENT(CLK_TOP_RG_APLL2_D8_EN), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int aud_i2s0_m_parents[] = { - CLK_TOP_RG_AUD1, - CLK_TOP_RG_AUD2 +static const struct mtk_parent aud_i2s0_m_parents[] = { + TOP_PARENT(CLK_TOP_RG_AUD1), + TOP_PARENT(CLK_TOP_RG_AUD2), }; -static const int pwm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int spi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int aud_spdifin_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2 +static const struct mtk_parent aud_spdifin_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), }; -static const int uart2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24 +static const struct mtk_parent uart2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int bsi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D20 +static const struct mtk_parent bsi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D20), }; -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int csw_nfiecc_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D5 +static const struct mtk_parent csw_nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D5), }; -static const int nfiecc_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_NFI2X_PAD_SEL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CSW_NFIECC_SEL, +static const struct mtk_parent nfiecc_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_NFI2X_PAD_SEL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CSW_NFIECC_SEL), }; static const struct mtk_composite top_muxes[] = { @@ -737,8 +745,9 @@ static const struct mtk_gate top_clks[] = { }; static const struct mtk_clk_tree mt8516_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_DMPLL, .muxes_offs = CLK_TOP_UART0_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index 2fc492e7170..2b213e720a0 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -16,6 +16,14 @@ #define MT8518_PLL_FMAX (3000UL * MHZ) #define MT8518_CON0_RST_BAR BIT(27) +enum { + CLK_PAD_CLK26M, +}; + +static const ulong ext_clock_rates[] = { + [CLK_PAD_CLK26M] = 26 * MHZ, +}; + /* apmixedsys */ #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ @@ -37,9 +45,9 @@ static const struct mtk_pll_data apmixed_plls[] = { PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0, 21, 0x0104, 24, 0x0104, 0), PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001, - HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), + CLK_PLL_HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001, - HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), + CLK_PLL_HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0, 21, 0x0164, 24, 0x0164, 0), PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, @@ -52,7 +60,7 @@ static const struct mtk_pll_data apmixed_plls[] = { /* topckgen */ #define FIXED_CLK0(_id, _rate) \ - FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate) + FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate) #define FIXED_CLK1(_id, _rate) \ FIXED_CLK(_id, CLK_TOP_CLK_NULL, CLK_PARENT_TOPCKGEN, _rate) @@ -64,7 +72,7 @@ static const struct mtk_pll_data apmixed_plls[] = { FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) #define FACTOR2(_id, _parent, _mult, _div) \ - FACTOR(_id, _parent, _mult, _div, 0) + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT) static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000), @@ -74,7 +82,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { }; static const struct mtk_fixed_factor top_fixed_divs[] = { - FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_DMPLL, CLK_PAD_CLK26M, 1, 1), FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8), FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16), @@ -109,11 +117,11 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3), FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4), FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8), - FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), - FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2), - FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4), - FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), - FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793), + FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1), + FACTOR2(CLK_TOP_CLK26M_D2, CLK_PAD_CLK26M, 1, 2), + FACTOR2(CLK_TOP_CLK26M_D4, CLK_PAD_CLK26M, 1, 4), + FACTOR2(CLK_TOP_CLK26M_D8, CLK_PAD_CLK26M, 1, 8), + FACTOR2(CLK_TOP_CLK26M_D793, CLK_PAD_CLK26M, 1, 793), FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1), FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2), FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4), @@ -134,1050 +142,1050 @@ static const struct mtk_fixed_factor top_fixed_divs[] = { FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2), }; -static const int uart0_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24 +static const struct mtk_parent uart0_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), }; -static const int emi1x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_DMPLL +static const struct mtk_parent emi1x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_DMPLL), }; -static const int emi_ddrphy_parents[] = { - CLK_TOP_EMI1X_SEL, - CLK_TOP_EMI1X_SEL +static const struct mtk_parent emi_ddrphy_parents[] = { + TOP_PARENT(CLK_TOP_EMI1X_SEL), + TOP_PARENT(CLK_TOP_EMI1X_SEL), }; -static const int msdc1_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12 +static const struct mtk_parent msdc1_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), }; -static const int pwm_mm_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent pwm_mm_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int pmicspi_parents[] = { - CLK_TOP_UNIVPLL_D20, - CLK_TOP_USB20_48M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2 +static const struct mtk_parent pmicspi_parents[] = { + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_USB20_48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), }; -static const int nfi2x_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D8, - CLK_TOP_MAINPLL_D10, - CLK_TOP_MAINPLL_D12 +static const struct mtk_parent nfi2x_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D12), }; -static const int ddrphycfg_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D16 +static const struct mtk_parent ddrphycfg_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D16), }; -static const int smi_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_MAINPLL_D7, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D14 +static const struct mtk_parent smi_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D14), }; -static const int usb_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D20 +static const struct mtk_parent usb_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D20), }; -static const int spinor_parents[] = { - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12 +static const struct mtk_parent spinor_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), }; -static const int eth_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D40, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D20 +static const struct mtk_parent eth_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D40), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D20), }; -static const int aud1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL +static const struct mtk_parent aud1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), }; -static const int aud2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL +static const struct mtk_parent aud2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), }; -static const int i2c_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_USB20_48M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D8 +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_USB20_48M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), }; -static const int aud_i2s0_m_parents[] = { - CLK_TOP_AUD1, - CLK_TOP_AUD2 +static const struct mtk_parent aud_i2s0_m_parents[] = { + TOP_PARENT(CLK_TOP_AUD1), + TOP_PARENT(CLK_TOP_AUD2), }; -static const int aud_spdifin_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D2, - CLK_TOP_TVDPLL +static const struct mtk_parent aud_spdifin_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL), }; -static const int dbg_atclk_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5 +static const struct mtk_parent dbg_atclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), }; -static const int png_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent png_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int sej_13m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_CLK26M_D2 +static const struct mtk_parent sej_13m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK26M_D2), }; -static const int imgrz_sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_MAINPLL_D5, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6 +static const struct mtk_parent imgrz_sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), }; -static const int graph_eclk_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D6, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_MAINPLL_D7, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_MAINPLL_D8 +static const struct mtk_parent graph_eclk_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_MAINPLL_D8), }; -static const int fdbi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D12, - CLK_TOP_MAINPLL_D14, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_TVDPLL_D2, - CLK_TOP_TVDPLL_D4, - CLK_TOP_TVDPLL_D8, - CLK_TOP_TVDPLL_D16 +static const struct mtk_parent fdbi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_MAINPLL_D14), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_TVDPLL_D16), }; -static const int faudio_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_APLL1_D4, - CLK_TOP_APLL2_D4 +static const struct mtk_parent faudio_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_APLL1_D4), + TOP_PARENT(CLK_TOP_APLL2_D4), }; -static const int fa2sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL, - CLK_TOP_RG_APLL1_D2, - CLK_TOP_RG_APLL1_D4, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_RG_APLL1_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_RG_APLL1_D3 +static const struct mtk_parent fa2sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL1_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D4), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D3), }; -static const int fa1sys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL, - CLK_TOP_RG_APLL2_D2, - CLK_TOP_RG_APLL2_D4, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_RG_APLL2_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_RG_APLL2_D3 +static const struct mtk_parent fa1sys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL2_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_RG_APLL2_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D3), }; -static const int fasm_m_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D7 +static const struct mtk_parent fasm_m_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), }; -static const int fecc_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D3 +static const struct mtk_parent fecc_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D3), }; -static const int pe2_mac_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10 +static const struct mtk_parent pe2_mac_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), }; -static const int cmsys_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_MAINPLL_D5, - CLK_TOP_APLL2, - CLK_TOP_APLL2_D2, - CLK_TOP_APLL2_D4, - CLK_TOP_APLL2_D3 +static const struct mtk_parent cmsys_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_APLL2_D2), + TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_APLL2_D3), }; -static const int gcpu_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D4, - CLK_TOP_MAINPLL_D5, - CLK_TOP_MAINPLL_D6, - CLK_TOP_MAINPLL_D7, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent gcpu_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D5), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int spis_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D5, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D3 +static const struct mtk_parent spis_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D5), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), }; -static const int apll1_ref_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL +static const struct mtk_parent apll1_ref_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), }; -static const int int_32k_parents[] = { - CLK_TOP_CLK32K, - CLK_TOP_CLK26M_D793 +static const struct mtk_parent int_32k_parents[] = { + TOP_PARENT(CLK_TOP_CLK32K), + TOP_PARENT(CLK_TOP_CLK26M_D793), }; -static const int apll1_src_parents[] = { - CLK_TOP_APLL1, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL +static const struct mtk_parent apll1_src_parents[] = { + TOP_PARENT(CLK_TOP_APLL1), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), }; -static const int apll2_src_parents[] = { - CLK_TOP_APLL2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL +static const struct mtk_parent apll2_src_parents[] = { + TOP_PARENT(CLK_TOP_APLL2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), }; -static const int faud_intbus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D20 +static const struct mtk_parent faud_intbus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), }; -static const int axibus_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_MAINPLL_D11, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_APLL2_D8 +static const struct mtk_parent axibus_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D11), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_APLL2_D8), }; -static const int hapll1_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL1_SRC_SEL, - CLK_TOP_RG_APLL1_D2, - CLK_TOP_RG_APLL1_D4, - CLK_TOP_RG_APLL1_D8, - CLK_TOP_RG_APLL1_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M_D8, - CLK_TOP_RG_APLL1_D3 +static const struct mtk_parent hapll1_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL1_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL1_D2), + TOP_PARENT(CLK_TOP_RG_APLL1_D4), + TOP_PARENT(CLK_TOP_RG_APLL1_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M_D8), + TOP_PARENT(CLK_TOP_RG_APLL1_D3), }; -static const int hapll2_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_APLL2_SRC_SEL, - CLK_TOP_RG_APLL2_D2, - CLK_TOP_RG_APLL2_D4, - CLK_TOP_RG_APLL2_D8, - CLK_TOP_RG_APLL2_D16, - CLK_TOP_CLK26M_D2, - CLK_TOP_CLK26M_D4, - CLK_TOP_RG_APLL2_D3 +static const struct mtk_parent hapll2_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_APLL2_SRC_SEL), + TOP_PARENT(CLK_TOP_RG_APLL2_D2), + TOP_PARENT(CLK_TOP_RG_APLL2_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D8), + TOP_PARENT(CLK_TOP_RG_APLL2_D16), + TOP_PARENT(CLK_TOP_CLK26M_D2), + TOP_PARENT(CLK_TOP_CLK26M_D4), + TOP_PARENT(CLK_TOP_RG_APLL2_D3), }; -static const int spinfi_parents[] = { - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D24, - CLK_TOP_UNIVPLL_D20, - CLK_TOP_MAINPLL_D22, - CLK_TOP_UNIVPLL_D16, - CLK_TOP_MAINPLL_D16, - CLK_TOP_UNIVPLL_D12, - CLK_TOP_UNIVPLL_D10, - CLK_TOP_MAINPLL_D11 +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D24), + TOP_PARENT(CLK_TOP_UNIVPLL_D20), + TOP_PARENT(CLK_TOP_MAINPLL_D22), + TOP_PARENT(CLK_TOP_UNIVPLL_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_D12), + TOP_PARENT(CLK_TOP_UNIVPLL_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D11), }; -static const int msdc0_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_APMIXED_MMPLL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2 +static const struct mtk_parent msdc0_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_APMIXED_MMPLL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), }; -static const int msdc0_clk50_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D6 +static const struct mtk_parent msdc0_clk50_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D6), }; -static const int msdc2_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_UNIVPLL_D6, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_UNIVPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D16, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MMPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_MAINPLL_D12, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_APMIXED_MMPLL +static const struct mtk_parent msdc2_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_UNIVPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D16), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MMPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_MAINPLL_D12), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_APMIXED_MMPLL), }; -static const int disp_dpi_ck_parents[] = { - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK26M, - CLK_TOP_TVDPLL_D2, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D4, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D8, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_CLK_NULL, - CLK_TOP_TVDPLL_D16 +static const struct mtk_parent disp_dpi_ck_parents[] = { + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK26M), + TOP_PARENT(CLK_TOP_TVDPLL_D2), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D4), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D8), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_CLK_NULL), + TOP_PARENT(CLK_TOP_TVDPLL_D16), }; static const struct mtk_composite top_muxes[] = { @@ -1493,8 +1501,9 @@ static const struct mtk_gate top_clks[] = { }; static const struct mtk_clk_tree mt8518_clk_tree = { - .xtal_rate = 26 * MHZ, - .xtal2_rate = 26 * MHZ, + .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), .fdivs_offs = CLK_TOP_DMPLL, .muxes_offs = CLK_TOP_UART0_SEL, .plls = apmixed_plls, diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4de38719e1..3557aeac3d5 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -85,6 +85,34 @@ static int mtk_common_clk_get_unmapped_id(struct clk *clk) return -ENOENT; } +static bool mtk_clk_id_is_pll(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->plls && mapped_id < tree->num_plls; +} + +static bool mtk_clk_id_is_fclk(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->fclks && mapped_id < tree->num_fclks; +} + +static bool mtk_clk_id_is_fdiv(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->fdivs && mapped_id >= tree->fdivs_offs && + mapped_id < tree->fdivs_offs + tree->num_fdivs; +} + +static bool mtk_clk_id_is_mux(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->muxes && mapped_id >= tree->muxes_offs && + mapped_id < tree->muxes_offs + tree->num_muxes; +} + +static bool mtk_clk_id_is_gate(const struct mtk_clk_tree *tree, int mapped_id) +{ + return tree->gates && mapped_id >= tree->gates_offs && + mapped_id < tree->gates_offs + tree->num_gates; +} + static int mtk_dummy_enable(struct clk *clk) { return 0; @@ -140,6 +168,14 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) return 0; } +static ulong mtk_ext_clock_get_rate(const struct mtk_clk_tree *tree, int id) +{ + if (!tree->ext_clk_rates || id >= tree->num_ext_clks) + return -ENOENT; + + return tree->ext_clk_rates[id]; +} + /* * In case the rate change propagation to parent clocks is undesirable, * this function is recursively called to find the parent to calculate @@ -168,28 +204,83 @@ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, return clk_get_rate(&parent); } +const struct clk_ops mtk_clk_apmixedsys_ops; +const struct clk_ops mtk_clk_topckgen_ops; +const struct clk_ops mtk_clk_infrasys_ops; + +static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, + const int parent, u16 flags) +{ + struct udevice *parent_dev; + + switch (flags & CLK_PARENT_MASK) { + case CLK_PARENT_APMIXED: + /* APMIXEDSYS can be parent or grandparent. */ + if (dev_get_driver_ops(clk->dev) == &mtk_clk_apmixedsys_ops) + parent_dev = clk->dev; + else if (dev_get_driver_ops(priv->parent) == &mtk_clk_apmixedsys_ops) + parent_dev = priv->parent; + else if (dev_get_driver_ops(dev_get_parent(priv->parent)) == &mtk_clk_apmixedsys_ops) + parent_dev = dev_get_parent(priv->parent); + else + return -EINVAL; + + break; + case CLK_PARENT_TOPCKGEN: + if (dev_get_driver_ops(clk->dev) == &mtk_clk_topckgen_ops) + parent_dev = clk->dev; + else if (dev_get_driver_ops(priv->parent) == &mtk_clk_topckgen_ops) + parent_dev = priv->parent; + else + return -EINVAL; + + break; + case CLK_PARENT_INFRASYS: + if (dev_get_driver_ops(clk->dev) != &mtk_clk_infrasys_ops) + return -EINVAL; + + parent_dev = clk->dev; + break; + case CLK_PARENT_EXT: + return mtk_ext_clock_get_rate(priv->tree, parent); + default: + parent_dev = NULL; + break; + } + + return mtk_clk_find_parent_rate(clk, parent, parent_dev); +} + +static ulong mtk_clk_mux_get_rate(struct clk *clk, u32 off) +{ + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux = &priv->tree->muxes[off]; + const struct mtk_parent *parent; + u32 index; + + index = readl(priv->base + mux->mux_reg); + index &= mux->mux_mask << mux->mux_shift; + index = index >> mux->mux_shift; + parent = &mux->parent[index]; + + return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); +} + static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, u32 parent_type, const struct mtk_composite *mux) { u32 val, index = 0; - if (mux->flags & CLK_PARENT_MIXED) { - /* - * Assume parent_type in clk_tree to be always set with - * CLK_PARENT_MIXED implementation. If it's not, assume - * not parent clk ID clash is possible. - */ - while (mux->parent_flags[index].id != parent || - (parent_type && (mux->parent_flags[index].flags & CLK_PARENT_MASK) != - parent_type)) - if (++index == mux->num_parents) - return -EINVAL; - } else { - while (mux->parent[index] != parent) - if (++index == mux->num_parents) - return -EINVAL; - } + /* + * Assume parent_type in clk_tree to be always set. If it's not, assume + * parent clk ID clash is not possible. + */ + while (mux->parent[index].id != parent || + (parent_type && (mux->parent[index].flags & CLK_PARENT_MASK) != + parent_type)) + if (++index == mux->num_parents) + return -EINVAL; if (mux->flags & CLK_MUX_SETCLR_UPD) { val = (mux->mux_mask << mux->mux_shift); @@ -259,11 +350,8 @@ static void mtk_clk_print_parent(const char *prefix, int parent, u32 flags) case CLK_PARENT_INFRASYS: parent_type_str = "infrasys"; break; - case CLK_PARENT_XTAL: - parent_type_str = "xtal"; - break; - case CLK_PARENT_MIXED: - parent_type_str = "mixed"; + case CLK_PARENT_EXT: + parent_type_str = "ext"; break; default: parent_type_str = "default"; @@ -293,18 +381,14 @@ static void mtk_clk_print_mux_parents(struct mtk_clk_priv *priv, /* Print parents separated by "/" and selected parent enclosed in "*"s */ for (i = 0; i < mux->num_parents; i++) { + const struct mtk_parent *parent = &mux->parent[i]; + if (i == selected) { printf("%s", prefix); prefix = "*"; } - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[i]; - - mtk_clk_print_parent(prefix, parent->id, parent->flags); - } else { - mtk_clk_print_parent(prefix, mux->parent[i], mux->flags); - } + mtk_clk_print_parent(prefix, parent->id, parent->flags); prefix = "/"; @@ -328,15 +412,10 @@ static const int mtk_apmixedsys_of_xlate(struct clk *clk, return ret; /* apmixedsys only uses plls and gates. */ + if (!mtk_clk_id_is_pll(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->plls && clk->id < tree->num_plls) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, @@ -415,16 +494,21 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_priv *priv, u32 id, * @postdiv: The post divider (output) * @freq: The desired target frequency */ -static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id, - u32 *pcw, u32 *postdiv, u32 freq) +static int mtk_pll_calc_values(struct mtk_clk_priv *priv, struct clk *clk, + u32 *pcw, u32 *postdiv, u32 freq) { const struct mtk_pll_data *pll; - unsigned long fmin; + const struct mtk_parent *parent = &priv->tree->pll_parent; + unsigned long xtal_rate, fmin; u64 _pcw; int ibits; u32 val; - pll = &priv->tree->plls[id]; + xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags); + if (IS_ERR_VALUE(xtal_rate)) + return xtal_rate; + + pll = &priv->tree->plls[clk->id]; fmin = pll->fmin ? pll->fmin : 1000 * MHZ; if (freq > pll->fmax) @@ -439,9 +523,11 @@ static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id, /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; _pcw = ((u64)freq << val) << (pll->pcwbits - ibits); - do_div(_pcw, priv->tree->xtal2_rate); + do_div(_pcw, xtal_rate); *pcw = (u32)_pcw; + + return 0; } static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) @@ -449,11 +535,15 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); u32 pcw = 0; u32 postdiv; + int ret; - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) + if (!mtk_clk_id_is_pll(priv->tree, clk->id)) return -EINVAL; - mtk_pll_calc_values(priv, clk->id, &pcw, &postdiv, rate); + ret = mtk_pll_calc_values(priv, clk, &pcw, &postdiv, rate); + if (ret) + return ret; + mtk_pll_set_rate_regs(priv, clk->id, pcw, postdiv); return 0; @@ -462,17 +552,24 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate) static ulong mtk_apmixedsys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_parent *parent; const struct mtk_pll_data *pll; const struct mtk_gate *gate; + unsigned long xtal_rate; u32 postdiv; u32 pcw; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } + parent = &priv->tree->pll_parent; + xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags); + if (IS_ERR_VALUE(xtal_rate)) + return xtal_rate; + pll = &priv->tree->plls[clk->id]; postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & @@ -482,8 +579,7 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk) pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift; pcw &= GENMASK(pll->pcwbits - 1, 0); - return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate, - pcw, postdiv); + return __mtk_pll_recalc_rate(pll, xtal_rate, pcw, postdiv); } static int mtk_apmixedsys_enable(struct clk *clk) @@ -494,7 +590,7 @@ static int mtk_apmixedsys_enable(struct clk *clk) u32 r; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_enable(priv->base, gate); } @@ -515,7 +611,7 @@ static int mtk_apmixedsys_enable(struct clk *clk) udelay(20); - if (pll->flags & HAVE_RST_BAR) { + if (pll->flags & CLK_PLL_HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r |= pll->rst_bar_mask; writel(r, priv->base + pll->reg + REG_CON0); @@ -532,14 +628,14 @@ static int mtk_apmixedsys_disable(struct clk *clk) u32 r; /* GATE handling */ - if (priv->tree->gates && clk->id >= priv->tree->gates_offs) { + if (mtk_clk_id_is_gate(priv->tree, clk->id)) { gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_disable(priv->base, gate); } pll = &priv->tree->plls[clk->id]; - if (pll->flags & HAVE_RST_BAR) { + if (pll->flags & CLK_PLL_HAVE_RST_BAR) { r = readl(priv->base + pll->reg + REG_CON0); r &= ~pll->rst_bar_mask; writel(r, priv->base + pll->reg + REG_CON0); @@ -602,23 +698,11 @@ static const int mtk_topckgen_of_xlate(struct clk *clk, return ret; /* topckgen only uses fclks, fdivs, muxes and gates. */ + if (!mtk_clk_id_is_fclk(tree, clk->id) && !mtk_clk_id_is_fdiv(tree, clk->id) && + !mtk_clk_id_is_mux(tree, clk->id) && !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->fclks && clk->id < tree->num_fclks) - return 0; - - if (tree->fdivs && clk->id >= tree->fdivs_offs && - clk->id < tree->fdivs_offs + tree->num_fdivs) - return 0; - - if (tree->muxes && clk->id >= tree->muxes_offs && - clk->id < tree->muxes_offs + tree->num_muxes) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, @@ -637,105 +721,34 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; ulong rate; - switch (fdiv->flags & CLK_PARENT_MASK) { - case CLK_PARENT_APMIXED: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, - priv->parent); - break; - case CLK_PARENT_TOPCKGEN: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - break; - - case CLK_PARENT_XTAL: - default: - rate = priv->tree->xtal_rate; - } - + rate = mtk_find_parent_rate(priv, clk, fdiv->parent, fdiv->flags); if (IS_ERR_VALUE(rate)) return rate; return mtk_factor_recalc_rate(fdiv, rate); } -static ulong mtk_topckgen_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, - const int parent, u16 flags) -{ - switch (flags & CLK_PARENT_MASK) { - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; - case CLK_PARENT_APMIXED: - return mtk_clk_find_parent_rate(clk, parent, priv->parent); - default: - return mtk_clk_find_parent_rate(clk, parent, NULL); - } -} - -static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - u32 index; - - index = readl(priv->base + mux->mux_reg); - index &= mux->mux_mask << mux->mux_shift; - index = index >> mux->mux_shift; - - /* - * Parents can be either from APMIXED or TOPCKGEN, - * inspect the mtk_parent struct to check the source - */ - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[index]; - - return mtk_topckgen_find_parent_rate(priv, clk, parent->id, - parent->flags); - } - - if (mux->parent[index] == CLK_XTAL && - !(priv->tree->flags & CLK_BYPASS_XTAL)) - return priv->tree->xtal_rate; - - return mtk_topckgen_find_parent_rate(priv, clk, mux->parent[index], - mux->flags); -} - -static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, - const int parent, u16 flags) -{ - switch (flags & CLK_PARENT_MASK) { - case CLK_PARENT_XTAL: - return priv->tree->xtal_rate; - /* Assume the second level parent is always APMIXED */ - case CLK_PARENT_APMIXED: - priv = dev_get_priv(priv->parent); - fallthrough; - case CLK_PARENT_TOPCKGEN: - return mtk_clk_find_parent_rate(clk, parent, priv->parent); - default: - return mtk_clk_find_parent_rate(clk, parent, NULL); - } -} - static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_fclk(tree, clk->id)) + return tree->fclks[clk->id].rate; + + if (mtk_clk_id_is_fdiv(tree, clk->id)) + return mtk_topckgen_get_factor_rate(clk, clk->id - tree->fdivs_offs); + + if (mtk_clk_id_is_mux(tree, clk->id)) + return mtk_clk_mux_get_rate(clk, clk->id - tree->muxes_offs); + + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; - return mtk_clk_find_parent_rate(clk, gate->parent, NULL); + return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } - if (clk->id < priv->tree->fdivs_offs) - return priv->tree->fclks[clk->id].rate; - else if (clk->id < priv->tree->muxes_offs) - return mtk_topckgen_get_factor_rate(clk, clk->id - - priv->tree->fdivs_offs); - else - return mtk_topckgen_get_mux_rate(clk, clk->id - - priv->tree->muxes_offs); + return -ENOENT; } static int mtk_clk_mux_enable(struct clk *clk) @@ -744,7 +757,7 @@ static int mtk_clk_mux_enable(struct clk *clk) const struct mtk_composite *mux; u32 val; - if (clk->id < priv->tree->muxes_offs) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; @@ -761,7 +774,7 @@ static int mtk_clk_mux_enable(struct clk *clk) writel(val, priv->base + mux->gate_reg); } - if (mux->flags & CLK_DOMAIN_SCPSYS) { + if (mux->flags & CLK_MUX_DOMAIN_SCPSYS) { /* enable scpsys clock off control */ writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0); writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN, @@ -776,8 +789,7 @@ static int mtk_topckgen_enable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; return mtk_gate_enable(priv->base, gate); @@ -792,7 +804,7 @@ static int mtk_clk_mux_disable(struct clk *clk) const struct mtk_composite *mux; u32 val; - if (clk->id < priv->tree->muxes_offs) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs]; @@ -817,8 +829,7 @@ static int mtk_topckgen_disable(struct clk *clk) struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_clk_tree *tree = priv->tree; - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) { + if (mtk_clk_id_is_gate(tree, clk->id)) { const struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs]; return mtk_gate_disable(priv->base, gate); @@ -834,8 +845,7 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent) int parent_unmapped_id; u32 parent_type; - if (!priv->tree->muxes || clk->id < priv->tree->muxes_offs || - clk->id >= priv->tree->muxes_offs + priv->tree->num_muxes) + if (!mtk_clk_id_is_mux(priv->tree, clk->id)) return 0; if (!parent_priv) @@ -915,29 +925,20 @@ static const int mtk_infrasys_of_xlate(struct clk *clk, return ret; /* ifrasys only uses fdivs, muxes and gates. */ + if (!mtk_clk_id_is_fdiv(tree, clk->id) && !mtk_clk_id_is_mux(tree, clk->id) && + !mtk_clk_id_is_gate(tree, clk->id)) + return -ENOENT; - if (tree->fdivs && clk->id >= tree->fdivs_offs && - clk->id < tree->fdivs_offs + tree->num_fdivs) - return 0; - - if (tree->muxes && clk->id >= tree->muxes_offs && - clk->id < tree->muxes_offs + tree->num_muxes) - return 0; - - if (tree->gates && clk->id >= tree->gates_offs && - clk->id < tree->gates_offs + tree->num_gates) - return 0; - - return -ENOENT; + return 0; } static int mtk_clk_infrasys_enable(struct clk *clk) { - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; /* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!mtk_clk_id_is_gate(priv->tree, clk->id)) return mtk_clk_mux_enable(clk); gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; @@ -946,11 +947,11 @@ static int mtk_clk_infrasys_enable(struct clk *clk) static int mtk_clk_infrasys_disable(struct clk *clk) { - struct mtk_cg_priv *priv = dev_get_priv(clk->dev); + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate; /* MUX handling */ - if (!priv->tree->gates || clk->id < priv->tree->gates_offs) + if (!mtk_clk_id_is_gate(priv->tree, clk->id)) return mtk_clk_mux_disable(clk); gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; @@ -963,81 +964,33 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off) const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; ulong rate; - switch (fdiv->flags & CLK_PARENT_MASK) { - case CLK_PARENT_TOPCKGEN: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, - priv->parent); - break; - case CLK_PARENT_XTAL: - rate = priv->tree->xtal_rate; - break; - default: - rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); - } - + rate = mtk_find_parent_rate(priv, clk, fdiv->parent, fdiv->flags); if (IS_ERR_VALUE(rate)) return rate; return mtk_factor_recalc_rate(fdiv, rate); } -static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off) -{ - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - u32 index; - - index = readl(priv->base + mux->mux_reg); - index &= mux->mux_mask << mux->mux_shift; - index = index >> mux->mux_shift; - - /* - * Parents can be either from TOPCKGEN or INFRACFG, - * inspect the mtk_parent struct to check the source - */ - if (mux->flags & CLK_PARENT_MIXED) { - const struct mtk_parent *parent = &mux->parent_flags[index]; - - return mtk_find_parent_rate(priv, clk, parent->id, parent->flags); - } - - if (mux->parent[index] == CLK_XTAL && - !(priv->tree->flags & CLK_BYPASS_XTAL)) - return priv->tree->xtal_rate; - - return mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags); -} - static ulong mtk_infrasys_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); ulong rate; - if (clk->id < priv->tree->fdivs_offs) { + if (mtk_clk_id_is_fclk(priv->tree, clk->id)) { rate = priv->tree->fclks[clk->id].rate; - } else if (clk->id < priv->tree->muxes_offs) { + } else if (mtk_clk_id_is_fdiv(priv->tree, clk->id)) { rate = mtk_infrasys_get_factor_rate(clk, clk->id - priv->tree->fdivs_offs); /* No gates defined or ID is a MUX */ - } else if (!priv->tree->gates || clk->id < priv->tree->gates_offs) { - rate = mtk_infrasys_get_mux_rate(clk, clk->id - - priv->tree->muxes_offs); + } else if (!mtk_clk_id_is_gate(priv->tree, clk->id)) { + rate = mtk_clk_mux_get_rate(clk, clk->id - priv->tree->muxes_offs); /* Only valid with muxes + gates implementation */ } else { - struct udevice *parent = NULL; const struct mtk_gate *gate; gate = &priv->tree->gates[clk->id - priv->tree->gates_offs]; - if (gate->flags & CLK_PARENT_TOPCKGEN) - parent = priv->parent; - /* - * Assume xtal_rate to be declared if some gates have - * XTAL as parent - */ - else if (gate->flags & CLK_PARENT_XTAL) - return priv->tree->xtal_rate; - rate = mtk_clk_find_parent_rate(clk, gate->parent, parent); + rate = mtk_find_parent_rate(priv, clk, gate->parent, gate->flags); } return rate; @@ -1146,12 +1099,8 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk) parent->driver != DM_DRIVER_GET(mtk_clk_topckgen)) { priv = dev_get_priv(parent); parent = priv->parent; - /* - * Assume xtal_rate to be declared if some gates have - * XTAL as parent - */ - } else if (gate->flags & CLK_PARENT_XTAL) { - return priv->tree->xtal_rate; + } else if (gate->flags & CLK_PARENT_EXT) { + return mtk_ext_clock_get_rate(priv->tree, gate->parent); } return mtk_clk_find_parent_rate(clk, gate->parent, parent); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index e618e982e8b..b39a62edc43 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -8,20 +8,14 @@ #define __DRV_CLK_MTK_H #include -#define CLK_XTAL 0 + #define MHZ (1000 * 1000) /* flags in struct mtk_clk_tree */ -/* clk id == 0 doesn't mean it's xtal clk - * This doesn't apply when CLK_PARENT_MIXED is defined. - * With CLK_PARENT_MIXED declare CLK_PARENT_XTAL for the - * relevant parent. - */ -#define CLK_BYPASS_XTAL BIT(0) +#define CLK_PLL_HAVE_RST_BAR BIT(0) -#define HAVE_RST_BAR BIT(0) -#define CLK_DOMAIN_SCPSYS BIT(0) +#define CLK_MUX_DOMAIN_SCPSYS BIT(0) #define CLK_MUX_SETCLR_UPD BIT(1) #define CLK_GATE_SETCLR BIT(0) @@ -33,13 +27,8 @@ #define CLK_PARENT_APMIXED BIT(4) #define CLK_PARENT_TOPCKGEN BIT(5) #define CLK_PARENT_INFRASYS BIT(6) -#define CLK_PARENT_XTAL BIT(7) -/* - * For CLK_PARENT_MIXED to correctly work, is required to - * define in clk_tree flags the clk type using the alias. - */ -#define CLK_PARENT_MIXED BIT(8) -#define CLK_PARENT_MASK GENMASK(8, 4) +#define CLK_PARENT_EXT BIT(7) +#define CLK_PARENT_MASK GENMASK(7, 4) #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 @@ -127,12 +116,17 @@ struct mtk_parent { .flags = _flags, \ } +#define APMIXED_PARENT(id) PARENT(id, CLK_PARENT_APMIXED) +#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN) +#define INFRA_PARENT(id) PARENT(id, CLK_PARENT_INFRASYS) +#define EXT_PARENT(id) PARENT(id, CLK_PARENT_EXT) +#define VOID_PARENT PARENT(-1, 0) + /** * struct mtk_composite - aggregate clock of mux, divider and gate clocks * * @id: unmapped ID of clocks - * @parent: unmapped ID of parent clocks - * @parent_flags: table of parent clocks with flags + * @parent: array of parent clocks * @mux_reg: hardware-specific mux register * @gate_reg: hardware-specific gate register * @mux_mask: mask to the mux bit field @@ -143,10 +137,7 @@ struct mtk_parent { */ struct mtk_composite { const int id; - union { - const int *parent; - const struct mtk_parent *parent_flags; - }; + const struct mtk_parent *parent; u32 mux_reg; u32 mux_set_reg; u32 mux_clr_reg; @@ -176,19 +167,6 @@ struct mtk_composite { #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) -#define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ - .id = _id, \ - .mux_reg = _reg, \ - .mux_shift = _shift, \ - .mux_mask = BIT(_width) - 1, \ - .gate_shift = -1, \ - .parent_flags = _parents, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_PARENT_MIXED | (_flags), \ - } -#define MUX_MIXED(_id, _parents, _reg, _shift, _width) \ - MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, 0) - #define MUX_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ .id = _id, \ .mux_reg = _reg, \ @@ -243,10 +221,20 @@ struct mtk_gate { u32 flags; }; +#define GATE_FLAGS(_id, _parent, _regs, _shift, _flags) { \ + .id = _id, \ + .parent = _parent, \ + .regs = _regs, \ + .shift = _shift, \ + .flags = _flags, \ + } + /* struct mtk_clk_tree - clock tree */ struct mtk_clk_tree { - unsigned long xtal_rate; - unsigned long xtal2_rate; + const struct mtk_parent pll_parent; + /* External fixed clocks - excluded from mapping. */ + const ulong *ext_clk_rates; + const int num_ext_clks; /* * Clock IDs may be remapped with an auxiliary table. Enable this by * defining .id_offs_map and .id_offs_map_size. This is needed e.g. when diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 62072e100b1..6ac7c9c5654 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -2,6 +2,5 @@ config CLK_MPFS bool "Clock support for Microchip PolarFire SoC" depends on CLK && CLK_CCF depends on SYSCON - depends on REGMAP help This enables support clock driver for Microchip PolarFire SoC platform. diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 34b63d4df34..07525c36432 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3506) += clk_rk3506.o obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index b5054e84c32..d143a6b85ee 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -13,15 +13,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 3200U * 1000000, VCO_MIN_HZ = 800 * 1000000, diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index e73bb6790af..97043b8693c 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 3200U * 1000000, VCO_MIN_HZ = 800 * 1000000, diff --git a/drivers/clk/rockchip/clk_rk3506.c b/drivers/clk/rockchip/clk_rk3506.c new file mode 100644 index 00000000000..38066c5c3e3 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3506.c @@ -0,0 +1,1166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#define LOG_CATEGORY UCLASS_CLK + +#include +#include +#include +#include +#include +#include +#include + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +/* + * [FRAC PLL]: GPLL, V0PLL, V1PLL + * - VCO Frequency: 950MHz to 3800MHZ + * - Output Frequency: 19MHz to 3800MHZ + * - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode) + * - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode) + * - post1div: 1 to 7 + * - post2div: 1 to 7 + */ +static struct rockchip_pll_rate_table rk3506_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1500000000, 1, 125, 2, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1350000000, 4, 225, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 125, 1, 1, 1, 0), + RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355), + RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127), + RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(96000000, 1, 48, 6, 2, 1, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rk3506_pll_clks[] = { + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3506_PLL_CON(0), + RK3506_MODE_CON, 0, 10, 0, rk3506_pll_rates), + [V0PLL] = PLL(pll_rk3328, PLL_V0PLL, RK3506_PLL_CON(8), + RK3506_MODE_CON, 2, 10, 0, rk3506_pll_rates), + [V1PLL] = PLL(pll_rk3328, PLL_V1PLL, RK3506_PLL_CON(16), + RK3506_MODE_CON, 4, 10, 0, rk3506_pll_rates), +}; + +#define RK3506_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \ +{ \ + .rate = _rate##U, \ + .aclk_div = (_aclk_m_core), \ + .pclk_div = (_pclk_dbg), \ +} + +/* SIGN-OFF: aclk_core: 500M, pclk_core: 125M, */ +static struct rockchip_cpu_rate_table rk3506_cpu_rates[] = { + RK3506_CPUCLK_RATE(1179648000, 1, 6), + RK3506_CPUCLK_RATE(903168000, 1, 5), + RK3506_CPUCLK_RATE(800000000, 1, 4), + RK3506_CPUCLK_RATE(589824000, 1, 3), + RK3506_CPUCLK_RATE(400000000, 1, 2), + RK3506_CPUCLK_RATE(200000000, 1, 1), + { /* sentinel */ }, +}; + +static int rk3506_armclk_get_rate(struct rk3506_clk_priv *priv) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(15)); + sel = FIELD_GET(CLK_CORE_SRC_SEL_MASK, con); + div = FIELD_GET(CLK_CORE_SRC_DIV_MASK, con); + + if (sel == CLK_CORE_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_CORE_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == CLK_CORE_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static int rk3506_armclk_set_rate(struct rk3506_clk_priv *priv, ulong new_rate) +{ + const struct rockchip_cpu_rate_table *rate; + u32 con, div, old_div, sel; + ulong old_rate, prate; + + rate = rockchip_get_cpu_settings(rk3506_cpu_rates, new_rate); + if (!rate) { + log_debug("unsupported cpu rate %lu\n", new_rate); + return -EINVAL; + } + + /* + * set up dependent divisors for PCLK and ACLK clocks. + */ + old_rate = rk3506_armclk_get_rate(priv); + if (new_rate >= old_rate) { + rk_clrsetreg(RK3506_CLKSEL_CON(15), ACLK_CORE_DIV_MASK, + FIELD_PREP(ACLK_CORE_DIV_MASK, rate->aclk_div)); + rk_clrsetreg(RK3506_CLKSEL_CON(16), PCLK_CORE_DIV_MASK, + FIELD_PREP(PCLK_CORE_DIV_MASK, rate->pclk_div)); + } + + if (new_rate == 589824000 || new_rate == 1179648000) { + sel = CLK_CORE_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, new_rate); + prate = priv->v0pll_hz; + } else if (new_rate == 903168000) { + sel = CLK_CORE_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, new_rate); + prate = priv->v1pll_hz; + } else { + sel = CLK_CORE_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, new_rate); + prate = priv->gpll_hz; + } + assert(div - 1 <= 31); + + con = readl(RK3506_CLKSEL_CON(15)); + old_div = FIELD_GET(CLK_CORE_SRC_DIV_MASK, con); + if (DIV_TO_RATE(prate, old_div) > new_rate) { + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_DIV_MASK, + FIELD_PREP(CLK_CORE_SRC_DIV_MASK, div - 1)); + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_SEL_MASK, + FIELD_PREP(CLK_CORE_SRC_SEL_MASK, sel)); + } else { + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_SEL_MASK, + FIELD_PREP(CLK_CORE_SRC_SEL_MASK, sel)); + rk_clrsetreg(RK3506_CLKSEL_CON(15), CLK_CORE_SRC_DIV_MASK, + FIELD_PREP(CLK_CORE_SRC_DIV_MASK, div - 1)); + } + + if (new_rate < old_rate) { + rk_clrsetreg(RK3506_CLKSEL_CON(15), ACLK_CORE_DIV_MASK, + FIELD_PREP(ACLK_CORE_DIV_MASK, rate->aclk_div)); + rk_clrsetreg(RK3506_CLKSEL_CON(16), PCLK_CORE_DIV_MASK, + FIELD_PREP(PCLK_CORE_DIV_MASK, rate->pclk_div)); + } + + return rk3506_armclk_get_rate(priv); +} + +static ulong rk3506_pll_div_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div; + ulong prate; + + switch (clk_id) { + case CLK_GPLL_DIV: + con = readl(RK3506_CLKSEL_CON(0)); + div = FIELD_GET(CLK_GPLL_DIV_MASK, con); + prate = priv->gpll_hz; + break; + case CLK_GPLL_DIV_100M: + con = readl(RK3506_CLKSEL_CON(0)); + div = FIELD_GET(CLK_GPLL_DIV_100M_MASK, con); + prate = priv->gpll_div_hz; + break; + case CLK_V0PLL_DIV: + con = readl(RK3506_CLKSEL_CON(1)); + div = FIELD_GET(CLK_V0PLL_DIV_MASK, con); + prate = priv->v0pll_hz; + break; + case CLK_V1PLL_DIV: + con = readl(RK3506_CLKSEL_CON(1)); + div = FIELD_GET(CLK_V1PLL_DIV_MASK, con); + prate = priv->v1pll_hz; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_pll_div_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div; + + switch (clk_id) { + case CLK_GPLL_DIV: + div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(0), CLK_GPLL_DIV_MASK, + FIELD_PREP(CLK_GPLL_DIV_MASK, div - 1)); + break; + case CLK_GPLL_DIV_100M: + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(0), CLK_GPLL_DIV_100M_MASK, + FIELD_PREP(CLK_GPLL_DIV_100M_MASK, div - 1)); + break; + case CLK_V0PLL_DIV: + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(1), CLK_V0PLL_DIV_MASK, + FIELD_PREP(CLK_V0PLL_DIV_MASK, div - 1)); + break; + case CLK_V1PLL_DIV: + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(1), CLK_V1PLL_DIV_MASK, + FIELD_PREP(CLK_V1PLL_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_pll_div_get_rate(priv, clk_id); +} + +static ulong rk3506_bus_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case ACLK_BUS_ROOT: + con = readl(RK3506_CLKSEL_CON(21)); + sel = FIELD_GET(ACLK_BUS_SEL_MASK, con); + div = FIELD_GET(ACLK_BUS_DIV_MASK, con); + break; + case HCLK_BUS_ROOT: + con = readl(RK3506_CLKSEL_CON(21)); + sel = FIELD_GET(HCLK_BUS_SEL_MASK, con); + div = FIELD_GET(HCLK_BUS_DIV_MASK, con); + break; + case PCLK_BUS_ROOT: + con = readl(RK3506_CLKSEL_CON(22)); + sel = FIELD_GET(PCLK_BUS_SEL_MASK, con); + div = FIELD_GET(PCLK_BUS_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == ACLK_BUS_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == ACLK_BUS_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == ACLK_BUS_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_bus_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (priv->v0pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = ACLK_BUS_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 31); + + switch (clk_id) { + case ACLK_BUS_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(21), + ACLK_BUS_SEL_MASK | ACLK_BUS_DIV_MASK, + FIELD_PREP(ACLK_BUS_SEL_MASK, sel) | + FIELD_PREP(ACLK_BUS_DIV_MASK, div - 1)); + break; + case HCLK_BUS_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(21), + HCLK_BUS_SEL_MASK | HCLK_BUS_DIV_MASK, + FIELD_PREP(HCLK_BUS_SEL_MASK, sel) | + FIELD_PREP(HCLK_BUS_DIV_MASK, div - 1)); + break; + case PCLK_BUS_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(22), + PCLK_BUS_SEL_MASK | PCLK_BUS_DIV_MASK, + FIELD_PREP(PCLK_BUS_SEL_MASK, sel) | + FIELD_PREP(PCLK_BUS_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_bus_get_rate(priv, clk_id); +} + +static ulong rk3506_peri_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case ACLK_HSPERI_ROOT: + con = readl(RK3506_CLKSEL_CON(49)); + sel = FIELD_GET(ACLK_HSPERI_SEL_MASK, con); + div = FIELD_GET(ACLK_HSPERI_DIV_MASK, con); + break; + case HCLK_LSPERI_ROOT: + con = readl(RK3506_CLKSEL_CON(29)); + sel = FIELD_GET(HCLK_LSPERI_SEL_MASK, con); + div = FIELD_GET(HCLK_LSPERI_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == ACLK_HSPERI_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == ACLK_HSPERI_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == ACLK_HSPERI_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_peri_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (priv->v0pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_div_hz % rate == 0) { + sel = ACLK_BUS_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = ACLK_BUS_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 31); + + switch (clk_id) { + case ACLK_HSPERI_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(49), + ACLK_HSPERI_SEL_MASK | ACLK_HSPERI_DIV_MASK, + FIELD_PREP(ACLK_HSPERI_SEL_MASK, sel) | + FIELD_PREP(ACLK_HSPERI_DIV_MASK, div - 1)); + break; + case HCLK_LSPERI_ROOT: + rk_clrsetreg(RK3506_CLKSEL_CON(29), + HCLK_LSPERI_SEL_MASK | HCLK_LSPERI_DIV_MASK, + FIELD_PREP(HCLK_LSPERI_SEL_MASK, sel) | + FIELD_PREP(HCLK_LSPERI_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_peri_get_rate(priv, clk_id); +} + +static ulong rk3506_sdmmc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(49)); + sel = FIELD_GET(CCLK_SDMMC_SEL_MASK, con); + div = FIELD_GET(CCLK_SDMMC_DIV_MASK, con); + + if (sel == CCLK_SDMMC_SEL_24M) + prate = OSC_HZ; + else if (sel == CCLK_SDMMC_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CCLK_SDMMC_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == CCLK_SDMMC_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_sdmmc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (OSC_HZ % rate == 0) { + sel = CCLK_SDMMC_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_hz % rate == 0) { + sel = CCLK_SDMMC_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = CCLK_SDMMC_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = CCLK_SDMMC_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 63); + + rk_clrsetreg(RK3506_CLKSEL_CON(49), + CCLK_SDMMC_SEL_MASK | CCLK_SDMMC_DIV_MASK, + FIELD_PREP(CCLK_SDMMC_SEL_MASK, sel) | + FIELD_PREP(CCLK_SDMMC_DIV_MASK, div - 1)); + + return rk3506_sdmmc_get_rate(priv, clk_id); +} + +static ulong rk3506_saradc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(54)); + sel = FIELD_GET(CLK_SARADC_SEL_MASK, con); + div = FIELD_GET(CLK_SARADC_DIV_MASK, con); + + if (sel == CLK_SARADC_SEL_24M) + prate = OSC_HZ; + else if (sel == CLK_SARADC_SEL_400K) + prate = 400000; + else if (sel == CLK_SARADC_SEL_32K) + prate = 32000; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_saradc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (32000 % rate == 0) { + sel = CLK_SARADC_SEL_32K; + div = 1; + } else if (400000 % rate == 0) { + sel = CLK_SARADC_SEL_400K; + div = 1; + } else { + sel = CLK_SARADC_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } + assert(div - 1 <= 15); + + rk_clrsetreg(RK3506_CLKSEL_CON(54), + CLK_SARADC_SEL_MASK | CLK_SARADC_DIV_MASK, + FIELD_PREP(CLK_SARADC_SEL_MASK, sel) | + FIELD_PREP(CLK_SARADC_DIV_MASK, div - 1)); + + return rk3506_saradc_get_rate(priv, clk_id); +} + +static ulong rk3506_tsadc_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div; + + con = readl(RK3506_CLKSEL_CON(61)); + switch (clk_id) { + case CLK_TSADC_TSEN: + div = FIELD_GET(CLK_TSADC_TSEN_DIV_MASK, con); + break; + case CLK_TSADC: + div = FIELD_GET(CLK_TSADC_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3506_tsadc_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div; + + switch (clk_id) { + case CLK_TSADC_TSEN: + div = DIV_ROUND_UP(OSC_HZ, rate); + assert(div - 1 <= 7); + rk_clrsetreg(RK3506_CLKSEL_CON(61), CLK_TSADC_TSEN_DIV_MASK, + FIELD_PREP(CLK_TSADC_TSEN_DIV_MASK, div - 1)); + break; + case CLK_TSADC: + div = DIV_ROUND_UP(OSC_HZ, rate); + assert(div - 1 <= 255); + rk_clrsetreg(RK3506_CLKSEL_CON(61), CLK_TSADC_DIV_MASK, + FIELD_PREP(CLK_TSADC_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_tsadc_get_rate(priv, clk_id); +} + +static ulong rk3506_i2c_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case CLK_I2C0: + con = readl(RK3506_CLKSEL_CON(32)); + sel = FIELD_GET(CLK_I2C0_SEL_MASK, con); + div = FIELD_GET(CLK_I2C0_DIV_MASK, con); + case CLK_I2C1: + con = readl(RK3506_CLKSEL_CON(32)); + sel = FIELD_GET(CLK_I2C1_SEL_MASK, con); + div = FIELD_GET(CLK_I2C1_DIV_MASK, con); + case CLK_I2C2: + con = readl(RK3506_CLKSEL_CON(33)); + sel = FIELD_GET(CLK_I2C2_SEL_MASK, con); + div = FIELD_GET(CLK_I2C2_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == CLK_I2C_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == CLK_I2C_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == CLK_I2C_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_i2c_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (priv->v0pll_hz % rate == 0) { + sel = CLK_I2C_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = CLK_I2C_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = CLK_I2C_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 15); + + switch (clk_id) { + case CLK_I2C0: + rk_clrsetreg(RK3506_CLKSEL_CON(32), + CLK_I2C0_SEL_MASK | CLK_I2C0_DIV_MASK, + FIELD_PREP(CLK_I2C0_SEL_MASK, sel) | + FIELD_PREP(CLK_I2C0_DIV_MASK, div - 1)); + break; + case CLK_I2C1: + rk_clrsetreg(RK3506_CLKSEL_CON(32), + CLK_I2C1_SEL_MASK | CLK_I2C1_DIV_MASK, + FIELD_PREP(CLK_I2C1_SEL_MASK, sel) | + FIELD_PREP(CLK_I2C1_DIV_MASK, div - 1)); + break; + case CLK_I2C2: + rk_clrsetreg(RK3506_CLKSEL_CON(33), + CLK_I2C2_SEL_MASK | CLK_I2C2_DIV_MASK, + FIELD_PREP(CLK_I2C2_SEL_MASK, sel) | + FIELD_PREP(CLK_I2C2_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_i2c_get_rate(priv, clk_id); +} + +static ulong rk3506_pwm_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case CLK_PWM0: + con = readl(RK3506_PMU_CLKSEL_CON(0)); + div = FIELD_GET(CLK_PWM0_DIV_MASK, con); + prate = priv->gpll_div_100mhz; + break; + case CLK_PWM1: + con = readl(RK3506_CLKSEL_CON(33)); + sel = FIELD_GET(CLK_PWM1_SEL_MASK, con); + div = FIELD_GET(CLK_PWM1_DIV_MASK, con); + if (sel == CLK_PWM1_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == CLK_PWM1_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == CLK_PWM1_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_pwm_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + switch (clk_id) { + case CLK_PWM0: + div = DIV_ROUND_UP(priv->gpll_div_100mhz, rate); + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_PMU_CLKSEL_CON(0), CLK_PWM0_DIV_MASK, + FIELD_PREP(CLK_PWM0_DIV_MASK, div - 1)); + break; + case CLK_PWM1: + if (priv->v0pll_hz % rate == 0) { + sel = CLK_PWM1_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = CLK_PWM1_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = CLK_PWM1_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 15); + rk_clrsetreg(RK3506_CLKSEL_CON(33), + CLK_PWM1_SEL_MASK | CLK_PWM1_DIV_MASK, + FIELD_PREP(CLK_PWM1_SEL_MASK, sel) | + FIELD_PREP(CLK_PWM1_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_pwm_get_rate(priv, clk_id); +} + +static ulong rk3506_spi_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div, sel; + ulong prate; + + switch (clk_id) { + case CLK_SPI0: + con = readl(RK3506_CLKSEL_CON(34)); + sel = FIELD_GET(CLK_SPI0_SEL_MASK, con); + div = FIELD_GET(CLK_SPI0_DIV_MASK, con); + break; + case CLK_SPI1: + con = readl(RK3506_CLKSEL_CON(34)); + sel = FIELD_GET(CLK_SPI1_SEL_MASK, con); + div = FIELD_GET(CLK_SPI1_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + if (sel == CLK_SPI_SEL_24M) + prate = OSC_HZ; + else if (sel == CLK_SPI_SEL_GPLL_DIV) + prate = priv->gpll_div_hz; + else if (sel == CLK_SPI_SEL_V0PLL_DIV) + prate = priv->v0pll_div_hz; + else if (sel == CLK_SPI_SEL_V1PLL_DIV) + prate = priv->v1pll_div_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_spi_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div, sel; + + if (OSC_HZ % rate == 0) { + sel = CLK_SPI_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_div_hz % rate == 0) { + sel = CLK_SPI_SEL_V0PLL_DIV; + div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); + } else if (priv->v1pll_div_hz % rate == 0) { + sel = CLK_SPI_SEL_V1PLL_DIV; + div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); + } else { + sel = CLK_SPI_SEL_GPLL_DIV; + div = DIV_ROUND_UP(priv->gpll_div_hz, rate); + } + assert(div - 1 <= 15); + + switch (clk_id) { + case CLK_SPI0: + rk_clrsetreg(RK3506_CLKSEL_CON(34), + CLK_SPI0_SEL_MASK | CLK_SPI0_DIV_MASK, + FIELD_PREP(CLK_SPI0_SEL_MASK, sel) | + FIELD_PREP(CLK_SPI0_DIV_MASK, div - 1)); + break; + case CLK_SPI1: + rk_clrsetreg(RK3506_CLKSEL_CON(34), + CLK_SPI1_SEL_MASK | CLK_SPI1_DIV_MASK, + FIELD_PREP(CLK_SPI1_SEL_MASK, sel) | + FIELD_PREP(CLK_SPI1_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_spi_get_rate(priv, clk_id); +} + +static ulong rk3506_fspi_get_rate(struct rk3506_clk_priv *priv) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(50)); + sel = FIELD_GET(SCLK_FSPI_SEL_MASK, con); + div = FIELD_GET(SCLK_FSPI_DIV_MASK, con); + + if (sel == SCLK_FSPI_SEL_24M) + prate = OSC_HZ; + else if (sel == SCLK_FSPI_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == SCLK_FSPI_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == SCLK_FSPI_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_fspi_set_rate(struct rk3506_clk_priv *priv, ulong rate) +{ + int div, sel; + + if (OSC_HZ % rate == 0) { + sel = SCLK_FSPI_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_hz % rate == 0) { + sel = SCLK_FSPI_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = SCLK_FSPI_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = SCLK_FSPI_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 31); + + rk_clrsetreg(RK3506_CLKSEL_CON(50), + SCLK_FSPI_SEL_MASK | SCLK_FSPI_DIV_MASK, + FIELD_PREP(SCLK_FSPI_SEL_MASK, sel) | + FIELD_PREP(SCLK_FSPI_DIV_MASK, div - 1)); + + return rk3506_fspi_get_rate(priv); +} + +static ulong rk3506_vop_dclk_get_rate(struct rk3506_clk_priv *priv) +{ + u32 con, div, sel; + ulong prate; + + con = readl(RK3506_CLKSEL_CON(60)); + sel = FIELD_GET(DCLK_VOP_SEL_MASK, con); + div = FIELD_GET(DCLK_VOP_DIV_MASK, con); + + if (sel == DCLK_VOP_SEL_24M) + prate = OSC_HZ; + else if (sel == DCLK_VOP_SEL_GPLL) + prate = priv->gpll_hz; + else if (sel == DCLK_VOP_SEL_V0PLL) + prate = priv->v0pll_hz; + else if (sel == DCLK_VOP_SEL_V1PLL) + prate = priv->v1pll_hz; + else + return -EINVAL; + + return DIV_TO_RATE(prate, div); +} + +static ulong rk3506_vop_dclk_set_rate(struct rk3506_clk_priv *priv, ulong rate) +{ + int div, sel; + + if (OSC_HZ % rate == 0) { + sel = DCLK_VOP_SEL_24M; + div = DIV_ROUND_UP(OSC_HZ, rate); + } else if (priv->v0pll_hz % rate == 0) { + sel = DCLK_VOP_SEL_V0PLL; + div = DIV_ROUND_UP(priv->v0pll_hz, rate); + } else if (priv->v1pll_hz % rate == 0) { + sel = DCLK_VOP_SEL_V1PLL; + div = DIV_ROUND_UP(priv->v1pll_hz, rate); + } else { + sel = DCLK_VOP_SEL_GPLL; + div = DIV_ROUND_UP(priv->gpll_hz, rate); + } + assert(div - 1 <= 255); + + rk_clrsetreg(RK3506_CLKSEL_CON(60), + DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK, + FIELD_PREP(DCLK_VOP_SEL_MASK, sel) | + FIELD_PREP(DCLK_VOP_DIV_MASK, div - 1)); + + return rk3506_vop_dclk_get_rate(priv); +} + +static ulong rk3506_mac_get_rate(struct rk3506_clk_priv *priv, ulong clk_id) +{ + u32 con, div; + + switch (clk_id) { + case CLK_MAC0: + case CLK_MAC1: + con = readl(RK3506_CLKSEL_CON(50)); + div = FIELD_GET(CLK_MAC_DIV_MASK, con); + break; + case CLK_MAC_OUT: + con = readl(RK3506_PMU_CLKSEL_CON(0)); + div = FIELD_GET(CLK_MAC_OUT_DIV_MASK, con); + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rk3506_mac_set_rate(struct rk3506_clk_priv *priv, ulong clk_id, + ulong rate) +{ + u32 div; + + switch (clk_id) { + case CLK_MAC0: + case CLK_MAC1: + div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(RK3506_CLKSEL_CON(50), CLK_MAC_DIV_MASK, + FIELD_PREP(CLK_MAC_DIV_MASK, div - 1)); + break; + case CLK_MAC_OUT: + div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(RK3506_PMU_CLKSEL_CON(0), CLK_MAC_OUT_DIV_MASK, + FIELD_PREP(CLK_MAC_OUT_DIV_MASK, div - 1)); + break; + default: + return -ENOENT; + } + + return rk3506_mac_get_rate(priv, clk_id); +} + +static ulong rk3506_clk_get_rate(struct clk *clk) +{ + struct rk3506_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz || !priv->v0pll_hz || !priv->v1pll_hz) { + log_debug("gpll=%lu, v0pll=%lu, v1pll=%lu\n", + priv->gpll_hz, priv->v0pll_hz, priv->v1pll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_GPLL: + rate = priv->gpll_hz; + break; + case PLL_V0PLL: + rate = priv->v0pll_hz; + break; + case PLL_V1PLL: + rate = priv->v1pll_hz; + break; + case ARMCLK: + rate = rk3506_armclk_get_rate(priv); + break; + case CLK_GPLL_DIV: + case CLK_GPLL_DIV_100M: + case CLK_V0PLL_DIV: + case CLK_V1PLL_DIV: + rate = rk3506_pll_div_get_rate(priv, clk->id); + break; + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + case PCLK_BUS_ROOT: + rate = rk3506_bus_get_rate(priv, clk->id); + break; + case ACLK_HSPERI_ROOT: + case HCLK_LSPERI_ROOT: + rate = rk3506_peri_get_rate(priv, clk->id); + break; + case HCLK_SDMMC: + case CCLK_SRC_SDMMC: + rate = rk3506_sdmmc_get_rate(priv, clk->id); + break; + case CLK_SARADC: + rate = rk3506_saradc_get_rate(priv, clk->id); + break; + case CLK_TSADC: + case CLK_TSADC_TSEN: + rate = rk3506_tsadc_get_rate(priv, clk->id); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + rate = rk3506_i2c_get_rate(priv, clk->id); + break; + case CLK_PWM0: + case CLK_PWM1: + rate = rk3506_pwm_get_rate(priv, clk->id); + break; + case CLK_SPI0: + case CLK_SPI1: + rate = rk3506_spi_get_rate(priv, clk->id); + break; + case SCLK_FSPI: + rate = rk3506_fspi_get_rate(priv); + break; + case DCLK_VOP: + rate = rk3506_vop_dclk_get_rate(priv); + break; + case CLK_MAC0: + case CLK_MAC1: + case CLK_MAC_OUT: + rate = rk3506_mac_get_rate(priv, clk->id); + break; + default: + log_debug("unsupported clk id=%ld\n", clk->id); + return -ENOENT; + } + + return rate; +}; + +static ulong rk3506_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3506_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz || !priv->v0pll_hz || !priv->v1pll_hz) { + log_debug("gpll=%lu, v0pll=%lu, v1pll=%lu\n", + priv->gpll_hz, priv->v0pll_hz, priv->v1pll_hz); + return -ENOENT; + } + + switch (clk->id) { + case ARMCLK: + ret = rk3506_armclk_set_rate(priv, rate); + break; + case CLK_GPLL_DIV: + case CLK_GPLL_DIV_100M: + case CLK_V0PLL_DIV: + case CLK_V1PLL_DIV: + ret = rk3506_pll_div_set_rate(priv, clk->id, rate); + break; + case ACLK_BUS_ROOT: + case HCLK_BUS_ROOT: + case PCLK_BUS_ROOT: + ret = rk3506_bus_set_rate(priv, clk->id, rate); + break; + case ACLK_HSPERI_ROOT: + case HCLK_LSPERI_ROOT: + ret = rk3506_peri_set_rate(priv, clk->id, rate); + break; + case HCLK_SDMMC: + case CCLK_SRC_SDMMC: + ret = rk3506_sdmmc_set_rate(priv, clk->id, rate); + break; + case CLK_SARADC: + ret = rk3506_saradc_set_rate(priv, clk->id, rate); + break; + case CLK_TSADC: + case CLK_TSADC_TSEN: + ret = rk3506_tsadc_set_rate(priv, clk->id, rate); + break; + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + ret = rk3506_i2c_set_rate(priv, clk->id, rate); + break; + case CLK_PWM0: + case CLK_PWM1: + ret = rk3506_pwm_set_rate(priv, clk->id, rate); + break; + case CLK_SPI0: + case CLK_SPI1: + ret = rk3506_spi_set_rate(priv, clk->id, rate); + break; + case SCLK_FSPI: + ret = rk3506_fspi_set_rate(priv, rate); + break; + case DCLK_VOP: + ret = rk3506_vop_dclk_set_rate(priv, rate); + break; + case CLK_MAC0: + case CLK_MAC1: + case CLK_MAC_OUT: + ret = rk3506_mac_set_rate(priv, clk->id, rate); + break; + default: + log_debug("unsupported clk id=%ld rate=%ld\n", clk->id, rate); + return -ENOENT; + } + + return ret; +}; + +static struct clk_ops rk3506_clk_ops = { + .get_rate = rk3506_clk_get_rate, + .set_rate = rk3506_clk_set_rate, +}; + +static void rk3506_clk_init(struct rk3506_clk_priv *priv) +{ + static void * const cru_base = (void *)RK3506_CRU_BASE; + + if (!priv->gpll_hz) { + priv->gpll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[GPLL], + cru_base, GPLL); + priv->gpll_hz = roundup(priv->gpll_hz, 1000); + } + if (!priv->v0pll_hz) { + priv->v0pll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[V0PLL], + cru_base, V0PLL); + priv->v0pll_hz = roundup(priv->v0pll_hz, 1000); + } + if (!priv->v1pll_hz) { + priv->v1pll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[V1PLL], + cru_base, V1PLL); + priv->v1pll_hz = roundup(priv->v1pll_hz, 1000); + } + if (!priv->gpll_div_hz) { + priv->gpll_div_hz = rk3506_pll_div_get_rate(priv, CLK_GPLL_DIV); + priv->gpll_div_hz = roundup(priv->gpll_div_hz, 1000); + } + if (!priv->gpll_div_100mhz) { + priv->gpll_div_100mhz = rk3506_pll_div_get_rate(priv, + CLK_GPLL_DIV_100M); + priv->gpll_div_100mhz = roundup(priv->gpll_div_100mhz, 1000); + } + if (!priv->v0pll_div_hz) { + priv->v0pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V0PLL_DIV); + priv->v0pll_div_hz = roundup(priv->v0pll_div_hz, 1000); + } + if (!priv->v1pll_div_hz) { + priv->v1pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V1PLL_DIV); + priv->v1pll_div_hz = roundup(priv->v1pll_div_hz, 1000); + } +} + +static void rk3506_clk_init_xpl(void) +{ + /* Init pka crypto rate, sel=v0pll, div=3 */ + rk_clrsetreg(RK3506_SCRU_BASE + 0x0010, + CLK_PKA_CRYPTO_SEL_MASK | CLK_PKA_CRYPTO_DIV_MASK, + FIELD_PREP(CLK_PKA_CRYPTO_SEL_MASK, CLK_PKA_CRYPTO_SEL_V0PLL) | + FIELD_PREP(CLK_PKA_CRYPTO_DIV_MASK, 3)); + + /* Change clk core src rate, sel=gpll, div=3 */ + rk_clrsetreg(RK3506_CLKSEL_CON(15), + CLK_CORE_SRC_SEL_MASK | CLK_CORE_SRC_DIV_MASK, + FIELD_PREP(CLK_CORE_SRC_SEL_MASK, CLK_CORE_SEL_GPLL) | + FIELD_PREP(CLK_CORE_SRC_DIV_MASK, 3)); +} + +static int rk3506_clk_probe(struct udevice *dev) +{ + struct rk3506_clk_priv *priv = dev_get_priv(dev); + int ret; + + rk3506_clk_init(priv); + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev, 1); + if (ret) + log_debug("clk_set_defaults failed: ret=%d\n", ret); + + return 0; +} + +static int rk3506_clk_bind(struct udevice *dev) +{ + struct udevice *sys_child; + struct sysreset_reg *priv; + int ret; + + if (IS_ENABLED(CONFIG_XPL_BUILD)) + rk3506_clk_init_xpl(); + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + log_debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = RK3506_GLB_SRST_FST; + priv->glb_srst_snd_value = RK3506_GLB_SRST_SND; + dev_set_priv(sys_child, priv); + } + + if (!CONFIG_IS_ENABLED(RESET_ROCKCHIP)) + return 0; + + ret = rk3506_reset_bind_lut(dev, RK3506_SOFTRST_CON0, 23); + if (ret) + log_debug("Warning: software reset driver bind failed\n"); + + return 0; +} + +static const struct udevice_id rk3506_clk_ids[] = { + { .compatible = "rockchip,rk3506-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_cru) = { + .name = "rockchip_rk3506_cru", + .id = UCLASS_CLK, + .of_match = rk3506_clk_ids, + .priv_auto = sizeof(struct rk3506_clk_priv), + .ops = &rk3506_clk_ops, + .bind = rk3506_clk_bind, + .probe = rk3506_clk_probe, +}; diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index d58557ff56d..bcdc0f930d2 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) /* diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 533031caead..bb49af358e6 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -16,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3568_clk_plat { struct dtd_rockchip_rk3568_cru dtd; diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index 125b08ee832..1026af27ca1 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) static struct rockchip_pll_rate_table rk3576_24m_pll_rates[] = { diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 8c3a113526f..be401a9faee 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) static struct rockchip_pll_rate_table rk3588_pll_rates[] = { diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 75202a66aa6..e1b9ccf1236 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 2400U * 1000000, VCO_MIN_HZ = 600 * 1000000, diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index aeeea956914..39920d34b75 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -18,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ { \ .rate = _rate##U, \ diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index e55a26ab8fd..5d0b08d3755 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -59,25 +59,25 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { /* List of clock controls provided by the PRCI */ static struct __prci_clock __prci_init_clocks_fu540[] = { - [PRCI_CLK_COREPLL] = { + [FU540_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU540_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU540_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU540_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu540_prci_tlclksel_clk_ops, diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index c9253099e6e..5419bf65b5d 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -195,7 +195,7 @@ config DM_DMA the physical address space. config REGMAP - bool "Support register maps" + bool depends on DM select DEVRES help @@ -206,7 +206,7 @@ config REGMAP direct memory access. config SPL_REGMAP - bool "Support register maps in SPL" + bool depends on SPL_DM help Hardware peripherals tend to have one or more sets of registers @@ -216,7 +216,7 @@ config SPL_REGMAP direct memory access. config TPL_REGMAP - bool "Support register maps in TPL" + bool depends on TPL_DM help Hardware peripherals tend to have one or more sets of registers @@ -226,7 +226,7 @@ config TPL_REGMAP direct memory access. config VPL_REGMAP - bool "Support register maps in VPL" + bool depends on VPL_DM help Hardware peripherals tend to have one or more sets of registers @@ -237,7 +237,7 @@ config VPL_REGMAP config SYSCON bool "Support system controllers" - depends on REGMAP + select REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided @@ -246,7 +246,8 @@ config SYSCON config SPL_SYSCON bool "Support system controllers in SPL" - depends on SPL_REGMAP + depends on SPL_DM + select SPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided @@ -255,7 +256,8 @@ config SPL_SYSCON config TPL_SYSCON bool "Support system controllers in TPL" - depends on TPL_REGMAP + depends on TPL_DM + select TPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided @@ -264,7 +266,8 @@ config TPL_SYSCON config VPL_SYSCON bool "Support system controllers in VPL" - depends on VPL_REGMAP + depends on VPL_DM + select VPL_REGMAP help Many SoCs have a number of system controllers which are dealt with as a group by a single driver. Some common functionality is provided diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index 437080ed778..557afb8d817 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -198,7 +198,7 @@ static int flags_remove(uint flags, uint drv_flags) int device_remove(struct udevice *dev, uint flags) { const struct driver *drv; - int ret; + int ret, cret; if (!dev) return -EINVAL; @@ -210,25 +210,35 @@ int device_remove(struct udevice *dev, uint flags) if (ret) return ret; - /* - * If the child returns EKEYREJECTED, continue. It just means that it - * didn't match the flags. - */ - ret = device_chld_remove(dev, NULL, flags); - if (ret && ret != -EKEYREJECTED) - return ret; - /* * Remove the device if called with the "normal" remove flag set, * or if the remove flag matches any of the drivers remove flags */ drv = dev->driver; assert(drv); - ret = flags_remove(flags, drv->flags); - if (ret) { - log_debug("%s: When removing: flags=%x, drv->flags=%x, err=%d\n", - dev->name, flags, drv->flags, ret); + cret = flags_remove(flags, drv->flags); + + /* + * Remove all children. If this device is being removed due to + * active-DMA or OS-prepare flags, drop the active-flag requirement + * for children so they are removed even without matching active + * flags, since a deactivated device must not have activated + * children. Preserve other flags (e.g. DM_REMOVE_NON_VITAL) so + * that vital children are still protected. + * + * If the child returns EKEYREJECTED, continue. It just means that it + * didn't match the flags. + */ + ret = device_chld_remove(dev, NULL, + cret ? flags : + (flags & ~DM_REMOVE_ACTIVE_ALL)); + if (ret && ret != -EKEYREJECTED) return ret; + + if (cret) { + log_debug("%s: When removing: flags=%x, drv->flags=%x, err=%d\n", + dev->name, flags, drv->flags, cret); + return cret; } ret = uclass_pre_remove_device(dev); diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 6a96be94de4..c805c0bbfa1 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -35,9 +35,8 @@ config CPU_ARMV8 config CPU_MICROBLAZE bool "Enable Microblaze CPU driver" - depends on CPU && MICROBLAZE + depends on CPU && MICROBLAZE && XILINX_MICROBLAZE0_PVR select DM_EVENT - select XILINX_MICROBLAZE0_PVR help Support CPU cores for Microblaze architecture. diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c index 59a7b142c95..ad638cd8fff 100644 --- a/drivers/cpu/bcm283x_cpu.c +++ b/drivers/cpu/bcm283x_cpu.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include "armv8_cpu.h" -DECLARE_GLOBAL_DATA_PTR; - struct bcm_plat { u64 release_addr; }; diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 2c8e46c05e3..b73768de918 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -15,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int cpu_probe_all(void) { int ret = uclass_probe_all(UCLASS_CPU); diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 5f17122c36c..785c299eca5 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define IMX_REV_LEN 4 struct cpu_imx_plat { const char *name; @@ -115,6 +112,8 @@ static const char *get_imx_type_str(u32 imxtype) return "95"; case MXC_CPU_IMX94: return "94"; + case MXC_CPU_IMX952: + return "952"; default: return "??"; } diff --git a/drivers/cpu/mtk_cpu.c b/drivers/cpu/mtk_cpu.c index 2a08be9b6d1..4f4e5480eac 100644 --- a/drivers/cpu/mtk_cpu.c +++ b/drivers/cpu/mtk_cpu.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct mtk_cpu_plat { struct regmap *hwver; }; diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index fe694f6022c..eb01c6cf700 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -3,6 +3,7 @@ if ARM || PPC config FSL_CAAM bool "Freescale Crypto Driver Support" select SHA_HW_ACCEL + select ARCH_MISC_INIT # hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL select MISC if DM imply SPL_CRYPTO if (ARM && SPL) diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 4660d20deff..615e0421abf 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64 - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 || ARCH_SOCFPGA_SOC64 + select RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 + select SPL_RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 7ed43965be5..8259ab04a7e 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -7,11 +7,11 @@ # Copyright (C) 2014-2025 Altera Corporation ifdef CONFIG_$(PHASE_)ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += sdram_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index 2a2f86a650e..3156cb9d4b6 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -86,7 +86,7 @@ #define INTF_DDR_TYPE_MASK GENMASK(2, 0) /* offset info of MEM_TOTAL_CAPACITY_INTF */ -#define INTF_CAPACITY_GBITS_MASK GENMASK(7, 0) +#define INTF_CAPACITY_GBITS_MASK GENMASK(31, 0) /* offset info of ECC_ENABLE_INTF */ #define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index d3305a6c82d..c281f711fdf 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -667,6 +668,22 @@ static int of_sdram_firewall_setup(const void *blob) return 0; } +static void sdram_size_check(void) +{ + phys_size_t ram_check = 0; + + debug("DDR: Running SDRAM size sanity check\n"); + + ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, + gd->bd->bi_dram[0].size); + if (ram_check != gd->bd->bi_dram[0].size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + + debug("DDR: SDRAM size check passed!\n"); +} + int ddr_calibration_sequence(void) { schedule(); @@ -702,11 +719,26 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); + if (gd->ram_size != gd->bd->bi_dram[0].size) { + printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", + gd->bd->bi_dram[0].size >> 20); + printf(" mismatch with hardware (%ld MiB).\n", + gd->ram_size >> 20); + } + + if (gd->bd->bi_dram[0].size > gd->ram_size) { + printf("DDR: Error: DRAM size from device tree is greater\n"); + printf(" than hardware size.\n"); + hang(); + } + if (of_sdram_firewall_setup(gd->fdt_blob)) puts("FW: Error Configuring Firewall\n"); if (sdram_is_ecc_enabled()) sdram_init_ecc_bits(gd->ram_size); + sdram_size_check(); + return 0; } diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 2d0093c591c..8ee7049b164 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -32,7 +32,7 @@ #define SINGLE_RANK_CLAMSHELL 0xc3c3 #define DUAL_RANK_CLAMSHELL 0xa5a5 -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -106,7 +106,7 @@ int emif_reset(struct altera_sdram_plat *plat) } #endif -#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) +#if !(IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + @@ -347,7 +347,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) } } -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) static void sdram_set_firewall_f2sdram(struct bd_info *bd) { u32 i, lower, upper; @@ -397,22 +397,22 @@ void sdram_set_firewall(struct bd_info *bd) { sdram_set_firewall_non_f2sdram(bd); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) sdram_set_firewall_f2sdram(bd); #endif } static int altera_sdram_of_to_plat(struct udevice *dev) { -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) struct altera_sdram_plat *plat = dev_get_plat(dev); fdt_addr_t addr; #endif /* These regs info are part of DDR handoff in bitstream */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) return 0; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6fe0653922c..e8090f91002 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -15,13 +15,13 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) struct altera_sdram_plat { fdt_addr_t mpfe_base_addr; bool dualport; bool dualemif; }; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) enum memory_type { DDR_MEMORY = 0, HBM_MEMORY diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 2cf4289b448..962bda40ad2 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -13,10 +13,10 @@ config DFU_OVER_TFTP bool depends on NET -if DFU config DFU_WRITE_ALT bool +if DFU config DFU_TFTP bool "DFU via TFTP" depends on NETDEVICES diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index 5cec6ddd3e3..d904982c800 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -8,7 +8,6 @@ config TI_K3_NAVSS_UDMA select DEVRES select DMA select TI_K3_NAVSS_RINGACC - select TI_K3_NAVSS_PSILCFG select TI_K3_PSIL help Support for UDMA used in K3 devices. diff --git a/drivers/fastboot/fb_block.c b/drivers/fastboot/fb_block.c index 2a7e47992f8..51d1abb18c7 100644 --- a/drivers/fastboot/fb_block.c +++ b/drivers/fastboot/fb_block.c @@ -28,6 +28,11 @@ */ #define FASTBOOT_MAX_BLOCKS_WRITE 65536 +__weak lbaint_t fb_mmc_get_boot_offset(void) +{ + return 0; +} + struct fb_block_sparse { struct blk_desc *dev_desc; }; @@ -160,7 +165,8 @@ void fastboot_block_raw_erase_disk(struct blk_desc *dev_desc, const char *disk_n debug("Start Erasing %s...\n", disk_name); - written = fb_block_write(dev_desc, 0, dev_desc->lba, NULL); + written = fb_block_write(dev_desc, fb_mmc_get_boot_offset(), + dev_desc->lba, NULL); if (written != dev_desc->lba) { pr_err("Failed to erase %s\n", disk_name); fastboot_response("FAIL", response, "Failed to erase %s", disk_name); @@ -211,7 +217,8 @@ void fastboot_block_erase(const char *part_name, char *response) if (fastboot_block_get_part_info(part_name, &dev_desc, &part_info, response) < 0) return; - fastboot_block_raw_erase(dev_desc, &part_info, part_name, 0, response); + fastboot_block_raw_erase(dev_desc, &part_info, part_name, + fb_mmc_get_boot_offset(), response); } void fastboot_block_write_raw_disk(struct blk_desc *dev_desc, const char *disk_name, @@ -224,7 +231,7 @@ void fastboot_block_write_raw_disk(struct blk_desc *dev_desc, const char *disk_n blkcnt = ((download_bytes + (dev_desc->blksz - 1)) & ~(dev_desc->blksz - 1)); blkcnt = lldiv(blkcnt, dev_desc->blksz); - if (blkcnt > dev_desc->lba) { + if ((blkcnt + fb_mmc_get_boot_offset()) > dev_desc->lba) { pr_err("too large for disk: '%s'\n", disk_name); fastboot_fail("too large for disk", response); return; @@ -232,7 +239,7 @@ void fastboot_block_write_raw_disk(struct blk_desc *dev_desc, const char *disk_n printf("Flashing Raw Image\n"); - blks = fb_block_write(dev_desc, 0, blkcnt, buffer); + blks = fb_block_write(dev_desc, fb_mmc_get_boot_offset(), blkcnt, buffer); if (blks != blkcnt) { pr_err("failed writing to %s\n", disk_name); diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index 96c64964bb7..76a8775e911 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -12,15 +12,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Error mapping declarations */ int ffa_to_std_errmap[MAX_NUMBER_FFA_ERR] = { diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c index 94e6105cb38..9e6b5dcc542 100644 --- a/drivers/firmware/arm-ffa/arm-ffa.c +++ b/drivers/firmware/arm-ffa/arm-ffa.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /** * invoke_ffa_fn() - SMC wrapper * @args: FF-A ABI arguments to be copied to Xn registers diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c index 1521d9b66ac..6198d687354 100644 --- a/drivers/firmware/arm-ffa/ffa-emul-uclass.c +++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -17,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* The partitions (SPs) table */ static struct ffa_partition_desc sandbox_partitions[SANDBOX_PARTITIONS_CNT] = { { diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c index 44b32a829dd..f1e8de4bf0d 100644 --- a/drivers/firmware/arm-ffa/sandbox_ffa.c +++ b/drivers/firmware/arm-ffa/sandbox_ffa.c @@ -8,13 +8,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /** * sandbox_ffa_discover() - perform sandbox FF-A discovery * @dev: The sandbox FF-A bus device diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index f8a9945c1da..fb583580ebe 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -427,6 +427,104 @@ U_BOOT_DRIVER(zynqmp_power) = { }; #endif +static const char *const pinctrl_functions[] = { + "can0", + "can1", + "ethernet0", + "ethernet1", + "ethernet2", + "ethernet3", + "gemtsu0", + "gpio0", + "i2c0", + "i2c1", + "mdio0", + "mdio1", + "mdio2", + "mdio3", + "qspi0", + "qspi_fbclk", + "qspi_ss", + "spi0", + "spi1", + "spi0_ss", + "spi1_ss", + "sdio0", + "sdio0_pc", + "sdio0_cd", + "sdio0_wp", + "sdio1", + "sdio1_pc", + "sdio1_cd", + "sdio1_wp", + "nand0", + "nand0_ce", + "nand0_rb", + "nand0_dqs", + "ttc0_clk", + "ttc0_wav", + "ttc1_clk", + "ttc1_wav", + "ttc2_clk", + "ttc2_wav", + "ttc3_clk", + "ttc3_wav", + "uart0", + "uart1", + "usb0", + "usb1", + "swdt0_clk", + "swdt0_rst", + "swdt1_clk", + "swdt1_rst", + "pmu0", + "pcie0", + "csu0", + "dpaux0", + "pjtag0", + "trace0", + "trace0_clk", + "testscan0", +}; + +/* + * PM_QUERY_DATA is implemented by ATF and not the PMU firmware, so we have to + * emulate it in SPL. Just implement functions/pins since the groups take up a + * lot of rodata and are mostly superfluous. + */ +static int zynqmp_pm_query_data(enum pm_query_id qid, u32 arg1, u32 arg2, + u32 *ret_payload) +{ + switch (qid) { + case PM_QID_PINCTRL_GET_NUM_PINS: + ret_payload[1] = 78; /* NUM_PINS */ + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_NUM_FUNCTIONS: + ret_payload[1] = ARRAY_SIZE(pinctrl_functions); + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS: + ret_payload[1] = 0; + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_FUNCTION_NAME: + assert(arg1 < ARRAY_SIZE(pinctrl_functions)); + memset(ret_payload, 0, MAX_FUNC_NAME_LEN); + strcpy((char *)ret_payload, pinctrl_functions[arg1]); + return 0; + case PM_QID_PINCTRL_GET_FUNCTION_GROUPS: + case PM_QID_PINCTRL_GET_PIN_GROUPS: + memset(ret_payload + 1, 0xff, + sizeof(s16) * NUM_GROUPS_PER_RESP); + ret_payload[0] = 0; + return 0; + default: + ret_payload[0] = 1; + return 1; + } +} + smc_call_handler_t __data smc_call_handler; static int smc_call_legacy(u32 api_id, u32 arg0, u32 arg1, u32 arg2, @@ -493,6 +591,9 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, __func__, current_el(), api_id, arg0, arg1, arg2, arg3, arg4, arg5); if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { + if (CONFIG_IS_ENABLED(PINCTRL_ZYNQMP) && + api_id == PM_QUERY_DATA) + return zynqmp_pm_query_data(arg0, arg1, arg2, ret_payload); #if defined(CONFIG_ZYNQMP_IPI) /* * Use fixed payload and arg size as the EL2 call. The firmware diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig index 33e089c460b..cd912ebe409 100644 --- a/drivers/firmware/scmi/Kconfig +++ b/drivers/firmware/scmi/Kconfig @@ -3,6 +3,7 @@ config SCMI_FIRMWARE select FIRMWARE select OF_TRANSLATE depends on SANDBOX || DM_MAILBOX || ARM_SMCCC || OPTEE + depends on OF_CONTROL help System Control and Management Interface (SCMI) is a communication protocol that defines standard interfaces for power, performance diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile index 6129726f817..761d89a1161 100644 --- a/drivers/firmware/scmi/Makefile +++ b/drivers/firmware/scmi/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_SCMI_AGENT_SMCCC) += smccc_agent.o obj-$(CONFIG_SCMI_AGENT_MAILBOX) += mailbox_agent.o obj-$(CONFIG_SCMI_AGENT_OPTEE) += optee_agent.o obj-$(CONFIG_SCMI_POWER_DOMAIN) += pwdom.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl.o obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o obj-y += vendors/imx/ diff --git a/drivers/firmware/scmi/pinctrl.c b/drivers/firmware/scmi/pinctrl.c new file mode 100644 index 00000000000..47f7a8ad9b8 --- /dev/null +++ b/drivers/firmware/scmi/pinctrl.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Linaro Ltd. + */ + +#define LOG_CATEGORY UCLASS_PINCTRL + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int map_config_param_to_scmi(u32 config_param) +{ + switch (config_param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + return SCMI_PIN_BIAS_BUS_HOLD; + case PIN_CONFIG_BIAS_DISABLE: + return SCMI_PIN_BIAS_DISABLE; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + return SCMI_PIN_BIAS_HIGH_IMPEDANCE; + case PIN_CONFIG_BIAS_PULL_DOWN: + return SCMI_PIN_BIAS_PULL_DOWN; + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + return SCMI_PIN_BIAS_PULL_DEFAULT; + case PIN_CONFIG_BIAS_PULL_UP: + return SCMI_PIN_BIAS_PULL_UP; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + return SCMI_PIN_DRIVE_OPEN_DRAIN; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + return SCMI_PIN_DRIVE_OPEN_SOURCE; + case PIN_CONFIG_DRIVE_PUSH_PULL: + return SCMI_PIN_DRIVE_PUSH_PULL; + case PIN_CONFIG_DRIVE_STRENGTH: + return SCMI_PIN_DRIVE_STRENGTH; + case PIN_CONFIG_INPUT_DEBOUNCE: + return SCMI_PIN_INPUT_DEBOUNCE; + case PIN_CONFIG_INPUT_ENABLE: + return SCMI_PIN_INPUT_MODE; + case PIN_CONFIG_INPUT_SCHMITT: + return SCMI_PIN_INPUT_SCHMITT; + case PIN_CONFIG_LOW_POWER_MODE: + return SCMI_PIN_LOW_POWER_MODE; + case PIN_CONFIG_OUTPUT_ENABLE: + return SCMI_PIN_OUTPUT_MODE; + case PIN_CONFIG_OUTPUT: + return SCMI_PIN_OUTPUT_VALUE; + case PIN_CONFIG_POWER_SOURCE: + return SCMI_PIN_POWER_SOURCE; + case PIN_CONFIG_SLEW_RATE: + return SCMI_PIN_SLEW_RATE; + } + + return -EINVAL; +} + +int scmi_pinctrl_protocol_attrs(struct udevice *dev, int *num_pins, + int *num_groups, int *num_functions) +{ + struct scmi_pinctrl_protocol_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PROTOCOL_ATTRIBUTES, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + if (num_groups) + *num_groups = FIELD_GET(GENMASK(31, 16), out.attr_low); + if (num_pins) + *num_pins = FIELD_GET(GENMASK(15, 0), out.attr_low); + if (num_functions) + *num_functions = FIELD_GET(GENMASK(15, 0), out.attr_high); + + return 0; +} + +int scmi_pinctrl_attrs(struct udevice *dev, enum select_type select_type, + unsigned int selector, bool *gpio, unsigned int *count, + char *name) +{ + struct scmi_pinctrl_attrs_in in; + struct scmi_pinctrl_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_ATTRIBUTES, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.select_type = select_type; + in.id = selector; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + if (gpio) + *gpio = FIELD_GET(BIT(17), out.attr); + if (count) + *count = FIELD_GET(GENMASK(15, 0), out.attr); + if (name) + strncpy(name, out.name, sizeof(out.name)); + + return 0; +} + +int scmi_pinctrl_list_associations(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + unsigned short *output, + unsigned short num_out) +{ + struct scmi_pinctrl_list_associations_in in; + struct scmi_pinctrl_list_associations_out *out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_LIST_ASSOCIATIONS, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + }; + size_t out_sz = sizeof(*out) + num_out * sizeof(out->array[0]); + unsigned int count; + int ret = -EINVAL; + + out = kzalloc(out_sz, GFP_KERNEL); + if (!out) + return -ENOMEM; + + msg.out_msg = (u8 *)out; + msg.out_msg_sz = out_sz; + in.select_type = select_type; + in.id = selector; + in.index = 0; + + while (num_out > 0) { + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out->status) { + ret = scmi_to_linux_errno(out->status); + goto free; + } + + count = FIELD_GET(GENMASK(11, 0), out->flags); + if (count > num_out) + return -EINVAL; + memcpy(&output[in.index], out->array, count * sizeof(u16)); + num_out -= count; + in.index += count; + } +free: + kfree(out); + return ret; +} + +#define SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION -2u + +int scmi_pinctrl_settings_get_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 config_type, u32 *value) +{ + struct scmi_pinctrl_settings_get_in in; + struct scmi_pinctrl_settings_get_out *out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_SETTINGS_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + }; + size_t out_sz = sizeof(*out) + (sizeof(u32) * 2); + u32 num_configs; + int ret; + + if (config_type == SCMI_PINCTRL_CONFIG_SETTINGS_ALL) { + /* FIXME: implement */ + return -EIO; + } + + out = kzalloc(out_sz, GFP_KERNEL); + if (!out) + return -ENOMEM; + + msg.out_msg = (u8 *)out; + msg.out_msg_sz = out_sz; + in.id = selector; + in.attr = 0; + if (config_type == SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION) + in.attr = FIELD_PREP(GENMASK(19, 18), 2); + in.attr |= FIELD_PREP(GENMASK(17, 16), select_type); + if (config_type != SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION) + in.attr |= FIELD_PREP(GENMASK(7, 0), config_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out->status) { + ret = scmi_to_linux_errno(out->status); + goto free; + } + num_configs = FIELD_GET(GENMASK(7, 0), out->num_configs); + if (out->num_configs == 0) { + *value = out->function_selected; + goto free; + } + if (num_configs != 1) { + ret = -EINVAL; + goto free; + } + + *value = out->configs[1]; +free: + kfree(out); + return ret; +} + +static int scmi_pinctrl_settings_configure_helper(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + u32 function_id, + u16 num_configs, u32 *configs) +{ + struct scmi_pinctrl_settings_configure_in *in; + struct scmi_pinctrl_settings_configure_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_SETTINGS_CONFIGURE, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + size_t in_sz = sizeof(*in) + (num_configs * sizeof(u32) * 2); + int ret; + + in = kzalloc(in_sz, GFP_KERNEL); + if (!in) + return -ENOMEM; + + msg.in_msg = (u8 *)in; + msg.in_msg_sz = in_sz; + in->id = selector; + in->function_id = function_id; + in->attr = 0; + in->attr |= FIELD_PREP(GENMASK(9, 2), num_configs); + in->attr |= FIELD_PREP(GENMASK(1, 0), select_type); + memcpy(in->configs, configs, num_configs * sizeof(u32) * 2); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out.status) { + ret = scmi_to_linux_errno(out.status); + goto free; + } +free: + kfree(in); + return ret; +} + +int scmi_pinctrl_settings_configure(struct udevice *dev, enum select_type select_type, + unsigned int selector, u16 num_configs, + u32 *configs) +{ + return scmi_pinctrl_settings_configure_helper(dev, select_type, + selector, + SCMI_PINCTRL_FUNCTION_NONE, + num_configs, configs); +} + +int scmi_pinctrl_settings_configure_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 param, u32 argument) +{ + u32 config_value[2]; + int scmi_config; + + /* see stmfx_pinctrl_conf_set() */ + scmi_config = map_config_param_to_scmi(param); + if (scmi_config < 0) + return scmi_config; + + config_value[0] = scmi_config; + config_value[1] = argument; + + return scmi_pinctrl_settings_configure(dev, select_type, selector, 1, + &config_value[0]); +} + +int scmi_pinctrl_set_function(struct udevice *dev, enum select_type select_type, + unsigned int selector, u32 function_id) +{ + return scmi_pinctrl_settings_configure_helper(dev, select_type, selector, + function_id, 0, NULL); +} + +int scmi_pinctrl_request(struct udevice *dev, enum select_type select_type, + unsigned int selector) +{ + struct scmi_pinctrl_request_in in; + struct scmi_pinctrl_request_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_REQUEST, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.id = selector; + in.flags = FIELD_PREP(GENMASK(1, 0), select_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + return 0; +} + +int scmi_pinctrl_release(struct udevice *dev, enum select_type select_type, + unsigned int selector) +{ + struct scmi_pinctrl_release_in in; + struct scmi_pinctrl_release_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_RELEASE, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.id = selector; + in.flags = FIELD_PREP(GENMASK(1, 0), select_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + return 0; +} + diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index ad825d66da2..cd458a7f458 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -106,7 +106,7 @@ struct udevice *scmi_get_protocol(struct udevice *dev, proto = priv->voltagedom_dev; break; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) case SCMI_PROTOCOL_ID_PINCTRL: proto = priv->pinctrl_dev; break; @@ -179,7 +179,7 @@ static int scmi_add_protocol(struct udevice *dev, priv->voltagedom_dev = proto; break; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) case SCMI_PROTOCOL_ID_PINCTRL: priv->pinctrl_dev = proto; break; diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index e2593057fac..1658c73bca4 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -46,7 +46,7 @@ config FPGA_CYCLON2 config FPGA_INTEL_SDM_MAILBOX bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" - depends on TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_SOC64 select FPGA_ALTERA help Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index f22d3b3d86e..ccfed94717e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -21,6 +21,6 @@ obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += socfpga_arria10.o endif diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 4a9aa74357e..822183c5785 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,8 +12,8 @@ /* * Altera FPGA support */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #include #endif #include @@ -48,8 +48,8 @@ static const struct altera_fpga { #endif }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) int fpga_is_partial_data(int devnum, size_t img_len) { /* diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig index 42736a5e43b..59571ac01ea 100644 --- a/drivers/fwu-mdata/Kconfig +++ b/drivers/fwu-mdata/Kconfig @@ -1,4 +1,4 @@ -config FWU_MDATA +menuconfig FWU_MDATA bool "Driver support for accessing FWU Metadata" depends on DM help @@ -6,16 +6,14 @@ config FWU_MDATA FWU Metadata partitions reside on the same storage device which contains the other FWU updatable firmware images. -choice - prompt "Storage Layout Scheme" - depends on FWU_MDATA - default FWU_MDATA_GPT_BLK +if FWU_MDATA config FWU_MDATA_GPT_BLK bool "FWU Metadata access for GPT partitioned Block devices" select PARTITION_TYPE_GUID select PARTITION_UUIDS - depends on FWU_MDATA && BLK && EFI_PARTITION + depends on BLK && EFI_PARTITION + default y help Enable support for accessing FWU Metadata on GPT partitioned block devices. @@ -28,4 +26,4 @@ config FWU_MDATA_MTD (or non-GPT partitioned, e.g. partition nodes in devicetree) MTD devices. -endchoice +endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 60c5c54688e..1484dd3504c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1,3 +1,11 @@ +config GPIO_DELAY + bool "GPIO delay driver" + depends on DM_GPIO + help + Enable the GPIO delay driver. + This driver allows wrapping another GPIO controller and inserting + ramp-up/ramp-down delays on output changes, as described in the + Linux gpio-delay binding. # # GPIO infrastructure and drivers # @@ -375,6 +383,7 @@ config OMAP_GPIO config CMD_PCA953X bool "Enable the pca953x command" + depends on PCA953X help Deprecated: This should be converted to driver model. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 910478c0c7a..fec258f59f5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o obj-$(CONFIG_CORTINA_GPIO) += cortina_gpio.o obj-$(CONFIG_FXL6408_GPIO) += gpio-fxl6408.o +obj-$(CONFIG_GPIO_DELAY) += gpio-delay.o obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o diff --git a/drivers/gpio/gpio-delay.c b/drivers/gpio/gpio-delay.c new file mode 100644 index 00000000000..9105deecc4f --- /dev/null +++ b/drivers/gpio/gpio-delay.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 - 2026, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include +#include + +struct gpio_delay_desc { + struct gpio_desc real_gpio; + u32 ramp_up_us; + u32 ramp_down_us; +}; + +struct gpio_delay_priv { + struct gpio_delay_desc *descs; +}; + +static int gpio_delay_direction_input(struct udevice *dev, unsigned int offset) +{ + return -ENOSYS; +} + +static int gpio_delay_get_value(struct udevice *dev, unsigned int offset) +{ + return -ENOSYS; +} + +static int gpio_delay_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct gpio_delay_priv *priv = dev_get_priv(dev); + struct gpio_delay_desc *desc = &priv->descs[offset]; + u32 wait; + int ret; + + dev_dbg(dev, "gpio %d set to %d\n", offset, value); + + ret = dm_gpio_set_value(&desc->real_gpio, value); + if (ret) { + dev_err(dev, "Failed to set gpio %d, value %d\n", offset, value); + return ret; + } + + if (value) + wait = desc->ramp_up_us; + else + wait = desc->ramp_down_us; + + udelay(wait); + + dev_dbg(dev, "waited for %d us\n", wait); + + return 0; +} + +static int gpio_delay_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + return gpio_delay_set_value(dev, offset, value); +} + +static int gpio_delay_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + struct gpio_delay_priv *priv = dev_get_priv(dev); + + if (args->args_count < 3) + return -EINVAL; + + if (args->args[0] >= 32) + return -EINVAL; + + struct gpio_delay_desc *d = &priv->descs[args->args[0]]; + + d->ramp_up_us = args->args[1]; + d->ramp_down_us = args->args[2]; + + dev_dbg(dev, "pin: %d, ramp_up_us: %d, ramp_down_us: %d\n", + args->args[0], d->ramp_up_us, d->ramp_down_us); + + return 0; +} + +static const struct dm_gpio_ops gpio_delay_ops = { + .direction_output = gpio_delay_direction_output, + .direction_input = gpio_delay_direction_input, + .get_value = gpio_delay_get_value, + .set_value = gpio_delay_set_value, + .xlate = gpio_delay_xlate, +}; + +static int gpio_delay_probe(struct udevice *dev) +{ + struct gpio_delay_priv *priv = dev_get_priv(dev); + struct gpio_delay_desc *d; + ofnode node = dev_ofnode(dev); + int i = 0, ret, ngpio; + + ngpio = gpio_get_list_count(dev, "gpios"); + if (ngpio < 0) + return ngpio; + + dev_dbg(dev, "gpios: %d\n", ngpio); + + priv->descs = devm_kmalloc_array(dev, ngpio, sizeof(*d), GFP_KERNEL); + if (!priv->descs) + return -ENOMEM; + + /* Request all GPIOs described in the controller node */ + for (i = 0; i < ngpio; i++) { + d = &priv->descs[i]; + ret = gpio_request_by_name_nodev(node, "gpios", i, + &d->real_gpio, 0); + if (ret) + return ret; + } + + return 0; +} + +static const struct udevice_id gpio_delay_ids[] = { + { .compatible = "gpio-delay" }, + { } +}; + +U_BOOT_DRIVER(gpio_delay) = { + .name = "gpio-delay", + .id = UCLASS_GPIO, + .of_match = gpio_delay_ids, + .ops = &gpio_delay_ops, + .priv_auto = sizeof(struct gpio_delay_priv), + .probe = gpio_delay_probe, +}; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 38151ef1bee..7651d5360d6 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -18,15 +18,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define GPIO_ALLOC_BITS 32 /** diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c index 741b2ff7f17..5abbb34daea 100644 --- a/drivers/gpio/nx_gpio.c +++ b/drivers/gpio/nx_gpio.c @@ -7,12 +7,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct nx_gpio_regs { u32 data; /* Data register */ u32 outputenb; /* Output Enable register */ diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index d13947a0d9c..3e933acb24b 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -28,6 +28,7 @@ enum pca_type { PCA9548, PCA9646, PCA9847, + PCA9848, }; struct chip_desc { @@ -106,6 +107,10 @@ static const struct chip_desc chips[] = { .muxtype = pca954x_ismux, .width = 8, }, + [PCA9848] = { + .muxtype = pca954x_isswi, + .width = 8, + }, }; static int pca954x_deselect(struct udevice *mux, struct udevice *bus, @@ -152,6 +157,7 @@ static const struct udevice_id pca954x_ids[] = { { .compatible = "nxp,pca9548", .data = PCA9548 }, { .compatible = "nxp,pca9646", .data = PCA9646 }, { .compatible = "nxp,pca9847", .data = PCA9847 }, + { .compatible = "nxp,pca9848", .data = PCA9848 }, { } }; diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 2dfc1c4eab5..268bb39f009 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -30,8 +29,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define I2C_QUIRK_FLAG (1 << 0) #define IMX_I2C_REGSHIFT 2 diff --git a/drivers/i2c/nx_i2c.c b/drivers/i2c/nx_i2c.c index 8562dd82bd6..706b7adefe8 100644 --- a/drivers/i2c/nx_i2c.c +++ b/drivers/i2c/nx_i2c.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #define I2C_WRITE 0 @@ -45,8 +44,6 @@ #define DEFAULT_SPEED 100000 /* default I2C speed [Hz] */ -DECLARE_GLOBAL_DATA_PTR; - struct nx_i2c_regs { uint iiccon; uint iicstat; diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index cf714d22ee4..32704ee8854 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -12,7 +12,6 @@ * Andreas Larsson */ -#include #include #include #include @@ -75,8 +74,6 @@ struct ocores_i2c_bus { u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg); }; -DECLARE_GLOBAL_DATA_PTR; - /* Boolean attribute values */ enum { FALSE = 0, diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 79f7a320502..4102375e5b7 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -25,7 +25,6 @@ #endif #endif #include -#include #include #if defined(CONFIG_SOFT_I2C_GPIO_SCL) @@ -82,8 +81,6 @@ /* #define DEBUG_I2C */ -DECLARE_GLOBAL_DATA_PTR; - #ifndef I2C_SOFT_DECLARATIONS # define I2C_SOFT_DECLARATIONS #endif diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c index 6672d9435e3..6e5722327c5 100644 --- a/drivers/i2c/synquacer_i2c.c +++ b/drivers/i2c/synquacer_i2c.c @@ -112,8 +112,6 @@ #define SPEED_FM 400 // Fast Mode #define SPEED_SM 100 // Standard Mode -DECLARE_GLOBAL_DATA_PTR; - struct synquacer_i2c { void __iomem *base; unsigned long pclkrate; diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 47ce0ea690f..5bf122c5505 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -48,7 +48,8 @@ config APPLE_SPI_KEYB config BUTTON_KEYBOARD bool "Buttons as keyboard" - depends on DM_KEYBOARD + depends on DM_KEYBOARD && DM_GPIO + select BUTTON select BUTTON_GPIO help Enable support for mapping buttons to keycode events. Use linux,code button driver diff --git a/drivers/input/cpcap_pwrbutton.c b/drivers/input/cpcap_pwrbutton.c index c8ad39d33ca..ef6311bbfc5 100644 --- a/drivers/input/cpcap_pwrbutton.c +++ b/drivers/input/cpcap_pwrbutton.c @@ -76,7 +76,7 @@ static int cpcap_pwrbutton_of_to_plat(struct udevice *dev) /* Check interrupt parent, driver supports only CPCAP as parent */ irq_parent = ofnode_parse_phandle(dev_ofnode(dev), "interrupt-parent", 0); - if (!ofnode_device_is_compatible(irq_parent, "motorola,cpcap")) + if (!strstr(ofnode_get_name(irq_parent), "cpcap")) return -EINVAL; ret = dev_read_u32(dev, "interrupts", &irq_desc); @@ -87,9 +87,7 @@ static int cpcap_pwrbutton_of_to_plat(struct udevice *dev) priv->bank = irq_desc / 16; priv->id = irq_desc % 16; - ret = dev_read_u32(dev, "linux,code", &priv->keycode); - if (ret) - return ret; + priv->keycode = dev_read_u32_default(dev, "linux,code", KEY_POWER); priv->old_state = false; priv->skip = false; diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index cc715ceb286..de95a1debdc 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -138,271 +138,4 @@ config SPL_LED_GPIO This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. -config LED_STATUS - bool "Enable legacy status LED API" - depends on !LED - help - Allows common u-boot commands to use a board's leds to - provide status for activities like booting and downloading files. - -if LED_STATUS - -# Hidden constants - -config LED_STATUS_OFF - int - default 0 - -config LED_STATUS_BLINKING - int - default 1 - -config LED_STATUS_ON - int - default 2 - -# Hidden constants end - -config LED_STATUS_GPIO - bool "GPIO status LED implementation" - help - The status LED can be connected to a GPIO pin. In such cases, the - gpio_led driver can be used as a status LED backend implementation. - -config LED_STATUS_BOARD_SPECIFIC - bool "Specific board" - default y - help - LED support is only for a specific board. - -comment "LEDs parameters" - -config LED_STATUS0 - bool "Enable status LED 0" - -if LED_STATUS0 - -config LED_STATUS_BIT - int "identification" - help - CONFIG_LED_STATUS_BIT is passed into the __led_* functions to identify - which LED is being acted on. As such, the chosen value must be unique - with respect to the other CONFIG_LED_STATUS_BIT's. Mapping the value - to a physical LED is the responsibility of the __led_* function. - -config LED_STATUS_STATE - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ: - LED_STATUS_PERIOD = CONFIG_SYS_HZ/LED_STATUS_FREQ - Values range: 2 - 10 - -endif # LED_STATUS0 - -config LED_STATUS1 - bool "Enable status LED 1" - -if LED_STATUS1 - -config LED_STATUS_BIT1 - int "identification" - help - CONFIG_LED_STATUS_BIT1 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE1 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ1 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ1: - LED_STATUS_PERIOD1 = CONFIG_SYS_HZ/LED_STATUS_FREQ1 - Values range: 2 - 10 - -endif # LED_STATUS1 - -config LED_STATUS2 - bool "Enable status LED 2" - -if LED_STATUS2 - -config LED_STATUS_BIT2 - int "identification" - help - CONFIG_LED_STATUS_BIT2 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE2 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ2 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ2: - LED_STATUS_PERIOD2 = CONFIG_SYS_HZ/LED_STATUS_FREQ2 - Values range: 2 - 10 - -endif # LED_STATUS2 - -config LED_STATUS3 - bool "Enable status LED 3" - -if LED_STATUS3 - -config LED_STATUS_BIT3 - int "identification" - help - CONFIG_LED_STATUS_BIT3 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE3 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ3 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ3: - LED_STATUS_PERIOD3 = CONFIG_SYS_HZ/LED_STATUS_FREQ3 - Values range: 2 - 10 - -endif # LED_STATUS3 - -config LED_STATUS4 - bool "Enable status LED 4" - -if LED_STATUS4 - -config LED_STATUS_BIT4 - int "identification" - help - CONFIG_LED_STATUS_BIT4 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE4 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ4 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ4: - LED_STATUS_PERIOD4 = CONFIG_SYS_HZ/LED_STATUS_FREQ4 - Values range: 2 - 10 - -endif # LED_STATUS4 - -config LED_STATUS5 - bool "Enable status LED 5" - -if LED_STATUS5 - -config LED_STATUS_BIT5 - int "identification" - help - CONFIG_LED_STATUS_BIT5 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE5 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ5 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ5: - LED_STATUS_PERIOD5 = CONFIG_SYS_HZ/LED_STATUS_FREQ5 - Values range: 2 - 10 - -endif # LED_STATUS5 - -config LED_STATUS_BOOT_ENABLE - bool "Enable BOOT LED" - help - Enable to turn an LED on when the board is booting. - -if LED_STATUS_BOOT_ENABLE - -config LED_STATUS_BOOT - int "LED to light when the board is booting" - help - Valid enabled LED device number. - -endif # LED_STATUS_BOOT_ENABLE - -config LED_STATUS_CMD - bool "Enable status LED commands" - -endif # LED_STATUS - endmenu diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index b1e0465e7a8..c7eaa3de96f 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -15,8 +15,6 @@ /* This driver only exposes the status bits to keep with the * polling methodology of u-boot. */ -DECLARE_GLOBAL_DATA_PTR; - #define IMX_MU_CHANS 24 #define IMX_MU_V2_PAR_OFF 0x4 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index a0aa290480e..ea785793d18 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -86,6 +86,7 @@ config GATEWORKS_SC config QCOM_GENI bool "Qualcomm Generic Interface (GENI) driver" depends on MISC + select EFI_PARTITION select PARTITION_TYPE_GUID help Enable support for Qualcomm GENI and it's peripherals. GENI is responseible @@ -256,7 +257,7 @@ config VPL_CROS_EC_LPC config CROS_EC_SANDBOX bool "Enable Chrome OS EC sandbox driver" - depends on CROS_EC && SANDBOX + depends on CROS_EC && SANDBOX && HASH help Enable a sandbox emulation of the Chrome OS EC. This supports keyboard (use the -l flag to enable the LCD), verified boot context, @@ -350,7 +351,8 @@ config MXS_OCOTP config NPCM_HOST bool "Enable support espi or LPC for Host" - depends on REGMAP && SYSCON + depends on SYSCON + select REGMAP help Enable NPCM BMC espi or LPC support for Host reading and writing. diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 1d950f7a0ab..e2170212e5a 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -48,8 +48,6 @@ obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ obj-$(CONFIG_IMX_ELE) += imx_ele/ obj-$(CONFIG_K3_FUSE) += k3_fuse.o -obj-$(CONFIG_LED_STATUS) += status_led.o -obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o obj-$(CONFIG_$(PHASE_)LS2_SFP) += ls2_sfp.o obj-$(CONFIG_$(PHASE_)MXC_OCOTP) += mxc_ocotp.o diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index 3b9046da880..aa3094fcc01 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -25,8 +24,6 @@ #define ATSHA204A_TRANSACTION_RETRY 5 #define ATSHA204A_EXECTIME 5000 -DECLARE_GLOBAL_DATA_PTR; - static inline u16 atsha204a_crc16(const u8 *buffer, size_t len) { return bitrev16(crc16(0, buffer, len)); diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 2928cf75f89..6af4c7f15e7 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -25,8 +24,6 @@ #include #endif -DECLARE_GLOBAL_DATA_PTR; - /** * struct firmware - A place for storing firmware and its attribute data. * diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c deleted file mode 100644 index 1e2f83cca93..00000000000 --- a/drivers/misc/gpio_led.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Status LED driver based on GPIO access conventions of Linux - * - * Copyright (C) 2010 Thomas Chou - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#ifndef CFG_GPIO_LED_INVERTED_TABLE -#define CFG_GPIO_LED_INVERTED_TABLE {} -#endif - -static led_id_t gpio_led_inv[] = CFG_GPIO_LED_INVERTED_TABLE; - -static int gpio_led_gpio_value(led_id_t mask, int state) -{ - int i, gpio_value = (state == CONFIG_LED_STATUS_ON); - - for (i = 0; i < ARRAY_SIZE(gpio_led_inv); i++) { - if (gpio_led_inv[i] == mask) - gpio_value = !gpio_value; - } - - return gpio_value; -} - -void __led_init(led_id_t mask, int state) -{ - int gpio_value; - - if (gpio_request(mask, "gpio_led") != 0) { - printf("%s: failed requesting GPIO%lu!\n", __func__, mask); - return; - } - - gpio_value = gpio_led_gpio_value(mask, state); - gpio_direction_output(mask, gpio_value); -} - -void __led_set(led_id_t mask, int state) -{ - int gpio_value = gpio_led_gpio_value(mask, state); - - gpio_set_value(mask, gpio_value); -} - -void __led_toggle(led_id_t mask) -{ - gpio_set_value(mask, !gpio_get_value(mask)); -} diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 90d251a4405..872713e30b6 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -8,11 +8,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #define FSL_ECC_WORD_START_1 0x10 #define FSL_ECC_WORD_END_1 0x10F diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index d9cc7acb970..c15a4a629ad 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -374,6 +374,31 @@ void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) __func__, status, RPC_R8(&msg)); } +int sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type) +{ + struct udevice *dev = gd->arch.scu_dev; + int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; + int ret; + + if (!dev) + hang(); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_BOOT_TYPE; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret < 0) + return ret; + + if (type) + *type = (u8)RPC_U8(&msg, 0U); + + return 0; +} + int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx) { struct udevice *dev = gd->arch.scu_dev; diff --git a/drivers/misc/imx_ele/Makefile b/drivers/misc/imx_ele/Makefile index f8d8c55f983..a5317454583 100644 --- a/drivers/misc/imx_ele/Makefile +++ b/drivers/misc/imx_ele/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += ele_api.o ele_mu.o -obj-$(CONFIG_CMD_FUSE) += fuse.o +obj-y += ele_api.o ele_mu.o fuse.o diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index e7aee0fcef1..8ee0a7733ca 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -844,3 +844,31 @@ int ele_volt_change_finish_req(void) return ret; } + +int ele_set_gmid(u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_SET_GMID_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} diff --git a/drivers/misc/k3_fuse.c b/drivers/misc/k3_fuse.c index 4a8ff1f2523..faafaffe07e 100644 --- a/drivers/misc/k3_fuse.c +++ b/drivers/misc/k3_fuse.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #define K3_SIP_OTP_WRITEBUFF 0xC2000000 @@ -28,20 +29,19 @@ int fuse_read(u32 bank, u32 word, u32 *val) *val = res.a1; if (res.a0 != 0) - printf("SMC call failed: Error code %lu\n", res.a0); + printf("SMC call failed: Error code %ld\n", res.a0); return res.a0; } int fuse_sense(u32 bank, u32 word, u32 *val) { - return -EPERM; + return fuse_read(bank, word, val); } int fuse_prog(u32 bank, u32 word, u32 val) { struct arm_smccc_res res; - u32 mask = val; if (bank != 0U) { printf("Invalid bank argument, ONLY bank 0 is supported\n"); @@ -49,11 +49,18 @@ int fuse_prog(u32 bank, u32 word, u32 val) } /* Make SiP SMC call and send the word, val and mask in the parameter register */ - arm_smccc_smc(K3_SIP_OTP_WRITE, word, - val, mask, 0, 0, 0, 0, &res); + arm_smccc_smc(K3_SIP_OTP_WRITE, bank, word, + val, GENMASK(25, 0), 0, 0, 0, &res); - if (res.a0 != 0) - printf("SMC call failed: Error code %lu\n", res.a0); + if (res.a0 != 0) { + printf("SMC call failed: Error code %ld\n", res.a0); + return res.a0; + } + + if (res.a1 != val) { + printf("Readback failed, written 0x%x readback 0x%lx\n", val, res.a1); + return -EINVAL; + } return res.a0; } @@ -72,7 +79,7 @@ int fuse_writebuff(ulong addr) 0, 0, 0, 0, 0, 0, &res); if (res.a0 != 0) - printf("SMC call failed: Error code %lu\n", res.a0); + printf("SMC call failed: Error code %ld\n", res.a0); return res.a0; } diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c index 46820425a84..64b6238981b 100644 --- a/drivers/misc/rockchip-otp.c +++ b/drivers/misc/rockchip-otp.c @@ -390,6 +390,10 @@ static const struct udevice_id rockchip_otp_ids[] = { .compatible = "rockchip,rk3308-otp", .data = (ulong)&px30_data, }, + { + .compatible = "rockchip,rk3506-otp", + .data = (ulong)&rk3568_data, + }, { .compatible = "rockchip,rk3528-otp", .data = (ulong)&rk3568_data, diff --git a/drivers/misc/status_led.c b/drivers/misc/status_led.c deleted file mode 100644 index 3b1baa4f840..00000000000 --- a/drivers/misc/status_led.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include - -/* - * The purpose of this code is to signal the operational status of a - * target which usually boots over the network; while running in - * U-Boot, a status LED is blinking. As soon as a valid BOOTP reply - * message has been received, the LED is turned off. The Linux - * kernel, once it is running, will start blinking the LED again, - * with another frequency. - */ - -/* ------------------------------------------------------------------------- */ - -typedef struct { - led_id_t mask; - int state; - int period; - int cnt; -} led_dev_t; - -led_dev_t led_dev[] = { - { CONFIG_LED_STATUS_BIT, - CONFIG_LED_STATUS_STATE, - LED_STATUS_PERIOD, - 0, - }, -#if defined(CONFIG_LED_STATUS1) - { CONFIG_LED_STATUS_BIT1, - CONFIG_LED_STATUS_STATE1, - LED_STATUS_PERIOD1, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS2) - { CONFIG_LED_STATUS_BIT2, - CONFIG_LED_STATUS_STATE2, - LED_STATUS_PERIOD2, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS3) - { CONFIG_LED_STATUS_BIT3, - CONFIG_LED_STATUS_STATE3, - LED_STATUS_PERIOD3, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS4) - { CONFIG_LED_STATUS_BIT4, - CONFIG_LED_STATUS_STATE4, - LED_STATUS_PERIOD4, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS5) - { CONFIG_LED_STATUS_BIT5, - CONFIG_LED_STATUS_STATE5, - LED_STATUS_PERIOD5, - 0, - }, -#endif -}; - -#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t)) - -static int status_led_init_done = 0; - -void status_led_init(void) -{ - led_dev_t *ld; - int i; - - for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) - __led_init (ld->mask, ld->state); - status_led_init_done = 1; -} - -void status_led_tick(ulong timestamp) -{ - led_dev_t *ld; - int i; - - if (!status_led_init_done) - status_led_init(); - - for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) { - - if (ld->state != CONFIG_LED_STATUS_BLINKING) - continue; - - if (++ld->cnt >= ld->period) { - __led_toggle (ld->mask); - ld->cnt -= ld->period; - } - - } -} - -void status_led_set(int led, int state) -{ - led_dev_t *ld; - - if (led < 0 || led >= MAX_LED_DEV) - return; - - if (!status_led_init_done) - status_led_init(); - - ld = &led_dev[led]; - - ld->state = state; - if (state == CONFIG_LED_STATUS_BLINKING) { - ld->cnt = 0; /* always start with full period */ - state = CONFIG_LED_STATUS_ON; /* always start with LED _ON_ */ - } - __led_set (ld->mask, state); -} diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 39caf2eff1b..22bd3a972bd 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -627,8 +627,9 @@ config MMC_SDHCI_AM654 depends on ARCH_K3 depends on MMC_SDHCI depends on OF_CONTROL - depends on REGMAP select MMC_SDHCI_IO_ACCESSORS + select REGMAP + select SPL_REGMAP if SPL_MMC help Support for Secure Digital Host Controller Interface (SDHCI) controllers present on TI's AM654 SOCs. diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index 1af5ec0532e..d5a4453a62e 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #define MIN_FREQ (400000) -DECLARE_GLOBAL_DATA_PTR; - struct ca_mmc_plat { struct mmc_config cfg; struct mmc mmc; diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c index f47cf848521..f0356e1e960 100644 --- a/drivers/mmc/f_sdh30.c +++ b/drivers/mmc/f_sdh30.c @@ -29,8 +29,6 @@ struct f_sdh30_plat { const struct f_sdh30_data *data; }; -DECLARE_GLOBAL_DATA_PTR; - static void f_sdh30_e51_init(struct udevice *dev) { struct f_sdh30_plat *plat = dev_get_plat(dev); diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 7dc76563b7e..335b44a8a1a 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -752,10 +752,11 @@ static int esdhc_set_voltage(struct mmc *mmc) int ret; priv->signal_voltage = mmc->signal_voltage; + if (priv->vs18_enable) + return -ENOTSUPP; + switch (mmc->signal_voltage) { case MMC_SIGNAL_VOLTAGE_330: - if (priv->vs18_enable) - return -ENOTSUPP; if (CONFIG_IS_ENABLED(DM_REGULATOR) && !IS_ERR_OR_NULL(priv->vqmmc_dev)) { ret = regulator_set_value(priv->vqmmc_dev, diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c index fc10bb256a4..651d9868305 100644 --- a/drivers/mmc/jz_mmc.c +++ b/drivers/mmc/jz_mmc.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include @@ -419,8 +418,6 @@ int jz_mmc_init(void __iomem *base) #else /* CONFIG_DM_MMC */ #include -DECLARE_GLOBAL_DATA_PTR; - static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c5705f4f215..f0e38efb262 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2343,7 +2343,8 @@ static int mmc_startup_v4(struct mmc *mmc) MMC_VERSION_4_41, MMC_VERSION_4_5, MMC_VERSION_5_0, - MMC_VERSION_5_1 + MMC_VERSION_5_1, + MMC_VERSION_5_1B }; #if CONFIG_IS_ENABLED(MMC_TINY) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 38dc36a2194..66f3cf2de4f 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -61,8 +60,6 @@ struct msm_sdhc_variant_info { u32 core_vendor_spec_capabilities0; }; -DECLARE_GLOBAL_DATA_PTR; - static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 4928a880038..7a4bdee7496 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -1979,6 +1979,16 @@ static const struct msdc_compatible mt8183_compat = { .use_dma_mode = true, }; +static const struct msdc_compatible mt8189_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, +}; + static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat }, { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat }, @@ -1990,6 +2000,7 @@ static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, + { .compatible = "mediatek,mt8189-mmc", .data = (ulong)&mt8189_compat }, {} }; diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 2da5334c21f..a8b63a20387 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #define MVSDH_NAME "mv_sdh" @@ -14,8 +13,6 @@ #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4)) #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4)) -DECLARE_GLOBAL_DATA_PTR; - struct mv_sdhci_plat { struct mmc_config cfg; struct mmc mmc; diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 6219284df3e..c8da6ead0ea 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -58,8 +58,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Disable SDMMC clock. */ clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); @@ -95,8 +95,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); #endif - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 306175873fa..2999e6b1710 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -217,7 +217,7 @@ config NAND_DENALI bool select DEVRES select SYS_NAND_SELF_INIT - select SYS_NAND_ONFI_DETECTION if TARGET_SOCFPGA_SOC64 + select SYS_NAND_ONFI_DETECTION if ARCH_SOCFPGA_SOC64 imply CMD_NAND config NAND_DENALI_DT diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 7bf54fa4654..7324dc72e0a 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -30,8 +29,6 @@ #include "pxa3xx_nand.h" -DECLARE_GLOBAL_DATA_PTR; - #define TIMEOUT_DRAIN_FIFO 5 /* in ms */ #define CHIP_DELAY_TIMEOUT 200 #define NAND_STOP_DELAY 40 diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c index ef43dcad079..0bee7eace90 100644 --- a/drivers/mtd/nand/raw/tegra_nand.c +++ b/drivers/mtd/nand/raw/tegra_nand.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include "tegra_nand.h" -DECLARE_GLOBAL_DATA_PTR; - #define NAND_CMD_TIMEOUT_MS 10 #define SKIPPED_SPARE_BYTES 4 diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c index 1a109bee557..383971bea66 100644 --- a/drivers/mtd/nvmxip/nvmxip_qspi.c +++ b/drivers/mtd/nvmxip/nvmxip_qspi.c @@ -11,9 +11,6 @@ #include #include -#include -DECLARE_GLOBAL_DATA_PTR; - #define NVMXIP_QSPI_DRV_NAME "nvmxip_qspi" /** diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index a13c7fc60e6..56f6fb70acd 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -292,4 +292,10 @@ config SPL_SPI_FLASH_MTD If unsure, say N +config SPI_FRAM_FUJITSU + bool "Fujitsu SPI FRAM support" + help + Add support for the Fujitsu MB85RS256TY FRAM chip. It's treated the same + as SPI NOR flash at the moment. + endmenu # menu "SPI Flash Support" diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 102a9236826..a9db5296b2d 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -11,13 +11,10 @@ #include #include #include -#include #include #include #include "sf_internal.h" -DECLARE_GLOBAL_DATA_PTR; - int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf) { return log_ret(sf_get_ops(dev)->read(dev, offset, len, buf)); diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 76c33b24368..937d79af64e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -4250,6 +4250,90 @@ static struct spi_nor_fixups macronix_octal_fixups = { }; #endif /* CONFIG_SPI_FLASH_MACRONIX */ +#if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND) + +#define WINBOND_NOR_OP_SELDIE 0xc2 /* Select active die */ + +struct winbond_nor_priv { + unsigned int n_dice; +}; + +/** + * winbond_nor_select_die() - Set active die. + * @nor: pointer to 'struct spi_nor'. + * @die: die to set active. + * + * Certain Winbond chips feature more than a single die. This is mostly hidden + * to the user, except that some chips may experience time deviation when + * modifying the status bits between dies, which in some corner cases may + * produce problematic races. Being able to explicitly select a die to check its + * state in this case may be useful. + * + * Return: 0 on success, -errno otherwise. + */ +static int winbond_nor_select_die(struct spi_nor *nor, u8 die) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_SELDIE, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &die, 0)); + + int ret; + + spi_nor_setup_op(nor, &op, SNOR_PROTO_1_1_1); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + debug("Error %d selecting die %d\n", ret, die); + + return ret; +} + +static int winbond_nor_multi_die_ready(struct spi_nor *nor) +{ + struct winbond_nor_priv *winbond_priv = nor->priv; + unsigned int n_dice = winbond_priv ? winbond_priv->n_dice : 1; + int ret, i; + + for (i = 0; i < n_dice; i++) { + ret = winbond_nor_select_die(nor, i); + if (ret) + return ret; + + ret = spi_nor_sr_ready(nor); + if (ret <= 0) + return ret; + } + + return 1; +} + +static void winbond_nor_multi_die_post_sfdp_fixups(struct spi_nor *nor, + struct spi_nor_flash_parameter *param) +{ + struct winbond_nor_priv *winbond_priv; + + winbond_priv = kmalloc(sizeof(*winbond_priv), GFP_KERNEL); + if (!winbond_priv) + return; + + winbond_priv->n_dice = param->size / SZ_64M; + + /* + * SFDP supports dice numbers, but this information is only available in + * optional additional tables which are not provided by these chips. + * Dice number has an impact though, because these devices need extra + * care when reading the busy bit. + */ + nor->priv = winbond_priv; + nor->ready = winbond_nor_multi_die_ready; +} + +static struct spi_nor_fixups winbond_nor_multi_die_fixups = { + .post_sfdp = winbond_nor_multi_die_post_sfdp_fixups, +}; +#endif /* CONFIG_SPI_FLASH_WINBOND */ + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @@ -4464,6 +4548,23 @@ void spi_nor_set_fixups(struct spi_nor *nor) nor->info->flags & SPI_NOR_OCTAL_DTR_READ) nor->fixups = ¯onix_octal_fixups; #endif /* SPI_FLASH_MACRONIX */ + +#if CONFIG_IS_ENABLED(SPI_FLASH_WINBOND) + if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND) { + u8 multi_die_models[][2] = { + { 0x40, 0x21 }, /* W25Q01JV */ + { 0x70, 0x22 }, /* W25Q02JV */ + }; + int i; + + for (i = 0; i < sizeof(multi_die_models) / 2; i++) { + if (!memcmp(nor->info->id + 1, multi_die_models[i], 2)) { + nor->fixups = &winbond_nor_multi_die_fixups; + break; + } + } + } +#endif /* SPI_FLASH_WINBOND */ } int spi_nor_scan(struct spi_nor *nor) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index b6a07fa9063..e7fea375706 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -86,6 +86,19 @@ const struct flash_info spi_nor_ids[] = { { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif +#ifdef CONFIG_SPI_FRAM_FUJITSU + /* Fujitsu MB85RS256TY */ + { + INFO_NAME("mb85rs256ty") + .id = {0x04, 0x7f, 0x25, 0x00, 0x00}, + .id_len = 3, + .sector_size = 32 * 1024, + .n_sectors = 1, + .page_size = 32 * 1024, /* Whole chip can be written at once */ + .flags = SPI_NOR_NO_ERASE, + .addr_width = 2, + }, +#endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ /* GigaDevice */ { @@ -243,6 +256,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) }, { INFO("is25lp01gg", 0x9d6021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25wp02gg", 0x9d7022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -473,7 +488,6 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, - { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -539,11 +553,6 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, - { - INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, { INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -581,7 +590,7 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, - { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 23de64a1520..cf00473ee83 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -220,6 +220,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, /* Some Micron need WREN command; all will accept it */ need_wren = true; fallthrough; + case SNOR_MFR_ISSI: case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: if (need_wren) @@ -246,6 +247,9 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, } return status; + case SNOR_MFR_CYPRESS: + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS; + return spi_nor_write_reg(nor, cmd, NULL, 0); default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index fce8004e134..ed07e286676 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1,7 +1,3 @@ -source "drivers/net/phy/Kconfig" -source "drivers/net/pfe_eth/Kconfig" -source "drivers/net/fsl-mc/Kconfig" - config ETH def_bool y @@ -94,9 +90,10 @@ config DSA_SANDBOX Ethernet device used as DSA master, to test DSA class code, including exported DSA API and datapath processing of Ethernet traffic. -menuconfig NETDEVICES - bool "Network device support" - depends on NET || NET_LWIP +menu "Network device support" + +config NETDEVICES + bool select DM_ETH help You must select Y to enable any network device support @@ -121,11 +118,15 @@ config AG7XXX This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips. +source "drivers/net/airoha/Kconfig" + config AIROHA_ETH bool "Airoha Ethernet QDMA Driver" depends on ARCH_AIROHA + select MISC select PHYLIB select DEVRES + select DM_ETH_PHY select DM_RESET select MDIO_MT7531_MMIO help @@ -194,7 +195,7 @@ config DWC_ETH_XGMAC_SOCFPGA select SYSCON select DWC_ETH_XGMAC depends on ARCH_SOCFPGA - default y if TARGET_SOCFPGA_AGILEX5 + default y if ARCH_SOCFPGA_AGILEX5 help The Synopsys Designware Ethernet XGMAC IP block with specific configuration used in Intel SoC FPGA chip. @@ -979,7 +980,11 @@ source "drivers/net/mtk_eth/Kconfig" config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" + depends on DM && OF_CONTROL + select CLK select DM_CLK + select DM_ETH_PHY + select DM_MDIO select DM_RESET select PHYLIB help @@ -989,13 +994,14 @@ config HIFEMAC_ETH config HIFEMAC_MDIO bool "HiSilicon Fast Ethernet Controller MDIO interface" depends on DM_MDIO - select DM_CLK + select CLK help This driver supports the internal MDIO interface of HIFEMAC Ethernet controller. config HIGMACV300_ETH bool "HiSilicon Gigabit Ethernet Controller" + depends on DM && OF_CONTROL select DM_RESET select PHYLIB help @@ -1098,4 +1104,10 @@ config MDIO_MUX_MESON_GXL This driver is used for the MDIO mux found on the Amlogic GXL & compatible SoCs. +source "drivers/net/phy/Kconfig" +source "drivers/net/pfe_eth/Kconfig" +source "drivers/net/fsl-mc/Kconfig" + endif # NETDEVICES + +endmenu diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5bb40480d88..5e90183d090 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o +obj-y += airoha/ obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o diff --git a/drivers/net/airoha/Kconfig b/drivers/net/airoha/Kconfig new file mode 100644 index 00000000000..d0c007ced80 --- /dev/null +++ b/drivers/net/airoha/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PCS_AIROHA + bool + select MISC + +config PCS_AIROHA_AN7581 + bool "Airoha AN7581 PCS driver" + depends on ARCH_AIROHA + select PCS_AIROHA + help + This module provides helper to phylink for managing the Airoha + AN7581 PCS for SoC Ethernet and PON SERDES. diff --git a/drivers/net/airoha/Makefile b/drivers/net/airoha/Makefile new file mode 100644 index 00000000000..81fd26cf813 --- /dev/null +++ b/drivers/net/airoha/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PCS_AIROHA) += pcs-airoha-common.o +obj-$(CONFIG_PCS_AIROHA_AN7581) += pcs-an7581.o diff --git a/drivers/net/airoha/pcs-airoha-common.c b/drivers/net/airoha/pcs-airoha-common.c new file mode 100644 index 00000000000..1263092fcdd --- /dev/null +++ b/drivers/net/airoha/pcs-airoha-common.c @@ -0,0 +1,827 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pcs-airoha.h" + +static void airoha_pcs_setup_scu_eth(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 xsi_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + xsi_sel = AIROHA_SCU_ETH_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + xsi_sel = AIROHA_SCU_ETH_XSI_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSR3, + AIROHA_SCU_ETH_XSI_SEL, + xsi_sel); +} + +static void airoha_pcs_setup_scu_pon(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 xsi_sel, wan_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + wan_sel = AIROHA_SCU_WAN_SEL_SGMII; + xsi_sel = AIROHA_SCU_PON_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_2500BASEX: + wan_sel = AIROHA_SCU_WAN_SEL_HSGMII; + xsi_sel = AIROHA_SCU_PON_XSI_HSGMII; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + default: + wan_sel = AIROHA_SCU_WAN_SEL_USXGMII; + xsi_sel = AIROHA_SCU_PON_XSI_USXGMII; + } + + regmap_update_bits(priv->scu, AIROHA_SCU_SSTR, + AIROHA_SCU_PON_XSI_SEL, + xsi_sel); + + regmap_update_bits(priv->scu, AIROHA_SCU_WAN_CONF, + AIROHA_SCU_WAN_SEL, + wan_sel); +} + +static int airoha_pcs_setup_scu(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + const struct airoha_pcs_match_data *data = priv->data; + int ret; + + if (priv->xfi_rst) { + ret = reset_assert(priv->xfi_rst); + if (ret) + return ret; + } + + switch (data->port_type) { + case AIROHA_PCS_ETH: + airoha_pcs_setup_scu_eth(priv, interface); + break; + case AIROHA_PCS_PON: + airoha_pcs_setup_scu_pon(priv, interface); + break; + } + + if (priv->xfi_rst) { + ret = reset_deassert(priv->xfi_rst); + if (ret) + return ret; + } + + /* TODO better handle reset from MAC */ + ret = reset_assert_bulk(&priv->rsts); + if (ret) + return ret; + + ret = reset_deassert_bulk(&priv->rsts); + if (ret) + return ret; + + return 0; +} + +static void airoha_pcs_init_usxgmii(struct airoha_pcs_priv *priv) +{ + const struct airoha_pcs_match_data *data = priv->data; + + regmap_set_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + /* Disable Hibernation */ + if (data->hibernation_workaround) + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTROL_1, + AIROHA_PCS_USXGMII_SPEED_SEL_H); + + /* FIXME: wait Airoha */ + /* Avoid PCS sending garbage to MAC in some HW revision (E0) */ + if (data->usxgmii_ber_time_fixup) + regmap_write(priv->usxgmii_pcs, AIROHA_PCS_USGMII_VENDOR_DEFINE_116, 0); + + if (data->usxgmii_rx_gb_out_vld_tweak) + regmap_clear_bits(priv->usxgmii_pcs, AN7583_PCS_USXGMII_RTL_MODIFIED, + AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD); +} + +static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv) +{ + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_TBI_10B_MODE); +} + +static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv) +{ + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0, + AIROHA_PCS_HSGMII_XFI_SEL); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_TBI_10B_MODE); + + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L, 0x07070707)); + + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C, 0xff)); +} + +static void airoha_pcs_init(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + airoha_pcs_init_sgmii(priv); + break; + case PHY_INTERFACE_MODE_2500BASEX: + airoha_pcs_init_hsgmii(priv); + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + airoha_pcs_init_usxgmii(priv); + break; + default: + return; + } +} + +static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv) +{ + /* Disable every interrupt */ + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT); + + /* Clear interrupt */ + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT, + AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR | + AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR); +} + +static void airoha_pcs_interrupt_init_usxgmii(struct airoha_pcs_priv *priv) +{ + /* Disable every Interrupt */ + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_0, + AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_1, + AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN | + AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN | + AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_2, + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN | + AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_3, + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN | + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN | + AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN | + AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN); + + regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_CTRL_4, + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN); + + /* Clear any pending interrupt */ + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_2, + AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT | + AIROHA_PCS_USXGMII_R_TYPE_E_INT | + AIROHA_PCS_USXGMII_R_TYPE_T_INT | + AIROHA_PCS_USXGMII_R_TYPE_D_INT); + + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_3, + AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT | + AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT | + AIROHA_PCS_USXGMII_LINK_UP_ST_INT | + AIROHA_PCS_USXGMII_HI_BER_ST_INT); + + regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_INT_STA_4, + AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT); + + /* Interrupt saddly seems to be not weel supported for Link Down. + * PCS Poll is a must to correctly read and react on Cable Deatch + * as only cable attach interrupt are fired and Link Down interrupt + * are fired only in special case like AN restart. + */ +} + +static void airoha_pcs_interrupt_init(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + return airoha_pcs_interrupt_init_sgmii(priv); + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + return airoha_pcs_interrupt_init_usxgmii(priv); + default: + return; + } +} + +int airoha_pcs_config(struct udevice *dev, bool neg_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + const struct airoha_pcs_match_data *data; + u32 rate_adapt; + int ret; + + priv->interface = interface; + data = priv->data; + + /* Apply Analog and Digital configuration for PCS */ + if (data->bringup) { + ret = data->bringup(priv, interface); + if (ret) + return ret; + } + + /* Set final configuration for various modes */ + airoha_pcs_init(priv, interface); + + /* Configure Interrupt for various modes */ + airoha_pcs_interrupt_init(priv, interface); + + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN; + + if (interface == PHY_INTERFACE_MODE_SGMII) + rate_adapt |= AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS; + + /* AN Auto Settings (Rate Adaptation) */ + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN | + AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN, rate_adapt); + + /* FIXME: With an attached Aeonsemi PHY, AN is needed + * even with no inband. + */ + if (interface == PHY_INTERFACE_MODE_USXGMII || + interface == PHY_INTERFACE_MODE_10GBASER) { + if (interface == PHY_INTERFACE_MODE_USXGMII) + regmap_set_bits(priv->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_ENABLE); + else + regmap_clear_bits(priv->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0, + AIROHA_PCS_USXGMII_AN_ENABLE); + + if (data->usxgmii_xfi_mode_sel && neg_mode) + regmap_set_bits(priv->usxgmii_pcs, + AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7, + AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL | + AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL); + } + + /* Clear any force bit that my be set by bootloader */ + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX || + interface == PHY_INTERFACE_MODE_2500BASEX) { + regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0, + AIROHA_PCS_LINK_MODE_P0 | + AIROHA_PCS_FORCE_SPD_MODE_P0 | + AIROHA_PCS_FORCE_LINKDOWN_P0 | + AIROHA_PCS_FORCE_LINKUP_P0); + } + + /* Toggle Rate Adaption for SGMII/HSGMII mode */ /* TODO */ + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX || + interface == PHY_INTERFACE_MODE_2500BASEX) { + if (neg_mode) + regmap_clear_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0, + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE); + else + regmap_set_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0, + AIROHA_PCS_HSGMII_P0_DIS_MII_MODE); + } + + /* Setup SGMII AN and advertisement in DEV_ABILITY */ /* TODO */ + if (interface == PHY_INTERFACE_MODE_SGMII) { + if (neg_mode) { + int advertise = 0x1; + + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4, + AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY, + FIELD_PREP(AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY, + advertise)); + + regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + } else { + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + } + } + + if (interface == PHY_INTERFACE_MODE_2500BASEX) { + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0, + AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_TX_ENABLE); + } + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX) { + u32 if_mode = AIROHA_PCS_HSGMII_AN_SIDEBAND_EN; + + /* Toggle SGMII or 1000base-x mode */ + if (interface == PHY_INTERFACE_MODE_SGMII) + if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_EN; + + if (neg_mode) + regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS); + else + regmap_clear_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS); + + if (neg_mode) { + /* Clear force speed bits and MAC mode */ + regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 | + AIROHA_PCS_HSGMII_PCS_MAC_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT); + } else { + /* Enable compatibility with MAC PCS Layer */ + if_mode |= AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN; + + /* AN off force rate adaption, speed is set later in Link Up */ + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_MAC_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT); + } + + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0, if_mode); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_TX_ENABLE | + AIROHA_PCS_HSGMII_PCS_MODE2_EN); + } + + if (interface == PHY_INTERFACE_MODE_1000BASEX && + !neg_mode) { + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1, + AIROHA_PCS_SGMII_SEND_AN_ERR_EN); + + regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37, + AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE); + } + + /* Configure Flow Control on XFI */ + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN, + permit_pause_to_mac ? + AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN : + 0); + + return 0; +} + +void airoha_pcs_link_up(struct udevice *dev, unsigned int neg_mode, + phy_interface_t interface, int speed, int duplex) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + const struct airoha_pcs_match_data *data; + + data = priv->data; + + if (neg_mode) { + if (interface == PHY_INTERFACE_MODE_SGMII) { + regmap_update_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0x0) | + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x0)); + udelay(1); + regmap_update_bits(priv->hsgmii_rate_adp, + AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1, + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR | + AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR, 0xf) | + FIELD_PREP(AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR, 0x5)); + } + } else { + if (interface == PHY_INTERFACE_MODE_USXGMII || + interface == PHY_INTERFACE_MODE_10GBASER) { + u32 mode; + u32 rate_adapt; + + switch (speed) { + case SPEED_10000: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000; + mode = AIROHA_PCS_USXGMII_MODE_10000; + break; + /* case SPEED_5000: not supported in U-Boot + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000; + mode = AIROHA_PCS_USXGMII_MODE_5000; + break; */ + case SPEED_2500: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500; + mode = AIROHA_PCS_USXGMII_MODE_2500; + break; + case SPEED_1000: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000; + mode = AIROHA_PCS_USXGMII_MODE_1000; + break; + case SPEED_100: + rate_adapt = AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100; + mode = AIROHA_PCS_USXGMII_MODE_100; + break; + } + + /* Trigger USXGMII change mode and force selected speed */ + regmap_update_bits(priv->usxgmii_pcs, AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7, + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | + AIROHA_PCS_USXGMII_MODE, + AIROHA_PCS_USXGMII_RATE_UPDATE_MODE | mode); + + regmap_update_bits(priv->hsgmii_rate_adp, AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11, + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN | + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, + AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN | + rate_adapt); + } + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_1000BASEX) { + u32 force_speed; + u32 rate_adapt; + + switch (speed) { + case SPEED_1000: + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000; + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000; + break; + case SPEED_100: + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100; + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100; + break; + case SPEED_10: + force_speed = AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10; + rate_adapt = AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10; + break; + } + + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_6, + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 | + AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 | + AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, + force_speed | rate_adapt); + } + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_2500BASEX) { + u32 ck_gen_mode; + u32 speed_reg; + u32 if_mode; + + switch (speed) { + case SPEED_2500: + speed_reg = AIROHA_PCS_LINK_MODE_P0_2_5G; + break; + case SPEED_1000: + speed_reg = AIROHA_PCS_LINK_MODE_P0_1G; + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000; + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000; + break; + case SPEED_100: + speed_reg = AIROHA_PCS_LINK_MODE_P0_100M; + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100; + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100; + break; + case SPEED_10: + speed_reg = AIROHA_PCS_LINK_MODE_P0_100M; + if_mode = AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10; + ck_gen_mode = AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10; + break; + } + + if (interface == PHY_INTERFACE_MODE_SGMII) { + regmap_update_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13, + AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, + if_mode); + + regmap_update_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE, + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE | + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL, + ck_gen_mode | + AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL); + } + + regmap_update_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0, + AIROHA_PCS_LINK_MODE_P0 | + AIROHA_PCS_FORCE_SPD_MODE_P0, + speed_reg | + AIROHA_PCS_FORCE_SPD_MODE_P0); + } + } + + if (data->link_up) + data->link_up(priv); + + /* BPI BMI enable */ + regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); +} + +void airoha_pcs_link_down(struct udevice *dev) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + + /* MPI MBI disable */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); +} + +void airoha_pcs_pre_config(struct udevice *dev, phy_interface_t interface) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + + /* Select HSGMII or USXGMII in SCU regs */ + airoha_pcs_setup_scu(priv, interface); + + /* MPI MBI disable */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RXMPI_STOP | + AIROHA_PCS_XFI_RXMBI_STOP | + AIROHA_PCS_XFI_TXMPI_STOP | + AIROHA_PCS_XFI_TXMBI_STOP); + + /* Write 1 to trigger reset and clear */ + regmap_clear_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST, + AIROHA_PCS_XFI_MAC_LOGIC_RST); + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST, + AIROHA_PCS_XFI_MAC_LOGIC_RST); + + udelay(1000); + + /* Clear XFI MAC counter */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_CNT_CLR, + AIROHA_PCS_XFI_GLB_CNT_CLR); +} + +int airoha_pcs_post_config(struct udevice *dev, phy_interface_t interface) +{ + struct airoha_pcs_priv *priv = dev_get_priv(dev); + + /* Frag disable */ + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RX_FRAG_LEN, + FIELD_PREP(AIROHA_PCS_XFI_RX_FRAG_LEN, 31)); + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FRAG_LEN, + FIELD_PREP(AIROHA_PCS_XFI_TX_FRAG_LEN, 31)); + + /* IPG NUM */ + regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_IPG_NUM, + FIELD_PREP(AIROHA_PCS_XFI_IPG_NUM, 10)); + + /* Enable TX/RX flow control */ + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_TX_FC_EN); + regmap_set_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG, + AIROHA_PCS_XFI_RX_FC_EN); + + return 0; +} + +static const struct regmap_config airoha_pcs_regmap_config = { + .width = REGMAP_SIZE_32, +}; + +static int airoha_pcs_probe(struct udevice *dev) +{ + struct regmap_config syscon_config = airoha_pcs_regmap_config; + struct airoha_pcs_priv *priv = dev_get_priv(dev); + fdt_addr_t base; + fdt_size_t size; + int ret; + + priv->dev = dev; + priv->data = (void *)dev_get_driver_data(dev); + + base = dev_read_addr_size_name(dev, "xfi_mac", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->xfi_mac = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->xfi_mac)) + return PTR_ERR(priv->xfi_mac); + + base = dev_read_addr_size_name(dev, "hsgmii_an", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->hsgmii_an = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->hsgmii_an)) + return PTR_ERR(priv->hsgmii_an); + + base = dev_read_addr_size_name(dev, "hsgmii_pcs", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->hsgmii_pcs = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->hsgmii_pcs)) + return PTR_ERR(priv->hsgmii_pcs); + + base = dev_read_addr_size_name(dev, "hsgmii_rate_adp", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->hsgmii_rate_adp = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->hsgmii_rate_adp)) + return PTR_ERR(priv->hsgmii_rate_adp); + + base = dev_read_addr_size_name(dev, "multi_sgmii", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->multi_sgmii = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->multi_sgmii)) + return PTR_ERR(priv->multi_sgmii); + + base = dev_read_addr_size_name(dev, "usxgmii", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->usxgmii_pcs = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->usxgmii_pcs)) + return PTR_ERR(priv->usxgmii_pcs); + + base = dev_read_addr_size_name(dev, "xfi_pma", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->xfi_pma = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->xfi_pma)) + return PTR_ERR(priv->xfi_pma); + + base = dev_read_addr_size_name(dev, "xfi_ana", &size); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + syscon_config.r_start = base; + syscon_config.r_size = size; + priv->xfi_ana = devm_regmap_init(dev, NULL, NULL, &syscon_config); + if (IS_ERR(priv->xfi_ana)) + return PTR_ERR(priv->xfi_ana); + + /* SCU is used to toggle XFI or HSGMII in global SoC registers */ + priv->scu = airoha_get_scu_regmap(); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + + priv->rsts.resets = devm_kcalloc(dev, AIROHA_PCS_MAX_NUM_RSTS, + sizeof(struct reset_ctl), GFP_KERNEL); + if (!priv->rsts.resets) + return -ENOMEM; + priv->rsts.count = AIROHA_PCS_MAX_NUM_RSTS; + + ret = reset_get_by_name(dev, "mac", &priv->rsts.resets[0]); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "phy", &priv->rsts.resets[1]); + if (ret) + return ret; + + priv->xfi_rst = devm_reset_control_get_optional(dev, "xfi"); + + /* For Ethernet PCS, read the AN7581 SoC revision to check if + * manual rx calibration is needed. This is only limited to + * any SoC revision before E2. + */ + if (device_is_compatible(dev, "airoha,an7581-pcs-eth") && + priv->data->port_type == AIROHA_PCS_ETH) { + u32 val; + + ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val); + if (ret) + return ret; + + if (FIELD_GET(AIROHA_SCU_PRODUCT_ID, val) < 0x2) + priv->manual_rx_calib = true; + } + + return 0; +} + +static const struct airoha_pcs_match_data an7581_pcs_eth = { + .port_type = AIROHA_PCS_ETH, + .hibernation_workaround = true, + .usxgmii_ber_time_fixup = true, + .bringup = an7581_pcs_bringup, + .link_up = an7581_pcs_phya_link_up, +}; + +static const struct airoha_pcs_match_data an7581_pcs_pon = { + .port_type = AIROHA_PCS_PON, + .hibernation_workaround = true, + .usxgmii_ber_time_fixup = true, + .bringup = an7581_pcs_bringup, + .link_up = an7581_pcs_phya_link_up, +}; + +static const struct udevice_id airoha_pcs_of_table[] = { + { .compatible = "airoha,an7581-pcs-eth", + .data = (ulong)&an7581_pcs_eth }, + { .compatible = "airoha,an7581-pcs-pon", + .data = (ulong)&an7581_pcs_pon }, + { }, +}; + +U_BOOT_DRIVER(airoha_pcs) = { + .name = "airoha-pcs", + .id = UCLASS_MISC, + .of_match = airoha_pcs_of_table, + .probe = airoha_pcs_probe, + .priv_auto = sizeof(struct airoha_pcs_priv), +}; diff --git a/drivers/net/airoha/pcs-airoha.h b/drivers/net/airoha/pcs-airoha.h new file mode 100644 index 00000000000..714d2ebe520 --- /dev/null +++ b/drivers/net/airoha/pcs-airoha.h @@ -0,0 +1,1220 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ + +#include +#include +#include + +/* SCU*/ +#define AIROHA_SCU_PDIDR 0x5c +#define AIROHA_SCU_PRODUCT_ID GENMASK(15, 0) +#define AIROHA_SCU_WAN_CONF 0x70 +#define AIROHA_SCU_ETH_MAC_SEL BIT(24) +#define AIROHA_SCU_ETH_MAC_SEL_XFI FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x0) +#define AIROHA_SCU_ETH_MAC_SEL_PON FIELD_PREP_CONST(AIROHA_SCU_ETH_MAC_SEL, 0x1) +#define AIROHA_SCU_WAN_SEL GENMASK(7, 0) +#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10) +#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11) +#define AIROHA_SCU_WAN_SEL_USXGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x12) +#define AIROHA_SCU_SSR3 0x94 +#define AIROHA_SCU_ETH_XSI_SEL GENMASK(14, 13) +#define AIROHA_SCU_ETH_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x1) +#define AIROHA_SCU_ETH_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_ETH_XSI_SEL, 0x2) +#define AIROHA_SCU_SSTR 0x9c +#define AIROHA_SCU_PON_XSI_SEL GENMASK(10, 9) +#define AIROHA_SCU_PON_XSI_USXGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x1) +#define AIROHA_SCU_PON_XSI_HSGMII FIELD_PREP_CONST(AIROHA_SCU_PON_XSI_SEL, 0x2) + +/* XFI_MAC */ +#define AIROHA_PCS_XFI_MAC_XFI_GIB_CFG 0x0 +#define AIROHA_PCS_XFI_RX_FRAG_LEN GENMASK(26, 22) +#define AIROHA_PCS_XFI_TX_FRAG_LEN GENMASK(21, 17) +#define AIROHA_PCS_XFI_IPG_NUM GENMASK(15, 10) +#define AIROHA_PCS_XFI_TX_FC_EN BIT(5) +#define AIROHA_PCS_XFI_RX_FC_EN BIT(4) +#define AIROHA_PCS_XFI_RXMPI_STOP BIT(3) +#define AIROHA_PCS_XFI_RXMBI_STOP BIT(2) +#define AIROHA_PCS_XFI_TXMPI_STOP BIT(1) +#define AIROHA_PCS_XFI_TXMBI_STOP BIT(0) +#define AIROHA_PCS_XFI_MAC_XFI_LOGIC_RST 0x10 +#define AIROHA_PCS_XFI_MAC_LOGIC_RST BIT(0) +#define AIROHA_PCS_XFI_MAC_XFI_MACADDRH 0x60 +#define AIROHA_PCS_XFI_MAC_MACADDRH GENMASK(15, 0) +#define AIROHA_PCS_XFI_MAC_XFI_MACADDRL 0x64 +#define AIROHA_PCS_XFI_MAC_MACADDRL GENMASK(31, 0) +#define AIROHA_PCS_XFI_MAC_XFI_CNT_CLR 0x100 +#define AIROHA_PCS_XFI_GLB_CNT_CLR BIT(0) + +/* HSGMII_AN */ +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0 +#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */ +#define AIROHA_PCS_HSGMII_AN_SGMII_UNIDIR_ABILITY BIT(6) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_COMPLETE BIT(5) +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT BIT(4) +#define AIROHA_PCS_HSGMII_AN_SGMII_AN_ABILITY BIT(3) +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_STATUS BIT(2) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_4 0x10 +#define AIROHA_PCS_HSGMII_AN_SGMII_DEV_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_5 0x14 /* LPA */ +#define AIROHA_PCS_HSGMII_AN_SGMII_PARTNER_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_11 0x2c +#define AIROHA_PCS_HSGMII_AN_SGMII_LINK_TIMER GENMASK(19, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_13 0x34 +#define AIROHA_PCS_HSGMII_AN_SGMII_REMOTE_FAULT_DIS BIT(8) +#define AIROHA_PCS_HSGMII_AN_SGMII_IF_MODE_5_0 GENMASK(5, 0) +#define AIROHA_PCS_HSGMII_AN_SGMII_COMPAT_EN BIT(5) +#define AIROHA_PCS_HSGMII_AN_DUPLEX_FORCE_MODE BIT(4) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE GENMASK(3, 2) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x2) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x1) +#define AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_AN_SPEED_FORCE_MODE, 0x0) +#define AIROHA_PCS_HSGMII_AN_SIDEBAND_EN BIT(1) +#define AIROHA_PCS_HSGMII_AN_SGMII_EN BIT(0) +#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_FORCE_CL37 0x60 +#define AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE BIT(0) + +/* HSGMII_PCS */ +#define AIROHA_PCS_HSGMII_PCS_CTROL_1 0x0 +#define AIROHA_PCS_TBI_10B_MODE BIT(30) +#define AIROHA_PCS_SGMII_SEND_AN_ERR_EN BIT(24) +#define AIROHA_PCS_REMOTE_FAULT_DIS BIT(12) +#define AIROHA_PCS_HSGMII_PCS_CTROL_3 0x8 +#define AIROHA_PCS_HSGMII_PCS_LINK_STSTIME GENMASK(19, 0) +#define AIROHA_PCS_HSGMII_PCS_CTROL_6 0x14 +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_10 BIT(14) +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_100 BIT(13) +#define AIROHA_PCS_HSGMII_PCS_SGMII_SPD_FORCE_1000 BIT(12) +#define AIROHA_PCS_HSGMII_PCS_MAC_MODE BIT(8) +#define AIROHA_PCS_HSGMII_PCS_TX_ENABLE BIT(4) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL GENMASK(3, 2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x0) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x1) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT_VAL, 0x2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_RATEADAPT BIT(1) +#define AIROHA_PCS_HSGMII_PCS_MODE2_EN BIT(0) +#define AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT 0x20 +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR BIT(11) +#define AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT BIT(10) +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR BIT(9) +#define AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT BIT(8) +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR BIT(5) +#define AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT BIT(4) +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR BIT(3) +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR BIT(2) +#define AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT BIT(1) +#define AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT BIT(0) +#define AIROHA_PCS_HSGMII_PCS_AN_SGMII_MODE_FORCE 0x24 +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE GENMASK(5, 4) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x0) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x1) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_10 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE, 0x2) +#define AIROHA_PCS_HSGMII_PCS_FORCE_CUR_SGMII_MODE_SEL BIT(0) +#define ARIOHA_PCS_HSGMII_PCS_STATE_2 0x104 +#define AIROHA_PCS_HSGMII_PCS_RX_SYNC BIT(5) +#define AIROHA_PCS_HSGMII_PCS_AN_DONE BIT(0) +#define AIROHA_PCS_HSGMII_PCS_INT_STATE 0x15c +#define AIROHA_PCS_HSGMII_PCS_MODE2_REMOTE_FAULT_OCCUR_INT BIT(4) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_MLS BIT(3) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_CL37_TIMERDONE_INT BIT(2) +#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1) +#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0) + +/* MULTI_SGMII */ +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14 +#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0) +#define AIROHA_PCS_MULTI_SGMII_SGMII_STS_CTRL_0 0x18 +#define AIROHA_PCS_LINK_MODE_P0 GENMASK(5, 4) +#define AIROHA_PCS_LINK_MODE_P0_2_5G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x3) +#define AIROHA_PCS_LINK_MODE_P0_1G FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x2) +#define AIROHA_PCS_LINK_MODE_P0_100M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x1) +#define AIROHA_PCS_LINK_MODE_P0_10M FIELD_PREP_CONST(AIROHA_PCS_LINK_MODE_P0, 0x0) +#define AIROHA_PCS_FORCE_SPD_MODE_P0 BIT(2) +#define AIROHA_PCS_FORCE_LINKDOWN_P0 BIT(1) +#define AIROHA_PCS_FORCE_LINKUP_P0 BIT(0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0 0x100 +#define AIROHA_PCS_HSGMII_XFI_SEL BIT(28) +#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_SEL 0x14c +#define AIROHA_PCS_HSGMII_PCS_INT BIT(0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_15 0x43c +#define AIROHA_PCS_LINK_STS_P0 BIT(3) +#define AIROHA_PCS_SPEED_STS_P0 GENMASK(2, 0) +#define AIROHA_PCS_SPEED_STS_P0_1G FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x2) +#define AIROHA_PCS_SPEED_STS_P0_100M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x1) +#define AIROHA_PCS_SPEED_STS_P0_10M FIELD_PREP_CONST(AIROHA_PCS_SPEED_STS_P0, 0x0) +#define AIROHA_PCS_MULTI_SGMII_MSG_RX_STS_18 0x448 +#define AIROHA_PCS_P0_SGMII_IS_10 BIT(2) +#define AIROHA_PCS_P0_SGMII_IS_100 BIT(1) +#define AIROHA_PCS_P0_SGMII_IS_1000 BIT(0) + +/* HSGMII_RATE_ADP */ +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_0 0x0 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_BYPASS BIT(27) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_BYPASS BIT(26) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_EN BIT(4) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_TX_EN BIT(0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_1 0x4 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_WR_THR GENMASK(20, 16) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_RD_THR GENMASK(28, 24) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_6 0x18 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_L GENMASK(31, 0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_8 0x20 +#define AIROHA_PCS_HSGMII_RATE_ADAPT_RX_AFIFO_DOUT_C GENMASK(7, 0) +#define AIROHA_PCS_HSGMII_RATE_ADAPT_CTRL_11 0x2c +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_EN BIT(8) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE GENMASK(15, 12) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_10000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x0) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_5000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x1) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_2500 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x2) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_1000 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x4) +#define AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE_100 \ + FIELD_PREP_CONST(AIROHA_PCS_HSGMII_RATE_ADPT_FORCE_RATE_ADAPT_MODE, 0x6) +#define AIROHA_PCS_HSGMII_RATE_ADP_P0_CTRL_0 0x100 +#define AIROHA_PCS_HSGMII_P0_DIS_MII_MODE BIT(31) + +/* USXGMII */ +#define AIROHA_PCS_USXGMII_PCS_CTROL_1 0x0 +#define AIROHA_PCS_USXGMII_SPEED_SEL_H BIT(13) +#define AIROHA_PCS_USXGMII_PCS_STUS_1 0x30 +#define AIROHA_PCS_USXGMII_RX_LINK_STUS BIT(12) +#define AIROHA_PCS_USXGMII_PRBS9_PATT_TST_ABILITY BIT(3) +#define AIROHA_PCS_USXGMII_PRBS31_PATT_TST_ABILITY BIT(2) +#define AIROHA_PCS_USXGMII_PCS_BLK_LK BIT(0) +#define AIROHA_PCS_USGMII_VENDOR_DEFINE_116 0x22c +#define AIROHA_PCS_USXGMII_PCS_CTRL_0 0x2c0 +#define AIROHA_PCS_USXGMII_T_TYPE_T_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_T_TYPE_D_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_T_TYPE_C_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_T_TYPE_S_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_1 0x2c4 +#define AIROHA_PCS_USXGMII_R_TYPE_C_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_S_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_TXPCS_FSM_ENC_ERR_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_T_TYPE_E_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_2 0x2c8 +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_3 0x2cc +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT_EN BIT(24) +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT_EN BIT(16) +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT_EN BIT(8) +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_2 0x2d8 +#define AIROHA_PCS_USXGMII_RPCS_FSM_DEC_ERR_INT BIT(24) +#define AIROHA_PCS_USXGMII_R_TYPE_E_INT BIT(16) +#define AIROHA_PCS_USXGMII_R_TYPE_T_INT BIT(8) +#define AIROHA_PCS_USXGMII_R_TYPE_D_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_3 0x2dc +#define AIROHA_PCS_USXGMII_FAIL_SYNC_XOR_ST_INT BIT(24) +#define AIROHA_PCS_USXGMII_RX_BLOCK_LOCK_ST_INT BIT(16) +#define AIROHA_PCS_USXGMII_LINK_UP_ST_INT BIT(8) +#define AIROHA_PCS_USXGMII_HI_BER_ST_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_CTRL_4 0x2e0 +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT_EN BIT(0) +#define AIROHA_PCS_USXGMII_PCS_INT_STA_4 0x2e4 +#define AIROHA_PCS_USXGMII_LINK_DOWN_ST_INT BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_0 0x2f8 +#define AIROHA_PCS_USXGMII_AN_RESTART BIT(8) +#define AIROHA_PCS_USXGMII_AN_ENABLE BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_0 0x310 +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE GENMASK(30, 28) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_10G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x0) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x1) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_2_5G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x2) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_1G FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x3) +#define AIROHA_PCS_USXGMII_CUR_USXGMII_MODE_100M FIELD_PREP_CONST(AIROHA_PCS_USXGMII_CUR_USXGMII_MODE, 0x4) +#define AIROHA_PCS_USXGMII_PARTNER_ABILITY GENMASK(15, 0) +#define AIROHA_PCS_USXGMII_PCS_AN_STATS_2 0x318 +#define AIROHA_PCS_USXGMII_PCS_AN_COMPLETE BIT(24) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c +#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0) +#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320 +#define AIROHA_PCS_USXGMII_XFI_MODE_TX_SEL BIT(20) +#define AIROHA_PCS_USXGMII_XFI_MODE_RX_SEL BIT(16) +#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12) +#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8) +#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0) +#define AIROHA_PCS_USXGMII_MODE_5000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x1) +#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2) +#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3) +#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4) +#define AN7583_PCS_USXGMII_RTL_MODIFIED 0x334 +#define AIROHA_PCS_USXGMII_MODIFIED_RX_GB_OUT_VLD BIT(25) + +/* PMA_PHYA */ +#define AIROHA_PCS_ANA_PXP_CMN_EN 0x0 +#define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x0) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x1) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x2) +#define AIROHA_PCS_ANA_CMN_VREFSEL_8_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x3) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x4) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9_25V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x5) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9_5V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x6) +#define AIROHA_PCS_ANA_CMN_VREFSEL_9_75V FIELD_PREP_CONST(AIROHA_PCS_ANA_CMN_VREFSEL, 0x7) +#define AIROHA_PCS_ANA_CMN_VREFSEL GENMASK(18, 16) +/* GENMASK(2, 0) input selection from 0 to 7 + * BIT(3) OPAMP and path EN + * BIT(4) Current path measurement + * BIT(5) voltage/current path to PAD + */ +#define AIROHA_PCS_ANA_CMN_MPXSELTOP_DC GENMASK(13, 8) +#define AIROHA_PCS_ANA_CMN_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4 +#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24) +#define AIROHA_PCS_ANA_JCPLL_CHP_IBIAS GENMASK(21, 16) +#define AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN BIT(8) +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR 0x8 +#define AIROHA_PCS_ANA_JCPLL_LPF_BWR GENMASK(28, 24) +#define AIROHA_PCS_ANA_JCPLL_LPF_BP GENMASK(20, 16) +#define AIROHA_PCS_ANA_JCPLL_LPF_BC GENMASK(12, 8) +#define AIROHA_PCS_ANA_JCPLL_LPF_BR GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC 0xc +#define AIROHA_PCS_ANA_JCPLL_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_KBAND_CODE GENMASK(23, 16) +#define AIROHA_PCS_ANA_JCPLL_KBAND_OPTION BIT(8) +#define AIROHA_PCS_ANA_JCPLL_LPF_BWC GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC 0x10 +#define AIROHA_PCS_ANA_JCPLL_KBAND_KS GENMASK(17, 16) +#define AIROHA_PCS_ANA_JCPLL_KBAND_KF GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_KBAND_KFC GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE 0x14 +#define AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 BIT(24) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE GENMASK(1, 0) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x0) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x1) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x2) +#define AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, 0x3) +#define AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY 0x1c +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS GENMASK(25, 24) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x0) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x1) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x2) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_DI_LS, 0x3) +#define AIROHA_PCS_ANA_JCPLL_SDM_DI_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_PLL_RSTB BIT(8) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY GENMASK(2, 0) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_20_25 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x1) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_40_50 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x2) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_80_100 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x3) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x4) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_300_400 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x5) +#define AIROHA_PCS_ANA_JCPLL_RST_DLY_600_800 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_RST_DLY, 0x6) +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM 0x20 +#define AIROHA_PCS_ANA_JCPLL_SDM_OUT BIT(24) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD GENMASK(17, 16) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x1) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x2) +#define AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x3) +#define AIROHA_PCS_ANA_JCPLL_SDM_MODE GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_SDM_IFM BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN 0x24 +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF GENMASK(28, 24) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN GENMASK(18, 16) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x0) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x1) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x2) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x3) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_10 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN, 0x4) +#define AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN BIT(8) +#define AIROHA_PCS_ANA_JCPLL_SDM_HREN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN 0x28 +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x0) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x1) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x2) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x3) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x4) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW, 0x6) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW GENMASK(26, 24) +#define AIROHA_PCS_ANA_PXP_JCPLL_VCODIV 0x2c +#define AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR GENMASK(26, 24) +#define AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_VCO_CFIX GENMASK(9, 8) +#define AIROHA_PCS_ANA_JCPLL_VCODIV GENMASK(1, 0) +#define AIROHA_PCS_ANA_JCPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x0) +#define AIROHA_PCS_ANA_JCPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_VCODIV, 0x1) +#define AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR 0x30 +#define AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI BIT(17) +#define AIROHA_PCS_ANA_JCPLL_SSC_EN BIT(16) +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L GENMASK(10, 8) +#define AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H GENMASK(5, 3) +#define AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN 0x34 +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 GENMASK(23, 8) +#define AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA 0x38 +#define AIROHA_PCS_ANA_JCPLL_SSC_PERIOD GENMASK(31, 16) +#define AIROHA_PCS_ANA_JCPLL_SSC_DELTA GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H 0x48 +#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16) +#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8) +#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5)) +#define AIROHA_PCS_ANA_PXP_JCPLL_FREQ_MEAS_EN 0x4c +#define AIROHA_PCS_ANA_TXPLL_IB_EXT_EN BIT(24) +#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50 +#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24) +#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16) +#define AIROHA_PCS_ANA_TXPLL_CHP_IOFST GENMASK(13, 8) +#define AIROHA_PCS_ANA_TXPLL_CHP_IBIAS GENMASK(5, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP 0x54 +#define AIROHA_PCS_ANA_TXPLL_KBAND_OPTION BIT(24) +#define AIROHA_PCS_ANA_TXPLL_LPF_BWC GENMASK(20, 16) +#define AIROHA_PCS_ANA_TXPLL_LPF_BWR GENMASK(12, 8) +#define AIROHA_PCS_ANA_TXPLL_LPF_BP GENMASK(4, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE 0x58 +#define AIROHA_PCS_ANA_TXPLL_KBAND_KF GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_KBAND_KFC GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_KBAND_DIV GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_KBAND_CODE GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS 0x5c +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x0) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x1) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x2) +#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3) +#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8) +#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_PHY_CK1_EN 0x60 +#define AIROHA_PCS_ANA_TXPLL_PHY_CK2_EN BIT(8) +#define AIROHA_PCS_ANA_TXPLL_PHY_CK1_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64 +#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24) +#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV GENMASK(9, 8) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x0) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x1) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x2) +#define AIROHA_PCS_ANA_TXPLL_REFIN_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_REFIN_DIV, 0x3) +#define AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN 0x68 +#define AIROHA_PCS_ANA_TXPLL_SDM_MODE GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_SDM_IFM BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS GENMASK(9, 8) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x0) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_21 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x1) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_19 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x2) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_15 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_DI_LS, 0x3) +#define AIROHA_PCS_ANA_TXPLL_SDM_DI_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD 0x6c +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN BIT(24) +#define AIROHA_PCS_ANA_TXPLL_SDM_HREN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SDM_OUT BIT(8) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD GENMASK(1, 0) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_INT FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x0) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_1SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x1) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_2SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x2) +#define AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_SDM_ORD, 0x3) +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN 0x70 +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF GENMASK(12, 8) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN GENMASK(2, 0) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x0) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_2_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_3 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x2) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x3) +#define AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_6 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, 0x4) +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN 0x74 +#define AIROHA_PCS_ANA_TXPLL_VCO_CFIX GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_VCODIV GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_VCODIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x0) +#define AIROHA_PCS_ANA_TXPLL_VCODIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VCODIV, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x0) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x2) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x3) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_8 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x4) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_16 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW, 0x6) +#define AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN 0x78 +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L GENMASK(29, 27) +#define AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H GENMASK(26, 24) +#define AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR GENMASK(18, 16) +#define AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN 0x7c +#define AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI BIT(8) +#define AIROHA_PCS_ANA_TXPLL_SSC_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1 0x80 +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA GENMASK(31, 16) +#define AIROHA_PCS_ANA_TXPLL_SSC_DELTA1 GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD 0x84 +#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24) +#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16) +#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0) +#define AIROHA_PCS_ANA_PXP_TXPLL_VTP_EN 0x88 +#define AIROHA_PCS_ANA_TXPLL_VTP GENMASK(10, 8) +#define AIROHA_PCS_ANA_TXPLL_VTP_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF 0x94 +#define AIROHA_PCS_ANA_TXPLL_POSTDIV_D256_EN BIT(25) /* 0: 128 1: 256 */ +#define AIROHA_PCS_ANA_TXPLL_VCO_KBAND_MEAS_EN BIT(24) +#define AIROHA_PCS_ANA_TXPLL_FREQ_MEAS_EN BIT(16) +#define AIROHA_PCS_ANA_TXPLL_VREF_SEL BIT(8) +#define AIROHA_PCS_ANA_TXPLL_VREF_SEL_VBG FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x0) +#define AIROHA_PCS_ANA_TXPLL_VREF_SEL_AVDD FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_VREF_SEL, 0x1) +#define AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF GENMASK(4, 0) +#define AN7583_PCS_ANA_PXP_TXPLL_CHP_DOUBLE_EN 0x98 +#define AIROHA_PCS_ANA_TXPLL_SPARE_L BIT(0) /* ICHP_DOUBLE */ +#define AIROHA_PCS_ANA_PXP_PLL_MONCLK_SEL 0xa0 +#define AIROHA_PCS_ANA_TDC_AUTOEN BIT(24) +#define AIROHA_PCS_ANA_PXP_TDC_SYNC_CK_SEL 0xa8 +#define AIROHA_PCS_ANA_PLL_LDO_CKDRV_VSEL GENMASK(17, 16) +#define AIROHA_PCS_ANA_PLL_LDO_CKDRV_EN BIT(8) +#define AIROHA_PCS_ANA_PXP_TX_TXLBRC_EN 0xc0 +#define AIROHA_PCS_ANA_TX_TERMCAL_VREF_L GENMASK(26, 24) +#define AIROHA_PCS_ANA_TX_TERMCAL_VREF_H GENMASK(18, 16) +#define AIROHA_PCS_ANA_PXP_TX_CKLDO_EN 0xc4 +#define AIROHA_PCS_ANA_TX_DMEDGEGEN_EN BIT(24) +#define AIROHA_PCS_ANA_TX_CKLDO_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_TX_TERMCAL_SELPN 0xc8 +#define AIROHA_PCS_ANA_TX_TDC_CK_SEL GENMASK(17, 16) +#define AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL 0xcc +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE BIT(24) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL BIT(16) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_PR FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x0) +#define AIROHA_PCS_ANA_RX_PHY_CK_SEL_FROM_DES FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_PHY_CK_SEL, 0x1) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_FORCE BIT(8) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL BIT(0) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_8BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x0) +#define AIROHA_PCS_ANA_RX_BUSBIT_SEL_16BIT FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_BUSBIT_SEL, 0x1) +#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4 +#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16) +#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28) +#define AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL GENMASK(26, 24) +#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20) +#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18) +#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16) +#define AIROHA_PCS_ANA_RX_REV_0 GENMASK(15, 0) +#define AIROHA_PCS_ANA_REV_0_FE_BUF2_BIAS_TYPE GENMASK(13, 12) +#define AIROHA_PCS_ANA_REV_0_OSCAL_FE_MODE_SET_SEL BIT(11) +#define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_TRAINING BIT(10) +#define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_TRAINING GENMASK(9, 8) +#define AIROHA_PCS_ANA_REV_0_FE_EQ_GAIN_MODE_NORMAL BIT(6) +#define AIROHA_PCS_ANA_REV_0_FE_BUF_GAIN_MODE_NORMAL GENMASK(5, 4) +#define AIROHA_PCS_ANA_REV_0_VOS_PNINV GENMASK(3, 2) +#define AIROHA_PCS_ANA_REV_0_PLEYEBD4 BIT(1) +#define AIROHA_PCS_ANA_REV_0_PLEYE_XOR_MON_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8 +#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24) +#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16) +#define AIROHA_PCS_ANA_RX_PHYCK_SEL GENMASK(9, 8) +#define AIROHA_PCS_ANA_RX_PHYCK_DIV GENMASK(7, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc +#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8) +#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0) +#define AIROHA_PCS_ANA_PXP_CDR_LPF_BOT_LIM 0xe0 +#define AIROHA_PCS_ANA_CDR_LPF_BOT_LIM GENMASK(18, 0) +#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8 +#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8) +#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE 0xf4 +#define AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF BIT(24) +#define AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC 0xf8 +#define AIROHA_PCS_ANA_CDR_PR_KBAND_DIV GENMASK(26, 24) +#define AIROHA_PCS_ANA_CDR_PR_BETA_SEL GENMASK(19, 16) +#define AIROHA_PCS_ANA_CDR_PR_VCOADC_OS GENMASK(11, 8) +#define AIROHA_PCS_ANA_CDR_PR_BETA_DAC GENMASK(6, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL 0xfc +#define AIROHA_PCS_ANA_CDR_PR_FBKSEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16) +#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8) +#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0) +#define AIROHA_PCS_ANA_PXP_CDR_PR_CKREF_DIV 0x100 +#define AIROHA_PCS_ANA_CDR_PR_RSTB_BYPASS BIT(16) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV GENMASK(1, 0) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x0) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x1) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x2) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV, 0x3) +#define AIROHA_PCS_ANA_PXP_CDR_PR_TDC_REF_SEL 0x108 +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1 GENMASK(25, 24) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x0) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_2 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x1) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_4 FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x2) +#define AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1_X FIELD_PREP_CONST(AIROHA_PCS_ANA_CDR_PR_CKREF_DIV1, 0x3) +#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c +#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24) +#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19) +#define AIROHA_PCS_ANA_CDR_BUF_IN_SR GENMASK(18, 16) +#define AIROHA_PCS_ANA_CDR_PR_XFICK_EN BIT(2) +#define AIROHA_PCS_ANA_CDR_PR_MONDPI_EN BIT(1) +#define AIROHA_PCS_ANA_CDR_PR_MONDPR_EN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110 +#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24) +#define AIROHA_PCS_ANA_RX_DAC_RANGE_EYE GENMASK(9, 8) +#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114 +#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24) +#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16) +#define AIROHA_PCS_ANA_RX_SIGDET_PEAK GENMASK(9, 8) +#define AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN 0x118 +#define AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN BIT(24) +#define AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN BIT(16) +#define AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN BIT(8) +#define AIROHA_PCS_ANA_RX_FE_EQ_HZEN BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB 0x11c +#define AIROHA_PCS_ANA_FE_VCM_GEN_PWDB BIT(0) +#define AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW 0x120 +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE GENMASK(17, 8) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(0)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(1)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(2)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(3)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(4)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(5)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(6)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(7)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(8)) +#define AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS FIELD_PREP_CONST(AIROHA_PCS_ANA_RX_OSCAL_FORCE, BIT(9)) +#define AIROHA_PCS_ANA_PXP_AEQ_CFORCE 0x13c +#define AIROHA_PCS_ANA_AEQ_OFORCE GENMASK(19, 8) +#define AIROHA_PCS_ANA_AEQ_OFORCE_SAOS FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(0)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP1 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(1)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP2 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(2)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP3 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(3)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP4 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(4)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP5 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(5)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP6 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(6)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_DFETP7 FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(7)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_VGA FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(8)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_CTLE FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(9)) +#define AIROHA_PCS_ANA_AEQ_OFORCE_ATT FIELD_PREP_CONST(AIROHA_PCS_ANA_AEQ_OFORCE, BIT(10)) +#define AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB 0x144 +#define AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ 0x148 +#define AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ BIT(24) +#define AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ BIT(16) +#define AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ BIT(8) +#define AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ BIT(0) + +/* PMA_PHYD */ +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0 +#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24) +#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4 +#define AIROHA_PCS_PMA_LCPLL_CK_STB_TIMER GENMASK(31, 24) +#define AIROHA_PCS_PMA_LCPLL_PCW_MAN_LOAD_TIMER GENMASK(23, 16) +#define AIROHA_PCS_PMA_LCPLL_EN_TIMER GENMASK(15, 8) +#define AIROHA_PCS_PMA_LCPLL_MAN_PWDB BIT(0) +#define AIROHA_PCS_PMA_LCPLL_TDC_PW_0 0x10 +#define AIROHA_PCS_PMA_LCPLL_TDC_DIG_PWDB BIT(0) +#define AIROHA_PCS_PMA_LCPLL_TDC_PW_5 0x24 +#define AIROHA_PCS_PMA_LCPLL_TDC_SYNC_IN_MODE BIT(24) +#define AIROHA_PCS_PMA_LCPLL_AUTOK_TDC BIT(16) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_0 0x28 +#define AIROHA_PCS_PMA_LCPLL_KI GENMASK(10, 8) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC GENMASK(1, 0) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x0) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x1) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x2) +#define AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_PON_RX_CDR_DIVTDC, 0x3) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_1 0x2c +#define AIROHA_PCS_PMA_LCPLL_A_TDC GENMASK(11, 8) +#define AIROHA_PCS_PMA_LCPLL_GPON_SEL BIT(0) +#define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_EPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x0) +#define AIROHA_PCS_PMA_LCPLL_GPON_SEL_FROM_GPON FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_GPON_SEL, 0x1) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_3 0x34 +#define AIROHA_PCS_PMA_LCPLL_NCPO_LOAD BIT(8) +#define AIROHA_PCS_PMA_LCPLL_NCPO_SHIFT GENMASK(1, 0) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_5 0x3c +#define AIROHA_PCS_PMA_LCPLL_TDC_AUTOPW_NCPO BIT(16) +#define AIROHA_PCS_PMA_LCPLL_TDC_FLT_6 0x40 +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY GENMASK(9, 8) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x0) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D1 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x1) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D2 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x2) +#define AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY_SEL_D3 FIELD_PREP_CONST(AIROHA_PCS_PMA_LCPLL_NCPO_CHG_DELAY, 0x3) +#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_1 0x48 +#define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0) +#define AIROHA_PCS_PMA_LCPLL_TDC_PCW_2 0x4c +#define AIROHA_PCS_PMA_LCPLL_PON_HRDDS_PCW_NCPO_EPON GENMASK(30, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_0 0x68 +#define AIROHA_PCS_PMA_X_MAX GENMASK(26, 16) +#define AIROHA_PCS_PMA_X_MIN GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_1 0x6c +#define AIROHA_PCS_PMA_INDEX_MODE BIT(16) +#define AIROHA_PCS_PMA_Y_MAX GENMASK(14, 8) +#define AIROHA_PCS_PMA_Y_MIN GENMASK(6, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_2 0x70 +#define AIROHA_PCS_PMA_EYEDUR GENMASK(19, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEINDEX_CTRL_3 0x74 +#define AIROHA_PCS_PMA_EYE_NEXTPTS BIT(16) +#define AIROHA_PCS_PMA_EYE_NEXTPTS_TOGGLE BIT(8) +#define AIROHA_PCS_PMA_EYE_NEXTPTS_SEL BIT(0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_0 0x78 +#define AIROHA_PCS_PMA_EYECNT_VTH GENMASK(15, 8) +#define AIROHA_PCS_PMA_EYECNT_HTH GENMASK(7, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYEOPENING_CTRL_1 0x7c +#define AIROHA_PCS_PMA_EO_VTH GENMASK(23, 16) +#define AIROHA_PCS_PMA_EO_HTH GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_0 0x80 +#define AIROHA_PCS_PMA_EYE_MASK GENMASK(31, 24) +#define AIROHA_PCS_PMA_CNTFOREVER BIT(16) +#define AIROHA_PCS_PMA_CNTLEN GENMASK(9, 0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_1 0x84 +#define AIROHA_PCS_PMA_FORCE_EYEDUR_INIT_B BIT(24) +#define AIROHA_PCS_PMA_FORCE_EYEDUR_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_EYEDUR_INIT_B BIT(8) +#define AIROHA_PCS_PMA_DISB_EYEDUR_EN BIT(0) +#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88 +#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8) +#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0 0x8c +#define AIROHA_PCS_PMA_RX_OS_START GENMASK(23, 8) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT GENMASK(2, 0) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_05 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x0) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x1) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x2) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x3) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_0_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x4) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_1_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x5) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_3_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x6) +#define AIROHA_PCS_PMA_OSC_SPEED_OPT_6_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_OSC_SPEED_OPT, 0x7) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1 0x90 +#define AIROHA_PCS_PMA_RX_PICAL_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_PICAL_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2 0x94 +#define AIROHA_PCS_PMA_RX_PDOS_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_PDOS_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3 0x98 +#define AIROHA_PCS_PMA_RX_FEOS_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_FEOS_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4 0x9c +#define AIROHA_PCS_PMA_RX_SDCAL_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_SDCAL_START GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5 0x100 +#define AIROHA_PCS_PMA_RX_RDY GENMASK(31, 16) +#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104 +#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_0 0x108 +#define AIROHA_PCS_PMA_DISB_RX_FEOS_EN BIT(24) +#define AIROHA_PCS_PMA_DISB_RX_PDOS_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_RX_PICAL_EN BIT(8) +#define AIROHA_PCS_PMA_DISB_RX_OS_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_DISB_CTRL_1 0x10c +#define AIROHA_PCS_PMA_DISB_RX_RDY BIT(24) +#define AIROHA_PCS_PMA_DISB_RX_BLWC_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_RX_OS_RDY BIT(8) +#define AIROHA_PCS_PMA_DISB_RX_SDCAL_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_0 0x110 +#define AIROHA_PCS_PMA_FORCE_RX_FEOS_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_RX_PDOS_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_RX_PICAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_RX_OS_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_FORCE_CTRL_1 0x114 +#define AIROHA_PCS_PMA_FORCE_RX_RDY BIT(24) +#define AIROHA_PCS_PMA_FORCE_RX_BLWC_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_RX_OS_RDY BIT(8) +#define AIROHA_PCS_PMA_FORCE_RX_SDCAL_EN BIT(0) +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_0 0x118 +#define AIROHA_PCS_PMA_VEO_MASK GENMASK(31, 24) +#define AIROHA_PCS_PMA_HEO_MASK GENMASK(18, 8) +#define AIROHA_PCS_PMA_EQ_EN_DELAY GENMASK(7, 0) +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_1 0x11c +#define AIROHA_PCS_PMA_B_ZERO_SEL BIT(24) +#define AIROHA_PCS_PMA_HEO_EMPHASIS BIT(16) +#define AIROHA_PCS_PMA_A_MGAIN BIT(8) +#define AIROHA_PCS_PMA_A_LGAIN BIT(0) +#define AIROHA_PCS_PMA_PHY_EQ_CTRL_2 0x120 +#define AIROHA_PCS_PMA_EQ_DEBUG_SEL GENMASK(17, 16) +#define AIROHA_PCS_PMA_FOM_NUM_ORDER GENMASK(12, 8) +#define AIROHA_PCS_PMA_A_SEL GENMASK(1, 0) +#define AIROHA_PCS_PMA_SS_RX_FEOS 0x144 +#define AIROHA_PCS_PMA_EQ_FORCE_BLWC_FREEZE BIT(8) +#define AIROHA_PCS_PMA_LFSEL GENMASK(7, 0) +#define AIROHA_PCS_PMA_SS_RX_BLWC 0x148 +#define AIROHA_PCS_PMA_EQ_BLWC_CNT_BOT_LIM GENMASK(29, 23) +#define AIROHA_PCS_PMA_EQ_BLWC_CNT_TOP_LIM GENMASK(22, 16) +#define AIROHA_PCS_PMA_EQ_BLWC_GAIN GENMASK(11, 8) +#define AIROHA_PCS_PMA_EQ_BLWC_POL BIT(0) +#define AIROHA_PCS_PMA_EQ_BLWC_POL_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x0) +#define AIROHA_PCS_PMA_EQ_BLWC_POL_INVERSION FIELD_PREP_CONST(AIROHA_PCS_PMA_EQ_BLWC_POL, 0x1) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c +#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16) +#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_2 0x150 +#define AIROHA_PCS_PMA_LOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_LOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_3 0x154 +#define AIROHA_PCS_PMA_UNLOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_UNLOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_4 0x158 +#define AIROHA_PCS_PMA_LOCK_UNLOCKTH GENMASK(15, 12) +#define AIROHA_PCS_PMA_LOCK_LOCKTH GENMASK(11, 8) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN GENMASK(2, 0) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x0) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x1) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3) +#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7) +#define AIROHA_PCS_PMA_RX_PI_CAL 0x15c +#define AIROHA_PCS_PMA_KPGAIN GENMASK(10, 8) +#define AIROHA_PCS_PMA_RX_CAL1 0x160 +#define AIROHA_PCS_PMA_CAL_CYC GENMASK(25, 24) +#define AIROHA_PCS_PMA_CAL_CYC_63 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x0) +#define AIROHA_PCS_PMA_CAL_CYC_15 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x1) +#define AIROHA_PCS_PMA_CAL_CYC_31 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x2) +#define AIROHA_PCS_PMA_CAL_CYC_127 FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_CYC, 0x3) +#define AIROHA_PCS_PMA_CAL_STB GENMASK(17, 16) +#define AIROHA_PCS_PMA_CAL_STB_5US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x0) +#define AIROHA_PCS_PMA_CAL_STB_8US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x1) +#define AIROHA_PCS_PMA_CAL_STB_16US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x2) +#define AIROHA_PCS_PMA_CAL_STB_32US FIELD_PREP_CONST(AIROHA_PCS_PMA_CAL_STB, 0x3) +#define AIROHA_PCS_PMA_CAL_1US_SET GENMASK(15, 8) +#define AIROHA_PCS_PMA_SIM_FAST_EN BIT(0) +#define AIROHA_PCS_PMA_RX_CAL2 0x164 +#define AIROHA_PCS_PMA_CAL_CYC_TIME GENMASK(17, 16) +#define AIROHA_PCS_PMA_CAL_OUT_OS GENMASK(11, 8) +#define AIROHA_PCS_PMA_CAL_OS_PULSE BIT(0) +#define AIROHA_PCS_PMA_SS_RX_SIGDET_1 0x16c +#define AIROHA_PCS_PMA_SIGDET_EN BIT(0) +#define AIROHA_PCS_PMA_RX_FLL_0 0x170 +#define AIROHA_PCS_PMA_KBAND_KFC GENMASK(25, 24) +#define AIROHA_PCS_PMA_KBAND_KFC_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x0) +#define AIROHA_PCS_PMA_KBAND_KFC_16 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x1) +#define AIROHA_PCS_PMA_KBAND_KFC_32 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x2) +#define AIROHA_PCS_PMA_KBAND_KFC_64 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_KFC, 0x3) +#define AIROHA_PCS_PMA_FPKDIV GENMASK(18, 8) +#define AIROHA_PCS_PMA_KBAND_PREDIV GENMASK(2, 0) +#define AIROHA_PCS_PMA_KBAND_PREDIV_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x0) +#define AIROHA_PCS_PMA_KBAND_PREDIV_2 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x1) +#define AIROHA_PCS_PMA_KBAND_PREDIV_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x2) +#define AIROHA_PCS_PMA_KBAND_PREDIV_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_KBAND_PREDIV, 0x3) +#define AIROHA_PCS_PMA_RX_FLL_1 0x174 +#define AIROHA_PCS_PMA_SYMBOL_WD GENMASK(26, 24) +#define AIROHA_PCS_PMA_SETTLE_TIME_SEL GENMASK(18, 16) +#define AIROHA_PCS_PMA_LPATH_IDAC GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_FLL_2 0x178 +#define AIROHA_PCS_PMA_CK_RATE GENMASK(18, 16) +#define AIROHA_PCS_PMA_CK_RATE_20 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x0) +#define AIROHA_PCS_PMA_CK_RATE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x1) +#define AIROHA_PCS_PMA_CK_RATE_5 FIELD_PREP_CONST(AIROHA_PCS_PMA_CK_RATE, 0x2) +#define AIROHA_PCS_PMA_AMP GENMASK(10, 8) +#define AIROHA_PCS_PMA_PRBS_SEL GENMASK(2, 0) +#define AIROHA_PCS_PMA_RX_FLL_5 0x184 +#define AIROHA_PCS_PMA_FLL_IDAC_MIN GENMASK(26, 16) +#define AIROHA_PCS_PMA_FLL_IDAC_MAX GENMASK(10, 0) +#define AIROHA_PCS_PMA_RX_FLL_6 0x188 +#define AIROHA_PCS_PMA_LNX_SW_FLL_4_LATCH_EN BIT(24) +#define AIROHA_PCS_PMA_LNX_SW_FLL_3_LATCH_EN BIT(16) +#define AIROHA_PCS_PMA_LNX_SW_FLL_2_LATCH_EN BIT(8) +#define AIROHA_PCS_PMA_LNX_SW_FLL_1_LATCH_EN BIT(0) +#define AIROHA_PCS_PMA_RX_FLL_B 0x19c +#define AIROHA_PCS_PMA_LOAD_EN BIT(0) +#define AIROHA_PCS_PMA_RX_PDOS_CTRL_0 0x200 +#define AIROHA_PCS_PMA_SAP_SEL GENMASK(18, 16) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x0) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x1) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_8 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x2) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x3) +#define AIROHA_PCS_PMA_SAP_SEL_SHIFT_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_SAP_SEL, 0x4) +#define AIROHA_PCS_PMA_EYE_BLWC_ADD BIT(8) +#define AIROHA_PCS_PMA_DATA_BLWC_ADD BIT(0) +#define AIROHA_PCS_PMA_RX_RESET_0 0x204 +#define AIROHA_PCS_PMA_CAL_RST_B BIT(24) +#define AIROHA_PCS_PMA_EQ_PI_CAL_RST_B BIT(16) +#define AIROHA_PCS_PMA_FEOS_RST_B BIT(8) +#define AIROHA_PCS_PMA_RX_RESET_1 0x208 +#define AIROHA_PCS_PMA_SIGDET_RST_B BIT(8) +#define AIROHA_PCS_PMA_PDOS_RST_B BIT(0) +#define AIROHA_PCS_PMA_RX_DEBUG_0 0x20c +#define AIROHA_PCS_PMA_RO_TOGGLE BIT(24) +#define AIROHA_PCS_PMA_BISTCTL_CONTROL 0x210 +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL GENMASK(4, 0) +/* AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x0) */ +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x1) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x2) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS15 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x3) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS23 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x4) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS31 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x5) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_HFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x6) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_MFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x7) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_4 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x8) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_5_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x9) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_6 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xa) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_7 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xb) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_8_LFTP FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xc) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_9 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xd) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_10 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xe) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_SQUARE_11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0xf) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PROG_80 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x10) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_1 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x11) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_ALL_0 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x12) +#define AIROHA_PCS_PMA_BISTCTL_PAT_SEL_PRBS11 FIELD_PREP_CONST(AIROHA_PCS_PMA_BISTCTL_PAT_SEL, 0x13) +#define AIROHA_PCS_PMA_BISTCTL_ALIGN_PAT 0x214 +#define AIROHA_PCS_PMA_BISTCTL_POLLUTION 0x220 +#define AIROHA_PCS_PMA_BIST_TX_DATA_POLLUTION_LATCH BIT(16) +#define AIROHA_PCS_PMA_BISTCTL_PRBS_INITIAL_SEED 0x224 +#define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD 0x230 +#define AIROHA_PCS_PMA_BISTCTL_PRBS_FAIL_THRESHOLD_MASK GENMASK(15, 0) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_2 0x23c +#define AIROHA_PCS_PMA_PI_CAL_DATA_OUT GENMASK(22, 16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_5 0x248 +#define AIROHA_PCS_PMA_VEO_RDY BIT(24) +#define AIROHA_PCS_PMA_HEO_RDY BIT(16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_9 0x258 +#define AIROHA_PCS_PMA_EO_Y_DONE BIT(24) +#define AIROHA_PCS_PMA_EO_X_DONE BIT(16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_10 0x25c +#define AIROHA_PCS_PMA_EYE_EL GENMASK(26, 16) +#define AIROHA_PCS_PMA_EYE_ER GENMASK(10, 0) +#define AIROHA_PCS_PMA_TX_RST_B 0x260 +#define AIROHA_PCS_PMA_TXCALIB_RST_B BIT(8) +#define AIROHA_PCS_PMA_TX_TOP_RST_B BIT(0) +#define AIROHA_PCS_PMA_TX_CALIB_0 0x264 +#define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL GENMASK(25, 24) +#define AIROHA_PCS_PMA_TXCALIB_FORCE_TERMP_SEL_EN BIT(16) +#define AIROHA_PCS_PMA_RX_TORGS_DEBUG_11 0x290 +#define AIROHA_PCS_PMA_EYE_EB GENMASK(14, 8) +#define AIROHA_PCS_PMA_EYE_EU GENMASK(6, 0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_0 0x294 +#define AIROHA_PCS_PMA_FORCE_DA_XPON_CDR_LPF_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_XPON_RX_FE_GAIN_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_0 0x300 +#define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_LPF_RSTB BIT(24) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_GAIN_CTRL BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_1 0x304 +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E0 BIT(24) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D1 BIT(16) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_D0 BIT(8) +#define AIROHA_PCS_PMA_RX_DISB_MODE_2 0x308 +#define AIROHA_PCS_PMA_DISB_DA_XPON_CDR_PR_PIEYE BIT(24) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_FE_VOS BIT(16) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_EYE BIT(8) +#define AIROHA_PCS_PMA_DISB_DA_XPON_RX_DAC_E1 BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_3 0x30c +#define AIROHA_PCS_PMA_FORCE_EQ_PI_CAL_RDY BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_6 0x318 +#define AIROHA_PCS_PMA_FORCE_RX_OR_PICAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_EYECNT_RDY BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_3 0x31c +#define AIROHA_PCS_PMA_DISB_RQ_PI_CAL_RDY BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_4 0x320 +#define AIROHA_PCS_PMA_DISB_BLWC_OFFSET BIT(24) +#define AIROHA_PCS_PMA_RX_DISB_MODE_5 0x324 +#define AIROHA_PCS_PMA_DISB_RX_OR_PICAL_EN BIT(24) +#define AIROHA_PCS_PMA_DISB_EYECNT_RDY BIT(16) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_7 0x328 +#define AIROHA_PCS_PMA_FORCE_PDOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_FORCE_RX_AND_PICAL_RSTB BIT(8) +#define AIROHA_PCS_PMA_FORCE_REF_AND_PICAL_RSTB BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_8 0x32c +#define AIROHA_PCS_PMA_FORCE_EYECNT_RX_RST_B BIT(24) +#define AIROHA_PCS_PMA_FORCE_FEOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_FORCE_SDCAL_REF_RST_B BIT(8) +#define AIROHA_PCS_PMA_FORCE_BLWC_RX_RST_B BIT(0) +#define AIROHA_PCS_PMA_RX_FORCE_MODE_9 0x330 +#define AIROHA_PCS_PMA_FORCE_EYE_TOP_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_EYE_RESET_PLU_O BIT(8) +#define AIROHA_PCS_PMA_FORCE_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_6 0x334 +#define AIROHA_PCS_PMA_DISB_PDOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_DISB_RX_AND_PICAL_RSTB BIT(8) +#define AIROHA_PCS_PMA_DISB_REF_AND_PICAL_RSTB BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_7 0x338 +#define AIROHA_PCS_PMA_DISB_EYECNT_RX_RST_B BIT(24) +#define AIROHA_PCS_PMA_DISB_FEOS_RX_RST_B BIT(16) +#define AIROHA_PCS_PMA_DISB_SDCAL_REF_RST_B BIT(8) +#define AIROHA_PCS_PMA_DISB_BLWC_RX_RST_B BIT(0) +#define AIROHA_PCS_PMA_RX_DISB_MODE_8 0x33c +#define AIROHA_PCS_PMA_DISB_EYE_TOP_EN BIT(16) +#define AIROHA_PCS_PMA_DISB_EYE_RESET_PLU_O BIT(8) +#define AIROHA_PCS_PMA_DISB_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_SS_BIST_1 0x344 +#define AIROHA_PCS_PMA_LNX_BISTCTL_BIT_ERROR_RST_SEL BIT(24) +#define AIROHA_PCS_PMA_ANLT_PX_LNX_LT_LOS BIT(0) +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c +#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24) +#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16) +#define AIROHA_PCS_PMA_XPON_CDR_PW_PWDB BIT(8) +#define AIROHA_PCS_PMA_XPON_RX_FE_PWDB BIT(0) +#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1 0x350 +#define AIROHA_PCS_PMA_RX_SIDGET_PWDB BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_0 0x360 +#define AIROHA_PCS_PMA_XPON_RX_RESERVED_1 0x374 +#define AIROHA_PCS_PMA_XPON_RX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL_0 0x38c +#define AIROHA_PCS_PMA_RX_SYS_EN_SEL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_0 0x390 +#define AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT GENMASK(15, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_1 0x394 +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_END GENMASK(31, 16) +#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0) +#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c +#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8) +#define AIROHA_PCS_PMA_ADD_CLKPATH_RST_0 0x410 +#define AIROHA_PCS_PMA_CLKPATH_RSTB_CK BIT(8) +#define AIROHA_PCS_PMA_CLKPATH_RST_EN BIT(0) +#define AIROHA_PCS_PMA_ADD_XPON_MODE_1 0x414 +#define AIROHA_PCS_PMA_TX_BIST_GEN_EN BIT(16) +#define AIROHA_PCS_PMA_R2T_MODE BIT(8) +#define AIROHA_PCS_PMA_ADD_RX2ANA_1 0x424 +#define AIROHA_PCS_PMA_RX_DAC_E0 GENMASK(30, 24) +#define AIROHA_PCS_PMA_RX_DAC_D1 GENMASK(22, 16) +#define AIROHA_PCS_PMA_RX_DAC_D0 GENMASK(14, 8) +#define AIROHA_PCS_PMA_RX_DAC_EYE GENMASK(6, 0) +#define AIROHA_PCS_PMA_ADD_RX2ANA_2 0x428 +#define AIROHA_PCS_PMA_RX_FEOS_OUT GENMASK(13, 8) +#define AIROHA_PCS_PMA_RX_DAC_E1 GENMASK(6, 0) +#define AIROHA_PCS_PMA_PON_TX_COUNTER_0 0x440 +#define AIROHA_PCS_PMA_TXCALIB_5US GENMASK(31, 16) +#define AIROHA_PCS_PMA_TXCALIB_50US GENMASK(15, 0) +#define AIROHA_PCS_PMA_PON_TX_COUNTER_1 0x444 +#define AIROHA_PCS_PMA_TX_HSDATA_EN_WAIT GENMASK(31, 16) +#define AIROHA_PCS_PMA_TX_CK_EN_WAIT GENMASK(15, 0) +#define AIROHA_PCS_PMA_PON_TX_COUNTER_2 0x448 +#define AIROHA_PCS_PMA_TX_SERDES_RDY_WAIT GENMASK(31, 16) +#define AIROHA_PCS_PMA_TX_POWER_ON_WAIT GENMASK(15, 0) +#define AIROHA_PCS_PMA_SW_RST_SET 0x460 +#define AIROHA_PCS_PMA_SW_XFI_RXMAC_RST_N BIT(17) +#define AIROHA_PCS_PMA_SW_XFI_TXMAC_RST_N BIT(16) +#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11) +#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10) +#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9) +#define AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N BIT(8) +#define AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N BIT(7) +#define AIROHA_PCS_PMA_SW_TX_FIFO_RST_N BIT(6) +#define AIROHA_PCS_PMA_SW_REF_RST_N BIT(5) +#define AIROHA_PCS_PMA_SW_ALLPCS_RST_N BIT(4) +#define AIROHA_PCS_PMA_SW_PMA_RST_N BIT(3) +#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2) +#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1) +#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0) +#define AIROHA_PCS_PMA_TX_DLY_CTRL 0x468 +#define AIROHA_PCS_PMA_OUTBEN_DATA_MODE GENMASK(30, 28) +#define AIROHA_PCS_PMA_TX_BEN_EXTEN_FTUNE GENMASK(23, 16) +#define AIROHA_PCS_PMA_TX_DLY_BEN_FTUNE GENMASK(14, 8) +#define AIROHA_PCS_PMA_TX_DLY_DATA_FTUNE GENMASK(6, 0) +#define AIROHA_PCS_PMA_XPON_INT_EN_3 0x474 +#define AIROHA_PCS_PMA_RX_SIGDET_INT_EN BIT(16) +#define AIROHA_PCS_PMA_XPON_INT_STA_3 0x47c +#define AIROHA_PCS_PMA_RX_SIGDET_INT BIT(16) +#define AIROHA_PCS_PMA_RX_EXTRAL_CTRL 0x48c +/* 4ref_ck step: + * - 0x1 4ref_ck + * - 0x2 8ref_ck + * - 0x3 12ref_ck + * ... + */ +#define AIROHA_PCS_PMA_L2D_TRIG_EQ_EN_TIME GENMASK(15, 8) +#define AIROHA_PCS_PMA_OS_RDY_LATCH BIT(1) +#define AIROHA_PCS_PMA_DISB_LEQ BIT(0) +#define AIROHA_PCS_PMA_RX_FREQDET 0x530 +#define AIROHA_PCS_PMA_FL_OUT GENMASK(31, 16) +#define AIROHA_PCS_PMA_FBCK_LOCK BIT(0) +#define AIROHA_PCS_PMA_XPON_TX_RATE_CTRL 0x580 +#define AIROHA_PCS_PMA_PON_TX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_MD32_MEM_CLK_CTRL 0x60c +#define AIROHA_PCS_PMA_MD32PM_CK_SEL GENMASK(31, 0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16) +#define AIROHA_PCS_PMA_PXP_AEQ_SPEED 0x76c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_OSR_SEL GENMASK(17, 16) +#define AIROHA_PCS_PMA_PXP_TX_FIR_C0B 0x778 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 GENMASK(20, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_TX_TERM_SEL 0x77c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR GENMASK(19, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL GENMASK(2, 0) +#define AIROHA_PCS_PMA_PXP_TX_FIR_C1 0x780 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 GENMASK(20, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE GENMASK(22, 16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_FLL_COR 0x790 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_DAC_EYE BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_DAC_EYE GENMASK(22, 16) +#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16) +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC GENMASK(10, 0) +#define AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR GENMASK(10, 8) +#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW 0x798 +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW GENMASK(30, 0) +#define AIROHA_PCS_PMA_PXP_RX_FE_VOS 0x79c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_FE_VOS GENMASK(5, 0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW 0x800 +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW GENMASK(30, 0) +#define AIROHA_PCS_PMA_PXP_AEQ_BYPASS 0x80c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON BIT(16) +#define AIROHA_PCS_PMA_PXP_AEQ_RSTB 0x814 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL BIT(16) +#define AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA 0x818 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PD_PWDB 0x81c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN 0x820 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB 0x824 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN 0x828 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN_RSTB 0x83c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_CKON BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_CKON BIT(16) +#define AIROHA_PCS_PMA_PXP_RX_OSCAL_EN 0x840 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_RSTB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_RSTB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_OSCAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_OSCAL_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B BIT(0) +#define AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN 0x854 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_TXPLL_KBAND_LOAD_EN 0x858 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_KBAND_LOAD_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_KBAND_LOAD_EN BIT(0) +#define AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW_CHG 0x864 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW_CHG BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW_CHG BIT(0) +#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16) +#define AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL 0x88c +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL GENMASK(1, 0) +#define AIROHA_PCS_PMA_PXP_RX_FE_PWDB 0x894 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN BIT(24) +#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16) +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0) +#define AIROHA_PCS_PMA_PXP_RX_SIGDET_CAL_EN 0x898 +#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_CAL_EN BIT(8) +#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_CAL_EN BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_12 0x8b8 +#define AIROHA_PCS_PMA_RESERVE_12_FEOS_0 BIT(0) +#define AIROHA_PCS_PMA_DIG_RESERVE_24 0x8fc +#define AIROHA_PCS_PMA_FORCE_RX_GEARBOX BIT(12) +#define AIROHA_PCS_PMA_FORCE_SEL_RX_GEARBOX BIT(8) + +#define AIROHA_PCS_MAX_CALIBRATION_TRY 50 +#define AIROHA_PCS_MAX_NUM_RSTS 2 + +enum pon_eo_buf_vals { + EYE_EU, + EYE_EB, + DAC_D0, + DAC_D1, + DAC_E0, + DAC_E1, + DAC_EYE, + FEOS, + + EO_BUF_MAX, +}; + +enum xfi_port_type { + AIROHA_PCS_ETH, + AIROHA_PCS_PON, +}; + +struct airoha_pcs_priv { + struct udevice *dev; + const struct airoha_pcs_match_data *data; + phy_interface_t interface; + + struct regmap *scu; + + struct regmap *xfi_mac; + struct regmap *hsgmii_an; + struct regmap *hsgmii_pcs; + struct regmap *hsgmii_rate_adp; + struct regmap *multi_sgmii; + struct regmap *usxgmii_pcs; + + struct regmap *xfi_pma; + struct regmap *xfi_ana; + + struct reset_ctl *xfi_rst; + struct reset_ctl_bulk rsts; + + bool manual_rx_calib; +}; + +struct airoha_pcs_match_data { + enum xfi_port_type port_type; + + bool hibernation_workaround; + bool usxgmii_ber_time_fixup; + bool usxgmii_rx_gb_out_vld_tweak; + bool usxgmii_xfi_mode_sel; + + int (*bringup)(struct airoha_pcs_priv *priv, + phy_interface_t interface); + void (*link_up)(struct airoha_pcs_priv *priv); +}; + +void airoha_pcs_pre_config(struct udevice *dev, phy_interface_t interface); +int airoha_pcs_post_config(struct udevice *dev, phy_interface_t interface); +int airoha_pcs_config(struct udevice *dev, bool neg_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac); +void airoha_pcs_link_up(struct udevice *dev, unsigned int neg_mode, + phy_interface_t interface, int speed, int duplex); +void airoha_pcs_link_down(struct udevice *dev); + +#ifdef CONFIG_PCS_AIROHA_AN7581 +int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface); + +void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv); +#else +static inline int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + return -EOPNOTSUPP; +} + +static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv) +{ +} +#endif diff --git a/drivers/net/airoha/pcs-an7581.c b/drivers/net/airoha/pcs-an7581.c new file mode 100644 index 00000000000..746ff55d72f --- /dev/null +++ b/drivers/net/airoha/pcs-an7581.c @@ -0,0 +1,1375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Christian Marangi + */ +#include +#include +#include + +#include "pcs-airoha.h" + +static void an7581_pcs_jcpll_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 kband_vref; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + kband_vref = 0x10; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + kband_vref = 0xf; + break; + default: + return; + } + + /* Setup LDO */ + udelay(200); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, + AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO); + + /* Setup RSTB */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_RST_DLY_150_200); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_PLL_RSTB); + + /* Enable PLL force selection and Force Disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN | + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_EN); + + /* Setup SDM */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_RST_DLY, + AIROHA_PCS_ANA_JCPLL_SDM_DI_LS | + AIROHA_PCS_ANA_JCPLL_SDM_DI_EN, + AIROHA_PCS_ANA_JCPLL_SDM_DI_LS_2_23); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_IFM, + AIROHA_PCS_ANA_JCPLL_SDM_OUT | + AIROHA_PCS_ANA_JCPLL_SDM_ORD | + AIROHA_PCS_ANA_JCPLL_SDM_MODE | + AIROHA_PCS_ANA_JCPLL_SDM_IFM, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_ORD, 0x0) | + AIROHA_PCS_ANA_JCPLL_SDM_ORD_3SDM | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SDM_MODE, 0x0)); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, + AIROHA_PCS_ANA_JCPLL_SDM_HREN); + + /* Setup SSC */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_DELTA, + AIROHA_PCS_ANA_JCPLL_SSC_PERIOD | + AIROHA_PCS_ANA_JCPLL_SSC_DELTA, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_PERIOD, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA, 0x0)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SSC_TRI_EN, + AIROHA_PCS_ANA_JCPLL_SSC_DELTA1 | + AIROHA_PCS_ANA_JCPLL_SSC_TRI_EN, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_SSC_DELTA1, 0x0)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, + AIROHA_PCS_ANA_JCPLL_SSC_PHASE_INI | + AIROHA_PCS_ANA_JCPLL_SSC_EN | + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L | + AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x0)); + + /* Setup LPF */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN, + AIROHA_PCS_ANA_JCPLL_CHP_IOFST | + AIROHA_PCS_ANA_JCPLL_CHP_IBIAS | + AIROHA_PCS_ANA_JCPLL_LPF_SHCK_EN, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IOFST, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_CHP_IBIAS, 0x18)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BR, + AIROHA_PCS_ANA_JCPLL_LPF_BWR | + AIROHA_PCS_ANA_JCPLL_LPF_BP | + AIROHA_PCS_ANA_JCPLL_LPF_BC | + AIROHA_PCS_ANA_JCPLL_LPF_BR, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWR, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BP, 0x10) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BC, 0x1f) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BR, BIT(3) | BIT(1))); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, + AIROHA_PCS_ANA_JCPLL_LPF_BWC, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_LPF_BWC, 0x0)); + + /* Setup VCO */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, + AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR | + AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN | + AIROHA_PCS_ANA_JCPLL_VCO_CFIX, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_SCAPWR, 0x4) | + AIROHA_PCS_ANA_JCPLL_VCO_HALFLSB_EN | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_CFIX, 0x1)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCO_TCLVAR, + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L | + AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H | + AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_L, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_VCOVAR_BIAS_H, 0x3) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_VCO_TCLVAR, 0x3)); + + /* Setup PCW */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_PCW, + AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_JCPLL_SDM_PCW, 0x25800000)); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_SDM_PCW); + + /* Setup DIV */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_MMD_PREDIV_MODE, + AIROHA_PCS_ANA_JCPLL_POSTDIV_D5 | + AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE, + AIROHA_PCS_ANA_JCPLL_MMD_PREDIV_MODE_2); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_VCODIV, + AIROHA_PCS_ANA_JCPLL_VCODIV, + AIROHA_PCS_ANA_JCPLL_VCODIV_1); + + /* Setup KBand */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_KBAND_KFC, + AIROHA_PCS_ANA_JCPLL_KBAND_KS | + AIROHA_PCS_ANA_JCPLL_KBAND_KF | + AIROHA_PCS_ANA_JCPLL_KBAND_KFC, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KS, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KF, 0x3) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_KFC, 0x0)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_LPF_BWC, + AIROHA_PCS_ANA_JCPLL_KBAND_DIV | + AIROHA_PCS_ANA_JCPLL_KBAND_CODE | + AIROHA_PCS_ANA_JCPLL_KBAND_OPTION, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_DIV, 0x2) | + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_KBAND_CODE, 0xe4)); + + /* Setup TCL */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SPARE_H, + AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF, kband_vref)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_SDM_HREN, + AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN, + FIELD_PREP(AIROHA_PCS_ANA_JCPLL_TCL_AMP_VREF, 0x5) | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_GAIN_4 | + AIROHA_PCS_ANA_JCPLL_TCL_AMP_EN); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_JCPLL_TCL_CMP_EN, + AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW | + AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_JCPLL_TCL_LPF_BW_1 | + AIROHA_PCS_ANA_JCPLL_TCL_LPF_EN); + + /* Enable PLL */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN); + + /* Enale PLL Output */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN | + AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN); +} + +static void an7581_pcs_txpll_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 lpf_chp_ibias, lpf_bp, lpf_bwr, lpf_bwc; + u32 vco_cfix; + u32 pcw; + u32 tcl_amp_vref; + bool sdm_hren; + bool vcodiv; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + lpf_chp_ibias = 0xf; + lpf_bp = BIT(1); + lpf_bwr = BIT(3) | BIT(1) | BIT(0); + lpf_bwc = BIT(4) | BIT(3); + vco_cfix = BIT(1) | BIT(0); + pcw = BIT(27); + tcl_amp_vref = BIT(3) | BIT(1) | BIT(0); + vcodiv = false; + sdm_hren = false; + break; + case PHY_INTERFACE_MODE_2500BASEX: + lpf_chp_ibias = 0xa; + lpf_bp = BIT(2) | BIT(0); + lpf_bwr = 0; + lpf_bwc = 0; + vco_cfix = 0; + pcw = BIT(27) | BIT(25); + tcl_amp_vref = BIT(3) | BIT(2) | BIT(0); + vcodiv = true; + sdm_hren = false; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + lpf_chp_ibias = 0xf; + lpf_bp = BIT(1); + lpf_bwr = BIT(3) | BIT(1) | BIT(0); + lpf_bwc = BIT(4) | BIT(3); + vco_cfix = BIT(0); + pcw = BIT(27) | BIT(22); + tcl_amp_vref = BIT(3) | BIT(1) | BIT(0); + vcodiv = false; + sdm_hren = true; + break; + default: + return; + } + + /* Setup VCO LDO Output */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, + AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT | + AIROHA_PCS_ANA_TXPLL_LDO_OUT, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT, 0x1) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LDO_OUT, 0x1)); + + /* Setup RSTB */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL, + AIROHA_PCS_ANA_TXPLL_PLL_RSTB | + AIROHA_PCS_ANA_TXPLL_RST_DLY | + AIROHA_PCS_ANA_TXPLL_REFIN_DIV | + AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL, + AIROHA_PCS_ANA_TXPLL_PLL_RSTB | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_RST_DLY, 0x4) | + AIROHA_PCS_ANA_TXPLL_REFIN_DIV_1 | + AIROHA_PCS_ANA_TXPLL_REFIN_INTERNAL); + + /* Enable PLL force selection and Force Disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN | + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_EN); + + /* Setup SDM */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_DI_EN, + AIROHA_PCS_ANA_TXPLL_SDM_MODE | + AIROHA_PCS_ANA_TXPLL_SDM_IFM | + AIROHA_PCS_ANA_TXPLL_SDM_DI_LS | + AIROHA_PCS_ANA_TXPLL_SDM_DI_EN, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SDM_MODE, 0) | + AIROHA_PCS_ANA_TXPLL_SDM_DI_LS_2_23); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, + AIROHA_PCS_ANA_TXPLL_SDM_HREN | + AIROHA_PCS_ANA_TXPLL_SDM_OUT | + AIROHA_PCS_ANA_TXPLL_SDM_ORD, + (sdm_hren ? AIROHA_PCS_ANA_TXPLL_SDM_HREN : 0) | + AIROHA_PCS_ANA_TXPLL_SDM_ORD_3SDM); + + /* Setup SSC */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_DELTA1, + AIROHA_PCS_ANA_TXPLL_SSC_DELTA | + AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_DELTA1, 0x0)); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_EN, + AIROHA_PCS_ANA_TXPLL_SSC_TRI_EN | + AIROHA_PCS_ANA_TXPLL_SSC_PHASE_INI | + AIROHA_PCS_ANA_TXPLL_SSC_EN); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SSC_PERIOD, + AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_SSC_PERIOD, 0x0)); + + /* Setup LPF */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS, + AIROHA_PCS_ANA_TXPLL_LPF_BC | + AIROHA_PCS_ANA_TXPLL_LPF_BR | + AIROHA_PCS_ANA_TXPLL_CHP_IOFST | + AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BC, 0x1f) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BR, 0x5) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IOFST, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_CHP_IBIAS, lpf_chp_ibias)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, + AIROHA_PCS_ANA_TXPLL_LPF_BWC | + AIROHA_PCS_ANA_TXPLL_LPF_BWR | + AIROHA_PCS_ANA_TXPLL_LPF_BP, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWC, lpf_bwc) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BWR, lpf_bwr) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_LPF_BP, lpf_bp)); + + /* Setup VCO */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_VCO_CFIX, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_CFIX, vco_cfix)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_VCO_HALFLSB_EN, + AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L | + AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H | + AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR | + AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR | + AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_L, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_VCOVAR_BIAS_H, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_TCLVAR, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_VCO_SCAPWR, 0x7) | + AIROHA_PCS_ANA_TXPLL_VCO_HALFLSB_EN); + + /* Setup PCW */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_SDM_PCW, + AIROHA_PCS_PMA_FORCE_DA_TXPLL_SDM_PCW, pcw); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW); + + /* Setup KBand */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_CODE, + AIROHA_PCS_ANA_TXPLL_KBAND_KF | + AIROHA_PCS_ANA_TXPLL_KBAND_KFC | + AIROHA_PCS_ANA_TXPLL_KBAND_DIV | + AIROHA_PCS_ANA_TXPLL_KBAND_CODE, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KF, 0x3) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KFC, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_DIV, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_CODE, 0xe4)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, + AIROHA_PCS_ANA_TXPLL_KBAND_KS, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_KBAND_KS, 0x1)); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_LPF_BP, + AIROHA_PCS_ANA_TXPLL_KBAND_OPTION); + + /* Setup DIV */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_KBAND_KS, + AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE | + AIROHA_PCS_ANA_TXPLL_POSTDIV_EN, + AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_2); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_VCODIV, + vcodiv ? AIROHA_PCS_ANA_TXPLL_VCODIV_2 : + AIROHA_PCS_ANA_TXPLL_VCODIV_1); + + /* Setup TCL */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_KBAND_VREF, + AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_KBAND_VREF, 0xf)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_AMP_GAIN, + AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF | + AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN, + FIELD_PREP(AIROHA_PCS_ANA_TXPLL_TCL_AMP_VREF, tcl_amp_vref) | + AIROHA_PCS_ANA_TXPLL_TCL_AMP_GAIN_4); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW | + AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN, + AIROHA_PCS_ANA_TXPLL_TCL_LPF_BW_0_5 | + AIROHA_PCS_ANA_TXPLL_TCL_LPF_EN); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TXPLL_SDM_ORD, + AIROHA_PCS_ANA_TXPLL_TCL_AMP_EN); + + /* Enable PLL */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN); + + /* Enale PLL Output */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TXPLL_CKOUT_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN | + AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN); +} + +static void an7581_pcs_tx_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 tx_rate_ctrl; + u32 ckin_divisor; + u32 fir_cn1, fir_c0b, fir_c1; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + ckin_divisor = BIT(1); + tx_rate_ctrl = BIT(0); + fir_cn1 = 0; + fir_c0b = 12; + fir_c1 = 0; + break; + case PHY_INTERFACE_MODE_2500BASEX: + ckin_divisor = BIT(2); + tx_rate_ctrl = BIT(0); + fir_cn1 = 0; + fir_c0b = 11; + fir_c1 = 1; + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + ckin_divisor = BIT(2) | BIT(0); + tx_rate_ctrl = BIT(1); + fir_cn1 = 1; + fir_c0b = 1; + fir_c1 = 11; + break; + default: + return; + } + + /* Set TX rate ctrl */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_TX_RATE_CTRL, + AIROHA_PCS_PMA_PON_TX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_PON_TX_RATE_CTRL, + tx_rate_ctrl)); + + /* Setup TX Config */ + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_TX_CKLDO_EN, + AIROHA_PCS_ANA_TX_DMEDGEGEN_EN | + AIROHA_PCS_ANA_TX_CKLDO_EN); + + udelay(1); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL | + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL); + + /* FIXME: Ask Airoha TX term is OK to reset? */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_TERM_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR | + AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_TERM_SEL | + AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_DIVISOR | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_DIVISOR, + ckin_divisor) | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_TERM_SEL, 0x0)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_RATE_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL | + AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_RATE_CTRL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_RATE_CTRL, + tx_rate_ctrl)); + + /* Setup TX FIR Load Parameters (Reference 660mV) */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C0B, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1 | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_CN1 | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_CN1, fir_cn1) | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C0B | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C0B, fir_c0b)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_TX_FIR_C1, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C2 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C2 | + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 | + AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, + AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1, fir_c1)); + + /* Reset TX Bar */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_TX_RST_B, + AIROHA_PCS_PMA_TXCALIB_RST_B | AIROHA_PCS_PMA_TX_TOP_RST_B); +} + +static void an7581_pcs_rx_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 rx_rate_ctrl; + u32 osr; + u32 pr_cdr_beta_dac; + u32 cdr_pr_buf_in_sr; + bool cdr_pr_cap_en; + u32 sigdet_vth_sel; + u32 phyck_div, phyck_sel; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + osr = BIT(1) | BIT(0); /* 1.25G */ + pr_cdr_beta_dac = BIT(3); + rx_rate_ctrl = 0; + cdr_pr_cap_en = false; + cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0); + sigdet_vth_sel = BIT(2) | BIT(1); + phyck_div = BIT(5) | BIT(3) | BIT(0); + phyck_sel = BIT(0); + break; + case PHY_INTERFACE_MODE_2500BASEX: + osr = BIT(0); /* 2.5G */ + pr_cdr_beta_dac = BIT(2) | BIT(1); + rx_rate_ctrl = 0; + cdr_pr_cap_en = true; + cdr_pr_buf_in_sr = BIT(2) | BIT(1); + sigdet_vth_sel = BIT(2) | BIT(1); + phyck_div = BIT(3) | BIT(1) | BIT(0); + phyck_sel = BIT(0); + break; + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + osr = 0; /* 10G */ + cdr_pr_cap_en = false; + pr_cdr_beta_dac = BIT(3); + rx_rate_ctrl = BIT(1); + cdr_pr_buf_in_sr = BIT(2) | BIT(1) | BIT(0); + sigdet_vth_sel = BIT(1); + phyck_div = BIT(6) | BIT(1); + phyck_sel = BIT(1); + break; + default: + return; + } + + /* Set RX rate ctrl */ + if (interface == PHY_INTERFACE_MODE_2500BASEX) + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_2, + AIROHA_PCS_PMA_CK_RATE, + AIROHA_PCS_PMA_CK_RATE_10); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_XPON_RX_RESERVED_1, + AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_XPON_RX_RATE_CTRL, rx_rate_ctrl)); + + /* Setup RX Path */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_5, + AIROHA_PCS_PMA_FLL_IDAC_MIN | + AIROHA_PCS_PMA_FLL_IDAC_MAX, + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MIN, 0x400) | + FIELD_PREP(AIROHA_PCS_PMA_FLL_IDAC_MAX, 0x3ff)); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_D1_BYPASS_AEQ, + AIROHA_PCS_ANA_RX_DAC_EYE_BYPASS_AEQ | + AIROHA_PCS_ANA_RX_DAC_E1_BYPASS_AEQ | + AIROHA_PCS_ANA_RX_DAC_E0_BYPASS_AEQ | + AIROHA_PCS_ANA_RX_DAC_D1_BYPASS_AEQ); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_PEAKING_CTRL_MSB, + AIROHA_PCS_ANA_RX_DAC_D0_BYPASS_AEQ); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_VCM_GEN_PWDB, + AIROHA_PCS_ANA_FE_VCM_GEN_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1, + AIROHA_PCS_PMA_LCPLL_MAN_PWDB); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_AEQ_CFORCE, + AIROHA_PCS_ANA_AEQ_OFORCE, + AIROHA_PCS_ANA_AEQ_OFORCE_CTLE); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_OSCAL_WATCH_WNDW, + AIROHA_PCS_ANA_RX_OSCAL_FORCE, + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA2IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_VGA1IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE2IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1VOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_CTLE1IOS | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_LVSH | + AIROHA_PCS_ANA_RX_OSCAL_FORCE_COMPOS); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_4, + AIROHA_PCS_PMA_DISB_BLWC_OFFSET); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EXTRAL_CTRL, + AIROHA_PCS_PMA_DISB_LEQ); + + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, + AIROHA_PCS_ANA_CDR_PD_EDGE_DIS | + AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_BYPASS, + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON | + AIROHA_PCS_PMA_FORCE_DA_AEQ_CKON, + AIROHA_PCS_PMA_FORCE_SEL_DA_AEQ_CKON); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_RSTB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_INJCK_SEL | + AIROHA_PCS_PMA_FORCE_DA_CDR_INJCK_SEL); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, + AIROHA_PCS_ANA_RX_DAC_MON | + AIROHA_PCS_ANA_CDR_PR_XFICK_EN | + AIROHA_PCS_ANA_CDR_PR_MONDPI_EN | + AIROHA_PCS_ANA_CDR_PR_MONDPR_EN, + FIELD_PREP(AIROHA_PCS_ANA_RX_DAC_MON, 0x0) | + AIROHA_PCS_ANA_CDR_PR_XFICK_EN); + + /* Setup FE Gain and FE Peacking */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_FE_GAIN_CTRL, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_GAIN_CTRL | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_GAIN_CTRL, 0x0)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL, 0x0)); + + /* Setup FE VOS */ + if (interface != PHY_INTERFACE_MODE_USXGMII && + interface != PHY_INTERFACE_MODE_10GBASER) + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS | + AIROHA_PCS_PMA_FORCE_DA_FE_VOS, + AIROHA_PCS_PMA_FORCE_SEL_DA_FE_VOS | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_FE_VOS, 0x0)); + + /* Setup FLL PR FMeter (no bypass mode)*/ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_0, + AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_CYCLECNT, 0x1)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_1, + AIROHA_PCS_PMA_PLL_LOCK_TARGET_END | + AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_END, 0xffff) | + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG, 0x0)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PLL_TDC_FREQDET_3, + AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, + FIELD_PREP(AIROHA_PCS_PMA_PLL_LOCK_LOCKTH, 0x1)); + + /* FIXME: Warn and Ask Airoha about typo in air_eth_xsgmii.c line 1391 */ + /* AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL is set 0x0 in SDK but seems a typo */ + /* Setup REV */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_REV_0, + AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL | + AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL | + AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, + FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF1_BIAS_CTRL, BIT(2)) | + FIELD_PREP(AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL, BIT(2)) | + FIELD_PREP(AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK, 0x0)); + + /* Setup Rdy Timeout */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_5, + AIROHA_PCS_PMA_RX_RDY | + AIROHA_PCS_PMA_RX_BLWC_RDY_EN, + FIELD_PREP(AIROHA_PCS_PMA_RX_RDY, 0xa) | + FIELD_PREP(AIROHA_PCS_PMA_RX_BLWC_RDY_EN, 0x5)); + + /* Setup CaBoundry Init */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_0, + AIROHA_PCS_PMA_RX_OS_START | + AIROHA_PCS_PMA_OSC_SPEED_OPT, + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_START, 0x1) | + AIROHA_PCS_PMA_OSC_SPEED_OPT_0_1); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6, + AIROHA_PCS_PMA_RX_OS_END, + FIELD_PREP(AIROHA_PCS_PMA_RX_OS_END, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_1, + AIROHA_PCS_PMA_RX_PICAL_END | + AIROHA_PCS_PMA_RX_PICAL_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_PICAL_START, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_4, + AIROHA_PCS_PMA_RX_SDCAL_END | + AIROHA_PCS_PMA_RX_SDCAL_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_SDCAL_START, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_2, + AIROHA_PCS_PMA_RX_PDOS_END | + AIROHA_PCS_PMA_RX_PDOS_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_PDOS_START, 0x2)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_3, + AIROHA_PCS_PMA_RX_FEOS_END | + AIROHA_PCS_PMA_RX_FEOS_START, + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_END, 0x32) | + FIELD_PREP(AIROHA_PCS_PMA_RX_FEOS_START, 0x2)); + + /* Setup By Serdes*/ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_AEQ_SPEED, + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL | + AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, + AIROHA_PCS_PMA_FORCE_SEL_DA_OSR_SEL | + FIELD_PREP(AIROHA_PCS_PMA_FORCE_DA_OSR_SEL, osr)); + + /* Setup RX OSR */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV, + AIROHA_PCS_ANA_CDR_PD_EDGE_DIS, + osr ? AIROHA_PCS_ANA_CDR_PD_EDGE_DIS : 0); + + /* Setup CDR LPF Ratio */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO, + AIROHA_PCS_ANA_CDR_LPF_TOP_LIM | + AIROHA_PCS_ANA_CDR_LPF_RATIO, + FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_TOP_LIM, 0x20000) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_LPF_RATIO, osr)); + + /* Setup CDR PR */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_BETA_DAC, + AIROHA_PCS_ANA_CDR_PR_KBAND_DIV | + AIROHA_PCS_ANA_CDR_PR_BETA_SEL | + AIROHA_PCS_ANA_CDR_PR_VCOADC_OS | + AIROHA_PCS_ANA_CDR_PR_BETA_DAC, + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_KBAND_DIV, 0x4) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_SEL, 0x1) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VCOADC_OS, 0x8) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_BETA_DAC, pr_cdr_beta_dac)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_VREG_IBAND_VAL, + AIROHA_PCS_ANA_CDR_PR_FBKSEL | + AIROHA_PCS_ANA_CDR_PR_DAC_BAND | + AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL | + AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_FBKSEL, 0x0) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_DAC_BAND, pr_cdr_beta_dac) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL, 0x6) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL, 0x6)); + + /* Setup Eye Mon */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PHY_EQ_CTRL_2, + AIROHA_PCS_PMA_EQ_DEBUG_SEL | + AIROHA_PCS_PMA_FOM_NUM_ORDER | + AIROHA_PCS_PMA_A_SEL, + FIELD_PREP(AIROHA_PCS_PMA_EQ_DEBUG_SEL, 0x0) | + FIELD_PREP(AIROHA_PCS_PMA_FOM_NUM_ORDER, 0x1) | + FIELD_PREP(AIROHA_PCS_PMA_A_SEL, 0x3)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2, + AIROHA_PCS_PMA_DATA_SHIFT | + AIROHA_PCS_PMA_EYECNT_FAST, + AIROHA_PCS_PMA_EYECNT_FAST); + + /* Calibration Start */ + + /* Enable SYS */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_SYS_EN_SEL_0, + AIROHA_PCS_PMA_RX_SYS_EN_SEL, + FIELD_PREP(AIROHA_PCS_PMA_RX_SYS_EN_SEL, 0x1)); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0, + AIROHA_PCS_PMA_SW_LCPLL_EN); + + udelay(500); + + /* Setup FLL PR FMeter (bypass mode)*/ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_DISB_MODE_8, + AIROHA_PCS_PMA_DISB_FBCK_LOCK); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FORCE_MODE_9, + AIROHA_PCS_PMA_FORCE_FBCK_LOCK); + + /* Enable CMLEQ */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_FE_EQ_HZEN, + AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN | + AIROHA_PCS_ANA_RX_FE_EQ_HZEN, + AIROHA_PCS_ANA_RX_FE_VB_EQ3_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ2_EN | + AIROHA_PCS_ANA_RX_FE_VB_EQ1_EN); + + /* Setup CDR PR */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN, + AIROHA_PCS_ANA_CDR_PR_CAP_EN | + AIROHA_PCS_ANA_CDR_BUF_IN_SR, + (cdr_pr_cap_en ? AIROHA_PCS_ANA_CDR_PR_CAP_EN : 0) | + FIELD_PREP(AIROHA_PCS_ANA_CDR_BUF_IN_SR, cdr_pr_buf_in_sr)); + + /* Setup CDR xxx Pwdb, set force and disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PIEYE_PWDB); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_KBAND_RSTB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_KBAND_RSTB | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PD_PWDB); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_PDOSCAL_EN | + AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB | + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB | + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB | + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SCAN_RST_B | + AIROHA_PCS_PMA_FORCE_DA_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0, + AIROHA_PCS_PMA_XPON_CDR_PD_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB | + AIROHA_PCS_PMA_XPON_RX_FE_PWDB); + + /* FIXME: Ask Airoha WHY it's cleared? */ + /* regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, + * AIROHA_PCS_ANA_RX_FE_50OHMS_SEL); + */ + + /* Setup SigDet */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH, + AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL | + AIROHA_PCS_ANA_RX_SIGDET_PEAK, + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL, sigdet_vth_sel) | + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_PEAK, BIT(1))); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_DAC_RANGE, + AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, + FIELD_PREP(AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL, BIT(1) | BIT(0))); + + /* Disable SigDet Pwdb */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1, + AIROHA_PCS_PMA_RX_SIDGET_PWDB); + + /* Setup PHYCK */ + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV, + AIROHA_PCS_ANA_RX_TDC_CK_SEL | + AIROHA_PCS_ANA_RX_PHYCK_RSTB | + AIROHA_PCS_ANA_RX_PHYCK_SEL | + AIROHA_PCS_ANA_RX_PHYCK_DIV, + AIROHA_PCS_ANA_RX_PHYCK_RSTB | + FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_SEL, phyck_sel) | + FIELD_PREP(AIROHA_PCS_ANA_RX_PHYCK_DIV, phyck_div)); + + regmap_update_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_RX_BUSBIT_SEL, + AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE | + AIROHA_PCS_ANA_RX_PHY_CK_SEL, + AIROHA_PCS_ANA_RX_PHY_CK_SEL_FORCE); + + udelay(100); + + /* Enable CDR xxx Pwdb */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PIEYE_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PD_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PD_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_FE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B, + AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0, + AIROHA_PCS_PMA_XPON_CDR_PD_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB | + AIROHA_PCS_PMA_XPON_CDR_PW_PWDB | + AIROHA_PCS_PMA_XPON_RX_FE_PWDB); + + /* Enable SigDet Pwdb */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_DA_XPON_PWDB_1, + AIROHA_PCS_PMA_RX_SIDGET_PWDB); +} + +static unsigned int an7581_pcs_apply_cdr_pr_idac(struct airoha_pcs_priv *priv, + u32 cdr_pr_idac) +{ + u32 val; + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC, + FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC, + cdr_pr_idac)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_FREQLOCK_DET_EN, + AIROHA_PCS_PMA_FREQLOCK_DET_EN_FORCE_0); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_FREQLOCK_DET_EN, + AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL); + + udelay(5000); + + regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val); + + return FIELD_GET(AIROHA_PCS_PMA_FL_OUT, val); +} + +static u32 an7581_pcs_rx_prcal_idac_major(struct airoha_pcs_priv *priv, + u32 target_fl_out) +{ + unsigned int fl_out_diff = UINT_MAX; + unsigned int prcal_search; + u32 cdr_pr_idac = 0; + + for (prcal_search = 0; prcal_search < 8 ; prcal_search++) { + unsigned int fl_out_diff_new; + unsigned int fl_out; + u32 cdr_pr_idac_tmp; + + /* try to find the upper value by setting the last 3 bit */ + cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + prcal_search); + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new = abs(fl_out - target_fl_out); + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new < fl_out_diff) { + cdr_pr_idac = cdr_pr_idac_tmp; + fl_out_diff = fl_out_diff_new; + } + } + + return cdr_pr_idac; +} + +static u32 an7581_pcs_rx_prcal_idac_minor(struct airoha_pcs_priv *priv, u32 target_fl_out, + u32 cdr_pr_idac_major) +{ + unsigned int remaining_prcal_search_bits = 0; + u32 cdr_pr_idac = cdr_pr_idac_major; + unsigned int fl_out, fl_out_diff; + int best_prcal_search_bit = -1; + int prcal_search_bit; + + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac); + fl_out_diff = abs(fl_out - target_fl_out); + + /* Deadline search part. + * We start from top bits to bottom as we progressively decrease the + * signal. + */ + for (prcal_search_bit = 7; prcal_search_bit >= 0; prcal_search_bit--) { + unsigned int fl_out_diff_new; + u32 cdr_pr_idac_tmp; + + cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit); + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new = abs(fl_out - target_fl_out); + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new < fl_out_diff) { + best_prcal_search_bit = prcal_search_bit; + fl_out_diff = fl_out_diff_new; + } + } + + /* Set the idac with the best value we found and + * reset the search bit to start from bottom to top. + */ + if (best_prcal_search_bit >= 0) { + cdr_pr_idac |= BIT(best_prcal_search_bit); + remaining_prcal_search_bits = best_prcal_search_bit; + prcal_search_bit = 0; + } + + /* Fine tune part. + * Test remaining bits to find an even closer signal level to target + * by increasing the signal. + */ + while (remaining_prcal_search_bits) { + unsigned int fl_out_diff_new; + u32 cdr_pr_idac_tmp; + + cdr_pr_idac_tmp = cdr_pr_idac | BIT(prcal_search_bit); + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + + /* Use absolute values to find the closest one to target */ + fl_out_diff_new = abs(fl_out - target_fl_out); + /* Assume we found the deadline when the new absolue signal difference + * from target is greater than the previous and the difference is at + * least 10% greater between the old and new value. + * This is to account for signal detection level tollerance making + * sure we are actually over a deadline (AKA we are getting farther + * from target) + */ + dev_dbg(priv->dev, "Tested CDR Pr Idac: %x Fl Out: %x Diff: %u\n", + cdr_pr_idac_tmp, fl_out, fl_out_diff_new); + if (fl_out_diff_new > fl_out_diff && + (abs(fl_out_diff_new - fl_out_diff) * 100) / fl_out_diff > 10) { + /* Exit early if we are already at the deadline */ + if (prcal_search_bit == 0) + break; + + /* We found the deadline, set the value to the previous + * bit, and reset the loop to fine tune with the + * remaining values. + */ + cdr_pr_idac |= BIT(prcal_search_bit - 1); + remaining_prcal_search_bits = prcal_search_bit - 1; + prcal_search_bit = 0; + } else { + /* Update the signal level diff and try the next bit */ + fl_out_diff = fl_out_diff_new; + + /* If we didn't found the deadline, set the last bit + * and reset the loop to fine tune with the remainig + * values. + */ + if (prcal_search_bit == remaining_prcal_search_bits - 1) { + cdr_pr_idac |= BIT(prcal_search_bit); + remaining_prcal_search_bits = prcal_search_bit; + prcal_search_bit = 0; + } else { + prcal_search_bit++; + } + } + } + + return cdr_pr_idac; +} + +static void an7581_pcs_rx_prcal(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + u32 cdr_pr_idac_major, cdr_pr_idac; + unsigned int fl_out, fl_out_diff; + + u32 target_fl_out; + u32 cyclecnt; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: /* DS_1.25G / US_1.25G */ + case PHY_INTERFACE_MODE_1000BASEX: + target_fl_out = 0xa3d6; + cyclecnt = 32767; + break; + case PHY_INTERFACE_MODE_2500BASEX: /* DS_9.95328G / US_9.95328G */ + target_fl_out = 0xa000; + cyclecnt = 20000; + break; + case PHY_INTERFACE_MODE_USXGMII: /* DS_10.3125G / US_1.25G */ + case PHY_INTERFACE_MODE_10GBASER: + target_fl_out = 0x9edf; + cyclecnt = 32767; + break; + default: + return; + } + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_REF_RST_N); + + udelay(100); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_2, + AIROHA_PCS_PMA_LOCK_TARGET_END | + AIROHA_PCS_PMA_LOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_END, target_fl_out + 100) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_TARGET_BEG, target_fl_out - 100)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_1, + AIROHA_PCS_PMA_UNLOCK_CYCLECNT | + AIROHA_PCS_PMA_LOCK_CYCLECNT, + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_CYCLECNT, cyclecnt) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_CYCLECNT, cyclecnt)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_4, + AIROHA_PCS_PMA_LOCK_UNLOCKTH | + AIROHA_PCS_PMA_LOCK_LOCKTH, + FIELD_PREP(AIROHA_PCS_PMA_LOCK_UNLOCKTH, 3) | + FIELD_PREP(AIROHA_PCS_PMA_LOCK_LOCKTH, 3)); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SS_RX_FREQ_DET_3, + AIROHA_PCS_PMA_UNLOCK_TARGET_END | + AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_END, target_fl_out + 100) | + FIELD_PREP(AIROHA_PCS_PMA_UNLOCK_TARGET_BEG, target_fl_out - 100)); + + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, + AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_LPF_R_EN | + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + /* Calibration logic: + * First check the major value by looping with every + * value in the last 3 bit of CDR_PR_IDAC. + * Get the signal level and save the value that is closer to + * the target. + * + * Then check each remaining 7 bits in search of the deadline + * where the signal gets farther than signal target. + * + * Finally fine tune for the remaining bits to find the one that + * produce the closest signal level. + */ + cdr_pr_idac_major = an7581_pcs_rx_prcal_idac_major(priv, target_fl_out); + + cdr_pr_idac = an7581_pcs_rx_prcal_idac_minor(priv, target_fl_out, cdr_pr_idac_major); + + fl_out = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac); + fl_out_diff = abs(fl_out - target_fl_out); + if (fl_out_diff > 100) { + u32 pr_idac_major = FIELD_GET(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + cdr_pr_idac_major); + unsigned int fl_out_tmp, fl_out_diff_tmp; + u32 cdr_pr_idac_tmp; + + if (pr_idac_major > 0) { + cdr_pr_idac_tmp = FIELD_PREP(AIROHA_PCS_PMA_FORCE_CDR_PR_IDAC_MAJOR, + pr_idac_major - 1); + + dev_dbg(priv->dev, "Fl Out is %d far from target %d with Pr Idac %x. Trying with Pr Idac %x.\n", + fl_out_diff, target_fl_out, cdr_pr_idac_major, cdr_pr_idac_tmp); + + cdr_pr_idac_tmp = an7581_pcs_rx_prcal_idac_minor(priv, target_fl_out, + cdr_pr_idac_tmp); + + fl_out_tmp = an7581_pcs_apply_cdr_pr_idac(priv, cdr_pr_idac_tmp); + fl_out_diff_tmp = abs(fl_out_tmp - target_fl_out); + if (fl_out_diff_tmp < fl_out_diff) { + fl_out = fl_out_tmp; + fl_out_diff = fl_out_diff_tmp; + cdr_pr_idac = cdr_pr_idac_tmp; + } + } + } + dev_dbg(priv->dev, "Selected CDR Pr Idac: %x Fl Out: %x\n", cdr_pr_idac, fl_out); + if (fl_out_diff > 100) + dev_dbg(priv->dev, "Fl Out is %d far from target %d on intermediate calibration.\n", + fl_out_diff, target_fl_out); + + + /* Setup Load Band */ + regmap_clear_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CDR_PR_INJ_MODE, + AIROHA_PCS_ANA_CDR_PR_INJ_FORCE_OFF); + + /* Disable force of LPF C previously enabled */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_LPF_C_EN, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_LPF_C_EN); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_IDAC, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_B, + AIROHA_PCS_PMA_LOAD_EN); + + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_RX_FLL_1, + AIROHA_PCS_PMA_LPATH_IDAC, + FIELD_PREP(AIROHA_PCS_PMA_LPATH_IDAC, cdr_pr_idac)); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_DA_CDR_PR_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_PR_PIEYE_PWDB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_PWDB); + + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_REF_RST_N); + + udelay(100); +} + +/* This is used to both calibrate and lock to signal (after a previous + * calibration) after a global reset. + */ +static void an7581_pcs_cdr_reset(struct airoha_pcs_priv *priv, + phy_interface_t interface, bool calibrate) +{ + /* Setup LPF L2D force and disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA | + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA); + + /* Calibrate IDAC and setup Load Band */ + if (calibrate) + an7581_pcs_rx_prcal(priv, interface); + + /* Setup LPF RSTB force and disable */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB | + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB); + + udelay(700); + + /* Force Enable LPF RSTB */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_RSTB); + + udelay(100); + + /* Force Enable LPF L2D */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_DA_CDR_LPF_LCK2DATA); + + /* Disable LPF RSTB force bit */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_RSTB); + + /* Disable LPF L2D force bit */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_PXP_CDR_LPF_LCK_2DATA, + AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_LPF_LCK2DATA); +} + +static int an7581_pcs_phya_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + int calibration_try = 0; + u32 val; + + an7581_pcs_tx_bringup(priv, interface); + an7581_pcs_rx_bringup(priv, interface); + + udelay(100); + +retry_calibration: + an7581_pcs_cdr_reset(priv, interface, priv->manual_rx_calib); + + /* Global reset clear */ + regmap_update_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N | + AIROHA_PCS_PMA_SW_REF_RST_N | + AIROHA_PCS_PMA_SW_ALLPCS_RST_N | + AIROHA_PCS_PMA_SW_PMA_RST_N | + AIROHA_PCS_PMA_SW_TX_RST_N | + AIROHA_PCS_PMA_SW_RX_RST_N | + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N, + AIROHA_PCS_PMA_SW_REF_RST_N); + + udelay(100); + + /* Global reset */ + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N | + AIROHA_PCS_PMA_SW_XFI_RXPCS_RST_N | + AIROHA_PCS_PMA_SW_XFI_TXPCS_RST_N | + AIROHA_PCS_PMA_SW_TX_FIFO_RST_N | + AIROHA_PCS_PMA_SW_REF_RST_N | + AIROHA_PCS_PMA_SW_ALLPCS_RST_N | + AIROHA_PCS_PMA_SW_PMA_RST_N | + AIROHA_PCS_PMA_SW_TX_RST_N | + AIROHA_PCS_PMA_SW_RX_RST_N | + AIROHA_PCS_PMA_SW_RX_FIFO_RST_N); + + udelay(5000); + + an7581_pcs_cdr_reset(priv, interface, false); + + /* Manual RX calibration is required only for SoC before E2 + * revision. E2+ SoC autocalibrate RX and only CDR reset is needed. + */ + if (!priv->manual_rx_calib) + return 0; + + /* It was discovered that after a global reset and auto mode gets + * actually enabled, the fl_out from calibration might change and + * might deviates a lot from the expected value it was calibrated for. + * To correctly work, the PCS FreqDet module needs to Lock to the fl_out + * (frequency level output) or no signal can correctly be transmitted. + * This is detected by checking the FreqDet module Lock bit. + * + * If it's detected that the FreqDet module is not locked, retry + * calibration. From observation on real hardware with a 10g SFP module, + * it required a maximum of an additional calibration to actually make + * the FreqDet module to lock. Try 10 times before failing to handle + * really strange case. + */ + regmap_read(priv->xfi_pma, AIROHA_PCS_PMA_RX_FREQDET, &val); + if (!(val & AIROHA_PCS_PMA_FBCK_LOCK)) { + if (calibration_try > AIROHA_PCS_MAX_CALIBRATION_TRY) { + dev_err(priv->dev, "No FBCK Lock from FreqDet module after %d calibration try. PCS won't work.\n", + AIROHA_PCS_MAX_CALIBRATION_TRY); + return -EIO; + } + + calibration_try++; + + dev_dbg(priv->dev, "No FBCK Lock from FreqDet module, retry calibration.\n"); + goto retry_calibration; + } + + return 0; +} + +static void an7581_pcs_pll_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + an7581_pcs_jcpll_bringup(priv, interface); + + udelay(200); + + an7581_pcs_txpll_bringup(priv, interface); + + udelay(200); +} + +int an7581_pcs_bringup(struct airoha_pcs_priv *priv, + phy_interface_t interface) +{ + /* Enable Analog Common Lane */ + regmap_set_bits(priv->xfi_ana, AIROHA_PCS_ANA_PXP_CMN_EN, + AIROHA_PCS_ANA_CMN_EN); + + /* Setup PLL */ + an7581_pcs_pll_bringup(priv, interface); + + /* Setup PHYA */ + return an7581_pcs_phya_bringup(priv, interface); +} + +void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv) +{ + /* Reset TXPCS on link up */ + regmap_clear_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N); + + udelay(100); + + regmap_set_bits(priv->xfi_pma, AIROHA_PCS_PMA_SW_RST_SET, + AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N); +} diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c index 3a0ac7ce368..84ee9b2ad76 100644 --- a/drivers/net/airoha_eth.c +++ b/drivers/net/airoha_eth.c @@ -9,9 +9,11 @@ */ #include +#include #include #include #include +#include #include #include #include @@ -19,12 +21,15 @@ #include #include #include +#include #include #include #include #include -#define AIROHA_MAX_NUM_GDM_PORTS 1 +#include "airoha/pcs-airoha.h" + +#define AIROHA_MAX_NUM_GDM_PORTS 4 #define AIROHA_MAX_NUM_QDMA 1 #define AIROHA_MAX_NUM_RSTS 3 #define AIROHA_MAX_NUM_XSI_RSTS 4 @@ -38,6 +43,8 @@ #define TX_DSCP_NUM 16 #define RX_DSCP_NUM PKTBUFSRX +#define AIROHA_GDM_PORT_STRING_LEN sizeof("airoha-gdmX") + /* SCU */ #define SCU_SHARE_FEMEM_SEL 0x958 @@ -246,6 +253,21 @@ #define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16) #define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0) +enum { + FE_PSE_PORT_CDM1, + FE_PSE_PORT_GDM1, + FE_PSE_PORT_GDM2, + FE_PSE_PORT_GDM3, + FE_PSE_PORT_PPE1, + FE_PSE_PORT_CDM2, + FE_PSE_PORT_CDM3, + FE_PSE_PORT_CDM4, + FE_PSE_PORT_PPE2, + FE_PSE_PORT_GDM4, + FE_PSE_PORT_CDM5, + FE_PSE_PORT_DROP = 0xf, +}; + struct airoha_qdma_desc { __le32 rsv; __le32 ctrl; @@ -301,20 +323,30 @@ struct airoha_qdma { struct airoha_gdm_port { struct airoha_qdma *qdma; int id; + + struct udevice *pcs_dev; + phy_interface_t mode; + bool neg_mode; + + struct phy_device *phydev; }; struct airoha_eth { void __iomem *fe_regs; void __iomem *switch_regs; + struct udevice *switch_mdio_dev; struct reset_ctl_bulk rsts; struct reset_ctl_bulk xsi_rsts; + struct airoha_eth_soc_data *soc; + struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; - struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; + char gdm_port_str[AIROHA_MAX_NUM_GDM_PORTS + 1][AIROHA_GDM_PORT_STRING_LEN]; }; struct airoha_eth_soc_data { + u32 version; int num_xsi_rsts; const char * const *xsi_rsts_names; const char *switch_compatible; @@ -397,22 +429,33 @@ static inline void dma_unmap_unaligned(dma_addr_t addr, size_t len, dma_unmap_single(start, end - start, dir); } -static void airoha_fe_maccr_init(struct airoha_eth *eth) +static int airoha_get_fe_port(struct airoha_gdm_port *port) { - int p; + struct airoha_qdma *qdma = port->qdma; + struct airoha_eth *eth = qdma->eth; - for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) { - /* - * Disable any kind of CRC drop or offload. - * Enable padding of short TX packets to 60 bytes. - */ - airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), GDM_PAD_EN); + switch (eth->soc->version) { + case 0x7523: + /* FIXME: GDM1 is the only supported port */ + return FE_PSE_PORT_GDM1; + case 0x7581: + default: + return port->id == 4 ? FE_PSE_PORT_GDM4 : port->id; } } -static int airoha_fe_init(struct airoha_eth *eth) +static void airoha_fe_maccr_init(struct airoha_gdm_port *port) { - airoha_fe_maccr_init(eth); + /* + * Disable any kind of CRC drop or offload. + * Enable padding of short TX packets to 60 bytes. + */ + airoha_fe_wr(port->qdma->eth, REG_GDM_FWD_CFG(port->id), GDM_PAD_EN); +} + +static int airoha_fe_init(struct airoha_gdm_port *port) +{ + airoha_fe_maccr_init(port); return 0; } @@ -662,6 +705,36 @@ static int airoha_qdma_init(struct udevice *dev, return airoha_qdma_hw_init(qdma); } +#if defined(CONFIG_PCS_AIROHA) +static int airoha_pcs_init(struct udevice *dev) +{ + struct airoha_gdm_port *port = dev_get_priv(dev); + struct udevice *pcs_dev; + const char *managed; + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_MISC, dev, "pcs", + &pcs_dev); + if (ret || !pcs_dev) + return ret; + + port->pcs_dev = pcs_dev; + port->mode = dev_read_phy_mode(dev); + managed = dev_read_string(dev, "managed"); + port->neg_mode = !strncmp(managed, "in-band-status", + sizeof("in-band-status")); + + airoha_pcs_pre_config(pcs_dev, port->mode); + + ret = airoha_pcs_post_config(pcs_dev, port->mode); + if (ret) + return ret; + + return airoha_pcs_config(pcs_dev, port->neg_mode, + port->mode, NULL, true); +} +#endif + static int airoha_hw_init(struct udevice *dev, struct airoha_eth *eth) { @@ -682,12 +755,12 @@ static int airoha_hw_init(struct udevice *dev, if (ret) return ret; - mdelay(20); - - ret = airoha_fe_init(eth); + ret = reset_deassert_bulk(ð->xsi_rsts); if (ret) return ret; + mdelay(20); + for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { ret = airoha_qdma_init(dev, eth, ð->qdma[i]); if (ret) @@ -739,11 +812,45 @@ static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth) return 0; } +static int airoha_alloc_gdm_port(struct udevice *dev, ofnode node) +{ + struct airoha_eth *eth = dev_get_priv(dev); + struct udevice *gdm_dev; + struct driver *gdm_drv; + char *str; + int ret; + u32 id; + + gdm_drv = lists_driver_lookup_name("airoha-eth-port"); + if (!gdm_drv) + return -ENOENT; + + ret = ofnode_read_u32(node, "reg", &id); + if (ret) + return ret; + + if (id > AIROHA_MAX_NUM_GDM_PORTS) + return -EINVAL; + +#if !defined(CONFIG_PCS_AIROHA) + if (id != 1) + return -ENOTSUPP; +#endif + + str = eth->gdm_port_str[id]; + snprintf(str, AIROHA_GDM_PORT_STRING_LEN, + "airoha-gdm%d", id); + + return device_bind_with_driver_data(dev, gdm_drv, str, + (ulong)eth, node, &gdm_dev); +} + static int airoha_eth_probe(struct udevice *dev) { struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev); struct airoha_eth *eth = dev_get_priv(dev); struct regmap *scu_regmap; + ofnode node; int i, ret; scu_regmap = airoha_get_scu_regmap(); @@ -756,6 +863,8 @@ static int airoha_eth_probe(struct udevice *dev) */ regmap_write(scu_regmap, SCU_SHARE_FEMEM_SEL, 0x0); + eth->soc = data; + eth->fe_regs = dev_remap_addr_name(dev, "fe"); if (!eth->fe_regs) return -ENOMEM; @@ -795,13 +904,68 @@ static int airoha_eth_probe(struct udevice *dev) if (ret) return ret; - return airoha_switch_init(dev, eth); + ret = airoha_switch_init(dev, eth); + if (ret) + return ret; + + if (eth->switch_mdio_dev) { + if (!device_probe(eth->switch_mdio_dev)) + debug("Warning: failed to probe airoha switch mdio\n"); + } + + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (!ofnode_device_is_compatible(node, "airoha,eth-mac")) + continue; + + if (!ofnode_is_enabled(node)) + continue; + + ret = airoha_alloc_gdm_port(dev, node); + if (ret && ret != -ENOTSUPP) + return ret; + } + + return 0; +} + +static int airoha_eth_port_of_to_plat(struct udevice *dev) +{ + struct airoha_gdm_port *port = dev_get_priv(dev); + + return dev_read_u32(dev, "reg", &port->id); +} + +static int airoha_eth_port_probe(struct udevice *dev) +{ + struct airoha_eth *eth = (void *)dev_get_driver_data(dev); + struct airoha_gdm_port *port = dev_get_priv(dev); + int ret; + + port->qdma = ð->qdma[0]; + + ret = airoha_fe_init(port); + if (ret) + return ret; + + if (port->id > 1) { +#if defined(CONFIG_PCS_AIROHA) + ret = airoha_pcs_init(dev); + if (ret) + return ret; + + port->phydev = dm_eth_phy_connect(dev); +#else + return -EINVAL; +#endif + } + + return 0; } static int airoha_eth_init(struct udevice *dev) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_queue *q; int qid; @@ -814,13 +978,65 @@ static int airoha_eth_init(struct udevice *dev) GLOBAL_CFG_TX_DMA_EN_MASK | GLOBAL_CFG_RX_DMA_EN_MASK); +#if defined(CONFIG_PCS_AIROHA) + if (port->id > 1) { + struct phy_device *phydev = port->phydev; + int speed, duplex; + int ret; + + if (phydev) { + ret = phy_config(phydev); + if (ret) + return ret; + + ret = phy_startup(phydev); + if (ret) + return ret; + + speed = phydev->speed; + duplex = phydev->duplex; + } else { + duplex = DUPLEX_FULL; + + /* Hardcode speed for linkup */ + switch (port->mode) { + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + speed = SPEED_10000; + break; + case PHY_INTERFACE_MODE_2500BASEX: + speed = SPEED_2500; + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + speed = SPEED_1000; + break; + default: + return -EINVAL; + } + } + + airoha_pcs_link_up(port->pcs_dev, port->neg_mode, port->mode, + speed, duplex); + } +#endif + return 0; } static void airoha_eth_stop(struct udevice *dev) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; + +#if defined(CONFIG_PCS_AIROHA) + if (port->id > 1) { + if (port->phydev) + phy_shutdown(port->phydev); + + airoha_pcs_link_down(port->pcs_dev); + } +#endif airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, GLOBAL_CFG_TX_DMA_EN_MASK | @@ -829,8 +1045,8 @@ static void airoha_eth_stop(struct udevice *dev) static int airoha_eth_send(struct udevice *dev, void *packet, int length) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_qdma_desc *desc; struct airoha_queue *q; dma_addr_t dma_addr; @@ -852,7 +1068,7 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length) desc = &q->desc[q->head]; index = (q->head + 1) % q->ndesc; - fport = 1; + fport = airoha_get_fe_port(port); msg0 = 0; msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | @@ -894,8 +1110,8 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length) static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_qdma_desc *desc; struct airoha_queue *q; u16 length; @@ -922,8 +1138,8 @@ static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp) static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) { - struct airoha_eth *eth = dev_get_priv(dev); - struct airoha_qdma *qdma = ð->qdma[0]; + struct airoha_gdm_port *port = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; struct airoha_queue *q; int qid; @@ -964,8 +1180,9 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) static int arht_eth_write_hwaddr(struct udevice *dev) { + struct airoha_gdm_port *port = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); - struct airoha_eth *eth = dev_get_priv(dev); + struct airoha_qdma *qdma = port->qdma; unsigned char *mac = pdata->enetaddr; u32 macaddr_lsb, macaddr_msb; @@ -977,8 +1194,8 @@ static int arht_eth_write_hwaddr(struct udevice *dev) FIELD_PREP(SMACCR1_MAC0, mac[0]); /* Set MAC for Switch */ - airoha_switch_wr(eth, SWITCH_SMACCR0, macaddr_lsb); - airoha_switch_wr(eth, SWITCH_SMACCR1, macaddr_msb); + airoha_switch_wr(qdma->eth, SWITCH_SMACCR0, macaddr_lsb); + airoha_switch_wr(qdma->eth, SWITCH_SMACCR1, macaddr_msb); return 0; } @@ -986,9 +1203,15 @@ static int arht_eth_write_hwaddr(struct udevice *dev) static int airoha_eth_bind(struct udevice *dev) { struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev); + struct airoha_eth *eth = dev_get_priv(dev); ofnode switch_node, mdio_node; - struct udevice *mdio_dev; - int ret = 0; + int ret; + + /* + * Force Probe as we set the Main ETH driver as misc + * to register multiple eth port for each GDM + */ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); if (!CONFIG_IS_ENABLED(MDIO_MT7531_MMIO)) return 0; @@ -1006,8 +1229,8 @@ static int airoha_eth_bind(struct udevice *dev) return 0; } - ret = device_bind_driver_to_node(dev, "mt7531-mdio-mmio", "mdio", - mdio_node, &mdio_dev); + ret = device_bind_driver_to_node(dev, "mt7531-mdio-mmio", "mt7531-mdio", + mdio_node, ð->switch_mdio_dev); if (ret) debug("Warning: failed to bind mdio controller\n"); @@ -1015,12 +1238,14 @@ static int airoha_eth_bind(struct udevice *dev) } static const struct airoha_eth_soc_data en7523_data = { + .version = 0x7523, .xsi_rsts_names = en7523_xsi_rsts_names, .num_xsi_rsts = ARRAY_SIZE(en7523_xsi_rsts_names), .switch_compatible = "airoha,en7523-switch", }; static const struct airoha_eth_soc_data en7581_data = { + .version = 0x7581, .xsi_rsts_names = en7581_xsi_rsts_names, .num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names), .switch_compatible = "airoha,en7581-switch", @@ -1045,13 +1270,21 @@ static const struct eth_ops airoha_eth_ops = { .write_hwaddr = arht_eth_write_hwaddr, }; +U_BOOT_DRIVER(airoha_eth_port) = { + .name = "airoha-eth-port", + .id = UCLASS_ETH, + .of_to_plat = airoha_eth_port_of_to_plat, + .probe = airoha_eth_port_probe, + .ops = &airoha_eth_ops, + .priv_auto = sizeof(struct airoha_gdm_port), + .plat_auto = sizeof(struct eth_pdata), +}; + U_BOOT_DRIVER(airoha_eth) = { .name = "airoha-eth", - .id = UCLASS_ETH, + .id = UCLASS_MISC, .of_match = airoha_eth_ids, .probe = airoha_eth_probe, .bind = airoha_eth_bind, - .ops = &airoha_eth_ops, .priv_auto = sizeof(struct airoha_eth), - .plat_auto = sizeof(struct eth_pdata), }; diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig index 6ff3ffa137b..e25ed479678 100644 --- a/drivers/net/bnxt/Kconfig +++ b/drivers/net/bnxt/Kconfig @@ -1,6 +1,6 @@ config BNXT_ETH bool "BNXT PCI support" - select PCI_INIT_R + depends on PCI help This driver implements support for bnxt pci controller driver of ethernet class. diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 8a396d0b29e..0f31d646845 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1620,6 +1620,10 @@ static const struct udevice_id eqos_ids[] = { }, #endif #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP) + { + .compatible = "rockchip,rk3506-gmac", + .data = (ulong)&eqos_rockchip_config + }, { .compatible = "rockchip,rk3528-gmac", .data = (ulong)&eqos_rockchip_config diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index d646d3ebac8..4ccefda0ef5 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -50,6 +50,80 @@ struct rockchip_platform_data { (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) +#define RK3506_GRF_SOC_CON8 0x0020 +#define RK3506_GRF_SOC_CON11 0x002c + +#define RK3506_GMAC_RMII_MODE GRF_BIT(1) + +#define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3) +#define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3) + +#define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5) +#define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5) + +#define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2) +#define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2) + +static int rk3506_set_to_rgmii(struct udevice *dev, + int tx_delay, int rx_delay) +{ + return -EINVAL; +} + +static int rk3506_set_to_rmii(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 reg; + + reg = data->id == 1 ? RK3506_GRF_SOC_CON11 : + RK3506_GRF_SOC_CON8; + regmap_write(data->grf, reg, RK3506_GMAC_RMII_MODE); + + return 0; +} + +static int rk3506_set_gmac_speed(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 val, reg; + + switch (eqos->phy->speed) { + case SPEED_10: + val = RK3506_GMAC_CLK_RMII_DIV20; + break; + case SPEED_100: + val = RK3506_GMAC_CLK_RMII_DIV2; + break; + default: + return -EINVAL; + } + + reg = data->id == 1 ? RK3506_GRF_SOC_CON11 : + RK3506_GRF_SOC_CON8; + regmap_write(data->grf, reg, val); + + return 0; +} + +static void rk3506_set_clock_selection(struct udevice *dev, bool enable) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct rockchip_platform_data *data = pdata->priv_pdata; + u32 val, reg; + + val = data->clock_input ? RK3506_GMAC_CLK_SELECT_IO : + RK3506_GMAC_CLK_SELECT_CRU; + val |= enable ? RK3506_GMAC_CLK_RMII_NOGATE : + RK3506_GMAC_CLK_RMII_GATE; + + reg = data->id == 1 ? RK3506_GRF_SOC_CON11 : + RK3506_GRF_SOC_CON8; + regmap_write(data->grf, reg, val); +} + #define RK3528_VO_GRF_GMAC_CON 0x0018 #define RK3528_VPU_GRF_GMAC_CON5 0x0018 #define RK3528_VPU_GRF_GMAC_CON6 0x001c @@ -534,6 +608,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable) } static const struct rk_gmac_ops rk_gmac_ops[] = { + { + .compatible = "rockchip,rk3506-gmac", + .set_to_rgmii = rk3506_set_to_rgmii, + .set_to_rmii = rk3506_set_to_rmii, + .set_gmac_speed = rk3506_set_gmac_speed, + .set_clock_selection = rk3506_set_clock_selection, + .regs = { + 0xff4c8000, /* gmac0 */ + 0xff4d0000, /* gmac1 */ + 0x0, /* sentinel */ + }, + }, { .compatible = "rockchip,rk3528-gmac", .set_to_rgmii = rk3528_set_to_rgmii, diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c index 458b87af7a2..2ab5ec5f0d9 100644 --- a/drivers/net/dwc_eth_xgmac.c +++ b/drivers/net/dwc_eth_xgmac.c @@ -497,20 +497,6 @@ static int xgmac_start(struct udevice *dev) xgmac->reg_access_ok = true; - ret = wait_for_bit_le32(&xgmac->dma_regs->mode, - XGMAC_DMA_MODE_SWR, false, - xgmac->config->swr_wait, false); - if (ret) { - pr_err("%s XGMAC_DMA_MODE_SWR stuck: %d\n", dev->name, ret); - goto err_stop_resets; - } - - ret = xgmac->config->ops->xgmac_calibrate_pads(dev); - if (ret < 0) { - pr_err("%s xgmac_calibrate_pads() failed: %d\n", dev->name, ret); - goto err_stop_resets; - } - /* * if PHY was already connected and configured, * don't need to reconnect/reconfigure again @@ -559,6 +545,20 @@ static int xgmac_start(struct udevice *dev) goto err_shutdown_phy; } + ret = wait_for_bit_le32(&xgmac->dma_regs->mode, + XGMAC_DMA_MODE_SWR, false, + xgmac->config->swr_wait, false); + if (ret) { + pr_err("%s XGMAC_DMA_MODE_SWR stuck: %d\n", dev->name, ret); + goto err_stop_resets; + } + + ret = xgmac->config->ops->xgmac_calibrate_pads(dev); + if (ret < 0) { + pr_err("%s xgmac_calibrate_pads() failed: %d\n", dev->name, ret); + goto err_stop_resets; + } + /* Configure MTL */ /* Enable Store and Forward mode for TX */ diff --git a/drivers/net/dwmac_s700.c b/drivers/net/dwmac_s700.c index 969d247b4f3..76daab961c0 100644 --- a/drivers/net/dwmac_s700.c +++ b/drivers/net/dwmac_s700.c @@ -5,7 +5,6 @@ * Actions DWMAC specific glue layer */ -#include #include #include #include @@ -24,8 +23,6 @@ #define RMII_REF_CLK_MFP_CTL0 (0x0 << 6) #define CLKO_25M_EN_MFP_CTL3 BIT(30) -DECLARE_GLOBAL_DATA_PTR; - static void dwmac_board_setup(void) { clrbits_le32(MFP_CTL0, (RMII_TXD01_MFP_CTL0 | RMII_RXD01_MFP_CTL0 | diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1c51e936b5b..3d32bad0831 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include @@ -36,8 +35,6 @@ #include "fec_mxc.h" #include -DECLARE_GLOBAL_DATA_PTR; - /* * Timeout the transfer after 5 mS. This is usually a bit more, since * the code in the tightloops this timeout is used in adds some overhead. diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c8cfe7448d4..2b6080dd9ee 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -28,7 +27,6 @@ #include #include "designware.h" -DECLARE_GLOBAL_DATA_PTR; #define DELAY_ENABLE(soc, tx, rx) \ (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \ ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE)) diff --git a/drivers/net/mdio-mt7531-mmio.c b/drivers/net/mdio-mt7531-mmio.c index 5a0725010f2..930454a9b0e 100644 --- a/drivers/net/mdio-mt7531-mmio.c +++ b/drivers/net/mdio-mt7531-mmio.c @@ -6,6 +6,8 @@ #include #include +#include "mdio-mt7531-mmio.h" + #define MT7531_PHY_IAC 0x701c #define MT7531_PHY_ACS_ST BIT(31) #define MT7531_MDIO_REG_ADDR_CL22 GENMASK(29, 25) @@ -25,11 +27,7 @@ #define MT7531_MDIO_TIMEOUT 100000 #define MT7531_MDIO_SLEEP 20 -struct mt7531_mdio_priv { - phys_addr_t switch_regs; -}; - -static int mt7531_mdio_wait_busy(struct mt7531_mdio_priv *priv) +static int mt7531_mdio_wait_busy(struct mt7531_mdio_mmio_priv *priv) { unsigned int busy; @@ -38,7 +36,7 @@ static int mt7531_mdio_wait_busy(struct mt7531_mdio_priv *priv) MT7531_MDIO_SLEEP, MT7531_MDIO_TIMEOUT); } -static int mt7531_mdio_read(struct mt7531_mdio_priv *priv, int addr, int devad, int reg) +static int mt7531_mdio_read(struct mt7531_mdio_mmio_priv *priv, int addr, int devad, int reg) { u32 val; @@ -75,7 +73,7 @@ static int mt7531_mdio_read(struct mt7531_mdio_priv *priv, int addr, int devad, return val & MT7531_MDIO_RW_DATA; } -static int mt7531_mdio_write(struct mt7531_mdio_priv *priv, int addr, int devad, +static int mt7531_mdio_write(struct mt7531_mdio_mmio_priv *priv, int addr, int devad, int reg, u16 value) { u32 val; @@ -115,7 +113,7 @@ static int mt7531_mdio_write(struct mt7531_mdio_priv *priv, int addr, int devad, int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg) { - struct mt7531_mdio_priv *priv = bus->priv; + struct mt7531_mdio_mmio_priv *priv = bus->priv; return mt7531_mdio_read(priv, addr, devad, reg); } @@ -123,14 +121,14 @@ int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg) int mt7531_mdio_mmio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 value) { - struct mt7531_mdio_priv *priv = bus->priv; + struct mt7531_mdio_mmio_priv *priv = bus->priv; return mt7531_mdio_write(priv, addr, devad, reg, value); } static int dm_mt7531_mdio_read(struct udevice *dev, int addr, int devad, int reg) { - struct mt7531_mdio_priv *priv = dev_get_priv(dev); + struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev); return mt7531_mdio_read(priv, addr, devad, reg); } @@ -138,7 +136,7 @@ static int dm_mt7531_mdio_read(struct udevice *dev, int addr, int devad, int reg static int dm_mt7531_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 value) { - struct mt7531_mdio_priv *priv = dev_get_priv(dev); + struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev); return mt7531_mdio_write(priv, addr, devad, reg, value); } @@ -150,7 +148,7 @@ static const struct mdio_ops mt7531_mdio_ops = { static int mt7531_mdio_probe(struct udevice *dev) { - struct mt7531_mdio_priv *priv = dev_get_priv(dev); + struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev); ofnode switch_node; switch_node = ofnode_get_parent(dev_ofnode(dev)); @@ -169,5 +167,5 @@ U_BOOT_DRIVER(mt7531_mdio) = { .id = UCLASS_MDIO, .probe = mt7531_mdio_probe, .ops = &mt7531_mdio_ops, - .priv_auto = sizeof(struct mt7531_mdio_priv), + .priv_auto = sizeof(struct mt7531_mdio_mmio_priv), }; diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 1640868c24a..baa18202d6e 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -37,8 +36,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define MVNETA_NR_CPUS 1 #define ETH_HLEN 14 /* Total octets in header */ diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c index 217bcac2ce2..5a822b64427 100644 --- a/drivers/net/octeontx/smi.c +++ b/drivers/net/octeontx/smi.c @@ -10,15 +10,12 @@ #include #include #include -#include #include #include #include #define PCI_DEVICE_ID_OCTEONTX_SMI 0xA02B -DECLARE_GLOBAL_DATA_PTR; - enum octeontx_smi_mode { CLAUSE22 = 0, CLAUSE45 = 1, diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 709f1c91eb2..5d2277a4602 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -91,6 +91,7 @@ menuconfig PHY_AQUANTIA config PHY_AQUANTIA_UPLOAD_FW bool "Aquantia firmware loading support" depends on PHY_AQUANTIA + depends on SUPPORTS_FW_LOADER select FW_LOADER help Aquantia PHYs use firmware which can be either loaded automatically diff --git a/drivers/net/phy/airoha/Kconfig b/drivers/net/phy/airoha/Kconfig index 999564e4848..da8747939e3 100644 --- a/drivers/net/phy/airoha/Kconfig +++ b/drivers/net/phy/airoha/Kconfig @@ -5,7 +5,8 @@ menuconfig PHY_AIROHA config PHY_AIROHA_EN8811 bool "Airoha Ethernet EN8811H support" depends on PHY_AIROHA + depends on SUPPORTS_FW_LOADER select FW_LOADER help AIROHA EN8811H supported. - + AIROHA AN8811HB supported. diff --git a/drivers/net/phy/airoha/air_en8811.c b/drivers/net/phy/airoha/air_en8811.c index 1a628ede82b..0b974472732 100644 --- a/drivers/net/phy/airoha/air_en8811.c +++ b/drivers/net/phy/airoha/air_en8811.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Driver for the Airoha EN8811H 2.5 Gigabit PHY. + * Driver for the Airoha EN8811H and AN8811HB 2.5 Gigabit PHY. * * Limitations of the EN8811H: * - Only full duplex supported @@ -8,9 +8,8 @@ * * Source originated from linux air_en8811h.c * - * Copyright (C) 2025 Airoha Technology Corp. + * Copyright (C) 2025, 2026 Airoha Technology Corp. */ - #include #include #include @@ -20,27 +19,15 @@ #include #include #include +#include #include #include #include -#define EN8811H_PHY_ID 0x03a2a411 - -#define AIR_FW_ADDR_DM 0x00000000 -#define AIR_FW_ADDR_DSP 0x00100000 - -#define EN8811H_MD32_DM_SIZE 0x4000 -#define EN8811H_MD32_DSP_SIZE 0x20000 - -#define EN8811H_FW_CTRL_1 0x0f0018 -#define EN8811H_FW_CTRL_1_START 0x0 -#define EN8811H_FW_CTRL_1_FINISH 0x1 -#define EN8811H_FW_CTRL_2 0x800000 -#define EN8811H_FW_CTRL_2_LOADING BIT(11) - /* MII Registers */ #define AIR_AUX_CTRL_STATUS 0x1d #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) +#define AIR_AUX_CTRL_STATUS_SPEED_10 0x0 #define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc @@ -49,6 +36,7 @@ #define AIR_PHY_PAGE_STANDARD 0x0000 #define AIR_PHY_PAGE_EXTENDED_4 0x0004 +#define AIR_PBUS_MODE_ADDR_HIGH 0x1c /* MII Registers Page 4 */ #define AIR_BPBUS_MODE 0x10 #define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 @@ -63,8 +51,16 @@ #define AIR_BPBUS_RD_DATA_LOW 0x18 /* Registers on MDIO_MMD_VEND1 */ -#define EN8811H_PHY_FW_STATUS 0x8009 -#define EN8811H_PHY_READY 0x02 +#define AIR_PHY_MCU_CMD_1 0x800c +#define AIR_PHY_MCU_CMD_1_MODE1 0x0 +#define AIR_PHY_MCU_CMD_2 0x800d +#define AIR_PHY_MCU_CMD_2_MODE1 0x0 +#define AIR_PHY_MCU_CMD_3 0x800e +#define AIR_PHY_MCU_CMD_3_MODE1 0x1101 +#define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 +#define AIR_PHY_MCU_CMD_4 0x800f +#define AIR_PHY_MCU_CMD_4_MODE1 0x0002 +#define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 /* Registers on MDIO_MMD_VEND2 */ #define AIR_PHY_LED_BCR 0x021 @@ -77,7 +73,7 @@ #define AIR_PHY_LED_DUR_BLINK 0x023 -#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2)) +#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2)) #define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8)) #define AIR_PHY_LED_ON_LINK1000 BIT(0) #define AIR_PHY_LED_ON_LINK100 BIT(1) @@ -90,7 +86,7 @@ #define AIR_PHY_LED_ON_POLARITY BIT(14) #define AIR_PHY_LED_ON_ENABLE BIT(15) -#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2)) +#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2)) #define AIR_PHY_LED_BLINK_1000TX BIT(0) #define AIR_PHY_LED_BLINK_1000RX BIT(1) #define AIR_PHY_LED_BLINK_100TX BIT(2) @@ -104,21 +100,101 @@ #define AIR_PHY_LED_BLINK_2500TX BIT(10) #define AIR_PHY_LED_BLINK_2500RX BIT(11) +/* Registers on BUCKPBUS */ +#define AIR_PHY_CONTROL 0x3a9c +#define AIR_PHY_CONTROL_SURGE_5R BIT(3) +#define AIR_PHY_CONTROL_INTERNAL BIT(11) + +/* Led definitions */ +#define EN8811H_LED_COUNT 3 + +/* Firmware registers */ +#define AIR_FW_ADDR_DM 0x00000000 +#define AIR_FW_ADDR_DSP 0x00100000 +#define EN8811H_FW_CTRL_1 0x0f0018 +#define EN8811H_FW_CTRL_1_START 0x0 +#define EN8811H_FW_CTRL_1_FINISH 0x1 +#define EN8811H_FW_CTRL_2 0x800000 +#define EN8811H_FW_CTRL_2_LOADING BIT(11) +#define EN8811H_PHY_FW_STATUS 0x8009 +#define EN8811H_PHY_READY 0x02 +#define AIR_PHY_FW_STATUS 0x8009 +#define AIR_PHY_READY 0x02 + +#define AIR_PHY_FW_CTRL_1 0x0f0018 +#define AIR_PHY_FW_CTRL_1_START 0x0 +#define AIR_PHY_FW_CTRL_1_FINISH 0x1 + +/* EN8811H */ +#define EN8811H_PHY_ID 0x03a2a411 +#define EN8811H_MD32_DM_SIZE 0x4000 +#define EN8811H_MD32_DSP_SIZE 0x20000 #define EN8811H_FW_VERSION 0x3b3c #define EN8811H_POLARITY 0xca0f8 #define EN8811H_POLARITY_TX_NORMAL BIT(0) #define EN8811H_POLARITY_RX_REVERSE BIT(1) - #define EN8811H_CLK_CGM 0xcf958 #define EN8811H_CLK_CGM_CKO BIT(26) #define EN8811H_HWTRAP1 0xcf914 #define EN8811H_HWTRAP1_CKO BIT(12) -#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap) +/* AN8811HB */ +#define AN8811HB_PHY_ID 0xc0ff04a0 +#define AIR_MD32_DM_SIZE 0x8000 +#define AIR_MD32_DSP_SIZE 0x20000 +#define AIR_PHY_MD32FW_VERSION 0x3b3c -/* Led definitions */ -#define EN8811H_LED_COUNT 3 +#define AN8811HB_GPIO_OUTPUT 0x5cf8b8 +#define AN8811HB_GPIO_OUTPUT_MASK GENMASK(15, 0) +#define AN8811HB_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) +#define AN8811HB_GPIO_OUTPUT_0115 (BIT(0) | BIT(1) | BIT(15)) +#define AN8811HB_GPIO_SEL_1 0x5cf8bc +#define AN8811HB_GPIO_SEL_1_0_MASK GENMASK(2, 0) +#define AN8811HB_GPIO_SEL_1_1_MASK GENMASK(6, 4) +#define AN8811HB_GPIO_SEL_1_0 FIELD_PREP(AN8811HB_GPIO_SEL_1_0_MASK, 1) +#define AN8811HB_GPIO_SEL_1_1 FIELD_PREP(AN8811HB_GPIO_SEL_1_1_MASK, 0) +#define AN8811HB_GPIO_SEL_2 0x5cf8c0 +#define AN8811HB_GPIO_SEL_2_15_MASK GENMASK(30, 28) +#define AN8811HB_GPIO_SEL_2_15 FIELD_PREP(AN8811HB_GPIO_SEL_2_15_MASK, 2) + +#define AN8811HB_CRC_PM_SET1 0xf020c +#define AN8811HB_CRC_PM_MON2 0xf0218 +#define AN8811HB_CRC_PM_MON3 0xf021c +#define AN8811HB_CRC_DM_SET1 0xf0224 +#define AN8811HB_CRC_DM_MON2 0xf0230 +#define AN8811HB_CRC_DM_MON3 0xf0234 +#define AN8811HB_CRC_RD_EN BIT(0) +#define AN8811HB_CRC_ST (BIT(0) | BIT(1)) +#define AN8811HB_CRC_CHECK_PASS BIT(0) + +#define AN8811HB_TX_POLARITY 0x5ce004 +#define AN8811HB_TX_POLARITY_NORMAL BIT(7) +#define AN8811HB_RX_POLARITY 0x5ce61c +#define AN8811HB_RX_POLARITY_NORMAL BIT(7) + +#define AN8811HB_HWTRAP1 0x5cf910 +#define AN8811HB_HWTRAP2 0x5cf914 +#define AN8811HB_HWTRAP2_CKO BIT(28) +#define AN8811HB_HWTRAP2_PKG (BIT(12) | BIT(13) | BIT(14)) +#define AN8811HB_PRO_ID 0x5cf920 +#define AN8811HB_PRO_ID_VERSION GENMASK(3, 0) + +#define AN8811HB_CLK_DRV 0x5cf9e4 +#define AN8811HB_CLK_DRV_CKO_MASK GENMASK(14, 12) +#define AN8811HB_CLK_DRV_CKOPWD BIT(12) +#define AN8811HB_CLK_DRV_CKO_LDPWD BIT(13) +#define AN8811HB_CLK_DRV_CKO_LPPWD BIT(14) + +#define AN8811HB_MCU_SW_RST 0x5cf9f8 +#define AN8811HB_MCU_SW_RST_HOLD BIT(16) +#define AN8811HB_MCU_SW_RST_RUN (BIT(16) | BIT(0)) +#define AN8811HB_MCU_SW_START 0x5cf9fc +#define AN8811HB_MCU_SW_START_EN BIT(16) + +#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap) + +#define SCRIPT_NAME(name) #name "_load_firmware" struct led { unsigned long rules; @@ -191,11 +267,48 @@ enum air_led_trigger_netdev_modes { #define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS) struct en8811h_priv { - int firmware_version; + u32 firmware_version; bool mcu_needs_restart; struct led led[EN8811H_LED_COUNT]; + u32 pro_id; + u32 pkg_sel; + u32 mem_size; + const char *script_name; }; +static int air_pbus_reg_write(struct phy_device *phydev, + u32 pbus_reg, u32 pbus_data) +{ + int pbus_addr = (phydev->addr) + 8; + struct mii_dev *bus = phydev->bus; + int ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, + AIR_EXT_PAGE_ACCESS, + (pbus_reg >> 16)); + if (ret < 0) + return ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, + AIR_PBUS_MODE_ADDR_HIGH, + ((pbus_reg & GENMASK(15, 6)) >> 6)); + if (ret < 0) + return ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, + ((pbus_reg & GENMASK(5, 2)) >> 2), + (pbus_data & GENMASK(15, 0))); + if (ret < 0) + return ret; + + ret = bus->write(bus, pbus_addr, MDIO_DEVAD_NONE, 0x10, + ((pbus_data & GENMASK(31, 16)) >> 16)); + if (ret < 0) + return ret; + + return ret; +} + static int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address, u32 pbus_data) { @@ -359,8 +472,8 @@ restore_page: static int air_write_buf(struct phy_device *phydev, unsigned long address, unsigned long array_size, const unsigned char *buffer) { - unsigned int offset; int ret, saved_page; + u32 offset; u16 val; saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); @@ -419,18 +532,144 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev) return ret; } -int en8811h_read_fw(void **fw, size_t *fwsize) +static int an8811hb_check_crc(struct phy_device *phydev, + u32 set1, u32 mon2, u32 mon3) { + int ret, retry = 10; + u32 pbus_value; + + /* Configure CRC */ + ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, + AN8811HB_CRC_RD_EN); + if (ret < 0) + return ret; + + ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, set1, pbus_value); + + do { + mdelay(300); + + ret = air_buckpbus_reg_read(phydev, mon2, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, mon2, pbus_value); + + if (pbus_value & AN8811HB_CRC_ST) { + ret = air_buckpbus_reg_read(phydev, mon3, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, mon3, + pbus_value); + + if (pbus_value & AN8811HB_CRC_CHECK_PASS) + debug("CRC Check PASS!\n"); + else + dev_err(phydev->dev, "CRC Check FAIL!(0x%lx)\n", + pbus_value & AN8811HB_CRC_CHECK_PASS); + + break; + } + + if (!retry) { + dev_err(phydev->dev, + "CRC Check is not ready.(Status %u)\n", + pbus_value); + return -ENODEV; + } + } while (--retry); + + ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, 0); + if (ret < 0) + return ret; + + ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + if (ret < 0) + return ret; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, set1, pbus_value); + + return ret; +} + +static int an8811hb_mcu_assert(struct phy_device *phydev) +{ + int ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_RST, + AN8811HB_MCU_SW_RST_HOLD); + if (ret < 0) + return ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_START, 0); + if (ret < 0) + return ret; + + debug("MCU asserted\n"); + mdelay(50); + + return ret; +} + +static int an8811hb_mcu_deassert(struct phy_device *phydev) +{ + int ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_START, + AN8811HB_MCU_SW_START_EN); + if (ret < 0) + return ret; + + ret = air_pbus_reg_write(phydev, AN8811HB_MCU_SW_RST, + AN8811HB_MCU_SW_RST_RUN); + if (ret < 0) + return ret; + + debug("MCU deasserted\n"); + mdelay(50); + + return ret; +} + +static int an8811hb_surge_protect_cfg(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + int ret = 0; + + if (!ofnode_read_bool(node, "airoha,surge-5r")) { + debug("Surge Protection mode - 0R\n"); + return ret; + } + + ret = air_buckpbus_reg_modify(phydev, AIR_PHY_CONTROL, + AIR_PHY_CONTROL_SURGE_5R, + AIR_PHY_CONTROL_SURGE_5R); + if (ret < 0) + return ret; + + debug("Surge Protection mode - 5R\n"); + + return ret; +} + +static int en8811h_read_fw(void **fw, size_t *fwsize, struct en8811h_priv *priv) +{ + const char *script_name = priv->script_name; + u32 mem_size = priv->mem_size; void *buffer; int ret; - buffer = malloc(EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE); + buffer = malloc(mem_size); if (!buffer) return -ENOMEM; - ret = request_firmware_into_buf_via_script(buffer, - EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE, - "en8811h_load_firmware", fwsize); + ret = request_firmware_into_buf_via_script(buffer, mem_size, + script_name, fwsize); if (ret) { free(buffer); return ret; @@ -450,7 +689,10 @@ static int en8811h_load_firmware(struct phy_device *phydev) void *buffer; int ret; - ret = en8811h_read_fw(&buffer, &fw_size); + priv->script_name = SCRIPT_NAME(en8811h); + priv->mem_size = EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE; + + ret = en8811h_read_fw(&buffer, &fw_size, priv); if (ret < 0) { dev_err(phydev->dev, "Failed to get firmware data\n"); return -EINVAL; @@ -496,9 +738,12 @@ static int en8811h_load_firmware(struct phy_device *phydev) goto en8811h_load_firmware_out; ret = en8811h_wait_mcu_ready(phydev); + if (ret < 0) + goto en8811h_load_firmware_out; air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &priv->firmware_version); + dev_info(phydev->dev, "MD32 firmware version: %08x\n", priv->firmware_version); @@ -510,6 +755,130 @@ en8811h_load_firmware_out: return ret; } +static int an8811hb_load_firmware(struct phy_device *phydev) +{ + struct en8811h_priv *priv = phydev->priv; + int ret, retry = 10; + size_t fw_size; + void *buffer; + u32 reg_val; + + ret = an8811hb_mcu_assert(phydev); + if (ret < 0) + return ret; + + ret = an8811hb_mcu_deassert(phydev); + if (ret < 0) + return ret; + + priv->script_name = SCRIPT_NAME(an8811hb); + priv->mem_size = AIR_MD32_DM_SIZE + AIR_MD32_DSP_SIZE; + + ret = en8811h_read_fw(&buffer, &fw_size, priv); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_START); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_write_buf(phydev, AIR_FW_ADDR_DM, AIR_MD32_DM_SIZE, + (unsigned char *)buffer); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = an8811hb_check_crc(phydev, AN8811HB_CRC_DM_SET1, + AN8811HB_CRC_DM_MON2, AN8811HB_CRC_DM_MON3); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, AIR_MD32_DSP_SIZE, + (unsigned char *)buffer + AIR_MD32_DM_SIZE); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = an8811hb_check_crc(phydev, AN8811HB_CRC_PM_SET1, + AN8811HB_CRC_PM_MON2, AN8811HB_CRC_PM_MON3); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); + if (ret < 0) + goto an8811hb_load_firmware_out; + + ret = an8811hb_surge_protect_cfg(phydev); + if (ret < 0) { + dev_err(phydev->dev, "an8811hb_surge_protect_cfg fail. (ret=%d)\n", ret); + goto an8811hb_load_firmware_out; + } + + do { + mdelay(300); + + ret = air_buckpbus_reg_read(phydev, AIR_PHY_FW_CTRL_1, ®_val); + if (ret < 0) + goto an8811hb_load_firmware_out; + + if (reg_val == AIR_PHY_FW_CTRL_1_FINISH) + break; + + debug("%d: reg 0x%x val 0x%x!\n", __LINE__, AIR_PHY_FW_CTRL_1, + reg_val); + + ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); + if (ret < 0) + goto an8811hb_load_firmware_out; + + } while (--retry); + + ret = en8811h_wait_mcu_ready(phydev); + if (ret < 0) + goto an8811hb_load_firmware_out; + + air_buckpbus_reg_read(phydev, AIR_PHY_MD32FW_VERSION, + &priv->firmware_version); + + debug("MD32 firmware version: %08x\n", priv->firmware_version); + +an8811hb_load_firmware_out: + free(buffer); + if (ret < 0) + dev_err(phydev->dev, "Firmware loading failed: %d\n", ret); + + return ret; +} + +int an8811hb_cko_cfg(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 pbus_value; + int ret = 0; + + if (!ofnode_read_bool(node, "airoha,phy-output-clock")) { + ret = air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, + AN8811HB_CLK_DRV_CKO_MASK, + AN8811HB_CLK_DRV_CKOPWD | + AN8811HB_CLK_DRV_CKO_LDPWD | + AN8811HB_CLK_DRV_CKO_LPPWD); + if (ret < 0) + return ret; + + debug("CKO Output mode - Disabled\n"); + } else { + ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + if (ret < 0) + return ret; + + debug("CKO Output %dMHz - Enabled\n", + (pbus_value & AN8811HB_HWTRAP2_CKO) ? 50 : 25); + } + + return ret; +} + static int en8811h_restart_mcu(struct phy_device *phydev) { int ret; @@ -613,13 +982,30 @@ static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol) return 0; } +/** + * air_leds_init - Initialize and configure LEDs for a phy device. + * + * @phydev: Pointer to the phy_device structure. + * @num: Number of LEDs to initialize. + * @dur: Duration for LED blink in milliseconds. It sets the duration + * for both the ON and OFF periods (OFF period will be half of `dur`). + * @mode: LED operation mode. Supported modes are: + * - AIR_LED_MODE_DISABLE: Disables LED control. + * - AIR_LED_MODE_USER_DEFINE: Enables user-defined LED control. + * + * Initializes and configures LEDs on a phy device with a specified blink duration + * and mode. Supports disabling or enabling user-defined control. + * Return: + * On success, returns 0. On error, it returns a negative value that denotes + * the error code. + */ + static int air_leds_init(struct phy_device *phydev, int num, u16 dur, int mode) { struct en8811h_priv *priv = phydev->priv; int ret, i; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, - dur); + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, dur); if (ret < 0) return ret; @@ -707,7 +1093,8 @@ static int en8811h_config(struct phy_device *phydev) pbus_value |= EN8811H_POLARITY_TX_NORMAL; ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, EN8811H_POLARITY_RX_REVERSE | - EN8811H_POLARITY_TX_NORMAL, pbus_value); + EN8811H_POLARITY_TX_NORMAL, + pbus_value); if (ret < 0) return ret; @@ -721,6 +1108,198 @@ static int en8811h_config(struct phy_device *phydev) return 0; } +static int an8811hb_config(struct phy_device *phydev) +{ + struct en8811h_priv *priv = phydev->priv; + u32 pbus_value = 0; + ofnode node; + int ret = 0; + + node = phy_get_ofnode(phydev); + if (!ofnode_valid(node)) + return 0; + + /* If restart happened in .probe(), no need to restart now */ + if (priv->mcu_needs_restart) { + ret = an8811hb_mcu_assert(phydev); + if (ret < 0) + return ret; + + ret = an8811hb_mcu_deassert(phydev); + if (ret < 0) + return ret; + + ret = en8811h_restart_mcu(phydev); + if (ret < 0) + return ret; + } else { + ret = an8811hb_load_firmware(phydev); + if (ret) { + dev_err(phydev->dev, "Load firmware fail.\n"); + return ret; + } + /* Next calls to .config() mcu needs to restart */ + priv->mcu_needs_restart = true; + } + + ret = air_buckpbus_reg_read(phydev, AN8811HB_PRO_ID, &pbus_value); + if (ret < 0) + return ret; + priv->pro_id = (pbus_value & AN8811HB_PRO_ID_VERSION) + 1; + + ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + if (ret < 0) + return ret; + priv->pkg_sel = (pbus_value & AN8811HB_HWTRAP2_PKG) >> 12; + debug("%s(%d) Version: E%d\n", + priv->pkg_sel ? "AN8811HBCN" : "AN8811HBN", priv->pkg_sel, + priv->pro_id); + + /* Serdes polarity */ + pbus_value = 0; + if (ofnode_read_bool(node, "airoha,pnswap-rx")) + pbus_value &= ~AN8811HB_RX_POLARITY_NORMAL; + else + pbus_value |= AN8811HB_RX_POLARITY_NORMAL; + + debug("1 pbus_value 0x%x\n", pbus_value); + ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, + AN8811HB_RX_POLARITY_NORMAL, pbus_value); + if (ret < 0) + return ret; + + pbus_value = 0; + if (ofnode_read_bool(node, "airoha,pnswap-tx")) + pbus_value &= ~AN8811HB_TX_POLARITY_NORMAL; + else + pbus_value |= AN8811HB_TX_POLARITY_NORMAL; + + debug("2 pbus_value 0x%x\n", pbus_value); + ret = air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, + AN8811HB_TX_POLARITY_NORMAL, pbus_value); + if (ret < 0) + return ret; + + /* Configure led gpio pins as output */ + if (priv->pkg_sel) { + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_MASK, + AN8811HB_GPIO_OUTPUT_0115); + if (ret < 0) + return ret; + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_1, + AN8811HB_GPIO_SEL_1_0_MASK | + AN8811HB_GPIO_SEL_1_1_MASK, + AN8811HB_GPIO_SEL_1_0 | + AN8811HB_GPIO_SEL_1_1); + if (ret < 0) + return ret; + + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_2, + AN8811HB_GPIO_SEL_2_15_MASK, + AN8811HB_GPIO_SEL_2_15); + if (ret < 0) + return ret; + } else { + ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_345, + AN8811HB_GPIO_OUTPUT_345); + if (ret < 0) + return ret; + } + + ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, + AIR_LED_MODE_USER_DEFINE); + if (ret < 0) { + dev_err(phydev->dev, "Failed to disable leds: %d\n", ret); + return ret; + } + + /* Co-Clock Output */ + ret = an8811hb_cko_cfg(phydev); + if (ret) + return ret; + + printf("AN8811HB initialize OK !\n"); + + return 0; +} + +static int an8811hb_update_duplex(struct phy_device *phydev) +{ + int lpa; + + if (phydev->autoneg == AUTONEG_ENABLE) { + lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); + if (lpa < 0) + return lpa; + + switch (phydev->speed) { + case SPEED_2500: + case SPEED_1000: + phydev->duplex = DUPLEX_FULL; + break; + case SPEED_100: + phydev->duplex = (lpa & LPA_100FULL) ? DUPLEX_FULL : + DUPLEX_HALF; + break; + case SPEED_10: + phydev->duplex = (lpa & LPA_10FULL) ? DUPLEX_FULL : + DUPLEX_HALF; + break; + } + } else { + int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + if (phydev->speed == SPEED_2500) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : + DUPLEX_HALF; + } + + return 0; +} + +static int an8811hb_parse_status(struct phy_device *phydev) +{ + int ret = 0, reg_value; + + reg_value = phy_read(phydev, MDIO_DEVAD_NONE, AIR_AUX_CTRL_STATUS); + if (reg_value < 0) + return reg_value; + + switch (reg_value & AIR_AUX_CTRL_STATUS_SPEED_MASK) { + case AIR_AUX_CTRL_STATUS_SPEED_2500: + phydev->speed = SPEED_2500; + break; + case AIR_AUX_CTRL_STATUS_SPEED_1000: + phydev->speed = SPEED_1000; + break; + case AIR_AUX_CTRL_STATUS_SPEED_100: + phydev->speed = SPEED_100; + break; + case AIR_AUX_CTRL_STATUS_SPEED_10: + phydev->speed = SPEED_10; + break; + default: + dev_err(phydev->dev, + "Auto-neg error, defaulting to 2500M/FD\n"); + phydev->speed = SPEED_2500; + phydev->duplex = DUPLEX_FULL; + return 0; + } + + /* Update duplex mode based on speed and negotiation status */ + ret = an8811hb_update_duplex(phydev); + if (ret < 0) + return ret; + + debug("Speed: %d, %s duplex\n", phydev->speed, + (phydev->duplex) ? "full" : "half"); + return ret; +} + static int en8811h_parse_status(struct phy_device *phydev) { int ret = 0, reg_value; @@ -742,7 +1321,8 @@ static int en8811h_parse_status(struct phy_device *phydev) phydev->speed = SPEED_100; break; default: - dev_err(phydev->dev, "Auto-neg error, defaulting to 2500M/FD\n"); + dev_err(phydev->dev, + "Auto-neg error, defaulting to 2500M/FD\n"); phydev->speed = SPEED_2500; break; } @@ -752,24 +1332,35 @@ static int en8811h_parse_status(struct phy_device *phydev) static int en8811h_startup(struct phy_device *phydev) { + u32 phy_id = phydev->phy_id; int ret = 0; ret = genphy_update_link(phydev); if (ret) return ret; - return en8811h_parse_status(phydev); + if (phy_id == EN8811H_PHY_ID) + ret = en8811h_parse_status(phydev); + else if (phy_id == AN8811HB_PHY_ID) + ret = an8811hb_parse_status(phydev); + + return ret; } static int en8811h_probe(struct phy_device *phydev) { struct en8811h_priv *priv; + int phy_id; priv = malloc(sizeof(*priv)); if (!priv) return -ENOMEM; memset(priv, 0, sizeof(*priv)); + debug("%s driver is probed.\n", phydev->drv->name); + get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phy_id); + debug("phy id is 0x%x.\n", phy_id); + priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0; priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1; priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2; @@ -782,12 +1373,12 @@ static int en8811h_probe(struct phy_device *phydev) return 0; } -static int en8811h_read_page(struct phy_device *phydev) +static int air_phy_read_page(struct phy_device *phydev) { return phy_read(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS); } -static int en8811h_write_page(struct phy_device *phydev, int page) +static int air_phy_write_page(struct phy_device *phydev, int page) { return phy_write(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS, page); } @@ -798,8 +1389,20 @@ U_BOOT_PHY_DRIVER(en8811h) = { .mask = 0x0ffffff0, .config = &en8811h_config, .probe = &en8811h_probe, - .read_page = &en8811h_read_page, - .write_page = &en8811h_write_page, + .read_page = &air_phy_read_page, + .write_page = &air_phy_write_page, + .startup = &en8811h_startup, + .shutdown = &genphy_shutdown, +}; + +U_BOOT_PHY_DRIVER(an8811hb) = { + .name = "Airoha AN8811HB", + .uid = AN8811HB_PHY_ID, + .mask = 0x0ffffff0, + .config = &an8811hb_config, + .probe = &en8811h_probe, + .read_page = &air_phy_read_page, + .write_page = &air_phy_write_page, .startup = &en8811h_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 772cde1c520..7ce03b59b6a 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -257,14 +257,14 @@ static int dp83867_config(struct phy_device *phydev) dp83867 = (struct dp83867_private *)phydev->priv; - ret = dp83867_of_init(phydev); + /* Reset PHY to clear any stale state after warm reboot */ + ret = phy_reset(phydev); if (ret) return ret; - /* Restart the PHY. */ - val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); - phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, - val | DP83867_SW_RESTART); + ret = dp83867_of_init(phydev); + if (ret) + return ret; /* Mode 1 or 2 workaround */ if (dp83867->rxctrl_strap_quirk) { diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 11d36164976..4ab709a14d5 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int fixedphy_probe(struct phy_device *phydev) { diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kconfig index 933271f01fa..1ead391c7b6 100644 --- a/drivers/net/phy/mediatek/Kconfig +++ b/drivers/net/phy/mediatek/Kconfig @@ -6,6 +6,7 @@ config MTK_NET_PHYLIB config PHY_MEDIATEK_2P5GE bool "MediaTek built-in 2.5Gb ethernet PHYs" depends on OF_CONTROL && (TARGET_MT7987 || TARGET_MT7988) + depends on SUPPORTS_FW_LOADER select FW_LOADER select MTK_NET_PHYLIB help diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index f357e0f1c77..1a7116f4ddd 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -407,6 +407,9 @@ static int ksz9031_config(struct phy_device *phydev) if (ret) return ret; + /* soft reset */ + phy_reset(phydev); + ksz90x1_workaround_asymmetric_pause(phydev); /* add an option to disable the gigabit feature of this PHY */ diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index b58283fe3d5..d7e0c4fe02d 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Generic PHY support and helper functions */ /** diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index e44b7b75bd5..f5a7dd349c9 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -8,9 +8,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GMII2RGMII_REG 0x10 #define ZYNQ_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100) diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index c51908ed8f3..52fc3edd4e0 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -23,6 +24,7 @@ #include #include #include +#include #define RSWITCH_SLEEP_US 1000 #define RSWITCH_TIMEOUT_US 1000000 @@ -587,9 +589,11 @@ static void rswitch_bat_desc_init(struct rswitch_port_priv *priv) rswitch_flush_dcache((uintptr_t)priv->bat_desc, desc_size); } -static void rswitch_tx_desc_init(struct rswitch_port_priv *priv) +static void rswitch_tx_desc_init(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); const u32 desc_size = RSWITCH_NUM_TX_DESC * sizeof(struct rswitch_desc); + dma_addr_t tx_desc_ba; u64 tx_desc_addr; int i; @@ -603,21 +607,25 @@ static void rswitch_tx_desc_init(struct rswitch_port_priv *priv) /* Mark the end of the descriptors */ priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].die_dt = DT_LINKFIX; tx_desc_addr = (uintptr_t)priv->tx_desc; - priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_addr); - priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_addr); + tx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)tx_desc_addr); + + priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_ba); + priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_ba); rswitch_flush_dcache(tx_desc_addr, desc_size); /* Point the controller to the TX descriptor list */ priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].die_dt = DT_LINKFIX; - priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_addr); - priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_addr); + priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_ba); + priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_ba); rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_TX_CHAIN_INDEX], sizeof(struct rswitch_desc)); } -static void rswitch_rx_desc_init(struct rswitch_port_priv *priv) +static void rswitch_rx_desc_init(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); const u32 desc_size = RSWITCH_NUM_RX_DESC * sizeof(struct rswitch_rxdesc); + dma_addr_t packet_ba, next_rx_desc_ba, rx_desc_ba; int i; u64 packet_addr; u64 next_rx_desc_addr; @@ -631,26 +639,29 @@ static void rswitch_rx_desc_init(struct rswitch_port_priv *priv) priv->rx_desc[i].data.die_dt = DT_FEMPTY; priv->rx_desc[i].data.info_ds = PKTSIZE_ALIGN; packet_addr = (uintptr_t)priv->rx_desc[i].packet; - priv->rx_desc[i].data.dptrl = lower_32_bits(packet_addr); - priv->rx_desc[i].data.dptrh = upper_32_bits(packet_addr); + packet_ba = dev_phys_to_bus(dev, (phys_addr_t)packet_addr); + priv->rx_desc[i].data.dptrl = lower_32_bits(packet_ba); + priv->rx_desc[i].data.dptrh = upper_32_bits(packet_ba); priv->rx_desc[i].link.die_dt = DT_LINKFIX; next_rx_desc_addr = (uintptr_t)&priv->rx_desc[i + 1]; - priv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_addr); - priv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_addr); + next_rx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)next_rx_desc_addr); + priv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_ba); + priv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_ba); } /* Mark the end of the descriptors */ priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.die_dt = DT_LINKFIX; rx_desc_addr = (uintptr_t)priv->rx_desc; - priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_addr); - priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_addr); + rx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)rx_desc_addr); + priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_ba); + priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_ba); rswitch_flush_dcache(rx_desc_addr, desc_size); /* Point the controller to the rx descriptor list */ priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].die_dt = DT_LINKFIX; - priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_addr); - priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_addr); + priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_ba); + priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_ba); rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_RX_CHAIN_INDEX], sizeof(struct rswitch_desc)); } @@ -741,9 +752,11 @@ static int rswitch_gwca_axi_ram_reset(struct rswitch_gwca *gwca) RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US); } -static int rswitch_gwca_init(struct rswitch_port_priv *priv) +static int rswitch_gwca_init(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_gwca *gwca = &priv->gwca; + dma_addr_t bat_desc_ba; int ret; ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); @@ -765,9 +778,11 @@ static int rswitch_gwca_init(struct rswitch_port_priv *priv) /* Setting flow */ writel(GWVCC_VEM_SC_TAG, gwca->addr + GWVCC); writel(0, gwca->addr + GWTTFC); - writel(upper_32_bits((uintptr_t)priv->bat_desc) & GWDCBAC0_DCBAUP, + + bat_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)(priv->bat_desc)); + writel(upper_32_bits(bat_desc_ba) & GWDCBAC0_DCBAUP, gwca->addr + GWDCBAC0 + priv->drv_data->gwdcbac_offset); - writel(lower_32_bits((uintptr_t)priv->bat_desc), + writel(lower_32_bits(bat_desc_ba), gwca->addr + GWDCBAC1 + priv->drv_data->gwdcbac_offset); writel(GWDCC_DQT | GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_TX_CHAIN_INDEX)); writel(GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_RX_CHAIN_INDEX)); @@ -844,8 +859,9 @@ static int rswitch_etha_init(struct rswitch_port_priv *priv) return 0; } -static int rswitch_init(struct rswitch_port_priv *priv) +static int rswitch_start(struct udevice *dev) { + struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_etha *etha = &priv->etha; int ret; @@ -875,8 +891,8 @@ static int rswitch_init(struct rswitch_port_priv *priv) return ret; rswitch_bat_desc_init(priv); - rswitch_tx_desc_init(priv); - rswitch_rx_desc_init(priv); + rswitch_tx_desc_init(dev); + rswitch_rx_desc_init(dev); rswitch_clock_enable(priv); @@ -886,7 +902,7 @@ static int rswitch_init(struct rswitch_port_priv *priv) rswitch_mfwd_init(priv); - ret = rswitch_gwca_init(priv); + ret = rswitch_gwca_init(dev); if (ret) return ret; @@ -897,23 +913,12 @@ static int rswitch_init(struct rswitch_port_priv *priv) return 0; } -static int rswitch_start(struct udevice *dev) -{ - struct rswitch_port_priv *priv = dev_get_priv(dev); - int ret; - - ret = rswitch_init(priv); - if (ret) - return ret; - - return 0; -} - #define RSWITCH_TX_TIMEOUT_MS 1000 static int rswitch_send(struct udevice *dev, void *packet, int len) { struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_desc *desc = &priv->tx_desc[priv->tx_desc_index]; + dma_addr_t bpacket = dev_phys_to_bus(dev, (phys_addr_t)packet); struct rswitch_gwca *gwca = &priv->gwca; u32 gwtrc_index, start; @@ -923,8 +928,8 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; - desc->dptrl = lower_32_bits((uintptr_t)packet); - desc->dptrh = upper_32_bits((uintptr_t)packet); + desc->dptrl = lower_32_bits(bpacket); + desc->dptrh = upper_32_bits(bpacket); rswitch_flush_dcache((uintptr_t)desc, sizeof(*desc)); /* Start transmission */ @@ -954,6 +959,7 @@ static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp) { struct rswitch_port_priv *priv = dev_get_priv(dev); struct rswitch_rxdesc *desc = &priv->rx_desc[priv->rx_desc_index]; + dma_addr_t dpacket; u8 *packet; int len; @@ -963,7 +969,9 @@ static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp) return -EAGAIN; len = desc->data.info_ds & RX_DS; - packet = (u8 *)(((uintptr_t)(desc->data.dptrh) << 32) | (uintptr_t)desc->data.dptrl); + dpacket = ((u64)(desc->data.dptrh) << 32) | (u64)(desc->data.dptrl); + packet = (u8 *)(uintptr_t)dev_bus_to_phys(dev, dpacket); + rswitch_invalidate_dcache((uintptr_t)packet, len); *packetp = packet; diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index edcae88a3fc..5b093623619 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -270,6 +270,7 @@ static struct { {"RTL-8100e", 0x32, 0xff7e1880,}, {"RTL-8168h/8111h", 0x54, 0xff7e1880,}, {"RTL-8125B", 0x64, 0xff7e1880,}, + {"RTL-8125d", 0x6a, 0xff7e5880,}, }; enum _DescStatusBit { diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c index 1d716716778..c3d40f0b59e 100644 --- a/drivers/net/sandbox-raw.c +++ b/drivers/net/sandbox-raw.c @@ -12,9 +12,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int reply_arp; static struct in_addr arp_ip; diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index 2011fd31f41..0ea50c484c0 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -84,8 +83,6 @@ struct icmphdr { #define ICMP_ECHO_REPLY 0 #define IPPROTO_ICMP 1 -DECLARE_GLOBAL_DATA_PTR; - static const u8 null_ethaddr[6]; static bool skip_timeout; diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index d4abc9a0411..40c98e72e4d 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -7,7 +7,6 @@ */ #include #include -#include #include #include @@ -26,8 +25,6 @@ #include "cpsw_mdio.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef KEYSTONE2_EMAC_GIG_ENABLE #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) #else diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index fb48feb4469..e9cc5db52d2 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Link setup */ #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 407b022508c..a50d5aee03f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -64,6 +64,7 @@ #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ +#define ZYNQ_GEM_NWCFG_NBC 0x00000020 /* No broadcast */ #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ @@ -76,6 +77,7 @@ #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ ZYNQ_GEM_NWCFG_FDEN | \ + ZYNQ_GEM_NWCFG_NBC | \ ZYNQ_GEM_NWCFG_FSREM) #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ @@ -256,6 +258,7 @@ struct zynq_gem_priv { struct clk pclk; u32 max_speed; bool dma_64bit; + bool cache_on; u32 clk_en_info; struct reset_ctl_bulk resets; }; @@ -691,6 +694,7 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { dma_addr_t addr; u32 size; + int ret; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; struct emac_bd *current_bd = &priv->tx_bd[1]; @@ -722,7 +726,8 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) addr = (ulong) ptr; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); - flush_dcache_range(addr, addr + size); + if (priv->cache_on) + flush_dcache_range(addr, addr + size); barrier(); /* Start transmit */ @@ -732,8 +737,13 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) printf("TX buffers exhausted in mid frame\n"); - return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, - true, 20000, true); + ret = wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, + true, 20000, true); + + /* Clear the transfer complete */ + setbits_le32(®s->txsr, ZYNQ_GEM_TSR_DONE); + + return ret; } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ @@ -769,7 +779,8 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) *packetp = (uchar *)(uintptr_t)addr; - invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); + if (priv->cache_on) + invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier(); return frame_len; @@ -802,8 +813,8 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) #else addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; #endif - flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, - ARCH_DMA_MINALIGN)); + if (priv->cache_on) + flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier(); if ((++priv->rxbd_current) >= RX_BUF) @@ -926,7 +937,8 @@ static int zynq_gem_probe(struct udevice *dev) memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); ulong addr = (ulong)priv->rxbuffers; - flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); + if (priv->cache_on) + flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); barrier(); /* Align bd_space to MMU_SECTION_SHIFT */ @@ -936,8 +948,9 @@ static int zynq_gem_probe(struct udevice *dev) goto err1; } - mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, - BD_SPACE, DCACHE_OFF); + if (priv->cache_on) + mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, + BD_SPACE, DCACHE_OFF); /* Initialize the bd spaces for tx and rx bd's */ priv->tx_bd = (struct emac_bd *)bd_space; @@ -1050,6 +1063,9 @@ static int zynq_gem_of_to_plat(struct udevice *dev) /* Hardcode for now */ priv->phyaddr = -1; + if (!dev_read_bool(dev, "dma-coherent")) + priv->cache_on = true; + if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args)) { fdt_addr_t addr; diff --git a/drivers/pci/pci_octeontx.c b/drivers/pci/pci_octeontx.c index 875cf7f7115..6752112a878 100644 --- a/drivers/pci/pci_octeontx.c +++ b/drivers/pci/pci_octeontx.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * This driver supports multiple types of operations / host bridges / busses: * diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c index 483b07ce078..1eff6d1b0ed 100644 --- a/drivers/pci/pcie_dw_meson.c +++ b/drivers/pci/pcie_dw_meson.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -27,8 +26,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - /** * struct meson_pcie - Amlogic Meson DW PCIe controller state * diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c index 978754e8472..10c45aaba20 100644 --- a/drivers/pci/pcie_dw_qcom.c +++ b/drivers/pci/pcie_dw_qcom.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - struct qcom_pcie; struct qcom_pcie_ops { diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 208aa30463a..61117fa95e6 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - /** * struct rk_pcie - RK DW PCIe controller state * diff --git a/drivers/pci/pcie_dw_ti.c b/drivers/pci/pcie_dw_ti.c index dc6e65273b7..37c295fdd38 100644 --- a/drivers/pci/pcie_dw_ti.c +++ b/drivers/pci/pcie_dw_ti.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - #define PCIE_VENDORID_MASK GENMASK(15, 0) #define PCIE_DEVICEID_SHIFT 16 diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 11c4ccbfc55..8d853ecf2c2 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -728,15 +728,31 @@ static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf, static int imx_pcie_dm_probe(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); + int ret; #if CONFIG_IS_ENABLED(DM_REGULATOR) device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie); #endif /* if PERST# valid from dt then assert it */ - gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, - GPIOD_IS_OUT); - priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (!ret) { + /* + * Legacy property, invert assert logic based on + * reset-gpio-active-high. This won't work if flags are not + * matching the reset-gpio-active-high. + */ + priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + } else { + /* + * Linux kernel upstream property, assert active level based on + * GPIO flags, thus leave priv->reset_active_high=0. + */ + gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + } + if (dm_gpio_is_valid(&priv->reset_gpio)) { dm_gpio_set_value(&priv->reset_gpio, priv->reset_active_high ? 0 : 1); diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 1be33095b9c..db7c4f47916 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include @@ -16,8 +15,6 @@ #endif #include "pcie_layerscape.h" -DECLARE_GLOBAL_DATA_PTR; - LIST_HEAD(ls_pcie_list); unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index b7f692f6450..d5f4930e181 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -7,9 +7,11 @@ #ifndef _PCIE_LAYERSCAPE_H_ #define _PCIE_LAYERSCAPE_H_ -#include +#include +#include #include +#include #include #include diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 0908ae16b67..88a2bf84538 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -39,12 +38,11 @@ #define STG_SYSCON_RP_NEP_OFFSET 0xe8 #define STG_SYSCON_K_RP_NEP_MASK BIT(8) -DECLARE_GLOBAL_DATA_PTR; - struct starfive_pcie { struct pcie_plda plda; struct clk_bulk clks; struct reset_ctl_bulk rsts; + struct gpio_desc power_gpio; struct gpio_desc reset_gpio; struct regmap *regmap; unsigned int stg_pcie_base; @@ -184,6 +182,10 @@ static int starfive_pcie_parse_dt(struct udevice *dev) dev_err(dev, "reset-gpio is not valid\n"); return -EINVAL; } + + gpio_request_by_name(dev, "enable-gpios", 0, &priv->power_gpio, + GPIOD_IS_OUT); + return 0; } @@ -205,6 +207,9 @@ static int starfive_pcie_init_port(struct udevice *dev) goto err_deassert_clk; } + if (dm_gpio_is_valid(&priv->power_gpio)) + dm_gpio_set_value(&priv->power_gpio, 1); + dm_gpio_set_value(&priv->reset_gpio, 1); /* Disable physical functions except #0 */ for (i = 1; i < PLDA_FUNC_NUM; i++) { diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c index 902d1a51eaa..b71defe4019 100644 --- a/drivers/pci_endpoint/pci_ep-uclass.c +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -13,12 +13,9 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr) { struct pci_ep_ops *ops = pci_ep_get_ops(dev); diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 549ddbf5046..8c0ab80fbbc 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -9,3 +9,10 @@ config PHY_CADENCE_TORRENT depends on DM_RESET help Enable this to support the Cadence Torrent PHY driver + +config SPL_PHY_CADENCE_TORRENT + bool "Cadence Torrent PHY Driver" + depends on SPL_DM_RESET + help + Enable this to support the Cadence Torrent PHY driver at SPL + stage. diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index a4121423873..b074d58f9f6 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #define COMPHY_MAX_CHIP 4 -DECLARE_GLOBAL_DATA_PTR; - static const char *get_speed_string(u32 speed) { static const char * const speed_strings[] = { diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c index 2be0178882a..6df4ff4eb05 100644 --- a/drivers/phy/omap-usb2-phy.c +++ b/drivers/phy/omap-usb2-phy.c @@ -6,7 +6,6 @@ * Written by Jean-Jacques Hiblot */ -#include #include #include #include @@ -39,8 +38,6 @@ #define USB2PHY_USE_CHG_DET_REG BIT(29) #define USB2PHY_DIS_CHG_DET BIT(28) -DECLARE_GLOBAL_DATA_PTR; - struct omap_usb2_phy { struct regmap *pwr_regmap; ulong flags; diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 4ea6600ce7f..f80b2789333 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -421,6 +421,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = { + { + .reg = 0xff2b0000, + .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0060, 1, 0, 2, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0070, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = { { .reg = 0xffdf0000, @@ -540,6 +556,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_usb2phy_cfgs, }, + { + .compatible = "rockchip,rk3506-usb2phy", + .data = (ulong)&rk3506_phy_cfgs, + }, { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs, diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index d602f965d6a..82353ae7678 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -399,6 +399,14 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); param_write(priv->phy_grf, &cfg->usb_mode_set, true); + switch (priv->id) { + case 0: + param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); + break; + case 1: + param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); + break; + } break; case PHY_TYPE_SATA: writel(0x41, priv->mmio + 0x38); diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index 660037034ec..5775101c4cb 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * The higher 16-bit of this register is used for write protection * only if BIT(x + 16) set to 1 the BIT(x) can be written. diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 66d1d32d25c..305d5b0dd48 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define usleep_range(a, b) udelay((b)) #define CMN_SSM_BANDGAP (0x21 << 2) diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 111085f235d..df750b26d66 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -7,3 +7,13 @@ config PHY_J721E_WIZ signals to the SERDES (Sierra/Torrent). This driver configures three clock selects (pll0, pll1, dig) and resets for each of the lanes. + +config SPL_PHY_J721E_WIZ + bool "TI J721E WIZ (SERDES Wrapper) support" + depends on ARCH_K3 + help + This option enables support for WIZ module present in TI's J721E + SoC at SPL stage. WIZ is a serdes wrapper used to configure some + of the input signals to the SERDES (Sierra/Torrent). This driver + configures three clock selects (pll0, pll1, dig) and resets for + each of the lanes. diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ea90713ec6c..578edbf8168 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -291,6 +291,15 @@ config PINCTRL_SANDBOX Currently, this driver actually does nothing but print debug messages when pinctrl operations are invoked. +config PINCTRL_SCMI + bool "Support SCMI pin controllers" + depends on PINCTRL_FULL && SCMI_FIRMWARE + help + This is for pinctrl over the SCMI protocol. This allows the + initial pin configuration to be set up from the device tree. The + gpio_scmi driver is built on top of this driver if GPIO is + required. + config PINCTRL_SINGLE bool "Single register pin-control and pin-multiplex driver" depends on DM @@ -345,7 +354,7 @@ config SPL_PINCTRL_STMFX config PINCTRL_TH1520 bool "T-Head TH1520 pinctrl driver" - depends on DM && PINCTRL_FULL + depends on DM && PINCTRL_GENERIC select PINCONF help Support pin multiplexing and configuration control blocks on the @@ -386,6 +395,14 @@ config PINCTRL_ZYNQMP Generic Pinctrl framework and is compatible with the Linux driver, i.e. it uses the same device tree configuration. +config SPL_PINCTRL_ZYNQMP + bool "Xilinx ZynqMP pin control driver in SPL" + depends on SPL_DM && SPL_PINCTRL_GENERIC && ARCH_ZYNQMP + default PINCTRL_ZYNQMP + help + Support pin multiplexing control in SPL on Xilinx ZynqMP. Only "pins" + can be muxed; "groups" are not supported. + endif source "drivers/pinctrl/broadcom/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 33ff7b95ef2..29fb9b484d0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_MSCC) += mscc/ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_ARCH_NEXELL) += nexell/ obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o @@ -36,5 +37,5 @@ obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o obj-y += broadcom/ -obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o +obj-$(CONFIG_$(PHASE_)PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 8a588d17c4b..cf72a7df62c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -38,6 +38,14 @@ config PINCTRL_MT8188 bool "MT8188 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT8195 + bool "MT8195 SoC pinctrl driver" + select PINCTRL_MTK + +config PINCTRL_MT8189 + bool "MT8189 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT8365 bool "MT8365 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index b9116c073ea..f90c74314f4 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8189) += pinctrl-mt8189.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 0d48994bd89..8875c276f36 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -1070,6 +1070,7 @@ static const struct mtk_pinctrl_soc mt7981_data = { .gpio_mode = 0, .base_names = mt7981_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 61ce2ec8ac1..3288cc93972 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -755,6 +755,7 @@ static const struct mtk_pinctrl_soc mt7986_data = { .gpio_mode = 0, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7987.c b/drivers/pinctrl/mediatek/pinctrl-mt7987.c index 92b43cf3b55..0c90c1ceec5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7987.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c @@ -712,6 +712,7 @@ static const struct mtk_pinctrl_soc mt7987_data = { .gpio_mode = 0, .base_names = mt7987_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 74655493414..43982d7a859 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1250,6 +1250,7 @@ static const struct mtk_pinctrl_soc mt7988_data = { .gpio_mode = 0, .base_names = mt7988_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), + .rev = MTK_PINCTRL_V1, .base_calc = 1, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8188.c b/drivers/pinctrl/mediatek/pinctrl-mt8188.c index 386d4d4a922..256053f269f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8188.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8188.c @@ -1339,6 +1339,7 @@ U_BOOT_DRIVER(mt8188_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8188_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8188_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c new file mode 100644 index 00000000000..a64440d8bb3 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -0,0 +1,1277 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Bo-Chen Chen + */ +#include +#include "pinctrl-mtk-common.h" + +enum { + IO_BASE, + IO_BASE_LM, + IO_BASE_RB0, + IO_BASE_RB1, + IO_BASE_BM0, + IO_BASE_BM1, + IO_BASE_BM2, + IO_BASE_LT0, + IO_BASE_LT1, + IO_BASE_RT, + IO_BASE_EINT0, + IO_BASE_EINT1, + IO_BASE_EINT2, + IO_BASE_EINT3, + IO_BASE_EINT4, +}; + +#define PIN_FIELD_IOCFG0(s_pin, e_pin, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_BASE_CALC(s_pin, e_pin, IO_BASE, s_addr, x_addrs, s_bit, \ + x_bits, 32, 0) + +#define PIN_FIELD_BASE(pin, i_base, s_addr, s_bit, x_bits) \ + PIN_FIELD_BASE_CALC(pin, pin, i_base, s_addr, 0x10, s_bit, x_bits, \ + 32, 0) + +static const struct mtk_pin_field_calc mt8189_pin_mode_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8189_pin_dir_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_di_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_do_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_smt_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x00e0, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x00c0, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x00c0, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x00c0, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x00c0, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x00c0, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x00e0, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x00e0, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x00e0, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x00e0, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x00e0, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x00e0, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00e0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00e0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x00f0, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x00f0, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00e0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00e0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x00e0, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x00e0, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x00e0, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x00e0, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x00f0, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x00f0, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x00f0, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x00c0, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x00c0, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00e0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00e0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x00c0, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00e0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x00f0, 19, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x00c0, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x00f0, 21, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x00f0, 20, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x00f0, 23, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x00f0, 22, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x00f0, 25, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x00f0, 24, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x00f0, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x00f0, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x00f0, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x00f0, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x00f0, 6, 1), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00e0, 20, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00e0, 21, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00e0, 22, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00e0, 23, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x00c0, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x00c0, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x00c0, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x00c0, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x00c0, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x00c0, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x00c0, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x00c0, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x00c0, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00e0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00e0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00e0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00e0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00e0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00e0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00e0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00e0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x00f0, 10, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x00f0, 12, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x00f0, 11, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x00f0, 13, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00e0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00e0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00e0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00e0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00e0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00e0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x00f0, 13, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00e0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x00c0, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x00c0, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x00c0, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x00c0, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00e0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00e0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00e0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x00e0, 24, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x00e0, 25, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x00e0, 26, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x00e0, 27, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0120, 20, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0120, 19, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0120, 22, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0120, 21, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0120, 16, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0120, 17, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0120, 23, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0120, 15, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0120, 18, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0120, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0120, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0120, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0120, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0120, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0120, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x00e0, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x00e0, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x00e0, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x00e0, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x00e0, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x00e0, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x00e0, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x00e0, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x00e0, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x00c0, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x00c0, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x00c0, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00e0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00e0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00e0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00e0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x00c0, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x00c0, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x00c0, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x00c0, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x00c0, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x00c0, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x00c0, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x00c0, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x00c0, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x00c0, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x00c0, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x00c0, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x00c0, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x00c0, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x00c0, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x00c0, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x00c0, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x00c0, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00e0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00e0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x00c0, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x00c0, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x00c0, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x00c0, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x00c0, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x00c0, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x00c0, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x00c0, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x00c0, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x00c0, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x00c0, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x00f0, 14, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x00c0, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x00f0, 15, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x00f0, 16, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x00f0, 17, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x00f0, 18, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0120, 12, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0120, 11, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0120, 10, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0090, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0120, 14, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0120, 7, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0120, 6, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0090, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0120, 9, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0120, 8, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0090, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0120, 13, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00f0, 8, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00f0, 7, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00f0, 9, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00f0, 10, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00f0, 11, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00f0, 12, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00f0, 5, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00f0, 4, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00f0, 6, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00f0, 7, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00f0, 8, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00f0, 9, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0120, 24, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0120, 25, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x00f0, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_ies_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0050, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0050, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0050, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0050, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0050, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0050, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0050, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0050, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0050, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0050, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0050, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0050, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x0070, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x0070, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0050, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0050, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x0070, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x0070, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0050, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0050, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0050, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0050, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0040, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0040, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0040, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0050, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0050, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x0070, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x0070, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0050, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x0070, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0050, 19, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0050, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0050, 21, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0050, 20, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0050, 23, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0050, 22, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0050, 25, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0050, 24, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0050, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0050, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0050, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0050, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0050, 6, 1), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0050, 20, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0050, 21, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0050, 22, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0050, 23, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0050, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0050, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0050, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0050, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0050, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0050, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0050, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0050, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0050, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x0070, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x0070, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x0070, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x0070, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x0070, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x0070, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x0070, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x0070, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0040, 10, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0040, 12, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0040, 11, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0040, 13, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x0070, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x0070, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x0070, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x0070, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x0070, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x0070, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0050, 13, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x0070, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0050, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0050, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0050, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0050, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x0070, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x0070, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x0070, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0050, 24, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0050, 25, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0050, 26, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0050, 27, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0060, 20, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0060, 19, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0060, 22, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0060, 21, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0060, 16, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0060, 17, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0060, 23, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0060, 15, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0060, 18, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0060, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0060, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0060, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0060, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0060, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0060, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0050, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0050, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0050, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0050, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0050, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0050, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0050, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0050, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0050, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0050, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0050, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0050, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x0070, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x0070, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x0070, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x0070, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0050, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0050, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0050, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0050, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0050, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0050, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0050, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0050, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0050, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0050, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0050, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0050, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0050, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0050, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0050, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0050, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0050, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0050, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x0070, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x0070, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0050, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0050, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0050, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0050, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0050, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0050, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0050, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0050, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0050, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0050, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0050, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0050, 14, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0050, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0050, 15, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0050, 16, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0050, 17, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0050, 18, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0060, 12, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0060, 11, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0060, 10, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0020, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0060, 14, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0060, 7, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0060, 6, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0020, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0060, 9, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0060, 8, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0020, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0060, 13, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0050, 8, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0050, 7, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0050, 9, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0050, 10, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0050, 11, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0050, 12, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0040, 5, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0040, 4, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0040, 6, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0040, 7, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0040, 8, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0040, 9, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0060, 24, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0060, 25, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0040, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pupd_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0090, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0090, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0090, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0090, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00a0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00a0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00a0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0050, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00a0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00a0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00a0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0050, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00a0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00a0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0050, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00a0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0090, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0090, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0090, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0090, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0090, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0090, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0080, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0080, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0080, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0080, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0080, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0080, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_r0_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00b0, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00b0, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00b0, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00b0, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00c0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00c0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00c0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0060, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00c0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00c0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00c0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0060, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00c0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00c0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0060, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00c0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00b0, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00b0, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00b0, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00b0, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00b0, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00b0, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00a0, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00a0, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00a0, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00a0, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00a0, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00a0, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_r1_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00c0, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00c0, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00c0, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00c0, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00d0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00d0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00d0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0070, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00d0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00d0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00d0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0070, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00d0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00d0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0070, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00d0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00c0, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00c0, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00c0, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00c0, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00c0, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00c0, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00b0, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00b0, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00b0, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00b0, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00b0, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00b0, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pu_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x00a0, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0090, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0090, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0090, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0090, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0090, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x00a0, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x00a0, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x00a0, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x00a0, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x00a0, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x00a0, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00b0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00b0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x00a0, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x00a0, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00b0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00b0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x00a0, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x00a0, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x00a0, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x00a0, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0090, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0090, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0090, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0090, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0090, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00b0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00b0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0090, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00b0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x00a0, 13, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0090, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x00a0, 15, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x00a0, 14, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x00a0, 17, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x00a0, 16, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x00a0, 19, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x00a0, 18, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x00a0, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x00a0, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x00a0, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x00a0, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x00a0, 6, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0090, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0090, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0090, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0090, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0090, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0090, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0090, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0090, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0090, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00b0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00b0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00b0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00b0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00b0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00b0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00b0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00b0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0090, 4, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0090, 6, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0090, 5, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0090, 7, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00b0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00b0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00b0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00b0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00b0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00b0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x00a0, 7, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00b0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0090, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0090, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0090, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0090, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00b0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00b0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00b0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x00a0, 22, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x00a0, 23, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x00a0, 24, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x00a0, 25, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x00b0, 11, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x00b0, 10, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x00b0, 13, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x00b0, 12, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x00b0, 7, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x00b0, 8, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x00b0, 14, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x00b0, 6, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x00b0, 9, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x00b0, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x00b0, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x00b0, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x00b0, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x00b0, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x00b0, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x00a0, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x00a0, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x00a0, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x00a0, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x00a0, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x00a0, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x00a0, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x00a0, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x00a0, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0090, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0090, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0090, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00b0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00b0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00b0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00b0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0090, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0090, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0090, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0090, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0090, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0090, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0090, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0090, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0090, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0090, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0090, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0090, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0090, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0090, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0090, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0090, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0090, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0090, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00b0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00b0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0090, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0090, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0090, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0090, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0090, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0090, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0090, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0090, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0090, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0090, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0090, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x00a0, 8, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0090, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x00a0, 9, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x00a0, 10, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x00a0, 11, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x00a0, 12, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x00b0, 15, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x00b0, 16, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0090, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pd_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0080, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0080, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0080, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0080, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0080, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0080, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0080, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0080, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0080, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0080, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0080, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0080, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00a0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00a0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0080, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0080, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00a0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00a0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0080, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0080, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0080, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0080, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0070, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0070, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0070, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0080, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0080, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00a0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00a0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0080, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00a0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0080, 13, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0080, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0080, 15, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0080, 14, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0080, 17, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0080, 16, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0080, 19, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0080, 18, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0080, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0080, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0080, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0080, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0080, 6, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0080, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0080, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0080, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0080, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0080, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0080, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0080, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0080, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0080, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00a0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00a0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00a0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00a0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00a0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00a0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00a0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00a0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0070, 4, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0070, 6, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0070, 5, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0070, 7, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00a0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00a0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00a0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00a0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00a0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00a0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0080, 7, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00a0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0080, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0080, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0080, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0080, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00a0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00a0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00a0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0080, 22, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0080, 23, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0080, 24, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0080, 25, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0090, 11, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0090, 10, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0090, 13, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0090, 12, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0090, 7, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0090, 8, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0090, 14, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0090, 6, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0090, 9, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0090, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0090, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0090, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0090, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0090, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0090, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0080, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0080, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0080, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0080, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0080, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0080, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0080, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0080, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0080, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0080, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0080, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0080, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00a0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00a0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00a0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00a0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0080, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0080, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0080, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0080, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0080, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0080, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0080, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0080, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0080, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0080, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0080, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0080, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0080, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0080, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0080, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0080, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0080, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0080, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00a0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00a0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0080, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0080, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0080, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0080, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0080, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0080, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0080, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0080, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0080, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0080, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0080, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0080, 8, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0080, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0080, 9, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0080, 10, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0080, 11, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0080, 12, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0090, 15, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0090, 16, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0070, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0000, 15, 3), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0000, 9, 3), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0000, 12, 3), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0000, 15, 3), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0000, 18, 3), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0000, 21, 3), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0000, 18, 3), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0000, 21, 3), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0000, 24, 3), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0000, 27, 3), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0010, 0, 3), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0010, 3, 3), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x0000, 15, 3), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x0000, 18, 3), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0000, 0, 3), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0000, 3, 3), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x0000, 21, 3), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x0000, 24, 3), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0000, 0, 3), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0000, 6, 3), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0000, 3, 3), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0000, 9, 3), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0000, 0, 3), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0000, 3, 3), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0000, 6, 3), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0000, 6, 3), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0000, 3, 3), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x0000, 3, 3), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x0000, 6, 3), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0000, 0, 3), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x0000, 0, 3), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0010, 27, 3), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0030, 0, 3), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0020, 3, 3), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0020, 0, 3), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0020, 9, 3), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0020, 6, 3), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0020, 15, 3), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0020, 12, 3), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0000, 15, 3), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0000, 6, 3), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0000, 9, 3), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0000, 12, 3), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0000, 18, 3), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0020, 0, 3), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0020, 3, 3), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0020, 6, 3), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0020, 9, 3), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0000, 15, 3), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0000, 12, 3), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0000, 9, 3), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0000, 24, 3), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0010, 0, 3), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0000, 27, 3), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0010, 3, 3), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0000, 18, 3), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0000, 21, 3), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x0010, 9, 3), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x0010, 21, 3), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x0010, 12, 3), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x0010, 24, 3), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x0010, 15, 3), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x0010, 27, 3), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x0010, 18, 3), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x0020, 0, 3), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0010, 0, 3), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0010, 6, 3), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0010, 3, 3), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0010, 9, 3), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x0020, 6, 3), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x0020, 3, 3), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x0020, 12, 3), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x0020, 9, 3), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x0020, 18, 3), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x0020, 15, 3), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0010, 9, 3), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x0020, 21, 3), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0010, 9, 3), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0010, 6, 3), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0010, 15, 3), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0010, 12, 3), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x0020, 27, 3), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x0020, 24, 3), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x0030, 0, 3), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0020, 12, 3), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0020, 15, 3), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0020, 18, 3), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0020, 21, 3), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0020, 0, 3), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0010, 27, 3), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0020, 6, 3), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0020, 3, 3), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0010, 18, 3), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0010, 21, 3), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0020, 9, 3), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0010, 15, 3), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0010, 24, 3), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0000, 0, 3), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0000, 15, 3), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0000, 9, 3), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0000, 12, 3), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0000, 3, 3), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0000, 6, 3), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0010, 15, 3), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0010, 6, 3), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0010, 12, 3), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0010, 9, 3), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0010, 27, 3), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0010, 18, 3), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0010, 24, 3), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0010, 21, 3), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0000, 12, 3), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0000, 0, 3), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0000, 3, 3), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0000, 6, 3), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x0000, 27, 3), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x0010, 6, 3), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x0010, 0, 3), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x0010, 3, 3), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0020, 18, 3), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0020, 15, 3), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0020, 12, 3), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0020, 9, 3), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0010, 27, 3), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0010, 24, 3), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0010, 21, 3), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0010, 18, 3), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0020, 6, 3), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0010, 15, 3), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0020, 0, 3), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0020, 21, 3), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0010, 9, 3), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0010, 12, 3), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0020, 24, 3), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0020, 3, 3), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0010, 3, 3), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0010, 6, 3), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x0000, 9, 3), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x0000, 12, 3), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0000, 9, 3), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0000, 12, 3), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0000, 0, 3), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0000, 3, 3), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0000, 6, 3), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0000, 15, 3), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0000, 18, 3), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0000, 21, 3), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0000, 24, 3), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0000, 27, 3), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0010, 0, 3), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0010, 12, 3), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0020, 27, 3), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0010, 15, 3), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0010, 18, 3), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0010, 21, 3), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0010, 24, 3), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0010, 6, 3), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0010, 3, 3), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0010, 0, 3), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0000, 6, 3), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0010, 12, 3), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0000, 21, 3), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0000, 18, 3), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0000, 3, 3), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0000, 27, 3), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0000, 24, 3), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0000, 0, 3), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0010, 9, 3), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0000, 24, 3), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0000, 21, 3), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0000, 27, 3), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0010, 0, 3), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0010, 3, 3), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0010, 6, 3), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0000, 15, 3), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0000, 12, 3), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0000, 18, 3), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0000, 21, 3), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0000, 24, 3), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0000, 27, 3), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0020, 12, 3), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0020, 15, 3), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3), +}; + +static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8189_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8189_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8189_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8189_pin_ies_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8189_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8189_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8189_pin_r1_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range), +}; + +static const char * const mt8189_pinctrl_register_base_names[] = { + [IO_BASE] = "base", + [IO_BASE_LM] = "lm", + [IO_BASE_RB0] = "rb0", + [IO_BASE_RB1] = "rb1", + [IO_BASE_BM0] = "bm0", + [IO_BASE_BM1] = "bm1", + [IO_BASE_BM2] = "bm2", + [IO_BASE_LT0] = "lt0", + [IO_BASE_LT1] = "lt1", + [IO_BASE_RT] = "rt", + [IO_BASE_EINT0] = "eint0", + [IO_BASE_EINT1] = "eint1", + [IO_BASE_EINT2] = "eint2", + [IO_BASE_EINT3] = "eint3", + [IO_BASE_EINT4] = "eint4", +}; + +static const struct mtk_pin_desc mt8189_pins[] = { + MTK_TYPED_PIN(0, "GPIO00", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(1, "GPIO01", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(2, "GPIO02", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(3, "GPIO03", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(4, "GPIO04", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(5, "GPIO05", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(6, "GPIO06", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(7, "GPIO07", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(8, "GPIO08", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(9, "GPIO09", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(10, "GPIO10", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(11, "GPIO11", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(12, "GPIO12", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(13, "GPIO13", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(14, "GPIO14", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(15, "GPIO15", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(16, "GPIO16", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(17, "GPIO17", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(18, "GPIO18", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(19, "GPIO19", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(20, "GPIO20", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(21, "GPIO21", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(22, "GPIO22", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(23, "GPIO23", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(24, "GPIO24", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(25, "GPIO25", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(26, "GPIO26", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(27, "GPIO27", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(28, "GPIO28", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(29, "GPIO29", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(30, "GPIO30", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(31, "GPIO31", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(32, "GPIO32", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(33, "GPIO33", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(34, "GPIO34", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(35, "GPIO35", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(36, "GPIO36", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(37, "GPIO37", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(38, "GPIO38", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(39, "GPIO39", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(40, "GPIO40", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(41, "GPIO41", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(42, "GPIO42", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(43, "GPIO43", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(44, "GPIO44", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(45, "GPIO45", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(46, "GPIO46", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(47, "GPIO47", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(48, "GPIO48", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(49, "GPIO49", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(50, "GPIO50", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(51, "GPIO51", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(52, "GPIO52", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(53, "GPIO53", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(54, "GPIO54", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(55, "GPIO55", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(56, "GPIO56", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(57, "GPIO57", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(58, "GPIO58", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(59, "GPIO59", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(60, "GPIO60", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(61, "GPIO61", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(62, "GPIO62", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(63, "GPIO63", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(64, "GPIO64", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(65, "GPIO65", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(66, "GPIO66", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(67, "GPIO67", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(68, "GPIO68", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(69, "GPIO69", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(70, "GPIO70", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(71, "GPIO71", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(72, "GPIO72", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(73, "GPIO73", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(74, "GPIO74", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(75, "GPIO75", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(76, "GPIO76", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(77, "GPIO77", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(78, "GPIO78", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(79, "GPIO79", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(80, "GPIO80", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(81, "GPIO81", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(82, "GPIO82", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(83, "GPIO83", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(84, "GPIO84", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(85, "GPIO85", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(86, "GPIO86", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(87, "GPIO87", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(88, "GPIO88", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(89, "GPIO89", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(90, "GPIO90", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(91, "GPIO91", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(92, "GPIO92", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(93, "GPIO93", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(94, "GPIO94", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(95, "GPIO95", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(96, "GPIO96", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(97, "GPIO97", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(98, "GPIO98", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(99, "GPIO99", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(100, "GPIO100", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(101, "GPIO101", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(102, "GPIO102", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(103, "GPIO103", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(104, "GPIO104", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(105, "GPIO105", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(106, "GPIO106", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(107, "GPIO107", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(108, "GPIO108", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(109, "GPIO109", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(110, "GPIO110", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(111, "GPIO111", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(112, "GPIO112", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(113, "GPIO113", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(114, "GPIO114", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(115, "GPIO115", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(116, "GPIO116", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(117, "GPIO117", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(118, "GPIO118", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(119, "GPIO119", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(120, "GPIO120", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(121, "GPIO121", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(122, "GPIO122", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(123, "GPIO123", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(124, "GPIO124", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(125, "GPIO125", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(126, "GPIO126", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(127, "GPIO127", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(128, "GPIO128", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(129, "GPIO129", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(130, "GPIO130", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(131, "GPIO131", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(132, "GPIO132", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(133, "GPIO133", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(134, "GPIO134", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(135, "GPIO135", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(136, "GPIO136", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(137, "GPIO137", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(138, "GPIO138", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(139, "GPIO139", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(140, "GPIO140", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(141, "GPIO141", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(142, "GPIO142", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(143, "GPIO143", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(144, "GPIO144", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(145, "GPIO145", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(146, "GPIO146", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(147, "GPIO147", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(148, "GPIO148", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(149, "GPIO149", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(150, "GPIO150", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(151, "GPIO151", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(152, "GPIO152", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(153, "GPIO153", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(154, "GPIO154", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(155, "GPIO155", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(156, "GPIO156", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(157, "GPIO157", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(158, "GPIO158", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(159, "GPIO159", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(160, "GPIO160", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(161, "GPIO161", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(162, "GPIO162", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(163, "GPIO163", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(164, "GPIO164", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(165, "GPIO165", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(166, "GPIO166", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(167, "GPIO167", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(168, "GPIO168", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(169, "GPIO169", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(170, "GPIO170", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(171, "GPIO171", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(172, "GPIO172", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(173, "GPIO173", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(174, "GPIO174", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(175, "GPIO175", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(176, "GPIO176", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(177, "GPIO177", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(178, "GPIO178", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(179, "GPIO179", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(180, "GPIO180", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(181, "GPIO181", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(182, "GPIO182", DRV_GRP4, DRV_GRP0), +}; + +static const struct mtk_io_type_desc mt8189_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "mt8189", + .bias_set = mtk_pinconf_bias_set_v1, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +static struct mtk_pinctrl_soc mt8189_data = { + .name = "mt8189_pinctrl", + .reg_cal = mt8189_reg_cals, + .pins = mt8189_pins, + .npins = ARRAY_SIZE(mt8189_pins), + .io_type = mt8189_io_type_desc, + .ntype = ARRAY_SIZE(mt8189_io_type_desc), + .base_names = mt8189_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8189_pinctrl_register_base_names), + .base_calc = 1, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8189_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8189_data); +} + +static const struct udevice_id mt8189_pctrl_match[] = { + { .compatible = "mediatek,mt8189-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(mt8189_pinctrl) = { + .name = "mt8189_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8189_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt8189_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c new file mode 100644 index 00000000000..db619766a99 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -0,0 +1,1080 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT8195 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2026 MediaTek Inc. + * Author: Chris Chen + */ +#include +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD_IOCFG0(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, IOCFG0_BASE, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +#define MT8195_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT8195_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +enum { + IOCFG0_BASE, + IOCFG_BM_BASE, + IOCFG_BL_BASE, + IOCFG_BR_BASE, + IOCFG_LM_BASE, + IOCFG_RB_BASE, + IOCFG_TL_BASE, + EINT_BASE, +}; + +static const char * const mt8195_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint", +}; + +static const struct mtk_pin_field_calc mt8195_pin_mode_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8195_pin_dir_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_di_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_do_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x040, 0x10, 13, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x040, 0x10, 14, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x040, 0x10, 15, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x040, 0x10, 16, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x040, 0x10, 17, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x060, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x060, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x060, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x060, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x060, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x070, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x070, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x070, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x070, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x070, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x070, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x070, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x060, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x060, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x060, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x060, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x060, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x060, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x060, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x060, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x060, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x060, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x060, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x060, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x060, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x060, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x060, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x060, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x060, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x060, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x060, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x060, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x060, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x060, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x060, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x060, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x060, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x060, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x060, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x070, 0x10, 11, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x030, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x030, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x030, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x030, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x030, 0x10, 20, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x030, 0x10, 28, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x030, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x030, 0x10, 30, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x030, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x030, 0x10, 31, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x030, 0x10, 25, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x030, 0x10, 26, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x030, 0x10, 23, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x030, 0x10, 24, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x030, 0x10, 22, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x030, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x010, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x010, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x010, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x010, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x010, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x010, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x070, 0x10, 13, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x070, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x070, 0x10, 15, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x070, 0x10, 14, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x070, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x070, 0x10, 16, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x070, 0x10, 19, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x070, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0d0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0d0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0d0, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0d0, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0d0, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0d0, 0x10, 5, 1), + PINS_FIELD_BASE(6, 7, IOCFG_LM_BASE, 0x0d0, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0d0, 0x10, 12, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0d0, 0x10, 7, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0d0, 0x10, 13, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0d0, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0d0, 0x10, 14, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0d0, 0x10, 9, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0d0, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0d0, 0x10, 10, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0d0, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0d0, 0x10, 11, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x090, 0x10, 10, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x090, 0x10, 9, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x090, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x090, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x090, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x090, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x090, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x090, 0x10, 5, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x090, 0x10, 6, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x090, 0x10, 7, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x090, 0x10, 8, 1), + PINS_FIELD_BASE(31, 33, IOCFG_BM_BASE, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x0f0, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x0f0, 0x10, 1, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x0f0, 0x10, 2, 1), + PINS_FIELD_BASE(38, 39, IOCFG_BM_BASE, 0x0f0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x0f0, 0x10, 14, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x0f0, 0x10, 13, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x0f0, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x0f0, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x0f0, 0x10, 25, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x0f0, 0x10, 26, 1), + PINS_FIELD_BASE(46, 47, IOCFG_BM_BASE, 0x0f0, 0x10, 5, 1), + PINS_FIELD_BASE(48, 51, IOCFG_BM_BASE, 0x0f0, 0x10, 6, 1), + PINS_FIELD_BASE(52, 55, IOCFG_BM_BASE, 0x0f0, 0x10, 7, 1), + PINS_FIELD_BASE(56, 59, IOCFG_BM_BASE, 0x0f0, 0x10, 8, 1), + PINS_FIELD_BASE(60, 63, IOCFG_BM_BASE, 0x0f0, 0x10, 9, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(65, 68, IOCFG_BM_BASE, 0x0f0, 0x10, 3, 1), + PINS_FIELD_BASE(69, 71, IOCFG_BM_BASE, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(72, 75, IOCFG_BM_BASE, 0x0f0, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x0f0, 0x10, 12, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0e0, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0e0, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0e0, 0x10, 6, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0e0, 0x10, 7, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0e0, 0x10, 8, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0e0, 0x10, 9, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0e0, 0x10, 10, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0e0, 0x10, 11, 1), + PINS_FIELD_BASE(85, 88, IOCFG_BR_BASE, 0x0e0, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0e0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0e0, 0x10, 3, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0e0, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0e0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0e0, 0x10, 12, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0e0, 0x10, 13, 1), + PINS_FIELD_BASE(95, 98, IOCFG_BR_BASE, 0x0e0, 0x10, 15, 1), + PINS_FIELD_BASE(99, 102, IOCFG_BR_BASE, 0x0e0, 0x10, 16, 1), + PINS_FIELD_BASE(103, 104, IOCFG_BR_BASE, 0x0e0, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(106, 107, IOCFG_BR_BASE, 0x0e0, 0x10, 17, 1), + PINS_FIELD_BASE(108, 109, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0c0, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0c0, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0c0, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0c0, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0c0, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0c0, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0c0, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0c0, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0c0, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0c0, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0c0, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0c0, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(129, 131, IOCFG_BR_BASE, 0x0e0, 0x10, 19, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0c0, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0c0, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0c0, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0c0, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x0f0, 0x10, 18, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x0f0, 0x10, 17, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x0f0, 0x10, 20, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x0f0, 0x10, 19, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x0f0, 0x10, 22, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x0f0, 0x10, 21, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x0f0, 0x10, 24, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x0f0, 0x10, 23, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pu_range[] = { + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x00a0, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x00a0, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x00b0, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pd_range[] = { + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x0080, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x0080, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x0080, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x0090, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0050, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0070, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0080, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x000, 0x10, 15, 3), + PINS_FIELD_BASE(6, 7, IOCFG_LM_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x000, 0x10, 24, 3), + PINS_FIELD_BASE(31, 33, IOCFG_BM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(38, 39, IOCFG_BM_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x020, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x020, 0x10, 0, 3), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x030, 0x10, 0, 3), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x030, 0x10, 3, 3), + PINS_FIELD_BASE(46, 47, IOCFG_BM_BASE, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(48, 51, IOCFG_BM_BASE, 0x010, 0x10, 6, 3), + PINS_FIELD_BASE(52, 55, IOCFG_BM_BASE, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(56, 59, IOCFG_BM_BASE, 0x010, 0x10, 12, 3), + PINS_FIELD_BASE(60, 63, IOCFG_BM_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(65, 68, IOCFG_BM_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x000, 0x10, 28, 3), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(85, 88, IOCFG_BR_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(95, 98, IOCFG_BR_BASE, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(99, 102, IOCFG_BR_BASE, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(103, 104, IOCFG_BR_BASE, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(106, 107, IOCFG_BR_BASE, 0x010, 0x10, 24, 3), + PINS_FIELD_BASE(108, 109, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(129, 130, IOCFG_BR_BASE, 0x020, 0x10, 0, 3), + PINS_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x020, 0x10, 9, 3), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x020, 0x10, 6, 3), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x020, 0x10, 15, 3), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x020, 0x10, 12, 3), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x020, 0x10, 21, 3), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x020, 0x10, 18, 3), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x020, 0x10, 27, 3), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x020, 0x10, 24, 3), +}; + +static const struct mtk_pin_reg_calc mt8195_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8195_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8195_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8195_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8195_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8195_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8195_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8195_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8195_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range), +}; + +static const struct mtk_pin_desc mt8195_pins[] = { + MT8195_TYPE1_PIN(0, "GPIO_00"), + MT8195_TYPE1_PIN(1, "GPIO_01"), + MT8195_TYPE1_PIN(2, "GPIO_02"), + MT8195_TYPE1_PIN(3, "GPIO_03"), + MT8195_TYPE1_PIN(4, "GPIO_04"), + MT8195_TYPE1_PIN(5, "GPIO_05"), + MT8195_TYPE0_PIN(6, "GPIO_06"), + MT8195_TYPE0_PIN(7, "GPIO_07"), + MT8195_TYPE0_PIN(8, "SDA0"), + MT8195_TYPE0_PIN(9, "SCL0"), + MT8195_TYPE0_PIN(10, "SDA1"), + MT8195_TYPE0_PIN(11, "SCL1"), + MT8195_TYPE0_PIN(12, "SDA2"), + MT8195_TYPE0_PIN(13, "SCL2"), + MT8195_TYPE0_PIN(14, "SDA3"), + MT8195_TYPE0_PIN(15, "SCL3"), + MT8195_TYPE0_PIN(16, "SDA4"), + MT8195_TYPE0_PIN(17, "SCL4"), + MT8195_TYPE0_PIN(18, "DPTX_HPD"), + MT8195_TYPE0_PIN(19, "PCIE_WAKE_N"), + MT8195_TYPE0_PIN(20, "PCIE_PERESET_N"), + MT8195_TYPE0_PIN(21, "PCIE_CLKREQ_N"), + MT8195_TYPE0_PIN(22, "CMMCLK0"), + MT8195_TYPE0_PIN(23, "CMMCLK1"), + MT8195_TYPE0_PIN(24, "CMMCLK2"), + MT8195_TYPE0_PIN(25, "CMMRST"), + MT8195_TYPE0_PIN(26, "CMMPDN"), + MT8195_TYPE0_PIN(27, "HDMIRX_HTPLG"), + MT8195_TYPE0_PIN(28, "HDMIRX_PWR5V"), + MT8195_TYPE0_PIN(29, "HDMIRX_SCL"), + MT8195_TYPE0_PIN(30, "HDMIRX_SDA"), + MT8195_TYPE0_PIN(31, "HDMITX_PWR5V"), + MT8195_TYPE0_PIN(32, "HDMITX_HTPLG"), + MT8195_TYPE0_PIN(33, "HDMITX_CEC"), + MT8195_TYPE0_PIN(34, "HDMITX_SCL"), + MT8195_TYPE0_PIN(35, "HDMITX_SDA"), + MT8195_TYPE0_PIN(36, "PMIC_RTC32K_CK"), + MT8195_TYPE0_PIN(37, "PMIC_WATCHDOG"), + MT8195_TYPE0_PIN(38, "PMIC_SRCLKEN_IN0"), + MT8195_TYPE0_PIN(39, "PMIC_SRCLKEN_IN1"), + MT8195_TYPE0_PIN(40, "PWRAP_SPI_CSN"), + MT8195_TYPE0_PIN(41, "PWRAP_SPI_CK"), + MT8195_TYPE0_PIN(42, "PWRAP_SPI_MO"), + MT8195_TYPE0_PIN(43, "PWRAP_SPI_MI"), + MT8195_TYPE0_PIN(44, "SPMI_M_SCL"), + MT8195_TYPE0_PIN(45, "SPMI_M_SDA"), + MT8195_TYPE0_PIN(46, "I2SIN_MCK"), + MT8195_TYPE0_PIN(47, "I2SIN_BCK"), + MT8195_TYPE0_PIN(48, "I2SIN_WS"), + MT8195_TYPE0_PIN(49, "I2SIN_D0"), + MT8195_TYPE0_PIN(50, "I2SO1_MCK"), + MT8195_TYPE0_PIN(51, "I2SO1_BCK"), + MT8195_TYPE0_PIN(52, "I2SO1_WS"), + MT8195_TYPE0_PIN(53, "I2SO1_D0"), + MT8195_TYPE0_PIN(54, "I2SO1_D1"), + MT8195_TYPE0_PIN(55, "I2SO1_D2"), + MT8195_TYPE0_PIN(56, "I2SO1_D3"), + MT8195_TYPE0_PIN(57, "I2SO2_MCK"), + MT8195_TYPE0_PIN(58, "I2SO2_BCK"), + MT8195_TYPE0_PIN(59, "I2SO2_WS"), + MT8195_TYPE0_PIN(60, "I2SO2_D0"), + MT8195_TYPE0_PIN(61, "DMIC1_SCK"), + MT8195_TYPE0_PIN(62, "DMIC1_DAT"), + MT8195_TYPE0_PIN(63, "DMIC2_SCK"), + MT8195_TYPE0_PIN(64, "DMIC2_DAT"), + MT8195_TYPE0_PIN(65, "PCM_DO"), + MT8195_TYPE0_PIN(66, "PCM_CLK"), + MT8195_TYPE0_PIN(67, "PCM_DI"), + MT8195_TYPE0_PIN(68, "PCM_SYNC"), + MT8195_TYPE0_PIN(69, "AUD_CLK_MOSI"), + MT8195_TYPE0_PIN(70, "AUD_SYNC_MOSI"), + MT8195_TYPE0_PIN(71, "AUD_DAT_MOSI0"), + MT8195_TYPE0_PIN(72, "AUD_DAT_MOSI1"), + MT8195_TYPE0_PIN(73, "AUD_DAT_MISO0"), + MT8195_TYPE0_PIN(74, "AUD_DAT_MISO1"), + MT8195_TYPE0_PIN(75, "AUD_DAT_MISO2"), + MT8195_TYPE0_PIN(76, "SCP_VREQ_VAO"), + MT8195_TYPE1_PIN(77, "DGI_D0"), + MT8195_TYPE1_PIN(78, "DGI_D1"), + MT8195_TYPE1_PIN(79, "DGI_D2"), + MT8195_TYPE1_PIN(80, "DGI_D3"), + MT8195_TYPE1_PIN(81, "DGI_D4"), + MT8195_TYPE1_PIN(82, "DGI_D5"), + MT8195_TYPE1_PIN(83, "DGI_D6"), + MT8195_TYPE1_PIN(84, "DGI_D7"), + MT8195_TYPE1_PIN(85, "DGI_D8"), + MT8195_TYPE1_PIN(86, "DGI_D9"), + MT8195_TYPE1_PIN(87, "DGI_D10"), + MT8195_TYPE1_PIN(88, "DGI_D11"), + MT8195_TYPE1_PIN(89, "DGI_D12"), + MT8195_TYPE1_PIN(90, "DGI_D13"), + MT8195_TYPE1_PIN(91, "DGI_D14"), + MT8195_TYPE1_PIN(92, "DGI_D15"), + MT8195_TYPE1_PIN(93, "DGI_HSYNC"), + MT8195_TYPE1_PIN(94, "DGI_VSYNC"), + MT8195_TYPE1_PIN(95, "DGI_DE"), + MT8195_TYPE1_PIN(96, "DGI_CK"), + MT8195_TYPE0_PIN(97, "DISP_PWM0"), + MT8195_TYPE0_PIN(98, "UART0_TXD"), + MT8195_TYPE0_PIN(99, "UART0_RXD"), + MT8195_TYPE0_PIN(100, "UART1_RTS"), + MT8195_TYPE0_PIN(101, "UART1_CTS"), + MT8195_TYPE0_PIN(102, "UART1_TXD"), + MT8195_TYPE0_PIN(103, "UART1_RXD"), + MT8195_TYPE1_PIN(104, "KPROW0"), + MT8195_TYPE1_PIN(105, "KPROW1"), + MT8195_TYPE1_PIN(106, "KPCOL0"), + MT8195_TYPE1_PIN(107, "KPCOL1"), + MT8195_TYPE0_PIN(108, "DSI_LCM_RST"), + MT8195_TYPE0_PIN(109, "DSI_DSI_TE"), + MT8195_TYPE1_PIN(110, "MSDC1_CMD"), + MT8195_TYPE1_PIN(111, "MSDC1_CLK"), + MT8195_TYPE1_PIN(112, "MSDC1_DAT0"), + MT8195_TYPE1_PIN(113, "MSDC1_DAT1"), + MT8195_TYPE1_PIN(114, "MSDC1_DAT2"), + MT8195_TYPE1_PIN(115, "MSDC1_DAT3"), + MT8195_TYPE1_PIN(116, "EMMC_DAT7"), + MT8195_TYPE1_PIN(117, "EMMC_DAT6"), + MT8195_TYPE1_PIN(118, "EMMC_DAT5"), + MT8195_TYPE1_PIN(119, "EMMC_DAT4"), + MT8195_TYPE1_PIN(120, "EMMC_RSTB"), + MT8195_TYPE1_PIN(121, "EMMC_CMD"), + MT8195_TYPE1_PIN(122, "EMMC_CLK"), + MT8195_TYPE1_PIN(123, "EMMC_DAT3"), + MT8195_TYPE1_PIN(124, "EMMC_DAT2"), + MT8195_TYPE1_PIN(125, "EMMC_DAT1"), + MT8195_TYPE1_PIN(126, "EMMC_DAT0"), + MT8195_TYPE1_PIN(127, "EMMC_DSL"), + MT8195_TYPE0_PIN(128, "USB_IDDIG"), + MT8195_TYPE0_PIN(129, "USB_DRV_VBUS"), + MT8195_TYPE0_PIN(130, "USB_IDDIG_1P"), + MT8195_TYPE0_PIN(131, "USB_DRV_VBUS_1P"), + MT8195_TYPE0_PIN(132, "SPIM0_CSB"), + MT8195_TYPE0_PIN(133, "SPIM0_CLK"), + MT8195_TYPE0_PIN(134, "SPIM0_MO"), + MT8195_TYPE0_PIN(135, "SPIM0_MI"), + MT8195_TYPE0_PIN(136, "SPIM1_CSB"), + MT8195_TYPE0_PIN(137, "SPIM1_CLK"), + MT8195_TYPE0_PIN(138, "SPIM1_MO"), + MT8195_TYPE0_PIN(139, "SPIM1_MI"), + MT8195_TYPE0_PIN(140, "SPIM2_CSB"), + MT8195_TYPE0_PIN(141, "SPIM2_CLK"), + MT8195_TYPE0_PIN(142, "SPIM2_MO"), + MT8195_TYPE0_PIN(143, "SPIM2_MI"), +}; + +static const struct mtk_io_type_desc mt8195_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "mt8195", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP1] = { + .name = "MSDC", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART0_0_RXD_TXD */ +static int mt8195_uart0_0_rxd_txd_pins[] = { 99, 98 }; +static int mt8195_uart0_0_rxd_txd_funcs[] = { 1, 1 }; +/* UART1_0 */ +static int mt8195_uart1_0_pins[] = { 103, 102 }; +static int mt8195_uart1_0_funcs[] = { 1, 1 }; +/* MSDC0 */ +static int mt8195_msdc0_pins[] = { 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126 }; +static int mt8195_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +/* i2c0 */ +static int mt8195_i2c0_pins[] = { 8, 9 }; +static int mt8195_i2c0_funcs[] = { 1, 1 }; +/* i2c1 */ +static int mt8195_i2c1_pins[] = {10, 11 }; +static int mt8195_i2c1_funcs[] = { 1, 1 }; +/* i2c2 */ +static int mt8195_i2c2_pins[] = { 12, 13 }; +static int mt8195_i2c2_funcs[] = { 1, 1 }; +/* i2c3 */ +static int mt8195_i2c3_pins[] = { 14, 15 }; +static int mt8195_i2c3_funcs[] = { 1, 1 }; +/* i2c4 */ +static int mt8195_i2c4_pins[] = { 16, 17 }; +static int mt8195_i2c4_funcs[] = { 1, 1 }; +/* i2c5 */ +static int mt8195_i2c5_pins[] = { 30, 29 }; +static int mt8195_i2c5_funcs[] = { 3, 3 }; +/* i2c6 */ +static int mt8195_i2c6_pins[] = { 25, 26 }; +static int mt8195_i2c6_funcs[] = { 4, 4 }; +/* spi0 */ +static int mt8195_spi0_pins[] = { 132, 133, 134, 135 }; +static int mt8195_spi0_funcs[] = { 1, 1, 1, 1 }; +/* spi1 */ +static int mt8195_spi1_pins[] = { 136, 137, 138, 139 }; +static int mt8195_spi1_funcs[] = { 1, 1, 1, 1 }; +/* spi2 */ +static int mt8195_spi2_pins[] = { 140, 141, 142, 143 }; +static int mt8195_spi2_funcs[] = { 1, 1, 1, 1 }; + +static const struct mtk_group_desc mt8195_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8195_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0", mt8195_uart1_0), + PINCTRL_PIN_GROUP("msdc0", mt8195_msdc0), + PINCTRL_PIN_GROUP("i2c0", mt8195_i2c0), + PINCTRL_PIN_GROUP("i2c1", mt8195_i2c1), + PINCTRL_PIN_GROUP("i2c2", mt8195_i2c2), + PINCTRL_PIN_GROUP("i2c3", mt8195_i2c3), + PINCTRL_PIN_GROUP("i2c4", mt8195_i2c4), + PINCTRL_PIN_GROUP("i2c5", mt8195_i2c5), + PINCTRL_PIN_GROUP("i2c6", mt8195_i2c6), + PINCTRL_PIN_GROUP("spi0", mt8195_spi0), + PINCTRL_PIN_GROUP("spi1", mt8195_spi1), + PINCTRL_PIN_GROUP("spi2", mt8195_spi2), +}; + +static const char *const mt8195_uart_groups[] = { + "uart0_0_rxd_txd", "uart1_0", +}; + +static const char *const mt8195_msdc_groups[] = { + "msdc0", +}; + +static const char *const mt8195_i2c_groups[] = { + "i2c0", "i2c1", "i2c2", "i2c3", "i2c4", "i2c5", "i2c6" +}; + +static const char *const mt8195_spi_groups[] = { + "spi0", "spi1", "spi2", +}; + +static const struct mtk_function_desc mt8195_functions[] = { + { "uart", mt8195_uart_groups, ARRAY_SIZE(mt8195_uart_groups) }, + { "msdc", mt8195_msdc_groups, ARRAY_SIZE(mt8195_msdc_groups) }, + { "i2c", mt8195_i2c_groups, ARRAY_SIZE(mt8195_i2c_groups) }, + { "spi", mt8195_spi_groups, ARRAY_SIZE(mt8195_spi_groups) }, +}; + +static struct mtk_pinctrl_soc mt8195_data = { + .name = "mt8195_pinctrl", + .reg_cal = mt8195_reg_cals, + .pins = mt8195_pins, + .npins = ARRAY_SIZE(mt8195_pins), + .grps = mt8195_groups, + .ngrps = ARRAY_SIZE(mt8195_groups), + .funcs = mt8195_functions, + .nfuncs = ARRAY_SIZE(mt8195_functions), + .io_type = mt8195_io_type_desc, + .ntype = ARRAY_SIZE(mt8195_io_type_desc), + .base_names = mt8195_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8195_pinctrl_register_base_names), + .base_calc = 1, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8195_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8195_data); +} + +static const struct udevice_id mt8195_pctrl_match[] = { + { .compatible = "mediatek,mt8195-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8195_pinctrl) = { + .name = "mt8195_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8195_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt8195_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index a6985e48858..0ce99b92a9f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -596,6 +596,7 @@ U_BOOT_DRIVER(mt8365_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = mt8365_pctrl_match, .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, .probe = mtk_pinctrl_mt8365_probe, .priv_auto = sizeof(struct mtk_pinctrl_priv), }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index e991e03ea41..d152e216634 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -856,6 +856,9 @@ int mtk_pinctrl_common_probe(struct udevice *dev, if (!base_calc) nbase_names = 1; + if (nbase_names > MAX_BASE_CALC) + return -ENOSPC; + for (i = 0; i < nbase_names; i++) { if (soc->base_names) addr = dev_read_addr_name(dev, soc->base_names[i]); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 15ab3c1bf07..58f13613633 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -9,7 +9,7 @@ #define MTK_PINCTRL_V0 0x0 #define MTK_PINCTRL_V1 0x1 #define BASE_CALC_NONE 0 -#define MAX_BASE_CALC 10 +#define MAX_BASE_CALC 15 #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7628.c b/drivers/pinctrl/mtmips/pinctrl-mt7628.c index dc7acec4a77..be3a28eb94d 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mt7628.c +++ b/drivers/pinctrl/mtmips/pinctrl-mt7628.c @@ -6,15 +6,12 @@ */ #include -#include #include #include #include #include "pinctrl-mtmips-common.h" -DECLARE_GLOBAL_DATA_PTR; - #define AGPIO_OFS 0 #define GPIOMODE1_OFS 0x24 #define GPIOMODE2_OFS 0x28 diff --git a/drivers/pinctrl/nexell/pinctrl-nexell.c b/drivers/pinctrl/nexell/pinctrl-nexell.c index d5be7baf50d..af1acd91649 100644 --- a/drivers/pinctrl/nexell/pinctrl-nexell.c +++ b/drivers/pinctrl/nexell/pinctrl-nexell.c @@ -7,13 +7,10 @@ #include #include -#include #include #include "pinctrl-nexell.h" #include "pinctrl-s5pxx18.h" -DECLARE_GLOBAL_DATA_PTR; - /* given a pin-name, return the address of pin config registers */ unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name, u32 *pin) diff --git a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c index a6ae5764fbc..aeed3f1e1e1 100644 --- a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c +++ b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c @@ -9,15 +9,12 @@ #include #include -#include #include #include #include #include "pinctrl-nexell.h" #include "pinctrl-s5pxx18.h" -DECLARE_GLOBAL_DATA_PTR; - static void nx_gpio_set_bit(u32 *value, u32 bit, int enable) { register u32 newvalue; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 84d9a3641ff..b2a19557a27 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -103,13 +103,13 @@ config PINCTRL_IMX8M registers. config PINCTRL_IMX93 - bool "IMX8M pinctrl driver" + bool "IMX93/1 pinctrl driver" depends on ARCH_IMX9 && PINCTRL_FULL select PINCTRL_IMX_MMIO help - Say Y here to enable the imx8m pinctrl driver + Say Y here to enable the imx9[3,1] pinctrl driver - This provides a simple pinctrl driver for i.MX8M SoC familiy. + This provides a simple pinctrl driver for i.MX9[3,1] SoC. This feature depends on device tree configuration. This driver is different from the linux one, this is a simple implementation, only parses the 'fsl,pins' property and configure related diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 7d861ae52c1..7f1cc5a182f 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o -obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o +obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx9.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c index 2f4228a9fc5..7cdbbbba747 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c +++ b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config) { struct imx_pinctrl_priv *priv = dev_get_priv(dev); diff --git a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c index 781835c6852..dcd76fdc571 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c +++ b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c @@ -17,6 +17,7 @@ #define DAISY_OFFSET_IMX95 0x408 #define DAISY_OFFSET_IMX94 0x608 +#define DAISY_OFFSET_IMX952 0x460 /* SCMI pin control types */ #define PINCTRL_TYPE_MUX 192 @@ -69,7 +70,7 @@ static int imx_pinconf_scmi_set(struct udevice *dev, u32 mux_ofs, u32 mux, u32 c in.attributes = num_cfgs << PINCTRL_NUM_CFGS_SHIFT; msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_PINCTRL, - SCMI_MSG_PINCTRL_CONFIG_SET, in, out); + SCMI_PINCTRL_SETTINGS_CONFIGURE, in, out); ret = devm_scmi_process_msg(dev, &msg); if (ret || out.status) { @@ -136,6 +137,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev) priv->daisy_offset = DAISY_OFFSET_IMX95; else if (IS_ENABLED(CONFIG_IMX94)) priv->daisy_offset = DAISY_OFFSET_IMX94; + else if (IS_ENABLED(CONFIG_IMX952)) + priv->daisy_offset = DAISY_OFFSET_IMX952; else return -EINVAL; @@ -144,7 +147,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev) static int imx_scmi_pinctrl_bind(struct udevice *dev) { - if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94)) + if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) || + IS_ENABLED(CONFIG_IMX952)) return 0; return -ENODEV; diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 7d91ccfb26f..d8011768581 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config, int pin_size, u32 **pin_data, int *npins) { diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h index 9adf999d3bb..569bb869abd 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.h +++ b/drivers/pinctrl/nxp/pinctrl-imx.h @@ -6,6 +6,14 @@ #ifndef __DRIVERS_PINCTRL_IMX_H #define __DRIVERS_PINCTRL_IMX_H +#define PINCTRL_PIN(a, b) { .number = a, .name = b } +#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) + +struct imx_pinctrl_pin_desc { + unsigned int number; + const char *name; +}; + /** * @base: the address to the controller in virtual memory * @input_sel_base: the address of the select input in virtual memory. diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c index 9b3b5aec07a..23865ee6428 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -9,14 +9,11 @@ #include #include #include -#include #include #include #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - #define PADRING_IFMUX_EN_SHIFT 31 #define PADRING_IFMUX_EN_MASK BIT(31) #define PADRING_GP_EN_SHIFT 30 diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c index d9c63b3aca6..6eec1a277b3 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8m.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c @@ -4,21 +4,83 @@ */ #include +#include #include +#include +#include +#include #include "pinctrl-imx.h" static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data"); static const struct udevice_id imx8m_pinctrl_match[] = { +#if IS_ENABLED(CONFIG_IMX8MQ) { .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX8MM) { .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX8MN) { .compatible = "fsl,imx8mn-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX8MP) { .compatible = "fsl,imx8mp-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info }, +#endif { /* sentinel */ } }; +#if CONFIG_IS_ENABLED(CMD_PINMUX) + +#if IS_ENABLED(CONFIG_IMX8MP) +#include "pinctrl-imx8mp.c" +#elif IS_ENABLED(CONFIG_IMX8MN) +#include "pinctrl-imx8mn.c" +#elif IS_ENABLED(CONFIG_IMX8MM) +#include "pinctrl-imx8mm.c" +#elif IS_ENABLED(CONFIG_IMX8MQ) +#include "pinctrl-imx8mq.c" +#endif + +static int imx8m_get_pins_count(struct udevice *dev) +{ + return ARRAY_SIZE(imx8m_pinctrl_pads); +} + +static const char *imx8m_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + /* sanity checking */ + if (selector != imx8m_pinctrl_pads[selector].number) { + dev_err(dev, + "selector(%u) not match with imx8m_pinctrl_pads[selector].number(%u)\n", + selector, imx8m_pinctrl_pads[selector].number); + return NULL; + } + + return imx8m_pinctrl_pads[selector].name; +} + +static int imx8m_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + u32 mux_reg = selector << 2; + u32 mux_mode = readl(info->base + mux_reg); + + snprintf(buf, size, "Function(%d) at: 0x%p", mux_mode & 0x7, info->base + mux_reg); + + return 0; +} +#endif + static const struct pinctrl_ops imx8m_pinctrl_ops = { +#if CONFIG_IS_ENABLED(CMD_PINMUX) + .get_pin_name = imx8m_get_pin_name, + .get_pins_count = imx8m_get_pins_count, + .get_pin_muxing = imx8m_get_pin_muxing, +#endif .set_state = imx_pinctrl_set_state_mmio, }; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mm.c b/drivers/pinctrl/nxp/pinctrl-imx8mm.c new file mode 100644 index 00000000000..9aa2303b618 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mm.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mm_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + RESERVE5 = 5, + RESERVE6 = 6, + RESERVE7 = 7, + RESERVE8 = 8, + RESERVE9 = 9, + GPIO1_IO00 = 10, + GPIO1_IO01 = 11, + GPIO1_IO02 = 12, + GPIO1_IO03 = 13, + GPIO1_IO04 = 14, + GPIO1_IO05 = 15, + GPIO1_IO06 = 16, + GPIO1_IO07 = 17, + GPIO1_IO08 = 18, + GPIO1_IO09 = 19, + GPIO1_IO10 = 20, + GPIO1_IO11 = 21, + GPIO1_IO12 = 22, + GPIO1_IO13 = 23, + GPIO1_IO14 = 24, + GPIO1_IO15 = 25, + ENET_MDC = 26, + ENET_MDIO = 27, + ENET_TD3 = 28, + ENET_TD2 = 29, + ENET_TD1 = 30, + ENET_TD0 = 31, + ENET_TX_CTL = 32, + ENET_TXC = 33, + ENET_RX_CTL = 34, + ENET_RXC = 35, + ENET_RD0 = 36, + ENET_RD1 = 37, + ENET_RD2 = 38, + ENET_RD3 = 39, + SD1_CLK = 40, + SD1_CMD = 41, + SD1_DATA0 = 42, + SD1_DATA1 = 43, + SD1_DATA2 = 44, + SD1_DATA3 = 45, + SD1_DATA4 = 46, + SD1_DATA5 = 47, + SD1_DATA6 = 48, + SD1_DATA7 = 49, + SD1_RESET_B = 50, + SD1_STROBE = 51, + SD2_CD_B = 52, + SD2_CLK = 53, + SD2_CMD = 54, + SD2_DATA0 = 55, + SD2_DATA1 = 56, + SD2_DATA2 = 57, + SD2_DATA3 = 58, + SD2_RESET_B = 59, + SD2_WP = 60, + NAND_ALE = 61, + NAND_CE0 = 62, + NAND_CE1 = 63, + NAND_CE2 = 64, + NAND_CE3 = 65, + NAND_CLE = 66, + NAND_DATA00 = 67, + NAND_DATA01 = 68, + NAND_DATA02 = 69, + NAND_DATA03 = 70, + NAND_DATA04 = 71, + NAND_DATA05 = 72, + NAND_DATA06 = 73, + NAND_DATA07 = 74, + NAND_DQS = 75, + NAND_RE_B = 76, + NAND_READY_B = 77, + NAND_WE_B = 78, + NAND_WP_B = 79, + SAI5_RXFS = 80, + SAI5_RXC = 81, + SAI5_RXD0 = 82, + SAI5_RXD1 = 83, + SAI5_RXD2 = 84, + SAI5_RXD3 = 85, + SAI5_MCLK = 86, + SAI1_RXFS = 87, + SAI1_RXC = 88, + SAI1_RXD0 = 89, + SAI1_RXD1 = 90, + SAI1_RXD2 = 91, + SAI1_RXD3 = 92, + SAI1_RXD4 = 93, + SAI1_RXD5 = 94, + SAI1_RXD6 = 95, + SAI1_RXD7 = 96, + SAI1_TXFS = 97, + SAI1_TXC = 98, + SAI1_TXD0 = 99, + SAI1_TXD1 = 100, + SAI1_TXD2 = 101, + SAI1_TXD3 = 102, + SAI1_TXD4 = 103, + SAI1_TXD5 = 104, + SAI1_TXD6 = 105, + SAI1_TXD7 = 106, + SAI1_MCLK = 107, + SAI2_RXFS = 108, + SAI2_RXC = 109, + SAI2_RXD0 = 110, + SAI2_TXFS = 111, + SAI2_TXC = 112, + SAI2_TXD0 = 113, + SAI2_MCLK = 114, + SAI3_RXFS = 115, + SAI3_RXC = 116, + SAI3_RXD = 117, + SAI3_TXFS = 118, + SAI3_TXC = 119, + SAI3_TXD = 120, + SAI3_MCLK = 121, + SPDIF_TX = 122, + SPDIF_RX = 123, + SPDIF_EXT_CLK = 124, + ECSPI1_SCLK = 125, + ECSPI1_MOSI = 126, + ECSPI1_MISO = 127, + ECSPI1_SS0 = 128, + ECSPI2_SCLK = 129, + ECSPI2_MOSI = 130, + ECSPI2_MISO = 131, + ECSPI2_SS0 = 132, + I2C1_SCL = 133, + I2C1_SDA = 134, + I2C2_SCL = 135, + I2C2_SDA = 136, + I2C3_SCL = 137, + I2C3_SDA = 138, + I2C4_SCL = 139, + I2C4_SDA = 140, + UART1_RXD = 141, + UART1_TXD = 142, + UART2_RXD = 143, + UART2_TXD = 144, + UART3_RXD = 145, + UART3_TXD = 146, + UART4_RXD = 147, + UART4_TXD = 148, +}; + +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(RESERVE5), + IMX_PINCTRL_PIN(RESERVE6), + IMX_PINCTRL_PIN(RESERVE7), + IMX_PINCTRL_PIN(RESERVE8), + IMX_PINCTRL_PIN(RESERVE9), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0), + IMX_PINCTRL_PIN(NAND_CE1), + IMX_PINCTRL_PIN(NAND_CE2), + IMX_PINCTRL_PIN(NAND_CE3), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mn.c b/drivers/pinctrl/nxp/pinctrl-imx8mn.c new file mode 100644 index 00000000000..a3e22cf72ee --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mn.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mn_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + RESERVE5 = 5, + RESERVE6 = 6, + RESERVE7 = 7, + BOOT_MODE2 = 8, + BOOT_MODE3 = 9, + GPIO1_IO00 = 10, + GPIO1_IO01 = 11, + GPIO1_IO02 = 12, + GPIO1_IO03 = 13, + GPIO1_IO04 = 14, + GPIO1_IO05 = 15, + GPIO1_IO06 = 16, + GPIO1_IO07 = 17, + GPIO1_IO08 = 18, + GPIO1_IO09 = 19, + GPIO1_IO10 = 20, + GPIO1_IO11 = 21, + GPIO1_IO12 = 22, + GPIO1_IO13 = 23, + GPIO1_IO14 = 24, + GPIO1_IO15 = 25, + ENET_MDC = 26, + ENET_MDIO = 27, + ENET_TD3 = 28, + ENET_TD2 = 29, + ENET_TD1 = 30, + ENET_TD0 = 31, + ENET_TX_CTL = 32, + ENET_TXC = 33, + ENET_RX_CTL = 34, + ENET_RXC = 35, + ENET_RD0 = 36, + ENET_RD1 = 37, + ENET_RD2 = 38, + ENET_RD3 = 39, + SD1_CLK = 40, + SD1_CMD = 41, + SD1_DATA0 = 42, + SD1_DATA1 = 43, + SD1_DATA2 = 44, + SD1_DATA3 = 45, + SD1_DATA4 = 46, + SD1_DATA5 = 47, + SD1_DATA6 = 48, + SD1_DATA7 = 49, + SD1_RESET_B = 50, + SD1_STROBE = 51, + SD2_CD_B = 52, + SD2_CLK = 53, + SD2_CMD = 54, + SD2_DATA0 = 55, + SD2_DATA1 = 56, + SD2_DATA2 = 57, + SD2_DATA3 = 58, + SD2_RESET_B = 59, + SD2_WP = 60, + NAND_ALE = 61, + NAND_CE0 = 62, + NAND_CE1 = 63, + NAND_CE2 = 64, + NAND_CE3 = 65, + NAND_CLE = 66, + NAND_DATA00 = 67, + NAND_DATA01 = 68, + NAND_DATA02 = 69, + NAND_DATA03 = 70, + NAND_DATA04 = 71, + NAND_DATA05 = 72, + NAND_DATA06 = 73, + NAND_DATA07 = 74, + NAND_DQS = 75, + NAND_RE_B = 76, + NAND_READY_B = 77, + NAND_WE_B = 78, + NAND_WP_B = 79, + SAI5_RXFS = 80, + SAI5_RXC = 81, + SAI5_RXD0 = 82, + SAI5_RXD1 = 83, + SAI5_RXD2 = 84, + SAI5_RXD3 = 85, + SAI5_MCLK = 86, + SAI1_RXFS = 87, + SAI1_RXC = 88, + SAI1_RXD0 = 89, + SAI1_RXD1 = 90, + SAI1_RXD2 = 91, + SAI1_RXD3 = 92, + SAI1_RXD4 = 93, + SAI1_RXD5 = 94, + SAI1_RXD6 = 95, + SAI1_RXD7 = 96, + SAI1_TXFS = 97, + SAI1_TXC = 98, + SAI1_TXD0 = 99, + SAI1_TXD1 = 100, + SAI1_TXD2 = 101, + SAI1_TXD3 = 102, + SAI1_TXD4 = 103, + SAI1_TXD5 = 104, + SAI1_TXD6 = 105, + SAI1_TXD7 = 106, + SAI1_MCLK = 107, + SAI2_RXFS = 108, + SAI2_RXC = 109, + SAI2_RXD0 = 110, + SAI2_TXFS = 111, + SAI2_TXC = 112, + SAI2_TXD0 = 113, + SAI2_MCLK = 114, + SAI3_RXFS = 115, + SAI3_RXC = 116, + SAI3_RXD = 117, + SAI3_TXFS = 118, + SAI3_TXC = 119, + SAI3_TXD = 120, + SAI3_MCLK = 121, + SPDIF_TX = 122, + SPDIF_RX = 123, + SPDIF_EXT_CLK = 124, + ECSPI1_SCLK = 125, + ECSPI1_MOSI = 126, + ECSPI1_MISO = 127, + ECSPI1_SS0 = 128, + ECSPI2_SCLK = 129, + ECSPI2_MOSI = 130, + ECSPI2_MISO = 131, + ECSPI2_SS0 = 132, + I2C1_SCL = 133, + I2C1_SDA = 134, + I2C2_SCL = 135, + I2C2_SDA = 136, + I2C3_SCL = 137, + I2C3_SDA = 138, + I2C4_SCL = 139, + I2C4_SDA = 140, + UART1_RXD = 141, + UART1_TXD = 142, + UART2_RXD = 143, + UART2_TXD = 144, + UART3_RXD = 145, + UART3_TXD = 146, + UART4_RXD = 147, + UART4_TXD = 148, +}; + +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(RESERVE5), + IMX_PINCTRL_PIN(RESERVE6), + IMX_PINCTRL_PIN(RESERVE7), + IMX_PINCTRL_PIN(BOOT_MODE2), + IMX_PINCTRL_PIN(BOOT_MODE3), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0), + IMX_PINCTRL_PIN(NAND_CE1), + IMX_PINCTRL_PIN(NAND_CE2), + IMX_PINCTRL_PIN(NAND_CE3), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mp.c b/drivers/pinctrl/nxp/pinctrl-imx8mp.c new file mode 100644 index 00000000000..7f02eba5355 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mp.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mp_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + GPIO1_IO00 = 5, + GPIO1_IO01 = 6, + GPIO1_IO02 = 7, + GPIO1_IO03 = 8, + GPIO1_IO04 = 9, + GPIO1_IO05 = 10, + GPIO1_IO06 = 11, + GPIO1_IO07 = 12, + GPIO1_IO08 = 13, + GPIO1_IO09 = 14, + GPIO1_IO10 = 15, + GPIO1_IO11 = 16, + GPIO1_IO12 = 17, + GPIO1_IO13 = 18, + GPIO1_IO14 = 19, + GPIO1_IO15 = 20, + ENET_MDC = 21, + ENET_MDIO = 22, + ENET_TD3 = 23, + ENET_TD2 = 24, + ENET_TD1 = 25, + ENET_TD0 = 26, + ENET_TX_CTL = 27, + ENET_TXC = 28, + ENET_RX_CTL = 29, + ENET_RXC = 30, + ENET_RD0 = 31, + ENET_RD1 = 32, + ENET_RD2 = 33, + ENET_RD3 = 34, + SD1_CLK = 35, + SD1_CMD = 36, + SD1_DATA0 = 37, + SD1_DATA1 = 38, + SD1_DATA2 = 39, + SD1_DATA3 = 40, + SD1_DATA4 = 41, + SD1_DATA5 = 42, + SD1_DATA6 = 43, + SD1_DATA7 = 44, + SD1_RESET_B = 45, + SD1_STROBE = 46, + SD2_CD_B = 47, + SD2_CLK = 48, + SD2_CMD = 49, + SD2_DATA0 = 50, + SD2_DATA1 = 51, + SD2_DATA2 = 52, + SD2_DATA3 = 53, + SD2_RESET_B = 54, + SD2_WP = 55, + NAND_ALE = 56, + NAND_CE0_B = 57, + NAND_CE1_B = 58, + NAND_CE2_B = 59, + NAND_CE3_B = 60, + NAND_CLE = 61, + NAND_DATA00 = 62, + NAND_DATA01 = 63, + NAND_DATA02 = 64, + NAND_DATA03 = 65, + NAND_DATA04 = 66, + NAND_DATA05 = 67, + NAND_DATA06 = 68, + NAND_DATA07 = 69, + NAND_DQS = 70, + NAND_RE_B = 71, + NAND_READY_B = 72, + NAND_WE_B = 73, + NAND_WP_B = 74, + SAI5_RXFS = 75, + SAI5_RXC = 76, + SAI5_RXD0 = 77, + SAI5_RXD1 = 78, + SAI5_RXD2 = 79, + SAI5_RXD3 = 80, + SAI5_MCLK = 81, + SAI1_RXFS = 82, + SAI1_RXC = 83, + SAI1_RXD0 = 84, + SAI1_RXD1 = 85, + SAI1_RXD2 = 86, + SAI1_RXD3 = 87, + SAI1_RXD4 = 88, + SAI1_RXD5 = 89, + SAI1_RXD6 = 90, + SAI1_RXD7 = 91, + SAI1_TXFS = 92, + SAI1_TXC = 93, + SAI1_TXD0 = 94, + SAI1_TXD1 = 95, + SAI1_TXD2 = 96, + SAI1_TXD3 = 97, + SAI1_TXD4 = 98, + SAI1_TXD5 = 99, + SAI1_TXD6 = 100, + SAI1_TXD7 = 101, + SAI1_MCLK = 102, + SAI2_RXFS = 103, + SAI2_RXC = 104, + SAI2_RXD0 = 105, + SAI2_TXFS = 106, + SAI2_TXC = 107, + SAI2_TXD0 = 108, + SAI2_MCLK = 109, + SAI3_RXFS = 110, + SAI3_RXC = 111, + SAI3_RXD = 112, + SAI3_TXFS = 113, + SAI3_TXC = 114, + SAI3_TXD = 115, + SAI3_MCLK = 116, + SPDIF_TX = 117, + SPDIF_RX = 118, + SPDIF_EXT_CLK = 119, + ECSPI1_SCLK = 120, + ECSPI1_MOSI = 121, + ECSPI1_MISO = 122, + ECSPI1_SS0 = 123, + ECSPI2_SCLK = 124, + ECSPI2_MOSI = 125, + ECSPI2_MISO = 126, + ECSPI2_SS0 = 127, + I2C1_SCL = 128, + I2C1_SDA = 129, + I2C2_SCL = 130, + I2C2_SDA = 131, + I2C3_SCL = 132, + I2C3_SDA = 133, + I2C4_SCL = 134, + I2C4_SDA = 135, + UART1_RXD = 136, + UART1_TXD = 137, + UART2_RXD = 138, + UART2_TXD = 139, + UART3_RXD = 140, + UART3_TXD = 141, + UART4_RXD = 142, + UART4_TXD = 143, + HDMI_DDC_SCL = 144, + HDMI_DDC_SDA = 145, + HDMI_CEC = 146, + HDMI_HPD = 147, +}; + +/* Pad names for the pinmux subsystem */ +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0_B), + IMX_PINCTRL_PIN(NAND_CE1_B), + IMX_PINCTRL_PIN(NAND_CE2_B), + IMX_PINCTRL_PIN(NAND_CE3_B), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), + IMX_PINCTRL_PIN(HDMI_DDC_SCL), + IMX_PINCTRL_PIN(HDMI_DDC_SDA), + IMX_PINCTRL_PIN(HDMI_CEC), + IMX_PINCTRL_PIN(HDMI_HPD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mq.c b/drivers/pinctrl/nxp/pinctrl-imx8mq.c new file mode 100644 index 00000000000..bcc3e8ecbcf --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx8mq.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx8mq_pads { + RESERVE0 = 0, + RESERVE1 = 1, + RESERVE2 = 2, + RESERVE3 = 3, + RESERVE4 = 4, + PMIC_STBY_REQ_CCMSRCGPCMIX = 5, + PMIC_ON_REQ_SNVSMIX = 6, + ONOFF_SNVSMIX = 7, + POR_B_SNVSMIX = 8, + RTC_RESET_B_SNVSMIX = 9, + GPIO1_IO00 = 10, + GPIO1_IO01 = 11, + GPIO1_IO02 = 12, + GPIO1_IO03 = 13, + GPIO1_IO04 = 14, + GPIO1_IO05 = 15, + GPIO1_IO06 = 16, + GPIO1_IO07 = 17, + GPIO1_IO08 = 18, + GPIO1_IO09 = 19, + GPIO1_IO10 = 20, + GPIO1_IO11 = 21, + GPIO1_IO12 = 22, + GPIO1_IO13 = 23, + GPIO1_IO14 = 24, + GPIO1_IO15 = 25, + ENET_MDC = 26, + ENET_MDIO = 27, + ENET_TD3 = 28, + ENET_TD2 = 29, + ENET_TD1 = 30, + ENET_TD0 = 31, + ENET_TX_CTL = 32, + ENET_TXC = 33, + ENET_RX_CTL = 34, + ENET_RXC = 35, + ENET_RD0 = 36, + ENET_RD1 = 37, + ENET_RD2 = 38, + ENET_RD3 = 39, + SD1_CLK = 40, + SD1_CMD = 41, + SD1_DATA0 = 42, + SD1_DATA1 = 43, + SD1_DATA2 = 44, + SD1_DATA3 = 45, + SD1_DATA4 = 46, + SD1_DATA5 = 47, + SD1_DATA6 = 48, + SD1_DATA7 = 49, + SD1_RESET_B = 50, + SD1_STROBE = 51, + SD2_CD_B = 52, + SD2_CLK = 53, + SD2_CMD = 54, + SD2_DATA0 = 55, + SD2_DATA1 = 56, + SD2_DATA2 = 57, + SD2_DATA3 = 58, + SD2_RESET_B = 59, + SD2_WP = 60, + NAND_ALE = 61, + NAND_CE0_B = 62, + NAND_CE1_B = 63, + NAND_CE2_B = 64, + NAND_CE3_B = 65, + NAND_CLE = 66, + NAND_DATA00 = 67, + NAND_DATA01 = 68, + NAND_DATA02 = 69, + NAND_DATA03 = 70, + NAND_DATA04 = 71, + NAND_DATA05 = 72, + NAND_DATA06 = 73, + NAND_DATA07 = 74, + NAND_DQS = 75, + NAND_RE_B = 76, + NAND_READY_B = 77, + NAND_WE_B = 78, + NAND_WP_B = 79, + SAI5_RXFS = 80, + SAI5_RXC = 81, + SAI5_RXD0 = 82, + SAI5_RXD1 = 83, + SAI5_RXD2 = 84, + SAI5_RXD3 = 85, + SAI5_MCLK = 86, + SAI1_RXFS = 87, + SAI1_RXC = 88, + SAI1_RXD0 = 89, + SAI1_RXD1 = 90, + SAI1_RXD2 = 91, + SAI1_RXD3 = 92, + SAI1_RXD4 = 93, + SAI1_RXD5 = 94, + SAI1_RXD6 = 95, + SAI1_RXD7 = 96, + SAI1_TXFS = 97, + SAI1_TXC = 98, + SAI1_TXD0 = 99, + SAI1_TXD1 = 100, + SAI1_TXD2 = 101, + SAI1_TXD3 = 102, + SAI1_TXD4 = 103, + SAI1_TXD5 = 104, + SAI1_TXD6 = 105, + SAI1_TXD7 = 106, + SAI1_MCLK = 107, + SAI2_RXFS = 108, + SAI2_RXC = 109, + SAI2_RXD0 = 110, + SAI2_TXFS = 111, + SAI2_TXC = 112, + SAI2_TXD0 = 113, + SAI2_MCLK = 114, + SAI3_RXFS = 115, + SAI3_RXC = 116, + SAI3_RXD = 117, + SAI3_TXFS = 118, + SAI3_TXC = 119, + SAI3_TXD = 120, + SAI3_MCLK = 121, + SPDIF_TX = 122, + SPDIF_RX = 123, + SPDIF_EXT_CLK = 124, + ECSPI1_SCLK = 125, + ECSPI1_MOSI = 126, + ECSPI1_MISO = 127, + ECSPI1_SS0 = 128, + ECSPI2_SCLK = 129, + ECSPI2_MOSI = 130, + ECSPI2_MISO = 131, + ECSPI2_SS0 = 132, + I2C1_SCL = 133, + I2C1_SDA = 134, + I2C2_SCL = 135, + I2C2_SDA = 136, + I2C3_SCL = 137, + I2C3_SDA = 138, + I2C4_SCL = 139, + I2C4_SDA = 140, + UART1_RXD = 141, + UART1_TXD = 142, + UART2_RXD = 143, + UART2_TXD = 144, + UART3_RXD = 145, + UART3_TXD = 146, + UART4_RXD = 147, + UART4_TXD = 148, +}; + +static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = { + IMX_PINCTRL_PIN(RESERVE0), + IMX_PINCTRL_PIN(RESERVE1), + IMX_PINCTRL_PIN(RESERVE2), + IMX_PINCTRL_PIN(RESERVE3), + IMX_PINCTRL_PIN(RESERVE4), + IMX_PINCTRL_PIN(PMIC_STBY_REQ_CCMSRCGPCMIX), + IMX_PINCTRL_PIN(PMIC_ON_REQ_SNVSMIX), + IMX_PINCTRL_PIN(ONOFF_SNVSMIX), + IMX_PINCTRL_PIN(POR_B_SNVSMIX), + IMX_PINCTRL_PIN(RTC_RESET_B_SNVSMIX), + IMX_PINCTRL_PIN(GPIO1_IO00), + IMX_PINCTRL_PIN(GPIO1_IO01), + IMX_PINCTRL_PIN(GPIO1_IO02), + IMX_PINCTRL_PIN(GPIO1_IO03), + IMX_PINCTRL_PIN(GPIO1_IO04), + IMX_PINCTRL_PIN(GPIO1_IO05), + IMX_PINCTRL_PIN(GPIO1_IO06), + IMX_PINCTRL_PIN(GPIO1_IO07), + IMX_PINCTRL_PIN(GPIO1_IO08), + IMX_PINCTRL_PIN(GPIO1_IO09), + IMX_PINCTRL_PIN(GPIO1_IO10), + IMX_PINCTRL_PIN(GPIO1_IO11), + IMX_PINCTRL_PIN(GPIO1_IO12), + IMX_PINCTRL_PIN(GPIO1_IO13), + IMX_PINCTRL_PIN(GPIO1_IO14), + IMX_PINCTRL_PIN(GPIO1_IO15), + IMX_PINCTRL_PIN(ENET_MDC), + IMX_PINCTRL_PIN(ENET_MDIO), + IMX_PINCTRL_PIN(ENET_TD3), + IMX_PINCTRL_PIN(ENET_TD2), + IMX_PINCTRL_PIN(ENET_TD1), + IMX_PINCTRL_PIN(ENET_TD0), + IMX_PINCTRL_PIN(ENET_TX_CTL), + IMX_PINCTRL_PIN(ENET_TXC), + IMX_PINCTRL_PIN(ENET_RX_CTL), + IMX_PINCTRL_PIN(ENET_RXC), + IMX_PINCTRL_PIN(ENET_RD0), + IMX_PINCTRL_PIN(ENET_RD1), + IMX_PINCTRL_PIN(ENET_RD2), + IMX_PINCTRL_PIN(ENET_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_RESET_B), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(SD2_WP), + IMX_PINCTRL_PIN(NAND_ALE), + IMX_PINCTRL_PIN(NAND_CE0_B), + IMX_PINCTRL_PIN(NAND_CE1_B), + IMX_PINCTRL_PIN(NAND_CE2_B), + IMX_PINCTRL_PIN(NAND_CE3_B), + IMX_PINCTRL_PIN(NAND_CLE), + IMX_PINCTRL_PIN(NAND_DATA00), + IMX_PINCTRL_PIN(NAND_DATA01), + IMX_PINCTRL_PIN(NAND_DATA02), + IMX_PINCTRL_PIN(NAND_DATA03), + IMX_PINCTRL_PIN(NAND_DATA04), + IMX_PINCTRL_PIN(NAND_DATA05), + IMX_PINCTRL_PIN(NAND_DATA06), + IMX_PINCTRL_PIN(NAND_DATA07), + IMX_PINCTRL_PIN(NAND_DQS), + IMX_PINCTRL_PIN(NAND_RE_B), + IMX_PINCTRL_PIN(NAND_READY_B), + IMX_PINCTRL_PIN(NAND_WE_B), + IMX_PINCTRL_PIN(NAND_WP_B), + IMX_PINCTRL_PIN(SAI5_RXFS), + IMX_PINCTRL_PIN(SAI5_RXC), + IMX_PINCTRL_PIN(SAI5_RXD0), + IMX_PINCTRL_PIN(SAI5_RXD1), + IMX_PINCTRL_PIN(SAI5_RXD2), + IMX_PINCTRL_PIN(SAI5_RXD3), + IMX_PINCTRL_PIN(SAI5_MCLK), + IMX_PINCTRL_PIN(SAI1_RXFS), + IMX_PINCTRL_PIN(SAI1_RXC), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(SAI1_RXD1), + IMX_PINCTRL_PIN(SAI1_RXD2), + IMX_PINCTRL_PIN(SAI1_RXD3), + IMX_PINCTRL_PIN(SAI1_RXD4), + IMX_PINCTRL_PIN(SAI1_RXD5), + IMX_PINCTRL_PIN(SAI1_RXD6), + IMX_PINCTRL_PIN(SAI1_RXD7), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_TXD1), + IMX_PINCTRL_PIN(SAI1_TXD2), + IMX_PINCTRL_PIN(SAI1_TXD3), + IMX_PINCTRL_PIN(SAI1_TXD4), + IMX_PINCTRL_PIN(SAI1_TXD5), + IMX_PINCTRL_PIN(SAI1_TXD6), + IMX_PINCTRL_PIN(SAI1_TXD7), + IMX_PINCTRL_PIN(SAI1_MCLK), + IMX_PINCTRL_PIN(SAI2_RXFS), + IMX_PINCTRL_PIN(SAI2_RXC), + IMX_PINCTRL_PIN(SAI2_RXD0), + IMX_PINCTRL_PIN(SAI2_TXFS), + IMX_PINCTRL_PIN(SAI2_TXC), + IMX_PINCTRL_PIN(SAI2_TXD0), + IMX_PINCTRL_PIN(SAI2_MCLK), + IMX_PINCTRL_PIN(SAI3_RXFS), + IMX_PINCTRL_PIN(SAI3_RXC), + IMX_PINCTRL_PIN(SAI3_RXD), + IMX_PINCTRL_PIN(SAI3_TXFS), + IMX_PINCTRL_PIN(SAI3_TXC), + IMX_PINCTRL_PIN(SAI3_TXD), + IMX_PINCTRL_PIN(SAI3_MCLK), + IMX_PINCTRL_PIN(SPDIF_TX), + IMX_PINCTRL_PIN(SPDIF_RX), + IMX_PINCTRL_PIN(SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(ECSPI1_SCLK), + IMX_PINCTRL_PIN(ECSPI1_MOSI), + IMX_PINCTRL_PIN(ECSPI1_MISO), + IMX_PINCTRL_PIN(ECSPI1_SS0), + IMX_PINCTRL_PIN(ECSPI2_SCLK), + IMX_PINCTRL_PIN(ECSPI2_MOSI), + IMX_PINCTRL_PIN(ECSPI2_MISO), + IMX_PINCTRL_PIN(ECSPI2_SS0), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(I2C3_SCL), + IMX_PINCTRL_PIN(I2C3_SDA), + IMX_PINCTRL_PIN(I2C4_SCL), + IMX_PINCTRL_PIN(I2C4_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(UART3_RXD), + IMX_PINCTRL_PIN(UART3_TXD), + IMX_PINCTRL_PIN(UART4_RXD), + IMX_PINCTRL_PIN(UART4_TXD), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx9.c b/drivers/pinctrl/nxp/pinctrl-imx9.c new file mode 100644 index 00000000000..de22e29e953 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx9.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx9_pinctrl_soc_info __section(".data") = { + .flags = ZERO_OFFSET_VALID, +}; + +static const struct udevice_id imx9_pinctrl_match[] = { +#if IS_ENABLED(CONFIG_IMX93) + { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx9_pinctrl_soc_info }, +#endif +#if IS_ENABLED(CONFIG_IMX91) + { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx9_pinctrl_soc_info }, +#endif + { /* sentinel */ } +}; + +#if CONFIG_IS_ENABLED(CMD_PINMUX) + +#if IS_ENABLED(CONFIG_IMX93) +#include "pinctrl-imx93.c" +#elif IS_ENABLED(CONFIG_IMX91) +#include "pinctrl-imx91.c" +#endif + +static int imx9_get_pins_count(struct udevice *dev) +{ + return ARRAY_SIZE(imx9_pinctrl_pads); +} + +static const char *imx9_get_pin_name(struct udevice *dev, unsigned int selector) +{ + /* sanity checking */ + if (selector != imx9_pinctrl_pads[selector].number) { + dev_err(dev, + "selector(%u) not match with imx9_pinctrl_pads[selector].number(%u)\n", + selector, imx9_pinctrl_pads[selector].number); + return NULL; + } + + return imx9_pinctrl_pads[selector].name; +} + +static int imx9_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + u32 mux_reg = selector << 2; + u32 mux_mode = readl(info->base + mux_reg); + u32 sion = mux_mode >> 4; + + snprintf(buf, size, "Function(%d) SION(%d) at: 0x%p", mux_mode & 0x7, sion, + info->base + mux_reg); + + return 0; +} +#endif + +static const struct pinctrl_ops imx9_pinctrl_ops = { +#if CONFIG_IS_ENABLED(CMD_PINMUX) + .get_pin_name = imx9_get_pin_name, + .get_pins_count = imx9_get_pins_count, + .get_pin_muxing = imx9_get_pin_muxing, +#endif + .set_state = imx_pinctrl_set_state_mmio, +}; + +U_BOOT_DRIVER(imx9_pinctrl) = { + .name = "imx9-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx9_pinctrl_match), + .probe = imx_pinctrl_probe_mmio, + .remove = imx_pinctrl_remove_mmio, + .priv_auto = sizeof(struct imx_pinctrl_priv), + .ops = &imx9_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx91.c b/drivers/pinctrl/nxp/pinctrl-imx91.c new file mode 100644 index 00000000000..1dc63cda2fd --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx91.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "pinctrl-imx.h" + +enum imx91_pads { + DAP_TDI = 0, + DAP_TMS_SWDIO = 1, + DAP_TCLK_SWCLK = 2, + DAP_TDO_TRACESWO = 3, + GPIO_IO00 = 4, + GPIO_IO01 = 5, + GPIO_IO02 = 6, + GPIO_IO03 = 7, + GPIO_IO04 = 8, + GPIO_IO05 = 9, + GPIO_IO06 = 10, + GPIO_IO07 = 11, + GPIO_IO08 = 12, + GPIO_IO09 = 13, + GPIO_IO10 = 14, + GPIO_IO11 = 15, + GPIO_IO12 = 16, + GPIO_IO13 = 17, + GPIO_IO14 = 18, + GPIO_IO15 = 19, + GPIO_IO16 = 20, + GPIO_IO17 = 21, + GPIO_IO18 = 22, + GPIO_IO19 = 23, + GPIO_IO20 = 24, + GPIO_IO21 = 25, + GPIO_IO22 = 26, + GPIO_IO23 = 27, + GPIO_IO24 = 28, + GPIO_IO25 = 29, + GPIO_IO26 = 30, + GPIO_IO27 = 31, + GPIO_IO28 = 32, + GPIO_IO29 = 33, + CCM_CLKO1 = 34, + CCM_CLKO2 = 35, + CCM_CLKO3 = 36, + CCM_CLKO4 = 37, + ENET1_MDC = 38, + ENET1_MDIO = 39, + ENET1_TD3 = 40, + ENET1_TD2 = 41, + ENET1_TD1 = 42, + ENET1_TD0 = 43, + ENET1_TX_CTL = 44, + ENET1_TXC = 45, + ENET1_RX_CTL = 46, + ENET1_RXC = 47, + ENET1_RD0 = 48, + ENET1_RD1 = 49, + ENET1_RD2 = 50, + ENET1_RD3 = 51, + ENET2_MDC = 52, + ENET2_MDIO = 53, + ENET2_TD3 = 54, + ENET2_TD2 = 55, + ENET2_TD1 = 56, + ENET2_TD0 = 57, + ENET2_TX_CTL = 58, + ENET2_TXC = 59, + ENET2_RX_CTL = 60, + ENET2_RXC = 61, + ENET2_RD0 = 62, + ENET2_RD1 = 63, + ENET2_RD2 = 64, + ENET2_RD3 = 65, + SD1_CLK = 66, + SD1_CMD = 67, + SD1_DATA0 = 68, + SD1_DATA1 = 69, + SD1_DATA2 = 70, + SD1_DATA3 = 71, + SD1_DATA4 = 72, + SD1_DATA5 = 73, + SD1_DATA6 = 74, + SD1_DATA7 = 75, + SD1_STROBE = 76, + SD2_VSELECT = 77, + SD3_CLK = 78, + SD3_CMD = 79, + SD3_DATA0 = 80, + SD3_DATA1 = 81, + SD3_DATA2 = 82, + SD3_DATA3 = 83, + SD2_CD_B = 84, + SD2_CLK = 85, + SD2_CMD = 86, + SD2_DATA0 = 87, + SD2_DATA1 = 88, + SD2_DATA2 = 89, + SD2_DATA3 = 90, + SD2_RESET_B = 91, + I2C1_SCL = 92, + I2C1_SDA = 93, + I2C2_SCL = 94, + I2C2_SDA = 95, + UART1_RXD = 96, + UART1_TXD = 97, + UART2_RXD = 98, + UART2_TXD = 99, + PDM_CLK = 100, + PDM_BIT_STREAM0 = 101, + PDM_BIT_STREAM1 = 102, + SAI1_TXFS = 103, + SAI1_TXC = 104, + SAI1_TXD0 = 105, + SAI1_RXD0 = 106, + WDOG_ANY = 107, +}; + +static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = { + IMX_PINCTRL_PIN(DAP_TDI), + IMX_PINCTRL_PIN(DAP_TMS_SWDIO), + IMX_PINCTRL_PIN(DAP_TCLK_SWCLK), + IMX_PINCTRL_PIN(DAP_TDO_TRACESWO), + IMX_PINCTRL_PIN(GPIO_IO00), + IMX_PINCTRL_PIN(GPIO_IO01), + IMX_PINCTRL_PIN(GPIO_IO02), + IMX_PINCTRL_PIN(GPIO_IO03), + IMX_PINCTRL_PIN(GPIO_IO04), + IMX_PINCTRL_PIN(GPIO_IO05), + IMX_PINCTRL_PIN(GPIO_IO06), + IMX_PINCTRL_PIN(GPIO_IO07), + IMX_PINCTRL_PIN(GPIO_IO08), + IMX_PINCTRL_PIN(GPIO_IO09), + IMX_PINCTRL_PIN(GPIO_IO10), + IMX_PINCTRL_PIN(GPIO_IO11), + IMX_PINCTRL_PIN(GPIO_IO12), + IMX_PINCTRL_PIN(GPIO_IO13), + IMX_PINCTRL_PIN(GPIO_IO14), + IMX_PINCTRL_PIN(GPIO_IO15), + IMX_PINCTRL_PIN(GPIO_IO16), + IMX_PINCTRL_PIN(GPIO_IO17), + IMX_PINCTRL_PIN(GPIO_IO18), + IMX_PINCTRL_PIN(GPIO_IO19), + IMX_PINCTRL_PIN(GPIO_IO20), + IMX_PINCTRL_PIN(GPIO_IO21), + IMX_PINCTRL_PIN(GPIO_IO22), + IMX_PINCTRL_PIN(GPIO_IO23), + IMX_PINCTRL_PIN(GPIO_IO24), + IMX_PINCTRL_PIN(GPIO_IO25), + IMX_PINCTRL_PIN(GPIO_IO26), + IMX_PINCTRL_PIN(GPIO_IO27), + IMX_PINCTRL_PIN(GPIO_IO28), + IMX_PINCTRL_PIN(GPIO_IO29), + IMX_PINCTRL_PIN(CCM_CLKO1), + IMX_PINCTRL_PIN(CCM_CLKO2), + IMX_PINCTRL_PIN(CCM_CLKO3), + IMX_PINCTRL_PIN(CCM_CLKO4), + IMX_PINCTRL_PIN(ENET1_MDC), + IMX_PINCTRL_PIN(ENET1_MDIO), + IMX_PINCTRL_PIN(ENET1_TD3), + IMX_PINCTRL_PIN(ENET1_TD2), + IMX_PINCTRL_PIN(ENET1_TD1), + IMX_PINCTRL_PIN(ENET1_TD0), + IMX_PINCTRL_PIN(ENET1_TX_CTL), + IMX_PINCTRL_PIN(ENET1_TXC), + IMX_PINCTRL_PIN(ENET1_RX_CTL), + IMX_PINCTRL_PIN(ENET1_RXC), + IMX_PINCTRL_PIN(ENET1_RD0), + IMX_PINCTRL_PIN(ENET1_RD1), + IMX_PINCTRL_PIN(ENET1_RD2), + IMX_PINCTRL_PIN(ENET1_RD3), + IMX_PINCTRL_PIN(ENET2_MDC), + IMX_PINCTRL_PIN(ENET2_MDIO), + IMX_PINCTRL_PIN(ENET2_TD3), + IMX_PINCTRL_PIN(ENET2_TD2), + IMX_PINCTRL_PIN(ENET2_TD1), + IMX_PINCTRL_PIN(ENET2_TD0), + IMX_PINCTRL_PIN(ENET2_TX_CTL), + IMX_PINCTRL_PIN(ENET2_TXC), + IMX_PINCTRL_PIN(ENET2_RX_CTL), + IMX_PINCTRL_PIN(ENET2_RXC), + IMX_PINCTRL_PIN(ENET2_RD0), + IMX_PINCTRL_PIN(ENET2_RD1), + IMX_PINCTRL_PIN(ENET2_RD2), + IMX_PINCTRL_PIN(ENET2_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_VSELECT), + IMX_PINCTRL_PIN(SD3_CLK), + IMX_PINCTRL_PIN(SD3_CMD), + IMX_PINCTRL_PIN(SD3_DATA0), + IMX_PINCTRL_PIN(SD3_DATA1), + IMX_PINCTRL_PIN(SD3_DATA2), + IMX_PINCTRL_PIN(SD3_DATA3), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(PDM_CLK), + IMX_PINCTRL_PIN(PDM_BIT_STREAM0), + IMX_PINCTRL_PIN(PDM_BIT_STREAM1), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(WDOG_ANY), +}; diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c index 5d250db1081..d13969856f6 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx93.c +++ b/drivers/pinctrl/nxp/pinctrl-imx93.c @@ -1,34 +1,228 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2022 NXP + * Copyright 2026 NXP */ -#include -#include - #include "pinctrl-imx.h" -static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info __section(".data") = { - .flags = ZERO_OFFSET_VALID, +enum imx93_pads { + DAP_TDI = 0, + DAP_TMS_SWDIO = 1, + DAP_TCLK_SWCLK = 2, + DAP_TDO_TRACESWO = 3, + GPIO_IO00 = 4, + GPIO_IO01 = 5, + GPIO_IO02 = 6, + GPIO_IO03 = 7, + GPIO_IO04 = 8, + GPIO_IO05 = 9, + GPIO_IO06 = 10, + GPIO_IO07 = 11, + GPIO_IO08 = 12, + GPIO_IO09 = 13, + GPIO_IO10 = 14, + GPIO_IO11 = 15, + GPIO_IO12 = 16, + GPIO_IO13 = 17, + GPIO_IO14 = 18, + GPIO_IO15 = 19, + GPIO_IO16 = 20, + GPIO_IO17 = 21, + GPIO_IO18 = 22, + GPIO_IO19 = 23, + GPIO_IO20 = 24, + GPIO_IO21 = 25, + GPIO_IO22 = 26, + GPIO_IO23 = 27, + GPIO_IO24 = 28, + GPIO_IO25 = 29, + GPIO_IO26 = 30, + GPIO_IO27 = 31, + GPIO_IO28 = 32, + GPIO_IO29 = 33, + CCM_CLKO1 = 34, + CCM_CLKO2 = 35, + CCM_CLKO3 = 36, + CCM_CLKO4 = 37, + ENET1_MDC = 38, + ENET1_MDIO = 39, + ENET1_TD3 = 40, + ENET1_TD2 = 41, + ENET1_TD1 = 42, + ENET1_TD0 = 43, + ENET1_TX_CTL = 44, + ENET1_TXC = 45, + ENET1_RX_CTL = 46, + ENET1_RXC = 47, + ENET1_RD0 = 48, + ENET1_RD1 = 49, + ENET1_RD2 = 50, + ENET1_RD3 = 51, + ENET2_MDC = 52, + ENET2_MDIO = 53, + ENET2_TD3 = 54, + ENET2_TD2 = 55, + ENET2_TD1 = 56, + ENET2_TD0 = 57, + ENET2_TX_CTL = 58, + ENET2_TXC = 59, + ENET2_RX_CTL = 60, + ENET2_RXC = 61, + ENET2_RD0 = 62, + ENET2_RD1 = 63, + ENET2_RD2 = 64, + ENET2_RD3 = 65, + SD1_CLK = 66, + SD1_CMD = 67, + SD1_DATA0 = 68, + SD1_DATA1 = 69, + SD1_DATA2 = 70, + SD1_DATA3 = 71, + SD1_DATA4 = 72, + SD1_DATA5 = 73, + SD1_DATA6 = 74, + SD1_DATA7 = 75, + SD1_STROBE = 76, + SD2_VSELECT = 77, + SD3_CLK = 78, + SD3_CMD = 79, + SD3_DATA0 = 80, + SD3_DATA1 = 81, + SD3_DATA2 = 82, + SD3_DATA3 = 83, + SD2_CD_B = 84, + SD2_CLK = 85, + SD2_CMD = 86, + SD2_DATA0 = 87, + SD2_DATA1 = 88, + SD2_DATA2 = 89, + SD2_DATA3 = 90, + SD2_RESET_B = 91, + I2C1_SCL = 92, + I2C1_SDA = 93, + I2C2_SCL = 94, + I2C2_SDA = 95, + UART1_RXD = 96, + UART1_TXD = 97, + UART2_RXD = 98, + UART2_TXD = 99, + PDM_CLK = 100, + PDM_BIT_STREAM0 = 101, + PDM_BIT_STREAM1 = 102, + SAI1_TXFS = 103, + SAI1_TXC = 104, + SAI1_TXD0 = 105, + SAI1_RXD0 = 106, + WDOG_ANY = 107, }; -static const struct udevice_id imx93_pinctrl_match[] = { - { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, - { .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info }, - { /* sentinel */ } -}; - -static const struct pinctrl_ops imx93_pinctrl_ops = { - .set_state = imx_pinctrl_set_state_mmio, -}; - -U_BOOT_DRIVER(imx93_pinctrl) = { - .name = "imx93-pinctrl", - .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(imx93_pinctrl_match), - .probe = imx_pinctrl_probe_mmio, - .remove = imx_pinctrl_remove_mmio, - .priv_auto = sizeof(struct imx_pinctrl_priv), - .ops = &imx93_pinctrl_ops, - .flags = DM_FLAG_PRE_RELOC, +static const struct imx_pinctrl_pin_desc imx9_pinctrl_pads[] = { + IMX_PINCTRL_PIN(DAP_TDI), + IMX_PINCTRL_PIN(DAP_TMS_SWDIO), + IMX_PINCTRL_PIN(DAP_TCLK_SWCLK), + IMX_PINCTRL_PIN(DAP_TDO_TRACESWO), + IMX_PINCTRL_PIN(GPIO_IO00), + IMX_PINCTRL_PIN(GPIO_IO01), + IMX_PINCTRL_PIN(GPIO_IO02), + IMX_PINCTRL_PIN(GPIO_IO03), + IMX_PINCTRL_PIN(GPIO_IO04), + IMX_PINCTRL_PIN(GPIO_IO05), + IMX_PINCTRL_PIN(GPIO_IO06), + IMX_PINCTRL_PIN(GPIO_IO07), + IMX_PINCTRL_PIN(GPIO_IO08), + IMX_PINCTRL_PIN(GPIO_IO09), + IMX_PINCTRL_PIN(GPIO_IO10), + IMX_PINCTRL_PIN(GPIO_IO11), + IMX_PINCTRL_PIN(GPIO_IO12), + IMX_PINCTRL_PIN(GPIO_IO13), + IMX_PINCTRL_PIN(GPIO_IO14), + IMX_PINCTRL_PIN(GPIO_IO15), + IMX_PINCTRL_PIN(GPIO_IO16), + IMX_PINCTRL_PIN(GPIO_IO17), + IMX_PINCTRL_PIN(GPIO_IO18), + IMX_PINCTRL_PIN(GPIO_IO19), + IMX_PINCTRL_PIN(GPIO_IO20), + IMX_PINCTRL_PIN(GPIO_IO21), + IMX_PINCTRL_PIN(GPIO_IO22), + IMX_PINCTRL_PIN(GPIO_IO23), + IMX_PINCTRL_PIN(GPIO_IO24), + IMX_PINCTRL_PIN(GPIO_IO25), + IMX_PINCTRL_PIN(GPIO_IO26), + IMX_PINCTRL_PIN(GPIO_IO27), + IMX_PINCTRL_PIN(GPIO_IO28), + IMX_PINCTRL_PIN(GPIO_IO29), + IMX_PINCTRL_PIN(CCM_CLKO1), + IMX_PINCTRL_PIN(CCM_CLKO2), + IMX_PINCTRL_PIN(CCM_CLKO3), + IMX_PINCTRL_PIN(CCM_CLKO4), + IMX_PINCTRL_PIN(ENET1_MDC), + IMX_PINCTRL_PIN(ENET1_MDIO), + IMX_PINCTRL_PIN(ENET1_TD3), + IMX_PINCTRL_PIN(ENET1_TD2), + IMX_PINCTRL_PIN(ENET1_TD1), + IMX_PINCTRL_PIN(ENET1_TD0), + IMX_PINCTRL_PIN(ENET1_TX_CTL), + IMX_PINCTRL_PIN(ENET1_TXC), + IMX_PINCTRL_PIN(ENET1_RX_CTL), + IMX_PINCTRL_PIN(ENET1_RXC), + IMX_PINCTRL_PIN(ENET1_RD0), + IMX_PINCTRL_PIN(ENET1_RD1), + IMX_PINCTRL_PIN(ENET1_RD2), + IMX_PINCTRL_PIN(ENET1_RD3), + IMX_PINCTRL_PIN(ENET2_MDC), + IMX_PINCTRL_PIN(ENET2_MDIO), + IMX_PINCTRL_PIN(ENET2_TD3), + IMX_PINCTRL_PIN(ENET2_TD2), + IMX_PINCTRL_PIN(ENET2_TD1), + IMX_PINCTRL_PIN(ENET2_TD0), + IMX_PINCTRL_PIN(ENET2_TX_CTL), + IMX_PINCTRL_PIN(ENET2_TXC), + IMX_PINCTRL_PIN(ENET2_RX_CTL), + IMX_PINCTRL_PIN(ENET2_RXC), + IMX_PINCTRL_PIN(ENET2_RD0), + IMX_PINCTRL_PIN(ENET2_RD1), + IMX_PINCTRL_PIN(ENET2_RD2), + IMX_PINCTRL_PIN(ENET2_RD3), + IMX_PINCTRL_PIN(SD1_CLK), + IMX_PINCTRL_PIN(SD1_CMD), + IMX_PINCTRL_PIN(SD1_DATA0), + IMX_PINCTRL_PIN(SD1_DATA1), + IMX_PINCTRL_PIN(SD1_DATA2), + IMX_PINCTRL_PIN(SD1_DATA3), + IMX_PINCTRL_PIN(SD1_DATA4), + IMX_PINCTRL_PIN(SD1_DATA5), + IMX_PINCTRL_PIN(SD1_DATA6), + IMX_PINCTRL_PIN(SD1_DATA7), + IMX_PINCTRL_PIN(SD1_STROBE), + IMX_PINCTRL_PIN(SD2_VSELECT), + IMX_PINCTRL_PIN(SD3_CLK), + IMX_PINCTRL_PIN(SD3_CMD), + IMX_PINCTRL_PIN(SD3_DATA0), + IMX_PINCTRL_PIN(SD3_DATA1), + IMX_PINCTRL_PIN(SD3_DATA2), + IMX_PINCTRL_PIN(SD3_DATA3), + IMX_PINCTRL_PIN(SD2_CD_B), + IMX_PINCTRL_PIN(SD2_CLK), + IMX_PINCTRL_PIN(SD2_CMD), + IMX_PINCTRL_PIN(SD2_DATA0), + IMX_PINCTRL_PIN(SD2_DATA1), + IMX_PINCTRL_PIN(SD2_DATA2), + IMX_PINCTRL_PIN(SD2_DATA3), + IMX_PINCTRL_PIN(SD2_RESET_B), + IMX_PINCTRL_PIN(I2C1_SCL), + IMX_PINCTRL_PIN(I2C1_SDA), + IMX_PINCTRL_PIN(I2C2_SCL), + IMX_PINCTRL_PIN(I2C2_SDA), + IMX_PINCTRL_PIN(UART1_RXD), + IMX_PINCTRL_PIN(UART1_TXD), + IMX_PINCTRL_PIN(UART2_RXD), + IMX_PINCTRL_PIN(UART2_TXD), + IMX_PINCTRL_PIN(PDM_CLK), + IMX_PINCTRL_PIN(PDM_BIT_STREAM0), + IMX_PINCTRL_PIN(PDM_BIT_STREAM1), + IMX_PINCTRL_PIN(SAI1_TXFS), + IMX_PINCTRL_PIN(SAI1_TXC), + IMX_PINCTRL_PIN(SAI1_TXD0), + IMX_PINCTRL_PIN(SAI1_RXD0), + IMX_PINCTRL_PIN(WDOG_ANY), }; diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c index 85ab5fdf640..8b764738014 100644 --- a/drivers/pinctrl/nxp/pinctrl-mxs.c +++ b/drivers/pinctrl/nxp/pinctrl-mxs.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -15,8 +14,6 @@ #include #include "pinctrl-mxs.h" -DECLARE_GLOBAL_DATA_PTR; - struct mxs_pinctrl_priv { void __iomem *base; const struct mxs_regs *regs; diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c new file mode 100644 index 00000000000..63d4f8ffeb5 --- /dev/null +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct pinconf_param pinctrl_scmi_conf_params[] = { + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0}, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, + { "low-power-mode", PIN_CONFIG_LOW_POWER_MODE, 0 }, + { "output-mode", PIN_CONFIG_OUTPUT_ENABLE, 0 }, + { "output-value", PIN_CONFIG_OUTPUT, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, + /* The SCMI spec also include "default", "pull-mode" and "input-value */ +}; + +static bool valid_selector(struct udevice *dev, enum select_type select_type, u32 selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (select_type == SCMI_PIN) + return selector < priv->num_pins; + if (select_type == SCMI_GROUP) + return selector < priv->num_groups; + if (select_type == SCMI_FUNCTION) + return selector < priv->num_functions; + + return false; +} + +static int pinctrl_scmi_get_pins_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_pins; +} + +static int pinctrl_scmi_get_groups_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_groups; +} + +static int pinctrl_scmi_get_functions_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_functions; +} + +static const char *pinctrl_scmi_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_pins) + return NULL; + + return (const char *)priv->pin_info[selector].name; +} + +static const char *pinctrl_scmi_get_group_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_groups) + return NULL; + + return (const char *)priv->group_info[selector].name; +} + +static const char *pinctrl_scmi_get_function_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_functions) + return NULL; + + return (const char *)priv->function_info[selector].name; +} + +static int pinctrl_scmi_pinmux_set(struct udevice *dev, u32 pin, u32 function) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (pin >= priv->num_pins || function >= priv->num_functions) + return -EINVAL; + + return scmi_pinctrl_set_function(dev, SCMI_PIN, pin, function); +} + +static int pinctrl_scmi_pinmux_group_set(struct udevice *dev, u32 group, u32 function) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (group >= priv->num_groups || function >= priv->num_functions) + return -EINVAL; + + return scmi_pinctrl_set_function(dev, SCMI_GROUP, group, function); +} + +static int pinctrl_scmi_set_state(struct udevice *dev, struct udevice *config) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + /* batch the setup into 20 lines at a go (there are 5 u32s in a config) */ + const int batch_count = 20 * 5; + u32 prev_type = -1u; + u32 prev_selector; + u32 *configs; + const u32 *prop; + int offset, cnt, len; + int ret = 0; + + prop = dev_read_prop(config, "pinmux", &len); + if (!prop) + return 0; + + if (len % sizeof(u32) * 5) { + dev_err(dev, "invalid pin configuration: len=%d\n", len); + return -FDT_ERR_BADSTRUCTURE; + } + + configs = kcalloc(batch_count, sizeof(u32), GFP_KERNEL); + if (!configs) + return -ENOMEM; + + offset = 0; + cnt = 0; + while (offset + 4 < len / sizeof(u32)) { + u32 select_type = fdt32_to_cpu(prop[offset]); + u32 selector = fdt32_to_cpu(prop[offset + 1]); + u32 function = fdt32_to_cpu(prop[offset + 2]); + u32 config_type = fdt32_to_cpu(prop[offset + 3]); + u32 config_value = fdt32_to_cpu(prop[offset + 4]); + + if (select_type > SCMI_GROUP || + !valid_selector(dev, select_type, selector) || + (function != SCMI_PINCTRL_FUNCTION_NONE && + function > priv->num_functions)) { + dev_err(dev, "invalid pinctrl data (%u %u %u %u %u)\n", + select_type, selector, function, config_type, + config_value); + ret = -EINVAL; + goto free; + } + + if (function != SCMI_PINCTRL_FUNCTION_NONE) { + if (cnt) { + ret = scmi_pinctrl_settings_configure(dev, + prev_type, + prev_selector, + cnt / 2, configs); + if (ret) + goto free; + prev_type = -1u; + cnt = 0; + } + scmi_pinctrl_set_function(dev, select_type, selector, function); + offset += 5; + continue; + } + + if (cnt == batch_count) + goto set; + + if (prev_type == -1u) + goto store; + + if (select_type == prev_type && selector == prev_selector) + goto store; +set: + ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, + cnt / 2, configs); + if (ret) + goto free; + cnt = 0; +store: + prev_type = select_type; + prev_selector = selector; + configs[cnt++] = config_type; + configs[cnt++] = config_value; + offset += 5; + } + + if (cnt) + ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, + cnt / 2, configs); +free: + kfree(configs); + if (ret) + dev_err(dev, "set_state() failed: %d\n", ret); + + return ret; +} + +static int get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + u32 value; + int ret; + + ret = scmi_pinctrl_settings_get_one(dev, SCMI_PIN, selector, + SCMI_PIN_INPUT_VALUE, &value); + if (ret) { + dev_err(dev, "settings_get() failed: %d\n", ret); + return ret; + } + + snprintf(buf, size, "%d", value); + return 0; +} + +static int pinctrl_scmi_pinconf_set(struct udevice *dev, u32 pin, u32 param, u32 argument) +{ + return scmi_pinctrl_settings_configure_one(dev, SCMI_PIN, pin, param, argument); +} + +static int pinctrl_scmi_pinconf_group_set(struct udevice *dev, u32 group, u32 param, u32 argument) +{ + return scmi_pinctrl_settings_configure_one(dev, SCMI_GROUP, group, param, argument); +} + +static struct pinctrl_ops scmi_pinctrl_ops = { + .get_pins_count = pinctrl_scmi_get_pins_count, + .get_pin_name = pinctrl_scmi_get_pin_name, + + .get_groups_count = pinctrl_scmi_get_groups_count, + .get_group_name = pinctrl_scmi_get_group_name, + + .get_functions_count = pinctrl_scmi_get_functions_count, + .get_function_name = pinctrl_scmi_get_function_name, + + .pinmux_set = pinctrl_scmi_pinmux_set, + .pinmux_group_set = pinctrl_scmi_pinmux_group_set, + + .pinconf_num_params = ARRAY_SIZE(pinctrl_scmi_conf_params), + .pinconf_params = pinctrl_scmi_conf_params, + + .pinconf_set = pinctrl_scmi_pinconf_set, + .pinconf_group_set = pinctrl_scmi_pinconf_group_set, + .set_state = pinctrl_scmi_set_state, + .get_pin_muxing = get_pin_muxing, +}; + +static int scmi_pinctrl_probe(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + int ret; + int i; + + ret = devm_scmi_of_get_channel(dev); + if (ret) { + dev_err(dev, "get_channel() failed: %d\n", ret); + return ret; + } + + ret = scmi_pinctrl_protocol_attrs(dev, &priv->num_pins, + &priv->num_groups, + &priv->num_functions); + if (ret) { + dev_err(dev, "failed to get protocol attributes: %d\n", ret); + return ret; + } + + priv->pin_info = devm_kcalloc(dev, priv->num_pins, + sizeof(*priv->pin_info), GFP_KERNEL); + priv->group_info = devm_kcalloc(dev, priv->num_groups, + sizeof(*priv->group_info), GFP_KERNEL); + priv->function_info = devm_kcalloc(dev, priv->num_functions, + sizeof(*priv->function_info), GFP_KERNEL); + if (!priv->pin_info || !priv->group_info || !priv->function_info) + return -ENOMEM; + + for (i = 0; i < priv->num_pins; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_PIN, i, NULL, NULL, + priv->pin_info[i].name); + if (ret) + return ret; + } + + for (i = 0; i < priv->num_groups; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_GROUP, i, NULL, + &priv->group_info[i].num_pins, + priv->group_info[i].name); + if (ret) { + dev_err(dev, "loading group %d failed: %d\n", i, ret); + return ret; + } + priv->group_info[i].pins = devm_kcalloc(dev, + priv->group_info[i].num_pins, + sizeof(*priv->group_info[i].pins), + GFP_KERNEL); + if (!priv->group_info[i].pins) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(dev, SCMI_GROUP, i, + priv->group_info[i].pins, + priv->group_info[i].num_pins); + if (ret) { + dev_err(dev, "list association %d failed for group: %d\n", i, ret); + return ret; + } + } + + for (i = 0; i < priv->num_functions; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_FUNCTION, i, NULL, + &priv->function_info[i].num_groups, + priv->function_info[i].name); + if (ret) { + dev_err(dev, "loading function %d failed: %d\n", i, ret); + return ret; + } + priv->function_info[i].groups = devm_kcalloc(dev, + priv->function_info[i].num_groups, + sizeof(*priv->function_info[i].groups), + GFP_KERNEL); + if (!priv->function_info[i].groups) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(dev, SCMI_FUNCTION, i, + priv->function_info[i].groups, + priv->function_info[i].num_groups); + if (ret) { + dev_err(dev, "list association %d failed for function: %d\n", i, ret); + return ret; + } + } + + return 0; +} + +U_BOOT_DRIVER(pinctrl_scmi) = { + .name = "scmi_pinctrl", + .id = UCLASS_PINCTRL, + .ops = &scmi_pinctrl_ops, + .probe = scmi_pinctrl_probe, + .priv_auto = sizeof(struct pinctrl_scmi_priv), +}; + +static struct scmi_proto_match match[] = { + { .proto_id = SCMI_PROTOCOL_ID_PINCTRL }, + { /* Sentinel */ } +}; + +U_BOOT_SCMI_PROTO_DRIVER(pinctrl_scmi, match); + diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 7c11ac4c8b8..0b936684f8a 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -19,15 +19,11 @@ #include #include -#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12 -#define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12 -#define NUM_GROUPS_PER_RESP 6 -#define NA_GROUP -1 -#define RESERVED_GROUP -2 +#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN (sizeof(s16) * NUM_GROUPS_PER_RESP) +#define PINCTRL_GET_PIN_GROUPS_RESP_LEN (sizeof(s16) * NUM_GROUPS_PER_RESP) #define MAX_GROUP_PIN 50 #define MAX_PIN_GROUPS 50 #define MAX_GROUP_NAME_LEN 32 -#define MAX_FUNC_NAME_LEN 16 #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index e17415e1ca6..0405df128df 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3506) += pinctrl-rk3506.o obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3506.c b/drivers/pinctrl/rockchip/pinctrl-rk3506.c new file mode 100644 index 00000000000..969acb66f15 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3506.c @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include + +#include "pinctrl-rockchip.h" +#include + +static int rk3506_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, mask; + u8 bit; + u32 data, rmask; + + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else + regmap = priv->regmap_base; + + if (bank->bank_num == 1) + regmap = priv->regmap_ioc1; + else if (bank->bank_num == 4) + return 0; + + reg = bank->iomux[iomux_num].offset; + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + data = (mask << (bit + 16)); + rmask = data | (data >> 16); + data |= (mux & mask) << bit; + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3506_DRV_BITS_PER_PIN 8 +#define RK3506_DRV_PINS_PER_REG 2 +#define RK3506_DRV_GPIO0_A_OFFSET 0x100 +#define RK3506_DRV_GPIO0_D_OFFSET 0x830 +#define RK3506_DRV_GPIO1_OFFSET 0x140 +#define RK3506_DRV_GPIO2_OFFSET 0x180 +#define RK3506_DRV_GPIO3_OFFSET 0x1c0 +#define RK3506_DRV_GPIO4_OFFSET 0x840 + +static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = priv->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_DRV_GPIO0_A_OFFSET; + } else { + *reg = RK3506_DRV_GPIO0_D_OFFSET; + *bit = 3; + + return 0; + } + break; + + case 1: + *regmap = priv->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_DRV_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = priv->regmap_base; + if (pin_num < 17) + *reg = RK3506_DRV_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = priv->regmap_base; + if (pin_num < 15) + *reg = RK3506_DRV_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = priv->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_DRV_GPIO4_OFFSET; + *bit = 10; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + return ret; + } + + *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_DRV_PINS_PER_REG; + *bit *= RK3506_DRV_BITS_PER_PIN; + + return 0; +} + +static int rk3506_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret, i; + u32 data, rmask; + u8 bit; + int rmask_bits = RK3506_DRV_BITS_PER_PIN; + + ret = rk3506_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + + for (i = 0, ret = 1; i < strength; i++) + ret = (ret << 1) | 1; + + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + rmask_bits = 2; + ret = strength; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (ret << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3506_PULL_BITS_PER_PIN 2 +#define RK3506_PULL_PINS_PER_REG 8 +#define RK3506_PULL_GPIO0_A_OFFSET 0x200 +#define RK3506_PULL_GPIO0_D_OFFSET 0x830 +#define RK3506_PULL_GPIO1_OFFSET 0x210 +#define RK3506_PULL_GPIO2_OFFSET 0x220 +#define RK3506_PULL_GPIO3_OFFSET 0x230 +#define RK3506_PULL_GPIO4_OFFSET 0x840 + +static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = priv->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_PULL_GPIO0_A_OFFSET; + } else { + *reg = RK3506_PULL_GPIO0_D_OFFSET; + *bit = 5; + + return 0; + } + break; + + case 1: + *regmap = priv->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_PULL_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = priv->regmap_base; + if (pin_num < 17) + *reg = RK3506_PULL_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = priv->regmap_base; + if (pin_num < 15) + *reg = RK3506_PULL_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = priv->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_PULL_GPIO4_OFFSET; + *bit = 13; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + return ret; + } + + *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_PULL_PINS_PER_REG; + *bit *= RK3506_PULL_BITS_PER_PIN; + + return 0; +} + +static int rk3506_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data, rmask; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -EOPNOTSUPP; + + ret = rk3506_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + type = bank->pull_type[pin_num / 8]; + + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) + type = 1; + + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3506_PULL_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (ret << bit); + + return regmap_update_bits(regmap, reg, rmask, data); +} + +#define RK3506_SMT_BITS_PER_PIN 1 +#define RK3506_SMT_PINS_PER_REG 8 +#define RK3506_SMT_GPIO0_A_OFFSET 0x400 +#define RK3506_SMT_GPIO0_D_OFFSET 0x830 +#define RK3506_SMT_GPIO1_OFFSET 0x410 +#define RK3506_SMT_GPIO2_OFFSET 0x420 +#define RK3506_SMT_GPIO3_OFFSET 0x430 +#define RK3506_SMT_GPIO4_OFFSET 0x840 + +static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int ret = 0; + + switch (bank->bank_num) { + case 0: + *regmap = priv->regmap_pmu; + if (pin_num > 24) { + ret = -EINVAL; + } else if (pin_num < 24) { + *reg = RK3506_SMT_GPIO0_A_OFFSET; + } else { + *reg = RK3506_SMT_GPIO0_D_OFFSET; + *bit = 9; + + return 0; + } + break; + + case 1: + *regmap = priv->regmap_ioc1; + if (pin_num < 28) + *reg = RK3506_SMT_GPIO1_OFFSET; + else + ret = -EINVAL; + break; + + case 2: + *regmap = priv->regmap_base; + if (pin_num < 17) + *reg = RK3506_SMT_GPIO2_OFFSET; + else + ret = -EINVAL; + break; + + case 3: + *regmap = priv->regmap_base; + if (pin_num < 15) + *reg = RK3506_SMT_GPIO3_OFFSET; + else + ret = -EINVAL; + break; + + case 4: + *regmap = priv->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret = -EINVAL; + } else { + *reg = RK3506_SMT_GPIO4_OFFSET; + *bit = 8; + + return 0; + } + break; + + default: + ret = -EINVAL; + break; + } + + if (ret) { + debug("unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); + return ret; + } + + *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3506_SMT_PINS_PER_REG; + *bit *= RK3506_SMT_BITS_PER_PIN; + + return 0; +} + +static int rk3506_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg, ret; + u32 data, rmask; + u8 bit; + + ret = rk3506_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + if (ret) + return ret; + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3506_SMT_BITS_PER_PIN) - 1) << (bit + 16); + rmask = data | (data >> 16); + data |= (enable << bit); + + if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { + data = 0x3 << (bit + 16); + rmask = data | (data >> 16); + data |= ((enable ? 0x3 : 0) << bit); + } + + return regmap_update_bits(regmap, reg, rmask, data); +} + +static struct rockchip_mux_recalced_data rk3506_mux_recalced_data[] = { + { + .num = 0, + .pin = 24, + .reg = 0x830, + .bit = 0, + .mask = 0x3 + }, +}; + +static struct rockchip_pin_bank rk3506_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_8WIDTH_2BIT | IOMUX_SOURCE_PMU, + 0x0, 0x8, 0x10, 0x830), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0x28, 0x30, 0x38), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, 0x48, 0x50, 0x58), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x60, 0x68, 0x70, 0x78), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x80, 0x88, 0x90, 0x98), +}; + +static const struct rockchip_pin_ctrl rk3506_pin_ctrl = { + .pin_banks = rk3506_pin_banks, + .nr_banks = ARRAY_SIZE(rk3506_pin_banks), + .iomux_recalced = rk3506_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3506_mux_recalced_data), + .set_mux = rk3506_set_mux, + .set_pull = rk3506_set_pull, + .set_drive = rk3506_set_drive, + .set_schmitt = rk3506_set_schmitt, +}; + +static const struct udevice_id rk3506_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3506-pinctrl", + .data = (ulong)&rk3506_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_pinctrl) = { + .name = "rockchip_rk3506_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3506_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 4de67aba1c3..957dcb52059 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "pinctrl-rockchip.h" @@ -641,37 +642,30 @@ int rockchip_pinctrl_probe(struct udevice *dev) { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); struct rockchip_pin_ctrl *ctrl; - struct udevice *syscon; - struct regmap *regmap; - int ret = 0; - /* get rockchip grf syscon phandle */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", - &syscon); - if (ret) { - debug("unable to find rockchip,grf syscon device (%d)\n", ret); - return ret; + priv->regmap_base = + syscon_regmap_lookup_by_phandle(dev, "rockchip,grf"); + if (IS_ERR(priv->regmap_base)) { + debug("unable to find rockchip,grf regmap\n"); + return PTR_ERR(priv->regmap_base); } - /* get grf-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - debug("unable to find rockchip grf regmap\n"); - return -ENODEV; - } - priv->regmap_base = regmap; - - /* option: get pmu-reg base address */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", - &syscon); - if (!ret) { - /* get pmugrf-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - debug("unable to find rockchip pmu regmap\n"); - return -ENODEV; + if (dev_read_bool(dev, "rockchip,pmu")) { + priv->regmap_pmu = + syscon_regmap_lookup_by_phandle(dev, "rockchip,pmu"); + if (IS_ERR(priv->regmap_pmu)) { + debug("unable to find rockchip,pmu regmap\n"); + return PTR_ERR(priv->regmap_pmu); + } + } + + if (dev_read_bool(dev, "rockchip,ioc1")) { + priv->regmap_ioc1 = + syscon_regmap_lookup_by_phandle(dev, "rockchip,ioc1"); + if (IS_ERR(priv->regmap_ioc1)) { + debug("unable to find rockchip,ioc1 regmap\n"); + return PTR_ERR(priv->regmap_ioc1); } - priv->regmap_pmu = regmap; } ctrl = rockchip_pinctrl_get_soc_data(dev); diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index ba684baed24..568e6024b78 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -528,6 +528,7 @@ struct rockchip_pinctrl_priv { struct rockchip_pin_ctrl *ctrl; struct regmap *regmap_base; struct regmap *regmap_pmu; + struct regmap *regmap_ioc1; }; extern const struct pinctrl_ops rockchip_pinctrl_ops; diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 935f282d6c5..2f63a8e54e5 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -20,7 +20,7 @@ config APPLE_PMGR_POWER_DOMAIN config AGILEX5_PMGR_POWER_DOMAIN bool "Enable the Agilex5 PMGR power domain driver" - depends on SPL_POWER_DOMAIN && TARGET_SOCFPGA_SOC64 + depends on SPL_POWER_DOMAIN && ARCH_SOCFPGA_SOC64 help Enable support for power gating peripherals' SRAM specified in the handoff data values obtained from the bitstream to reduce diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index a7e64971a2a..1c731b897cc 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define GPC_PGC_CPU_MAPPING 0x0ec #define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index b1a5b1c2a1f..5bc14842e66 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -384,7 +384,7 @@ config DM_PMIC_TPS80031 config PMIC_STPMIC1 bool "Enable support for STMicroelectronics STPMIC1 PMIC" depends on DM_I2C - select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW + select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF && !ARM_PSCI_FW ---help--- The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. It is accessed via an I2C interface. The device is used with STM32MP1 @@ -433,6 +433,14 @@ config PMIC_RAA215300 support and several voltage regulators. For now, this driver simply allows register access and will bind the sysreset driver (CONFIG_SYSRESET_RAA215300) if it is enabled. + +config DM_PMIC_MTK_PWRAP + bool "Enable driver for MediaTek PMIC Wrapper Support" + help + Say yes here to add support for MediaTek PMIC Wrapper found + on different MediaTek SoCs. The PMIC wrapper is a proprietary + hardware to connect the PMIC. + endif config PMIC_TPS65217 diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 6bebffb05a6..2cda5a892fd 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PMIC_TPS65941) += tps65941.o obj-$(CONFIG_PMIC_RAA215300) += raa215300.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_$(PHASE_)DM_PMIC_CPCAP) += cpcap.o +obj-$(CONFIG_DM_PMIC_MTK_PWRAP) += mtk-pwrap.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c index a5df2570fc3..13642794765 100644 --- a/drivers/power/pmic/bd71837.c +++ b/drivers/power/pmic/bd71837.c @@ -7,14 +7,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = BD718XX_REGULATOR_DRIVER}, diff --git a/drivers/power/pmic/cpcap.c b/drivers/power/pmic/cpcap.c index f2076afff43..b9d783773ed 100644 --- a/drivers/power/pmic/cpcap.c +++ b/drivers/power/pmic/cpcap.c @@ -14,7 +14,9 @@ static const struct pmic_child_info pmic_children_info[] = { { .prefix = "sw", .driver = CPCAP_SW_DRIVER }, + { .prefix = "SW", .driver = CPCAP_SW_DRIVER }, { .prefix = "v", .driver = CPCAP_LDO_DRIVER }, + { .prefix = "V", .driver = CPCAP_LDO_DRIVER }, { }, }; @@ -112,6 +114,8 @@ static struct dm_pmic_ops cpcap_ops = { static const struct udevice_id cpcap_ids[] = { { .compatible = "motorola,cpcap" }, { .compatible = "st,6556002" }, + { .compatible = "motorola,mapphone-cpcap" }, + { .compatible = "motorola,mot-cpcap" }, { } }; diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c index c2a7cbf7e40..a06042e2918 100644 --- a/drivers/power/pmic/max77663.c +++ b/drivers/power/pmic/max77663.c @@ -46,7 +46,9 @@ static int max77663_bind(struct udevice *dev) ofnode regulators_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) { + if (IS_ENABLED(CONFIG_SYSRESET_MAX77663) && + (dev_read_bool(dev, "maxim,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER, "sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/max8907.c b/drivers/power/pmic/max8907.c index a7ef70177de..34bef0c8cd6 100644 --- a/drivers/power/pmic/max8907.c +++ b/drivers/power/pmic/max8907.c @@ -48,7 +48,8 @@ static int max8907_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_MAX8907) && - dev_read_bool(dev, "maxim,system-power-controller")) { + (dev_read_bool(dev, "maxim,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, MAX8907_RST_DRIVER, "sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/mc34708.c b/drivers/power/pmic/mc34708.c index 43badb5767a..0ec52e25a9e 100644 --- a/drivers/power/pmic/mc34708.c +++ b/drivers/power/pmic/mc34708.c @@ -9,11 +9,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static int mc34708_reg_count(struct udevice *dev) { return PMIC_NUM_OF_REGS; diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c index 9d44f0ae655..899c2beeb37 100644 --- a/drivers/power/pmic/mp5416.c +++ b/drivers/power/pmic/mp5416.c @@ -9,9 +9,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ diff --git a/drivers/power/pmic/mtk-pwrap.c b/drivers/power/pmic/mtk-pwrap.c new file mode 100644 index 00000000000..3e3a691d9e8 --- /dev/null +++ b/drivers/power/pmic/mtk-pwrap.c @@ -0,0 +1,896 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MT6357 regulator driver + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct pmic_child_info mt6357_pmic_children_info[] = { + { .prefix = "buck", .driver = MT6357_REGULATOR_DRIVER }, + { .prefix = "ldo", .driver = MT6357_REGULATOR_DRIVER }, + { } +}; + +static const struct pmic_child_info mt6359_pmic_children_info[] = { + { .prefix = "buck", .driver = MT6359_REGULATOR_DRIVER }, + { .prefix = "ldo", .driver = MT6359_REGULATOR_DRIVER }, + { } +}; + +/* macro for wrapper status */ +#define PWRAP_GET_WACS_RDATA GENMASK(15, 0) +#define PWRAP_GET_WACS_FSM GENMASK(18, 16) +#define PWRAP_GET_WACS_ARB_FSM GENMASK(3, 1) +#define PWRAP_STATE_SYNC_IDLE0 BIT(20) +#define PWRAP_STATE_INIT_DONE0 BIT(21) +#define PWRAP_STATE_INIT_DONE1 BIT(15) + +/* macro for WACS FSM */ +#define PWRAP_WACS_FSM_IDLE 0x00 +#define PWRAP_WACS_FSM_WFVLDCLR 0x06 + +/* macro for device wrapper default value */ +#define PWRAP_DEW_READ_TEST_VAL 0x5aa5 + +/* macro for manual command */ +#define PWRAP_MAN_CMD_SPI_WRITE BIT(13) +#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) +#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) +#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8) + +/* macro for Watch Dog Timer Source */ +#define PWRAP_WDT_SRC_MASK_ALL GENMASK(31, 0) + +/* Group of bits used for shown slave capability */ +#define PWRAP_SLV_CAP_SPI BIT(0) +#define PWRAP_SLV_CAP_DUALIO BIT(1) +#define HAS_CAP(_c, _x_val) (((_c) & (_x_val)) == (_x_val)) + +/* Group of bits used for shown pwrap capability */ +#define PWRAP_CAP_INT1_EN BIT(3) +#define PWRAP_CAP_WDT_SRC1 BIT(4) +#define PWRAP_CAP_ARB BIT(5) + +/* defines for slave device wrapper registers */ +enum dew_regs { + PWRAP_DEW_BASE, + PWRAP_DEW_DIO_EN, + PWRAP_DEW_READ_TEST, + PWRAP_DEW_WRITE_TEST, + PWRAP_DEW_CRC_EN, + PWRAP_DEW_CRC_VAL, + PWRAP_DEW_MON_GRP_SEL, + PWRAP_DEW_CIPHER_KEY_SEL, + PWRAP_DEW_CIPHER_IV_SEL, + PWRAP_DEW_CIPHER_RDY, + PWRAP_DEW_CIPHER_MODE, + PWRAP_DEW_CIPHER_SWRST, + + /* MT6323 only regs */ + PWRAP_DEW_CIPHER_EN, + PWRAP_DEW_RDDMY_NO, + + /* MT6358 only regs */ + PWRAP_SMT_CON1, + PWRAP_DRV_CON1, + PWRAP_FILTER_CON0, + PWRAP_GPIO_PULLEN0_CLR, + PWRAP_RG_SPI_CON0, + PWRAP_RG_SPI_RECORD0, + PWRAP_RG_SPI_CON2, + PWRAP_RG_SPI_CON3, + PWRAP_RG_SPI_CON4, + PWRAP_RG_SPI_CON5, + PWRAP_RG_SPI_CON6, + PWRAP_RG_SPI_CON7, + PWRAP_RG_SPI_CON8, + PWRAP_RG_SPI_CON13, + PWRAP_SPISLV_KEY, + + /* MT6359 only regs */ + PWRAP_DEW_CRC_SWRST, + PWRAP_DEW_RG_EN_RECORD, + PWRAP_DEW_RECORD_CMD0, + PWRAP_DEW_RECORD_CMD1, + PWRAP_DEW_RECORD_CMD2, + PWRAP_DEW_RECORD_CMD3, + PWRAP_DEW_RECORD_CMD4, + PWRAP_DEW_RECORD_CMD5, + PWRAP_DEW_RECORD_WDATA0, + PWRAP_DEW_RECORD_WDATA1, + PWRAP_DEW_RECORD_WDATA2, + PWRAP_DEW_RECORD_WDATA3, + PWRAP_DEW_RECORD_WDATA4, + PWRAP_DEW_RECORD_WDATA5, + PWRAP_DEW_RG_ADDR_TARGET, + PWRAP_DEW_RG_ADDR_MASK, + PWRAP_DEW_RG_WDATA_TARGET, + PWRAP_DEW_RG_WDATA_MASK, + PWRAP_DEW_RG_SPI_RECORD_CLR, + PWRAP_DEW_RG_CMD_ALERT_CLR, +}; + +static const u32 mt6357_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x040A, + [PWRAP_DEW_READ_TEST] = 0x040C, + [PWRAP_DEW_WRITE_TEST] = 0x040E, + [PWRAP_DEW_CRC_EN] = 0x0412, + [PWRAP_DEW_CRC_VAL] = 0x0414, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A, + [PWRAP_DEW_CIPHER_RDY] = 0x041E, + [PWRAP_DEW_CIPHER_MODE] = 0x0420, + [PWRAP_DEW_CIPHER_SWRST] = 0x0422, + [PWRAP_DEW_CIPHER_EN] = 0x041C, + [PWRAP_DEW_RDDMY_NO] = 0x0424, +}; + +static const u32 mt6359_regs[] = { + [PWRAP_DEW_RG_EN_RECORD] = 0x040a, + [PWRAP_DEW_DIO_EN] = 0x040c, + [PWRAP_DEW_READ_TEST] = 0x040e, + [PWRAP_DEW_WRITE_TEST] = 0x0410, + [PWRAP_DEW_CRC_SWRST] = 0x0412, + [PWRAP_DEW_CRC_EN] = 0x0414, + [PWRAP_DEW_CRC_VAL] = 0x0416, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a, + [PWRAP_DEW_CIPHER_EN] = 0x041c, + [PWRAP_DEW_CIPHER_RDY] = 0x041e, + [PWRAP_DEW_CIPHER_MODE] = 0x0420, + [PWRAP_DEW_CIPHER_SWRST] = 0x0422, + [PWRAP_DEW_RDDMY_NO] = 0x0424, + [PWRAP_DEW_RECORD_CMD0] = 0x0428, + [PWRAP_DEW_RECORD_CMD1] = 0x042a, + [PWRAP_DEW_RECORD_CMD2] = 0x042c, + [PWRAP_DEW_RECORD_CMD3] = 0x042e, + [PWRAP_DEW_RECORD_CMD4] = 0x0430, + [PWRAP_DEW_RECORD_CMD5] = 0x0432, + [PWRAP_DEW_RECORD_WDATA0] = 0x0434, + [PWRAP_DEW_RECORD_WDATA1] = 0x0436, + [PWRAP_DEW_RECORD_WDATA2] = 0x0438, + [PWRAP_DEW_RECORD_WDATA3] = 0x043a, + [PWRAP_DEW_RECORD_WDATA4] = 0x043c, + [PWRAP_DEW_RECORD_WDATA5] = 0x043e, + [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440, + [PWRAP_DEW_RG_ADDR_MASK] = 0x0442, + [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444, + [PWRAP_DEW_RG_WDATA_MASK] = 0x0446, + [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448, + [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448, + [PWRAP_SPISLV_KEY] = 0x044a, +}; + +enum pwrap_regs { + PWRAP_MUX_SEL, + PWRAP_WRAP_EN, + PWRAP_DIO_EN, + PWRAP_SIDLY, + PWRAP_CSHEXT_WRITE, + PWRAP_CSHEXT_READ, + PWRAP_CSLEXT_START, + PWRAP_CSLEXT_END, + PWRAP_STAUPD_PRD, + PWRAP_STAUPD_GRPEN, + PWRAP_STAUPD_MAN_TRIG, + PWRAP_STAUPD_STA, + PWRAP_WRAP_STA, + PWRAP_HARB_INIT, + PWRAP_HARB_HPRIO, + PWRAP_HIPRIO_ARB_EN, + PWRAP_HARB_STA0, + PWRAP_HARB_STA1, + PWRAP_MAN_EN, + PWRAP_MAN_CMD, + PWRAP_MAN_RDATA, + PWRAP_MAN_VLDCLR, + PWRAP_WACS0_EN, + PWRAP_INIT_DONE0, + PWRAP_WACS0_CMD, + PWRAP_WACS0_RDATA, + PWRAP_WACS0_VLDCLR, + PWRAP_WACS1_EN, + PWRAP_INIT_DONE1, + PWRAP_WACS1_CMD, + PWRAP_WACS1_RDATA, + PWRAP_WACS1_VLDCLR, + PWRAP_WACS2_EN, + PWRAP_INIT_DONE2, + PWRAP_WACS2_CMD, + PWRAP_WACS2_RDATA, + PWRAP_WACS2_VLDCLR, + PWRAP_INT_EN, + PWRAP_INT_FLG_RAW, + PWRAP_INT_FLG, + PWRAP_INT_CLR, + PWRAP_SIG_ADR, + PWRAP_SIG_MODE, + PWRAP_SIG_VALUE, + PWRAP_SIG_ERRVAL, + PWRAP_CRC_EN, + PWRAP_TIMER_EN, + PWRAP_TIMER_STA, + PWRAP_WDT_UNIT, + PWRAP_WDT_SRC_EN, + PWRAP_WDT_FLG, + PWRAP_DEBUG_INT_SEL, + PWRAP_CIPHER_KEY_SEL, + PWRAP_CIPHER_IV_SEL, + PWRAP_CIPHER_RDY, + PWRAP_CIPHER_MODE, + PWRAP_CIPHER_SWRST, + PWRAP_DCM_EN, + PWRAP_DCM_DBC_PRD, + PWRAP_EINT_STA0_ADR, + PWRAP_EINT_STA1_ADR, + PWRAP_SWINF_2_WDATA_31_0, + PWRAP_SWINF_2_RDATA_31_0, + + /* MT8390 only regs */ + PWRAP_STAUPD_CTRL, + + /* MT8365 only regs */ + PWRAP_INT1_EN, + PWRAP_INT1_FLG, + PWRAP_INT1_CLR, + PWRAP_WDT_SRC_EN_1, +}; + +static int mt8188_regs[] = { + [PWRAP_INIT_DONE2] = 0x0, + [PWRAP_STAUPD_CTRL] = 0x4C, + [PWRAP_TIMER_EN] = 0x3E4, + [PWRAP_INT_EN] = 0x420, + [PWRAP_INT_FLG] = 0x428, + [PWRAP_INT_CLR] = 0x42C, + [PWRAP_INT1_EN] = 0x450, + [PWRAP_INT1_FLG] = 0x458, + [PWRAP_INT1_CLR] = 0x45C, + [PWRAP_WACS2_CMD] = 0x880, + [PWRAP_SWINF_2_WDATA_31_0] = 0x884, + [PWRAP_SWINF_2_RDATA_31_0] = 0x894, + [PWRAP_WACS2_VLDCLR] = 0x8A4, + [PWRAP_WACS2_RDATA] = 0x8A8, +}; + +static int mt8189_regs[] = { + [PWRAP_INIT_DONE2] = 0x0, + [PWRAP_TIMER_EN] = 0x3E4, + [PWRAP_INT_EN] = 0x450, + [PWRAP_WACS2_CMD] = 0x880, + [PWRAP_SWINF_2_WDATA_31_0] = 0x884, + [PWRAP_SWINF_2_RDATA_31_0] = 0x894, + [PWRAP_WACS2_VLDCLR] = 0x8A4, + [PWRAP_WACS2_RDATA] = 0x8A8, +}; + +static int mt8365_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_CSHEXT_WRITE] = 0x24, + [PWRAP_CSHEXT_READ] = 0x28, + [PWRAP_STAUPD_PRD] = 0x3c, + [PWRAP_STAUPD_GRPEN] = 0x40, + [PWRAP_STAUPD_MAN_TRIG] = 0x58, + [PWRAP_STAUPD_STA] = 0x5c, + [PWRAP_WRAP_STA] = 0x60, + [PWRAP_HARB_INIT] = 0x64, + [PWRAP_HARB_HPRIO] = 0x68, + [PWRAP_HIPRIO_ARB_EN] = 0x6c, + [PWRAP_HARB_STA0] = 0x70, + [PWRAP_HARB_STA1] = 0x74, + [PWRAP_MAN_EN] = 0x7c, + [PWRAP_MAN_CMD] = 0x80, + [PWRAP_MAN_RDATA] = 0x84, + [PWRAP_MAN_VLDCLR] = 0x88, + [PWRAP_WACS0_EN] = 0x8c, + [PWRAP_INIT_DONE0] = 0x90, + [PWRAP_WACS0_CMD] = 0xc00, + [PWRAP_WACS0_RDATA] = 0xc04, + [PWRAP_WACS0_VLDCLR] = 0xc08, + [PWRAP_WACS1_EN] = 0x94, + [PWRAP_INIT_DONE1] = 0x98, + [PWRAP_WACS2_EN] = 0x9c, + [PWRAP_INIT_DONE2] = 0xa0, + [PWRAP_WACS2_CMD] = 0xc20, + [PWRAP_WACS2_RDATA] = 0xc24, + [PWRAP_WACS2_VLDCLR] = 0xc28, + [PWRAP_INT_EN] = 0xb4, + [PWRAP_INT_FLG_RAW] = 0xb8, + [PWRAP_INT_FLG] = 0xbc, + [PWRAP_INT_CLR] = 0xc0, + [PWRAP_SIG_ADR] = 0xd4, + [PWRAP_SIG_MODE] = 0xd8, + [PWRAP_SIG_VALUE] = 0xdc, + [PWRAP_SIG_ERRVAL] = 0xe0, + [PWRAP_CRC_EN] = 0xe4, + [PWRAP_TIMER_EN] = 0xe8, + [PWRAP_TIMER_STA] = 0xec, + [PWRAP_WDT_UNIT] = 0xf0, + [PWRAP_WDT_SRC_EN] = 0xf4, + [PWRAP_WDT_FLG] = 0xfc, + [PWRAP_DEBUG_INT_SEL] = 0x104, + [PWRAP_CIPHER_KEY_SEL] = 0x1c4, + [PWRAP_CIPHER_IV_SEL] = 0x1c8, + [PWRAP_CIPHER_RDY] = 0x1d0, + [PWRAP_CIPHER_MODE] = 0x1d4, + [PWRAP_CIPHER_SWRST] = 0x1d8, + [PWRAP_DCM_EN] = 0x1dc, + [PWRAP_DCM_DBC_PRD] = 0x1e0, + [PWRAP_EINT_STA0_ADR] = 0x44, + [PWRAP_EINT_STA1_ADR] = 0x48, + [PWRAP_INT1_EN] = 0xc4, + [PWRAP_INT1_FLG] = 0xcc, + [PWRAP_INT1_CLR] = 0xd0, + [PWRAP_WDT_SRC_EN_1] = 0xf8, +}; + +enum pwrap_type { + PWRAP_MT8188, + PWRAP_MT8189, + PWRAP_MT8365, +}; + +struct pwrap_slv_type { + const u32 *dew_regs; + u32 caps; +}; + +struct pmic_wrapper { + struct udevice *dev; + void __iomem *base; + const struct pmic_wrapper_type *master; + const struct pwrap_slv_type *slave; + struct clk *clk_spi; + struct clk *clk_wrap; + struct clk *clk_wrap_sys; + struct clk *clk_wrap_tmr; +}; + +struct pmic_wrapper_type { + int *regs; + enum pwrap_type type; + u32 arb_en_all; + u32 int_en_all; + u32 int1_en_all; + u32 spi_w; + u32 wdt_src; + /* Flags indicating the capability for the target pwrap */ + u32 caps; +}; + +static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) +{ + return readl(wrp->base + wrp->master->regs[reg]); +} + +static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) +{ + writel(val, wrp->base + wrp->master->regs[reg]); +} + +static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp) +{ + u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + return FIELD_GET(PWRAP_GET_WACS_ARB_FSM, val); + + return FIELD_GET(PWRAP_GET_WACS_FSM, val); +} + +static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp) +{ + return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE; +} + +static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp) +{ + return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR; +} + +/* + * Timeout issue sometimes caused by the last read command + * failed because pmic wrap could not got the FSM_VLDCLR + * in time after finishing WACS2_CMD. It made state machine + * still on FSM_VLDCLR and timeout next time. + * Check the status of FSM and clear the vldclr to recovery the + * error. + */ +static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp) +{ + if (pwrap_is_fsm_vldclr(wrp)) + pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); +} + +static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp) +{ + return FIELD_GET(PWRAP_STATE_SYNC_IDLE0, pwrap_readl(wrp, PWRAP_WACS2_RDATA)); +} + +static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp) +{ + u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); + + return FIELD_GET(PWRAP_GET_WACS_FSM, val) == PWRAP_WACS_FSM_IDLE && + FIELD_GET(PWRAP_STATE_SYNC_IDLE0, val); +} + +static int pwrap_wait_for_state(struct pmic_wrapper *wrp, bool (*fp)(struct pmic_wrapper *)) +{ + unsigned long timeout; + + timeout = timer_get_us() + 10000; + + do { + if (time_after(timer_get_us(), timeout)) + return fp(wrp) ? 0 : -ETIMEDOUT; + + if (fp(wrp)) + return 0; + } while (1); +} + +/* pwrap_read16 in linux kernel */ +static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) +{ + int ret; + u32 val; + + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); + if (ret) { + pwrap_leave_fsm_vldclr(wrp); + return ret; + } + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + val = adr; + else + val = (adr >> 1) << 16; + + pwrap_writel(wrp, val, PWRAP_WACS2_CMD); + + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); + if (ret) + return ret; + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0); + else + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA); + + *rdata = FIELD_GET(PWRAP_GET_WACS_RDATA, val); + + pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); + + return 0; +} + +/* pwrap_write16 in linux kernel */ +static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) +{ + int ret; + + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); + if (ret) { + pwrap_leave_fsm_vldclr(wrp); + return ret; + } + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) { + pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0); + pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD); + } else { + pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata, PWRAP_WACS2_CMD); + } + + return 0; +} + +static int pwrap_reset_spislave(struct pmic_wrapper *wrp) +{ + int ret, i; + + pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN); + pwrap_writel(wrp, 0, PWRAP_WRAP_EN); + pwrap_writel(wrp, 1, PWRAP_MUX_SEL); + pwrap_writel(wrp, 1, PWRAP_MAN_EN); + pwrap_writel(wrp, 0, PWRAP_DIO_EN); + + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL, PWRAP_MAN_CMD); + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, PWRAP_MAN_CMD); + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH, PWRAP_MAN_CMD); + + for (i = 0; i < 4; i++) + pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS, + PWRAP_MAN_CMD); + + ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle); + if (ret) { + dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); + return ret; + } + + pwrap_writel(wrp, 0, PWRAP_MAN_EN); + pwrap_writel(wrp, 0, PWRAP_MUX_SEL); + + return 0; +} + +/* + * pwrap_init_sidly - configure serial input delay + * + * This configures the serial input delay. We can configure 0, 2, 4 or 6ns + * delay. Do a read test with all possible values and chose the best delay. + */ +static int pwrap_init_sidly(struct pmic_wrapper *wrp) +{ + u32 rdata; + u32 i; + u32 pass = 0; + signed char dly[16] = { + -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 + }; + + for (i = 0; i < 4; i++) { + pwrap_writel(wrp, i, PWRAP_SIDLY); + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); + if (rdata == PWRAP_DEW_READ_TEST_VAL) { + dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); + pass |= 1 << i; + } + } + + if (dly[pass] < 0) { + dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n", pass); + return -EIO; + } + + pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); + + return 0; +} + +static int pwrap_init_dual_io(struct pmic_wrapper *wrp) +{ + int ret; + u32 rdata; + + /* Enable dual IO mode */ + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); + + /* Check IDLE & INIT_DONE in advance */ + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle); + if (ret) { + dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); + return ret; + } + + pwrap_writel(wrp, 1, PWRAP_DIO_EN); + + /* Read Test */ + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); + if (rdata != PWRAP_DEW_READ_TEST_VAL) { + dev_err(wrp->dev, "Read failed on DIO mode: 0x%04x!=0x%04x\n", + PWRAP_DEW_READ_TEST_VAL, rdata); + return -EFAULT; + } + + return 0; +} + +static int pwrap_init(struct pmic_wrapper *wrp) +{ + int ret; + + /* Reset SPI slave */ + if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { + ret = pwrap_reset_spislave(wrp); + if (ret) + return ret; + } + + pwrap_writel(wrp, 1, PWRAP_WRAP_EN); + + pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); + + pwrap_writel(wrp, 1, PWRAP_WACS2_EN); + + /* Setup serial input delay */ + if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { + ret = pwrap_init_sidly(wrp); + if (ret) + return ret; + } + + /* Enable dual I/O mode */ + if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { + ret = pwrap_init_dual_io(wrp); + if (ret) + return ret; + } + + pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); + pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN); + pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN); + pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD); + pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN); + + /* Setup the init done registers */ + pwrap_writel(wrp, 1, PWRAP_INIT_DONE2); + pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); + pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); + + return 0; +} + +static const struct pwrap_slv_type pmic_mt6357 = { + .dew_regs = mt6357_regs, + .caps = 0, +}; + +static const struct pwrap_slv_type pmic_mt6359 = { + .dew_regs = mt6359_regs, + .caps = PWRAP_SLV_CAP_DUALIO, +}; + +static const struct udevice_id mtk_pmic_ids[] = { + { .compatible = "mediatek,mt6357", .data = (ulong)&pmic_mt6357 }, + { .compatible = "mediatek,mt6359", .data = (ulong)&pmic_mt6359 }, + { } +}; + +static int mtk_pwrap_find_slave(const struct pwrap_slv_type **slave, ofnode pmic_node) +{ + const struct udevice_id *of_match = mtk_pmic_ids; + const char *pmic_name; + + pmic_name = ofnode_get_property(pmic_node, "compatible", NULL); + if (!pmic_name) { + log_err("%s: missing compatible property\n", __func__); + return -EINVAL; + } + + while (of_match->compatible) { + if (!strcmp(of_match->compatible, pmic_name)) { + *slave = (struct pwrap_slv_type *)of_match->data; + return 0; + } + of_match++; + } + + return -ENOENT; +} + +static int mtk_pwrap_probe(struct udevice *dev) +{ + struct pmic_wrapper *wrp = dev_get_priv(dev); + ofnode pmic_node; + u32 mask_done; + int ret; + + wrp->dev = dev; + + wrp->base = dev_remap_addr(dev); + if (IS_ERR(wrp->base)) + return PTR_ERR(wrp->base); + + wrp->master = (void *)dev_get_driver_data(dev); + + pmic_node = dev_read_first_subnode(dev); + if (!ofnode_valid(pmic_node)) { + dev_err(dev, "pmic subnode not found\n"); + return -ENXIO; + } + + ret = mtk_pwrap_find_slave(&wrp->slave, pmic_node); + if (ret) { + dev_err(dev, "pmic slave not found\n"); + return -EINVAL; + } + + wrp->clk_spi = devm_clk_get(dev, "spi"); + if (IS_ERR(wrp->clk_spi)) + return PTR_ERR(wrp->clk_spi); + + wrp->clk_wrap = devm_clk_get(dev, "wrap"); + if (IS_ERR(wrp->clk_wrap)) + return PTR_ERR(wrp->clk_wrap); + + wrp->clk_wrap_sys = devm_clk_get_optional(dev, "wrap_sys"); + wrp->clk_wrap_tmr = devm_clk_get_optional(dev, "wrap_tmr"); + + ret = clk_enable(wrp->clk_spi); + if (ret) + return ret; + + ret = clk_enable(wrp->clk_wrap); + if (ret) + return ret; + + ret = clk_enable(wrp->clk_wrap_sys); + if (ret) + return ret; + + ret = clk_enable(wrp->clk_wrap_tmr); + if (ret) + return ret; + + /* + * The PMIC could already be initialized by the bootloader. + * Skip initialization here in this case. + */ + if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) { + ret = pwrap_init(wrp); + if (ret) { + dev_err(dev, "init failed with %d\n", ret); + return ret; + } + } + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + mask_done = PWRAP_STATE_INIT_DONE1; + else + mask_done = PWRAP_STATE_INIT_DONE0; + + if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { + dev_dbg(dev, "initialization isn't finished\n"); + return -ENODEV; + } + + /* + * Since STAUPD was not used on mt8173 platform, + * so STAUPD of WDT_SRC which should be turned off + */ + pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN); + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1)) + pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1); + + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) + pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN); + else + pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); + + pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); + + /* + * We add INT1 interrupt to handle starvation and request exception + * If we support it, we should enable it here. + */ + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) + pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN); + + return 0; +} + +static int mtk_pwrap_bind(struct udevice *dev) +{ + ofnode pmic_node, regulators_node; + int children; + const struct pmic_child_info *pmic_children_info; + struct pmic_wrapper_type *pw_type = (void *)dev_get_driver_data(dev); + + pmic_node = dev_read_first_subnode(dev); + if (!ofnode_valid(pmic_node)) { + dev_err(dev, "pmic subnode not found\n"); + return -ENXIO; + } + + switch (pw_type->type) { + case PWRAP_MT8365: + pmic_children_info = mt6357_pmic_children_info; + break; + case PWRAP_MT8188: + case PWRAP_MT8189: + pmic_children_info = mt6359_pmic_children_info; + break; + default: + dev_err(dev, "pwrap type %d not supported\n", pw_type->type); + return -ENXIO; + } + + regulators_node = ofnode_find_subnode(pmic_node, "regulators"); + if (ofnode_valid(regulators_node)) { + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + dev_dbg(dev, "no children found\n"); + } else { + dev_dbg(dev, "regulators subnode not found\n"); + } + + return 0; +} + +static int mtk_pwrap_reg_count(struct udevice *dev) +{ + return 0x8000; +} + +static int mtk_pwrap_read(struct udevice *dev, uint reg, uint8_t *buf, int len) +{ + struct pmic_wrapper *wrp = dev_get_priv(dev); + + if ((len * sizeof(uint8_t)) > sizeof(u32)) + return -EINVAL; + + return pwrap_read(wrp, reg, (u32 *)buf); +} + +static int mtk_pwrap_write(struct udevice *dev, uint reg, const uint8_t *buf, int len) +{ + struct pmic_wrapper *wrp = dev_get_priv(dev); + + if ((len * sizeof(uint8_t)) > sizeof(u32)) + return -EINVAL; + + return pwrap_write(wrp, reg, *(u32 *)buf); +} + +static struct dm_pmic_ops mtk_pwrap_ops = { + .reg_count = mtk_pwrap_reg_count, + .read = mtk_pwrap_read, + .write = mtk_pwrap_write, +}; + +static struct pmic_wrapper_type pwrap_mt8188 = { + .regs = mt8188_regs, + .type = PWRAP_MT8188, + .arb_en_all = 0x777f, + .int_en_all = 0x180000, + .int1_en_all = 0x0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, +}; + +static struct pmic_wrapper_type pwrap_mt8189 = { + .regs = mt8189_regs, + .type = PWRAP_MT8189, + .arb_en_all = 0x777f, + .int_en_all = 0x180000, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_ARB, +}; + +static const struct pmic_wrapper_type pwrap_mt8365 = { + .regs = mt8365_regs, + .type = PWRAP_MT8365, + .arb_en_all = 0x3ffff, + .int_en_all = 0x7f1fffff, + .int1_en_all = 0x0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, +}; + +static const struct udevice_id mtk_pwrap_ids[] = { + { .compatible = "mediatek,mt8188-pwrap", .data = (ulong)&pwrap_mt8188 }, + { .compatible = "mediatek,mt8189-pwrap", .data = (ulong)&pwrap_mt8189 }, + { .compatible = "mediatek,mt8365-pwrap", .data = (ulong)&pwrap_mt8365 }, + { } +}; + +U_BOOT_DRIVER(mtk_pwrap) = { + .name = "mtk_pwrap", + .id = UCLASS_PMIC, + .of_match = mtk_pwrap_ids, + .bind = mtk_pwrap_bind, + .probe = mtk_pwrap_probe, + .ops = &mtk_pwrap_ops, + .priv_auto = sizeof(struct pmic_wrapper), +}; diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index 37d4190fabe..e5b497dfc39 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -48,7 +48,9 @@ static int palmas_bind(struct udevice *dev) ofnode subnode, gpio_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { + if (IS_ENABLED(CONFIG_SYSRESET_PALMAS) && + (dev_read_bool(dev, "ti,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER, "sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index e5c1f037b61..c95e6357ee8 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, diff --git a/drivers/power/pmic/pmic_tps65910_dm.c b/drivers/power/pmic/pmic_tps65910_dm.c index de8d805566a..bce35603275 100644 --- a/drivers/power/pmic/pmic_tps65910_dm.c +++ b/drivers/power/pmic/pmic_tps65910_dm.c @@ -61,7 +61,9 @@ static int pmic_tps65910_bind(struct udevice *dev) ofnode regulators_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_TPS65910)) { + if (IS_ENABLED(CONFIG_SYSRESET_TPS65910) && + (dev_read_bool(dev, "ti,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver(dev, TPS65910_RST_DRIVER, "sysreset", NULL); if (ret) { diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index d11f7a7886e..95b71d2fe49 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -220,7 +220,9 @@ static int rk8xx_bind(struct udevice *dev) debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); - if (CONFIG_IS_ENABLED(SYSRESET)) { + if (CONFIG_IS_ENABLED(SYSRESET) && + (dev_read_bool(dev, "rockchip,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver_to_node(dev, "rk8xx_sysreset", "rk8xx_sysreset", dev_ofnode(dev), NULL); diff --git a/drivers/power/pmic/tps80031.c b/drivers/power/pmic/tps80031.c index a2f935b0c6d..6004a14cd6c 100644 --- a/drivers/power/pmic/tps80031.c +++ b/drivers/power/pmic/tps80031.c @@ -46,7 +46,9 @@ static int tps80031_bind(struct udevice *dev) ofnode regulators_node; int children, ret; - if (IS_ENABLED(CONFIG_SYSRESET_TPS80031)) { + if (IS_ENABLED(CONFIG_SYSRESET_TPS80031) && + (dev_read_bool(dev, "ti,system-power-controller") || + dev_read_bool(dev, "system-power-controller"))) { ret = device_bind_driver(dev, TPS80031_RST_DRIVER, "sysreset", NULL); if (ret) { diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index d8b3e0f62e6..a4ee5f1335a 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -191,6 +191,14 @@ config DM_REGULATOR_FAN53555 or switching the mode is not supported by this driver (at this time). +config SPL_DM_REGULATOR_FAN53555 + bool "Enable Driver Model for REGULATOR FAN53555 in SPL" + depends on SPL_DM_PMIC_FAN53555 + help + This configuration setting enables the implementation of the + driver-model regulator uclass features for the FAN53555 + regulator in SPL. + config DM_REGULATOR_COMMON bool depends on DM_REGULATOR @@ -521,3 +529,21 @@ config DM_REGULATOR_CPCAP REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP PMIC and implements get/set api for voltage and state. + +config DM_REGULATOR_MT6357 + bool "Enable driver for MediaTek MT6357 PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP + help + Say y here to select this option to enable the power regulator of + MediaTek MT6357 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + +config DM_REGULATOR_MT6359 + bool "Enable driver for MediaTek MT6359 PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP + help + Say y here to select this option to enable the power regulator of + MediaTek MT6359 PMIC. + This driver supports the control of different power rails of device + through regulator interface. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index ee8f56ea3b9..9e303d4f7f8 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -47,3 +47,5 @@ obj-$(CONFIG_$(PHASE_)DM_REGULATOR_ANATOP) += anatop_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o +obj-$(CONFIG_DM_REGULATOR_MT6357) += mt6357_regulator.o +obj-$(CONFIG_DM_REGULATOR_MT6359) += mt6359_regulator.o diff --git a/drivers/power/regulator/cpcap_regulator.c b/drivers/power/regulator/cpcap_regulator.c index 04cd6651374..0fbce57048c 100644 --- a/drivers/power/regulator/cpcap_regulator.c +++ b/drivers/power/regulator/cpcap_regulator.c @@ -55,7 +55,7 @@ #define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask, \ _volt_mask, _volt_shft, _mode_val, _off_mode_val, _val_tbl, \ - _mode_cntr, _volt_trans_time, _turn_on_time, _bit_offset) { \ + _mode_cntr, _volt_trans_time, _turn_on_time) { \ .reg = CPCAP_REG_##_reg, \ .assignment_reg = CPCAP_REG_##_assignment_reg, \ .assignment_mask = CPCAP_BIT_##_assignment_mask, \ @@ -69,60 +69,59 @@ .mode_cntr = _mode_cntr, \ .volt_trans_time = _volt_trans_time, \ .turn_on_time = _turn_on_time, \ - .bit_offset_from_cpcap_lowest_voltage = _bit_offset, \ } static const struct cpcap_regulator_data tegra20_regulators[CPCAP_REGULATORS_COUNT] = { /* BUCK */ [CPCAP_SW1] = CPCAP_REG(S1C1, ASSIGN2, SW1_SEL, 0x6f00, 0x007f, - 0, 0x6800, 0, sw1_val_tbl, 0, 0, 1500, 0x0c), + 0, 0x6800, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW2] = CPCAP_REG(S2C1, ASSIGN2, SW2_SEL, 0x6f00, 0x007f, - 0, 0x4804, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + 0, 0x4804, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW3] = CPCAP_REG(S3C, ASSIGN2, SW3_SEL, 0x0578, 0x0003, - 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0, 0), + 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0), [CPCAP_SW4] = CPCAP_REG(S4C1, ASSIGN2, SW4_SEL, 0x6f00, 0x007f, - 0, 0x4909, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + 0, 0x4909, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW5] = CPCAP_REG(S5C, ASSIGN2, SW5_SEL, 0x0028, 0x0000, - 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500, 0), + 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500), [CPCAP_SW6] = CPCAP_REG(S6C, ASSIGN2, SW6_SEL, 0x0000, 0x0000, - 0, 0, 0, unknown_val_tbl, 0, 0, 0, 0), + 0, 0, 0, unknown_val_tbl, 0, 0, 0), /* LDO */ [CPCAP_VCAM] = CPCAP_REG(VCAMC, ASSIGN2, VCAM_SEL, 0x0087, 0x0030, - 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000, 0), + 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000), [CPCAP_VCSI] = CPCAP_REG(VCSIC, ASSIGN3, VCSI_SEL, 0x0047, 0x0010, - 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000, 0), + 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000), [CPCAP_VDAC] = CPCAP_REG(VDACC, ASSIGN3, VDAC_SEL, 0x0087, 0x0030, - 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000), [CPCAP_VDIG] = CPCAP_REG(VDIGC, ASSIGN2, VDIG_SEL, 0x0087, 0x0030, - 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000), [CPCAP_VFUSE] = CPCAP_REG(VFUSEC, ASSIGN3, VFUSE_SEL, 0x00a0, 0x000f, - 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000, 0), + 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000), [CPCAP_VHVIO] = CPCAP_REG(VHVIOC, ASSIGN3, VHVIO_SEL, 0x0017, 0x0000, - 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000, 0), + 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000), [CPCAP_VSDIO] = CPCAP_REG(VSDIOC, ASSIGN2, VSDIO_SEL, 0x0087, 0x0038, - 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000, 0), + 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000), [CPCAP_VPLL] = CPCAP_REG(VPLLC, ASSIGN3, VPLL_SEL, 0x0047, 0x0018, - 3, 0x1, 0, vpll_val_tbl, 0, 420, 100, 0), + 3, 0x1, 0, vpll_val_tbl, 0, 420, 100), [CPCAP_VRF1] = CPCAP_REG(VRF1C, ASSIGN3, VRF1_SEL, 0x00ac, 0x0002, - 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000, 0), + 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000), [CPCAP_VRF2] = CPCAP_REG(VRF2C, ASSIGN3, VRF2_SEL, 0x0023, 0x0008, - 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000, 0), + 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000), [CPCAP_VRFREF] = CPCAP_REG(VRFREFC, ASSIGN3, VRFREF_SEL, 0x0023, 0x0008, - 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100, 0), + 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100), [CPCAP_VWLAN1] = CPCAP_REG(VWLAN1C, ASSIGN3, VWLAN1_SEL, 0x0047, 0x0010, - 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000), [CPCAP_VWLAN2] = CPCAP_REG(VWLAN2C, ASSIGN3, VWLAN2_SEL, 0x020c, 0x00c0, - 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000, 0), + 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000), [CPCAP_VSIM] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x0023, 0x0008, - 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000, 0), + 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000), [CPCAP_VSIMCARD] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x1e80, 0x0008, - 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000, 0), + 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000), [CPCAP_VVIB] = CPCAP_REG(VVIBC, ASSIGN3, VVIB_SEL, 0x0001, 0x000c, - 2, 0x1, 0, vvib_val_tbl, 0, 500, 500, 0), + 2, 0x1, 0, vvib_val_tbl, 0, 500, 500), [CPCAP_VUSB] = CPCAP_REG(VUSBC, ASSIGN3, VUSB_SEL, 0x011c, 0x0040, - 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000, 0), + 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000), [CPCAP_VAUDIO] = CPCAP_REG(VAUDIOC, ASSIGN4, VAUDIO_SEL, 0x0016, 0x0001, - 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000, 0), + 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000), }; static int cpcap_regulator_get_value(struct udevice *dev) @@ -139,7 +138,6 @@ static int cpcap_regulator_get_value(struct udevice *dev) return 0; value &= regulator->volt_mask; - value -= regulator->bit_offset_from_cpcap_lowest_voltage; return regulator->val_tbl[value >> volt_shift]; } @@ -164,7 +162,6 @@ static int cpcap_regulator_set_value(struct udevice *dev, int uV) value = regulator->val_tbl_sz; value <<= volt_shift; - value += regulator->bit_offset_from_cpcap_lowest_voltage; } ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->volt_mask, @@ -232,7 +229,7 @@ static int cpcap_regulator_probe(struct udevice *dev) for (id = 0; id < CPCAP_REGULATORS_COUNT; id++) if (cpcap_regulator_to_name[id]) - if (!strcmp(dev->name, cpcap_regulator_to_name[id])) + if (!strcasecmp(dev->name, cpcap_regulator_to_name[id])) break; switch (id) { diff --git a/drivers/power/regulator/mt6357_regulator.c b/drivers/power/regulator/mt6357_regulator.c new file mode 100644 index 00000000000..533cc22b93a --- /dev/null +++ b/drivers/power/regulator/mt6357_regulator.c @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MT6357 regulator driver + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson + */ + +#include +#include +#include +#include + +enum mt6357_regulator_type { + MT6357_REG_TYPE_RANGE, + MT6357_REG_TYPE_TABLE, + MT6357_REG_TYPE_FIXED, +}; + +struct mt6357_linear_range { + unsigned int min; + unsigned int min_sel; + unsigned int max_sel; + unsigned int step; +}; + +struct mt6357_regulator_desc { + const char *name; + const char *of_match; + enum mt6357_regulator_type type; + int id; + unsigned int n_voltages; + const unsigned int *volt_table; + const struct mt6357_linear_range *linear_ranges; + int n_linear_ranges; + unsigned int min_uV; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; +}; + +struct mt6357_regulator_info { + struct mt6357_regulator_desc desc; + const u32 *index_table; + unsigned int n_table; + u32 vsel_shift; + u32 da_vsel_reg; + u32 da_vsel_mask; + u32 da_vsel_shift; +}; + +/* Initialize struct mt6357_linear_range for regulators */ +#define REGULATOR_LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV) \ +{ \ + .min = _min_uV, \ + .min_sel = _min_sel, \ + .max_sel = _max_sel, \ + .step = _step_uV, \ +} + +#define MT6357_BUCK(match, vreg, min, max, step, \ + volt_ranges, vosel_reg, vosel_mask, _da_vsel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_RANGE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel_reg, \ + .vsel_mask = vosel_mask, \ + .enable_reg = MT6357_BUCK_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_BUCK_##vreg##_DBG0, \ + .da_vsel_mask = _da_vsel_mask, \ + .da_vsel_shift = 0, \ + } + +#define MT6357_LDO(match, vreg, ldo_volt_table, \ + ldo_index_table, enreg, vosel, \ + vosel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_TABLE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask << 8, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .index_table = ldo_index_table, \ + .n_table = ARRAY_SIZE(ldo_index_table), \ + } + +#define MT6357_LDO1(match, vreg, min, max, step, volt_ranges, \ + enreg, vosel, vosel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_RANGE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_LDO_##vreg##_DBG0, \ + .da_vsel_mask = 0x7f, \ + .da_vsel_shift = 8, \ + } + +#define MT6357_REG_FIXED(match, vreg, volt) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_FIXED, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = 1, \ + .enable_reg = MT6357_LDO_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + .min_uV = volt, \ + }, \ + } + +static int mt6357_range_find_value(const struct mt6357_linear_range *r, + unsigned int sel, + unsigned int *val) +{ + if (!val || sel < r->min_sel || sel > r->max_sel) + return -EINVAL; + + *val = r->min + r->step * (sel - r->min_sel); + + return 0; +} + +static int mt6357_range_find_selector(const struct mt6357_linear_range *r, + int val, unsigned int *sel) +{ + int num_vals = r->max_sel - r->min_sel + 1; + int ret = -EINVAL; + + if (val >= r->min && val <= r->min + r->step * (num_vals - 1)) { + if (r->step) { + *sel = r->min_sel + ((val - r->min) / r->step); + ret = 0; + } else { + *sel = r->min_sel; + ret = 0; + } + } + return ret; +} + +static int mt6357_get_enable(struct udevice *dev) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.enable_reg); + if (ret < 0) + return ret; + + return ret & info->desc.enable_mask ? true : false; +} + +static int mt6357_set_enable(struct udevice *dev, bool enable) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + + return pmic_clrsetbits(dev->parent, info->desc.enable_reg, + info->desc.enable_mask, + enable ? info->desc.enable_mask : 0); +} + +static int mt6357_get_value(struct udevice *dev) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + unsigned int val_uV; + int selector, idx, ret; + const u32 *pvol; + + switch (info->desc.type) { + case MT6357_REG_TYPE_RANGE: + selector = pmic_reg_read(dev->parent, info->da_vsel_reg); + if (selector < 0) + return selector; + + selector = (selector & info->da_vsel_mask) >> info->da_vsel_shift; + ret = mt6357_range_find_value(info->desc.linear_ranges, selector, &val_uV); + if (ret < 0) + return ret; + + return val_uV; + case MT6357_REG_TYPE_TABLE: + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + if (selector < 0) + return selector; + + selector = (selector & info->desc.vsel_mask) >> 8; + pvol = info->index_table; + + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (pvol[idx] == selector) + return info->desc.volt_table[idx]; + } + + return -EINVAL; + case MT6357_REG_TYPE_FIXED: + return info->desc.min_uV; + default: + return -EINVAL; + } +} + +static int mt6357_set_value(struct udevice *dev, int uvolt) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + int selector, idx, ret; + const u32 *pvol; + + switch (info->desc.type) { + case MT6357_REG_TYPE_RANGE: + ret = mt6357_range_find_selector(info->desc.linear_ranges, uvolt, + &selector); + if (ret < 0) + return ret; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, selector); + case MT6357_REG_TYPE_TABLE: + pvol = info->desc.volt_table; + + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (pvol[idx] == uvolt) { + selector = info->index_table[idx]; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, selector << 8); + } + } + + return -EINVAL; + default: + return -EINVAL; + } +} + +static const int vxo22_voltages[] = { + 2200000, + 2400000, +}; + +static const int vefuse_voltages[] = { + 1200000, + 1300000, + 1500000, + 1800000, + 2800000, + 2900000, + 3000000, + 3300000, +}; + +static const int vcn33_voltages[] = { + 3300000, + 3400000, + 3500000, +}; + +static const int vcama_voltages[] = { + 2500000, + 2800000, +}; + +static const int vcamd_voltages[] = { + 1000000, + 1100000, + 1200000, + 1300000, + 1500000, + 1800000, +}; + +static const int vldo28_voltages[] = { + 2800000, + 3000000, +}; + +static const int vdram_voltages[] = { + 1100000, + 1200000, +}; + +static const int vsim_voltages[] = { + 1700000, + 1800000, + 2700000, + 3000000, + 3100000, +}; + +static const int vibr_voltages[] = { + 1200000, + 1300000, + 1500000, + 1800000, + 2000000, + 2800000, + 3000000, + 3300000, +}; + +static const int vmc_voltages[] = { + 1800000, + 2900000, + 3000000, + 3300000, +}; + +static const int vmch_voltages[] = { + 2900000, + 3000000, + 3300000, +}; + +static const int vemc_voltages[] = { + 2900000, + 3000000, + 3300000, +}; + +static const int vusb_voltages[] = { + 3000000, + 3100000, +}; + +static const int vmc_idx[] = { + 4, 10, 11, 13, +}; + +static const int vmch_idx[] = { + 2, 3, 5, +}; + +static const int vemc_idx[] = { + 2, 3, 5, +}; + +static const int vusb_idx[] = { + 3, 4, +}; + +static const int vxo22_idx[] = { + 0, 2, +}; + +static const int vefuse_idx[] = { + 0, 1, 2, 4, 9, 10, 11, 13, +}; + +static const int vcn33_idx[] = { + 1, 2, 3, +}; + +static const int vcama_idx[] = { + 7, 10, +}; + +static const int vcamd_idx[] = { + 4, 5, 6, 7, 9, 12, +}; + +static const int vldo28_idx[] = { + 1, 3, +}; + +static const int vdram_idx[] = { + 1, 2, +}; + +static const int vsim_idx[] = { + 3, 4, 8, 11, 12, +}; + +static const int vibr_idx[] = { + 0, 1, 2, 4, 5, 9, 11, 13, +}; + +static const struct mt6357_linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(518750, 0, 0x7f, 6250), +}; + +static const struct mt6357_linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), +}; + +static const struct mt6357_linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct mt6357_linear_range buck_volt_range4[] = { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 12500), +}; + +/* The array is indexed by id(MT6357_ID_XXX) */ +static struct mt6357_regulator_info mt6357_regulators[] = { + /* Bucks */ + MT6357_BUCK("buck-vcore", VCORE, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VCORE_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vproc", VPROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VPROC_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vmodem", VMODEM, 500000, 1293750, 6250, + buck_volt_range2, MT6357_BUCK_VMODEM_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vpa", VPA, 500000, 3650000, 50000, + buck_volt_range3, MT6357_BUCK_VPA_CON1, 0x3f, 0x3f), + MT6357_BUCK("buck-vs1", VS1, 1200000, 2787500, 12500, + buck_volt_range4, MT6357_BUCK_VS1_ELR0, 0x7f, 0x7f), + + /* LDOs */ + MT6357_LDO("ldo-vcama", VCAMA, vcama_voltages, vcama_idx, + MT6357_LDO_VCAMA_CON0, MT6357_VCAMA_ANA_CON0, 0xf), + MT6357_LDO("ldo-vcamd", VCAMD, vcamd_voltages, vcamd_idx, + MT6357_LDO_VCAMD_CON0, MT6357_VCAMD_ANA_CON0, 0xf), + MT6357_LDO("ldo-vcn33-bt", VCN33_BT, vcn33_voltages, vcn33_idx, + MT6357_LDO_VCN33_CON0_0, MT6357_VCN33_ANA_CON0, 0x3), + MT6357_LDO("ldo-vcn33-wifi", VCN33_WIFI, vcn33_voltages, vcn33_idx, + MT6357_LDO_VCN33_CON0_1, MT6357_VCN33_ANA_CON0, 0x3), + MT6357_LDO("ldo-vdram", VDRAM, vdram_voltages, vdram_idx, + MT6357_LDO_VDRAM_CON0, MT6357_VDRAM_ELR_2, 0x3), + MT6357_LDO("ldo-vefuse", VEFUSE, vefuse_voltages, vefuse_idx, + MT6357_LDO_VEFUSE_CON0, MT6357_VEFUSE_ANA_CON0, 0xf), + MT6357_LDO("ldo-vemc", VEMC, vemc_voltages, vemc_idx, + MT6357_LDO_VEMC_CON0, MT6357_VEMC_ANA_CON0, 0x7), + MT6357_LDO("ldo-vibr", VIBR, vibr_voltages, vibr_idx, + MT6357_LDO_VIBR_CON0, MT6357_VIBR_ANA_CON0, 0xf), + MT6357_LDO("ldo-vldo28", VLDO28, vldo28_voltages, vldo28_idx, + MT6357_LDO_VLDO28_CON0_0, MT6357_VLDO28_ANA_CON0, 0x3), + MT6357_LDO("ldo-vmc", VMC, vmc_voltages, vmc_idx, + MT6357_LDO_VMC_CON0, MT6357_VMC_ANA_CON0, 0xf), + MT6357_LDO("ldo-vmch", VMCH, vmch_voltages, vmch_idx, + MT6357_LDO_VMCH_CON0, MT6357_VMCH_ANA_CON0, 0x7), + MT6357_LDO("ldo-vsim1", VSIM1, vsim_voltages, vsim_idx, + MT6357_LDO_VSIM1_CON0, MT6357_VSIM1_ANA_CON0, 0xf), + MT6357_LDO("ldo-vsim2", VSIM2, vsim_voltages, vsim_idx, + MT6357_LDO_VSIM2_CON0, MT6357_VSIM2_ANA_CON0, 0xf), + MT6357_LDO("ldo-vusb33", VUSB33, vusb_voltages, vusb_idx, + MT6357_LDO_VUSB33_CON0_0, MT6357_VUSB33_ANA_CON0, 0x7), + MT6357_LDO("ldo-vxo22", VXO22, vxo22_voltages, vxo22_idx, + MT6357_LDO_VXO22_CON0, MT6357_VXO22_ANA_CON0, 0x3), + + MT6357_LDO1("ldo-vsram-proc", VSRAM_PROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_PROC_CON0, + MT6357_LDO_VSRAM_CON0, 0x7f), + MT6357_LDO1("ldo-vsram-others", VSRAM_OTHERS, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_OTHERS_CON0, + MT6357_LDO_VSRAM_CON1, 0x7f), + + MT6357_REG_FIXED("ldo-vaud28", VAUD28, 2800000), + MT6357_REG_FIXED("ldo-vaux18", VAUX18, 1800000), + MT6357_REG_FIXED("ldo-vcamio18", VCAMIO, 1800000), + MT6357_REG_FIXED("ldo-vcn18", VCN18, 1800000), + MT6357_REG_FIXED("ldo-vcn28", VCN28, 2800000), + MT6357_REG_FIXED("ldo-vfe28", VFE28, 2800000), + MT6357_REG_FIXED("ldo-vio18", VIO18, 1800000), + MT6357_REG_FIXED("ldo-vio28", VIO28, 2800000), + MT6357_REG_FIXED("ldo-vrf12", VRF12, 1200000), + MT6357_REG_FIXED("ldo-vrf18", VRF18, 1800000), +}; + +static int mt6357_regulator_probe(struct udevice *dev) +{ + struct mt6357_regulator_info *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(mt6357_regulators); i++) { + if (!strcmp(dev->name, mt6357_regulators[i].desc.of_match)) { + *priv = mt6357_regulators[i]; + return 0; + } + } + + return -ENOENT; +} + +static const struct dm_regulator_ops mt6357_regulator_ops = { + .get_value = mt6357_get_value, + .set_value = mt6357_set_value, + .get_enable = mt6357_get_enable, + .set_enable = mt6357_set_enable, +}; + +U_BOOT_DRIVER(mt6357_regulator) = { + .name = MT6357_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &mt6357_regulator_ops, + .probe = mt6357_regulator_probe, + .priv_auto = sizeof(struct mt6357_regulator_info), +}; diff --git a/drivers/power/regulator/mt6359_regulator.c b/drivers/power/regulator/mt6359_regulator.c new file mode 100644 index 00000000000..cdafcfcb25e --- /dev/null +++ b/drivers/power/regulator/mt6359_regulator.c @@ -0,0 +1,711 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +enum mt6359_regulator_type { + MT6359_REG_TYPE_LINEAR, + MT6359_REG_TYPE_TABLE, + MT6359_REG_TYPE_FIXED, + MT6359_REG_TYPE_VEMC, +}; + +struct regulator_desc { + const char *name; + const char *of_match; + enum mt6359_regulator_type type; + int id; + unsigned int uV_step; + unsigned int n_voltages; + const unsigned int *volt_table; + unsigned int min_uV; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; + unsigned int fixed_uV; +}; + +/* + * MT6359 regulators' information + * + * @desc: standard fields of regulator description. + * @status_reg: for query status of regulators. + * @qi: Mask for query enable signal status of regulators. + * @modeset_reg: for operating AUTO/PWM mode register. + * @modeset_mask: MASK for operating modeset register. + */ +struct mt6359_regulator_info { + struct regulator_desc desc; + u32 status_reg; + u32 qi; + u32 modeset_reg; + u32 modeset_mask; + u32 lp_mode_reg; + u32 lp_mode_mask; +}; + +#define MT6359_BUCK(match, _name, _min, _max, _step, \ + _enable_reg, _status_reg, \ + _vsel_reg, _vsel_mask, \ + _lp_mode_reg, _lp_mode_shift, \ + _modeset_reg, _modeset_shift) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_LINEAR, \ + .id = MT6359_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ + .lp_mode_reg = _lp_mode_reg, \ + .lp_mode_mask = BIT(_lp_mode_shift), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = BIT(_modeset_shift), \ +} + +#define MT6359_LDO_LINEAR(match, _name, _min, _max, _step, \ + _enable_reg, _status_reg, _vsel_reg, _vsel_mask) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_LINEAR, \ + .id = MT6359_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359_LDO(match, _name, _tmp_volt_table, \ + _enable_reg, _enable_mask, _status_reg, \ + _vsel_reg, _vsel_mask, _en_delay) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_TABLE, \ + .id = MT6359_ID_##_name, \ + .n_voltages = ARRAY_SIZE(_tmp_volt_table), \ + .volt_table = _tmp_volt_table, \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(_enable_mask), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359_REG_FIXED(match, _name, _enable_reg, \ + _status_reg, _fixed_volt) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_FIXED, \ + .id = MT6359_ID_##_name, \ + .n_voltages = 1, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + .fixed_uV = (_fixed_volt), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359P_LDO1(match, _name, _type, _tmp_volt_table, \ + _enable_reg, _enable_mask, _status_reg, \ + _vsel_reg, _vsel_mask) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = _type, \ + .id = MT6359_ID_##_name, \ + .n_voltages = ARRAY_SIZE(_tmp_volt_table), \ + .volt_table = _tmp_volt_table, \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(_enable_mask), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +static const unsigned int vsim1_voltages[] = { + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, +}; + +static const unsigned int vibr_voltages[] = { + 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000, + 0, 3000000, 0, 3300000, +}; + +static const unsigned int vrf12_voltages[] = { + 0, 0, 1100000, 1200000, 1300000, +}; + +static const unsigned int volt18_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, +}; + +static const unsigned int vcn13_voltages[] = { + 900000, 1000000, 0, 1200000, 1300000, +}; + +static const unsigned int vcn33_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000, +}; + +static const unsigned int vefuse_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000, +}; + +static const unsigned int vxo22_voltages[] = { + 1800000, 0, 0, 0, 2200000, +}; + +static const unsigned int vrfck_voltages_1[] = { + 1240000, 1600000, +}; + +static const unsigned int vio28_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000, +}; + +static const unsigned int vemc_voltages_1[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000, + 3300000, +}; + +static const unsigned int va12_voltages[] = { + 0, 0, 0, 0, 0, 0, 1200000, 1300000, +}; + +static const unsigned int va09_voltages[] = { + 0, 0, 800000, 900000, 0, 0, 1200000, +}; + +static const unsigned int vrf18_voltages[] = { + 0, 0, 0, 0, 0, 1700000, 1800000, 1810000, +}; + +static const unsigned int vbbck_voltages[] = { + 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000, +}; + +static const unsigned int vsim2_voltages[] = { + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, +}; + +static int mt6359_set_voltage_sel_regmap(struct udevice *dev, + struct mt6359_regulator_info *info, + unsigned int sel) +{ + sel <<= ffs(info->desc.vsel_mask) - 1; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, sel); +} + +static int mt6359p_vemc_set_voltage_sel(struct udevice *dev, + struct mt6359_regulator_info *info, unsigned int sel) +{ + int ret; + + sel <<= ffs(info->desc.vsel_mask) - 1; + ret = pmic_reg_write(dev->parent, MT6359P_TMA_KEY_ADDR, MT6359P_TMA_KEY); + if (ret) + return ret; + + ret = pmic_reg_read(dev->parent, MT6359P_VM_MODE_ADDR); + if (ret < 0) + return ret; + + switch (ret) { + case 0: + /* If HW trapping is 0, use VEMC_VOSEL_0 */ + ret = pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, sel); + if (ret) + return ret; + + break; + case 1: + /* If HW trapping is 1, use VEMC_VOSEL_1 */ + ret = pmic_clrsetbits(dev->parent, info->desc.vsel_reg + 0x2, + info->desc.vsel_mask, sel); + if (ret) + return ret; + + break; + default: + return -EINVAL; + } + + return pmic_reg_write(dev->parent, MT6359P_TMA_KEY_ADDR, 0); +} + +static int mt6359_get_voltage_sel(struct udevice *dev, struct mt6359_regulator_info *info) +{ + int selector; + + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + if (selector < 0) + return selector; + + selector &= info->desc.vsel_mask; + selector >>= ffs(info->desc.vsel_mask) - 1; + + return selector; +} + +static int mt6359p_vemc_get_voltage_sel(struct udevice *dev, struct mt6359_regulator_info *info) +{ + int selector; + + switch (pmic_reg_read(dev->parent, MT6359P_VM_MODE_ADDR)) { + case 0: + /* If HW trapping is 0, use VEMC_VOSEL_0 */ + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + break; + case 1: + /* If HW trapping is 1, use VEMC_VOSEL_1 */ + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg + 0x2); + break; + default: + return -EINVAL; + } + if (selector < 0) + return selector; + + selector &= info->desc.vsel_mask; + selector >>= ffs(info->desc.vsel_mask) - 1; + + return selector; +} + +static int mt6359_get_enable(struct udevice *dev) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.enable_reg); + if (ret < 0) + return ret; + + return ret & info->desc.enable_mask ? true : false; +} + +static int mt6359_set_enable(struct udevice *dev, bool enable) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + + return pmic_clrsetbits(dev->parent, info->desc.enable_reg, + info->desc.enable_mask, + enable ? info->desc.enable_mask : 0); +} + +static int mt6359_get_value(struct udevice *dev) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int selector; + + switch (info->desc.type) { + case MT6359_REG_TYPE_LINEAR: + /* Get selection */ + selector = mt6359_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.min_uV + (info->desc.uV_step * selector); + case MT6359_REG_TYPE_TABLE: + /* Get selection */ + selector = mt6359_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (!info->desc.volt_table) { + dev_err(dev, "invalid voltage table for %s\n", info->desc.name); + return -EINVAL; + } + + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.volt_table[selector]; + case MT6359_REG_TYPE_FIXED: + return info->desc.fixed_uV; + case MT6359_REG_TYPE_VEMC: + /* Get selection */ + selector = mt6359p_vemc_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (!info->desc.volt_table) { + dev_err(dev, "invalid voltage table for %s\n", info->desc.name); + return -EINVAL; + } + + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.volt_table[selector]; + default: + return -EINVAL; + } +} + +static int mt6359_set_value(struct udevice *dev, int uvolt) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int selector; + int i; + + switch (info->desc.type) { + case MT6359_REG_TYPE_LINEAR: + /* Find selection */ + if (uvolt < info->desc.min_uV) + return -EINVAL; + selector = DIV_ROUND_UP(uvolt - info->desc.min_uV, info->desc.uV_step); + if (selector < 0) + return -EINVAL; + + /* Set selection */ + return mt6359_set_voltage_sel_regmap(dev, info, selector); + case MT6359_REG_TYPE_TABLE: + /* Find selection */ + for (i = 0; i < info->desc.n_voltages; i++) { + if (info->desc.volt_table[i] == uvolt) + return mt6359_set_voltage_sel_regmap(dev, info, i); + } + + return -EINVAL; + case MT6359_REG_TYPE_VEMC: + /* Find selection */ + for (i = 0; i < info->desc.n_voltages; i++) { + if (info->desc.volt_table[i] == uvolt) + return mt6359p_vemc_set_voltage_sel(dev, info, i); + } + + return -EINVAL; + default: + return -EINVAL; + } +} + +static struct mt6359_regulator_info mt6359p_regulators[] = { + MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, + MT6359_RG_BUCK_VS1_EN_ADDR, + MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR, + MT6359_RG_BUCK_VS1_VOSEL_MASK << + MT6359_RG_BUCK_VS1_VOSEL_SHIFT, + MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT, + MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT), + MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, + MT6359_RG_BUCK_VGPU11_EN_ADDR, + MT6359_DA_VGPU11_EN_ADDR, MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR, + MT6359_RG_BUCK_VGPU11_VOSEL_MASK << + MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT, + MT6359_RG_BUCK_VGPU11_LP_ADDR, + MT6359_RG_BUCK_VGPU11_LP_SHIFT, + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), + MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, + MT6359_RG_BUCK_VMODEM_EN_ADDR, + MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR, + MT6359_RG_BUCK_VMODEM_VOSEL_MASK << + MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT, + MT6359_RG_BUCK_VMODEM_LP_ADDR, + MT6359_RG_BUCK_VMODEM_LP_SHIFT, + MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT), + MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPU_EN_ADDR, + MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR, + MT6359_RG_BUCK_VPU_VOSEL_MASK << + MT6359_RG_BUCK_VPU_VOSEL_SHIFT, + MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT, + MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT), + MT6359_BUCK("buck_vcore", VCORE, 506250, 1300000, 6250, + MT6359_RG_BUCK_VCORE_EN_ADDR, + MT6359_DA_VCORE_EN_ADDR, MT6359P_RG_BUCK_VCORE_VOSEL_ADDR, + MT6359_RG_BUCK_VCORE_VOSEL_MASK << + MT6359_RG_BUCK_VCORE_VOSEL_SHIFT, + MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, + MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), + MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, + MT6359_RG_BUCK_VS2_EN_ADDR, + MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR, + MT6359_RG_BUCK_VS2_VOSEL_MASK << + MT6359_RG_BUCK_VS2_VOSEL_SHIFT, + MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT, + MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT), + MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, + MT6359_RG_BUCK_VPA_EN_ADDR, + MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR, + MT6359_RG_BUCK_VPA_VOSEL_MASK << + MT6359_RG_BUCK_VPA_VOSEL_SHIFT, + MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT, + MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT), + MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPROC2_EN_ADDR, + MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR, + MT6359_RG_BUCK_VPROC2_VOSEL_MASK << + MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT, + MT6359_RG_BUCK_VPROC2_LP_ADDR, + MT6359_RG_BUCK_VPROC2_LP_SHIFT, + MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT), + MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPROC1_EN_ADDR, + MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR, + MT6359_RG_BUCK_VPROC1_VOSEL_MASK << + MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT, + MT6359_RG_BUCK_VPROC1_LP_ADDR, + MT6359_RG_BUCK_VPROC1_LP_SHIFT, + MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT), + MT6359_BUCK("buck_vgpu11_sshub", VGPU11_SSHUB, 400000, 1193750, 6250, + MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR, + MT6359_DA_VGPU11_EN_ADDR, + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR, + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK << + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT, + MT6359_RG_BUCK_VGPU11_LP_ADDR, + MT6359_RG_BUCK_VGPU11_LP_SHIFT, + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), + MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359P_RG_LDO_VAUD18_EN_ADDR, + MT6359P_DA_VAUD18_B_EN_ADDR, 1800000), + MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages, + MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT, + MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR, + MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vibr", VIBR, vibr_voltages, + MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT, + MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR, + MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages, + MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT, + MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR, + MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT, + 480), + MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359P_RG_LDO_VUSB_EN_0_ADDR, + MT6359P_DA_VUSB_B_EN_ADDR, 3000000), + MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR, + MT6359P_DA_VSRAM_PROC2_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), + MT6359_LDO("ldo_vio18", VIO18, volt18_voltages, + MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT, + MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR, + MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages, + MT6359P_RG_LDO_VCAMIO_EN_ADDR, + MT6359P_RG_LDO_VCAMIO_EN_SHIFT, + MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR, + MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT, + 1290), + MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359P_RG_LDO_VCN18_EN_ADDR, + MT6359P_DA_VCN18_B_EN_ADDR, 1800000), + MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359P_RG_LDO_VFE28_EN_ADDR, + MT6359P_DA_VFE28_B_EN_ADDR, 2800000), + MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages, + MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT, + MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR, + MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages, + MT6359P_RG_LDO_VCN33_1_EN_0_ADDR, + MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, + MT6359_RG_VCN33_1_VOSEL_MASK << + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages, + MT6359P_RG_LDO_VCN33_1_EN_1_ADDR, + MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT, + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, + MT6359_RG_VCN33_1_VOSEL_MASK << + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), + MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359P_RG_LDO_VAUX18_EN_ADDR, + MT6359P_DA_VAUX18_B_EN_ADDR, 1800000), + MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR, + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), + MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, + MT6359P_RG_LDO_VEFUSE_EN_ADDR, + MT6359P_RG_LDO_VEFUSE_EN_SHIFT, + MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR, + MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages, + MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT, + MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR, + MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages_1, + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vrfck_1", VRFCK, vrfck_voltages_1, + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, + 480), + MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359P_RG_LDO_VBIF28_EN_ADDR, + MT6359P_DA_VBIF28_B_EN_ADDR, 2800000), + MT6359_LDO("ldo_vio28", VIO28, vio28_voltages, + MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT, + MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR, + MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT, + 1920), + MT6359P_LDO1("ldo_vemc_1", VEMC, MT6359_REG_TYPE_VEMC, vemc_voltages_1, + MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT, + MT6359P_DA_VEMC_B_EN_ADDR, + MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR, + MT6359P_RG_LDO_VEMC_VOSEL_0_MASK << + MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT), + MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages, + MT6359P_RG_LDO_VCN33_2_EN_0_ADDR, + MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT, + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, + MT6359_RG_VCN33_2_VOSEL_MASK << + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages, + MT6359P_RG_LDO_VCN33_2_EN_1_ADDR, + MT6359_RG_LDO_VCN33_2_EN_1_SHIFT, + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, + MT6359_RG_VCN33_2_VOSEL_MASK << + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_va12", VA12, va12_voltages, + MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT, + MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR, + MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_va09", VA09, va09_voltages, + MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT, + MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR, + MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages, + MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT, + MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR, + MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT, + 240), + MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_MD_EN_ADDR, + MT6359P_DA_VSRAM_MD_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT), + MT6359_LDO("ldo_vufs", VUFS, volt18_voltages, + MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT, + MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR, + MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT, + 1920), + MT6359_LDO("ldo_vm18", VM18, volt18_voltages, + MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT, + MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR, + MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT, + 1920), + MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages, + MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT, + MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR, + MT6359P_RG_VBBCK_VOSEL_MASK << MT6359P_RG_VBBCK_VOSEL_SHIFT, + 480), + MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR, + MT6359P_DA_VSRAM_PROC1_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), + MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages, + MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT, + MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR, + MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT, + 480), + MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, + 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), +}; + +static int mt6359_regulator_probe(struct udevice *dev) +{ + struct mt6359_regulator_info *priv = dev_get_priv(dev); + int i, hw_ver; + + hw_ver = pmic_reg_read(dev->parent, MT6359P_HWCID); + if (hw_ver < MT6359P_CHIP_VER) { + dev_err(dev, "mt6359 is not supported. Only support mt6359p, hw_ver(%d)\n", + hw_ver); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(mt6359p_regulators); i++) { + if (!strcmp(dev->name, mt6359p_regulators[i].desc.of_match)) { + *priv = mt6359p_regulators[i]; + return 0; + } + } + + return -ENOENT; +} + +static const struct dm_regulator_ops mt6359_regulator_ops = { + .get_value = mt6359_get_value, + .set_value = mt6359_set_value, + .get_enable = mt6359_get_enable, + .set_enable = mt6359_set_enable, +}; + +U_BOOT_DRIVER(mt6359_regulator) = { + .name = MT6359_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &mt6359_regulator_ops, + .probe = mt6359_regulator_probe, + .priv_auto = sizeof(struct mt6359_regulator_info), +}; diff --git a/drivers/power/regulator/pwm_regulator.c b/drivers/power/regulator/pwm_regulator.c index ff738faadc5..adde5156c76 100644 --- a/drivers/power/regulator/pwm_regulator.c +++ b/drivers/power/regulator/pwm_regulator.c @@ -11,12 +11,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct pwm_regulator_info { /* pwm id corresponding to the PWM driver */ int pwm_id; diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 94c52cf555b..1c7f75a9338 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -449,7 +449,7 @@ static int regulator_post_bind(struct udevice *dev) } if (!regulator_name_is_unique(dev, uc_pdata->name)) { - dev_err(dev, "'%s' has nonunique value: '%s\n", + dev_err(dev, "'%s' has nonunique value: '%s'\n", property, uc_pdata->name); return -EINVAL; } diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index bb37b39fa0e..fc5d2a3e5e3 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -232,17 +232,19 @@ static int imx_pwm_of_to_plat(struct udevice *dev) priv->regs = dev_read_addr_ptr(dev); - ret = clk_get_by_name(dev, "per", &priv->per_clk); - if (ret) { - printf("Failed to get per_clk\n"); - return ret; - } + if (CONFIG_IS_ENABLED(CLK)) { + ret = clk_get_by_name(dev, "per", &priv->per_clk); + if (ret) { + printf("Failed to get per_clk\n"); + return ret; + } - ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); - if (ret) { - printf("Failed to get ipg_clk\n"); - return ret; - } + ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); + if (ret) { + printf("Failed to get ipg_clk\n"); + return ret; + } + } return 0; } @@ -252,17 +254,19 @@ static int imx_pwm_probe(struct udevice *dev) int ret; struct imx_pwm_priv *priv = dev_get_priv(dev); - ret = clk_enable(&priv->per_clk); - if (ret) { - printf("Failed to enable per_clk\n"); - return ret; - } + if (CONFIG_IS_ENABLED(CLK)) { + ret = clk_enable(&priv->per_clk); + if (ret) { + printf("Failed to enable per_clk\n"); + return ret; + } - ret = clk_enable(&priv->ipg_clk); - if (ret) { - printf("Failed to enable ipg_clk\n"); - return ret; - } + ret = clk_enable(&priv->ipg_clk); + if (ret) { + printf("Failed to enable ipg_clk\n"); + return ret; + } + } return 0; } diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index e9777c71f5e..dea7bc57495 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -40,8 +39,6 @@ #define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0 #define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff -DECLARE_GLOBAL_DATA_PTR; - struct pwm_sifive_regs { unsigned long cfg; unsigned long cnt; diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 0a64eb01dc2..b51dee31a98 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct rockchip_pwm_data { struct rockchip_pwm_regs regs; unsigned int prescaler; diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c index 2140a05b679..1dd2428da77 100644 --- a/drivers/pwm/sunxi_pwm.c +++ b/drivers/pwm/sunxi_pwm.c @@ -9,13 +9,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define OSC_24MHZ 24000000 struct sunxi_pwm_priv { diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index e3f1417f2ad..3d8f9daa2b0 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -4,38 +4,94 @@ */ #include +#include +#include #include #include #include #include #include +#include + +#define PWM_PDIV_WIDTH 8 +#define PWM_PDIV_MAX BIT(PWM_PDIV_WIDTH) +#define PWM_FDIV_WIDTH 13 struct tegra_pwm_priv { struct pwm_ctlr *regs; + u64 clk_rate; + u32 min_period_ns; + u8 polarity; }; +static int tegra_pwm_set_invert(struct udevice *dev, uint channel, bool polarity) +{ + struct tegra_pwm_priv *priv = dev_get_priv(dev); + + if (channel >= 4) + return -EINVAL; + + clrsetbits_8(&priv->polarity, BIT(channel), (polarity << channel)); + + return 0; +} + static int tegra_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, uint duty_ns) { struct tegra_pwm_priv *priv = dev_get_priv(dev); struct pwm_ctlr *regs = priv->regs; - const u32 pwm_max_freq = dev_get_driver_data(dev); - uint pulse_width; + u64 pulse_width; u32 reg; + s64 rate; if (channel >= 4) return -EINVAL; debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq); + if (period_ns < priv->min_period_ns) { + debug("%s: Channel %u period too low, period_ns %u minimum %u\n", + __func__, channel, period_ns, priv->min_period_ns); + return -EINVAL; + } - pulse_width = duty_ns * 255 / period_ns; + /* + * Convert from duty_ns / period_ns to a fixed number of duty ticks + * per (1 << PWM_PDIV_WIDTH) cycles and make sure to round to the + * nearest integer during division. + */ + pulse_width = duty_ns * PWM_PDIV_MAX; + pulse_width = DIV_ROUND_CLOSEST_ULL(pulse_width, period_ns); + + if (priv->polarity & BIT(channel)) + pulse_width = PWM_PDIV_MAX - pulse_width; + + if (pulse_width > PWM_PDIV_MAX) { + debug("%s: Channel %u pulse_width too high %llu\n", + __func__, channel, pulse_width); + return -EINVAL; + } + + /* + * Since the actual PWM divider is the register's frequency divider + * field plus 1, we need to decrement to get the correct value to + * write to the register. + */ + rate = (priv->clk_rate * period_ns) / ((u64)NSEC_PER_SEC << PWM_PDIV_WIDTH) - 1; + if (rate < 0) { + debug("%s: Channel %u rate is not positive\n", __func__, channel); + return -EINVAL; + } + + if (rate >> PWM_FDIV_WIDTH) { + debug("%s: Channel %u rate too high %llu\n", __func__, channel, rate); + return -EINVAL; + } reg = pulse_width << PWM_WIDTH_SHIFT; - reg |= 1 << PWM_DIVIDER_SHIFT; + reg |= rate << PWM_DIVIDER_SHIFT; reg |= PWM_ENABLE_MASK; writel(reg, ®s[channel].control); - debug("%s: pulse_width=%u\n", __func__, pulse_width); return 0; } @@ -63,9 +119,32 @@ static int tegra_pwm_of_to_plat(struct udevice *dev) return 0; } +static int tegra_pwm_probe(struct udevice *dev) +{ + struct tegra_pwm_priv *priv = dev_get_priv(dev); + const u32 pwm_max_freq = dev_get_driver_data(dev); + struct clk *clk; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + debug("%s: Could not get PWM clock: %ld\n", __func__, PTR_ERR(clk)); + return PTR_ERR(clk); + } + + priv->clk_rate = clock_start_periph_pll(clk->id, CLOCK_ID_PERIPH, + pwm_max_freq); + priv->min_period_ns = (NSEC_PER_SEC / (pwm_max_freq >> PWM_PDIV_WIDTH)) + 1; + + debug("%s: clk_rate = %llu min_period_ns = %u\n", __func__, + priv->clk_rate, priv->min_period_ns); + + return 0; +} + static const struct pwm_ops tegra_pwm_ops = { .set_config = tegra_pwm_set_config, .set_enable = tegra_pwm_set_enable, + .set_invert = tegra_pwm_set_invert, }; static const struct udevice_id tegra_pwm_ids[] = { @@ -80,5 +159,6 @@ U_BOOT_DRIVER(tegra_pwm) = { .of_match = tegra_pwm_ids, .ops = &tegra_pwm_ops, .of_to_plat = tegra_pwm_of_to_plat, + .probe = tegra_pwm_probe, .priv_auto = sizeof(struct tegra_pwm_priv), }; diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index fd94aad0cd4..27921ae4921 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3506) += sdram_rk3506.o obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o diff --git a/drivers/ram/rockchip/sdram_rk3506.c b/drivers/ram/rockchip/sdram_rk3506.c new file mode 100644 index 00000000000..a8396ea8888 --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3506.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include +#include +#include + +#define PMUGRF_BASE 0xff910000 +#define OS_REG2_REG 0x208 + +static int rk3506_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = CFG_SYS_SDRAM_BASE; + info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG2_REG); + + return 0; +} + +static struct ram_ops rk3506_dmc_ops = { + .get_info = rk3506_dmc_get_info, +}; + +static const struct udevice_id rk3506_dmc_ids[] = { + { .compatible = "rockchip,rk3506-dmc" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_dmc) = { + .name = "rockchip_rk3506_dmc", + .id = UCLASS_RAM, + .of_match = rk3506_dmc_ids, + .ops = &rk3506_dmc_ops, +}; diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c index 6108faa7073..3b41d6045ad 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.c +++ b/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include "stm32mp1_tests.h" @@ -19,8 +18,6 @@ #define PATTERN_DEFAULT "-" -DECLARE_GLOBAL_DATA_PTR; - static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, size_t *bufsize, size_t default_size, size_t min_size) { diff --git a/drivers/reboot-mode/reboot-mode-gpio.c b/drivers/reboot-mode/reboot-mode-gpio.c index 22ee40c3433..8d3e53d50ee 100644 --- a/drivers/reboot-mode/reboot-mode-gpio.c +++ b/drivers/reboot-mode/reboot-mode-gpio.c @@ -10,8 +10,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static int reboot_mode_get(struct udevice *dev, u32 *buf) { int ret; diff --git a/drivers/reboot-mode/reboot-mode-rtc.c b/drivers/reboot-mode/reboot-mode-rtc.c index 4f4ad63febc..adca584d622 100644 --- a/drivers/reboot-mode/reboot-mode-rtc.c +++ b/drivers/reboot-mode/reboot-mode-rtc.c @@ -9,8 +9,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static int reboot_mode_get(struct udevice *dev, u32 *buf) { if (!buf) diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 2dbd3a21cea..47cb64fec77 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -22,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct resource_table { u32 ver; u32 num; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2fd91d6299c..66911199c8b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -208,7 +208,7 @@ config RESET_RASPBERRYPI config RESET_SCMI bool "Enable SCMI reset domain driver" - select SCMI_FIRMWARE + depends on SCMI_FIRMWARE help Enable this option if you want to support reset controller devices exposed by a SCMI agent based on SCMI reset domain diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index ee5b009d134..088545c6473 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index e57729f0ef9..36a205f9fca 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -115,7 +115,7 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10)) writel(0, data->modrst_base + 8); } diff --git a/drivers/reset/rst-rk3506.c b/drivers/reset/rst-rk3506.c new file mode 100644 index 00000000000..9c384db0589 --- /dev/null +++ b/drivers/reset/rst-rk3506.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#include +#include +#include + +/* 0xFF9A0000 + 0x0A00 */ +#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3506_register_offset[] = { + /* CRU-->SOFTRST_CON00 */ + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0), + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1), + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6), + RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10), + + /* CRU-->SOFTRST_CON02 */ + RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14), + RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15), + + /* CRU-->SOFTRST_CON03 */ + RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1), + RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4), + RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6), + RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9), + + /* CRU-->SOFTRST_CON04 */ + RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3), + RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6), + RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7), + RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10), + RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12), + RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13), + + /* CRU-->SOFTRST_CON05 */ + RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4), + RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5), + RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6), + RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7), + RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10), + RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15), + + /* CRU-->SOFTRST_CON06 */ + RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0), + RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8), + RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9), + RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11), + RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12), + RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14), + RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15), + + /* CRU-->SOFTRST_CON07 */ + RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0), + RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2), + RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3), + RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14), + + /* CRU-->SOFTRST_CON08 */ + RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0), + RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1), + + /* CRU-->SOFTRST_CON09 */ + RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1), + + /* CRU-->SOFTRST_CON10 */ + RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0), + RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1), + RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2), + RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3), + RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4), + + /* CRU-->SOFTRST_CON11 */ + RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4), + RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6), + RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8), + RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9), + RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10), + RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11), + RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12), + RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14), + RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15), + + /* CRU-->SOFTRST_CON12 */ + RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), + RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2), + RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3), + RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4), + RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10), + RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12), + RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15), + + /* CRU-->SOFTRST_CON13 */ + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4), + RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5), + RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6), + RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8), + RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9), + RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10), + RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12), + RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13), + RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15), + + /* CRU-->SOFTRST_CON14 */ + RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5), + RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6), + RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7), + RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8), + + /* CRU-->SOFTRST_CON17 */ + RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8), + RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10), + RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11), + RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12), + + /* CRU-->SOFTRST_CON18 */ + RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12), + RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14), + RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15), + + /* CRU-->SOFTRST_CON19 */ + RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0), + RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1), + RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3), + RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4), + RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6), + RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8), + + /* CRU-->SOFTRST_CON21 */ + RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6), + RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7), + RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10), + RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11), + RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12), + RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14), + RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15), + + /* CRU-->SOFTRST_CON22 */ + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1), +}; + +int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + return rockchip_reset_bind_lut(pdev, rk3506_register_offset, + reg_offset, reg_number); +} diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index ef1663f3450..65d9bf533cb 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -73,6 +73,7 @@ config RTC_DS1307 config RTC_DS1337 bool "Enable DS1337 driver" + depends on DM_RTC help Support for Dallas Semiconductor (now Maxim) DS1337/8/9 compatible Real Time Clock devices. @@ -81,15 +82,9 @@ config RTC_DS1337_NOOSC bool "Enable support for no oscillator output in DS1337 driver" depends on RTC_DS1337 -config RTC_DS1338 - bool "Enable DS1338 driver" - help - Support for Dallas Semiconductor (now Maxim) DS1338 and compatible - Real Time Clock devices. - config RTC_DS1374 bool "Enable DS1374 driver" - depends on !DM_RTC + depends on !DM_RTC && !DM_I2C help Support for Dallas Semiconductor (now Maxim) DS1374 and compatible Real Time Clock devices. @@ -171,12 +166,14 @@ config RTC_PCF85063 config RTC_PCF8563 bool "Philips PCF8563" + depends on DM_RTC help If you say yes here you get support for the Philips PCF8563 RTC and compatible chips. config RTC_PT7C4338 bool "Enable Pericom Technology PT7C4338 RTC driver" + depends on DM_RTC config RTC_RV3028 bool "Enable RV3028 driver" @@ -240,13 +237,14 @@ config RTC_MV config RTC_S35392A bool "Enable S35392A driver" + depends on DM_RTC select BITREVERSE help Enable s35392a driver which provides rtc get and set function. config RTC_MC13XXX bool "Enable MC13XXX RTC driver" - depends on !DM_RTC + depends on !DM_RTC && POWER_LEGACY config RTC_MC146818 bool "Enable MC146818 driver" @@ -258,6 +256,7 @@ config RTC_MC146818 config MCFRTC bool "Use common CF RTC driver" + depends on DM_RTC depends on M68K config SYS_MCFRTC_BASE @@ -267,9 +266,11 @@ config SYS_MCFRTC_BASE config RTC_MXS bool "Enable i.MXS RTC driver" depends on ARCH_MX23 || ARCH_MX28 + depends on !DM_RTC config RTC_M41T62 bool "Enable M41T62 driver" + depends on DM_RTC help Enable driver for ST's M41T62 compatible RTC devices (like RV-4162). It is a serial (I2C) real-time clock (RTC) with alarm. @@ -310,6 +311,7 @@ config RTC_ABX80X config RTC_DAVINCI bool "Enable TI OMAP RTC driver" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS + depends on DM_RTC help Say "yes" here to support the on chip real time clock present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx. diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 9df373d5148..782f5a3bc3d 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_$(PHASE_)DM_RTC) += rtc-uclass.o obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o obj-$(CONFIG_RTC_DS1307) += ds1307.o -obj-$(CONFIG_RTC_DS1338) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o obj-$(CONFIG_RTC_DS1672) += ds1672.o diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 77544298d8a..e9db6220c55 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -21,7 +21,6 @@ /* * RTC register addresses */ -#if defined CONFIG_RTC_DS1337 #define RTC_SEC_REG_ADDR 0x0 #define RTC_MIN_REG_ADDR 0x1 #define RTC_HR_REG_ADDR 0x2 @@ -32,18 +31,6 @@ #define RTC_CTL_REG_ADDR 0x0e #define RTC_STAT_REG_ADDR 0x0f #define RTC_TC_REG_ADDR 0x10 -#elif defined CONFIG_RTC_DS1388 -#define RTC_SEC_REG_ADDR 0x1 -#define RTC_MIN_REG_ADDR 0x2 -#define RTC_HR_REG_ADDR 0x3 -#define RTC_DAY_REG_ADDR 0x4 -#define RTC_DATE_REG_ADDR 0x5 -#define RTC_MON_REG_ADDR 0x6 -#define RTC_YR_REG_ADDR 0x7 -#define RTC_CTL_REG_ADDR 0x0c -#define RTC_STAT_REG_ADDR 0x0b -#define RTC_TC_REG_ADDR 0x0a -#endif /* * RTC control register bits @@ -62,132 +49,6 @@ #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ -#if !CONFIG_IS_ENABLED(DM_RTC) -static uchar rtc_read (uchar reg); -static void rtc_write (uchar reg, uchar val); - -/* - * Get the current time from the RTC - */ -int rtc_get (struct rtc_time *tmp) -{ - int rel = 0; - uchar sec, min, hour, mday, wday, mon_cent, year, control, status; - - control = rtc_read (RTC_CTL_REG_ADDR); - status = rtc_read (RTC_STAT_REG_ADDR); - sec = rtc_read (RTC_SEC_REG_ADDR); - min = rtc_read (RTC_MIN_REG_ADDR); - hour = rtc_read (RTC_HR_REG_ADDR); - wday = rtc_read (RTC_DAY_REG_ADDR); - mday = rtc_read (RTC_DATE_REG_ADDR); - mon_cent = rtc_read (RTC_MON_REG_ADDR); - year = rtc_read (RTC_YR_REG_ADDR); - - /* No century bit, assume year 2000 */ -#ifdef CONFIG_RTC_DS1388 - mon_cent |= 0x80; -#endif - - debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", - year, mon_cent, mday, wday, hour, min, sec, control, status); - - if (status & RTC_STAT_BIT_OSF) { - printf ("### Warning: RTC oscillator has stopped\n"); - /* clear the OSF flag */ - rtc_write (RTC_STAT_REG_ADDR, - rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); - rel = -1; - } - - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon_cent & 0x1F); - tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); - tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return rel; -} - -/* - * Set the RTC - */ -int rtc_set (struct rtc_time *tmp) -{ - uchar century; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); - - century = (tmp->tm_year >= 2000) ? 0x80 : 0; - rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); - - rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); - rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); - rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); - - return 0; -} - -/* - * Reset the RTC. We also enable the oscillator output on the - * SQW/INTB* pin and program it for 32,768 Hz output. Note that - * according to the datasheet, turning on the square wave output - * increases the current drain on the backup battery from about - * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn - * off the OSC output. - */ - -#ifdef CONFIG_RTC_DS1337_NOOSC - #define RTC_DS1337_RESET_VAL \ - (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) -#else - #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) -#endif -void rtc_reset (void) -{ -#ifdef CONFIG_RTC_DS1337 - rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); -#elif defined CONFIG_RTC_DS1388 - rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */ -#endif -#ifdef CONFIG_RTC_DS1339_TCR_VAL - rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); -#endif -#ifdef CONFIG_RTC_DS1388_TCR_VAL - rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); -#endif -} - -/* - * Helper functions - */ - -static -uchar rtc_read (uchar reg) -{ - return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); -} - -static void rtc_write (uchar reg, uchar val) -{ - i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); -} -#else static uchar rtc_read(struct udevice *dev, uchar reg) { return dm_i2c_reg_read(dev, reg); @@ -213,11 +74,6 @@ static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp) mon_cent = rtc_read(dev, RTC_MON_REG_ADDR); year = rtc_read(dev, RTC_YR_REG_ADDR); - /* No century bit, assume year 2000 */ -#ifdef CONFIG_RTC_DS1388 - mon_cent |= 0x80; -#endif - debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n", year, mon_cent, mday, wday); debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", @@ -278,17 +134,8 @@ static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp) #endif static int ds1337_rtc_reset(struct udevice *dev) { -#ifdef CONFIG_RTC_DS1337 rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); -#elif defined CONFIG_RTC_DS1388 - rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */ -#endif -#ifdef CONFIG_RTC_DS1339_TCR_VAL - rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); -#endif -#ifdef CONFIG_RTC_DS1388_TCR_VAL - rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); -#endif + return 0; } @@ -311,4 +158,3 @@ U_BOOT_DRIVER(rtc_ds1337) = { .of_match = ds1337_rtc_ids, .ops = &ds1337_rtc_ops, }; -#endif diff --git a/drivers/rtc/zynqmp_rtc.c b/drivers/rtc/zynqmp_rtc.c index 15122a04838..4fee75bf9cf 100644 --- a/drivers/rtc/zynqmp_rtc.c +++ b/drivers/rtc/zynqmp_rtc.c @@ -5,26 +5,30 @@ #define LOG_CATEGORY UCLASS_RTC +#include #include #include #include +#include /* RTC Registers */ #define RTC_SET_TM_WR 0x00 #define RTC_SET_TM_RD 0x04 #define RTC_CALIB_WR 0x08 +#define RTC_CALIB_RD 0x0C #define RTC_CUR_TM 0x10 #define RTC_INT_STS 0x20 #define RTC_CTRL 0x40 #define RTC_INT_SEC BIT(0) #define RTC_BATT_EN BIT(31) -#define RTC_CALIB_DEF 0x198233 +#define RTC_CALIB_DEF 0x7FFF +#define RTC_FREQ_MAX 0x10000 #define RTC_CALIB_MASK 0x1FFFFF struct zynqmp_rtc_priv { fdt_addr_t base; - unsigned int calibval; + unsigned long calibval; }; static int zynqmp_rtc_get(struct udevice *dev, struct rtc_time *tm) @@ -70,13 +74,6 @@ static int zynqmp_rtc_set(struct udevice *dev, const struct rtc_time *tm) */ new_time = rtc_mktime(tm) + 1; - /* - * Writing into calibration register will clear the Tick Counter and - * force the next second to be signaled exactly in 1 second period - */ - priv->calibval &= RTC_CALIB_MASK; - writel(priv->calibval, (priv->base + RTC_CALIB_WR)); - writel(new_time, priv->base + RTC_SET_TM_WR); /* @@ -107,15 +104,6 @@ static int zynqmp_rtc_init(struct udevice *dev) rtc_ctrl |= RTC_BATT_EN; writel(rtc_ctrl, priv->base + RTC_CTRL); - /* - * Based on crystal freq of 33.330 KHz - * set the seconds counter and enable, set fractions counter - * to default value suggested as per design spec - * to correct RTC delay in frequency over period of time. - */ - priv->calibval &= RTC_CALIB_MASK; - writel(priv->calibval, (priv->base + RTC_CALIB_WR)); - return 0; } @@ -128,8 +116,44 @@ static int zynqmp_rtc_probe(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; - priv->calibval = dev_read_u32_default(dev, "calibration", - RTC_CALIB_DEF); + ret = readl(priv->base + RTC_CALIB_RD); + if (!ret) { + struct clk rtc_clk; + unsigned long clk_rate; + + /* Get the RTC clock rate */ + ret = clk_get_by_name_optional(dev, "rtc", &rtc_clk); + if (!ret) { + clk_rate = clk_get_rate(&rtc_clk); + /* Use clock frequency if valid, fallback to calibration value */ + if (clk_rate > 0 && clk_rate <= RTC_FREQ_MAX) { + /* Valid clock frequency */ + priv->calibval = clk_rate - 1; + } else if (clk_rate == 0) { + priv->calibval = dev_read_u32_default(dev, "calibration", + RTC_CALIB_DEF); + } else { + dev_err(dev, "Invalid clock frequency 0x%lx\n", + clk_rate); + return -EINVAL; + } + } else { + /* Clock framework unavailable, use DT calibration */ + priv->calibval = dev_read_u32_default(dev, "calibration", + RTC_CALIB_DEF); + } + + /* Validate final calibration value */ + if (priv->calibval > RTC_FREQ_MAX) { + dev_err(dev, "Invalid calibration 0x%lx\n", + priv->calibval); + return -EINVAL; + } + + writel(priv->calibval, (priv->base + RTC_CALIB_WR)); + } else { + priv->calibval = ret & RTC_CALIB_MASK; + } ret = zynqmp_rtc_init(dev); diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index b76de1b22a8..c9af60d5d03 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -16,4 +16,7 @@ ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_SATA obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o endif +ifdef CONFIG_SPL_UFS_SUPPORT +obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o +endif endif diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 8fe6b38a8c7..116b696b08d 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -513,7 +513,7 @@ static int scsi_detect_dev(struct udevice *dev, int target, int lun, pccb->target = target; pccb->lun = lun; pccb->pdata = tempbuff; - pccb->datalen = 512; + pccb->datalen = 36; pccb->dma_dir = DMA_FROM_DEVICE; scsi_setup_inquiry(pccb); if (scsi_exec(dev, pccb)) { diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index b84cb9ec781..c86c883e0cb 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -398,7 +398,7 @@ config DEBUG_UART_PL010 config DEBUG_UART_PL011 bool "pl011" - depends on PL01X_SERIAL || PL011_SERIAL + depends on PL01X_SERIAL help Select this to enable a debug UART using the pl01x driver with the PL011 UART type. You will need to provide parameters to make this @@ -862,12 +862,6 @@ config INTEL_MID_SERIAL Select this to enable a UART for Intel MID platforms. This uses the ns16550 driver as a library. -config PL011_SERIAL - bool "ARM PL011 driver" - depends on !DM_SERIAL - help - Select this to enable a UART for platforms using PL011. - config PL01X_SERIAL bool "ARM PL010 and PL011 driver" depends on DM_SERIAL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index fe8d23be512..66088b44eb6 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -10,7 +10,6 @@ obj-y += serial.o endif obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o -obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_$(PHASE_)SYS_NS16550_SERIAL) += serial_ns16550.o obj-$(CONFIG_ALTERA_UART) += altera_uart.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 4f7de3ea215..2f24f47badf 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ @@ -140,9 +137,9 @@ static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr) } } else if (plat->flags & NS16550_FLAG_BE) { return readb(addr + (1 << plat->reg_shift) - 1); - } else { - return readb(addr); } + + return readb(addr); } #else static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr, diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index cc0491bc3c8..658cbd2bbc9 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static size_t _sandbox_serial_written = 1; static bool sandbox_serial_enabled = true; diff --git a/drivers/serial/serial_adi_uart4.c b/drivers/serial/serial_adi_uart4.c index 24b2071d705..8039ee4d1d8 100644 --- a/drivers/serial/serial_adi_uart4.c +++ b/drivers/serial/serial_adi_uart4.c @@ -78,8 +78,6 @@ #define ERXS BIT(8) #define ETXS BIT(9) -DECLARE_GLOBAL_DATA_PTR; - struct uart4_reg { u32 revid; u32 control; diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c index 2a93bbbcc9f..690de3fc085 100644 --- a/drivers/serial/serial_htif.c +++ b/drivers/serial/serial_htif.c @@ -8,14 +8,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define HTIF_DATA_BITS 48 #define HTIF_DATA_MASK ((1ULL << HTIF_DATA_BITS) - 1) #define HTIF_DATA_SHIFT 0 diff --git a/drivers/serial/serial_pl01x_internal.h b/drivers/serial/serial_pl01x_internal.h index 7ae3ae50908..3c481b1e3d1 100644 --- a/drivers/serial/serial_pl01x_internal.h +++ b/drivers/serial/serial_pl01x_internal.h @@ -26,11 +26,7 @@ struct pl01x_regs { u32 pl010_lcrl; /* 0x10 Line control register, low byte */ u32 pl010_cr; /* 0x14 Control register */ u32 fr; /* 0x18 Flag register (Read only) */ -#ifdef CONFIG_PL011_SERIAL_RLCR - u32 pl011_rlcr; /* 0x1c Receive line control register */ -#else u32 reserved; -#endif u32 ilpr; /* 0x20 IrDA low-power counter register */ u32 pl011_ibrd; /* 0x24 Integer baud rate register */ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c index e05805f6372..4ba8d3ee641 100644 --- a/drivers/serial/serial_xen.c +++ b/drivers/serial/serial_xen.c @@ -7,7 +7,6 @@ #include #include #include -#include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 console_evtchn; /* diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c index b6b92d3530d..7a50d5a5792 100644 --- a/drivers/smem/msm_smem.c +++ b/drivers/smem/msm_smem.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * The Qualcomm shared memory system is an allocate-only heap structure that * consists of one of more memory areas that can be accessed by the processors diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8c6c095a8cf..4ff17617d99 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -34,7 +34,7 @@ config DM_SPI spi_slave structure. config SPI_MEM - bool "SPI memory extension" + bool select DEVRES help Enable this option if you want to enable the SPI memory extension. @@ -43,7 +43,7 @@ config SPI_MEM config SPI_DIRMAP bool "SPI direct mapping" - depends on SPI_MEM + select SPI_MEM help Enable the SPI direct mapping API. Most modern SPI controllers can directly map a SPI memory (or a portion of the SPI memory) in the CPU @@ -62,7 +62,8 @@ config ADI_SPI3 config AIROHA_SNFI_SPI bool "Airoha SPI memory controller driver" - depends on SPI_MEM && ARCH_AIROHA + depends on ARCH_AIROHA + select SPI_MEM help Enable the Airoha SPI memory controller driver. This driver is originally based on the Airoha SNFI IP core. It can only be @@ -102,7 +103,8 @@ config ATH79_SPI config ATMEL_QSPI bool "Atmel Quad SPI Controller" - depends on ARCH_AT91 && SPI_MEM + depends on ARCH_AT91 + select SPI_MEM help Enable the Atmel Quad SPI controller in master mode. This driver does not support generic SPI. The implementation supports only the @@ -152,7 +154,7 @@ config BCMSTB_SPI config CORTINA_SFLASH bool "Cortina-Access Serial Flash controller driver" - depends on SPI_MEM + select SPI_MEM help Enable the Cortina-Access Serial Flash controller driver. This driver can be used to access the SPI NOR/NAND flash on platforms embedding this @@ -160,6 +162,7 @@ config CORTINA_SFLASH config CADENCE_QSPI bool "Cadence QSPI driver" + select SPI_MEM help Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this @@ -205,7 +208,7 @@ config CF_SPI config CV1800B_SPIF bool "Sophgo cv1800b SPI Flash Controller driver" - depends on SPI_MEM + select SPI_MEM help Enable the Sophgo cv1800b SPI Flash Controller driver. This driver can be used to access the SPI NOR flash on platforms embedding this @@ -243,6 +246,7 @@ config FSL_DSPI config FSL_QSPI bool "Freescale QSPI driver" + select SPI_MEM imply SPI_FLASH_BAR help Enable the Freescale Quad-SPI (QSPI) driver. This driver can be @@ -294,6 +298,7 @@ config MESON_SPIFC config MICROCHIP_COREQSPI bool "Microchip FPGA QSPI Controller driver" + select SPI_MEM help Enable the QSPI driver for Microchip FPGA QSPI controllers. This driver can be used on Polarfire SoC. @@ -343,7 +348,7 @@ config MT7621_SPI config MTK_SNOR bool "Mediatek SPI-NOR controller driver" - depends on SPI_MEM + select SPI_MEM select DEVRES help Enable the Mediatek SPINOR controller driver. This driver has @@ -351,7 +356,7 @@ config MTK_SNOR config MTK_SNFI_SPI bool "Mediatek SPI memory controller driver" - depends on SPI_MEM + select SPI_MEM help Enable the Mediatek SPI memory controller driver. This driver is originally based on the MediaTek SNFI IP core. It can only be @@ -360,7 +365,7 @@ config MTK_SNFI_SPI config MTK_SPIM bool "Mediatek SPI-MEM master controller driver" - depends on SPI_MEM + select SPI_MEM help Enable MediaTek SPI-MEM master controller driver. This driver mainly supports SPI flashes. You can use single, dual or quad mode @@ -385,6 +390,7 @@ config MXS_SPI config SPI_MXIC bool "Macronix MX25F0A SPI controller" + select SPI_MEM help Enable the Macronix MX25F0A SPI controller driver. This driver can be used to access the SPI flash on platforms embedding @@ -403,11 +409,19 @@ config NPCM_PSPI config NXP_FSPI bool "NXP FlexSPI driver" - depends on SPI_MEM + select SPI_MEM help Enable the NXP FlexSPI (FSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this NXP IP core. +config NXP_XSPI + bool "NXP XSPI driver" + depends on ARCH_IMX9 + select SPI_MEM + help + Enable the NXP External SPI (XSPI) driver. This driver can be used to + access the SPI NOR/NAND flash on platforms embedding this NXP IP core. + config OCTEON_SPI bool "Octeon SPI driver" depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2 @@ -513,7 +527,8 @@ config SANDBOX_SPI_MAX_CS config SPI_ASPEED_SMC bool "ASPEED SPI flash controller driver" - depends on DM_SPI && SPI_MEM && ARCH_ASPEED + depends on DM_SPI && ARCH_ASPEED + select SPI_MEM help Enable ASPEED SPI flash controller driver for AST2500 and AST2600 SoCs. @@ -534,7 +549,7 @@ config SOFT_SPI config SPI_SN_F_OSPI tristate "Socionext F_OSPI SPI flash controller" - depends on SPI_MEM + select SPI_MEM help This enables support for the Socionext F_OSPI controller for connecting an SPI flash memory over up to 8-bit wide bus. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 0dc2d23e172..13d9c5dce80 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o +obj-$(CONFIG_NXP_XSPI) += nxp_xspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c index db32e39add2..f00df93a5f5 100644 --- a/drivers/spi/ca_sflash.c +++ b/drivers/spi/ca_sflash.c @@ -21,9 +21,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; struct ca_sflash_regs { u32 idr; /* 0x00:Flash word ID Register */ diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a00642d09d3..e6f4ba49e77 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -35,6 +35,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, bytes_to_dma = n_rx - rx_rem; if (bytes_to_dma) { + if (priv->use_dac_mode) + clrbits_le32(priv->regbase + CQSPI_REG_CONFIG, + CQSPI_REG_CONFIG_DIRECT); + cadence_qspi_apb_enable_linear_mode(false); reg = readl(priv->regbase + CQSPI_REG_CONFIG); reg |= CQSPI_REG_CONFIG_ENBL_DMA; @@ -125,6 +129,9 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, memcpy(rxbuf, rxbuf + 1, n_rx - 1); } + if (priv->use_dac_mode) + cadence_qspi_apb_dac_mode_enable(priv->regbase); + return 0; } diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index d1404e13810..2a4a49c5f1c 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -254,8 +255,23 @@ static int cadence_spi_probe(struct udevice *bus) } priv->resets = devm_reset_bulk_get_optional(bus); - if (priv->resets) - reset_deassert_bulk(priv->resets); + if (priv->resets) { + /* Assert all OSPI reset lines */ + ret = reset_assert_bulk(priv->resets); + if (ret) { + dev_err(bus, "Failed to assert OSPI reset: %d\n", ret); + return ret; + } + + udelay(10); + + /* Deassert all OSPI reset lines */ + ret = reset_deassert_bulk(priv->resets); + if (ret) { + dev_err(bus, "Failed to deassert OSPI reset: %d\n", ret); + return ret; + } + } if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(priv); diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7ed35aa3e66..117e36376b7 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -275,7 +275,7 @@ int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, } } if (data_in) { - memcpy(data_in, buffer + 2 * cmd_len, tran_len); + memcpy(data_in, buffer + rx_offset, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c index a84b257fb1a..b3ff611e8f7 100644 --- a/drivers/spi/microchip_coreqspi.c +++ b/drivers/spi/microchip_coreqspi.c @@ -18,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * QSPI Control register mask defines */ diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index fde9b142fb8..79836d7e271 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define MVEBU_SPI_A3700_XFER_RDY BIT(1) #define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) #define MVEBU_SPI_A3700_BYTE_LEN BIT(5) diff --git a/drivers/spi/nxp_xspi.c b/drivers/spi/nxp_xspi.c new file mode 100644 index 00000000000..200138f5adf --- /dev/null +++ b/drivers/spi/nxp_xspi.c @@ -0,0 +1,914 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "nxp_xspi.h" + +static inline void xspi_writel(u32 val, u32 addr) +{ + void __iomem *_addr = (void __iomem *)(uintptr_t)addr; + + out_le32(_addr, val); +}; + +static inline u32 xspi_readl(u32 addr) +{ + return in_le32((uintptr_t)addr); +}; + +#define xspi_config_sfp_tg(x, env, sfar, ipcr) \ + do { \ + xspi_writel_offset(x, env, (sfar), SFP_TG_SFAR); \ + xspi_writel_offset(x, env, (ipcr), SFP_TG_IPCR); \ + } while (0) + +static int xspi_readl_poll_tout(struct nxp_xspi *x, int env, u32 offset, + u32 mask, u32 delay_us, u32 timeout_us, bool wait_mask_set) +{ + u32 reg; + void __iomem *addr = (void __iomem *)(uintptr_t)x->iobase + (env * ENV_ADDR_SIZE) + offset; + + if (wait_mask_set) + return readl_poll_sleep_timeout(addr, reg, (reg & mask), + delay_us, timeout_us); + else + return readl_poll_sleep_timeout(addr, reg, !(reg & mask), + delay_us, timeout_us); +}; + +static struct nxp_xspi_devtype_data imx94_data = { + .rxfifo = SZ_512, /* RX fifo Size*/ + .rx_buf_size = 64 * 4, /* RBDR buffer size */ + .txfifo = SZ_1K, + .ahb_buf_size = SZ_4K, + .quirks = 0, +}; + +static const struct udevice_id nxp_xspi_ids[] = { + { .compatible = "nxp,imx94-xspi", .data = (ulong)&imx94_data, }, + { } +}; + +static int nxp_xspi_claim_bus(struct udevice *dev) +{ + return 0; +} + +#if CONFIG_IS_ENABLED(CLK) +static int nxp_xspi_clk_prep_enable(struct nxp_xspi *x) +{ + return clk_enable(&x->clk); +}; + +static void nxp_xspi_clk_disable_unprep(struct nxp_xspi *x) +{ + clk_disable(&x->clk); +}; +#endif + +static int xspi_swreset(struct nxp_xspi *x) +{ + u32 reg; + + reg = xspi_readl_offset(x, 0, MCR); + reg |= (XSPI_MCR_SWRSTHD_MASK | XSPI_MCR_SWRSTSD_MASK); + xspi_writel_offset(x, 0, reg, MCR); + udelay(2); + reg &= ~(XSPI_MCR_SWRSTHD_MASK | XSPI_MCR_SWRSTSD_MASK); + xspi_writel_offset(x, 0, reg, MCR); + + return 0; +}; + +static void nxp_xspi_dll_bypass(struct nxp_xspi *x) +{ + u32 reg; + int ret; + + xspi_swreset(x); + + xspi_writel_offset(x, 0, 0, DLLCRA); + + reg = XSPI_DLLCRA_SLV_EN_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg = XSPI_DLLCRA_FREQEN_MASK | XSPI_DLLCRA_SLV_EN_MASK | + XSPI_DLLCRA_SLV_DLL_BYPASS_MASK | XSPI_DLLCRA_SLV_DLY_COARSE(7); + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg |= XSPI_DLLCRA_SLV_UPD_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + ret = xspi_readl_poll_tout(x, 0, XSPI_DLLSR, XSPI_DLLSR_SLVA_LOCK_MASK, 1, POLL_TOUT, true); + if (ret) + dev_err(x->dev, "DLL SLVA unlock, the DLL status is %x, need to check!\n", + xspi_readl(x->iobase + XSPI_DLLSR)); + + reg &= ~XSPI_DLLCRA_SLV_UPD_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); +} + +static void nxp_xspi_dll_auto(struct nxp_xspi *x, unsigned long rate) +{ + u32 reg; + int ret; + + xspi_swreset(x); + + xspi_writel_offset(x, 0, 0, DLLCRA); + + reg = XSPI_DLLCRA_SLV_EN_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg = XSPI_DLLCRA_DLL_REFCNTR(2) | XSPI_DLLCRA_DLLRES(8) | + XSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK | XSPI_DLLCRA_SLV_EN_MASK; + if (rate > MHZ(133)) + reg |= XSPI_DLLCRA_FREQEN_MASK; + + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg |= XSPI_DLLCRA_SLV_UPD_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + reg |= XSPI_DLLCRA_DLLEN_MASK; + xspi_writel_offset(x, 0, reg, DLLCRA); + + ret = xspi_readl_poll_tout(x, 0, XSPI_DLLSR, + XSPI_DLLSR_DLLA_LOCK_MASK | XSPI_DLLSR_SLVA_LOCK_MASK, + 1, POLL_TOUT, true); + if (ret) + dev_err(x->dev, "the DLL status is %x, need to check!\n", + xspi_readl(x->iobase + XSPI_DLLSR)); +} + +static void nxp_xspi_disable_ddr(struct nxp_xspi *x) +{ + u32 reg; + + reg = xspi_readl_offset(x, 0, MCR); + reg |= XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + reg &= ~(XSPI_MCR_DQS_EN_MASK | XSPI_MCR_DDR_EN_MASK); + reg &= ~XSPI_MCR_DQS_FA_SEL_MASK; + reg |= XSPI_MCR_DQS_FA_SEL(1); + xspi_writel_offset(x, 0, reg, MCR); + + reg = xspi_readl_offset(x, 0, FLSHCR); + reg &= ~XSPI_FLSHCR_TDH_MASK; + xspi_writel_offset(x, 0, reg, FLSHCR); + + xspi_writel_offset(x, 0, XSPI_SMPR_DLLFSMPFA(7), SMPR); + + reg = xspi_readl_offset(x, 0, MCR); + reg &= ~XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + x->support_max_rate = MHZ(133); +} + +static void nxp_xspi_enable_ddr(struct nxp_xspi *x) +{ + u32 reg; + + reg = xspi_readl_offset(x, 0, MCR); + reg |= XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + reg |= XSPI_MCR_DQS_EN_MASK | XSPI_MCR_DDR_EN_MASK; + reg &= ~XSPI_MCR_DQS_FA_SEL_MASK; + reg |= XSPI_MCR_DQS_FA_SEL(3); + xspi_writel_offset(x, 0, reg, MCR); + + reg = xspi_readl_offset(x, 0, FLSHCR); + reg |= XSPI_FLSHCR_TDH(1); + xspi_writel_offset(x, 0, reg, FLSHCR); + + xspi_writel_offset(x, 0, XSPI_SMPR_DLLFSMPFA(4), SMPR); + + reg = xspi_readl_offset(x, 0, MCR); + reg &= ~XSPI_MCR_MDIS_MASK; + xspi_writel_offset(x, 0, reg, MCR); + + x->support_max_rate = MHZ(200); +} + +static int nxp_xspi_set_speed(struct udevice *bus, uint speed) +{ + debug("%s: %u\n", __func__, speed); +#if CONFIG_IS_ENABLED(CLK) + struct nxp_xspi *x = dev_get_priv(bus); + int ret; + + nxp_xspi_clk_disable_unprep(x); + + ret = clk_set_rate(&x->clk, speed); + if (ret < 0) + return ret; + + ret = nxp_xspi_clk_prep_enable(x); + if (ret) + return ret; + + xspi_swreset(x); +#endif + return 0; +} + +static int nxp_xspi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int nxp_xspi_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) +{ + struct nxp_xspi *x; + struct udevice *bus; + + bus = slave->dev->parent; + x = dev_get_priv(bus); + + if (op->data.dir == SPI_MEM_DATA_OUT) { + if (op->data.nbytes > x->devtype_data->txfifo) + op->data.nbytes = x->devtype_data->txfifo; + } else { + if (op->data.nbytes > x->devtype_data->ahb_buf_size) + op->data.nbytes = x->devtype_data->ahb_buf_size; + else if (op->data.nbytes > x->devtype_data->rxfifo) + op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); + } + + return 0; +} + +static int nxp_xspi_check_buswidth(struct nxp_xspi *x, u8 width) +{ + switch (width) { + case 1: + case 2: + case 4: + case 8: + return 0; + } + + return -ENOTSUPP; +} + +static bool nxp_xspi_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct nxp_xspi *x; + struct udevice *bus; + int ret; + + bus = slave->dev->parent; + x = dev_get_priv(bus); + + ret = nxp_xspi_check_buswidth(x, op->cmd.buswidth); + + if (op->addr.nbytes) + ret |= nxp_xspi_check_buswidth(x, op->addr.buswidth); + + if (op->dummy.nbytes) + ret |= nxp_xspi_check_buswidth(x, op->dummy.buswidth); + + if (op->data.nbytes) + ret |= nxp_xspi_check_buswidth(x, op->data.buswidth); + + if (ret) + return false; + + /* + * The number of address bytes should be equal to or less than 4 bytes. + */ + if (op->addr.nbytes > 4) + return false; + + /* + * If requested address value is greater than controller assigned + * memory mapped space, return error as it didn't fit in the range + * of assigned address space. + */ + if (op->addr.val >= x->a1_size + x->a2_size) + return false; + + /* Max 64 dummy clock cycles supported */ + if (op->dummy.buswidth && + (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) + return false; + + /* Max data length, check controller limits and alignment */ + if (op->data.dir == SPI_MEM_DATA_IN && + (op->data.nbytes > x->devtype_data->ahb_buf_size || + (op->data.nbytes > x->devtype_data->rxfifo && + !IS_ALIGNED(op->data.nbytes, 8)))) + return false; + + if (op->data.dir == SPI_MEM_DATA_OUT && + op->data.nbytes > x->devtype_data->txfifo) + return false; + + if (op->cmd.dtr) + return spi_mem_dtr_supports_op(slave, op); + else + return spi_mem_default_supports_op(slave, op); +} + +static int xspi_update_lut(struct nxp_xspi *x, u32 seq_index, const u32 *lut_base, u32 num_of_seq) +{ + int ret; + + ret = xspi_readl_poll_tout(x, 0, XSPI_SR, XSPI_SR_BUSY_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear.\n", __func__); + return ret; + } + + xspi_writel_offset(x, 0, XSPI_LUT_KEY_VAL, LUTKEY); + xspi_writel_offset(x, 0, 0x2, LCKCR); + + for (int i = 0; i < num_of_seq; i++) + xspi_writel(*(lut_base + i), x->iobase + XSPI_LUT + (seq_index * 5 + i) * 4); + + xspi_writel_offset(x, 0, XSPI_LUT_KEY_VAL, LUTKEY); + xspi_writel_offset(x, 0, 0x1, LCKCR); + + return 0; +} + +static int nxp_xspi_prepare_lut(struct nxp_xspi *x, + const struct spi_mem_op *op) +{ + u32 lutval[5] = {0}; + int lutidx = 1; + int ret; + + /* cmd */ + if (op->cmd.dtr) { + lutval[0] |= LUT_DEF(0, CMD_DDR, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode >> 8); + lutval[lutidx / 2] |= LUT_DEF(lutidx, CMD_DDR, + LUT_PAD(op->cmd.buswidth), + op->cmd.opcode & 0x00ff); + lutidx++; + } else { + lutval[0] |= LUT_DEF(0, CMD_SDR, LUT_PAD(op->cmd.buswidth), + op->cmd.opcode); + } + + /* addr bytes */ + if (op->addr.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? RADDR_DDR : RADDR_SDR, + LUT_PAD(op->addr.buswidth), + op->addr.nbytes * 8); + lutidx++; + } + + /* dummy bytes, if needed */ + if (op->dummy.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, DUMMY_CYCLE, + LUT_PAD(op->data.buswidth), + op->dummy.nbytes * 8 / + op->dummy.buswidth / (op->dummy.dtr ? 2 : 1)); + lutidx++; + } + + /* read/write data bytes */ + if (op->data.nbytes) { + lutval[lutidx / 2] |= LUT_DEF(lutidx, + op->data.dir == SPI_MEM_DATA_IN ? + (op->data.dtr ? READ_DDR : READ_SDR) : + (op->data.dtr ? WRITE_DDR : WRITE_SDR), + LUT_PAD(op->data.buswidth), + 0); + lutidx++; + } + + /* stop condition. */ + lutval[lutidx / 2] |= LUT_DEF(lutidx, CMD_STOP, 0, 0); +#ifdef DEBUG + print_buffer(0, lutval, 4, lutidx / 2 + 1, 4); +#endif + ret = xspi_update_lut(x, CMD_LUT_FOR_IP_CMD, lutval, ARRAY_SIZE(lutval)); + if (ret) + return ret; + + if (op->data.nbytes && + (op->data.dir == SPI_MEM_DATA_IN || op->data.dir == SPI_MEM_DATA_OUT) && + op->addr.nbytes) { + ret = xspi_update_lut(x, CMD_LUT_FOR_AHB_CMD, lutval, ARRAY_SIZE(lutval)); + if (ret) + return ret; + } + + return 0; +} + +static void nxp_xspi_read_ahb(struct nxp_xspi *x, const struct spi_mem_op *op) +{ + u32 len = op->data.nbytes; + + /* Read out the data directly from the AHB buffer. */ + memcpy_fromio(op->data.buf.in, (void *)(uintptr_t)(x->ahb_addr + op->addr.val), len); +} + +static int nxp_xspi_fill_txfifo(struct nxp_xspi *x, + const struct spi_mem_op *op) +{ + const u8 *buf = (u8 *)op->data.buf.out; + int xfer_remaining_size = op->data.nbytes; + u32 reg, val = 0; + int ret; + + /* clear the TX FIFO. */ + xspi_set_reg_field(x, x->config.env, 1, MCR, CLR_TXF); + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_MCR, + XSPI_MCR_CLR_TXF_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for TX FIFO clear\n", __func__); + return ret; + } + + reg = XSPI_TBCT_WMRK((x->devtype_data->txfifo - ALIGN_DOWN(op->data.nbytes, 4)) / 4 + 1); + xspi_writel_offset(x, x->config.env, reg, TBCT); + + reg = x->ahb_addr + op->addr.val; + xspi_writel_offset(x, x->config.env, reg, SFP_TG_SFAR); + + udelay(2); + reg = XSPI_SFP_TG_IPCR_SEQID(CMD_LUT_FOR_IP_CMD) | XSPI_SFP_TG_IPCR_IDATSZ(op->data.nbytes); + u64 start = timer_get_us(); + + xspi_writel_offset(x, x->config.env, reg, SFP_TG_IPCR); + + while (xfer_remaining_size > 0) { + if (xspi_get_reg_field(x, x->config.env, SR, TXFULL)) + continue; + + if (xfer_remaining_size > 4) { + memcpy(&val, buf, 4); + buf += 4; + } else { + val = 0; + memcpy(&val, buf, xfer_remaining_size); + buf += xfer_remaining_size; + } + + xspi_writel_offset(x, x->config.env, val, TBDR); + xfer_remaining_size -= 4; + + if (xspi_get_reg_field(x, x->config.env, FR, ILLINE)) + break; + } + + /* Wait for controller being ready. */ + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, + XSPI_SR_BUSY_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear\n", __func__); + return ret; + } + + u32 trctr = xspi_get_reg_field(x, x->config.env, TBSR, TRCTR); + + if ((ALIGN(op->data.nbytes, 4) / 4) != trctr) + dev_dbg(x->dev, "Fail to write data. tx_size = %u, trctr = %u.\n", + op->data.nbytes, trctr * 4); + + dev_dbg(x->dev, "tx data size: %u bytes, spend: %llu us\r\n", + op->data.nbytes, timer_get_us() - start); + + return 0; +} + +static int nxp_xspi_read_rxfifo(struct nxp_xspi *x, + const struct spi_mem_op *op) +{ + u32 reg; + int ret, i; + u32 val; + + u8 *buf = op->data.buf.in; + + reg = XSPI_RBCT_WMRK(x->devtype_data->rx_buf_size / 4 - 1); + xspi_writel_offset(x, x->config.env, reg, RBCT); + + /* clear the TX FIFO. */ + xspi_set_reg_field(x, x->config.env, 1, MCR, CLR_RXF); + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_MCR, + XSPI_MCR_CLR_RXF_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for RX FIFO clear\n", __func__); + return ret; + } + + xspi_writel_offset(x, x->config.env, x->ahb_addr + op->addr.val, SFP_TG_SFAR); + reg = XSPI_SFP_TG_IPCR_SEQID(CMD_LUT_FOR_IP_CMD) | XSPI_SFP_TG_IPCR_IDATSZ(op->data.nbytes); + u64 start = timer_get_us(); + + xspi_writel_offset(x, x->config.env, reg, SFP_TG_IPCR); + + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, XSPI_SR_BUSY_MASK, 1, + POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear\n", __func__); + return ret; + } + + for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { + if (i == x->devtype_data->rx_buf_size) { + reg = xspi_readl_offset(x, x->config.env, FR); + reg |= XSPI_FR_RBDF_MASK; + xspi_writel_offset(x, x->config.env, reg, FR); + } + val = xspi_readl(x->iobase + (x->config.env * ENV_ADDR_SIZE) + + XSPI_RBDR + (i % x->devtype_data->rx_buf_size)); + memcpy(buf + i, &val, 4); + } + + if (i < op->data.nbytes) { + val = xspi_readl(x->iobase + (x->config.env * ENV_ADDR_SIZE) + + XSPI_RBDR + (i % x->devtype_data->rx_buf_size)); + memcpy(buf + i, &val, op->data.nbytes - i); + } + + /* clear the RX FIFO. */ + xspi_set_reg_field(x, x->config.env, 1, MCR, CLR_RXF); + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_MCR, + XSPI_MCR_CLR_RXF_MASK, 1, POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for RX FIFO clear\n", __func__); + return ret; + } + + dev_dbg(x->dev, "rx data size: %u bytes, spend: %llu us\r\n", + op->data.nbytes, timer_get_us() - start); + + return 0; +} + +static int nxp_xspi_xfer_cmd(struct nxp_xspi *x, const struct spi_mem_op *op) +{ + u32 reg; + int ret; + + xspi_writel_offset(x, x->config.env, x->ahb_addr + op->addr.val, SFP_TG_SFAR); + reg = XSPI_SFP_TG_IPCR_SEQID(CMD_LUT_FOR_IP_CMD) | XSPI_SFP_TG_IPCR_IDATSZ(op->data.nbytes); + xspi_writel_offset(x, x->config.env, reg, SFP_TG_IPCR); + + /* Wait for controller being ready. */ + ret = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, XSPI_SR_BUSY_MASK, 1, + POLL_TOUT, false); + if (ret) { + dev_err(x->dev, "%s: Timeout while waiting for busy flag to clear\n", __func__); + return ret; + } + + return 0; +} + +static void nxp_xspi_select_mem(struct nxp_xspi *xspi, struct spi_slave *slave, + const struct spi_mem_op *op) +{ + unsigned long rate = slave->max_hz; + + if (xspi->selected == spi_chip_select(slave->dev) && + xspi->dtr == op->cmd.dtr) + return; + + if (!op->cmd.dtr) { + nxp_xspi_disable_ddr(xspi); + rate = min(xspi->support_max_rate, rate); + xspi->dtr = false; + } else { + nxp_xspi_enable_ddr(xspi); + rate = min(xspi->support_max_rate, rate); + rate *= 2; + xspi->dtr = true; + } + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + nxp_xspi_clk_disable_unprep(xspi); + + ret = clk_set_rate(&xspi->clk, rate); + if (ret < 0) + return; + + ret = nxp_xspi_clk_prep_enable(xspi); + if (ret) + return; +#endif + + xspi->selected = spi_chip_select(slave->dev); + + if (!op->cmd.dtr || rate < MHZ(60)) + nxp_xspi_dll_bypass(xspi); + else + nxp_xspi_dll_auto(xspi, rate); +} + +static int nxp_xspi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct nxp_xspi *x; + struct udevice *bus; + int err = 0; + + bus = slave->dev->parent; + x = dev_get_priv(bus); + + dev_dbg(bus, "%s:%s:%d\n", __FILE__, __func__, __LINE__); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u, opcode = 0x%x\n", + op->cmd.buswidth, op->cmd.nbytes, op->cmd.dtr, op->cmd.opcode); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u, val = 0x%llx\n", + op->addr.buswidth, op->addr.nbytes, op->addr.dtr, op->addr.val); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u\n", + op->dummy.buswidth, op->dummy.nbytes, op->dummy.dtr); + dev_dbg(bus, "buswidth = %u, nbytes = %u, dtr = %u, dir = %u, buf = 0x%llx\n", + op->data.buswidth, op->data.nbytes, op->data.dtr, op->data.dir, + (u64)op->data.buf.in); + + nxp_xspi_select_mem(x, slave, op); + + nxp_xspi_prepare_lut(x, op); + /* + * If we have large chunks of data, we read them through the AHB bus by + * accessing the mapped memory. In all other cases we use IP commands + * to access the flash. Read via AHB bus may be corrupted due to + * existence of an errata and therefore discard AHB read in such cases. + */ + if (op->data.nbytes > (x->config.gmid ? x->devtype_data->rxfifo : DEFAULT_XMIT_SIZE) && + op->data.dir == SPI_MEM_DATA_IN) { + dev_dbg(bus, "ahb read\n"); + nxp_xspi_read_ahb(x, op); + } else { + dev_dbg(bus, "ip command\n"); + /* Wait for controller being ready. */ + err = xspi_readl_poll_tout(x, x->config.env, XSPI_SR, XSPI_SR_BUSY_MASK, + 1, POLL_TOUT, false); + if (err) { + dev_err(x->dev, "Timeout while waiting for XSPI busy flag to clear.\n"); + return err; + } + + xspi_writel_offset(x, x->config.env, GENMASK(31, 0), FR); + + if (op->data.nbytes) { + if (op->data.dir == SPI_MEM_DATA_OUT) + nxp_xspi_fill_txfifo(x, op); + else if (op->data.dir == SPI_MEM_DATA_IN) + nxp_xspi_read_rxfifo(x, op); + else + dev_dbg(x->dev, "%d: never should happen\r\n", __LINE__); + } else { + nxp_xspi_xfer_cmd(x, op); + } + } + +#ifdef DEBUG + if (op->data.nbytes <= 10) + if (op->data.dir != SPI_MEM_NO_DATA) + print_buffer(0, op->data.buf.out, 1, op->data.nbytes, 16); +#endif + + return err; +} + +static const struct spi_controller_mem_ops nxp_xspi_mem_ops = { + .adjust_op_size = nxp_xspi_adjust_op_size, + .supports_op = nxp_xspi_supports_op, + .exec_op = nxp_xspi_exec_op, +}; + +static const struct dm_spi_ops nxp_xspi_ops = { + .claim_bus = nxp_xspi_claim_bus, + .set_speed = nxp_xspi_set_speed, + .set_mode = nxp_xspi_set_mode, + .mem_ops = &nxp_xspi_mem_ops, +}; + +static int nxp_xspi_of_to_plat(struct udevice *bus) +{ + struct nxp_xspi *x = dev_get_priv(bus); + fdt_addr_t iobase; + fdt_addr_t iobase_size; + fdt_addr_t ahb_addr; + fdt_addr_t ahb_size; + +#if CONFIG_IS_ENABLED(CLK) + int ret; +#endif + + x->dev = bus; + + iobase = devfdt_get_addr_size_name(bus, "xspi_base", &iobase_size); + if (iobase == FDT_ADDR_T_NONE) { + dev_err(bus, "xspi_base regs missing\n"); + return -ENODEV; + } + x->iobase = iobase; + + ahb_addr = devfdt_get_addr_size_name(bus, "xspi_mmap", &ahb_size); + if (ahb_addr == FDT_ADDR_T_NONE) { + dev_err(bus, "xspi_mmap regs missing\n"); + return -ENODEV; + } + x->ahb_addr = ahb_addr; + x->a1_size = ahb_size; + x->a2_size = 0; + x->config.gmid = true; + x->config.env = 0; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(bus, "xspi", &x->clk); + if (ret) { + dev_err(bus, "failed to get xspi clock\n"); + return ret; + } +#endif + + dev_dbg(bus, "iobase=<0x%x>, ahb_addr=<0x%x>, a1_size=<0x%x>, a2_size=<0x%x>, env=<0x%x>, gmid=<0x%x>\n", + x->iobase, x->ahb_addr, x->a1_size, x->a2_size, x->config.env, x->config.gmid); + + return 0; +} + +static int nxp_xspi_config_ahb_buffers(struct nxp_xspi *x) +{ + u32 reg; + + reg = XSPI_BUF3CR_MSTRID(0xa); + xspi_writel_offset(x, 0, reg, BUF0CR); + reg = XSPI_BUF3CR_MSTRID(0x2); + xspi_writel_offset(x, 0, reg, BUF1CR); + reg = XSPI_BUF3CR_MSTRID(0xd); + xspi_writel_offset(x, 0, reg, BUF2CR); + + reg = XSPI_BUF3CR_MSTRID(0x6) | XSPI_BUF3CR_ALLMST_MASK; + reg |= XSPI_BUF3CR_ADATSZ(x->devtype_data->ahb_buf_size / 8U); + xspi_writel_offset(x, 0, reg, BUF3CR); + + /* Only the buffer3 is used */ + xspi_writel_offset(x, 0, 0, BUF0IND); + xspi_writel_offset(x, 0, 0, BUF1IND); + xspi_writel_offset(x, 0, 0, BUF2IND); + + /* Program the Sequence ID for read/write operation. */ + reg = XSPI_BFGENCR_SEQID_WR_EN_MASK | XSPI_BFGENCR_SEQID(CMD_LUT_FOR_AHB_CMD); + xspi_writel_offset(x, 0, reg, BFGENCR); + + /* AHB access towards flash is broken if this AHB alignment boundary is crossed */ + /* 0-No limit 1-256B 10-512B 11b-limit */ + xspi_set_reg_field(x, 0, 0, BFGENCR, ALIGN); + + return 0; +}; + +static void nxp_xspi_config_mdad(struct nxp_xspi *x) +{ + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG0MDAD); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG1MDAD); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG2MDAD_EXT); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG3MDAD_EXT); + xspi_writel_offset(x, 0, XSPI_TG2MDAD_EXT_VLD_MASK, TG4MDAD_EXT); +} + +static void nxp_xspi_config_frad(struct nxp_xspi *x) +{ + /* Enable Read/Write Access permissions & Valid */ + for (int i = 0; i < 8; i++) { + xspi_writel(XSPI_FRAD0_WORD2_MD0ACP_MASK | XSPI_FRAD0_WORD2_MD1ACP_MASK, + x->iobase + XSPI_FRAD0_WORD2 + (i * 0x20U)); + xspi_writel(XSPI_FRAD0_WORD3_VLD_MASK, + x->iobase + XSPI_FRAD0_WORD3 + (i * 0x20U)); + } + for (int i = 0; i < 8; i++) { + xspi_writel(XSPI_FRAD0_WORD2_MD0ACP_MASK | XSPI_FRAD0_WORD2_MD1ACP_MASK, + x->iobase + XSPI_FRAD8_WORD2 + (i * 0x20U)); + xspi_writel(XSPI_FRAD0_WORD3_VLD_MASK, + x->iobase + XSPI_FRAD8_WORD3 + (i * 0x20U)); + } +} + +static int nxp_xspi_default_setup(struct nxp_xspi *x) +{ + int ret = 0; + u32 reg; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_set_rate(&x->clk, 20UL * 1000000UL); + if (ret < 0) { + dev_err(x->dev, "clk_set_rate fail\n"); + return ret; + } + dev_dbg(x->dev, "clk rate = %lu\n", clk_get_rate(&x->clk)); + + ret = nxp_xspi_clk_prep_enable(x); + if (ret) { + dev_err(x->dev, "nxp_xspi_clk_prep_enable fail\n"); + return ret; + } +#endif + + if (x->config.gmid) { + reg = xspi_readl_offset(x, 0, MGC); + reg &= ~(XSPI_MGC_GVLD_MASK | XSPI_MGC_GVLDMDAD_MASK | XSPI_MGC_GVLDFRAD_MASK); + xspi_writel_offset(x, 0, reg, MGC); + + xspi_writel_offset(x, 0, GENMASK(31, 0), MTO); + } + + nxp_xspi_config_mdad(x); + nxp_xspi_config_frad(x); + + xspi_set_reg_field(x, 0, 0, MCR, MDIS); + + xspi_swreset(x); + + xspi_set_reg_field(x, 0, 1, MCR, MDIS); + + reg = xspi_readl_offset(x, 0, MCR); + reg &= ~(XSPI_MCR_END_CFG_MASK | XSPI_MCR_DQS_FA_SEL_MASK | + XSPI_MCR_DDR_EN_MASK | XSPI_MCR_DQS_EN_MASK | XSPI_MCR_CKN_FA_EN_MASK | + XSPI_MCR_DQS_OUT_EN_MASK | XSPI_MCR_ISD2FA_MASK | XSPI_MCR_ISD3FA_MASK); + + reg |= XSPI_MCR_ISD2FA_MASK; + reg |= XSPI_MCR_ISD3FA_MASK; + + reg |= XSPI_MCR_END_CFG(3); + + xspi_writel_offset(x, 0, reg, MCR); + + reg = xspi_readl_offset(x, 0, SFACR); + + reg &= ~(uint32_t)(XSPI_SFACR_CAS_MASK | XSPI_SFACR_WA_MASK | + XSPI_SFACR_BYTE_SWAP_MASK | XSPI_SFACR_WA_4B_EN_MASK | + XSPI_SFACR_FORCE_A10_MASK); + + xspi_writel_offset(x, 0, reg, SFACR); + + nxp_xspi_config_ahb_buffers(x); + + reg = XSPI_FLSHCR_TCSH(3) | XSPI_FLSHCR_TCSS(3); + xspi_writel_offset(x, 0, reg, FLSHCR); + + xspi_writel_offset(x, 0, x->ahb_addr + x->a1_size, SFA1AD); + xspi_writel_offset(x, 0, x->ahb_addr + x->a1_size + x->a2_size, SFA2AD); + + reg = XSPI_SMPR_DLLFSMPFA(7); + xspi_writel_offset(x, 0, reg, SMPR); + + xspi_set_reg_field(x, 0, 0, MCR, MDIS); + + xspi_swreset(x); + + x->selected = -1; + + return ret; +}; + +static int nxp_xspi_probe(struct udevice *bus) +{ + int ret; + struct nxp_xspi *x = dev_get_priv(bus); + + x->devtype_data = + (struct nxp_xspi_devtype_data *)dev_get_driver_data(bus); + + ret = nxp_xspi_default_setup(x); + if (ret) + dev_err(x->dev, "nxp_xspi_default_setup fail %d\n", ret); + + return ret; +}; + +U_BOOT_DRIVER(nxp_xspi) = { + .name = "nxp_xspi", + .id = UCLASS_SPI, + .of_match = nxp_xspi_ids, + .ops = &nxp_xspi_ops, + .of_to_plat = nxp_xspi_of_to_plat, + .priv_auto = sizeof(struct nxp_xspi), + .probe = nxp_xspi_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/spi/nxp_xspi.h b/drivers/spi/nxp_xspi.h new file mode 100644 index 00000000000..31c4147ebe1 --- /dev/null +++ b/drivers/spi/nxp_xspi.h @@ -0,0 +1,703 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __NXP_XSPI_H +#define __NXP_XSPI_H + +/* XSPI Register defination */ + +#define XSPI_MCR 0x0 + +#define XSPI_MCR_CKN_FA_EN_MASK BIT(26) +#define XSPI_MCR_CKN_FA_EN_SHIFT 26 +#define XSPI_MCR_DQS_FA_SEL_MASK GENMASK(25, 24) +#define XSPI_MCR_DQS_FA_SEL_SHIFT 24 +#define XSPI_MCR_DQS_FA_SEL(x) ((x) << 24) +#define XSPI_MCR_ISD3FA_MASK BIT(17) +#define XSPI_MCR_ISD3FA_SHIFT 17 +#define XSPI_MCR_ISD3FA_MASK BIT(17) +#define XSPI_MCR_ISD3FA_SHIFT 17 +#define XSPI_MCR_ISD2FA_MASK BIT(16) +#define XSPI_MCR_ISD2FA_SHIFT 16 +#define XSPI_MCR_DOZE_MASK BIT(15) +#define XSPI_MCR_DOZE_SHIFT 15 +#define XSPI_MCR_MDIS_MASK BIT(14) +#define XSPI_MCR_MDIS_SHIFT 14 +#define XSPI_MCR_DLPEN_MASK BIT(12) +#define XSPI_MCR_DLPEN_SHIFT 12 +#define XSPI_MCR_CLR_TXF_MASK BIT(11) +#define XSPI_MCR_CLR_TXF_SHIFT 11 +#define XSPI_MCR_CLR_RXF_MASK BIT(10) +#define XSPI_MCR_CLR_RXF_SHIFT 10 +#define XSPI_MCR_IPS_TG_RST_MASK BIT(9) +#define XSPI_MCR_IPS_TG_RST_SHIFT 9 +#define XSPI_MCR_VAR_LAT_EN_MASK BIT(8) +#define XSPI_MCR_VAR_LAT_EN_SHIFT 8 +#define XSPI_MCR_DDR_EN_MASK BIT(7) +#define XSPI_MCR_DDR_EN_SHIFT 7 +#define XSPI_MCR_DQS_EN_MASK BIT(6) +#define XSPI_MCR_DQS_EN_SHIFT 6 +#define XSPI_MCR_DQS_LAT_EN_MASK BIT(5) +#define XSPI_MCR_DQS_LAT_EN_SHIFT 5 +#define XSPI_MCR_DQS_OUT_EN_MASK BIT(4) +#define XSPI_MCR_DQS_OUT_EN_SHIFT 4 +#define XSPI_MCR_END_CFG_MASK GENMASK(3, 2) +#define XSPI_MCR_END_CFG_SHIFT 2 +#define XSPI_MCR_END_CFG(x) ((x) << 2) +#define XSPI_MCR_SWRSTHD_MASK BIT(1) +#define XSPI_MCR_SWRSTHD_SHIFT 1 +#define XSPI_MCR_SWRSTSD_MASK BIT(0) +#define XSPI_MCR_SWRSTSD_SHIFT 0 + +#define XSPI_IPCR 0x8U + +#define XSPI_IPCR_SEQID_MASK GENMASK(27, 24) +#define XSPI_IPCR_SEQID_SHIFT 24 +#define XSPI_IPCR_SEQID(x) ((x) << 24) +#define XSPI_IPCR_IDATSZ_MASK GENMASK(14, 0) +#define XSPI_IPCR_IDATSZ_SHIFT 0 +#define XSPI_IPCR_IDATSZ(x) ((x) << 0) + +#define XSPI_FLSHCR 0xCU + +#define XSPI_FLSHCR_TDH_MASK GENMASK(17, 16) +#define XSPI_FLSHCR_TDH_SHIFT 16 +#define XSPI_FLSHCR_TDH(x) ((x) << 16) +#define XSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) +#define XSPI_FLSHCR_TCSH_SHIFT 8 +#define XSPI_FLSHCR_TCSH(x) ((x) << 8) +#define XSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) +#define XSPI_FLSHCR_TCSS_SHIFT 0 +#define XSPI_FLSHCR_TCSS(x) ((x) << 0) + +#define XSPI_BUF0CR 0x010U + +#define XSPI_BUF0CR_HP_EN_MASK BIT(31) +#define XSPI_BUF0CR_HP_EN_SHIFT 31 +#define XSPI_BUF0CR_SUB_DIV_EN_MASK BIT(30) +#define XSPI_BUF0CR_SUB_DIV_EN_SHIFT 30 +#define XSPI_BUF0CR_SUBBUF2_DIV_MASK GENMASK(29, 27) +#define XSPI_BUF0CR_SUBBUF2_DIV_SHIFT 27 +#define XSPI_BUF0CR_SUBBUF2_DIV(x) ((x) << 27) +#define XSPI_BUF0CR_SUBBUF1_DIV_MASK GENMASK(26, 24) +#define XSPI_BUF0CR_SUBBUF1_DIV_SHIFT 24 +#define XSPI_BUF0CR_SUBBUF1_DIV(x) ((x) << 24) +#define XSPI_BUF0CR_SUBBUF0_DIV_MASK GENMASK(23, 21) +#define XSPI_BUF0CR_SUBBUF0_DIV_SHIFT 21 +#define XSPI_BUF0CR_SUBBUF0_DIV(x) ((x) << 21) +#define XSPI_BUF0CR_ADATSZ_MASK GENMASK(17, 8) +#define XSPI_BUF0CR_ADATSZ_SHIFT 8 +#define XSPI_BUF0CR_ADATSZ(x) ((x) << 8) +#define XSPI_BUF0CR_MSTRID_MASK GENMASK(3, 0) +#define XSPI_BUF0CR_MSTRID_SHIFT 0 +#define XSPI_BUF0CR_MSTRID(x) ((x) << 0) + +#define XSPI_BUF1CR 0x014U +#define XSPI_BUF2CR 0x018U +#define XSPI_BUF3CR 0x1CU + +#define XSPI_BUF3CR_ALLMST_MASK BIT(31) +#define XSPI_BUF3CR_ALLMST_SHIFT 31 +#define XSPI_BUF3CR_SUB_DIV_EN_MASK BIT(30) +#define XSPI_BUF3CR_SUB_DIV_EN_SHIFT 30 +#define XSPI_BUF3CR_SUBBUF2_DIV_MASK GENMASK(29, 27) +#define XSPI_BUF3CR_SUBBUF2_DIV_SHIFT 27 +#define XSPI_BUF3CR_SUBBUF2_DIV(x) ((x) << 27) +#define XSPI_BUF3CR_SUBBUF1_DIV_MASK GENMASK(26, 24) +#define XSPI_BUF3CR_SUBBUF1_DIV_SHIFT 24 +#define XSPI_BUF3CR_SUBBUF1_DIV(x) ((x) << 24) +#define XSPI_BUF3CR_SUBBUF0_DIV_MASK GENMASK(23, 21) +#define XSPI_BUF3CR_SUBBUF0_DIV_SHIFT 21 +#define XSPI_BUF3CR_SUBBUF0_DIV(x) ((x) << 21) +#define XSPI_BUF3CR_ADATSZ_MASK GENMASK(17, 8) +#define XSPI_BUF3CR_ADATSZ_SHIFT 8 +#define XSPI_BUF3CR_ADATSZ(x) ((x) << 8) +#define XSPI_BUF3CR_MSTRID_MASK GENMASK(3, 0) +#define XSPI_BUF3CR_MSTRID_SHIFT 0 +#define XSPI_BUF3CR_MSTRID(x) ((x) << 0) + +#define XSPI_BUF0IND 0x030U + +#define XSPI_BUF0IND_TPINDX_MASK GENMASK(12, 3) +#define XSPI_BUF0IND_TPINDX_SHIFT 3 +#define XSPI_BUF0IND_TPINDX(x) ((x) << 3) + +#define XSPI_BUF1IND 0x034U + +#define XSPI_BUF2IND 0x038U + +#define XSPI_AWRCR 0x50 + +#define XSPI_AWRCR_PPW_WR_DIS_MASK BIT(15) +#define XSPI_AWRCR_PPW_WR_DIS_SHIFT 15 +#define XSPI_AWRCR_PPW_RD_DIS_MASK BIT(14) +#define XSPI_AWRCR_PPW_RD_DIS_SHIFT 14 + +#define XSPI_DLLCRA 0x60U + +#define XSPI_DLLCRA_DLLEN_MASK BIT(31) +#define XSPI_DLLCRA_DLLEN_SHIFT 31 +#define XSPI_DLLCRA_FREQEN_MASK BIT(30) +#define XSPI_DLLCRA_FREQEN_SHIFT 30 +#define XSPI_DLLCRA_DLL_REFCNTR_MASK GENMASK(27, 24) +#define XSPI_DLLCRA_DLL_REFCNTR_SHIFT 24 +#define XSPI_DLLCRA_DLL_REFCNTR(x) ((x) << 24) +#define XSPI_DLLCRA_DLLRES_MASK GENMASK(23, 20) +#define XSPI_DLLCRA_DLLRES_SHIFT 20 +#define XSPI_DLLCRA_DLLRES(x) ((x) << 20) +#define XSPI_DLLCRA_SLV_FINE_OFFSET_MASK GENMASK(19, 16) +#define XSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT 16 +#define XSPI_DLLCRA_SLV_FINE_OFFSET(x) ((x) << 16) +#define XSPI_DLLCRA_SLV_DLY_OFFSET_MASK GENMASK(14, 12) +#define XSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT 12 +#define XSPI_DLLCRA_SLV_DLY_OFFSET(x) ((x) << 12) +#define XSPI_DLLCRA_SLV_DLY_COARSE_MASK GENMASK(11, 8) +#define XSPI_DLLCRA_SLV_DLY_COARSE_SHIFT 8 +#define XSPI_DLLCRA_SLV_DLY_COARSE(x) ((x) << 8) +#define XSPI_DLLCRA_SLV_DLY_FINE_MASK GENMASK(7, 5) +#define XSPI_DLLCRA_SLV_DLY_FINE_SHIFT 5 +#define XSPI_DLLCRA_SLV_DLY_FINE(x) ((x) << 5) +#define XSPI_DLLCRA_DLL_CDL8_MASK BIT(4) +#define XSPI_DLLCRA_DLL_CDL8_SHIFT 4 +#define XSPI_DLLCRA_SLAVE_AUTO_UPDT_MASK BIT(3) +#define XSPI_DLLCRA_SLAVE_AUTO_UPDT_SHIFT 3 +#define XSPI_DLLCRA_SLV_EN_MASK BIT(2) +#define XSPI_DLLCRA_SLV_EN_SHIFT 2 +#define XSPI_DLLCRA_SLV_DLL_BYPASS_MASK BIT(1) +#define XSPI_DLLCRA_SLV_DLL_BYPASS_SHIFT 1 +#define XSPI_DLLCRA_SLV_UPD_MASK BIT(0) +#define XSPI_DLLCRA_SLV_UPD_SHIFT 0 + +#define XSPI_SFACR 0x104U + +#define XSPI_SFACR_FORCE_A10_MASK BIT(22) +#define XSPI_SFACR_FORCE_A10_SHIFT 22 +#define XSPI_SFACR_WA_4B_EN_MASK BIT(21) +#define XSPI_SFACR_WA_4B_EN_SHIFT 21 +#define XSPI_SFACR_CAS_INTRLVD_MASK BIT(20) +#define XSPI_SFACR_CAS_INTRLVD_SHIFT 20 +#define XSPI_SFACR_RX_BP_EN_MASK BIT(18) +#define XSPI_SFACR_RX_BP_EN_SHIFT 18 +#define XSPI_SFACR_BYTE_SWAP_MASK BIT(17) +#define XSPI_SFACR_BYTE_SWAP_SHIFT 17 +#define XSPI_SFACR_WA_MASK BIT(16) +#define XSPI_SFACR_WA_SHIFT 16 +#define XSPI_SFACR_PPWB_MASK GENMASK(12, 8) +#define XSPI_SFACR_PPWB_SHIFT 8 +#define XSPI_SFACR_PPWB(x) ((x) << 8) +#define XSPI_SFACR_CAS_MASK GENMASK(3, 0) +#define XSPI_SFACR_CAS_SHIFT 0 +#define XSPI_SFACR_CAS(x) ((x) << 0) + +#define XSPI_SFAR 0x100U + +#define XSPI_SFAR_SFADR_MASK GENMASK(31, 0) +#define XSPI_SFAR_SFADR_SHIFT 0 +#define XSPI_SFAR_SFADR(x) ((x) << 0) + +#define XSPI_SMPR 0x108U + +#define XSPI_SMPR_DLLFSMPFA_MASK GENMASK(26, 24) +#define XSPI_SMPR_DLLFSMPFA_SHIFT 24 +#define XSPI_SMPR_DLLFSMPFA(x) ((x) << 24) +#define XSPI_SMPR_FSDLY_MASK BIT(6) +#define XSPI_SMPR_FSDLY_SHIFT 6 +#define XSPI_SMPR_FSPHS_MASK BIT(5) +#define XSPI_SMPR_FSPHS_SHIFT 5 + +#define XSPI_RBSR 0x10CU + +#define XSPI_RBSR_RDCTR_MASK GENMASK(31, 16) +#define XSPI_RBSR_RDCTR_SHIFT 16 +#define XSPI_RBSR_RDCTR(x) ((x) << 16) +#define XSPI_RBSR_RDBFL_MASK GENMASK(8, 0) +#define XSPI_RBSR_RDBFL_SHIFT 0 +#define XSPI_RBSR_RDBFL(x) ((x) << 0) + +#define XSPI_RBCT 0x110U + +#define XSPI_RBCT_WMRK_MASK GENMASK(8, 0) +#define XSPI_RBCT_WMRK_SHIFT 0 +#define XSPI_RBCT_WMRK(x) ((x) << 0) + +#define XSPI_DLLSR 0x12CU + +#define XSPI_DLLSR_DLLA_LOCK_MASK BIT(15) +#define XSPI_DLLSR_DLLA_LOCK_SHIFT 15 +#define XSPI_DLLSR_SLVA_LOCK_MASK BIT(14) +#define XSPI_DLLSR_SLVA_LOCK_SHIFT 14 +#define XSPI_DLLSR_DLLA_RANGE_ERR_MASK BIT(13) +#define XSPI_DLLSR_DLLA_RANGE_ERR_SHIFT 13 +#define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK BIT(12) +#define XSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT 12 +#define XSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK GENMASK(7, 4) +#define XSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT 4 +#define XSPI_DLLSR_DLLA_SLV_FINE_VAL(x) ((x) << 4) +#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK GENMASK(3, 0) +#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT 0 +#define XSPI_DLLSR_DLLA_SLV_COARSE_VAL(x) ((x) << 0) + +#define XSPI_DLCR 0x130U + +#define XSPI_DLCR_DL_NONDLP_FLSH_MASK BIT(24) +#define XSPI_DLCR_DL_NONDLP_FLSH_SHIFT 24 +#define XSPI_DLCR_DLP_SEL_FA_MASK GENMASK(15, 14) +#define XSPI_DLCR_DLP_SEL_FA_SHIFT 14 +#define XSPI_DLCR_DLP_SEL_FA(x) ((x) << 14) + +#define XSPI_TBSR 0x150U + +#define XSPI_TBSR_TRCTR_MASK GENMASK(31, 16) +#define XSPI_TBSR_TRCTR_SHIFT 16 +#define XSPI_TBSR_TRCTR(x) ((x) << 16) +#define XSPI_TBSR_TRBFL_MASK GENMASK(8, 0) +#define XSPI_TBSR_TRBFL_SHIFT 0 +#define XSPI_TBSR_TRBFL(x) ((x) << 0) + +#define XSPI_TBDR 0x154U + +#define XSPI_TBDR_TXDATA_MASK GENMASK(31, 0) +#define XSPI_TBDR_TXDATA_SHIFT 0 +#define XSPI_TBDR_TXDATA(x) ((x) << 0) + +#define XSPI_TBCT 0x158U + +#define XSPI_TBCT_WMRK_MASK GENMASK(7, 0) +#define XSPI_TBCT_WMRK_SHIFT 0 +#define XSPI_TBCT_WMRK(x) ((x) << 0) + +#define XSPI_SR 0x15CU + +#define XSPI_SR_TXFULL_MASK BIT(27) +#define XSPI_SR_TXFULL_SHIFT 27 +#define XSPI_SR_TXDMA_MASK BIT(26) +#define XSPI_SR_TXDMA_SHIFT 26 +#define XSPI_SR_TXWA_MASK BIT(25) +#define XSPI_SR_TXWA_SHIFT 25 +#define XSPI_SR_TXNE_MASK BIT(24) +#define XSPI_SR_TXNE_SHIFT 24 +#define XSPI_SR_RXDMA_MASK BIT(23) +#define XSPI_SR_RXDMA_SHIFT 23 +#define XSPI_SR_ARB_STATE_MASK GENMASK(22, 20) +#define XSPI_SR_ARB_STATE_SHIFT 20 +#define XSPI_SR_ARB_STATE(x) ((x) << 20) +#define XSPI_SR_RXFULL_MASK BIT(19) +#define XSPI_SR_RXFULL_SHIFT 19 +#define XSPI_SR_RXWE_MASK BIT(16) +#define XSPI_SR_RXWE_SHIFT 16 +#define XSPI_SR_ARB_LCK_MASK BIT(15) +#define XSPI_SR_ARB_LCK_SHIFT 15 +#define XSPI_SR_AHBnFUL_MASK GENMASK(14, 11) +#define XSPI_SR_AHBnFUL_SHIFT 11 +#define XSPI_SR_AHBnFUL(x) ((x) << 11) +#define XSPI_SR_AHBnNE_MASK GENMASK(10, 7) +#define XSPI_SR_AHBnNE_SHIFT 7 +#define XSPI_SR_AHBnNE(x) ((x) << 7) +#define XSPI_SR_AHBTRN_MASK BIT(6) +#define XSPI_SR_AHBTRN_SHIFT 6 +#define XSPI_SR_AWRACC_MASK BIT(4) +#define XSPI_SR_AWRACC_SHIFT 4 +#define XSPI_SR_AHB_ACC_MASK BIT(2) +#define XSPI_SR_AHB_ACC_SHIFT 2 +#define XSPI_SR_IP_ACC_MASK BIT(1) +#define XSPI_SR_IP_ACC_SHIFT 1 +#define XSPI_SR_BUSY_MASK BIT(0) +#define XSPI_SR_BUSY_SHIFT 0 + +#define XSPI_FR 0x160U + +#define XSPI_FR_DLPFF_MASK BIT(31) +#define XSPI_FR_DLPFF_SHIFT 31 +#define XSPI_FR_DLLABRT_MASK BIT(28) +#define XSPI_FR_DLLABRT_SHIFT 28 +#define XSPI_FR_TBFF_MASK BIT(27) +#define XSPI_FR_TBFF_SHIFT 27 +#define XSPI_FR_TBUF_MASK BIT(26) +#define XSPI_FR_TBUF_SHIFT 26 +#define XSPI_FR_DLLUNLCK_MASK BIT(24) +#define XSPI_FR_DLLUNLCK_SHIFT 24 +#define XSPI_FR_ILLINE_MASK BIT(23) +#define XSPI_FR_ILLINE_SHIFT 23 +#define XSPI_FR_RBOF_MASK BIT(17) +#define XSPI_FR_RBOF_SHIFT 17 +#define XSPI_FR_RBDF_MASK BIT(16) +#define XSPI_FR_RBDF_SHIFT 16 +#define XSPI_FR_AAEF_MASK BIT(15) +#define XSPI_FR_AAEF_SHIFT 15 +#define XSPI_FR_AITEF_MASK BIT(14) +#define XSPI_FR_AITEF_SHIFT 14 +#define XSPI_FR_AIBSEF_MASK BIT(13) +#define XSPI_FR_AIBSEF_SHIFT 13 +#define XSPI_FR_ABOF_MASK BIT(12) +#define XSPI_FR_ABOF_SHIFT 12 +#define XSPI_FR_CRCAEF_MASK BIT(10) +#define XSPI_FR_CRCAEF_SHIFT 10 +#define XSPI_FR_PPWF_MASK BIT(8) +#define XSPI_FR_PPWF_SHIFT 8 +#define XSPI_FR_IPIEF_MASK BIT(6) +#define XSPI_FR_IPIEF_SHIFT 6 +#define XSPI_FR_IPEDERR_MASK BIT(5) +#define XSPI_FR_IPEDERR_SHIFT 5 +#define XSPI_FR_PERFOVF_MASK BIT(2) +#define XSPI_FR_PERFOVF_SHIFT 2 +#define XSPI_FR_RDADDR_MASK BIT(1) +#define XSPI_FR_RDADDR_SHIFT 1 +#define XSPI_FR_TFF_MASK BIT(0) +#define XSPI_FR_TFF_SHIFT 0 + +#define XSPI_SFA1AD 0x180U + +#define XSPI_SFA1AD_TPAD_MASK GENMASK(31, 10) +#define XSPI_SFA1AD_TPAD_SHIFT 10 +#define XSPI_SFA1AD_TPAD(x) ((x) << 10) + +#define XSPI_SFA2AD 0x184U + +#define XSPI_DLPR 0x190U + +#define XSPI_DLPR_DLPV_MASK GENMASK(31, 0) +#define XSPI_DLPR_DLPV_SHIFT 0 +#define XSPI_DLPR_DLPV(x) ((x) << 0) + +#define XSPI_RBDR 0x200U + +#define XSPI_LUTKEY 0x300U + +#define XSPI_LCKCR 0x304U + +#define XSPI_LCKCR_UNLOCK_MASK BIT(1) +#define XSPI_LCKCR_UNLOCK_SHIFT 1 +#define XSPI_LCKCR_LOCK_MASK BIT(0) +#define XSPI_LCKCR_LOCK_SHIFT 0 + +#define XSPI_LUT 0x310 + +#define XSPI_BFGENCR 0x20 + +#define XSPI_BFGENCR_SEQID_WR_MASK GENMASK(31, 28) +#define XSPI_BFGENCR_SEQID_WR_SHIFT 28 +#define XSPI_BFGENCR_SEQID_WR(x) ((x) << 28) +#define XSPI_BFGENCR_ALIGN_MASK GENMASK(23, 22) +#define XSPI_BFGENCR_ALIGN_SHIFT 22 +#define XSPI_BFGENCR_ALIGN(x) ((x) << 22) +#define XSPI_BFGENCR_WR_FLUSH_EN_MASK BIT(21) +#define XSPI_BFGENCR_WR_FLUSH_EN_SHIFT 21 +#define XSPI_BFGENCR_PPWF_CLR_MASK BIT(20) +#define XSPI_BFGENCR_PPWF_CLR_SHIFT 20 +#define XSPI_BFGENCR_SEQID_WR_EN_MASK BIT(17) +#define XSPI_BFGENCR_SEQID_WR_EN_SHIFT 17 +#define XSPI_BFGENCR_SEQID_MASK GENMASK(15, 12) +#define XSPI_BFGENCR_SEQID_SHIFT 12 +#define XSPI_BFGENCR_SEQID(x) ((x) << 12) +#define XSPI_BFGENCR_AHBSSIZE_MASK GENMASK(10, 9) +#define XSPI_BFGENCR_AHBSSIZE_SHIFT 9 +#define XSPI_BFGENCR_AHBSSIZE(x) ((x) << 9) +#define XSPI_BFGENCR_SPLITEN_MASK BIT(8) +#define XSPI_BFGENCR_SPLITEN_SHIFT 8 +#define XSPI_BFGENCR_SEQID_RDSR_MASK GENMASK(3, 0) +#define XSPI_BFGENCR_SEQID_RDSR_SHIFT 0 +#define XSPI_BFGENCR_SEQID_RDSR(x) ((x) << 0) + +#define XSPI_FRAD0_WORD2 0x808U + +#define XSPI_FRAD0_WORD2_EALO_MASK GENMASK(29, 24) +#define XSPI_FRAD0_WORD2_EALO_SHIFT 24 +#define XSPI_FRAD0_WORD2_EALO(x) ((x) << 24) +#define XSPI_FRAD0_WORD2_MD4ACP_MASK GENMASK(14, 12) +#define XSPI_FRAD0_WORD2_MD4ACP_SHIFT 12 +#define XSPI_FRAD0_WORD2_MD4ACP(x) ((x) << 12) +#define XSPI_FRAD0_WORD2_MD3ACP_MASK GENMASK(11, 9) +#define XSPI_FRAD0_WORD2_MD3ACP_SHIFT 9 +#define XSPI_FRAD0_WORD2_MD3ACP(x) ((x) << 9) +#define XSPI_FRAD0_WORD2_MD2ACP_MASK GENMASK(8, 6) +#define XSPI_FRAD0_WORD2_MD2ACP_SHIFT 6 +#define XSPI_FRAD0_WORD2_MD2ACP(x) ((x) << 6) +#define XSPI_FRAD0_WORD2_MD1ACP_MASK GENMASK(5, 3) +#define XSPI_FRAD0_WORD2_MD1ACP_SHIFT 3 +#define XSPI_FRAD0_WORD2_MD1ACP(x) ((x) << 3) +#define XSPI_FRAD0_WORD2_MD0ACP_MASK GENMASK(2, 0) +#define XSPI_FRAD0_WORD2_MD0ACP_SHIFT 0 +#define XSPI_FRAD0_WORD2_MD0ACP(x) ((x) << 0) + +#define XSPI_FRAD1_WORD2 0x828U + +#define XSPI_FRAD2_WORD2 0x848U + +#define XSPI_FRAD3_WORD2 0x868U + +#define XSPI_FRAD4_WORD2 0x888U + +#define XSPI_FRAD5_WORD2 0x8A8U + +#define XSPI_FRAD6_WORD2 0x8C8U + +#define XSPI_FRAD7_WORD2 0x8E8U + +#define XSPI_FRAD8_WORD2 0x988U + +#define XSPI_FRAD9_WORD2 0x9A8U + +#define XSPI_FRAD10_WORD2 0x9C8U + +#define XSPI_FRAD11_WORD2 0x9E8U + +#define XSPI_FRAD12_WORD2 0xA08U + +#define XSPI_FRAD13_WORD2 0xA28U + +#define XSPI_FRAD14_WORD2 0xA48U + +#define XSPI_FRAD15_WORD2 0xA68U + +#define XSPI_FRAD0_WORD3 0x80CU + +#define XSPI_FRAD0_WORD3_VLD_MASK BIT(31) +#define XSPI_FRAD0_WORD3_VLD_SHIFT 31 +#define XSPI_FRAD0_WORD3_LOCK_MASK GENMASK(30, 29) +#define XSPI_FRAD0_WORD3_LOCK_SHIFT 29 +#define XSPI_FRAD0_WORD3_LOCK(x) ((x) << 29) +#define XSPI_FRAD0_WORD3_EAL_MASK GENMASK(25, 24) +#define XSPI_FRAD0_WORD3_EAL_SHIFT 24 +#define XSPI_FRAD0_WORD3_EAL(x) ((x) << 24) + +#define XSPI_FRAD1_WORD3 0x82CU + +#define XSPI_FRAD2_WORD3 0x84CU + +#define XSPI_FRAD3_WORD3 0x86CU + +#define XSPI_FRAD4_WORD3 0x88CU + +#define XSPI_FRAD5_WORD3 0x8ACU + +#define XSPI_FRAD6_WORD3 0x8CCU + +#define XSPI_FRAD7_WORD3 0x8ECU + +#define XSPI_FRAD8_WORD3 0x98CU + +#define XSPI_FRAD9_WORD3 0x9ACU + +#define XSPI_FRAD10_WORD3 0x9CCU + +#define XSPI_FRAD11_WORD3 0x9ECU + +#define XSPI_FRAD12_WORD3 0xA0CU + +#define XSPI_FRAD13_WORD3 0xA2CU + +#define XSPI_FRAD14_WORD3 0xA4CU + +#define XSPI_FRAD15_WORD3 0xA6CU + +#define XSPI_TG0MDAD 0x900U + +#define XSPI_TG0MDAD_VLD_MASK BIT(31) +#define XSPI_TG0MDAD_VLD_SHIFT 31 +#define XSPI_TG0MDAD_LCK_MASK BIT(29) +#define XSPI_TG0MDAD_LCK_SHIFT 29 +#define XSPI_TG0MDAD_SA_MASK GENMASK(15, 14) +#define XSPI_TG0MDAD_SA_SHIFT 14 +#define XSPI_TG0MDAD_SA(x) ((x) << 14) +#define XSPI_TG0MDAD_MASKTYPE_MASK BIT(12) +#define XSPI_TG0MDAD_MASKTYPE_SHIFT 12 +#define XSPI_TG0MDAD_MASK_MASK GENMASK(11, 6) +#define XSPI_TG0MDAD_MASK_SHIFT 6 +#define XSPI_TG0MDAD_MASK(x) ((x) << 6) +#define XSPI_TG0MDAD_MIDMATCH_MASK GENMASK(5, 0) +#define XSPI_TG0MDAD_MIDMATCH_SHIFT 0 +#define XSPI_TG0MDAD_MIDMATCH(x) ((x) << 0) + +#define XSPI_TG1MDAD 0x910U + +#define XSPI_MGC 0x920 + +#define XSPI_MGC_GVLD_MASK BIT(31) +#define XSPI_MGC_GVLD_SHIFT 31 +#define XSPI_MGC_GVLDMDAD_MASK BIT(29) +#define XSPI_MGC_GVLDMDAD_SHIFT 29 +#define XSPI_MGC_GVLDFRAD_MASK BIT(27) +#define XSPI_MGC_GVLDFRAD_SHIFT 27 +#define XSPI_MGC_TG1_FIX_PRIO_MASK BIT(16) +#define XSPI_MGC_TG1_FIX_PRIO_SHIFT 16 +#define XSPI_MGC_GCLCK_MASK GENMASK(11, 10) +#define XSPI_MGC_GCLCK_SHIFT 10 +#define XSPI_MGC_GCLCK(x) ((x) << 10) +#define XSPI_MGC_GCLCKMID_MASK GENMASK(5, 0) +#define XSPI_MGC_GCLCKMID_SHIFT 0 +#define XSPI_MGC_GCLCKMID(x) ((x) << 0) + +#define XSPI_MTO 0x928 + +#define XSPI_MTO_SFP_ACC_TO_MASK GENMASK(31, 0) +#define XSPI_MTO_SFP_ACC_TO_SHIFT 0 +#define XSPI_MTO_SFP_ACC_TO(x) ((x) << 0) + +#define XSPI_TG2MDAD_EXT 0x940U + +#define XSPI_TG2MDAD_EXT_VLD_MASK BIT(31) +#define XSPI_TG2MDAD_EXT_VLD_SHIFT 31 +#define XSPI_TG2MDAD_EXT_LCK_MASK BIT(29) +#define XSPI_TG2MDAD_EXT_LCK_SHIFT 29 +#define XSPI_TG2MDAD_EXT_SA_MASK GENMASK(15, 14) +#define XSPI_TG2MDAD_EXT_SA_SHIFT 14 +#define XSPI_TG2MDAD_EXT_SA(x) ((x) << 14) +#define XSPI_TG2MDAD_EXT_MASKTYPE_MASK BIT(12) +#define XSPI_TG2MDAD_EXT_MASKTYPE_SHIFT 12 +#define XSPI_TG2MDAD_EXT_MASK_MASK GENMASK(11, 6) +#define XSPI_TG2MDAD_EXT_MASK_SHIFT 6 +#define XSPI_TG2MDAD_EXT_MASK(x) ((x) << 6) +#define XSPI_TG2MDAD_EXT_MIDMATCH_MASK GENMASK(5, 0) +#define XSPI_TG2MDAD_EXT_MIDMATCH_SHIFT 0 +#define XSPI_TG2MDAD_EXT_MIDMATCH(x) ((x) << 0) + +#define XSPI_TG3MDAD_EXT 0x944U + +#define XSPI_TG4MDAD_EXT 0x948U + +#define XSPI_SFP_TG_IPCR 0x958U + +#define XSPI_SFP_TG_IPCR_SEQID_MASK GENMASK(27, 24) +#define XSPI_SFP_TG_IPCR_SEQID_SHIFT 24 +#define XSPI_SFP_TG_IPCR_SEQID(x) ((x) << 24) +#define XSPI_SFP_TG_IPCR_ARB_UNLOCK_MASK BIT(23) +#define XSPI_SFP_TG_IPCR_ARB_UNLOCK_SHIFT 23 +#define XSPI_SFP_TG_IPCR_ARB_LOCK_MASK BIT(22) +#define XSPI_SFP_TG_IPCR_ARB_LOCK_SHIFT 22 +#define XSPI_SFP_TG_IPCR_IDATSZ_MASK GENMASK(15, 0) +#define XSPI_SFP_TG_IPCR_IDATSZ_SHIFT 0 +#define XSPI_SFP_TG_IPCR_IDATSZ(x) ((x) << 0) + +#define XSPI_SFP_TG_SFAR 0x95CU + +/* XSPI Register defination end */ + +/* xspi data structure */ +struct nxp_xspi_devtype_data { + unsigned int rxfifo; + unsigned int rx_buf_size; + unsigned int txfifo; + unsigned int ahb_buf_size; + unsigned int quirks; +}; + +struct nxp_xspi { + struct udevice *dev; + u32 iobase; + u32 ahb_addr; + u32 a1_size; + u32 a2_size; + struct { + bool gmid; + u8 env; + } config; + struct clk clk; + struct nxp_xspi_devtype_data *devtype_data; + unsigned long support_max_rate; + int selected; + bool dtr; +}; + +/* xspi data structure end */ + +/********* XSPI CMD definitions ***************************/ +#define CMD_SDR 0x01U +#define CMD_DDR 0x11U +#define RADDR_SDR 0x02U +#define RADDR_DDR 0x0AU +#define CADDR_SDR 0x12U +#define CADDR_DDR 0x13U +#define MODE2_SDR 0x05U +#define MODE2_DDR 0x0CU +#define MODE4_SDR 0x06U +#define MODE4_DDR 0x0DU +#define MODE8_SDR 0x04U +#define MODE8_DDR 0x0BU +#define WRITE_SDR 0x08U +#define WRITE_DDR 0x0FU +#define READ_SDR 0x07U +#define READ_DDR 0x0EU +#define DATA_LEARN 0x10U +#define DUMMY_CYCLE 0x03U +#define JMP_ON_CS 0x09U +#define JMP_TO_SEQ 0x14U +#define CMD_STOP 0U + +/********* XSPI PAD definitions ************/ +#define XSPI_1PAD 0U +#define XSPI_2PAD 1U +#define XSPI_4PAD 2U +#define XSPI_8PAD 3U + +#define DEFAULT_XMIT_SIZE 0x40U + +#define ENV_ADDR_SIZE SZ_64K + +#define XSPI_LUT_KEY_VAL 0x5AF05AF0UL + +#define xspi_get_reg_field(x, env, reg_name, field_name) \ + ({ \ + u32 reg; \ + reg = xspi_readl_offset(x, env, reg_name); \ + reg &= XSPI_##reg_name##_##field_name##_MASK; \ + reg = reg >> XSPI_##reg_name##_##field_name##_SHIFT; \ + reg; \ + }) + +#define xspi_set_reg_field(x, env, val, reg_name, field_name) \ + do { \ + u32 reg; \ + reg = xspi_readl_offset(x, env, reg_name); \ + reg &= ~XSPI_##reg_name##_##field_name##_MASK; \ + reg |= (val << XSPI_##reg_name##_##field_name##_SHIFT); \ + xspi_writel_offset(x, env, reg, reg_name); \ + } while (0) + +#define xspi_writel_offset(x, env, val, offset) \ + do { \ + out_le32((void __iomem *)(uintptr_t)x->iobase + \ + (env * ENV_ADDR_SIZE) + XSPI_##offset, val); \ + } while (0) + +#define xspi_readl_offset(x, env, offset) ({ \ + u32 reg; \ + reg = in_le32((void __iomem *)(uintptr_t)x->iobase + \ + (env * ENV_ADDR_SIZE) + XSPI_##offset); \ + reg; \ +}) + +#define POLL_TOUT 5000 + +#define CMD_LUT_FOR_IP_CMD 1 +#define CMD_LUT_FOR_AHB_CMD 0 + +/* + * Calculate number of required PAD bits for LUT register. + * + * The pad stands for the number of IO lines [0:7]. + * For example, the octal read needs eight IO lines, + * so you should use LUT_PAD(8). This macro + * returns 3 i.e. use eight (2^3) IP lines for read. + */ +#define LUT_PAD(x) (fls(x) - 1) + +/* + * Macro for constructing the LUT entries with the following + * register layout: + * + * --------------------------------------------------- + * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | + * --------------------------------------------------- + */ +#define PAD_SHIFT 8 +#define INSTR_SHIFT 10 +#define OPRND_SHIFT 16 + +/* Macros for constructing the LUT register. */ +#define LUT_DEF(idx, ins, pad, opr) \ + ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ + (opr)) << (((idx) % 2) * OPRND_SHIFT)) + +#endif diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 35bd8766097..b2d115aded4 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -20,13 +20,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct omap2_mcspi_platform_config { unsigned int regs_offset; }; diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 50bd7be5640..e97352000f8 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -173,7 +173,8 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, soft_spi_scl(dev, !cidle); if ((txrx & SPI_MASTER_NO_TX) == 0) soft_spi_sda(dev, !!(tmpdout & 0x80)); - udelay(plat->spi_delay_us); + if (plat->spi_delay_us) + udelay(plat->spi_delay_us); /* * sample bit @@ -190,7 +191,8 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, &plat->mosi : &plat->miso); tmpdout <<= 1; - udelay(plat->spi_delay_us); + if (plat->spi_delay_us) + udelay(plat->spi_delay_us); /* * drive bit diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index e00532a371b..0bdc112d249 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -35,8 +34,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - /* sun4i spi registers */ #define SUN4I_RXDATA_REG 0x00 #define SUN4I_TXDATA_REG 0x04 diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index a3c0ad17121..66c97da610b 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -99,8 +99,6 @@ #define TXBIT 1 #define RXBIT 2 -DECLARE_GLOBAL_DATA_PTR; - struct synquacer_spi_plat { void __iomem *base; bool aces, rtm; diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 49b584c648d..6b7ad47c22d 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -12,14 +12,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define SPI_DEFAULT_SPEED_HZ 100000 static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) @@ -180,11 +177,76 @@ int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); + int mode = 0; + int value; + int ret; if (!dev_has_ofnode(dev)) return 0; - return spi_slave_of_to_plat(dev, plat); + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); + if (ret && ret != -EOVERFLOW && ret != -FDT_ERR_BADLAYOUT) { + dev_err(dev, "has no valid 'reg' property (%d)\n", ret); + return ret; + } + } + + plat->cs[0] = dev_read_u32_default(dev, "reg", -1); + + plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", + SPI_DEFAULT_SPEED_HZ); + if (dev_read_bool(dev, "spi-cpol")) + mode |= SPI_CPOL; + if (dev_read_bool(dev, "spi-cpha")) + mode |= SPI_CPHA; + if (dev_read_bool(dev, "spi-cs-high")) + mode |= SPI_CS_HIGH; + if (dev_read_bool(dev, "spi-3wire")) + mode |= SPI_3WIRE; + if (dev_read_bool(dev, "spi-half-duplex")) + mode |= SPI_PREAMBLE; + + /* Device DUAL/QUAD mode */ + value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_TX_DUAL; + break; + case 4: + mode |= SPI_TX_QUAD; + break; + case 8: + mode |= SPI_TX_OCTAL; + break; + default: + warn_non_xpl("spi-tx-bus-width %d not supported\n", value); + break; + } + + value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_RX_DUAL; + break; + case 4: + mode |= SPI_RX_QUAD; + break; + case 8: + mode |= SPI_RX_OCTAL; + break; + default: + warn_non_xpl("spi-rx-bus-width %d not supported\n", value); + break; + } + + plat->mode = mode; + + return 0; } #endif @@ -511,81 +573,6 @@ void spi_free_slave(struct spi_slave *slave) device_remove(slave->dev, DM_REMOVE_NORMAL); } -int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) -{ - int mode = 0; - int value; - -#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) - int ret; - - ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); - - if (ret == -EOVERFLOW || ret == -FDT_ERR_BADLAYOUT) { - dev_read_u32(dev, "reg", &plat->cs[0]); - } else { - dev_err(dev, "has no valid 'reg' property (%d)\n", ret); - return ret; - } -#else - plat->cs[0] = dev_read_u32_default(dev, "reg", -1); -#endif - - plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", - SPI_DEFAULT_SPEED_HZ); - if (dev_read_bool(dev, "spi-cpol")) - mode |= SPI_CPOL; - if (dev_read_bool(dev, "spi-cpha")) - mode |= SPI_CPHA; - if (dev_read_bool(dev, "spi-cs-high")) - mode |= SPI_CS_HIGH; - if (dev_read_bool(dev, "spi-3wire")) - mode |= SPI_3WIRE; - if (dev_read_bool(dev, "spi-half-duplex")) - mode |= SPI_PREAMBLE; - - /* Device DUAL/QUAD mode */ - value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_TX_DUAL; - break; - case 4: - mode |= SPI_TX_QUAD; - break; - case 8: - mode |= SPI_TX_OCTAL; - break; - default: - warn_non_xpl("spi-tx-bus-width %d not supported\n", value); - break; - } - - value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_RX_DUAL; - break; - case 4: - mode |= SPI_RX_QUAD; - break; - case 8: - mode |= SPI_RX_OCTAL; - break; - default: - warn_non_xpl("spi-rx-bus-width %d not supported\n", value); - break; - } - - plat->mode = mode; - - return 0; -} - UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index b969a7993d4..0f77fbc8d41 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include "tegra_spi.h" -DECLARE_GLOBAL_DATA_PTR; - /* COMMAND1 */ #define QSPI_CMD1_GO BIT(31) #define QSPI_CMD1_M_S BIT(30) diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index f3cd98c3db8..b89dd0b406b 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -10,13 +10,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* PMIC Arbiter configuration registers */ #define PMIC_ARB_VERSION 0x0000 #define PMIC_ARB_VERSION_V2_MIN 0x20010000 diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index 99104274f72..ff5873c940e 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -24,6 +24,7 @@ struct sysinfo_plat_priv { struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX]; u16 cache_handles[SYSINFO_CACHE_LVL_MAX]; u8 cache_level; + u16 marray_handles[SYSINFO_MEM_HANDLE_MAX]; }; static void smbios_cache_info_dump(struct smbios_type7 *cache_info) @@ -165,6 +166,10 @@ static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf, *buf = &priv->cache_handles[0]; *size = sizeof(priv->cache_handles); break; + case SYSID_SM_MEMARRAY_HANDLE: + *buf = &priv->marray_handles[0]; + *size = sizeof(priv->marray_handles); + break; default: return -EOPNOTSUPP; } diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 120e7510f15..16ef434a8d9 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -196,14 +196,14 @@ config SYSRESET_SBI config SYSRESET_SOCFPGA bool "Enable support for Intel SOCFPGA family" - depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) + depends on ARCH_SOCFPGA && (ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10) help This enables the system reset driver support for Intel SOCFPGA SoCs (Cyclone 5, Arria 5 and Arria 10). config SYSRESET_SOCFPGA_SOC64 bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA && ARCH_SOCFPGA_SOC64 help This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index c8389d507ee..1bde4d07f52 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define SITES_MAX 16 #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index a84a0dc0539..500a25638a9 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -11,7 +11,7 @@ config TIMER config SPL_TIMER bool "Enable driver model for timer drivers in SPL" - depends on TIMER && SPL + depends on TIMER && SPL && SPL_DM help Enable support for timer drivers in SPL. These can be used to get a timer value when in SPL, or perhaps for implementing a delay @@ -328,7 +328,7 @@ config XILINX_TIMER bool "Xilinx timer support" depends on TIMER select REGMAP - select SPL_REGMAP if SPL + select SPL_REGMAP if SPL_TIMER help Select this to enable support for the timer found on any Xilinx boards (axi timer). diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c index 314f956cdfb..3841d3c90d0 100644 --- a/drivers/timer/ostm_timer.c +++ b/drivers/timer/ostm_timer.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #define OSTM_CTL 0x20 #define OSTM_CTL_D BIT(1) -DECLARE_GLOBAL_DATA_PTR; - struct ostm_priv { fdt_addr_t regs; }; diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c index 3e57f4b98ba..05532e3330c 100644 --- a/drivers/timer/sp804_timer.c +++ b/drivers/timer/sp804_timer.c @@ -8,15 +8,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define SP804_TIMERX_LOAD 0x00 #define SP804_TIMERX_VALUE 0x04 #define SP804_TIMERX_CONTROL 0x08 diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 6c75bb2a079..49472933de3 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -76,6 +76,10 @@ config UFS_RENESAS_GEN5 config UFS_ROCKCHIP bool "Rockchip specific hooks to UFS controller platform driver" depends on UFS + depends on DM_GPIO + depends on RESET_ROCKCHIP + depends on SPL_DM_GPIO || !SPL_UFS_SUPPORT + depends on SPL_RESET_ROCKCHIP || !SPL_UFS_SUPPORT help This selects the Rockchip specific additions to UFSHCD platform driver. diff --git a/drivers/ufs/ufs-rockchip.c b/drivers/ufs/ufs-rockchip.c index 643a6ffb9bc..a13236c7f76 100644 --- a/drivers/ufs/ufs-rockchip.c +++ b/drivers/ufs/ufs-rockchip.c @@ -5,6 +5,7 @@ * Copyright (C) 2025 Rockchip Electronics Co.Ltd. */ +#include #include #include #include @@ -29,12 +30,9 @@ static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba, ufshcd_dme_reset(hba); ufshcd_dme_enable(hba); - if (hba->ops->phy_initialization) { - err = hba->ops->phy_initialization(hba); - if (err) - dev_err(hba->dev, - "Phy init failed (%d)\n", err); - } + err = ufshcd_ops_phy_initialization(hba); + if (err) + dev_err(hba->dev, "Phy init failed (%d)\n", err); return err; } @@ -152,11 +150,31 @@ static int ufs_rockchip_common_init(struct ufs_hba *hba) return err; } + err = gpio_request_by_name(dev, "reset-gpios", 0, &host->device_reset, + GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); + if (err) { + dev_err(dev, "Cannot get reset GPIO\n"); + return err; + } + host->hba = hba; return 0; } +static int ufs_rockchip_device_reset(struct ufs_hba *hba) +{ + struct ufs_rockchip_host *host = dev_get_priv(hba->dev); + + dm_gpio_set_value(&host->device_reset, true); + udelay(20); + + dm_gpio_set_value(&host->device_reset, false); + udelay(20); + + return 0; +} + static int ufs_rockchip_rk3576_init(struct ufs_hba *hba) { int ret = 0; @@ -174,6 +192,7 @@ static struct ufs_hba_ops ufs_hba_rk3576_vops = { .init = ufs_rockchip_rk3576_init, .phy_initialization = ufs_rockchip_rk3576_phy_init, .hce_enable_notify = ufs_rockchip_hce_enable_notify, + .device_reset = ufs_rockchip_device_reset, }; static const struct udevice_id ufs_rockchip_of_match[] = { diff --git a/drivers/ufs/ufs-rockchip.h b/drivers/ufs/ufs-rockchip.h index 3dcb80f5702..50c2539da78 100644 --- a/drivers/ufs/ufs-rockchip.h +++ b/drivers/ufs/ufs-rockchip.h @@ -72,6 +72,7 @@ struct ufs_rockchip_host { void __iomem *ufs_sys_ctrl; void __iomem *mphy_base; struct reset_ctl_bulk rsts; + struct gpio_desc device_reset; struct clk ref_out_clk; uint64_t caps; uint32_t phy_config_mode; diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index 7a80a9d5664..bb997aace8f 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -127,11 +127,6 @@ static void ufshcd_print_pwr_info(struct ufs_hba *hba) hba->pwr_info.hs_rate); } -static void ufshcd_device_reset(struct ufs_hba *hba) -{ - ufshcd_vops_device_reset(hba); -} - /** * ufshcd_ready_for_uic_cmd - Check if controller is ready * to accept UIC commands @@ -512,7 +507,9 @@ static int ufshcd_link_startup(struct ufs_hba *hba) int retries = DME_LINKSTARTUP_RETRIES; do { - ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); + ret = ufshcd_ops_link_startup_notify(hba, PRE_CHANGE); + if (ret) + goto out; ret = ufshcd_dme_link_startup(hba); @@ -598,12 +595,18 @@ static inline void ufshcd_hba_start(struct ufs_hba *hba) static int ufshcd_hba_enable(struct ufs_hba *hba) { int retry; + int ret; if (!ufshcd_is_hba_active(hba)) /* change controller state to "reset state" */ ufshcd_hba_stop(hba); - ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); + ret = ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE); + if (ret) { + dev_err(hba->dev, "Controller enable notify PRE_CHANGE failed: %i\n", + ret); + return ret; + } /* start controller initialization sequence */ ufshcd_hba_start(hba); @@ -635,7 +638,12 @@ static int ufshcd_hba_enable(struct ufs_hba *hba) /* enable UIC related interrupts */ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); - ufshcd_ops_hce_enable_notify(hba, POST_CHANGE); + ret = ufshcd_ops_hce_enable_notify(hba, POST_CHANGE); + if (ret) { + dev_err(hba->dev, "Controller enable notify POST_CHANGE failed: %i\n", + ret); + return ret; + } return 0; } @@ -2184,7 +2192,11 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) /* Set descriptor lengths to specification defaults */ ufshcd_def_desc_sizes(hba); - ufshcd_ops_init(hba); + err = ufshcd_ops_init(hba); + if (err) { + dev_err(hba->dev, "Host controller init failed: %i\n", err); + return err; + } /* Read capabilities registers */ hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); @@ -2228,7 +2240,11 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) mb(); /* flush previous writes */ /* Reset the attached device */ - ufshcd_device_reset(hba); + err = ufshcd_vops_device_reset(hba); + if (err) { + dev_err(hba->dev, "Failed to reset attached device: %i\n", err); + return err; + } err = ufshcd_hba_enable(hba); if (err) { diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index bc839a43704..0f6c93fbce7 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -509,7 +509,7 @@ struct ufs_query { }; /** - * struct ufs_dev_cmd - all assosiated fields with device management commands + * struct ufs_dev_cmd - all associated fields with device management commands * @type: device management command type - Query, NOP OUT * @tag_wq: wait queue until free command slot is available */ @@ -756,6 +756,14 @@ static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba, return 0; } +static inline int ufshcd_ops_phy_initialization(struct ufs_hba *hba) +{ + if (hba->ops && hba->ops->phy_initialization) + return hba->ops->phy_initialization(hba); + + return 0; +} + static inline int ufshcd_vops_device_reset(struct ufs_hba *hba) { if (hba->ops && hba->ops->device_reset) diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 13e9a61072a..22aa6525c96 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -7,14 +7,11 @@ */ #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static const char *const usb_dr_modes[] = { [USB_DR_MODE_UNKNOWN] = "", [USB_DR_MODE_HOST] = "host", diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index ebb306852a6..baa2eb61ea3 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -89,6 +89,7 @@ config USB_GADGET_PRODUCT_NUM default 0x350b if ROCKCHIP_RK3588 default 0x350c if ROCKCHIP_RK3528 default 0x350e if ROCKCHIP_RK3576 + default 0x350f if ROCKCHIP_RK3506 default 0x4ee0 if ARCH_SNAPDRAGON default 0x0 help diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 046bb335ecb..4729570c525 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -990,7 +990,7 @@ int dm_usb_gadget_handle_interrupts(struct udevice *dev) return value; } -void udc_disconnect(void) +static void udc_disconnect(void) { struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; /* disable pullup */ diff --git a/drivers/usb/isp1760/Kconfig b/drivers/usb/isp1760/Kconfig index 993d71e74cd..d1c5a687d9e 100644 --- a/drivers/usb/isp1760/Kconfig +++ b/drivers/usb/isp1760/Kconfig @@ -1,11 +1,13 @@ # SPDX-License-Identifier: GPL-2.0 config USB_ISP1760 - tristate "NXP ISP 1760/1761/1763 support" + bool "NXP ISP 1760/1761/1763 support" + depends on DM && OF_CONTROL select DM_USB + select REGMAP select USB_HOST help - Say Y or M here if your system as an ISP1760/1761/1763 USB host + Say Y here if your system as an ISP1760/1761/1763 USB host controller. This USB controller is usually attached to a non-DMA-Master diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c index bcd31adba52..cc6c3b94a65 100644 --- a/drivers/usb/musb-new/ti-musb.c +++ b/drivers/usb/musb-new/ti-musb.c @@ -83,17 +83,17 @@ static int ti_musb_of_to_plat(struct udevice *dev) struct ti_musb_plat *plat = dev_get_plat(dev); const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); - int phys; - int ctrl_mod; + ofnode phys_node; + ofnode ctrl_mod_node; int usb_index; int ret; struct musb_hdrc_config *musb_config; plat->base = devfdt_get_addr_index_ptr(dev, 1); - phys = fdtdec_lookup_phandle(fdt, node, "phys"); - ctrl_mod = fdtdec_lookup_phandle(fdt, phys, "ti,ctrl_mod"); - plat->ctrl_mod_base = (void *)fdtdec_get_addr(fdt, ctrl_mod, "reg"); + phys_node = ofnode_get_by_phandle(dev_read_u32_default(dev, "phys", 0)); + ctrl_mod_node = ofnode_get_by_phandle(ofnode_read_u32_default(phys_node, "ti,ctrl_mod", 0)); + plat->ctrl_mod_base = (void *)ofnode_get_addr(ctrl_mod_node); usb_index = ti_musb_get_usb_index(node); switch (usb_index) { case 1: @@ -183,6 +183,21 @@ static int ti_musb_host_remove(struct udevice *dev) } #if CONFIG_IS_ENABLED(OF_CONTROL) +static const struct udevice_id ti_musb_host_periph_ids[] = { + { .compatible = "ti,musb-am33xx" }, + { } +}; + +static int ti_musb_host_bind(struct udevice *dev) +{ + enum usb_dr_mode dr_mode = usb_get_dr_mode(dev_ofnode(dev)); + + if (dr_mode != USB_DR_MODE_HOST && dr_mode != USB_DR_MODE_OTG) + return -ENODEV; + + return 0; +} + static int ti_musb_host_of_to_plat(struct udevice *dev) { struct ti_musb_plat *plat = dev_get_plat(dev); @@ -206,6 +221,8 @@ U_BOOT_DRIVER(ti_musb_host) = { .name = "ti-musb-host", .id = UCLASS_USB, #if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = ti_musb_host_periph_ids, + .bind = ti_musb_host_bind, .of_to_plat = ti_musb_host_of_to_plat, #endif .probe = ti_musb_host_probe, @@ -221,6 +238,16 @@ struct ti_musb_peripheral { }; #if CONFIG_IS_ENABLED(OF_CONTROL) +static int ti_musb_peripheral_bind(struct udevice *dev) +{ + enum usb_dr_mode dr_mode = usb_get_dr_mode(dev_ofnode(dev)); + + if (dr_mode != USB_DR_MODE_PERIPHERAL) + return -ENODEV; + + return 0; +} + static int ti_musb_peripheral_of_to_plat(struct udevice *dev) { struct ti_musb_plat *plat = dev_get_plat(dev); @@ -283,6 +310,8 @@ U_BOOT_DRIVER(ti_musb_peripheral) = { .name = "ti-musb-peripheral", .id = UCLASS_USB_GADGET_GENERIC, #if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = ti_musb_host_periph_ids, + .bind = ti_musb_peripheral_bind, .of_to_plat = ti_musb_peripheral_of_to_plat, #endif .ops = &ti_musb_gadget_ops, diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c index ce9a7b5b819..bdbd0d44813 100644 --- a/drivers/usb/phy/rockchip_usb2_phy.c +++ b/drivers/usb/phy/rockchip_usb2_phy.c @@ -5,15 +5,12 @@ #include #include -#include #include #include #include #include "../gadget/dwc2_udc_otg_priv.h" -DECLARE_GLOBAL_DATA_PTR; - #define BIT_WRITEABLE_SHIFT 16 struct usb2phy_reg { diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c index 0aee57cb2f4..3061b466d7c 100644 --- a/drivers/usb/tcpm/tcpm.c +++ b/drivers/usb/tcpm/tcpm.c @@ -19,8 +19,6 @@ #include #include "tcpm-internal.h" -DECLARE_GLOBAL_DATA_PTR; - const char * const tcpm_states[] = { FOREACH_TCPM_STATE(GENERATE_TCPM_STRING) }; diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c index f0220e4cc07..b6980b1aec1 100644 --- a/drivers/video/hx8238d.c +++ b/drivers/video/hx8238d.c @@ -16,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Register Address */ #define HX8238D_OUTPUT_CTRL_ADDR 0x01 #define HX8238D_LCD_AC_CTRL_ADDR 0x02 diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index b35ba965efc..c25f209629e 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -15,6 +15,13 @@ config IMX_HDMI bool "Enable HDMI support in IPUv3" depends on VIDEO_IPUV3 +config IPU_CLK_LEGACY + bool "Use legacy clock management for IPU" + depends on VIDEO_IPUV3 && !CLK + default y + help + Use legacy clock management instead of Common Clock Framework. + config IMX_LDB bool "Freescale i.MX8MP LDB bridge" depends on VIDEO_BRIDGE diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile index 1edf5a6bdf0..0e7f71a9f93 100644 --- a/drivers/video/imx/Makefile +++ b/drivers/video/imx/Makefile @@ -4,5 +4,6 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_IPU_CLK_LEGACY) += ipu_clk_legacy.o obj-$(CONFIG_IMX_LDB) += ldb.o obj-$(CONFIG_IMX_LCDIF) += lcdif.o diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index 62827dc480d..ae40e20bc28 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -18,14 +18,23 @@ #ifndef __ASM_ARCH_IPU_H__ #define __ASM_ARCH_IPU_H__ +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) +#include +#endif #include #include +#define IPUV3_CLK_MX51 133000000 +#define IPUV3_CLK_MX53 200000000 +#define IPUV3_CLK_MX6Q 264000000 +#define IPUV3_CLK_MX6DL 198000000 + #define IDMA_CHAN_INVALID 0xFF #define HIGH_RESOLUTION_WIDTH 1024 struct ipu_ctx; -struct ipu_di_config; + +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) struct clk { const char *name; @@ -75,6 +84,46 @@ struct clk { int (*set_parent)(struct clk *clk, struct clk *parent); }; +/* Legacy clock API functions */ +void clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); +int clk_get_usecount(struct clk *clk); +u32 clk_get_rate(struct clk *clk); +struct clk *clk_get_parent(struct clk *clk); +int clk_set_rate(struct clk *clk, unsigned long rate); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); + +/* IPU clock initialization */ +int ipu_clk_init_legacy(struct ipu_ctx *ctx); +int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx); +int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id); + +#else + +static inline int clk_get_usecount(struct clk *clk) +{ + return clk->enable_count; +} + +/* Stub functions for non-legacy builds */ +static inline int ipu_clk_init_legacy(struct ipu_ctx *ctx) +{ + return -ENOSYS; +} + +static inline int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx) +{ + return -ENOSYS; +} + +static inline int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id) +{ + return -ENOSYS; +} + +#endif /* CONFIG_IS_ENABLED(IPU_CLK_LEGACY) */ + struct udevice; /* @@ -298,15 +347,6 @@ int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, u32 bytes_per_pixel(u32 fmt); -void clk_enable(struct clk *clk); -void clk_disable(struct clk *clk); -u32 clk_get_rate(struct clk *clk); -int clk_set_rate(struct clk *clk, unsigned long rate); -long clk_round_rate(struct clk *clk, unsigned long rate); -int clk_set_parent(struct clk *clk, struct clk *parent); -int clk_get_usecount(struct clk *clk); -struct clk *clk_get_parent(struct clk *clk); - void ipu_dump_registers(void); struct ipu_ctx *ipu_probe(struct udevice *dev); bool ipu_clk_enabled(struct ipu_ctx *ctx); diff --git a/drivers/video/imx/ipu_clk_legacy.c b/drivers/video/imx/ipu_clk_legacy.c new file mode 100644 index 00000000000..8aaafa2a080 --- /dev/null +++ b/drivers/video/imx/ipu_clk_legacy.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Legacy IPU clock management for i.MX5/6 without Common Clock Framework + * + * (C) Copyright 2026 + * Brian Ruley, GE HealthCare, brian.ruley@gehealthcare.com + */ + +#include "ipu.h" +#include "ipu_regs.h" +#include +#include +#include +#include +#include +#include +#include + +extern struct mxc_ccm_reg *mxc_ccm; + +void clk_enable(struct clk *clk) +{ + if (clk) { + if (clk->usecount++ == 0) + clk->enable(clk); + } +} + +void clk_disable(struct clk *clk) +{ + if (clk) { + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + } + } +} + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL) + return 0; + + return clk->usecount; +} + +u32 clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->parent; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (!clk) + return 0; + + if (clk->set_rate) + clk->set_rate(clk, rate); + + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + if (clk->set_parent) + return clk->set_parent(clk, parent); + return 0; +} + +static int clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + +#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) + reg = __raw_readl(&mxc_ccm->ccdr); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + reg = __raw_readl(&mxc_ccm->clpcr); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); +#endif + return 0; +} + +static void clk_ipu_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + +#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) + reg = __raw_readl(&mxc_ccm->ccdr); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + reg = __raw_readl(&mxc_ccm->clpcr); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); +#endif +} + +static void ipu_pixel_clk_recalc(struct clk *clk) +{ + u32 div; + u64 final_rate = (unsigned long long)clk->parent->rate * 16; + + div = __raw_readl(DI_BS_CLKGEN0(clk->id)); + debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n", div, + final_rate, clk->parent->rate); + + clk->rate = 0; + if (div != 0) { + do_div(final_rate, div); + clk->rate = final_rate; + } +} + +static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, + unsigned long rate) +{ + u64 div, final_rate; + u32 remainder; + u64 parent_rate = (unsigned long long)clk->parent->rate * 16; + + div = parent_rate; + remainder = do_div(div, rate); + if (remainder > (rate / 2)) + div++; + if (div < 0x10) + div = 0x10; + if (div & ~0xFEF) + div &= 0xFF8; + else { + if ((div & 0xC) == 0xC) { + div += 0x10; + div &= ~0xF; + } + } + final_rate = parent_rate; + do_div(final_rate, div); + + return final_rate; +} + +static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u64 div, parent_rate; + u32 remainder; + + parent_rate = (unsigned long long)clk->parent->rate * 16; + div = parent_rate; + remainder = do_div(div, rate); + if (remainder > (rate / 2)) + div++; + + if ((div & 0xC) == 0xC) { + div += 0x10; + div &= ~0xF; + } + if (div > 0x1000) + debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div); + + __raw_writel(div, DI_BS_CLKGEN0(clk->id)); + __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); + + do_div(parent_rate, div); + clk->rate = parent_rate; + + return 0; +} + +static int ipu_pixel_clk_enable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + + return 0; +} + +static void ipu_pixel_clk_disable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); +} + +static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); + struct ipu_ctx *ctx = clk->ctx; + + if (parent == ctx->ipu_clk) + di_gen &= ~DI_GEN_DI_CLK_EXT; + else if (!IS_ERR(ctx->di_clk[clk->id]) && parent == ctx->ldb_clk) + di_gen |= DI_GEN_DI_CLK_EXT; + else + return -EINVAL; + + __raw_writel(di_gen, DI_GENERAL(clk->id)); + ipu_pixel_clk_recalc(clk); + return 0; +} + +int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id) +{ + struct clk *pixel_clk; + + pixel_clk = devm_kzalloc(ctx->dev, sizeof(*pixel_clk), GFP_KERNEL); + if (!pixel_clk) + return -ENOMEM; + + pixel_clk->name = "pixel_clk"; + pixel_clk->id = id; + pixel_clk->ctx = ctx; + pixel_clk->recalc = ipu_pixel_clk_recalc; + pixel_clk->set_rate = ipu_pixel_clk_set_rate; + pixel_clk->round_rate = ipu_pixel_clk_round_rate; + pixel_clk->set_parent = ipu_pixel_clk_set_parent; + pixel_clk->enable = ipu_pixel_clk_enable; + pixel_clk->disable = ipu_pixel_clk_disable; + pixel_clk->usecount = 0; + + ctx->pixel_clk[id] = pixel_clk; + return 0; +} + +int ipu_clk_init_legacy(struct ipu_ctx *ctx) +{ + struct clk *ipu_clk; + + ipu_clk = devm_kzalloc(ctx->dev, sizeof(*ipu_clk), GFP_KERNEL); + if (!ipu_clk) + return -ENOMEM; + + ipu_clk->name = "ipu_clk"; + ipu_clk->ctx = ctx; +#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) + ipu_clk->enable_reg = + (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)); + ipu_clk->enable_shift = MXC_CCM_CCGR5_IPU_OFFSET; +#else + ipu_clk->enable_reg = + (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR3)); + ipu_clk->enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; +#endif + + ipu_clk->enable = clk_ipu_enable; + ipu_clk->disable = clk_ipu_disable; + ipu_clk->usecount = 0; + +#if CONFIG_IS_ENABLED(MX51) + ipu_clk->rate = IPUV3_CLK_MX51; +#elif CONFIG_IS_ENABLED(MX53) + ipu_clk->rate = IPUV3_CLK_MX53; +#else + ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q; +#endif + + ctx->ipu_clk = ipu_clk; + return 0; +} + +#if !defined CFG_SYS_LDB_CLOCK +#define CFG_SYS_LDB_CLOCK 65000000 +#endif + +int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx) +{ + struct clk *ldb_clk; + + ldb_clk = devm_kzalloc(ctx->dev, sizeof(*ldb_clk), GFP_KERNEL); + if (!ldb_clk) + return -ENOMEM; + + ldb_clk->name = "ldb_clk"; + ldb_clk->ctx = ctx; + ldb_clk->rate = CFG_SYS_LDB_CLOCK; + ldb_clk->usecount = 0; + + ctx->ldb_clk = ldb_clk; + return 0; +} diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index e9897ee79d2..8630374a055 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -31,8 +31,8 @@ #include #include -extern struct mxc_ccm_reg *mxc_ccm; -extern u32 *ipu_cpmem_base; +u32 *ipu_cpmem_base; +u32 *ipu_dc_tmpl_reg; struct ipu_ch_param_word { u32 data[5]; @@ -92,126 +92,6 @@ struct ipu_ch_param { #define IPU_SW_RST_TOUT_USEC (10000) -#define IPUV3_CLK_MX51 133000000 -#define IPUV3_CLK_MX53 200000000 -#define IPUV3_CLK_MX6Q 264000000 -#define IPUV3_CLK_MX6DL 198000000 - -void clk_enable(struct clk *clk) -{ - if (clk) { - if (clk->usecount++ == 0) - clk->enable(clk); - } -} - -void clk_disable(struct clk *clk) -{ - if (clk) { - if (!(--clk->usecount)) { - if (clk->disable) - clk->disable(clk); - } - } -} - -int clk_get_usecount(struct clk *clk) -{ - if (clk == NULL) - return 0; - - return clk->usecount; -} - -u32 clk_get_rate(struct clk *clk) -{ - if (!clk) - return 0; - - return clk->rate; -} - -struct clk *clk_get_parent(struct clk *clk) -{ - if (!clk) - return 0; - - return clk->parent; -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - if (!clk) - return 0; - - if (clk->set_rate) - clk->set_rate(clk, rate); - - return clk->rate; -} - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (clk == NULL || !clk->round_rate) - return 0; - - return clk->round_rate(clk, rate); -} - -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - clk->parent = parent; - if (clk->set_parent) - return clk->set_parent(clk, parent); - return 0; -} - -static int clk_ipu_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - -#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) - /* Handshake with IPU when certain clock rates are changed. */ - reg = __raw_readl(&mxc_ccm->ccdr); - reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; - __raw_writel(reg, &mxc_ccm->ccdr); - - /* Handshake with IPU when LPM is entered as its enabled. */ - reg = __raw_readl(&mxc_ccm->clpcr); - reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, &mxc_ccm->clpcr); -#endif - return 0; -} - -static void clk_ipu_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); - -#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) - /* - * No handshake with IPU whe dividers are changed - * as its not enabled. - */ - reg = __raw_readl(&mxc_ccm->ccdr); - reg |= MXC_CCM_CCDR_IPU_HS_MASK; - __raw_writel(reg, &mxc_ccm->ccdr); - - /* No handshake with IPU when LPM is entered as its not enabled. */ - reg = __raw_readl(&mxc_ccm->clpcr); - reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; - __raw_writel(reg, &mxc_ccm->clpcr); -#endif -} - /* * Function to initialize the ipu clock * @@ -221,43 +101,19 @@ static void clk_ipu_disable(struct clk *clk) */ static int ipu_clk_init(struct ipu_ctx *ctx) { - struct clk *ipu_clk; - - ipu_clk = devm_kzalloc(ctx->dev, sizeof(*ipu_clk), GFP_KERNEL); - if (!ipu_clk) - return -ENOMEM; - - ipu_clk->name = "ipu_clk"; - ipu_clk->ctx = ctx; -#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53) - ipu_clk->enable_reg = - (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)); - ipu_clk->enable_shift = MXC_CCM_CCGR5_IPU_OFFSET; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return ipu_clk_init_legacy(ctx); #else - ipu_clk->enable_reg = - (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR3)); - ipu_clk->enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; -#endif + struct clk *clk; - ipu_clk->enable = clk_ipu_enable; - ipu_clk->disable = clk_ipu_disable; - ipu_clk->usecount = 0; + clk = devm_clk_get(ctx->dev, "bus"); + if (IS_ERR(clk)) + return PTR_ERR(clk); -#if CONFIG_IS_ENABLED(MX51) - ipu_clk->rate = IPUV3_CLK_MX51; -#elif CONFIG_IS_ENABLED(MX53) - ipu_clk->rate = IPUV3_CLK_MX53; -#else - ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q; -#endif - - ctx->ipu_clk = ipu_clk; + ctx->ipu_clk = clk; return 0; -}; - -#if !defined CFG_SYS_LDB_CLOCK -#define CFG_SYS_LDB_CLOCK 65000000 #endif +} /* * Function to initialize the ldb dummy clock @@ -268,23 +124,14 @@ static int ipu_clk_init(struct ipu_ctx *ctx) */ static int ipu_ldb_clk_init(struct ipu_ctx *ctx) { - struct clk *ldb_clk; - - ldb_clk = devm_kzalloc(ctx->dev, sizeof(*ldb_clk), GFP_KERNEL); - if (!ldb_clk) - return -ENOMEM; - - ldb_clk->name = "ldb_clk"; - ldb_clk->ctx = ctx; - ldb_clk->rate = CFG_SYS_LDB_CLOCK; - ldb_clk->usecount = 0; - - ctx->ldb_clk = ldb_clk; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return ipu_ldb_clk_init_legacy(ctx); +#else + /* Set this in the FB driver where we know the display id */ + ctx->ldb_clk = NULL; return 0; -}; - -u32 *ipu_cpmem_base; -u32 *ipu_dc_tmpl_reg; +#endif +} /* Static functions */ @@ -320,124 +167,29 @@ static inline void ipu_ch_param_set_buffer(u32 ch, int buf_num, #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0) #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma)) -static void ipu_pixel_clk_recalc(struct clk *clk) +/* + * Function to initialize the display clocks + * + * @param ctx The ipu context for which the function is called + * + * Return: Returns 0 on success or negative error code on error + */ +static int ipu_di_clk_init(struct ipu_ctx *ctx, int id) { - u32 div; - u64 final_rate = (unsigned long long)clk->parent->rate * 16; - - div = __raw_readl(DI_BS_CLKGEN0(clk->id)); - debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n", div, - final_rate, clk->parent->rate); - - clk->rate = 0; - if (div != 0) { - do_div(final_rate, div); - clk->rate = final_rate; - } -} - -static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, - unsigned long rate) -{ - u64 div, final_rate; - u32 remainder; - u64 parent_rate = (unsigned long long)clk->parent->rate * 16; - - /* - * Calculate divider - * Fractional part is 4 bits, - * so simply multiply by 2^4 to get fractional part. - */ - div = parent_rate; - remainder = do_div(div, rate); - /* Round the divider value */ - if (remainder > (rate / 2)) - div++; - if (div < 0x10) /* Min DI disp clock divider is 1 */ - div = 0x10; - if (div & ~0xFEF) - div &= 0xFF8; - else { - /* Round up divider if it gets us closer to desired pix clk */ - if ((div & 0xC) == 0xC) { - div += 0x10; - div &= ~0xF; - } - } - final_rate = parent_rate; - do_div(final_rate, div); - - return final_rate; -} - -static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) -{ - u64 div, parent_rate; - u32 remainder; - - parent_rate = (unsigned long long)clk->parent->rate * 16; - div = parent_rate; - remainder = do_div(div, rate); - /* Round the divider value */ - if (remainder > (rate / 2)) - div++; - - /* Round up divider if it gets us closer to desired pix clk */ - if ((div & 0xC) == 0xC) { - div += 0x10; - div &= ~0xF; - } - if (div > 0x1000) - debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div); - - __raw_writel(div, DI_BS_CLKGEN0(clk->id)); - - /* - * Setup pixel clock timing - * Down time is half of period - */ - __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); - - do_div(parent_rate, div); - - clk->rate = parent_rate; - +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + ctx->di_clk[id] = NULL; return 0; -} +#else + struct clk *clk; -static int ipu_pixel_clk_enable(struct clk *clk) -{ - u32 disp_gen = __raw_readl(IPU_DISP_GEN); - disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; - __raw_writel(disp_gen, IPU_DISP_GEN); + clk = devm_clk_get(ctx->dev, id ? "di1" : "di0"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ctx->di_clk[id] = clk; return 0; +#endif } - -static void ipu_pixel_clk_disable(struct clk *clk) -{ - u32 disp_gen = __raw_readl(IPU_DISP_GEN); - disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; - __raw_writel(disp_gen, IPU_DISP_GEN); -} - -static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) -{ - u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); - struct ipu_ctx *ctx = clk->ctx; - - if (parent == ctx->ipu_clk) - di_gen &= ~DI_GEN_DI_CLK_EXT; - else if (!IS_ERR(ctx->di_clk[clk->id]) && parent == ctx->ldb_clk) - di_gen |= DI_GEN_DI_CLK_EXT; - else - return -EINVAL; - - __raw_writel(di_gen, DI_GENERAL(clk->id)); - ipu_pixel_clk_recalc(clk); - return 0; -} - /* * Function to initialize the pixel clock * @@ -447,26 +199,13 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) */ static int ipu_pixel_clk_init(struct ipu_ctx *ctx, int id) { - struct clk *pixel_clk; - - pixel_clk = devm_kzalloc(ctx->dev, sizeof(*pixel_clk), GFP_KERNEL); - if (!pixel_clk) - return -ENOMEM; - - pixel_clk->name = "pixel_clk"; - pixel_clk->id = id; - pixel_clk->ctx = ctx; - pixel_clk->recalc = ipu_pixel_clk_recalc; - pixel_clk->set_rate = ipu_pixel_clk_set_rate; - pixel_clk->round_rate = ipu_pixel_clk_round_rate; - pixel_clk->set_parent = ipu_pixel_clk_set_parent; - pixel_clk->enable = ipu_pixel_clk_enable; - pixel_clk->disable = ipu_pixel_clk_disable; - pixel_clk->usecount = 0; - - ctx->pixel_clk[id] = pixel_clk; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return ipu_pixel_clk_init_legacy(ctx, id); +#else + ctx->pixel_clk[id] = ctx->ipu_clk; return 0; -}; +#endif +} /* * This function resets IPU @@ -536,33 +275,39 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); - ret = ipu_pixel_clk_init(ctx, 0); - if (ret) - goto err; - - ret = ipu_pixel_clk_init(ctx, 1); - if (ret) - goto err; + for (int i = 0; i <= 1; i++) { + ret = ipu_pixel_clk_init(ctx, i); + if (ret) + goto err; + } ret = ipu_clk_init(ctx); if (ret) goto err; - debug("ipu_clk = %u\n", clk_get_rate(ctx->ipu_clk)); + debug("ipu_clk = %lu\n", (ulong)clk_get_rate(ctx->ipu_clk)); ret = ipu_ldb_clk_init(ctx); if (ret) goto err; - debug("ldb_clk = %u\n", clk_get_rate(ctx->ldb_clk)); + if (ctx->ldb_clk) + debug("ldb_clk = %lu\n", (ulong)clk_get_rate(ctx->ldb_clk)); + ipu_reset(); +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); - clk_enable(ctx->ipu_clk); - ctx->di_clk[0] = NULL; - ctx->di_clk[1] = NULL; + clk_enable(ctx->ipu_clk); +#endif + + for (int i = 0; i <= 1; i++) { + ret = ipu_di_clk_init(ctx, i); + if (ret) + goto err; + } __raw_writel(0x807FFFFF, IPU_MEM_RST); while (__raw_readl(IPU_MEM_RST) & 0x80000000) @@ -584,7 +329,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) /* Set MCU_T to divide MCU access window into 2 */ __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_disable(ctx->ipu_clk); +#endif return ctx; err: diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c index 6a337b13af6..5e78574da9b 100644 --- a/drivers/video/imx/ipu_disp.c +++ b/drivers/video/imx/ipu_disp.c @@ -612,6 +612,11 @@ void ipu_dp_dc_enable(struct ipu_ctx *ctx, ipu_channel_t channel) __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); clk_enable(ctx->pixel_clk[di]); +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + reg = __raw_readl(IPU_DISP_GEN); + reg |= di ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); +#endif } static unsigned char dc_swap; @@ -702,6 +707,12 @@ void ipu_dp_dc_disable(struct ipu_ctx *ctx, ipu_channel_t channel, /* Clock is already off because it must be done quickly, but we need to fix the ref count */ +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + reg = __raw_readl(IPU_DISP_GEN); + reg &= ctx->dc_di_assignment[dc_chan] ? ~DI1_COUNTER_RELEASE : + ~DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); +#endif clk_disable(ctx->pixel_clk[ctx->dc_di_assignment[dc_chan]]); } } @@ -765,40 +776,21 @@ static int ipu_pixfmt_to_map(u32 fmt) * * @param sig Bitfield of signal polarities for LCD interface. * - * Return: This function returns 0 on success or negative error code on - * fail. + * Return: The integer portion of the divider set for the pixel clock. */ - -int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) +static u32 ipu_di_clk_config(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) { struct ipu_ctx *ctx = di->ctx; int disp = di->disp; - u32 reg; - u32 di_gen, vsync_cnt; - u32 div, rounded_pixel_clk; - u32 h_total, v_total; - int map; - struct clk *di_parent; - - debug("panel size = %d x %d\n", di->width, di->height); - - if ((di->v_sync_width == 0) || (di->h_sync_width == 0)) - return -EINVAL; - - /* adapt panel to ipu restricitions */ - if (di->v_end_width < 2) { - di->v_end_width = 2; - puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n"); - } - - h_total = di->width + di->h_sync_width + di->h_start_width + - di->h_end_width; - v_total = di->height + di->v_sync_width + di->v_start_width + - di->v_end_width; + u32 div; /* Init clocking */ debug("pixel clk = %dHz\n", di->pixel_clk_rate); +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + u32 rounded_pixel_clk; + struct clk *di_parent; + if (sig.ext_clk) { if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ /* @@ -830,13 +822,109 @@ int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) if (clk_get_usecount(ctx->pixel_clk[disp]) != 0) clk_set_parent(ctx->pixel_clk[disp], ctx->ipu_clk); } + rounded_pixel_clk = clk_round_rate(ctx->pixel_clk[disp], di->pixel_clk_rate); clk_set_rate(ctx->pixel_clk[disp], rounded_pixel_clk); - udelay(5000); + /* Get integer portion of divider */ div = clk_get_rate(clk_get_parent(ctx->pixel_clk[disp])) / rounded_pixel_clk; +#else + struct clk *clk; + u32 clkgen0, di_gen; + ulong id; + + if (sig.ext_clk) { + /* + * Bypass the divider, assuming synchronous mode + */ + clk = ctx->di_clk[disp]; + div = 1; + } else { + + ulong clk_rate = clk_get_rate(ctx->ipu_clk); + u32 error; + + div = DIV_ROUND_CLOSEST(clk_rate, di->pixel_clk_rate); + div = clamp(div, 1U, 255U); + + error = (clk_rate / div) / (di->pixel_clk_rate / 1000); + + /* + * Select IPU if the rate is within 1% of requested pixel + * clock, otherwise, use the DI clock + */ + if (990 <= error && error < 1010) { + clk = ctx->ipu_clk; + } else { + clk = ctx->di_clk[disp]; + + clk_set_rate(clk, di->pixel_clk_rate); + div = DIV_ROUND_CLOSEST(clk_get_rate(clk), + di->pixel_clk_rate); + div = clamp(div, 1U, 255U); + } + } + + clkgen0 = div << 4; + + ctx->pixel_clk[disp] = clk; + debug("new pixel rate: %lu Hz\n", clk_get_rate(clk)); + + id = clk_get_id(clk); + __raw_writel(clkgen0, DI_BS_CLKGEN0(id)); + __raw_writel((clkgen0 & 0xFFF0) << 12, DI_BS_CLKGEN1(id)); + + di_gen = __raw_readl(DI_GENERAL(id)) & ~DI_GEN_DI_CLK_EXT; + if (clk == ctx->di_clk[disp]) + di_gen |= DI_GEN_DI_CLK_EXT; + + __raw_writel(di_gen, DI_GENERAL(id)); +#endif + + udelay(5000); + return div; +} + +/* + * This function is called to initialize a synchronous LCD panel. + * + * @param di Pointer to display data. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * Return: This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig) +{ + int disp = di->disp; + u32 reg; + u32 di_gen, vsync_cnt; + u32 div; + u32 h_total, v_total; + int map; + + debug("panel size = %d x %d\n", di->width, di->height); + + if ((di->v_sync_width == 0) || (di->h_sync_width == 0)) + return -EINVAL; + + /* adapt panel to ipu restricitions */ + if (di->v_end_width < 2) { + di->v_end_width = 2; + puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n"); + } + + h_total = di->width + di->h_sync_width + di->h_start_width + + di->h_end_width; + v_total = di->height + di->v_sync_width + di->v_start_width + + di->v_end_width; + + div = ipu_di_clk_config(di, sig); + if (div < 0) + return div; ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index ab416fdd33c..3a327b9e97d 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -21,7 +21,6 @@ #include "ipu_regs.h" #include "mxcfb.h" #include -#include #include #include #include @@ -36,8 +35,7 @@ #include #include #include - -DECLARE_GLOBAL_DATA_PTR; +#include static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); @@ -602,6 +600,22 @@ static int ipuv3_video_probe(struct udevice *dev) if (ret < 0) return ret; +#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + if (of_machine_is_compatible("fsl,imx6qp")) + ret = clk_get_by_id(gdisp ? IMX6QDL_CLK_LDB_DI1_PODF : + IMX6QDL_CLK_LDB_DI0_PODF, + &ctx->ldb_clk); + else + ret = clk_get_by_id(gdisp ? IMX6QDL_CLK_LDB_DI1 : + IMX6QDL_CLK_LDB_DI0, + &ctx->ldb_clk); + + if (ret < 0) + return ret; + + debug("ldb_clk = %lu\n", clk_get_rate(ctx->ldb_clk)); +#endif + ret = mxcfb_probe(dev, gpixfmt, gdisp, gmode); if (ret < 0) return ret; diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index ea3776258a0..e0416b70ec0 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -16,14 +16,11 @@ #include #include #include /* For struct video_uc_plat */ -#include #include #include #include #include "videomodes.h" -DECLARE_GLOBAL_DATA_PTR; - #if !defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL) static struct nx_display_dev *dp_dev; #endif diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c index ef6fab1e953..b643fd1db89 100644 --- a/drivers/video/renesas-r61307.c +++ b/drivers/video/renesas-r61307.c @@ -228,7 +228,7 @@ static int renesas_r61307_of_to_plat(struct udevice *dev) } priv->dig_cont_adj = dev_read_bool(dev, "renesas,contrast"); - priv->inversion = dev_read_bool(dev, "renesas,inversion"); + priv->inversion = dev_read_bool(dev, "renesas,column-inversion"); priv->gamma = dev_read_u32_default(dev, "renesas,gamma", 0); return 0; diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index c969dae30b6..97c8619a6d8 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /** * struct rk_lvds_priv - private rockchip lvds display driver info * diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 0a603083ba9..e7b5973ca58 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -10,7 +10,6 @@ #include #include #include -#include #include "rk_mipi.h" #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int rk_mipi_read_timing(struct udevice *dev, struct display_timing *timing) { diff --git a/drivers/video/samsung-ltl106hl02.c b/drivers/video/samsung-ltl106hl02.c index 1efc9fca610..97881a1524e 100644 --- a/drivers/video/samsung-ltl106hl02.c +++ b/drivers/video/samsung-ltl106hl02.c @@ -93,9 +93,9 @@ static int samsung_ltl106hl02_of_to_plat(struct udevice *dev) } ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, - "vdd-supply", &priv->vdd); + "power-supply", &priv->vdd); if (ret) - log_debug("%s: cannot get vdd-supply: error %d\n", + log_debug("%s: cannot get power-supply: error %d\n", __func__, ret); ret = gpio_request_by_name(dev, "reset-gpios", 0, diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c index 69dfa930273..48da350080a 100644 --- a/drivers/video/sandbox_sdl.c +++ b/drivers/video/sandbox_sdl.c @@ -7,15 +7,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { /* Default LCD size we support */ LCD_MAX_WIDTH = 1366, diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c index 790ff6e591c..c231fd0341e 100644 --- a/drivers/video/tidss/tidss_drv.c +++ b/drivers/video/tidss/tidss_drv.c @@ -42,8 +42,6 @@ #include "tidss_regs.h" #include "tidss_oldi.h" -DECLARE_GLOBAL_DATA_PTR; - /* Panel parameters */ enum { LCD_MAX_WIDTH = 1920, diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index a0efd3393f5..fba65bb3d5b 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -20,12 +20,9 @@ #include #include #include -#include #include "zynqmp_dpsub.h" -DECLARE_GLOBAL_DATA_PTR; - /* Maximum supported resolution */ #define WIDTH 1024 #define HEIGHT 768 diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index ac563991b90..c36e9e9b3a7 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -292,6 +292,9 @@ static int virtio_uclass_child_pre_probe(struct udevice *vdev) if (ret) goto err; + /* After a reset we always need to start the init sequence again */ + virtio_add_status(vdev, VIRTIO_CONFIG_S_ACKNOWLEDGE); + /* We have a driver! */ virtio_add_status(vdev, VIRTIO_CONFIG_S_DRIVER); diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c index 90a371a59cc..c6de62142bb 100644 --- a/drivers/virtio/virtio_rng.c +++ b/drivers/virtio/virtio_rng.c @@ -46,7 +46,7 @@ static int virtio_rng_read(struct udevice *dev, void *data, size_t len) ; if (rsize > sg.length) - return -EIO; + rsize = sg.length; memcpy(ptr, buf, rsize); len -= rsize; diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c index 4b51178e1b8..d7a6b8de492 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -7,14 +7,11 @@ #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct a37xx_wdt { void __iomem *sel_reg; void __iomem *reg; diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 72e13787448..2fb25126b8c 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, * use this to convert a watchdog diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index 6308d9632a8..08ef3d84e26 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -11,12 +11,9 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct mt762x_wdt { void __iomem *regs; }; diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 4d4ab4cbe90..3c7e043c08e 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -146,6 +146,7 @@ static const struct udevice_id mtk_wdt_ids[] = { { .compatible = "mediatek,mt6589-wdt"}, { .compatible = "mediatek,mt7986-wdt" }, { .compatible = "mediatek,mt8188-wdt" }, + { .compatible = "mediatek,mt8195-wdt" }, {} }; diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 4562b2a37e3..a2000b968c9 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -16,15 +16,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct orion_wdt_priv { void __iomem *reg; int wdt_counter_offset; diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 03585529bb6..807884c5bc7 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -5,7 +5,6 @@ * Copyright 2020 NXP */ -#include #include #include #include @@ -15,8 +14,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* SBSA Generic Watchdog register definitions */ /* refresh frame */ #define SBSA_GWDT_WRR 0x000 diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index b32590069d9..438833b2245 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) struct wdt_priv { diff --git a/dts/upstream/Bindings/.yamllint b/dts/upstream/Bindings/.yamllint index 53279950180..8f9dd18dfe0 100644 --- a/dts/upstream/Bindings/.yamllint +++ b/dts/upstream/Bindings/.yamllint @@ -30,7 +30,7 @@ rules: document-start: present: true empty-lines: - max: 3 + max: 1 max-end: 1 empty-values: forbid-in-block-mappings: true diff --git a/dts/upstream/Bindings/Makefile b/dts/upstream/Bindings/Makefile index 8390d6c0003..8d6f85f4455 100644 --- a/dts/upstream/Bindings/Makefile +++ b/dts/upstream/Bindings/Makefile @@ -32,7 +32,8 @@ find_cmd = $(find_all_cmd) | \ sed 's|^$(srctree)/||' | \ grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" | \ sed 's|^|$(srctree)/|' -CHK_DT_EXAMPLES := $(patsubst $(srctree)/%.yaml,%.example.dtb, $(shell $(find_cmd))) +CHK_DT_EXAMPLES := $(patsubst $(srctree)/%.yaml,%.example.dtb, \ + $(shell $(find_cmd) | xargs grep -l '^examples:')) quiet_cmd_yamllint = LINT $(src) cmd_yamllint = ($(find_cmd) | \ diff --git a/dts/upstream/Bindings/arm/altera.yaml b/dts/upstream/Bindings/arm/altera.yaml index 30c44a0e640..db61537b711 100644 --- a/dts/upstream/Bindings/arm/altera.yaml +++ b/dts/upstream/Bindings/arm/altera.yaml @@ -31,7 +31,9 @@ properties: - description: Mercury+ AA1 boards items: - enum: - - enclustra,mercury-pe1 + - enclustra,mercury-aa1-pe1 + - enclustra,mercury-aa1-pe3 + - enclustra,mercury-aa1-st1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 @@ -52,6 +54,26 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: Mercury SA1 boards + items: + - enum: + - enclustra,mercury-sa1-pe1 + - enclustra,mercury-sa1-pe3 + - enclustra,mercury-sa1-st1 + - const: enclustra,mercury-sa1 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + + - description: Mercury+ SA2 boards + items: + - enum: + - enclustra,mercury-sa2-pe1 + - enclustra,mercury-sa2-pe3 + - enclustra,mercury-sa2-st1 + - const: enclustra,mercury-sa2 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: diff --git a/dts/upstream/Bindings/arm/altera/socfpga-clk-manager.yaml b/dts/upstream/Bindings/arm/altera/socfpga-clk-manager.yaml index a758f4bb2bb..4683bd1293f 100644 --- a/dts/upstream/Bindings/arm/altera/socfpga-clk-manager.yaml +++ b/dts/upstream/Bindings/arm/altera/socfpga-clk-manager.yaml @@ -27,17 +27,17 @@ properties: additionalProperties: false properties: - "#address-cells": + '#address-cells': const: 1 - "#size-cells": + '#size-cells': const: 0 patternProperties: - "^osc[0-9]$": + '^osc[0-9]$': type: object - "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$": + '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$': type: object $ref: '#/$defs/clock-props' unevaluatedProperties: false @@ -58,14 +58,14 @@ properties: minItems: 1 maxItems: 5 - "#address-cells": + '#address-cells': const: 1 - "#size-cells": + '#size-cells': const: 0 patternProperties: - "^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$": + '^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$': type: object $ref: '#/$defs/clock-props' unevaluatedProperties: false @@ -86,11 +86,11 @@ properties: required: - compatible - clocks - - "#clock-cells" + - '#clock-cells' required: - compatible - - "#clock-cells" + - '#clock-cells' required: - compatible @@ -104,7 +104,7 @@ $defs: reg: maxItems: 1 - "#clock-cells": + '#clock-cells': const: 0 clk-gate: diff --git a/dts/upstream/Bindings/arm/amd,seattle.yaml b/dts/upstream/Bindings/arm/amd,seattle.yaml new file mode 100644 index 00000000000..7a3fc05b19e --- /dev/null +++ b/dts/upstream/Bindings/arm/amd,seattle.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,seattle.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Seattle SoC Platforms + +maintainers: + - Suravee Suthikulpanit + - Tom Lendacky + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - description: Boards with AMD Seattle SoC + items: + - const: amd,seattle-overdrive + - const: amd,seattle + +additionalProperties: true +... diff --git a/dts/upstream/Bindings/arm/amlogic.yaml b/dts/upstream/Bindings/arm/amlogic.yaml index 2a096e060ed..08d9963fe92 100644 --- a/dts/upstream/Bindings/arm/amlogic.yaml +++ b/dts/upstream/Bindings/arm/amlogic.yaml @@ -134,6 +134,7 @@ properties: - libretech,aml-s912-pc - minix,neo-u9h - nexbox,a1 + - oranth,tx9-pro - tronsmart,vega-s96 - ugoos,am3 - videostrong,gxm-kiii-pro diff --git a/dts/upstream/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/dts/upstream/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml index b4f6695a601..fa7c403c874 100644 --- a/dts/upstream/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +++ b/dts/upstream/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -34,6 +34,9 @@ properties: - amlogic,a4-ao-secure - amlogic,c3-ao-secure - amlogic,s4-ao-secure + - amlogic,s6-ao-secure + - amlogic,s7-ao-secure + - amlogic,s7d-ao-secure - amlogic,t7-ao-secure - const: amlogic,meson-gx-ao-secure - const: syscon diff --git a/dts/upstream/Bindings/arm/apm.yaml b/dts/upstream/Bindings/arm/apm.yaml new file mode 100644 index 00000000000..ea0d362cea3 --- /dev/null +++ b/dts/upstream/Bindings/arm/apm.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/apm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC Platforms + +maintainers: + - Khuong Dinh + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - description: Boards with X-Gene1 Soc + items: + - const: apm,mustang + - const: apm,xgene-storm + + - description: Boards with X-Gene2 SoC + items: + - const: apm,merlin + - const: apm,xgene-shadowcat + +additionalProperties: true +... diff --git a/dts/upstream/Bindings/arm/arm,integrator.yaml b/dts/upstream/Bindings/arm/arm,integrator.yaml index 1bdbd1b7ee3..8fe22185a33 100644 --- a/dts/upstream/Bindings/arm/arm,integrator.yaml +++ b/dts/upstream/Bindings/arm/arm,integrator.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Integrator Boards maintainers: - - Linus Walleij + - Linus Walleij description: |+ These were the first ARM platforms officially supported by ARM Ltd. diff --git a/dts/upstream/Bindings/arm/arm,realview.yaml b/dts/upstream/Bindings/arm/arm,realview.yaml index 3c5f1688dbd..0b3133ecdda 100644 --- a/dts/upstream/Bindings/arm/arm,realview.yaml +++ b/dts/upstream/Bindings/arm/arm,realview.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM RealView Boards maintainers: - - Linus Walleij + - Linus Walleij description: |+ The ARM RealView series of reference designs were built to explore the Arm11, diff --git a/dts/upstream/Bindings/arm/arm,scu.yaml b/dts/upstream/Bindings/arm/arm,scu.yaml index dae2aa27e64..f735b7fb8e1 100644 --- a/dts/upstream/Bindings/arm/arm,scu.yaml +++ b/dts/upstream/Bindings/arm/arm,scu.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Snoop Control Unit (SCU) maintainers: - - Linus Walleij + - Linus Walleij description: | As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided diff --git a/dts/upstream/Bindings/arm/arm,versatile-sysreg.yaml b/dts/upstream/Bindings/arm/arm,versatile-sysreg.yaml index 3b060c36b90..e72dc45c1af 100644 --- a/dts/upstream/Bindings/arm/arm,versatile-sysreg.yaml +++ b/dts/upstream/Bindings/arm/arm,versatile-sysreg.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Arm Versatile system registers maintainers: - - Linus Walleij + - Linus Walleij description: This is a system control registers block, providing multiple low level diff --git a/dts/upstream/Bindings/arm/arm,versatile.yaml b/dts/upstream/Bindings/arm/arm,versatile.yaml index 7a3caf6af20..c777e455d03 100644 --- a/dts/upstream/Bindings/arm/arm,versatile.yaml +++ b/dts/upstream/Bindings/arm/arm,versatile.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Versatile Boards maintainers: - - Linus Walleij + - Linus Walleij description: |+ The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards diff --git a/dts/upstream/Bindings/arm/arm,vexpress-juno.yaml b/dts/upstream/Bindings/arm/arm,vexpress-juno.yaml index 4cdca532054..6430218ba1c 100644 --- a/dts/upstream/Bindings/arm/arm,vexpress-juno.yaml +++ b/dts/upstream/Bindings/arm/arm,vexpress-juno.yaml @@ -8,7 +8,7 @@ title: ARM Versatile Express and Juno Boards maintainers: - Sudeep Holla - - Linus Walleij + - Linus Walleij description: |+ ARM's Versatile Express platform were built as reference designs for exploring diff --git a/dts/upstream/Bindings/arm/aspeed/aspeed.yaml b/dts/upstream/Bindings/arm/aspeed/aspeed.yaml index aedefca7cf4..9298c1a75dd 100644 --- a/dts/upstream/Bindings/arm/aspeed/aspeed.yaml +++ b/dts/upstream/Bindings/arm/aspeed/aspeed.yaml @@ -93,7 +93,10 @@ properties: - facebook,minerva-cmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc + - facebook,yosemite5-bmc + - ibm,balcones-bmc - ibm,blueridge-bmc + - ibm,bonnell-bmc - ibm,everest-bmc - ibm,fuji-bmc - ibm,rainier-bmc diff --git a/dts/upstream/Bindings/arm/bst.yaml b/dts/upstream/Bindings/arm/bst.yaml new file mode 100644 index 00000000000..a3a7f424fd5 --- /dev/null +++ b/dts/upstream/Bindings/arm/bst.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BST platforms + +description: + Black Sesame Technologies (BST) is a semiconductor company that produces + automotive-grade system-on-chips (SoCs) for intelligent driving, focusing + on computer vision and AI capabilities. The BST C1200 family includes SoCs + for ADAS (Advanced Driver Assistance Systems) and autonomous driving + applications. + +maintainers: + - Ge Gordon + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BST C1200 CDCU1.0 ADAS 4C2G board + items: + - const: bst,c1200-cdcu1.0-adas-4c2g + - const: bst,c1200 + +additionalProperties: true + +... diff --git a/dts/upstream/Bindings/arm/fsl.yaml b/dts/upstream/Bindings/arm/fsl.yaml index 00cdf490b06..336669e16d7 100644 --- a/dts/upstream/Bindings/arm/fsl.yaml +++ b/dts/upstream/Bindings/arm/fsl.yaml @@ -1105,12 +1105,14 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board - - gocontroll,moduline-display # GOcontroll Moduline Display controller + - prt,prt8ml # Protonic PRT8ML - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel + - skov,imx8mp-skov-revc-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate + - skov,imx8mp-skov-revc-jutouch-jt101tm023 # SKOV i.MX8MP climate control with 10" JuTouch panel - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel - ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board @@ -1161,6 +1163,14 @@ properties: - const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM - const: fsl,imx8mp + - description: Ka-Ro TX8P-ML81 SoM based boards + items: + - enum: + - gocontroll,moduline-display + - gocontroll,moduline-display-106 + - const: karo,tx8p-ml81 + - const: fsl,imx8mp + - description: Kontron i.MX8MP OSM-S SoM based Boards items: - const: kontron,imx8mp-bl-osm-s # Kontron BL i.MX8MP OSM-S Board @@ -1430,6 +1440,7 @@ properties: - enum: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 - description: PHYTEC i.MX 95 FPSC based Boards @@ -1439,6 +1450,12 @@ properties: - const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC - const: fsl,imx95 + - description: Toradex Boards with SMARC iMX95 Modules + items: + - const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board + - const: toradex,smarc-imx95 # Toradex SMARC iMX95 Module + - const: fsl,imx95 + - description: i.MXRT1050 based Boards items: - enum: @@ -1492,6 +1509,13 @@ properties: - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM - const: fsl,imx93 + - description: PHYTEC phyCORE-i.MX91 SoM based boards + items: + - enum: + - phytec,imx91-phyboard-segin # phyBOARD-Segin with i.MX91 + - const: phytec,imx91-phycore-som # phyCORE-i.MX91 SoM + - const: fsl,imx91 + - description: PHYTEC phyCORE-i.MX93 SoM based boards items: - enum: diff --git a/dts/upstream/Bindings/arm/gemini.yaml b/dts/upstream/Bindings/arm/gemini.yaml index f6a0b675830..fc092962ab5 100644 --- a/dts/upstream/Bindings/arm/gemini.yaml +++ b/dts/upstream/Bindings/arm/gemini.yaml @@ -20,7 +20,7 @@ description: | Many of the IP blocks used in the SoC comes from Faraday Technology. maintainers: - - Linus Walleij + - Linus Walleij properties: $nodename: diff --git a/dts/upstream/Bindings/arm/intel,socfpga.yaml b/dts/upstream/Bindings/arm/intel,socfpga.yaml index c75cd7d29f1..c918837bd41 100644 --- a/dts/upstream/Bindings/arm/intel,socfpga.yaml +++ b/dts/upstream/Bindings/arm/intel,socfpga.yaml @@ -21,10 +21,17 @@ properties: - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 + - const: intel,socfpga-agilex5 - description: Agilex5 boards items: - enum: - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-013b - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 diff --git a/dts/upstream/Bindings/arm/intel-ixp4xx.yaml b/dts/upstream/Bindings/arm/intel-ixp4xx.yaml index b7b43089659..0f1bf634a98 100644 --- a/dts/upstream/Bindings/arm/intel-ixp4xx.yaml +++ b/dts/upstream/Bindings/arm/intel-ixp4xx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx maintainers: - - Linus Walleij + - Linus Walleij properties: $nodename: diff --git a/dts/upstream/Bindings/arm/lge.yaml b/dts/upstream/Bindings/arm/lge.yaml new file mode 100644 index 00000000000..d983ef7fcbd --- /dev/null +++ b/dts/upstream/Bindings/arm/lge.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/lge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LG Electronics SoC Platforms + +maintainers: + - Chanho Min + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - description: Boards with LG1312 Soc + items: + - const: lge,lg1312-ref + - const: lge,lg1312 + + - description: Boards with LG1313 SoC + items: + - const: lge,lg1313-ref + - const: lge,lg1313 + +additionalProperties: true +... diff --git a/dts/upstream/Bindings/arm/marvell/ap80x-system-controller.txt b/dts/upstream/Bindings/arm/marvell/ap80x-system-controller.txt deleted file mode 100644 index 72de11bd2ef..00000000000 --- a/dts/upstream/Bindings/arm/marvell/ap80x-system-controller.txt +++ /dev/null @@ -1,146 +0,0 @@ -Marvell Armada AP80x System Controller -====================================== - -The AP806/AP807 is one of the two core HW blocks of the Marvell Armada -7K/8K/931x SoCs. It contains system controllers, which provide several -registers giving access to numerous features: clocks, pin-muxing and -many other SoC configuration items. This DT binding allows to describe -these system controllers. - -For the top level node: - - compatible: must be: "syscon", "simple-mfd"; - - reg: register area of the AP80x system controller - -SYSTEM CONTROLLER 0 -=================== - -Clocks: -------- - - -The Device Tree node representing the AP806/AP807 system controller -provides a number of clocks: - - - 0: reference clock of CPU cluster 0 - - 1: reference clock of CPU cluster 1 - - 2: fixed PLL at 1200 Mhz - - 3: MSS clock, derived from the fixed PLL - -Required properties: - - - compatible: must be one of: - * "marvell,ap806-clock" - * "marvell,ap807-clock" - - #clock-cells: must be set to 1 - -Pinctrl: --------- - -For common binding part and usage, refer to -Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. - -Required properties: -- compatible must be "marvell,ap806-pinctrl", - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, sdio(clk), spi0(clk) -mpp1 1 gpio, sdio(cmd), spi0(miso) -mpp2 2 gpio, sdio(d0), spi0(mosi) -mpp3 3 gpio, sdio(d1), spi0(cs0n) -mpp4 4 gpio, sdio(d2), i2c0(sda) -mpp5 5 gpio, sdio(d3), i2c0(sdk) -mpp6 6 gpio, sdio(ds) -mpp7 7 gpio, sdio(d4), uart1(rxd) -mpp8 8 gpio, sdio(d5), uart1(txd) -mpp9 9 gpio, sdio(d6), spi0(cs1n) -mpp10 10 gpio, sdio(d7) -mpp11 11 gpio, uart0(txd) -mpp12 12 gpio, sdio(pw_off), sdio(hw_rst) -mpp13 13 gpio -mpp14 14 gpio -mpp15 15 gpio -mpp16 16 gpio -mpp17 17 gpio -mpp18 18 gpio -mpp19 19 gpio, uart0(rxd), sdio(pw_off) - -GPIO: ------ -For common binding part and usage, refer to -Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml. - -Required properties: - -- compatible: "marvell,armada-8k-gpio" - -- offset: offset address inside the syscon block - -Optional properties: - -- marvell,pwm-offset: offset address of PWM duration control registers inside - the syscon block - -Example: -ap_syscon: system-controller@6f4000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f4000 0x1000>; - - ap_clk: clock { - compatible = "marvell,ap806-clock"; - #clock-cells = <1>; - }; - - ap_pinctrl: pinctrl { - compatible = "marvell,ap806-pinctrl"; - }; - - ap_gpio: gpio { - compatible = "marvell,armada-8k-gpio"; - offset = <0x1040>; - ngpios = <19>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ap_pinctrl 0 0 19>; - marvell,pwm-offset = <0x10c0>; - #pwm-cells = <2>; - clocks = <&ap_clk 3>; - }; -}; - -SYSTEM CONTROLLER 1 -=================== - -Cluster clocks: ---------------- - -Device Tree Clock bindings for cluster clock of Marvell -AP806/AP807. Each cluster contain up to 2 CPUs running at the same -frequency. - -Required properties: - - compatible: must be one of: - * "marvell,ap806-cpu-clock" - * "marvell,ap807-cpu-clock" -- #clock-cells : should be set to 1. - -- clocks : shall be the input parent clock(s) phandle for the clock - (one per cluster) - -- reg: register range associated with the cluster clocks - -ap_syscon1: system-controller@6f8000 { - compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - cpu_clk: clock-cpu@278 { - compatible = "marvell,ap806-cpu-clock"; - clocks = <&ap_clk 0>, <&ap_clk 1>; - #clock-cells = <1>; - reg = <0x278 0xa30>; - }; -}; diff --git a/dts/upstream/Bindings/arm/marvell/cp110-system-controller.txt b/dts/upstream/Bindings/arm/marvell/cp110-system-controller.txt deleted file mode 100644 index 54ff9f21832..00000000000 --- a/dts/upstream/Bindings/arm/marvell/cp110-system-controller.txt +++ /dev/null @@ -1,191 +0,0 @@ -Marvell Armada CP110 System Controller -====================================== - -The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K -SoCs. It contains system controllers, which provide several registers -giving access to numerous features: clocks, pin-muxing and many other -SoC configuration items. This DT binding allows to describe these -system controllers. - -For the top level node: - - compatible: must be: "syscon", "simple-mfd"; - - reg: register area of the CP110 system controller - -SYSTEM CONTROLLER 0 -=================== - -Clocks: -------- - -The Device Tree node representing this System Controller 0 provides a -number of clocks: - - - a set of core clocks - - a set of gateable clocks - -Those clocks can be referenced by other Device Tree nodes using two -cells: - - The first cell must be 0 or 1. 0 for the core clocks and 1 for the - gateable clocks. - - The second cell identifies the particular core clock or gateable - clocks. - -The following clocks are available: - - Core clocks - - 0 0 APLL - - 0 1 PPv2 core - - 0 2 EIP - - 0 3 Core - - 0 4 NAND core - - 0 5 SDIO core - - Gateable clocks - - 1 0 Audio - - 1 1 Comm Unit - - 1 2 NAND - - 1 3 PPv2 - - 1 4 SDIO - - 1 5 MG Domain - - 1 6 MG Core - - 1 7 XOR1 - - 1 8 XOR0 - - 1 9 GOP DP - - 1 11 PCIe x1 0 - - 1 12 PCIe x1 1 - - 1 13 PCIe x4 - - 1 14 PCIe / XOR - - 1 15 SATA - - 1 16 SATA USB - - 1 17 Main - - 1 18 SD/MMC/GOP - - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) - - 1 22 USB3H0 - - 1 23 USB3H1 - - 1 24 USB3 Device - - 1 25 EIP150 - - 1 26 EIP197 - -Required properties: - - - compatible: must be: - "marvell,cp110-clock" - - #clock-cells: must be set to 2 - -Pinctrl: --------- - -For common binding part and usage, refer to the file -Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. - -Required properties: - -- compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl", - "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl" - depending on the specific variant of the SoC being used. - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -name pins functions -================================================================================ -mpp0 0 gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio) -mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc) -mpp2 2 gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc) -mpp3 3 gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), xg(mdio) -mpp4 4 gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc) -mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio) -mpp6 6 gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse) -mpp7 7 gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk) -mpp8 8 gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk) -mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk) -mpp10 10 gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act) -mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sata0(present_act) -mpp12 12 gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk) -mpp13 13 gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso) -mpp14 14 gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn) -mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp) -mpp16 16 gpio, dev(ad6), spi1(clk), mss_spi(clk) -mpp17 17 gpio, dev(ad5), ge0(txd3) -mpp18 18 gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp) -mpp19 19 gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp) -mpp20 20 gpio, dev(ad2), ge0(txd0) -mpp21 21 gpio, dev(ad1), ge0(txctl), sei(in_cp2cp) -mpp22 22 gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp) -mpp23 23 gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp) -mpp24 24 gpio, dev(a0), au(i2slrclk) -mpp25 25 gpio, dev(oen), au(i2sdo_spdifo) -mpp26 26 gpio, dev(wen0), au(i2sbclk) -mpp27 27 gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp) -mpp28 28 gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data) -mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb) -mpp30 30 gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), led(clk) -mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc) -mpp32 32 gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0 -mpp33 33 gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1 -mpp34 34 gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), mss_gpio2 -mpp35 35 gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_detect), xg(mdio), ge(mdio), pcie(rstoutn), mss_gpio3 -mpp36 36 gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5 -mpp37 37 gpio, uart2(rxd), i2c0(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq), mss_gpio6, link(rd_out_cp2cp) -mpp38 38 gpio, uart2(txd), i2c0(sda), ptp(pulse), tdm(rstn), mss_i2c(sda), sata0(present_act), ge(mdio), xg(mdio), au(i2sextclk), mss_gpio7, ptp(pulse_cp2cp) -mpp39 39 gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0 -mpp40 40 gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), uart1(txd), ge(mdio), sata0(present_act), mss_gpio1 -mpp41 41 gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act), mss_gpio2, rei(out_cp2cp) -mpp42 42 gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act), mss_gpio4 -mpp43 43 gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts), xg(mdio), sata1(present_act), mss_gpio5, wakeup(out_cp2cp) -mpp44 44 gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp) -mpp45 45 gpio, ge1(txd3), uart0(txd), pcie(rstoutn) -mpp46 46 gpio, ge1(txd1), uart1(rts) -mpp47 47 gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc) -mpp48 48 gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp) -mpp49 49 gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_en), sei(out_cp2cp) -mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(mdio), sdio(pwr11) -mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10) -mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq) -mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led) -mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect) -mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect) -mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk) -mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd) -mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0) -mpp59 59 gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), uart1(txd), sdio(d1) -mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uart1(rxd), sdio(d2) -mpp61 61 gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3) -mpp62 62 gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc) - -GPIO: ------ - -For common binding part and usage, refer to -Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml. - -Required properties: - -- compatible: "marvell,armada-8k-gpio" - -- offset: offset address inside the syscon block - -Example: - -CP110_LABEL(syscon0): system-controller@440000 { - compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; - - CP110_LABEL(clk): clock { - compatible = "marvell,cp110-clock"; - #clock-cells = <2>; - }; - - CP110_LABEL(pinctrl): pinctrl { - compatible = "marvell,armada-8k-cpm-pinctrl"; - }; - - CP110_LABEL(gpio1): gpio@100 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x100>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; - }; - -}; diff --git a/dts/upstream/Bindings/arm/mediatek.yaml b/dts/upstream/Bindings/arm/mediatek.yaml index f0427787369..718d732174b 100644 --- a/dts/upstream/Bindings/arm/mediatek.yaml +++ b/dts/upstream/Bindings/arm/mediatek.yaml @@ -38,6 +38,7 @@ properties: - const: mediatek,mt6580 - items: - enum: + - alcatel,yarisxl - prestigio,pmt5008-3g - const: mediatek,mt6582 - items: @@ -113,6 +114,12 @@ properties: - const: bananapi,bpi-r4-2g5 - const: bananapi,bpi-r4 - const: mediatek,mt7988a + - items: + - enum: + - bananapi,bpi-r4-pro-4e + - bananapi,bpi-r4-pro-8x + - const: bananapi,bpi-r4-pro + - const: mediatek,mt7988a - items: - enum: - mediatek,mt8127-moose @@ -445,6 +452,7 @@ properties: - enum: - kontron,3-5-sbc-i1200 - mediatek,mt8395-evk + - mediatek,mt8395-evk-ufs - radxa,nio-12l - const: mediatek,mt8395 - const: mediatek,mt8195 diff --git a/dts/upstream/Bindings/arm/psci.yaml b/dts/upstream/Bindings/arm/psci.yaml index 7360a2849b5..6e2e0c55184 100644 --- a/dts/upstream/Bindings/arm/psci.yaml +++ b/dts/upstream/Bindings/arm/psci.yaml @@ -163,7 +163,6 @@ examples: method = "smc"; }; - - |+ // Case 3: PSCI v0.2 and PSCI v0.1. diff --git a/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml b/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml index 4edc4748385..c349306f0d5 100644 --- a/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml +++ b/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml @@ -36,9 +36,12 @@ properties: $nodename: pattern: "^tpdm(@[0-9a-f]+)$" compatible: - items: - - const: qcom,coresight-tpdm - - const: arm,primecell + oneOf: + - items: + - const: qcom,coresight-static-tpdm + - items: + - const: qcom,coresight-tpdm + - const: arm,primecell reg: maxItems: 1 @@ -147,4 +150,18 @@ examples: }; }; }; + + turing-llm-tpdm { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + turing_llm_tpdm_out: endpoint { + remote-endpoint = <&turing0_funnel_in1>; + }; + }; + }; + }; ... diff --git a/dts/upstream/Bindings/arm/qcom.yaml b/dts/upstream/Bindings/arm/qcom.yaml index 18b5ed044f9..d84bd3bca20 100644 --- a/dts/upstream/Bindings/arm/qcom.yaml +++ b/dts/upstream/Bindings/arm/qcom.yaml @@ -88,6 +88,7 @@ properties: - items: - enum: + - asus,z00t - huawei,kiwi - longcheer,l9100 - samsung,a7 @@ -191,6 +192,11 @@ properties: - xiaomi,riva - const: qcom,msm8917 + - items: + - enum: + - xiaomi,land + - const: qcom,msm8937 + - items: - enum: - flipkart,rimob @@ -340,6 +346,7 @@ properties: - particle,tachyon - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - radxa,dragon-q6a - shift,otter - const: qcom,qcm6490 @@ -893,6 +900,7 @@ properties: - items: - enum: + - huawei,planck - lenovo,yoga-c630 - lg,judyln - lg,judyp @@ -1083,7 +1091,13 @@ properties: - items: - enum: - - asus,zenbook-a14-ux3407qa + - asus,zenbook-a14-ux3407qa-lcd + - asus,zenbook-a14-ux3407qa-oled + - const: asus,zenbook-a14-ux3407qa + - const: qcom,x1p42100 + + - items: + - enum: - hp,omnibook-x14-fe1 - lenovo,thinkbook-16 - qcom,x1p42100-crd @@ -1167,6 +1181,7 @@ allOf: - qcom,apq8094 - qcom,apq8096 - qcom,msm8917 + - qcom,msm8937 - qcom,msm8939 - qcom,msm8953 - qcom,msm8956 diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml index 6aceaa8acbb..d496421dbd8 100644 --- a/dts/upstream/Bindings/arm/rockchip.yaml +++ b/dts/upstream/Bindings/arm/rockchip.yaml @@ -15,6 +15,11 @@ properties: compatible: oneOf: + - description: 100ASK DshanPi A1 board + items: + - const: 100ask,dshanpi-a1 + - const: rockchip,rk3576 + - description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition) items: - const: vamrs,ficus @@ -25,6 +30,12 @@ properties: - const: vamrs,rock960 - const: rockchip,rk3399 + - description: 9Tripod X3568 series board + items: + - enum: + - 9tripod,x3568-v4 + - const: rockchip,rk3568 + - description: Amarula Vyasa RK3288 items: - const: amarula,vyasa-rk3288 @@ -78,13 +89,17 @@ properties: - description: Asus Tinker board items: - - const: asus,rk3288-tinker + - enum: + - asus,rk3288-tinker + - asus,rk3288-tinker-s - const: rockchip,rk3288 - - description: Asus Tinker board S + - description: Asus Tinker Board 3/3S items: - - const: asus,rk3288-tinker-s - - const: rockchip,rk3288 + - enum: + - asus,rk3566-tinker-board-3 + - asus,rk3566-tinker-board-3s + - const: rockchip,rk3566 - description: Beelink A1 items: @@ -330,6 +345,11 @@ properties: - friendlyarm,nanopi-r6s - const: rockchip,rk3588s + - description: FriendlyElec NanoPi R76S + items: + - const: friendlyarm,nanopi-r76s + - const: rockchip,rk3576 + - description: FriendlyElec NanoPi Zero2 items: - const: friendlyarm,nanopi-zero2 @@ -748,6 +768,11 @@ properties: - const: lckfb,tspi-rk3566 - const: rockchip,rk3566 + - description: LinkEase EasePi R1 + items: + - const: linkease,easepi-r1 + - const: rockchip,rk3568 + - description: Luckfox Core3576 Module based boards items: - enum: @@ -868,9 +893,11 @@ properties: - const: prt,mecsbc - const: rockchip,rk3568 - - description: QNAP TS-433-4G 4-Bay NAS + - description: QNAP TS-x33 NAS devices items: - - const: qnap,ts433 + - enum: + - qnap,ts233 + - qnap,ts433 - const: rockchip,rk3568 - description: Radxa Compute Module 3 (CM3) diff --git a/dts/upstream/Bindings/arm/tegra.yaml b/dts/upstream/Bindings/arm/tegra.yaml index 6139407c2cb..50a31dba7be 100644 --- a/dts/upstream/Bindings/arm/tegra.yaml +++ b/dts/upstream/Bindings/arm/tegra.yaml @@ -189,6 +189,11 @@ properties: - nvidia,p2371-2180 - nvidia,p2571 - nvidia,p2894-0050-a08 + - nvidia,p3450-0000 + - const: nvidia,tegra210 + - items: + - const: nvidia,p3541-0000 + - const: nvidia,p3450-0000 - const: nvidia,tegra210 - description: Jetson TX2 Developer Kit items: diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml b/dts/upstream/Bindings/arm/ti/k3.yaml index 0105dcda6e0..85deda6d429 100644 --- a/dts/upstream/Bindings/arm/ti/k3.yaml +++ b/dts/upstream/Bindings/arm/ti/k3.yaml @@ -37,6 +37,12 @@ properties: - const: phytec,am62a-phycore-som - const: ti,am62a7 + - description: K3 AM62L3 SoC and Boards + items: + - enum: + - ti,am62l3-evm + - const: ti,am62l3 + - description: K3 AM62P5 SoC and Boards items: - enum: @@ -158,6 +164,14 @@ properties: - ti,am654-evm - const: ti,am654 + - description: K3 AM69 SoC Toradex Aquila Modules and Carrier Boards + items: + - enum: + - toradex,aquila-am69-clover # Aquila AM69 Module on Clover Board + - toradex,aquila-am69-dev # Aquila AM69 Module on Aquila Development Board + - const: toradex,aquila-am69 # Aquila AM69 Module + - const: ti,j784s4 + - description: K3 J7200 SoC oneOf: - const: ti,j7200 @@ -194,6 +208,7 @@ properties: items: - enum: - beagle,am67a-beagley-ai + - kontron,sa67 # Kontron SMARC-sAM67 board - ti,j722s-evm - const: ti,j722s diff --git a/dts/upstream/Bindings/arm/ti/omap.yaml b/dts/upstream/Bindings/arm/ti/omap.yaml index aa5df4692e3..14f1b9d8f59 100644 --- a/dts/upstream/Bindings/arm/ti/omap.yaml +++ b/dts/upstream/Bindings/arm/ti/omap.yaml @@ -129,6 +129,13 @@ properties: - const: phytec,am335x-phycore-som - const: ti,am33xx + - description: TQ-Systems TQMa335x[L] SoM + items: + - enum: + - tq,tqma3359-mba335x # MBa335x carrier board + - const: tq,tqma3359 + - const: ti,am33xx + - description: TI OMAP4430 SoC based platforms items: - enum: diff --git a/dts/upstream/Bindings/arm/ux500.yaml b/dts/upstream/Bindings/arm/ux500.yaml index b42d20fa435..3a8611e5786 100644 --- a/dts/upstream/Bindings/arm/ux500.yaml +++ b/dts/upstream/Bindings/arm/ux500.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ux500 platforms maintainers: - - Linus Walleij + - Linus Walleij properties: $nodename: diff --git a/dts/upstream/Bindings/ata/ata-generic.yaml b/dts/upstream/Bindings/ata/ata-generic.yaml index 0697927f3d7..9da341ea091 100644 --- a/dts/upstream/Bindings/ata/ata-generic.yaml +++ b/dts/upstream/Bindings/ata/ata-generic.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic Parallel ATA Controller maintainers: - - Linus Walleij + - Linus Walleij description: Generic Parallel ATA controllers supporting PIO modes only. diff --git a/dts/upstream/Bindings/ata/cortina,gemini-sata-bridge.yaml b/dts/upstream/Bindings/ata/cortina,gemini-sata-bridge.yaml index 52909366650..66de6d4769c 100644 --- a/dts/upstream/Bindings/ata/cortina,gemini-sata-bridge.yaml +++ b/dts/upstream/Bindings/ata/cortina,gemini-sata-bridge.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cortina Systems Gemini SATA Bridge maintainers: - - Linus Walleij + - Linus Walleij description: | The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that diff --git a/dts/upstream/Bindings/ata/eswin,eic7700-ahci.yaml b/dts/upstream/Bindings/ata/eswin,eic7700-ahci.yaml new file mode 100644 index 00000000000..6554e30018b --- /dev/null +++ b/dts/upstream/Bindings/ata/eswin,eic7700-ahci.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC SATA Controller + +maintainers: + - Yulin Lu + - Huan He + +description: + AHCI SATA controller embedded into the EIC7700 SoC is based on the DWC AHCI + SATA v5.00a IP core. + +select: + properties: + compatible: + const: eswin,eic7700-ahci + required: + - compatible + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + +properties: + compatible: + items: + - const: eswin,eic7700-ahci + - const: snps,dwc-ahci + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: aclk + + resets: + maxItems: 1 + + reset-names: + const: arst + + ports-implemented: + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports-implemented + +unevaluatedProperties: false + +examples: + - | + sata@50420000 { + compatible = "eswin,eic7700-ahci", "snps,dwc-ahci"; + reg = <0x50420000 0x10000>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clock 171>, <&clock 186>; + clock-names = "pclk", "aclk"; + phys = <&sata_phy>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + resets = <&reset 96>; + reset-names = "arst"; + }; diff --git a/dts/upstream/Bindings/ata/faraday,ftide010.yaml b/dts/upstream/Bindings/ata/faraday,ftide010.yaml index fa16f3767c6..32e11d8a0a3 100644 --- a/dts/upstream/Bindings/ata/faraday,ftide010.yaml +++ b/dts/upstream/Bindings/ata/faraday,ftide010.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FTIDE010 PATA controller maintainers: - - Linus Walleij + - Linus Walleij description: | This controller is the first Faraday IDE interface block, used in the diff --git a/dts/upstream/Bindings/ata/intel,ixp4xx-compact-flash.yaml b/dts/upstream/Bindings/ata/intel,ixp4xx-compact-flash.yaml index 378692010c5..894a8b9eb91 100644 --- a/dts/upstream/Bindings/ata/intel,ixp4xx-compact-flash.yaml +++ b/dts/upstream/Bindings/ata/intel,ixp4xx-compact-flash.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx CompactFlash Card Controller maintainers: - - Linus Walleij + - Linus Walleij description: | The IXP4xx network processors have a CompactFlash interface that presents diff --git a/dts/upstream/Bindings/ata/pata-common.yaml b/dts/upstream/Bindings/ata/pata-common.yaml index 4e867dd4d40..cee4bb7eb0b 100644 --- a/dts/upstream/Bindings/ata/pata-common.yaml +++ b/dts/upstream/Bindings/ata/pata-common.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Common Properties for Parallel AT attachment (PATA) controllers maintainers: - - Linus Walleij + - Linus Walleij description: | This document defines device tree properties common to most Parallel diff --git a/dts/upstream/Bindings/ata/sata-common.yaml b/dts/upstream/Bindings/ata/sata-common.yaml index 58c9342b992..667f48c3319 100644 --- a/dts/upstream/Bindings/ata/sata-common.yaml +++ b/dts/upstream/Bindings/ata/sata-common.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Common Properties for Serial AT attachment (SATA) controllers maintainers: - - Linus Walleij + - Linus Walleij description: | This document defines device tree properties common to most Serial diff --git a/dts/upstream/Bindings/ata/snps,dwc-ahci.yaml b/dts/upstream/Bindings/ata/snps,dwc-ahci.yaml index 4c848fcb5a5..7707cbed226 100644 --- a/dts/upstream/Bindings/ata/snps,dwc-ahci.yaml +++ b/dts/upstream/Bindings/ata/snps,dwc-ahci.yaml @@ -33,6 +33,10 @@ properties: - description: SPEAr1340 AHCI SATA device const: snps,spear-ahci + iommus: + minItems: 1 + maxItems: 3 + patternProperties: "^sata-port@[0-9a-e]$": $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port diff --git a/dts/upstream/Bindings/auxdisplay/arm,versatile-lcd.yaml b/dts/upstream/Bindings/auxdisplay/arm,versatile-lcd.yaml index 439f7b811a9..51d68a778b5 100644 --- a/dts/upstream/Bindings/auxdisplay/arm,versatile-lcd.yaml +++ b/dts/upstream/Bindings/auxdisplay/arm,versatile-lcd.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Versatile Character LCD maintainers: - - Linus Walleij + - Linus Walleij - Rob Herring description: diff --git a/dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml b/dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml index 28b37772fb6..e889dac052e 100644 --- a/dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml +++ b/dts/upstream/Bindings/board/fsl,fpga-qixis-i2c.yaml @@ -22,6 +22,13 @@ properties: - fsl,lx2160aqds-fpga - const: fsl,fpga-qixis-i2c - const: simple-mfd + - const: fsl,lx2160ardb-fpga + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 interrupts: maxItems: 1 @@ -32,10 +39,37 @@ properties: mux-controller: $ref: /schemas/mux/reg-mux.yaml +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + enum: + - fsl,lx2160ardb-fpga-gpio-sfp + required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,lx2160ardb-fpga + then: + required: + - "#address-cells" + - "#size-cells" + else: + properties: + "#address-cells": false + "#size-cells": false + additionalProperties: false examples: @@ -68,3 +102,27 @@ examples: }; }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + board-control@66 { + compatible = "fsl,lx2160ardb-fpga"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@19 { + compatible = "fsl,lx2160ardb-fpga-gpio-sfp"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SFP2_TX_EN", "", + "", "", + "SFP2_RX_LOS", "SFP2_TX_FAULT", + "", "SFP2_MOD_ABS"; + }; + }; + }; diff --git a/dts/upstream/Bindings/board/fsl,fpga-qixis.yaml b/dts/upstream/Bindings/board/fsl,fpga-qixis.yaml index 5a3cd431ef6..2eacb581b9f 100644 --- a/dts/upstream/Bindings/board/fsl,fpga-qixis.yaml +++ b/dts/upstream/Bindings/board/fsl,fpga-qixis.yaml @@ -57,6 +57,16 @@ patternProperties: '^mdio-mux@[a-f0-9,]+$': $ref: /schemas/net/mdio-mux-mmioreg.yaml + '^gpio@[0-9a-f]+$': + type: object + additionalProperties: true + + properties: + compatible: + contains: + enum: + - fsl,ls1046aqds-fpga-gpio-stat-pres2 + required: - compatible - reg diff --git a/dts/upstream/Bindings/bus/allwinner,sun8i-a23-rsb.yaml b/dts/upstream/Bindings/bus/allwinner,sun8i-a23-rsb.yaml index 24c939f5909..cd5c2a532a9 100644 --- a/dts/upstream/Bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/dts/upstream/Bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -43,7 +43,7 @@ properties: maximum: 20000000 patternProperties: - "^.*@[0-9a-fA-F]+$": + "@[0-9a-f]+$": type: object additionalProperties: true properties: diff --git a/dts/upstream/Bindings/bus/cznic,moxtet.yaml b/dts/upstream/Bindings/bus/cznic,moxtet.yaml new file mode 100644 index 00000000000..d340899ca5f --- /dev/null +++ b/dts/upstream/Bindings/bus/cznic,moxtet.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/cznic,moxtet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Turris Moxtet SPI bus + +maintainers: + - Marek Behún + +description: > + Turris Mox module status and configuration bus (over SPI) + + The driver finds the devices connected to the bus by itself, but it may be + needed to reference some of them from other parts of the device tree. In that + case the devices can be defined as subnodes of the moxtet node. + +properties: + compatible: + const: cznic,moxtet + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + spi-cpol: true + + spi-cpha: true + + spi-max-frequency: true + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - spi-cpol + - spi-cpha + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: + type: object + + required: + - reg + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + moxtet@1 { + compatible = "cznic,moxtet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + spi-max-frequency = <10000000>; + spi-cpol; + spi-cpha; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gpiosb>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + gpio@0 { + compatible = "cznic,moxtet-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + }; + }; + }; diff --git a/dts/upstream/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/dts/upstream/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml index 4adbb7afa88..6645352c7f6 100644 --- a/dts/upstream/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml +++ b/dts/upstream/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml @@ -70,7 +70,7 @@ properties: - const: ahb patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]+$": description: Devices attached to the bus type: object diff --git a/dts/upstream/Bindings/bus/moxtet.txt b/dts/upstream/Bindings/bus/moxtet.txt deleted file mode 100644 index fb50fc86533..00000000000 --- a/dts/upstream/Bindings/bus/moxtet.txt +++ /dev/null @@ -1,46 +0,0 @@ -Turris Mox module status and configuration bus (over SPI) - -Required properties: - - compatible : Should be "cznic,moxtet" - - #address-cells : Has to be 1 - - #size-cells : Has to be 0 - - spi-cpol : Required inverted clock polarity - - spi-cpha : Required shifted clock phase - - interrupts : Must contain reference to the shared interrupt line - - interrupt-controller : Required - - #interrupt-cells : Has to be 1 - -For other required and optional properties of SPI slave nodes please refer to -../spi/spi-bus.txt. - -Required properties of subnodes: - - reg : Should be position on the Moxtet bus (how many Moxtet - modules are between this module and CPU module, so - either 0 or a positive integer) - -The driver finds the devices connected to the bus by itself, but it may be -needed to reference some of them from other parts of the device tree. In that -case the devices can be defined as subnodes of the moxtet node. - -Example: - - moxtet@1 { - compatible = "cznic,moxtet"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - spi-max-frequency = <10000000>; - spi-cpol; - spi-cpha; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gpiosb>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - - moxtet_sfp: gpio@0 { - compatible = "cznic,moxtet-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - } - }; diff --git a/dts/upstream/Bindings/bus/st,stm32-etzpc.yaml b/dts/upstream/Bindings/bus/st,stm32-etzpc.yaml index d12b62a3a5a..bf0af3424c9 100644 --- a/dts/upstream/Bindings/bus/st,stm32-etzpc.yaml +++ b/dts/upstream/Bindings/bus/st,stm32-etzpc.yaml @@ -44,7 +44,7 @@ properties: Contains the firewall ID associated to the peripheral. patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]+$": description: Peripherals type: object diff --git a/dts/upstream/Bindings/bus/st,stm32mp25-rifsc.yaml b/dts/upstream/Bindings/bus/st,stm32mp25-rifsc.yaml index 20acd1a6b17..4d19917ad2c 100644 --- a/dts/upstream/Bindings/bus/st,stm32mp25-rifsc.yaml +++ b/dts/upstream/Bindings/bus/st,stm32mp25-rifsc.yaml @@ -33,14 +33,18 @@ select: properties: compatible: contains: - const: st,stm32mp25-rifsc + enum: + - st,stm32mp21-rifsc + - st,stm32mp25-rifsc required: - compatible properties: compatible: items: - - const: st,stm32mp25-rifsc + - enum: + - st,stm32mp21-rifsc + - st,stm32mp25-rifsc - const: simple-bus reg: @@ -60,7 +64,7 @@ properties: Contains the firewall ID associated to the peripheral. patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]+$": description: Peripherals type: object diff --git a/dts/upstream/Bindings/cache/qcom,llcc.yaml b/dts/upstream/Bindings/cache/qcom,llcc.yaml index 37e3ebd5548..a620a2ff5c5 100644 --- a/dts/upstream/Bindings/cache/qcom,llcc.yaml +++ b/dts/upstream/Bindings/cache/qcom,llcc.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,ipq5424-llcc + - qcom,kaanapali-llcc - qcom,qcs615-llcc - qcom,qcs8300-llcc - qcom,qdu1000-llcc @@ -272,6 +273,7 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc diff --git a/dts/upstream/Bindings/cache/sifive,ccache0.yaml b/dts/upstream/Bindings/cache/sifive,ccache0.yaml index 579bacb66f3..c0e5ebb1fa4 100644 --- a/dts/upstream/Bindings/cache/sifive,ccache0.yaml +++ b/dts/upstream/Bindings/cache/sifive,ccache0.yaml @@ -48,6 +48,11 @@ properties: - const: microchip,mpfs-ccache - const: sifive,fu540-c000-ccache - const: cache + - items: + - const: microchip,pic64gx-ccache + - const: microchip,mpfs-ccache + - const: sifive,fu540-c000-ccache + - const: cache cache-block-size: const: 64 diff --git a/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml b/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml index fe2c5c1baf4..a8471367175 100644 --- a/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml +++ b/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml @@ -64,8 +64,6 @@ allOf: reg: minItems: 2 - '#reset-cells': false - - if: properties: compatible: @@ -85,6 +83,7 @@ examples: reg = <0x1fa20000 0x400>, <0x1fb00000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; - | diff --git a/dts/upstream/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml b/dts/upstream/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml index c4714d0fbe0..e588a7e8f26 100644 --- a/dts/upstream/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml +++ b/dts/upstream/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml @@ -132,7 +132,6 @@ examples: "ahb_mp", "ahb_mali400"; }; - - | clk@1c20068 { #clock-cells = <1>; diff --git a/dts/upstream/Bindings/clock/armada3700-xtal-clock.txt b/dts/upstream/Bindings/clock/armada3700-xtal-clock.txt deleted file mode 100644 index 4c0807f28cf..00000000000 --- a/dts/upstream/Bindings/clock/armada3700-xtal-clock.txt +++ /dev/null @@ -1,29 +0,0 @@ -* Xtal Clock bindings for Marvell Armada 37xx SoCs - -Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by -reading the gpio latch register. - -This node must be a subnode of the node exposing the register address -of the GPIO block where the gpio latch is located. -See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt - -Required properties: -- compatible : shall be one of the following: - "marvell,armada-3700-xtal-clock" -- #clock-cells : from common clock binding; shall be set to 0 - -Optional properties: -- clock-output-names : from common clock binding; allows overwrite default clock - output names ("xtal") - -Example: -pinctrl_nb: pinctrl-nb@13800 { - compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd"; - reg = <0x13800 0x100>, <0x13C00 0x20>; - - xtalclk: xtal-clk { - compatible = "marvell,armada-3700-xtal-clock"; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/dts/upstream/Bindings/clock/fsl,imx8ulp-sim-lpav.yaml b/dts/upstream/Bindings/clock/fsl,imx8ulp-sim-lpav.yaml new file mode 100644 index 00000000000..662e07528d7 --- /dev/null +++ b/dts/upstream/Bindings/clock/fsl,imx8ulp-sim-lpav.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP LPAV System Integration Module (SIM) + +maintainers: + - Laurentiu Mihalcea + +description: + The i.MX8ULP LPAV subsystem contains a block control module known as + SIM LPAV, which offers functionalities such as clock gating or reset + line assertion/de-assertion. + +properties: + compatible: + const: fsl,imx8ulp-sim-lpav + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: bus + - const: core + - const: plat + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + mux-controller: + $ref: /schemas/mux/reg-mux.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - mux-controller + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2da50000 { + compatible = "fsl,imx8ulp-sim-lpav"; + reg = <0x2da50000 0x10000>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; + clock-names = "bus", "core", "plat"; + #clock-cells = <1>; + #reset-cells = <1>; + + mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; diff --git a/dts/upstream/Bindings/clock/google,gs101-clock.yaml b/dts/upstream/Bindings/clock/google,gs101-clock.yaml index caf442ead24..31e106ef913 100644 --- a/dts/upstream/Bindings/clock/google,gs101-clock.yaml +++ b/dts/upstream/Bindings/clock/google,gs101-clock.yaml @@ -46,6 +46,9 @@ properties: "#clock-cells": const: 1 + power-domains: + maxItems: 1 + reg: maxItems: 1 diff --git a/dts/upstream/Bindings/clock/marvell,ap80x-clock.yaml b/dts/upstream/Bindings/clock/marvell,ap80x-clock.yaml new file mode 100644 index 00000000000..43b0631ba16 --- /dev/null +++ b/dts/upstream/Bindings/clock/marvell,ap80x-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,ap80x-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada AP80x System Controller Clocks + +maintainers: + - Gregory Clement + - Miquel Raynal + +description: > + The AP806/AP807 is one of the two core HW blocks of the Marvell Armada + 7K/8K/931x SoCs. It contains system controllers, which provide several + registers giving access to numerous features: clocks, pin-muxing and many + other SoC configuration items. + +properties: + compatible: + enum: + - marvell,ap806-clock + - marvell,ap806-cpu-clock + - marvell,ap807-clock + - marvell,ap807-cpu-clock + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: cluster 0 parent clock phandle + - description: cluster 1 parent clock phandle + +required: + - compatible + - "#clock-cells" + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - marvell,ap806-cpu-clock + - marvell,ap807-cpu-clock + then: + required: + - clocks diff --git a/dts/upstream/Bindings/clock/marvell,cp110-clock.yaml b/dts/upstream/Bindings/clock/marvell,cp110-clock.yaml new file mode 100644 index 00000000000..ad0bc79b24c --- /dev/null +++ b/dts/upstream/Bindings/clock/marvell,cp110-clock.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,cp110-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada CP110 System Controller Clocks + +maintainers: + - Gregory Clement + - Miquel Raynal + +description: > + The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K/931x + SoCs. It contains system controllers, which provide several registers giving + access to numerous features: clocks, pin-muxing and many other SoC + configuration items. + +properties: + compatible: + const: marvell,cp110-clock + + "#clock-cells": + const: 2 + description: > + The first cell must be 0 or 1. 0 for the core clocks and 1 for the + gateable clocks. The second cell identifies the particular core clock or + gateable clocks. + + The following clocks are available: + + - Core clocks + - 0 0 APLL + - 0 1 PPv2 core + - 0 2 EIP + - 0 3 Core + - 0 4 NAND core + - 0 5 SDIO core + + - Gateable clocks + - 1 0 Audio + - 1 1 Comm Unit + - 1 2 NAND + - 1 3 PPv2 + - 1 4 SDIO + - 1 5 MG Domain + - 1 6 MG Core + - 1 7 XOR1 + - 1 8 XOR0 + - 1 9 GOP DP + - 1 11 PCIe x1 0 + - 1 12 PCIe x1 1 + - 1 13 PCIe x4 + - 1 14 PCIe / XOR + - 1 15 SATA + - 1 16 SATA USB + - 1 17 Main + - 1 18 SD/MMC/GOP + - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) + - 1 22 USB3H0 + - 1 23 USB3H1 + - 1 24 USB3 Device + - 1 25 EIP150 + - 1 26 EIP197 + +required: + - compatible + - "#clock-cells" + +additionalProperties: false diff --git a/dts/upstream/Bindings/clock/microchip,mpfs-clkcfg.yaml b/dts/upstream/Bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d..ee4f31596d9 100644 --- a/dts/upstream/Bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/dts/upstream/Bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and reset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of the mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells = <2>; - #size-cells = <2>; - clkcfg: clock-controller@20002000 { + #address-cells = <1>; + #size-cells = <1>; + + clkcfg: clock-controller@3E001000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; + reg = <0x3E001000 0x1000>; clocks = <&ref>; #clock-cells = <1>; }; diff --git a/dts/upstream/Bindings/clock/nvidia,tegra124-car.yaml b/dts/upstream/Bindings/clock/nvidia,tegra124-car.yaml index a9ba21144a5..13bb616249a 100644 --- a/dts/upstream/Bindings/clock/nvidia,tegra124-car.yaml +++ b/dts/upstream/Bindings/clock/nvidia,tegra124-car.yaml @@ -37,7 +37,7 @@ properties: '#clock-cells': const: 1 - "#reset-cells": + '#reset-cells': const: 1 nvidia,external-memory-controller: @@ -46,7 +46,7 @@ properties: phandle of the external memory controller node patternProperties: - "^emc-timings-[0-9]+$": + '^emc-timings-[0-9]+$': type: object properties: nvidia,ram-code: @@ -56,7 +56,7 @@ patternProperties: this timing set is used for patternProperties: - "^timing-[0-9]+$": + '^timing-[0-9]+$': type: object properties: clock-frequency: @@ -94,7 +94,7 @@ required: - compatible - reg - '#clock-cells' - - "#reset-cells" + - '#reset-cells' additionalProperties: false diff --git a/dts/upstream/Bindings/clock/nvidia,tegra20-car.yaml b/dts/upstream/Bindings/clock/nvidia,tegra20-car.yaml index bee2dd4b29b..73cccc0df42 100644 --- a/dts/upstream/Bindings/clock/nvidia,tegra20-car.yaml +++ b/dts/upstream/Bindings/clock/nvidia,tegra20-car.yaml @@ -39,11 +39,11 @@ properties: '#clock-cells': const: 1 - "#reset-cells": + '#reset-cells': const: 1 patternProperties: - "^(sclk)|(pll-[cem])$": + '^(sclk)|(pll-[cem])$': type: object properties: compatible: @@ -76,7 +76,7 @@ required: - compatible - reg - '#clock-cells' - - "#reset-cells" + - '#reset-cells' additionalProperties: false diff --git a/dts/upstream/Bindings/clock/qcom,ipq9574-nsscc.yaml b/dts/upstream/Bindings/clock/qcom,ipq9574-nsscc.yaml index 17252b6ea3b..7ff4ff3587c 100644 --- a/dts/upstream/Bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/dts/upstream/Bindings/clock/qcom,ipq9574-nsscc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424 maintainers: - Bjorn Andersson @@ -12,21 +12,29 @@ maintainers: description: | Qualcomm networking sub system clock control module provides the clocks, - resets on IPQ9574 + resets on IPQ9574 and IPQ5424 - See also:: + See also: + include/dt-bindings/clock/qcom,ipq5424-nsscc.h include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq5424-nsscc.h include/dt-bindings/reset/qcom,ipq9574-nsscc.h properties: compatible: - const: qcom,ipq9574-nsscc + enum: + - qcom,ipq5424-nsscc + - qcom,ipq9574-nsscc clocks: items: - description: Board XO source - - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source - - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate + can vary for different IPQ SoCs. For example, it is 1200 MHz on the + IPQ9574 and 300 MHz on the IPQ5424. + - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock + rate can vary for different IPQ SoCs. For example, it is 353 MHz + on the IPQ9574 and 375 MHz on the IPQ5424. - description: GCC GPLL0 OUT AUX clock source - description: Uniphy0 NSS Rx clock source - description: Uniphy0 NSS Tx clock source @@ -42,8 +50,12 @@ properties: clock-names: items: - const: xo - - const: nss_1200 - - const: ppe_353 + - enum: + - nss_1200 + - nss + - enum: + - ppe_353 + - ppe - const: gpll0_out - const: uniphy0_rx - const: uniphy0_tx @@ -60,6 +72,40 @@ required: allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + const: qcom,ipq9574-nsscc + then: + properties: + clock-names: + items: + - const: xo + - const: nss_1200 + - const: ppe_353 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + else: + properties: + clock-names: + items: + - const: xo + - const: nss + - const: ppe + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus unevaluatedProperties: false @@ -94,5 +140,6 @@ examples: "bus"; #clock-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; ... diff --git a/dts/upstream/Bindings/clock/qcom,rpmcc.yaml b/dts/upstream/Bindings/clock/qcom,rpmcc.yaml index 90cd3feab5f..ab97d4b7dba 100644 --- a/dts/upstream/Bindings/clock/qcom,rpmcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,rpmcc.yaml @@ -8,7 +8,7 @@ title: Qualcomm RPM Clock Controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: | The clock enumerators are defined in and diff --git a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml index 78fa0572668..3f5f1336262 100644 --- a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,glymur-rpmh-clk + - qcom,kaanapali-rpmh-clk - qcom,milos-rpmh-clk - qcom,qcs615-rpmh-clk - qcom,qdu1000-rpmh-clk diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml index fcd2727dae4..b31bd833552 100644 --- a/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml +++ b/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - - Taniya Das + - Taniya Das - Jagadeesh Kona description: | @@ -17,6 +17,7 @@ description: | See also: include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h + include/dt-bindings/clock/qcom,sm8750-videocc.h properties: compatible: @@ -25,6 +26,7 @@ properties: - qcom,sm8475-videocc - qcom,sm8550-videocc - qcom,sm8650-videocc + - qcom,sm8750-videocc - qcom,x1e80100-videocc clocks: @@ -61,6 +63,7 @@ allOf: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8750-videocc then: required: - required-opps diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml index 2c992b3437f..784fef83068 100644 --- a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml +++ b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml @@ -25,6 +25,7 @@ properties: items: - enum: - qcom,glymur-tcsr + - qcom,kaanapali-tcsr - qcom,milos-tcsr - qcom,sar2130p-tcsr - qcom,sm8550-tcsr diff --git a/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml index aab7039fd28..0114d347b26 100644 --- a/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml @@ -13,11 +13,15 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SM8750 - See also: include/dt-bindings/clock/qcom,sm8750-gcc.h + See also: + include/dt-bindings/clock/qcom,kaanapali-gcc.h + include/dt-bindings/clock/qcom,sm8750-gcc.h properties: compatible: - const: qcom,sm8750-gcc + enum: + - qcom,kaanapali-gcc + - qcom,sm8750-gcc clocks: items: diff --git a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml index 68dde0720c7..1b15b507095 100644 --- a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml +++ b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml @@ -32,9 +32,36 @@ properties: - description: PCIe 5 pipe clock - description: PCIe 6a pipe clock - description: PCIe 6b pipe clock - - description: USB QMP Phy 0 clock source - - description: USB QMP Phy 1 clock source - - description: USB QMP Phy 2 clock source + - description: USB4_0 QMPPHY clock source + - description: USB4_1 QMPPHY clock source + - description: USB4_2 QMPPHY clock source + - description: USB4_0 PHY DP0 GMUX clock source + - description: USB4_0 PHY DP1 GMUX clock source + - description: USB4_0 PHY PCIE PIPEGMUX clock source + - description: USB4_0 PHY PIPEGMUX clock source + - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_1 PHY DP0 GMUX 2 clock source + - description: USB4_1 PHY DP1 GMUX 2 clock source + - description: USB4_1 PHY PCIE PIPEGMUX clock source + - description: USB4_1 PHY PIPEGMUX clock source + - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_2 PHY DP0 GMUX 2 clock source + - description: USB4_2 PHY DP1 GMUX 2 clock source + - description: USB4_2 PHY PCIE PIPEGMUX clock source + - description: USB4_2 PHY PIPEGMUX clock source + - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_0 PHY RX 0 clock source + - description: USB4_0 PHY RX 1 clock source + - description: USB4_1 PHY RX 0 clock source + - description: USB4_1 PHY RX 1 clock source + - description: USB4_2 PHY RX 0 clock source + - description: USB4_2 PHY RX 1 clock source + - description: USB4_0 PHY PCIE PIPE clock source + - description: USB4_0 PHY max PIPE clock source + - description: USB4_1 PHY PCIE PIPE clock source + - description: USB4_1 PHY max PIPE clock source + - description: USB4_2 PHY PCIE PIPE clock source + - description: USB4_2 PHY max PIPE clock source power-domains: description: @@ -67,7 +94,34 @@ examples: <&pcie6b_phy>, <&usb_1_ss0_qmpphy 0>, <&usb_1_ss1_qmpphy 1>, - <&usb_1_ss2_qmpphy 2>; + <&usb_1_ss2_qmpphy 2>, + <&usb4_0_phy_dp0_gmux_clk>, + <&usb4_0_phy_dp1_gmux_clk>, + <&usb4_0_phy_pcie_pipegmux_clk>, + <&usb4_0_phy_pipegmux_clk>, + <&usb4_0_phy_sys_pcie_pipegmux_clk>, + <&usb4_1_phy_dp0_gmux_2_clk>, + <&usb4_1_phy_dp1_gmux_2_clk>, + <&usb4_1_phy_pcie_pipegmux_clk>, + <&usb4_1_phy_pipegmux_clk>, + <&usb4_1_phy_sys_pcie_pipegmux_clk>, + <&usb4_2_phy_dp0_gmux_2_clk>, + <&usb4_2_phy_dp1_gmux_2_clk>, + <&usb4_2_phy_pcie_pipegmux_clk>, + <&usb4_2_phy_pipegmux_clk>, + <&usb4_2_phy_sys_pcie_pipegmux_clk>, + <&usb4_0_phy_rx_0_clk>, + <&usb4_0_phy_rx_1_clk>, + <&usb4_1_phy_rx_0_clk>, + <&usb4_1_phy_rx_1_clk>, + <&usb4_2_phy_rx_0_clk>, + <&usb4_2_phy_rx_1_clk>, + <&usb4_0_phy_pcie_pipe_clk>, + <&usb4_0_phy_max_pipe_clk>, + <&usb4_1_phy_pcie_pipe_clk>, + <&usb4_1_phy_max_pipe_clk>, + <&usb4_2_phy_pcie_pipe_clk>, + <&usb4_2_phy_max_pipe_clk>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/dts/upstream/Bindings/clock/renesas,cpg-mssr.yaml b/dts/upstream/Bindings/clock/renesas,cpg-mssr.yaml index bc2fd376132..655154534c0 100644 --- a/dts/upstream/Bindings/clock/renesas,cpg-mssr.yaml +++ b/dts/upstream/Bindings/clock/renesas,cpg-mssr.yaml @@ -99,7 +99,6 @@ properties: the datasheet. const: 1 - required: - compatible - reg diff --git a/dts/upstream/Bindings/clock/rockchip,rk3506-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rk3506-cru.yaml new file mode 100644 index 00000000000..ca940475336 --- /dev/null +++ b/dts/upstream/Bindings/clock/rockchip,rk3506-cru.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3506 Clock and Reset Unit (CRU) + +maintainers: + - Finley Xiao + - Heiko Stuebner + +description: + The RK3506 CRU generates the clock and also implements reset for SoC + peripherals. + +properties: + compatible: + const: rockchip,rk3506-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clock-controller@ff9a0000 { + compatible = "rockchip,rk3506-cru"; + reg = <0xff9a0000 0x20000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&xin24m>; + clock-names = "xin"; + }; diff --git a/dts/upstream/Bindings/clock/rockchip,rv1126b-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rv1126b-cru.yaml new file mode 100644 index 00000000000..04b0a5c51e4 --- /dev/null +++ b/dts/upstream/Bindings/clock/rockchip,rv1126b-cru.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1126B Clock and Reset Unit + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: + The rv1126b clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + enum: + - rockchip,rv1126b-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@20000000 { + compatible = "rockchip,rv1126b-cru"; + reg = <0x20000000 0xc0000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml b/dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml index 72f59db73f7..5bf905f88a1 100644 --- a/dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml +++ b/dts/upstream/Bindings/clock/samsung,exynosautov920-clock.yaml @@ -38,6 +38,8 @@ properties: - samsung,exynosautov920-cmu-hsi0 - samsung,exynosautov920-cmu-hsi1 - samsung,exynosautov920-cmu-hsi2 + - samsung,exynosautov920-cmu-m2m + - samsung,exynosautov920-cmu-mfc - samsung,exynosautov920-cmu-misc - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 @@ -226,6 +228,46 @@ allOf: - const: embd - const: ethernet + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-m2m + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_M2M NOC clock (from CMU_TOP) + - description: CMU_M2M JPEG clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: jpeg + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-mfc + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_MFC MFC clock (from CMU_TOP) + - description: CMU_MFC WFD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: mfc + - const: wfd + required: - compatible - "#clock-cells" diff --git a/dts/upstream/Bindings/clock/sprd,sc9860-clk.yaml b/dts/upstream/Bindings/clock/sprd,sc9860-clk.yaml index 502cd723511..b131390207d 100644 --- a/dts/upstream/Bindings/clock/sprd,sc9860-clk.yaml +++ b/dts/upstream/Bindings/clock/sprd,sc9860-clk.yaml @@ -114,25 +114,6 @@ allOf: - reg properties: sprd,syscon: false - - if: - properties: - compatible: - contains: - enum: - - sprd,sc9860-agcp-gate - - sprd,sc9860-aon-gate - - sprd,sc9860-apahb-gate - - sprd,sc9860-apapb-gate - - sprd,sc9860-cam-gate - - sprd,sc9860-disp-gate - - sprd,sc9860-pll - - sprd,sc9860-pmu-gate - - sprd,sc9860-vsp-gate - then: - required: - - sprd,syscon - properties: - reg: false additionalProperties: false @@ -142,13 +123,6 @@ examples: #address-cells = <2>; #size-cells = <2>; - pmu-gate { - compatible = "sprd,sc9860-pmu-gate"; - clocks = <&ext_26m>; - #clock-cells = <1>; - sprd,syscon = <&pmu_regs>; - }; - clock-controller@20000000 { compatible = "sprd,sc9860-ap-clk"; reg = <0 0x20000000 0 0x400>; diff --git a/dts/upstream/Bindings/clock/stericsson,u8500-clks.yaml b/dts/upstream/Bindings/clock/stericsson,u8500-clks.yaml index 2150307219a..4ebfa5a8d52 100644 --- a/dts/upstream/Bindings/clock/stericsson,u8500-clks.yaml +++ b/dts/upstream/Bindings/clock/stericsson,u8500-clks.yaml @@ -8,7 +8,7 @@ title: ST-Ericsson DB8500 (U8500) clocks maintainers: - Ulf Hansson - - Linus Walleij + - Linus Walleij description: While named "U8500 clocks" these clocks are inside the DB8500 digital baseband system-on-chip and its siblings such as diff --git a/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml b/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml index b44a76a958f..b497c28e809 100644 --- a/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml +++ b/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml @@ -22,7 +22,6 @@ properties: - xlnx,clocking-wizard-v6.0 - xlnx,versal-clk-wizard - reg: maxItems: 1 diff --git a/dts/upstream/Bindings/crypto/amd,ccp-seattle-v1a.yaml b/dts/upstream/Bindings/crypto/amd,ccp-seattle-v1a.yaml index 32bf3a1c3b4..5fb70847105 100644 --- a/dts/upstream/Bindings/crypto/amd,ccp-seattle-v1a.yaml +++ b/dts/upstream/Bindings/crypto/amd,ccp-seattle-v1a.yaml @@ -21,6 +21,9 @@ properties: dma-coherent: true + iommus: + maxItems: 4 + required: - compatible - reg diff --git a/dts/upstream/Bindings/crypto/intel,ixp4xx-crypto.yaml b/dts/upstream/Bindings/crypto/intel,ixp4xx-crypto.yaml index a4006237aa8..fd20b819720 100644 --- a/dts/upstream/Bindings/crypto/intel,ixp4xx-crypto.yaml +++ b/dts/upstream/Bindings/crypto/intel,ixp4xx-crypto.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx cryptographic engine maintainers: - - Linus Walleij + - Linus Walleij description: | The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE diff --git a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml index 08fe6a707a3..c3408dcf5d2 100644 --- a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml @@ -13,6 +13,7 @@ properties: compatible: items: - enum: + - qcom,kaanapali-inline-crypto-engine - qcom,qcs8300-inline-crypto-engine - qcom,sa8775p-inline-crypto-engine - qcom,sc7180-inline-crypto-engine diff --git a/dts/upstream/Bindings/crypto/qcom,prng.yaml b/dts/upstream/Bindings/crypto/qcom,prng.yaml index ed7e16bd11d..597441d94cf 100644 --- a/dts/upstream/Bindings/crypto/qcom,prng.yaml +++ b/dts/upstream/Bindings/crypto/qcom,prng.yaml @@ -20,6 +20,7 @@ properties: - qcom,ipq5332-trng - qcom,ipq5424-trng - qcom,ipq9574-trng + - qcom,kaanapali-trng - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng diff --git a/dts/upstream/Bindings/crypto/qcom-qce.yaml b/dts/upstream/Bindings/crypto/qcom-qce.yaml index e009cb712fb..79d5be2548b 100644 --- a/dts/upstream/Bindings/crypto/qcom-qce.yaml +++ b/dts/upstream/Bindings/crypto/qcom-qce.yaml @@ -45,6 +45,7 @@ properties: - items: - enum: + - qcom,kaanapali-qce - qcom,qcs615-qce - qcom,qcs8300-qce - qcom,sa8775p-qce diff --git a/dts/upstream/Bindings/devfreq/nvidia,tegra30-actmon.yaml b/dts/upstream/Bindings/devfreq/nvidia,tegra30-actmon.yaml index e3379d10672..ea1dc86bc31 100644 --- a/dts/upstream/Bindings/devfreq/nvidia,tegra30-actmon.yaml +++ b/dts/upstream/Bindings/devfreq/nvidia,tegra30-actmon.yaml @@ -19,11 +19,14 @@ description: | properties: compatible: - enum: - - nvidia,tegra30-actmon - - nvidia,tegra114-actmon - - nvidia,tegra124-actmon - - nvidia,tegra210-actmon + oneOf: + - enum: + - nvidia,tegra30-actmon + - nvidia,tegra114-actmon + - nvidia,tegra124-actmon + - items: + - const: nvidia,tegra210-actmon + - const: nvidia,tegra124-actmon reg: maxItems: 1 diff --git a/dts/upstream/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml b/dts/upstream/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml index 98e8240a05b..995b3ef408b 100644 --- a/dts/upstream/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml +++ b/dts/upstream/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml @@ -121,5 +121,4 @@ examples: }; }; - ... diff --git a/dts/upstream/Bindings/display/allwinner,sun6i-a31-drc.yaml b/dts/upstream/Bindings/display/allwinner,sun6i-a31-drc.yaml index 895506d93f4..85a6086cc10 100644 --- a/dts/upstream/Bindings/display/allwinner,sun6i-a31-drc.yaml +++ b/dts/upstream/Bindings/display/allwinner,sun6i-a31-drc.yaml @@ -121,5 +121,4 @@ examples: }; }; - ... diff --git a/dts/upstream/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/dts/upstream/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml index 60fd927b5a0..c43b02ec884 100644 --- a/dts/upstream/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +++ b/dts/upstream/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -142,7 +142,6 @@ then: reset-names: minItems: 2 - additionalProperties: false examples: diff --git a/dts/upstream/Bindings/display/amlogic,meson-vpu.yaml b/dts/upstream/Bindings/display/amlogic,meson-vpu.yaml index cb0a90f0232..3ae45db85ea 100644 --- a/dts/upstream/Bindings/display/amlogic,meson-vpu.yaml +++ b/dts/upstream/Bindings/display/amlogic,meson-vpu.yaml @@ -25,7 +25,6 @@ description: | M |-------|______|----|____________| |________________| | | ___|__________________________________________________________|_______________| - VIU: Video Input Unit --------------------- diff --git a/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml b/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml index 6d11f5955b5..c1cefd54739 100644 --- a/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml +++ b/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml @@ -56,22 +56,12 @@ properties: - const: cec interrupts: - items: - - description: CEC TX interrupt - - description: CEC RX interrupt - - description: CEC stuck at low interrupt - - description: Wake-up interrupt - - description: Hotplug connected interrupt - - description: Hotplug removed interrupt + minItems: 5 + maxItems: 6 interrupt-names: - items: - - const: cec-tx - - const: cec-rx - - const: cec-low - - const: wakeup - - const: hpd-connected - - const: hpd-removed + minItems: 5 + maxItems: 6 ddc: $ref: /schemas/types.yaml#/definitions/phandle @@ -112,6 +102,61 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm2711-hdmi0 + - brcm,bcm2711-hdmi1 + then: + properties: + interrupts: + items: + - description: CEC TX interrupt + - description: CEC RX interrupt + - description: CEC stuck at low interrupt + - description: Wake-up interrupt + - description: Hotplug connected interrupt + - description: Hotplug removed interrupt + interrupt-names: + items: + - const: cec-tx + - const: cec-rx + - const: cec-low + - const: wakeup + - const: hpd-connected + - const: hpd-removed + + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm2712-hdmi0 + - brcm,bcm2712-hdmi1 + then: + properties: + interrupts: + items: + - description: CEC TX interrupt + - description: CEC RX interrupt + - description: CEC stuck at low interrupt + - description: Hotplug connected interrupt + - description: Hotplug removed interrupt + interrupts-names: + items: + - const: cec-tx + - const: cec-rx + - const: cec-low + - const: hpd-connected + - const: hpd-removed + + required: + - interrupts + - interrupt-names + examples: - | hdmi0: hdmi@7ef00700 { @@ -136,6 +181,9 @@ examples: "hd"; clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; clock-names = "hdmi", "bvb", "audio", "cec"; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", "wakeup", + "hpd-connected", "hpd-removed"; resets = <&dvp 0>; ddc = <&ddc0>; }; diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml index f91c9dce2a4..9aca38a58a1 100644 --- a/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml +++ b/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml @@ -20,11 +20,20 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 3 + + interrupt-names: + minItems: 1 + maxItems: 3 clocks: - maxItems: 1 - description: Core Clock + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 required: - compatible @@ -33,17 +42,68 @@ required: additionalProperties: false -if: - properties: - compatible: - contains: - enum: - - brcm,bcm2711-hvs - - brcm,bcm2712-hvs +allOf: + - if: + properties: + compatible: + contains: + const: brcm,bcm2711-hvs -then: - required: - - clocks + then: + properties: + clocks: + items: + - description: Core Clock + interrupts: + maxItems: 1 + clock-names: false + interrupt-names: false + + required: + - clocks + + - if: + properties: + compatible: + contains: + const: brcm,bcm2712-hvs + + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: core + - const: disp + interrupts: + items: + - description: Channel 0 End of frame + - description: Channel 1 End of frame + - description: Channel 2 End of frame + interrupt-names: + items: + - const: ch0-eof + - const: ch1-eof + - const: ch2-eof + required: + - clocks + - clock-names + - interrupt-names + + - if: + properties: + compatible: + contains: + const: brcm,bcm2835-hvs + + then: + properties: + interrupts: + maxItems: 1 + clock-names: false + interrupt-names: false examples: - | diff --git a/dts/upstream/Bindings/display/bridge/adi,adv7511.yaml b/dts/upstream/Bindings/display/bridge/adi,adv7511.yaml index 5bbe81862c8..d29a0d06187 100644 --- a/dts/upstream/Bindings/display/bridge/adi,adv7511.yaml +++ b/dts/upstream/Bindings/display/bridge/adi,adv7511.yaml @@ -156,7 +156,6 @@ else: adi,input-style: false adi,input-justification: false - required: - compatible - reg diff --git a/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml b/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml index 05442d43775..6211ab8bbb0 100644 --- a/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml +++ b/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml @@ -49,6 +49,10 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: HDMI output port + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel audio input port + required: - port@0 - port@1 @@ -98,5 +102,13 @@ examples: remote-endpoint = <&hdmi0_con>; }; }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&pai_to_hdmi_tx>; + }; + }; }; }; diff --git a/dts/upstream/Bindings/display/bridge/ite,it66121.yaml b/dts/upstream/Bindings/display/bridge/ite,it66121.yaml index ba644c30dcf..17d1f97ce8c 100644 --- a/dts/upstream/Bindings/display/bridge/ite,it66121.yaml +++ b/dts/upstream/Bindings/display/bridge/ite,it66121.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - ite,it66121 + - ite,it66122 - ite,it6610 reg: diff --git a/dts/upstream/Bindings/display/bridge/lvds-codec.yaml b/dts/upstream/Bindings/display/bridge/lvds-codec.yaml index 0487bbffd7f..4f7d3e9cf0c 100644 --- a/dts/upstream/Bindings/display/bridge/lvds-codec.yaml +++ b/dts/upstream/Bindings/display/bridge/lvds-codec.yaml @@ -131,7 +131,6 @@ required: additionalProperties: false - examples: - | lvds-encoder { diff --git a/dts/upstream/Bindings/display/bridge/parade,ps8622.yaml b/dts/upstream/Bindings/display/bridge/parade,ps8622.yaml index e6397ac2048..235018a81e8 100644 --- a/dts/upstream/Bindings/display/bridge/parade,ps8622.yaml +++ b/dts/upstream/Bindings/display/bridge/parade,ps8622.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Parade PS8622/PS8625 DisplayPort to LVDS Converter maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski properties: compatible: diff --git a/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml index c167795c63f..b95f10edd3a 100644 --- a/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml +++ b/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml @@ -14,6 +14,9 @@ description: | R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up to four data lanes. +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + properties: compatible: enum: @@ -80,14 +83,14 @@ required: - resets - ports -additionalProperties: false +unevaluatedProperties: false examples: - | #include #include - dsi0: dsi-encoder@fed80000 { + dsi@fed80000 { compatible = "renesas,r8a779a0-dsi-csi2-tx"; reg = <0xfed80000 0x10000>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -117,4 +120,51 @@ examples: }; }; }; + + - | + #include + #include + + dsi@fed80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0xfed80000 0x10000>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 415>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + dsi0port1_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <1 2>; + }; + }; + }; + + panel@0 { + reg = <0>; + compatible = "raspberrypi,dsi-7inch", "ilitek,ili9881c"; + power-supply = <&vcc_lcd_reg>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0port1_out>; + }; + }; + }; + }; ... diff --git a/dts/upstream/Bindings/display/bridge/sil,sii8620.yaml b/dts/upstream/Bindings/display/bridge/sil,sii8620.yaml index 6d1a36b76fc..a5fe46de353 100644 --- a/dts/upstream/Bindings/display/bridge/sil,sii8620.yaml +++ b/dts/upstream/Bindings/display/bridge/sil,sii8620.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Silicon Image SiI8620 HDMI/MHL bridge maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski properties: compatible: diff --git a/dts/upstream/Bindings/display/bridge/simple-bridge.yaml b/dts/upstream/Bindings/display/bridge/simple-bridge.yaml index 9ef587d4650..20c7e0a7780 100644 --- a/dts/upstream/Bindings/display/bridge/simple-bridge.yaml +++ b/dts/upstream/Bindings/display/bridge/simple-bridge.yaml @@ -27,7 +27,9 @@ properties: - const: adi,adv7123 - enum: - adi,adv7123 + - asl-tek,cs5263 - dumb-vga-dac + - parade,ps185hdm - radxa,ra620 - realtek,rtd2171 - ti,opa362 diff --git a/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml b/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml index b78f64c9c5f..70f229dc4e0 100644 --- a/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml +++ b/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml @@ -123,7 +123,6 @@ properties: - required: - port@1 - required: - compatible - reg diff --git a/dts/upstream/Bindings/display/dsi-controller.yaml b/dts/upstream/Bindings/display/dsi-controller.yaml index bb4d6e9e7d0..850b86fe03c 100644 --- a/dts/upstream/Bindings/display/dsi-controller.yaml +++ b/dts/upstream/Bindings/display/dsi-controller.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Common Properties for DSI Display Panels maintainers: - - Linus Walleij + - Linus Walleij description: | This document defines device tree properties common to DSI, Display diff --git a/dts/upstream/Bindings/display/faraday,tve200.yaml b/dts/upstream/Bindings/display/faraday,tve200.yaml index e2ee7776732..b09628b6917 100644 --- a/dts/upstream/Bindings/display/faraday,tve200.yaml +++ b/dts/upstream/Bindings/display/faraday,tve200.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday TV Encoder TVE200 maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/display/ilitek,ili9486.yaml b/dts/upstream/Bindings/display/ilitek,ili9486.yaml index 9cc1fd0751c..7d78edc403d 100644 --- a/dts/upstream/Bindings/display/ilitek,ili9486.yaml +++ b/dts/upstream/Bindings/display/ilitek,ili9486.yaml @@ -54,7 +54,6 @@ examples: #address-cells = <1>; #size-cells = <0>; - display@0{ compatible = "waveshare,rpi-lcd-35", "ilitek,ili9486"; reg = <0>; diff --git a/dts/upstream/Bindings/display/imx/fsl,imx8mp-hdmi-pai.yaml b/dts/upstream/Bindings/display/imx/fsl,imx8mp-hdmi-pai.yaml new file mode 100644 index 00000000000..4f99682a308 --- /dev/null +++ b/dts/upstream/Bindings/display/imx/fsl,imx8mp-hdmi-pai.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pai.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI Parallel Audio Interface + +maintainers: + - Shengjiu Wang + +description: + The HDMI TX Parallel Audio Interface (HTX_PAI) is a bridge between the + Audio Subsystem to the HDMI TX Controller. + +properties: + compatible: + const: fsl,imx8mp-hdmi-pai + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: apb + + power-domains: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Output to the HDMI TX controller. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - port + +additionalProperties: false + +examples: + - | + #include + #include + + audio-bridge@32fc4800 { + compatible = "fsl,imx8mp-hdmi-pai"; + reg = <0x32fc4800 0x800>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <14>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "apb"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI>; + + port { + pai_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pai>; + }; + }; + }; diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,dp.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,dp.yaml index 274f590807c..8f4bd9fb560 100644 --- a/dts/upstream/Bindings/display/mediatek/mediatek,dp.yaml +++ b/dts/upstream/Bindings/display/mediatek/mediatek,dp.yaml @@ -11,7 +11,7 @@ maintainers: - Jitao shi description: | - MediaTek DP and eDP are different hardwares and there are some features + MediaTek DP and eDP are different hardware and there are some features which are not supported for eDP. For example, audio is not supported for eDP. Therefore, we need to use two different compatibles to describe them. In addition, We just need to enable the power domain of DP, so the clock diff --git a/dts/upstream/Bindings/display/msm/dp-controller.yaml b/dts/upstream/Bindings/display/msm/dp-controller.yaml index aeb4e4f3604..ebda78db87a 100644 --- a/dts/upstream/Bindings/display/msm/dp-controller.yaml +++ b/dts/upstream/Bindings/display/msm/dp-controller.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - qcom,glymur-dp - qcom,sa8775p-dp - qcom,sc7180-dp - qcom,sc7280-dp @@ -31,6 +32,11 @@ properties: - qcom,sm8650-dp - qcom,x1e80100-dp + - items: + - enum: + - qcom,qcs8300-dp + - const: qcom,sa8775p-dp + - items: - enum: - qcom,sm6350-dp @@ -53,6 +59,12 @@ properties: - qcom,sm8550-dp - const: qcom,sm8350-dp + - items: + - enum: + - qcom,sm6150-dp + - const: qcom,sm8150-dp + - const: qcom,sm8350-dp + - items: - enum: - qcom,sm8750-dp @@ -195,9 +207,11 @@ allOf: compatible: contains: enum: + - qcom,glymur-dp - qcom,sa8775p-dp - qcom,x1e80100-dp then: + $ref: /schemas/sound/dai-common.yaml# oneOf: - required: - aux-bus @@ -239,6 +253,7 @@ allOf: enum: # these platforms support 2 streams MST on some interfaces, # others are SST only + - qcom,glymur-dp - qcom,sc8280xp-dp - qcom,x1e80100-dp then: @@ -295,7 +310,7 @@ allOf: minItems: 6 maxItems: 8 -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/upstream/Bindings/display/msm/gmu.yaml b/dts/upstream/Bindings/display/msm/gmu.yaml index afc18793574..e32056ae0f5 100644 --- a/dts/upstream/Bindings/display/msm/gmu.yaml +++ b/dts/upstream/Bindings/display/msm/gmu.yaml @@ -21,7 +21,7 @@ properties: compatible: oneOf: - items: - - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu - items: - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$' @@ -299,6 +299,64 @@ allOf: required: - qcom,qmp + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-840.1 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: memnoc + - const: hub + + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-x285.1 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + - description: GMU RSCC HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: memnoc + - const: hub + - const: rscc + - if: properties: compatible: diff --git a/dts/upstream/Bindings/display/msm/gpu.yaml b/dts/upstream/Bindings/display/msm/gpu.yaml index 3696b083e35..826aafdcc20 100644 --- a/dts/upstream/Bindings/display/msm/gpu.yaml +++ b/dts/upstream/Bindings/display/msm/gpu.yaml @@ -133,7 +133,6 @@ properties: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. - required: - compatible - reg diff --git a/dts/upstream/Bindings/display/msm/qcom,glymur-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,glymur-mdss.yaml new file mode 100644 index 00000000000..2329ed96e6c --- /dev/null +++ b/dts/upstream/Bindings/display/msm/qcom,glymur-mdss.yaml @@ -0,0 +1,264 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Glymur Display MDSS + +maintainers: + - Abel Vesa + +description: + Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DP interfaces, etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,glymur-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,glymur-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,glymur-dp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,glymur-dp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&dispcc_mdp_clk>; + clock-names = "bus", "nrt_bus", "core"; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + resets = <&disp_cc_mdss_core_bcr>; + + power-domains = <&mdss_gdsc>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_mdp_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@ae90000 { + compatible = "qcom,glymur-dp"; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0x600>, + <0xae91000 0x400>, + <0xae91400 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc_mdss_ahb_clk>, + <&dispcc_dptx0_aux_clk>, + <&dispcc_dptx0_link_clk>, + <&dispcc_dptx0_link_intf_clk>, + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>; + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&mdss_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/display/msm/qcom,qcs8300-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,qcs8300-mdss.yaml new file mode 100644 index 00000000000..e96baaae9ba --- /dev/null +++ b/dts/upstream/Bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -0,0 +1,286 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,qcs8300-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS8300 Display MDSS + +maintainers: + - Yongxing Mou + +description: + QCS8300 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DP interfaces and EDP etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,qcs8300-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,qcs8300-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,qcs8300-dp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,qcs8300-edp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + mdss: display-subsystem@ae00000 { + compatible = "qcom,qcs8300-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets = <&dispcc_core_bcr>; + power-domains = <&dispcc_gdsc>; + + clocks = <&dispcc_ahb_clk>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc_mdp_clk>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0_phy: phy@aec2a00 { + compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; + + reg = <0x0aec2a00 0x200>, + <0x0aec2200 0xd0>, + <0x0aec2600 0xd0>, + <0x0aec2000 0x1c8>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + }; + + displayport-controller@af54000 { + compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; + + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0xaf57000 0x09c>, + <0xaf58000 0x09c>, + <0xaf59000 0x09c>, + <0xaf5a000 0x23c>, + <0xaf5b000 0x23c>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>; + phys = <&mdss_dp0_phy>; + phy-names = "dp"; + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml index 9ac24f99d3a..46e9335f849 100644 --- a/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml +++ b/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml @@ -51,6 +51,14 @@ patternProperties: compatible: const: qcom,sm6150-dpu + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sm6150-dp + "^dsi@[0-9a-f]+$": type: object additionalProperties: true @@ -130,35 +138,37 @@ examples: #size-cells = <0>; port@0 { - reg = <0>; - dpu_intf0_out: endpoint { - }; + reg = <0>; + + dpu_intf0_out: endpoint { + }; }; port@1 { - reg = <1>; - dpu_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; - }; + reg = <1>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; }; }; mdp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_low_svs>; + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs>; }; - opp-25600000 { - opp-hz = /bits/ 64 <25600000>; - required-opps = <&rpmhpd_opp_svs>; + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmhpd_opp_svs>; }; opp-307200000 { - opp-hz = /bits/ 64 <307200000>; - required-opps = <&rpmhpd_opp_nom>; + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmhpd_opp_nom>; }; }; }; diff --git a/dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml b/dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml index 0a46120dd86..fe296e3186d 100644 --- a/dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml @@ -13,11 +13,17 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - enum: - - qcom,sa8775p-dpu - - qcom,sm8650-dpu - - qcom,sm8750-dpu - - qcom,x1e80100-dpu + oneOf: + - enum: + - qcom,glymur-dpu + - qcom,sa8775p-dpu + - qcom,sm8650-dpu + - qcom,sm8750-dpu + - qcom,x1e80100-dpu + - items: + - enum: + - qcom,qcs8300-dpu + - const: qcom,sa8775p-dpu reg: items: diff --git a/dts/upstream/Bindings/display/msm/qcom,sm8750-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm8750-mdss.yaml index 4151f475f3b..d55fda9a523 100644 --- a/dts/upstream/Bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/dts/upstream/Bindings/display/msm/qcom,sm8750-mdss.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SM8750 Display MDSS maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like diff --git a/dts/upstream/Bindings/display/panel/arm,rtsm-display.yaml b/dts/upstream/Bindings/display/panel/arm,rtsm-display.yaml index 4ad484f09ba..fc04558fcc8 100644 --- a/dts/upstream/Bindings/display/panel/arm,rtsm-display.yaml +++ b/dts/upstream/Bindings/display/panel/arm,rtsm-display.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Arm RTSM Virtual Platforms Display maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: panel-common.yaml# diff --git a/dts/upstream/Bindings/display/panel/arm,versatile-tft-panel.yaml b/dts/upstream/Bindings/display/panel/arm,versatile-tft-panel.yaml index c9958f824d9..b6c18e7283c 100644 --- a/dts/upstream/Bindings/display/panel/arm,versatile-tft-panel.yaml +++ b/dts/upstream/Bindings/display/panel/arm,versatile-tft-panel.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Versatile TFT Panels maintainers: - - Linus Walleij + - Linus Walleij description: | These panels are connected to the daughterboards found on the diff --git a/dts/upstream/Bindings/display/panel/ilitek,il79900a.yaml b/dts/upstream/Bindings/display/panel/ilitek,il79900a.yaml new file mode 100644 index 00000000000..02f7fb1f16d --- /dev/null +++ b/dts/upstream/Bindings/display/panel/ilitek,il79900a.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,il79900a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek IL79900a based MIPI-DSI panels + +maintainers: + - Langyan Ye + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - tianma,tl121bvms07-00 + - const: ilitek,il79900a + + reg: + maxItems: 1 + description: DSI virtual channel used by the panel + + enable-gpios: + maxItems: 1 + description: GPIO specifier for the enable pin + + avdd-supply: + description: Positive analog voltage supply (AVDD) + + avee-supply: + description: Negative analog voltage supply (AVEE) + + pp1800-supply: + description: 1.8V logic voltage supply + + backlight: true + +required: + - compatible + - reg + - enable-gpios + - avdd-supply + - avee-supply + - pp1800-supply + +additionalProperties: false + +examples: + - | + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "tianma,tl121bvms07-00", "ilitek,il79900a"; + reg = <0>; + enable-gpios = <&pio 25 0>; + avdd-supply = <®_avdd>; + avee-supply = <®_avee>; + pp1800-supply = <®_pp1800>; + backlight = <&backlight>; + }; + }; + +... diff --git a/dts/upstream/Bindings/display/panel/ilitek,ili9322.yaml b/dts/upstream/Bindings/display/panel/ilitek,ili9322.yaml index 44423465f6e..4bdc33d1230 100644 --- a/dts/upstream/Bindings/display/panel/ilitek,ili9322.yaml +++ b/dts/upstream/Bindings/display/panel/ilitek,ili9322.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ilitek ILI9322 TFT panel driver with SPI control bus maintainers: - - Linus Walleij + - Linus Walleij description: | This is a driver for 320x240 TFT panels, accepting a variety of input diff --git a/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml b/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml index 434cc6af9c9..d979701a00a 100644 --- a/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml +++ b/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml @@ -20,9 +20,11 @@ properties: - bananapi,lhr050h41 - bestar,bsd1218-a101kl68 - feixin,k101-im2byl02 + - raspberrypi,dsi-5inch - raspberrypi,dsi-7inch - startek,kd050hdfia020 - tdo,tl050hdv35 + - wanchanglong,w552946aaa - wanchanglong,w552946aba - const: ilitek,ili9881c @@ -30,6 +32,7 @@ properties: maxItems: 1 backlight: true + port: true power-supply: true reset-gpios: true rotation: true diff --git a/dts/upstream/Bindings/display/panel/lg,ld070wx3-sl01.yaml b/dts/upstream/Bindings/display/panel/lg,ld070wx3-sl01.yaml new file mode 100644 index 00000000000..0f0b9079f19 --- /dev/null +++ b/dts/upstream/Bindings/display/panel/lg,ld070wx3-sl01.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/lg,ld070wx3-sl01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LG Corporation 7" WXGA TFT LCD panel + +maintainers: + - Svyatoslav Ryhel + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: lg,ld070wx3-sl01 + + reg: + maxItems: 1 + + vdd-supply: true + vcc-supply: true + + backlight: true + port: true + +required: + - compatible + - vdd-supply + - vcc-supply + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "lg,ld070wx3-sl01"; + reg = <0>; + + vdd-supply = <&vdd_3v3_lcd>; + vcc-supply = <&vcc_1v8_lcd>; + + backlight = <&backlight>; + + port { + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/display/panel/novatek,nt35510.yaml b/dts/upstream/Bindings/display/panel/novatek,nt35510.yaml index bb50fd5506c..b39fd0c5a48 100644 --- a/dts/upstream/Bindings/display/panel/novatek,nt35510.yaml +++ b/dts/upstream/Bindings/display/panel/novatek,nt35510.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Novatek NT35510-based display panels maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: panel-common.yaml# diff --git a/dts/upstream/Bindings/display/panel/panel-lvds.yaml b/dts/upstream/Bindings/display/panel/panel-lvds.yaml index 4388d537585..dbc01e64089 100644 --- a/dts/upstream/Bindings/display/panel/panel-lvds.yaml +++ b/dts/upstream/Bindings/display/panel/panel-lvds.yaml @@ -59,6 +59,8 @@ properties: # Jenson Display BL-JT60050-01A 7" WSVGA (1024x600) color TFT LCD LVDS panel - jenson,bl-jt60050-01a - tbs,a711-panel + # Winstar WF70A8SYJHLNGA 7" WSVGA (1024x600) color TFT LCD LVDS panel + - winstar,wf70a8syjhlnga - const: panel-lvds diff --git a/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml b/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml index 9b92a05791c..8d668979b62 100644 --- a/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml +++ b/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml @@ -19,6 +19,9 @@ description: | If the panel is more advanced a dedicated binding file is required. +allOf: + - $ref: panel-common.yaml# + properties: compatible: @@ -42,8 +45,6 @@ properties: - kingdisplay,kd097d04 # LG ACX467AKM-7 4.95" 1080×1920 LCD Panel - lg,acx467akm-7 - # LG Corporation 7" WXGA TFT LCD panel - - lg,ld070wx3-sl01 # LG Corporation 5" HD TFT LCD panel - lg,lh500wx1-sd03 # Lincoln LCD197 5" 1080x1920 LCD panel @@ -56,10 +57,6 @@ properties: - panasonic,vvx10f034n00 # Samsung s6e3fa7 1080x2220 based AMS559NK06 AMOLED panel - samsung,s6e3fa7-ams559nk06 - # Samsung s6e3fc2x01 1080x2340 AMOLED panel - - samsung,s6e3fc2x01 - # Samsung sofef00 1080x2280 AMOLED panel - - samsung,sofef00 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel - tdo,tl070wsh30 @@ -72,31 +69,12 @@ properties: reset-gpios: true port: true power-supply: true - vddio-supply: true - -allOf: - - $ref: panel-common.yaml# - - if: - properties: - compatible: - enum: - - samsung,s6e3fc2x01 - - samsung,sofef00 - then: - properties: - power-supply: false - required: - - vddio-supply - else: - properties: - vddio-supply: false - required: - - power-supply additionalProperties: false required: - compatible + - power-supply - reg examples: diff --git a/dts/upstream/Bindings/display/panel/panel-simple.yaml b/dts/upstream/Bindings/display/panel/panel-simple.yaml index 2017428d882..24e277b1909 100644 --- a/dts/upstream/Bindings/display/panel/panel-simple.yaml +++ b/dts/upstream/Bindings/display/panel/panel-simple.yaml @@ -184,6 +184,8 @@ properties: - innolux,n156bge-l21 # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel - innolux,zj070na-01p + # JuTouch Technology Co.. 10" JT101TM023 WXGA (1280 x 800) LVDS panel + - jutouch,jt101tm023 # Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel - koe,tx14d24vm1bpa # Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel @@ -268,6 +270,8 @@ properties: - qiaodian,qd43003c0-40 # Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel - qishenglong,gopher2b-lcd + # Raystar Optronics, Inc. RFF500F-AWH-DNN 5.0" TFT 840x480 + - raystar,rff500f-awh-dnn # Rocktech Displays Ltd. RK101II01D-CT 10.1" TFT 1280x800 - rocktech,rk101ii01d-ct # Rocktech Display Ltd. RK070ER9427 800(RGB)x480 TFT LCD panel @@ -276,6 +280,8 @@ properties: - rocktech,rk043fn48h # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel - samsung,ltl101al01 + # Samsung Electronics 10.6" FWXGA (1366x768) TFT LCD panel + - samsung,ltl106al01 # Samsung Electronics 10.1" WSVGA TFT LCD panel - samsung,ltn101nt05 # Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel diff --git a/dts/upstream/Bindings/display/panel/panel-timing.yaml b/dts/upstream/Bindings/display/panel/panel-timing.yaml index aea69b84ca5..8c977445877 100644 --- a/dts/upstream/Bindings/display/panel/panel-timing.yaml +++ b/dts/upstream/Bindings/display/panel/panel-timing.yaml @@ -41,7 +41,6 @@ description: | | | | v | | +-------+----------+-------------------------------------+----------+ - The following is the panel timings shown with time on the x-axis. This matches the timing diagrams often found in data sheets. diff --git a/dts/upstream/Bindings/display/panel/ronbo,rb070d30.yaml b/dts/upstream/Bindings/display/panel/ronbo,rb070d30.yaml index 04f86e0cbac..69403730158 100644 --- a/dts/upstream/Bindings/display/panel/ronbo,rb070d30.yaml +++ b/dts/upstream/Bindings/display/panel/ronbo,rb070d30.yaml @@ -9,6 +9,9 @@ title: Ronbo RB070D30 DSI Display Panel maintainers: - Maxime Ripard +allOf: + - $ref: panel-common.yaml# + properties: compatible: const: ronbo,rb070d30 @@ -20,10 +23,6 @@ properties: description: GPIO used for the power pin maxItems: 1 - reset-gpios: - description: GPIO used for the reset pin - maxItems: 1 - shlr-gpios: description: GPIO used for the shlr pin (horizontal flip) maxItems: 1 @@ -35,10 +34,6 @@ properties: vcc-lcd-supply: description: Power regulator - backlight: - description: Backlight used by the panel - $ref: /schemas/types.yaml#/definitions/phandle - required: - compatible - power-gpios @@ -47,5 +42,6 @@ required: - shlr-gpios - updn-gpios - vcc-lcd-supply + - port -additionalProperties: false +unevaluatedProperties: false diff --git a/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml index ccb574caed2..f1723e91025 100644 --- a/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml +++ b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml @@ -33,6 +33,8 @@ properties: - samsung,atna45dc02 # Samsung 15.6" 3K (2880x1620 pixels) eDP AMOLED panel - samsung,atna56ac03 + # Samsung 16.0" 3K (2880x1800 pixels) eDP AMOLED panel + - samsung,atna60cl08 - const: samsung,atna33xc20 enable-gpios: true diff --git a/dts/upstream/Bindings/display/panel/samsung,lms380kf01.yaml b/dts/upstream/Bindings/display/panel/samsung,lms380kf01.yaml index 7ce8540551f..74c2a617c2f 100644 --- a/dts/upstream/Bindings/display/panel/samsung,lms380kf01.yaml +++ b/dts/upstream/Bindings/display/panel/samsung,lms380kf01.yaml @@ -11,7 +11,7 @@ description: The LMS380KF01 is a 480x800 DPI display panel from Samsung Mobile used with internal or external backlight control. maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: panel-common.yaml# diff --git a/dts/upstream/Bindings/display/panel/samsung,lms397kf04.yaml b/dts/upstream/Bindings/display/panel/samsung,lms397kf04.yaml index 9363032883d..4cecf502a15 100644 --- a/dts/upstream/Bindings/display/panel/samsung,lms397kf04.yaml +++ b/dts/upstream/Bindings/display/panel/samsung,lms397kf04.yaml @@ -10,7 +10,7 @@ description: The datasheet claims this is based around a display controller named DB7430 with a separate backlight controller. maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: panel-common.yaml# diff --git a/dts/upstream/Bindings/display/panel/samsung,s6d16d0.yaml b/dts/upstream/Bindings/display/panel/samsung,s6d16d0.yaml index 2af5bc47323..0872476a8ac 100644 --- a/dts/upstream/Bindings/display/panel/samsung,s6d16d0.yaml +++ b/dts/upstream/Bindings/display/panel/samsung,s6d16d0.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S6D16D0 4" 864x480 AMOLED panel maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: panel-common.yaml# diff --git a/dts/upstream/Bindings/display/panel/samsung,s6e3fc2x01.yaml b/dts/upstream/Bindings/display/panel/samsung,s6e3fc2x01.yaml new file mode 100644 index 00000000000..d48354fb52e --- /dev/null +++ b/dts/upstream/Bindings/display/panel/samsung,s6e3fc2x01.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6e3fc2x01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S6E3FC2X01 AMOLED DDIC + +description: The S6E3FC2X01 is display driver IC with connected panel. + +maintainers: + - David Heidelberg + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + # Samsung 6.41 inch, 1080x2340 pixels, 19.5:9 ratio + - samsung,s6e3fc2x01-ams641rw + - const: samsung,s6e3fc2x01 + + reg: + maxItems: 1 + + reset-gpios: true + + port: true + + vddio-supply: + description: VDD regulator + + vci-supply: + description: VCI regulator + + poc-supply: + description: POC regulator + +required: + - compatible + - reset-gpios + - vddio-supply + - vci-supply + - poc-supply + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01"; + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + vci-supply = <&s2dos05_buck1>; + poc-supply = <&s2dos05_ldo1>; + + te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/dts/upstream/Bindings/display/panel/samsung,sofef00.yaml b/dts/upstream/Bindings/display/panel/samsung,sofef00.yaml new file mode 100644 index 00000000000..eeee3cac72e --- /dev/null +++ b/dts/upstream/Bindings/display/panel/samsung,sofef00.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,sofef00.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SOFEF00 AMOLED DDIC + +description: The SOFEF00 is display driver IC with connected panel. + +maintainers: + - David Heidelberg + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + # Samsung 6.01 inch, 1080x2160 pixels, 18:9 ratio + - samsung,sofef00-ams601nt22 + # Samsung 6.28 inch, 1080x2280 pixels, 19:9 ratio + - samsung,sofef00-ams628nw01 + - const: samsung,sofef00 + + reg: + maxItems: 1 + + poc-supply: + description: POC regulator + + vci-supply: + description: VCI regulator + + vddio-supply: + description: VDD regulator + +required: + - compatible + - reset-gpios + - poc-supply + - vci-supply + - vddio-supply + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,sofef00-ams628nw01", "samsung,sofef00"; + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + vci-supply = <&s2dos05_buck1>; + poc-supply = <&s2dos05_ldo1>; + + te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&panel_active>; + pinctrl-1 = <&panel_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/dts/upstream/Bindings/display/panel/sharp,lq079l1sx01.yaml b/dts/upstream/Bindings/display/panel/sharp,lq079l1sx01.yaml new file mode 100644 index 00000000000..08a35ebbbb3 --- /dev/null +++ b/dts/upstream/Bindings/display/panel/sharp,lq079l1sx01.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,lq079l1sx01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp Microelectronics 7.9" WQXGA TFT LCD panel + +maintainers: + - Svyatoslav Ryhel + +description: > + This panel requires a dual-channel DSI host to operate and it supports + only left-right split mode, where each channel drives the left or right + half of the screen and only video mode. + + Each of the DSI channels controls a separate DSI peripheral. + The peripheral driven by the first link (DSI-LINK1), left one, is + considered the primary peripheral and controls the device. + +allOf: + - $ref: panel-common-dual.yaml# + +properties: + compatible: + const: sharp,lq079l1sx01 + + reg: + maxItems: 1 + + avdd-supply: + description: regulator that supplies the analog voltage + + vddio-supply: + description: regulator that supplies the I/O voltage + + vsp-supply: + description: positive boost supply regulator + + vsn-supply: + description: negative boost supply regulator + + reset-gpios: + maxItems: 1 + + backlight: true + ports: true + +required: + - compatible + - reg + - avdd-supply + - vddio-supply + - ports + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sharp,lq079l1sx01"; + reg = <0>; + + reset-gpios = <&gpio 59 GPIO_ACTIVE_LOW>; + + avdd-supply = <&avdd_lcd>; + vddio-supply = <&vdd_lcd_io>; + vsp-supply = <&vsp_5v5_lcd>; + vsn-supply = <&vsn_5v5_lcd>; + + backlight = <&backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_in1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/display/panel/sony,acx424akp.yaml b/dts/upstream/Bindings/display/panel/sony,acx424akp.yaml index fd778a20f76..64fa086730b 100644 --- a/dts/upstream/Bindings/display/panel/sony,acx424akp.yaml +++ b/dts/upstream/Bindings/display/panel/sony,acx424akp.yaml @@ -12,7 +12,7 @@ description: The Sony ACX424AKP and ACX424AKM are panels built around AKP. maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: panel-common.yaml# diff --git a/dts/upstream/Bindings/display/panel/synaptics,td4300-panel.yaml b/dts/upstream/Bindings/display/panel/synaptics,td4300-panel.yaml new file mode 100644 index 00000000000..152d9436713 --- /dev/null +++ b/dts/upstream/Bindings/display/panel/synaptics,td4300-panel.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/synaptics,td4300-panel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synaptics TDDI Display Panel Controller + +maintainers: + - Kaustabh Chakraborty + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + enum: + - syna,td4101-panel + - syna,td4300-panel + + reg: + maxItems: 1 + + vio-supply: + description: core I/O voltage supply + + vsn-supply: + description: negative voltage supply for analog circuits + + vsp-supply: + description: positive voltage supply for analog circuits + + backlight-gpios: + maxItems: 1 + description: backlight enable GPIO + + reset-gpios: true + width-mm: true + height-mm: true + panel-timing: true + +required: + - compatible + - reg + - width-mm + - height-mm + - panel-timing + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "syna,td4300-panel"; + reg = <0>; + + vio-supply = <&panel_vio_reg>; + vsn-supply = <&panel_vsn_reg>; + vsp-supply = <&panel_vsp_reg>; + + backlight-gpios = <&gpd3 5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpd3 4 GPIO_ACTIVE_LOW>; + + width-mm = <68>; + height-mm = <121>; + + panel-timing { + clock-frequency = <144389520>; + + hactive = <1080>; + hsync-len = <4>; + hfront-porch = <120>; + hback-porch = <32>; + + vactive = <1920>; + vsync-len = <2>; + vfront-porch = <21>; + vback-porch = <4>; + }; + }; + }; + +... diff --git a/dts/upstream/Bindings/display/panel/ti,nspire.yaml b/dts/upstream/Bindings/display/panel/ti,nspire.yaml index 5c5a3b519e3..fc722f706ad 100644 --- a/dts/upstream/Bindings/display/panel/ti,nspire.yaml +++ b/dts/upstream/Bindings/display/panel/ti,nspire.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments NSPIRE Display Panels maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: panel-common.yaml# diff --git a/dts/upstream/Bindings/display/panel/tpo,tpg110.yaml b/dts/upstream/Bindings/display/panel/tpo,tpg110.yaml index 59a373728e6..e5f3108cde5 100644 --- a/dts/upstream/Bindings/display/panel/tpo,tpg110.yaml +++ b/dts/upstream/Bindings/display/panel/tpo,tpg110.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TPO TPG110 Panel maintainers: - - Linus Walleij + - Linus Walleij - Thierry Reding description: |+ @@ -38,7 +38,6 @@ description: |+ The serial protocol has line names that resemble I2C but the protocol is not I2C but 3WIRE SPI. - allOf: - $ref: panel-common.yaml# - $ref: /schemas/spi/spi-peripheral-props.yaml# diff --git a/dts/upstream/Bindings/display/renesas,rzg2l-du.yaml b/dts/upstream/Bindings/display/renesas,rzg2l-du.yaml index 1e32d14b6ed..2cc66dcef87 100644 --- a/dts/upstream/Bindings/display/renesas,rzg2l-du.yaml +++ b/dts/upstream/Bindings/display/renesas,rzg2l-du.yaml @@ -25,6 +25,9 @@ properties: - enum: - renesas,r9a07g054-du # RZ/V2L - const: renesas,r9a07g044-du # RZ/G2L fallback + - items: + - const: renesas,r9a09g056-du # RZ/V2N + - const: renesas,r9a09g057-du # RZ/V2H(P) fallback reg: maxItems: 1 diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,dw-dp.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,dw-dp.yaml index a8a00871799..6345f0132d4 100644 --- a/dts/upstream/Bindings/display/rockchip/rockchip,dw-dp.yaml +++ b/dts/upstream/Bindings/display/rockchip/rockchip,dw-dp.yaml @@ -125,7 +125,6 @@ examples: power-domains = <&power RK3588_PD_VO0>; #sound-dai-cells = <0>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index c59df3c1a3f..632b48bfabb 100644 --- a/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -17,6 +17,7 @@ properties: - rockchip,px30-mipi-dsi - rockchip,rk3128-mipi-dsi - rockchip,rk3288-mipi-dsi + - rockchip,rk3368-mipi-dsi - rockchip,rk3399-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi @@ -73,6 +74,7 @@ allOf: enum: - rockchip,px30-mipi-dsi - rockchip,rk3128-mipi-dsi + - rockchip,rk3368-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml index 96b4b088eeb..d649808c59d 100644 --- a/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml +++ b/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml @@ -113,6 +113,14 @@ properties: description: Additional HDMI QP related data is accessed through VO GRF regs. + frl-enable-gpios: + description: + Optional GPIO line to be asserted when operating in HDMI 2.1 FRL mode and + deasserted for HDMI 1.4/2.0 TMDS. It can be used to control external + voltage bias for HDMI data lines. When not present the HDMI encoder will + operate in TMDS mode only. + maxItems: 1 + required: - compatible - reg @@ -132,8 +140,10 @@ unevaluatedProperties: false examples: - | #include + #include #include #include + #include #include #include @@ -164,6 +174,7 @@ examples: rockchip,grf = <&sys_grf>; rockchip,vo-grf = <&vo1_grf>; #sound-dai-cells = <0>; + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; ports { #address-cells = <1>; diff --git a/dts/upstream/Bindings/display/simple-framebuffer.yaml b/dts/upstream/Bindings/display/simple-framebuffer.yaml index 296500f9da0..45ffdebc9d8 100644 --- a/dts/upstream/Bindings/display/simple-framebuffer.yaml +++ b/dts/upstream/Bindings/display/simple-framebuffer.yaml @@ -181,7 +181,6 @@ allOf: required: - amlogic,pipeline - additionalProperties: false examples: diff --git a/dts/upstream/Bindings/display/ste,mcde.yaml b/dts/upstream/Bindings/display/ste,mcde.yaml index 564ea845c82..7a12d0b817e 100644 --- a/dts/upstream/Bindings/display/ste,mcde.yaml +++ b/dts/upstream/Bindings/display/ste,mcde.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST-Ericsson Multi Channel Display Engine MCDE maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/display/tegra/nvidia,tegra114-tsec.yaml b/dts/upstream/Bindings/display/tegra/nvidia,tegra114-tsec.yaml new file mode 100644 index 00000000000..2c4d519a1bb --- /dev/null +++ b/dts/upstream/Bindings/display/tegra/nvidia,tegra114-tsec.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Security co-processor + +maintainers: + - Svyatoslav Ryhel + - Thierry Reding + +description: Tegra Security co-processor, an embedded security processor used + mainly to manage the HDCP encryption and keys on the HDMI link. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra114-tsec + - nvidia,tegra124-tsec + - nvidia,tegra210-tsec + + - items: + - const: nvidia,tegra132-tsec + - const: nvidia,tegra124-tsec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + iommus: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + +examples: + - | + #include + #include + + tsec@54500000 { + compatible = "nvidia,tegra114-tsec"; + reg = <0x54500000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_TSEC>; + resets = <&tegra_car TEGRA114_CLK_TSEC>; + }; diff --git a/dts/upstream/Bindings/display/tegra/nvidia,tegra20-csi.yaml b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-csi.yaml new file mode 100644 index 00000000000..a1aea959076 --- /dev/null +++ b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-csi.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 CSI controller + +maintainers: + - Svyatoslav Ryhel + +properties: + compatible: + enum: + - nvidia,tegra20-csi + - nvidia,tegra30-csi + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: module clock + - description: PAD A clock + - description: PAD B clock + + clock-names: + items: + - const: csi + - const: csia-pad + - const: csib-pad + + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + + power-domains: + maxItems: 1 + + "#nvidia,mipi-calibrate-cells": + description: + The number of cells in a MIPI calibration specifier. Should be 1. + The single cell specifies an id of the pad that need to be + calibrated for a given device. Valid pad ids for receiver would be + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@[0-1]$": + type: object + description: channel 0 represents CSI-A and 1 represents CSI-B + additionalProperties: false + + properties: + reg: + maximum: 1 + + nvidia,mipi-calibrate: + description: Should contain a phandle and a specifier specifying + which pad is used by this CSI channel and needs to be calibrated. + $ref: /schemas/types.yaml#/definitions/phandle-array + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: port receiving the video stream from the sensor + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: port sending the video stream to the VI + + required: + - reg + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-csi + then: + properties: + clocks: + maxItems: 1 + + clock-names: false + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-csi + then: + properties: + clocks: + minItems: 3 + + clock-names: + minItems: 3 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - power-domains + - "#address-cells" + - "#size-cells" + +# see nvidia,tegra20-vi.yaml for an example diff --git a/dts/upstream/Bindings/display/tegra/nvidia,tegra20-epp.yaml b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-epp.yaml index 3c095a5491f..334f5531b24 100644 --- a/dts/upstream/Bindings/display/tegra/nvidia,tegra20-epp.yaml +++ b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-epp.yaml @@ -15,10 +15,16 @@ properties: pattern: "^epp@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-epp - - nvidia,tegra30-epp - - nvidia,tegra114-epp + oneOf: + - enum: + - nvidia,tegra20-epp + - nvidia,tegra30-epp + - nvidia,tegra114-epp + - nvidia,tegra124-epp + + - items: + - const: nvidia,tegra132-epp + - const: nvidia,tegra124-epp reg: maxItems: 1 diff --git a/dts/upstream/Bindings/display/tegra/nvidia,tegra20-isp.yaml b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-isp.yaml index 3bc3b22e98e..ee25b5e6f1a 100644 --- a/dts/upstream/Bindings/display/tegra/nvidia,tegra20-isp.yaml +++ b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-isp.yaml @@ -12,10 +12,17 @@ maintainers: properties: compatible: - enum: - - nvidia,tegra20-isp - - nvidia,tegra30-isp - - nvidia,tegra210-isp + oneOf: + - enum: + - nvidia,tegra20-isp + - nvidia,tegra30-isp + - nvidia,tegra114-isp + - nvidia,tegra124-isp + - nvidia,tegra210-isp + + - items: + - const: nvidia,tegra132-isp + - const: nvidia,tegra124-isp reg: maxItems: 1 diff --git a/dts/upstream/Bindings/display/tegra/nvidia,tegra20-mpe.yaml b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-mpe.yaml index 2cd3e60cd0a..36b76fa8f52 100644 --- a/dts/upstream/Bindings/display/tegra/nvidia,tegra20-mpe.yaml +++ b/dts/upstream/Bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -12,13 +12,21 @@ maintainers: properties: $nodename: - pattern: "^mpe@[0-9a-f]+$" + oneOf: + - pattern: "^mpe@[0-9a-f]+$" + - pattern: "^msenc@[0-9a-f]+$" compatible: - enum: - - nvidia,tegra20-mpe - - nvidia,tegra30-mpe - - nvidia,tegra114-mpe + oneOf: + - enum: + - nvidia,tegra20-mpe + - nvidia,tegra30-mpe + - nvidia,tegra114-msenc + - nvidia,tegra124-msenc + + - items: + - const: nvidia,tegra132-msenc + - const: nvidia,tegra124-msenc reg: maxItems: 1 diff --git a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml index 361e9cae689..38fcee91211 100644 --- a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml +++ b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml @@ -84,8 +84,7 @@ properties: maxItems: 1 description: phandle to the associated power domain - dma-coherent: - type: boolean + dma-coherent: true ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/upstream/Bindings/display/ti/ti,j721e-dss.yaml b/dts/upstream/Bindings/display/ti/ti,j721e-dss.yaml index fad7cba58d3..65ae8a1c399 100644 --- a/dts/upstream/Bindings/display/ti/ti,j721e-dss.yaml +++ b/dts/upstream/Bindings/display/ti/ti,j721e-dss.yaml @@ -103,8 +103,7 @@ properties: maxItems: 1 description: phandle to the associated power domain - dma-coherent: - type: boolean + dma-coherent: true ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/upstream/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/dts/upstream/Bindings/dma/allwinner,sun50i-a64-dma.yaml index 0f2501f72cc..c3e14eb6cff 100644 --- a/dts/upstream/Bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/dts/upstream/Bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -29,7 +29,10 @@ properties: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma - items: - - const: allwinner,sun50i-h616-dma + - enum: + - allwinner,sun50i-h616-dma + - allwinner,sun55i-a523-dma + - allwinner,sun55i-a523-mcu-dma - const: allwinner,sun50i-a100-dma reg: diff --git a/dts/upstream/Bindings/dma/apm,xgene-storm-dma.yaml b/dts/upstream/Bindings/dma/apm,xgene-storm-dma.yaml new file mode 100644 index 00000000000..9ca5f784878 --- /dev/null +++ b/dts/upstream/Bindings/dma/apm,xgene-storm-dma.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/apm,xgene-storm-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene Storm SoC DMA + +maintainers: + - Khuong Dinh + +properties: + compatible: + const: apm,xgene-storm-dma + + reg: + items: + - description: DMA control and status registers + - description: Descriptor ring control and status registers + - description: Descriptor ring command registers + - description: SoC efuse registers + + interrupts: + items: + - description: DMA error reporting interrupt + - description: DMA channel 0 completion interrupt + - description: DMA channel 1 completion interrupt + - description: DMA channel 2 completion interrupt + - description: DMA channel 3 completion interrupt + + clocks: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + dma@1f270000 { + compatible = "apm,xgene-storm-dma"; + reg = <0x1f270000 0x10000>, + <0x1f200000 0x10000>, + <0x1b000000 0x400000>, + <0x1054a000 0x100>; + interrupts = <0x0 0x82 0x4>, + <0x0 0xb8 0x4>, + <0x0 0xb9 0x4>, + <0x0 0xba 0x4>, + <0x0 0xbb 0x4>; + dma-coherent; + clocks = <&dmaclk 0>; + }; diff --git a/dts/upstream/Bindings/dma/apm-xgene-dma.txt b/dts/upstream/Bindings/dma/apm-xgene-dma.txt deleted file mode 100644 index c53e0b08032..00000000000 --- a/dts/upstream/Bindings/dma/apm-xgene-dma.txt +++ /dev/null @@ -1,47 +0,0 @@ -Applied Micro X-Gene SoC DMA nodes - -DMA nodes are defined to describe on-chip DMA interfaces in -APM X-Gene SoC. - -Required properties for DMA interfaces: -- compatible: Should be "apm,xgene-dma". -- device_type: set to "dma". -- reg: Address and length of the register set for the device. - It contains the information of registers in the following order: - 1st - DMA control and status register address space. - 2nd - Descriptor ring control and status register address space. - 3rd - Descriptor ring command register address space. - 4th - Soc efuse register address space. -- interrupts: DMA has 5 interrupts sources. 1st interrupt is - DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts - are completion interrupts for each DMA channels. -- clocks: Reference to the clock entry. - -Optional properties: -- dma-coherent : Present if dma operations are coherent - -Example: - dmaclk: dmaclk@1f27c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f27c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "dmaclk"; - }; - - dma: dma@1f270000 { - compatible = "apm,xgene-storm-dma"; - device_type = "dma"; - reg = <0x0 0x1f270000 0x0 0x10000>, - <0x0 0x1f200000 0x0 0x10000>, - <0x0 0x1b000000 0x0 0x400000>, - <0x0 0x1054a000 0x0 0x100>; - interrupts = <0x0 0x82 0x4>, - <0x0 0xb8 0x4>, - <0x0 0xb9 0x4>, - <0x0 0xba 0x4>, - <0x0 0xbb 0x4>; - dma-coherent; - clocks = <&dmaclk 0>; - }; diff --git a/dts/upstream/Bindings/dma/snps,dma-spear1340.yaml b/dts/upstream/Bindings/dma/snps,dma-spear1340.yaml index c21a4f073f6..18c0a7c18bc 100644 --- a/dts/upstream/Bindings/dma/snps,dma-spear1340.yaml +++ b/dts/upstream/Bindings/dma/snps,dma-spear1340.yaml @@ -22,7 +22,6 @@ properties: - renesas,r9a06g032-dma - const: renesas,rzn1-dma - "#dma-cells": minimum: 3 maximum: 4 diff --git a/dts/upstream/Bindings/dma/snps,dw-axi-dmac.yaml b/dts/upstream/Bindings/dma/snps,dw-axi-dmac.yaml index 935735a59af..a393a33c890 100644 --- a/dts/upstream/Bindings/dma/snps,dw-axi-dmac.yaml +++ b/dts/upstream/Bindings/dma/snps,dw-axi-dmac.yaml @@ -42,6 +42,9 @@ properties: minItems: 1 maxItems: 8 + iommus: + maxItems: 1 + clocks: items: - description: Bus Clock diff --git a/dts/upstream/Bindings/dma/stericsson,dma40.yaml b/dts/upstream/Bindings/dma/stericsson,dma40.yaml index 7b94d24d5ef..607da11e7ba 100644 --- a/dts/upstream/Bindings/dma/stericsson,dma40.yaml +++ b/dts/upstream/Bindings/dma/stericsson,dma40.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST-Ericsson DMA40 DMA Engine maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: dma-controller.yaml# @@ -120,7 +120,6 @@ properties: - description: LCPA memory base, deprecated, use eSRAM pool instead deprecated: true - reg-names: oneOf: - items: diff --git a/dts/upstream/Bindings/dma/stm32/st,stm32-dma.yaml b/dts/upstream/Bindings/dma/stm32/st,stm32-dma.yaml index 11a289f1d50..59890335419 100644 --- a/dts/upstream/Bindings/dma/stm32/st,stm32-dma.yaml +++ b/dts/upstream/Bindings/dma/stm32/st,stm32-dma.yaml @@ -48,7 +48,6 @@ description: | by transfer completion. This must only be used on channels managing transfers for STM32 USART/UART. - maintainers: - Amelie Delaunay diff --git a/dts/upstream/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/dts/upstream/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index b5399c65a73..2da86037ad7 100644 --- a/dts/upstream/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/dts/upstream/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -59,8 +59,7 @@ properties: power-domains: maxItems: 1 - dma-coherent: - description: present if dma operations are coherent + dma-coherent: true required: - "#dma-cells" diff --git a/dts/upstream/Bindings/dts-coding-style.rst b/dts/upstream/Bindings/dts-coding-style.rst index 202acac0507..4a02ea60cbb 100644 --- a/dts/upstream/Bindings/dts-coding-style.rst +++ b/dts/upstream/Bindings/dts-coding-style.rst @@ -120,7 +120,8 @@ The following order of properties in device nodes is preferred: 4. Standard/common properties (defined by common bindings, e.g. without vendor-prefixes) 5. Vendor-specific properties -6. "status" (if applicable) +6. "status" (if applicable), preceded by a blank line if there is content + before the property 7. Child nodes, where each node is preceded with a blank line The "status" property is by default "okay", thus it can be omitted. @@ -150,6 +151,7 @@ Example:: #address-cells = <1>; #size-cells = <1>; vendor,custom-property = <2>; + status = "disabled"; child_node: child-class@100 { @@ -165,6 +167,7 @@ Example:: vdd-1v8-supply = <&board_vreg4>; vdd-3v3-supply = <&board_vreg2>; vdd-12v-supply = <&board_vreg3>; + status = "okay"; } diff --git a/dts/upstream/Bindings/edac/altr,socfpga-ecc-manager.yaml b/dts/upstream/Bindings/edac/altr,socfpga-ecc-manager.yaml index 3d787dea0f1..136e8fccd42 100644 --- a/dts/upstream/Bindings/edac/altr,socfpga-ecc-manager.yaml +++ b/dts/upstream/Bindings/edac/altr,socfpga-ecc-manager.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera SoCFPGA ECC Manager maintainers: - - Matthew Gerlach + - Niravkumar L Rabara description: This binding describes the device tree nodes required for the Altera SoCFPGA diff --git a/dts/upstream/Bindings/edac/apm,xgene-edac.yaml b/dts/upstream/Bindings/edac/apm,xgene-edac.yaml index 9afc78254cc..9637df7af3c 100644 --- a/dts/upstream/Bindings/edac/apm,xgene-edac.yaml +++ b/dts/upstream/Bindings/edac/apm,xgene-edac.yaml @@ -97,7 +97,6 @@ patternProperties: - reg - memory-controller - '^edacpmd@': description: PMD subnode type: object diff --git a/dts/upstream/Bindings/eeprom/at24.yaml b/dts/upstream/Bindings/eeprom/at24.yaml index 50af7ccf6e2..c2128263478 100644 --- a/dts/upstream/Bindings/eeprom/at24.yaml +++ b/dts/upstream/Bindings/eeprom/at24.yaml @@ -131,6 +131,7 @@ properties: - const: atmel,24c32 - items: - enum: + - belling,bl24s64 - onnn,n24s64b - puya,p24c64f - const: atmel,24c64 diff --git a/dts/upstream/Bindings/eeprom/at25.yaml b/dts/upstream/Bindings/eeprom/at25.yaml index 00e0f07b44f..e1599ce1091 100644 --- a/dts/upstream/Bindings/eeprom/at25.yaml +++ b/dts/upstream/Bindings/eeprom/at25.yaml @@ -25,6 +25,7 @@ properties: oneOf: - items: - enum: + - anvo,anv32c81w - anvo,anv32e61w - atmel,at25256B - fujitsu,mb85rs1mt diff --git a/dts/upstream/Bindings/embedded-controller/traverse,ten64-controller.yaml b/dts/upstream/Bindings/embedded-controller/traverse,ten64-controller.yaml new file mode 100644 index 00000000000..08d02c4df87 --- /dev/null +++ b/dts/upstream/Bindings/embedded-controller/traverse,ten64-controller.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/traverse,ten64-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Traverse Ten64 board microcontroller + +maintainers: + - Mathew McBride + +description: | + The board microcontroller on the Ten64 board family is responsible for + management of power sources on the board, as well as signalling the SoC + to power on and reset. + +properties: + compatible: + const: traverse,ten64-controller + + reg: + const: 0x7e + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + board-controller@7e { + compatible = "traverse,ten64-controller"; + reg = <0x7e>; + }; + }; diff --git a/dts/upstream/Bindings/extcon/fcs,fsa880.yaml b/dts/upstream/Bindings/extcon/fcs,fsa880.yaml index ef6a246a133..bff3fd5f7f4 100644 --- a/dts/upstream/Bindings/extcon/fcs,fsa880.yaml +++ b/dts/upstream/Bindings/extcon/fcs,fsa880.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Fairchild Semiconductor FSA880, FSA9480 and compatibles maintainers: - - Linus Walleij + - Linus Walleij description: The FSA880 and FSA9480 are USB port accessory detectors and switches. diff --git a/dts/upstream/Bindings/firmware/google,gs101-acpm-ipc.yaml b/dts/upstream/Bindings/firmware/google,gs101-acpm-ipc.yaml index 9785aac3b5f..d3bca6088d1 100644 --- a/dts/upstream/Bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/dts/upstream/Bindings/firmware/google,gs101-acpm-ipc.yaml @@ -24,6 +24,15 @@ properties: compatible: const: google,gs101-acpm-ipc + "#clock-cells": + const: 1 + description: + Clocks that are variable and index based. These clocks don't provide + an entire range of values between the limits but only discrete points + within the range. The firmware also manages the voltage scaling + appropriately with the clock scaling. The argument is the ID of the + clock contained by the firmware messages. + mboxes: maxItems: 1 @@ -45,6 +54,7 @@ properties: required: - compatible + - "#clock-cells" - mboxes - shmem @@ -56,6 +66,7 @@ examples: power-management { compatible = "google,gs101-acpm-ipc"; + #clock-cells = <1>; mboxes = <&ap2apm_mailbox>; shmem = <&apm_sram>; diff --git a/dts/upstream/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/dts/upstream/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml index 50f1f08744a..4d66ef48352 100644 --- a/dts/upstream/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml +++ b/dts/upstream/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx Network Processing Engine maintainers: - - Linus Walleij + - Linus Walleij description: | On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small diff --git a/dts/upstream/Bindings/firmware/intel,stratix10-svc.yaml b/dts/upstream/Bindings/firmware/intel,stratix10-svc.yaml index fac1e955852..b42cfa78b28 100644 --- a/dts/upstream/Bindings/firmware/intel,stratix10-svc.yaml +++ b/dts/upstream/Bindings/firmware/intel,stratix10-svc.yaml @@ -34,6 +34,7 @@ properties: enum: - intel,stratix10-svc - intel,agilex-svc + - intel,agilex5-svc method: description: | @@ -54,6 +55,9 @@ properties: reserved memory region for the service layer driver to communicate with the secure device manager. + iommus: + maxItems: 1 + fpga-mgr: $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml description: Optional child node for fpga manager to perform fabric configuration. @@ -63,6 +67,17 @@ required: - method - memory-region +allOf: + - if: + properties: + compatible: + contains: + enum: + - intel,agilex5-svc + then: + required: + - iommus + additionalProperties: false examples: diff --git a/dts/upstream/Bindings/firmware/qcom,scm.yaml b/dts/upstream/Bindings/firmware/qcom,scm.yaml index ef97faac7e4..d66459f1d84 100644 --- a/dts/upstream/Bindings/firmware/qcom,scm.yaml +++ b/dts/upstream/Bindings/firmware/qcom,scm.yaml @@ -23,6 +23,7 @@ properties: - enum: - qcom,scm-apq8064 - qcom,scm-apq8084 + - qcom,scm-glymur - qcom,scm-ipq4019 - qcom,scm-ipq5018 - qcom,scm-ipq5332 @@ -31,6 +32,7 @@ properties: - qcom,scm-ipq806x - qcom,scm-ipq8074 - qcom,scm-ipq9574 + - qcom,scm-kaanapali - qcom,scm-mdm9607 - qcom,scm-milos - qcom,scm-msm8226 @@ -202,6 +204,7 @@ allOf: compatible: contains: enum: + - qcom,scm-kaanapali - qcom,scm-milos - qcom,scm-sm8450 - qcom,scm-sm8550 diff --git a/dts/upstream/Bindings/firmware/qemu,fw-cfg-mmio.yaml b/dts/upstream/Bindings/firmware/qemu,fw-cfg-mmio.yaml index 3faae323666..c6fc1d6e25d 100644 --- a/dts/upstream/Bindings/firmware/qemu,fw-cfg-mmio.yaml +++ b/dts/upstream/Bindings/firmware/qemu,fw-cfg-mmio.yaml @@ -23,7 +23,6 @@ description: | The authoritative guest-side hardware interface documentation to the fw_cfg device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. - properties: compatible: const: qemu,fw-cfg-mmio diff --git a/dts/upstream/Bindings/fpga/fpga-region.yaml b/dts/upstream/Bindings/fpga/fpga-region.yaml index 7d2d3b7aa4b..55acf0ecfa3 100644 --- a/dts/upstream/Bindings/fpga/fpga-region.yaml +++ b/dts/upstream/Bindings/fpga/fpga-region.yaml @@ -18,7 +18,6 @@ description: | - Supported Use Models - Constraints - Introduction ============ @@ -31,7 +30,6 @@ description: | document isn't a replacement for any manufacturers specifications for FPGA usage. - Terminology =========== @@ -108,7 +106,6 @@ description: | a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be reprogrammed independently while the rest of the system continues to function. - Sequence ======== @@ -124,7 +121,6 @@ description: | When the overlay is removed, the child nodes will be removed and the FPGA Region will disable the bridges. - FPGA Region =========== @@ -170,7 +166,6 @@ description: | hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges within the static image of the FPGA. - Supported Use Models ==================== @@ -215,9 +210,9 @@ description: | FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. -- - [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf + [1] https://www.intel.com/programmable/technical-pdfs/683404.pdf [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf - [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf + [3] https://docs.amd.com/v/u/en-US/ug702 properties: $nodename: diff --git a/dts/upstream/Bindings/fpga/lattice,ice40-fpga-mgr.yaml b/dts/upstream/Bindings/fpga/lattice,ice40-fpga-mgr.yaml new file mode 100644 index 00000000000..5121c612078 --- /dev/null +++ b/dts/upstream/Bindings/fpga/lattice,ice40-fpga-mgr.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/lattice,ice40-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lattice iCE40 FPGA Manager + +maintainers: + - Joel Holdsworth + +properties: + compatible: + const: lattice,ice40-fpga-mgr + + reg: + maxItems: 1 + + spi-max-frequency: + minimum: 1000000 + maximum: 25000000 + + cdone-gpios: + maxItems: 1 + description: GPIO input connected to CDONE pin + + reset-gpios: + maxItems: 1 + description: + Active-low GPIO output connected to CRESET_B pin. Note that unless the + GPIO is held low during startup, the FPGA will enter Master SPI mode and + drive SCK with a clock signal potentially jamming other devices on the bus + until the firmware is loaded. + +required: + - compatible + - reg + - spi-max-frequency + - cdone-gpios + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + fpga@0 { + compatible = "lattice,ice40-fpga-mgr"; + reg = <0>; + spi-max-frequency = <1000000>; + cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/dts/upstream/Bindings/fpga/lattice-ice40-fpga-mgr.txt b/dts/upstream/Bindings/fpga/lattice-ice40-fpga-mgr.txt deleted file mode 100644 index 4dc412437b0..00000000000 --- a/dts/upstream/Bindings/fpga/lattice-ice40-fpga-mgr.txt +++ /dev/null @@ -1,21 +0,0 @@ -Lattice iCE40 FPGA Manager - -Required properties: -- compatible: Should contain "lattice,ice40-fpga-mgr" -- reg: SPI chip select -- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) -- cdone-gpios: GPIO input connected to CDONE pin -- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note - that unless the GPIO is held low during startup, the - FPGA will enter Master SPI mode and drive SCK with a - clock signal potentially jamming other devices on the - bus until the firmware is loaded. - -Example: - fpga: fpga@0 { - compatible = "lattice,ice40-fpga-mgr"; - reg = <0>; - spi-max-frequency = <1000000>; - cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; diff --git a/dts/upstream/Bindings/gnss/brcm,bcm4751.yaml b/dts/upstream/Bindings/gnss/brcm,bcm4751.yaml index 08916608949..c34b86bb7f6 100644 --- a/dts/upstream/Bindings/gnss/brcm,bcm4751.yaml +++ b/dts/upstream/Bindings/gnss/brcm,bcm4751.yaml @@ -8,7 +8,7 @@ title: Broadcom BCM4751 family GNSS Receiver maintainers: - Johan Hovold - - Linus Walleij + - Linus Walleij description: Broadcom GPS chips can be used over the UART or I2C bus. The UART diff --git a/dts/upstream/Bindings/gnss/gnss-common.yaml b/dts/upstream/Bindings/gnss/gnss-common.yaml index d4430d2d685..354c0524089 100644 --- a/dts/upstream/Bindings/gnss/gnss-common.yaml +++ b/dts/upstream/Bindings/gnss/gnss-common.yaml @@ -31,8 +31,7 @@ properties: maxItems: 1 timepulse-gpios: - description: When a timepulse is provided to the GNSS device using a - GPIO line, this is used. + description: Timepulse signal maxItems: 1 additionalProperties: true diff --git a/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml b/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml index c0c2bfaa606..b349b7bc041 100644 --- a/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml +++ b/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gnss/u-blox,neo-6m.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: U-blox GNSS Receiver +title: u-blox GNSS receiver allOf: - $ref: gnss-common.yaml# @@ -14,7 +14,7 @@ maintainers: - Johan Hovold description: > - The U-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces. + The u-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces. properties: compatible: @@ -36,6 +36,9 @@ properties: reset-gpios: maxItems: 1 + safeboot-gpios: + maxItems: 1 + vcc-supply: description: > Main voltage regulator @@ -64,6 +67,7 @@ examples: compatible = "u-blox,neo-8"; v-bckp-supply = <&gnss_v_bckp_reg>; vcc-supply = <&gnss_vcc_reg>; - reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + safeboot-gpios = <&gpio 2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; }; }; diff --git a/dts/upstream/Bindings/gpio/brcm,xgs-iproc-gpio.yaml b/dts/upstream/Bindings/gpio/brcm,xgs-iproc-gpio.yaml index c213cb9ddb9..5cfefbbea6c 100644 --- a/dts/upstream/Bindings/gpio/brcm,xgs-iproc-gpio.yaml +++ b/dts/upstream/Bindings/gpio/brcm,xgs-iproc-gpio.yaml @@ -66,5 +66,4 @@ examples: interrupts = ; }; - ... diff --git a/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml b/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml index ab35bcf9810..23410aeca30 100644 --- a/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml +++ b/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml @@ -22,7 +22,6 @@ description: | ___ ________ chip select# |___________________| - maintainers: - Maxime Ripard diff --git a/dts/upstream/Bindings/gpio/faraday,ftgpio010.yaml b/dts/upstream/Bindings/gpio/faraday,ftgpio010.yaml index 640da5b9b0c..3a6a47f1298 100644 --- a/dts/upstream/Bindings/gpio/faraday,ftgpio010.yaml +++ b/dts/upstream/Bindings/gpio/faraday,ftgpio010.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FTGPIO010 GPIO Controller maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/gpio/gpio-consumer-common.yaml b/dts/upstream/Bindings/gpio/gpio-consumer-common.yaml index 40d0be31e20..fa0148758b4 100644 --- a/dts/upstream/Bindings/gpio/gpio-consumer-common.yaml +++ b/dts/upstream/Bindings/gpio/gpio-consumer-common.yaml @@ -8,7 +8,7 @@ title: Common GPIO lines maintainers: - Bartosz Golaszewski - - Linus Walleij + - Linus Walleij description: Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs diff --git a/dts/upstream/Bindings/gpio/gpio-ep9301.yaml b/dts/upstream/Bindings/gpio/gpio-ep9301.yaml index 3a1079d6ee2..ebdb7ee5b79 100644 --- a/dts/upstream/Bindings/gpio/gpio-ep9301.yaml +++ b/dts/upstream/Bindings/gpio/gpio-ep9301.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: EP93xx GPIO controller maintainers: - - Linus Walleij + - Linus Walleij - Bartosz Golaszewski - Nikita Shubin diff --git a/dts/upstream/Bindings/gpio/gpio-mmio.yaml b/dts/upstream/Bindings/gpio/gpio-mmio.yaml index b4d55bf6a28..ee5d5d25ae8 100644 --- a/dts/upstream/Bindings/gpio/gpio-mmio.yaml +++ b/dts/upstream/Bindings/gpio/gpio-mmio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic MMIO GPIO maintainers: - - Linus Walleij + - Linus Walleij - Bartosz Golaszewski description: diff --git a/dts/upstream/Bindings/gpio/gpio-mxs.yaml b/dts/upstream/Bindings/gpio/gpio-mxs.yaml index aaf97124803..fed1b06495a 100644 --- a/dts/upstream/Bindings/gpio/gpio-mxs.yaml +++ b/dts/upstream/Bindings/gpio/gpio-mxs.yaml @@ -28,6 +28,7 @@ properties: '#address-cells': const: 1 + '#size-cells': const: 0 @@ -35,7 +36,7 @@ properties: maxItems: 1 patternProperties: - "^(?!gpio@)[^@]+@[0-9]+$": + '^(?!gpio@)[^@]+@[0-9]+$': type: object properties: fsl,pinmux-ids: @@ -93,7 +94,7 @@ patternProperties: additionalProperties: false - "^gpio@[0-9]+$": + '^gpio@[0-9]+$': type: object properties: compatible: @@ -110,10 +111,10 @@ patternProperties: interrupt-controller: true - "#interrupt-cells": + '#interrupt-cells': const: 2 - "#gpio-cells": + '#gpio-cells': const: 2 gpio-controller: true @@ -123,8 +124,8 @@ patternProperties: - reg - interrupts - interrupt-controller - - "#interrupt-cells" - - "#gpio-cells" + - '#interrupt-cells' + - '#gpio-cells' - gpio-controller additionalProperties: false diff --git a/dts/upstream/Bindings/gpio/intel,ixp4xx-gpio.yaml b/dts/upstream/Bindings/gpio/intel,ixp4xx-gpio.yaml index bfcb1f364c3..2a980c0ed86 100644 --- a/dts/upstream/Bindings/gpio/intel,ixp4xx-gpio.yaml +++ b/dts/upstream/Bindings/gpio/intel,ixp4xx-gpio.yaml @@ -22,7 +22,7 @@ description: | and this can be enabled by a special flag. maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/gpio/microchip,mpfs-gpio.yaml b/dts/upstream/Bindings/gpio/microchip,mpfs-gpio.yaml index d78da7dd2a5..184432d24ea 100644 --- a/dts/upstream/Bindings/gpio/microchip,mpfs-gpio.yaml +++ b/dts/upstream/Bindings/gpio/microchip,mpfs-gpio.yaml @@ -11,7 +11,10 @@ maintainers: properties: compatible: - items: + oneOf: + - items: + - const: microchip,pic64gx-gpio + - const: microchip,mpfs-gpio - enum: - microchip,mpfs-gpio - microchip,coregpio-rtl-v3 diff --git a/dts/upstream/Bindings/gpio/mrvl-gpio.yaml b/dts/upstream/Bindings/gpio/mrvl-gpio.yaml index 65155bb701a..7f420b9c048 100644 --- a/dts/upstream/Bindings/gpio/mrvl-gpio.yaml +++ b/dts/upstream/Bindings/gpio/mrvl-gpio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Marvell PXA GPIO controller maintainers: - - Linus Walleij + - Linus Walleij - Bartosz Golaszewski - Rob Herring diff --git a/dts/upstream/Bindings/gpio/pl061-gpio.yaml b/dts/upstream/Bindings/gpio/pl061-gpio.yaml index c51e10680c0..4d970e55104 100644 --- a/dts/upstream/Bindings/gpio/pl061-gpio.yaml +++ b/dts/upstream/Bindings/gpio/pl061-gpio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM PL061 GPIO controller maintainers: - - Linus Walleij + - Linus Walleij - Rob Herring # We need a select here so we don't match all nodes with 'arm,primecell' diff --git a/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml b/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml index ab2afc0e415..bba6f5b6606 100644 --- a/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml +++ b/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml @@ -111,8 +111,8 @@ additionalProperties: false required: - compatible - reg - - "#address-cells" - - "#size-cells" + - '#address-cells' + - '#size-cells' examples: - | diff --git a/dts/upstream/Bindings/gpio/st,nomadik-gpio.yaml b/dts/upstream/Bindings/gpio/st,nomadik-gpio.yaml index b3e8951959b..40b4a755144 100644 --- a/dts/upstream/Bindings/gpio/st,nomadik-gpio.yaml +++ b/dts/upstream/Bindings/gpio/st,nomadik-gpio.yaml @@ -12,7 +12,7 @@ description: with pinctrl-nomadik. maintainers: - - Linus Walleij + - Linus Walleij properties: $nodename: diff --git a/dts/upstream/Bindings/gpio/st,stmpe-gpio.yaml b/dts/upstream/Bindings/gpio/st,stmpe-gpio.yaml index 4555f1644a4..66dd602e797 100644 --- a/dts/upstream/Bindings/gpio/st,stmpe-gpio.yaml +++ b/dts/upstream/Bindings/gpio/st,stmpe-gpio.yaml @@ -14,7 +14,7 @@ description: GPIO portions of these expanders. maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/gpio/trivial-gpio.yaml b/dts/upstream/Bindings/gpio/trivial-gpio.yaml index c994177de94..3f4bbd57fc5 100644 --- a/dts/upstream/Bindings/gpio/trivial-gpio.yaml +++ b/dts/upstream/Bindings/gpio/trivial-gpio.yaml @@ -22,6 +22,8 @@ properties: - cznic,moxtet-gpio - dlg,slg7xl45106 - fcs,fxl6408 + - fsl,ls1046aqds-fpga-gpio-stat-pres2 + - fsl,lx2160ardb-fpga-gpio-sfp - gateworks,pld-gpio - ibm,ppc4xx-gpio - loongson,ls1x-gpio diff --git a/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml b/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml index be198182dbf..db49b8ff8c7 100644 --- a/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml +++ b/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt8183-mali - mediatek,mt8183b-mali - mediatek,mt8186-mali + - mediatek,mt8365-mali - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali diff --git a/dts/upstream/Bindings/gpu/arm,mali-valhall-csf.yaml b/dts/upstream/Bindings/gpu/arm,mali-valhall-csf.yaml index a5b4e002175..bee9faf1d3f 100644 --- a/dts/upstream/Bindings/gpu/arm,mali-valhall-csf.yaml +++ b/dts/upstream/Bindings/gpu/arm,mali-valhall-csf.yaml @@ -18,6 +18,8 @@ properties: oneOf: - items: - enum: + - mediatek,mt8196-mali + - nxp,imx95-mali # G310 - rockchip,rk3588-mali - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable @@ -44,7 +46,9 @@ properties: minItems: 1 items: - const: core - - const: coregroup + - enum: + - coregroup + - stacks - const: stacks mali-supply: true @@ -91,7 +95,6 @@ required: - interrupts - interrupt-names - clocks - - mali-supply additionalProperties: false @@ -108,6 +111,29 @@ allOf: power-domains: maxItems: 1 power-domain-names: false + required: + - mali-supply + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-mali + then: + properties: + mali-supply: false + sram-supply: false + operating-points-v2: false + power-domains: + maxItems: 1 + power-domain-names: false + clocks: + maxItems: 2 + clock-names: + items: + - const: core + - const: stacks + required: + - power-domains examples: - | @@ -143,5 +169,17 @@ examples: }; }; }; + - | + gpu@48000000 { + compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf"; + reg = <0x48000000 0x480000>; + clocks = <&gpufreq 0>, <&gpufreq 1>; + clock-names = "core", "stacks"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + power-domains = <&gpufreq>; + }; ... diff --git a/dts/upstream/Bindings/gpu/img,powervr-rogue.yaml b/dts/upstream/Bindings/gpu/img,powervr-rogue.yaml index c87d7bece0e..86ef6898531 100644 --- a/dts/upstream/Bindings/gpu/img,powervr-rogue.yaml +++ b/dts/upstream/Bindings/gpu/img,powervr-rogue.yaml @@ -13,6 +13,18 @@ maintainers: properties: compatible: oneOf: + - items: + - enum: + - renesas,r8a7796-gpu + - renesas,r8a77961-gpu + - const: img,img-gx6250 + - const: img,img-rogue + - items: + - enum: + - renesas,r8a77965-gpu + - renesas,r8a779a0-gpu + - const: img,img-ge7800 + - const: img,img-rogue - items: - enum: - ti,am62-gpu @@ -82,6 +94,33 @@ required: additionalProperties: false allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,am62-gpu + - ti,j721s2-gpu + then: + properties: + clocks: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - img,img-ge7800 + - img,img-gx6250 + - thead,th1520-gpu + then: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + - if: properties: compatible: @@ -90,14 +129,31 @@ allOf: then: properties: power-domains: - items: - - description: Power domain A + maxItems: 1 power-domain-names: maxItems: 1 required: - power-domains - power-domain-names + - if: + properties: + compatible: + contains: + enum: + - img,img-bxs-4-64 + - img,img-ge7800 + - img,img-gx6250 + then: + properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + required: + - power-domains + - power-domain-names + - if: properties: compatible: @@ -105,10 +161,6 @@ allOf: const: thead,th1520-gpu then: properties: - clocks: - minItems: 3 - clock-names: - minItems: 3 power-domains: items: - description: The single, unified power domain for the GPU on the @@ -117,35 +169,6 @@ allOf: required: - power-domains - - if: - properties: - compatible: - contains: - const: img,img-bxs-4-64 - then: - properties: - power-domains: - items: - - description: Power domain A - - description: Power domain B - power-domain-names: - minItems: 2 - required: - - power-domains - - power-domain-names - - - if: - properties: - compatible: - contains: - enum: - - ti,am62-gpu - - ti,j721s2-gpu - then: - properties: - clocks: - maxItems: 1 - examples: - | #include diff --git a/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml b/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml index 383020450d7..b9cdfe52b62 100644 --- a/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml +++ b/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml @@ -20,12 +20,14 @@ properties: - samsung,exynos5433-chipid - samsung,exynos7-chipid - samsung,exynos7870-chipid + - samsung,exynos8890-chipid - const: samsung,exynos4210-chipid - items: - enum: - samsung,exynos2200-chipid - samsung,exynos7885-chipid - samsung,exynos8895-chipid + - samsung,exynos9610-chipid - samsung,exynos9810-chipid - samsung,exynos990-chipid - samsung,exynosautov9-chipid diff --git a/dts/upstream/Bindings/hwmon/adi,ltc2947.yaml b/dts/upstream/Bindings/hwmon/adi,ltc2947.yaml index 152935334c7..3e3f49cf2f5 100644 --- a/dts/upstream/Bindings/hwmon/adi,ltc2947.yaml +++ b/dts/upstream/Bindings/hwmon/adi,ltc2947.yaml @@ -81,7 +81,6 @@ required: - compatible - reg - additionalProperties: false examples: diff --git a/dts/upstream/Bindings/hwmon/adi,max31827.yaml b/dts/upstream/Bindings/hwmon/adi,max31827.yaml index f60e06ab7d0..c2f7c6ee1a3 100644 --- a/dts/upstream/Bindings/hwmon/adi,max31827.yaml +++ b/dts/upstream/Bindings/hwmon/adi,max31827.yaml @@ -93,7 +93,6 @@ allOf: adi,fault-q: default: 4 - required: - compatible - reg diff --git a/dts/upstream/Bindings/hwmon/apm,xgene-slimpro-hwmon.yaml b/dts/upstream/Bindings/hwmon/apm,xgene-slimpro-hwmon.yaml new file mode 100644 index 00000000000..58c51626a9c --- /dev/null +++ b/dts/upstream/Bindings/hwmon/apm,xgene-slimpro-hwmon.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/apm,xgene-slimpro-hwmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SLIMpro hwmon + +maintainers: + - Khuong Dinh + +properties: + compatible: + const: apm,xgene-slimpro-hwmon + + mboxes: + maxItems: 1 + +required: + - compatible + - mboxes + +additionalProperties: false + +examples: + - | + hwmon { + compatible = "apm,xgene-slimpro-hwmon"; + mboxes = <&mailbox 7>; + }; diff --git a/dts/upstream/Bindings/hwmon/apm-xgene-hwmon.txt b/dts/upstream/Bindings/hwmon/apm-xgene-hwmon.txt deleted file mode 100644 index 59b38557f1b..00000000000 --- a/dts/upstream/Bindings/hwmon/apm-xgene-hwmon.txt +++ /dev/null @@ -1,14 +0,0 @@ -APM X-Gene hwmon driver - -APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox. - -Required properties : - - compatible : should be "apm,xgene-slimpro-hwmon" - - mboxes : use the label reference for the mailbox as the first parameter. - The second parameter is the channel number. - -Example : - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; diff --git a/dts/upstream/Bindings/hwmon/aspeed,g6-pwm-tach.yaml b/dts/upstream/Bindings/hwmon/aspeed,g6-pwm-tach.yaml index 9e5ed901ae5..851fb16ec7f 100644 --- a/dts/upstream/Bindings/hwmon/aspeed,g6-pwm-tach.yaml +++ b/dts/upstream/Bindings/hwmon/aspeed,g6-pwm-tach.yaml @@ -18,8 +18,11 @@ description: | properties: compatible: - enum: - - aspeed,ast2600-pwm-tach + oneOf: + - items: + - const: aspeed,ast2700-pwm-tach + - const: aspeed,ast2600-pwm-tach + - const: aspeed,ast2600-pwm-tach reg: maxItems: 1 diff --git a/dts/upstream/Bindings/hwmon/max31785.txt b/dts/upstream/Bindings/hwmon/max31785.txt deleted file mode 100644 index 106e08c56aa..00000000000 --- a/dts/upstream/Bindings/hwmon/max31785.txt +++ /dev/null @@ -1,22 +0,0 @@ -Bindings for the Maxim MAX31785 Intelligent Fan Controller -========================================================== - -Reference: - -https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf - -The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan -management with temperature and remote voltage sensing. Various fan control -features are provided, including PWM frequency control, temperature hysteresis, -dual tachometer measurements, and fan health monitoring. - -Required properties: -- compatible : One of "maxim,max31785" or "maxim,max31785a" -- reg : I2C address, one of 0x52, 0x53, 0x54, 0x55. - -Example: - - fans@52 { - compatible = "maxim,max31785"; - reg = <0x52>; - }; diff --git a/dts/upstream/Bindings/hwmon/maxim,max31790.yaml b/dts/upstream/Bindings/hwmon/maxim,max31790.yaml index b1ff496f87f..558cbd251b0 100644 --- a/dts/upstream/Bindings/hwmon/maxim,max31790.yaml +++ b/dts/upstream/Bindings/hwmon/maxim,max31790.yaml @@ -20,7 +20,11 @@ description: > properties: compatible: - const: maxim,max31790 + enum: + - maxim,max31785 + - maxim,max31785a + - maxim,max31785b + - maxim,max31790 reg: maxItems: 1 @@ -31,11 +35,17 @@ properties: resets: maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + "#pwm-cells": const: 1 patternProperties: - "^fan-[0-9]+$": + "^fan@[0-9]+$": $ref: fan-common.yaml# unevaluatedProperties: false @@ -56,13 +66,17 @@ examples: reg = <0x20>; clocks = <&sys_clk>; resets = <&reset 0>; + #address-cells = <1>; #pwm-cells = <1>; + #size-cells = <0>; - fan-0 { + fan@0 { + reg = <0x0>; pwms = <&pwm_provider 1>; }; - fan-1 { + fan@1 { + reg = <0x1>; pwms = <&pwm_provider 2>; }; }; diff --git a/dts/upstream/Bindings/hwmon/national,lm90.yaml b/dts/upstream/Bindings/hwmon/national,lm90.yaml index 1b871f166e7..164068ba069 100644 --- a/dts/upstream/Bindings/hwmon/national,lm90.yaml +++ b/dts/upstream/Bindings/hwmon/national,lm90.yaml @@ -45,7 +45,6 @@ properties: - ti,tmp461 - winbond,w83l771 - interrupts: items: - description: | diff --git a/dts/upstream/Bindings/hwmon/ntc-thermistor.yaml b/dts/upstream/Bindings/hwmon/ntc-thermistor.yaml index b8e500e6cd9..efd10bcfb08 100644 --- a/dts/upstream/Bindings/hwmon/ntc-thermistor.yaml +++ b/dts/upstream/Bindings/hwmon/ntc-thermistor.yaml @@ -6,7 +6,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NTC thermistor temperature sensors maintainers: - - Linus Walleij + - Linus Walleij description: | Thermistors with negative temperature coefficient (NTC) are resistors that @@ -75,6 +75,7 @@ properties: - const: murata,ncp15wl333 - const: murata,ncp03wf104 - const: murata,ncp15xh103 + - const: murata,ncp18wm474 - const: samsung,1404-001221 # Deprecated "ntc," compatible strings - const: ntc,ncp15wb473 diff --git a/dts/upstream/Bindings/hwmon/pmbus/adi,max17616.yaml b/dts/upstream/Bindings/hwmon/pmbus/adi,max17616.yaml new file mode 100644 index 00000000000..fa48af81e08 --- /dev/null +++ b/dts/upstream/Bindings/hwmon/pmbus/adi,max17616.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max17616.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX17616/MAX17616A Current-Limiter with PMBus Interface + +maintainers: + - Kim Seer Paller + +description: | + The MAX17616/MAX17616A is a 3V to 80V, 7A current-limiter with overvoltage, + surge, undervoltage, reverse polarity, and loss of ground protection. It allows + monitoring of input/output voltage, output current and temperature through the + PMBus serial interface. + Datasheet: + https://www.analog.com/en/products/max17616.html + +properties: + compatible: + const: adi,max17616 + + reg: + maxItems: 1 + + vcc-supply: true + + interrupts: + description: Fault condition signal provided on SMBALERT pin. + maxItems: 1 + +required: + - compatible + - reg + - vcc-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hwmon@16 { + compatible = "adi,max17616"; + reg = <0x16>; + vcc-supply = <&vcc>; + }; + }; +... diff --git a/dts/upstream/Bindings/hwmon/st,tsc1641.yaml b/dts/upstream/Bindings/hwmon/st,tsc1641.yaml new file mode 100644 index 00000000000..aaf24479066 --- /dev/null +++ b/dts/upstream/Bindings/hwmon/st,tsc1641.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/st,tsc1641.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST Microelectronics TSC1641 I2C power monitor + +maintainers: + - Igor Reznichenko + +description: | + TSC1641 is a 60 V, 16-bit high-precision power monitor with I2C and + MIPI I3C interface + + Datasheets: + https://www.st.com/resource/en/datasheet/tsc1641.pdf + +properties: + compatible: + const: st,tsc1641 + + reg: + maxItems: 1 + + interrupts: + description: Optional alert interrupt. + maxItems: 1 + + shunt-resistor-micro-ohms: + description: Shunt resistor value in micro-ohms. Since device has internal + 16-bit RSHUNT register with 10 uOhm LSB, the maximum value is capped at + 655.35 mOhm. + minimum: 100 + default: 1000 + maximum: 655350 + + st,alert-polarity-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: Default value is 0 which configures the normal polarity of the + ALERT pin, being active low open-drain. Setting this to 1 configures the + polarity of the ALERT pin to be inverted and active high open-drain. + Specify this property to set the alert polarity to active-high. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + power-sensor@40 { + compatible = "st,tsc1641"; + reg = <0x40>; + shunt-resistor-micro-ohms = <1000>; + st,alert-polarity-active-high; + }; + }; diff --git a/dts/upstream/Bindings/hwmon/ti,tmp513.yaml b/dts/upstream/Bindings/hwmon/ti,tmp513.yaml index cba5b4a1b81..0fe6ea190f6 100644 --- a/dts/upstream/Bindings/hwmon/ti,tmp513.yaml +++ b/dts/upstream/Bindings/hwmon/ti,tmp513.yaml @@ -20,7 +20,6 @@ description: | https://www.ti.com/lit/gpn/tmp513 https://www.ti.com/lit/gpn/tmp512 - properties: compatible: enum: diff --git a/dts/upstream/Bindings/hwmon/ti,tps23861.yaml b/dts/upstream/Bindings/hwmon/ti,tps23861.yaml index ee7de53e191..d57e4bf8f65 100644 --- a/dts/upstream/Bindings/hwmon/ti,tps23861.yaml +++ b/dts/upstream/Bindings/hwmon/ti,tps23861.yaml @@ -15,7 +15,6 @@ description: | Datasheets: https://www.ti.com/lit/gpn/tps23861 - properties: compatible: enum: diff --git a/dts/upstream/Bindings/hwmon/winbond,w83781d.yaml b/dts/upstream/Bindings/hwmon/winbond,w83781d.yaml index 6971ecb314e..d97b0e69847 100644 --- a/dts/upstream/Bindings/hwmon/winbond,w83781d.yaml +++ b/dts/upstream/Bindings/hwmon/winbond,w83781d.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Winbond W83781 and compatible hardware monitor IC maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/i2c/arm,i2c-versatile.yaml b/dts/upstream/Bindings/i2c/arm,i2c-versatile.yaml index e58465d1b0c..26026dfd788 100644 --- a/dts/upstream/Bindings/i2c/arm,i2c-versatile.yaml +++ b/dts/upstream/Bindings/i2c/arm,i2c-versatile.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: I2C Controller on ARM Ltd development platforms maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/dts/upstream/Bindings/i2c/brcm,iproc-i2c.yaml b/dts/upstream/Bindings/i2c/brcm,iproc-i2c.yaml index 2aa75b7add7..daa70a8500e 100644 --- a/dts/upstream/Bindings/i2c/brcm,iproc-i2c.yaml +++ b/dts/upstream/Bindings/i2c/brcm,iproc-i2c.yaml @@ -16,7 +16,8 @@ properties: - brcm,iproc-nic-i2c reg: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-frequency: enum: [ 100000, 400000 ] @@ -41,8 +42,15 @@ allOf: contains: const: brcm,iproc-nic-i2c then: + properties: + reg: + minItems: 2 required: - brcm,ape-hsls-addr-mask + else: + properties: + reg: + maxItems: 1 unevaluatedProperties: false diff --git a/dts/upstream/Bindings/i2c/i2c-mux-gpmux.yaml b/dts/upstream/Bindings/i2c/i2c-mux-gpmux.yaml index b6af924dee2..d8610daa10c 100644 --- a/dts/upstream/Bindings/i2c/i2c-mux-gpmux.yaml +++ b/dts/upstream/Bindings/i2c/i2c-mux-gpmux.yaml @@ -27,7 +27,6 @@ description: |+ | '------' | | dev | | dev | | dev | '------------' '-----' '-----' '-----' - allOf: - $ref: /schemas/i2c/i2c-mux.yaml# diff --git a/dts/upstream/Bindings/i2c/i2c-rk3x.yaml b/dts/upstream/Bindings/i2c/i2c-rk3x.yaml index 4ac5a40a388..91805fe8f39 100644 --- a/dts/upstream/Bindings/i2c/i2c-rk3x.yaml +++ b/dts/upstream/Bindings/i2c/i2c-rk3x.yaml @@ -37,6 +37,7 @@ properties: - rockchip,px30-i2c - rockchip,rk3308-i2c - rockchip,rk3328-i2c + - rockchip,rk3506-i2c - rockchip,rk3528-i2c - rockchip,rk3562-i2c - rockchip,rk3568-i2c diff --git a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml index 9bc99d73634..a3fe1eea6ae 100644 --- a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml +++ b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml @@ -15,6 +15,7 @@ properties: oneOf: - enum: - qcom,msm8226-cci + - qcom,msm8953-cci - qcom,msm8974-cci - qcom,msm8996-cci @@ -25,6 +26,7 @@ properties: - items: - enum: + - qcom,kaanapali-cci - qcom,qcm2290-cci - qcom,sa8775p-cci - qcom,sc7280-cci @@ -36,6 +38,7 @@ properties: - qcom,sm8450-cci - qcom,sm8550-cci - qcom,sm8650-cci + - qcom,sm8750-cci - qcom,x1e80100-cci - const: qcom,msm8996-cci # CCI v2 @@ -128,7 +131,9 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-cci - qcom,qcm2290-cci + - qcom,sm8750-cci then: properties: clocks: @@ -146,6 +151,7 @@ allOf: - contains: enum: - qcom,msm8916-cci + - qcom,msm8953-cci - const: qcom,msm8996-cci then: diff --git a/dts/upstream/Bindings/i2c/qcom,i2c-qup.yaml b/dts/upstream/Bindings/i2c/qcom,i2c-qup.yaml index 758d8f6321e..06a04db3eda 100644 --- a/dts/upstream/Bindings/i2c/qcom,i2c-qup.yaml +++ b/dts/upstream/Bindings/i2c/qcom,i2c-qup.yaml @@ -9,7 +9,7 @@ title: Qualcomm Universal Peripheral (QUP) I2C controller maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/dts/upstream/Bindings/i2c/realtek,rtl9301-i2c.yaml b/dts/upstream/Bindings/i2c/realtek,rtl9301-i2c.yaml index 17ce39c19ab..f9a449fee2b 100644 --- a/dts/upstream/Bindings/i2c/realtek,rtl9301-i2c.yaml +++ b/dts/upstream/Bindings/i2c/realtek,rtl9301-i2c.yaml @@ -64,7 +64,6 @@ patternProperties: required: - reg - allOf: - if: properties: diff --git a/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml b/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml index d904191bb0c..91420018880 100644 --- a/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml +++ b/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml @@ -34,8 +34,15 @@ properties: - const: snps,designware-i2c - description: Baikal-T1 SoC System I2C controller const: baikal,bt1-sys-i2c + - description: Mobileye EyeQ DesignWare I2C controller + items: + - enum: + - mobileye,eyeq7h-i2c + - const: mobileye,eyeq6lplus-i2c + - const: snps,designware-i2c - items: - enum: + - mobileye,eyeq6lplus-i2c - mscc,ocelot-i2c - sophgo,sg2044-i2c - thead,th1520-i2c diff --git a/dts/upstream/Bindings/i2c/st,nomadik-i2c.yaml b/dts/upstream/Bindings/i2c/st,nomadik-i2c.yaml index 012402debfe..63a459c63f6 100644 --- a/dts/upstream/Bindings/i2c/st,nomadik-i2c.yaml +++ b/dts/upstream/Bindings/i2c/st,nomadik-i2c.yaml @@ -12,7 +12,7 @@ description: The Nomadik I2C host controller began its life in the ST DB8500 after the merge of these two companies wireless divisions. maintainers: - - Linus Walleij + - Linus Walleij # Need a custom select here or 'arm,primecell' will match on lots of nodes select: diff --git a/dts/upstream/Bindings/i2c/tsd,mule-i2c-mux.yaml b/dts/upstream/Bindings/i2c/tsd,mule-i2c-mux.yaml index 28139b67666..19cfffb3929 100644 --- a/dts/upstream/Bindings/i2c/tsd,mule-i2c-mux.yaml +++ b/dts/upstream/Bindings/i2c/tsd,mule-i2c-mux.yaml @@ -16,7 +16,6 @@ description: | can be selected by writing the appropriate device number to an I2C config register. - +--------------------------------------------------+ | Mule | 0x18| +---------------+ | @@ -34,7 +33,6 @@ description: | | |__/ +--------+ | +--------------------------------------------------+ - allOf: - $ref: /schemas/i2c/i2c-mux.yaml# diff --git a/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml b/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml index 5f646737581..e803457d3f5 100644 --- a/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml +++ b/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml @@ -14,7 +14,11 @@ allOf: properties: compatible: - const: snps,dw-i3c-master-1.00a + oneOf: + - const: snps,dw-i3c-master-1.00a + - items: + - const: altr,agilex5-dw-i3c-master + - const: snps,dw-i3c-master-1.00a reg: maxItems: 1 diff --git a/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml b/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml index a23a626bfab..61d7ba89adc 100644 --- a/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml +++ b/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml @@ -35,15 +35,17 @@ properties: spi-3wire: true interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupt-names: + minItems: 1 items: - enum: [INT1, INT2] + - const: INT2 dependencies: interrupts: [ interrupt-names ] - interrupt-names: [ interrupts ] required: - compatible @@ -84,7 +86,8 @@ examples: spi-cpol; spi-cpha; interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "INT2"; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1", "INT2"; }; }; diff --git a/dts/upstream/Bindings/iio/accel/adi,adxl380.yaml b/dts/upstream/Bindings/iio/accel/adi,adxl380.yaml index f1ff5ff4f47..ab517720a6a 100644 --- a/dts/upstream/Bindings/iio/accel/adi,adxl380.yaml +++ b/dts/upstream/Bindings/iio/accel/adi,adxl380.yaml @@ -11,16 +11,19 @@ maintainers: - Antoniu Miclaus description: | - The ADXL380/ADXL382 is a low noise density, low power, 3-axis - accelerometer with selectable measurement ranges. The ADXL380 - supports the ±4 g, ±8 g, and ±16 g ranges, and the ADXL382 supports - ±15 g, ±30 g, and ±60 g ranges. + The ADXL380/ADXL382 and ADXL318/ADXL319 are low noise density, + low power, 3-axis accelerometers with selectable measurement ranges. + The ADXL380 and ADXL318 support the ±4 g, ±8 g, and ±16 g ranges, + while the ADXL382 and ADXL319 support ±15 g, ±30 g, and ±60 g ranges. + https://www.analog.com/en/products/adxl318.html https://www.analog.com/en/products/adxl380.html properties: compatible: enum: + - adi,adxl318 + - adi,adxl319 - adi,adxl380 - adi,adxl382 diff --git a/dts/upstream/Bindings/iio/accel/bosch,bma220.yaml b/dts/upstream/Bindings/iio/accel/bosch,bma220.yaml index ec643de031a..8c820c27f78 100644 --- a/dts/upstream/Bindings/iio/accel/bosch,bma220.yaml +++ b/dts/upstream/Bindings/iio/accel/bosch,bma220.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/accel/bosch,bma220.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bosch BMA220 Trixial Acceleration Sensor +title: Bosch BMA220 Triaxial Acceleration Sensor maintainers: - Jonathan Cameron @@ -20,6 +20,9 @@ properties: interrupts: maxItems: 1 + spi-cpha: true + spi-cpol: true + vdda-supply: true vddd-supply: true vddio-supply: true @@ -44,8 +47,10 @@ examples: compatible = "bosch,bma220"; reg = <0>; spi-max-frequency = <2500000>; + spi-cpol; + spi-cpha; interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; }; }; ... diff --git a/dts/upstream/Bindings/iio/accel/bosch,bma255.yaml b/dts/upstream/Bindings/iio/accel/bosch,bma255.yaml index 85c9537f1f0..c1387e02eb8 100644 --- a/dts/upstream/Bindings/iio/accel/bosch,bma255.yaml +++ b/dts/upstream/Bindings/iio/accel/bosch,bma255.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Bosch BMA255 and Similar Accelerometers maintainers: - - Linus Walleij + - Linus Walleij - Stephan Gerhold description: diff --git a/dts/upstream/Bindings/iio/adc/adi,ad4080.yaml b/dts/upstream/Bindings/iio/adc/adi,ad4080.yaml index ed849ba1b77..ccd6a0ac153 100644 --- a/dts/upstream/Bindings/iio/adc/adi,ad4080.yaml +++ b/dts/upstream/Bindings/iio/adc/adi,ad4080.yaml @@ -26,6 +26,11 @@ properties: compatible: enum: - adi,ad4080 + - adi,ad4081 + - adi,ad4083 + - adi,ad4084 + - adi,ad4086 + - adi,ad4087 reg: maxItems: 1 diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7380.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7380.yaml index 8dae89ecb64..b91bfb16ed6 100644 --- a/dts/upstream/Bindings/iio/adc/adi,ad7380.yaml +++ b/dts/upstream/Bindings/iio/adc/adi,ad7380.yaml @@ -30,7 +30,6 @@ description: | * https://www.analog.com/en/products/adaq4380-4.html * https://www.analog.com/en/products/adaq4381-4.html - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml index 1180d2ffbf8..73c8e9c532f 100644 --- a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml +++ b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml @@ -166,7 +166,6 @@ properties: An example of backend can be found at http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html - patternProperties: "^channel@[1-8]$": type: object diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7949.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7949.yaml index 9ee4d977c5e..238a8c9c414 100644 --- a/dts/upstream/Bindings/iio/adc/adi,ad7949.yaml +++ b/dts/upstream/Bindings/iio/adc/adi,ad7949.yaml @@ -48,7 +48,6 @@ properties: enum: [2500000, 4096000] default: 4096000 - '#io-channel-cells': const: 1 diff --git a/dts/upstream/Bindings/iio/adc/adi,ade9000.yaml b/dts/upstream/Bindings/iio/adc/adi,ade9000.yaml index bd429552d56..f22eba0250e 100644 --- a/dts/upstream/Bindings/iio/adc/adi,ade9000.yaml +++ b/dts/upstream/Bindings/iio/adc/adi,ade9000.yaml @@ -57,7 +57,6 @@ properties: description: External clock source when not using crystal maxItems: 1 - "#clock-cells": description: ADE9000 can provide clock output via CLKOUT pin with external buffer. diff --git a/dts/upstream/Bindings/iio/adc/adi,max14001.yaml b/dts/upstream/Bindings/iio/adc/adi,max14001.yaml new file mode 100644 index 00000000000..a2dc59c9dcd --- /dev/null +++ b/dts/upstream/Bindings/iio/adc/adi,max14001.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023-2025 Analog Devices Inc. +# Copyright 2023 Kim Seer Paller +# Copyright 2025 Marilene Andrade Garcia +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,max14001.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX14001-MAX14002 ADC + +maintainers: + - Kim Seer Paller + - Marilene Andrade Garcia + +description: | + Single channel 10 bit ADC with SPI interface. + Datasheet can be found here + https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14001-MAX14002.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - const: adi,max14002 + - items: + - const: adi,max14001 + - const: adi,max14002 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 5000000 + + vdd-supply: + description: + Isolated DC-DC power supply input voltage. + + vddl-supply: + description: + Logic power supply. + + refin-supply: + description: + ADC voltage reference supply. + + interrupts: + minItems: 1 + items: + - description: | + cout: comparator output signal that asserts high on the COUT pin + when ADC readings exceed the upper threshold and low when readings + fall below the lower threshold. + - description: | + fault: when fault reporting is enabled, the FAULT pin is asserted + low whenever one of the monitored fault conditions occurs. + + interrupt-names: + minItems: 1 + items: + - const: cout + - const: fault + +required: + - compatible + - reg + - vdd-supply + - vddl-supply + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,max14001", "adi,max14002"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-lsb-first; + vdd-supply = <&vdd>; + vddl-supply = <&vddl>; + }; + }; +... diff --git a/dts/upstream/Bindings/iio/adc/aspeed,ast2600-adc.yaml b/dts/upstream/Bindings/iio/adc/aspeed,ast2600-adc.yaml index 5c08d8b6e99..509bfb1007c 100644 --- a/dts/upstream/Bindings/iio/adc/aspeed,ast2600-adc.yaml +++ b/dts/upstream/Bindings/iio/adc/aspeed,ast2600-adc.yaml @@ -29,6 +29,8 @@ properties: enum: - aspeed,ast2600-adc0 - aspeed,ast2600-adc1 + - aspeed,ast2700-adc0 + - aspeed,ast2700-adc1 description: Their trimming data, which is used to calibrate internal reference volage, locates in different address of OTP. diff --git a/dts/upstream/Bindings/iio/adc/cosmic,10001-adc.yaml b/dts/upstream/Bindings/iio/adc/cosmic,10001-adc.yaml index 4e695b97d01..9ea44ce63f2 100644 --- a/dts/upstream/Bindings/iio/adc/cosmic,10001-adc.yaml +++ b/dts/upstream/Bindings/iio/adc/cosmic,10001-adc.yaml @@ -36,7 +36,6 @@ properties: "#io-channel-cells": const: 1 - required: - compatible - reg diff --git a/dts/upstream/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/dts/upstream/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml index 14363389f30..d9e825e5054 100644 --- a/dts/upstream/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/dts/upstream/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -42,6 +42,7 @@ properties: - mediatek,mt8183-auxadc - mediatek,mt8186-auxadc - mediatek,mt8188-auxadc + - mediatek,mt8189-auxadc - mediatek,mt8195-auxadc - mediatek,mt8516-auxadc - const: mediatek,mt8173-auxadc diff --git a/dts/upstream/Bindings/iio/adc/qcom,pm8018-adc.yaml b/dts/upstream/Bindings/iio/adc/qcom,pm8018-adc.yaml index 58ea1ca4a5e..c978c3a3e31 100644 --- a/dts/upstream/Bindings/iio/adc/qcom,pm8018-adc.yaml +++ b/dts/upstream/Bindings/iio/adc/qcom,pm8018-adc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm's PM8xxx voltage XOADC maintainers: - - Linus Walleij + - Linus Walleij description: | The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal diff --git a/dts/upstream/Bindings/iio/adc/renesas,r9a09g077-adc.yaml b/dts/upstream/Bindings/iio/adc/renesas,r9a09g077-adc.yaml new file mode 100644 index 00000000000..dc0206b2823 --- /dev/null +++ b/dts/upstream/Bindings/iio/adc/renesas,r9a09g077-adc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H / RZ/N2H ADC12 + +maintainers: + - Cosmin Tanislav + +description: | + A/D Converter block is a successive approximation analog-to-digital converter + with a 12-bit accuracy. Up to 16 analog input channels can be selected. + Conversions can be performed in single or continuous mode. Result of the ADC + is stored in a 16-bit data register corresponding to each channel. + +properties: + compatible: + oneOf: + - items: + - const: renesas,r9a09g087-adc # RZ/N2H + - const: renesas,r9a09g077-adc # RZ/T2H + - items: + - const: renesas,r9a09g077-adc # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: A/D scan end interrupt + - description: A/D scan end interrupt for Group B + - description: A/D scan end interrupt for Group C + - description: Window A compare match + - description: Window B compare match + - description: Compare match + - description: Compare mismatch + + interrupt-names: + items: + - const: adi + - const: gbadi + - const: gcadi + - const: cmpai + - const: cmpbi + - const: wcmpm + - const: wcmpum + + clocks: + items: + - description: Converter clock + - description: Peripheral clock + + clock-names: + items: + - const: adclk + - const: pclk + + power-domains: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + "#io-channel-cells": + const: 1 + +patternProperties: + "^channel@[0-9a-f]$": + $ref: adc.yaml + type: object + description: The external channels which are connected to the ADC. + + properties: + reg: + description: The channel number. + maximum: 15 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + + adc@80008000 { + compatible = "renesas,r9a09g077-adc"; + reg = <0x80008000 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@0 { + reg = <0x0>; + }; + channel@1 { + reg = <0x1>; + }; + channel@2 { + reg = <0x2>; + }; + channel@3 { + reg = <0x3>; + }; + }; diff --git a/dts/upstream/Bindings/iio/adc/renesas,rzn1-adc.yaml b/dts/upstream/Bindings/iio/adc/renesas,rzn1-adc.yaml new file mode 100644 index 00000000000..1a40352165f --- /dev/null +++ b/dts/upstream/Bindings/iio/adc/renesas,rzn1-adc.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,rzn1-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Analog to Digital Converter (ADC) + +maintainers: + - Herve Codina + +description: + The Renesas RZ/N1 ADC controller available in the Renesas RZ/N1 SoCs family + can use up to two internal ADC cores (ADC1 and ADC2) those internal cores are + handled through ADC controller virtual channels. + +properties: + compatible: + items: + - const: renesas,r9a06g032-adc # RZ/N1D + - const: renesas,rzn1-adc + + reg: + maxItems: 1 + + clocks: + items: + - description: APB internal bus clock + - description: ADC clock + + clock-names: + items: + - const: pclk + - const: adc + + power-domains: + maxItems: 1 + + adc1-avdd-supply: + description: + ADC1 analog power supply. + + adc1-vref-supply: + description: + ADC1 reference voltage supply. + + adc2-avdd-supply: + description: + ADC2 analog power supply. + + adc2-vref-supply: + description: + ADC2 reference voltage supply. + + '#io-channel-cells': + const: 1 + description: | + Channels numbers available: + if ADC1 is used (i.e. adc1-{avdd,vref}-supply present): + - 0: ADC1 IN0 + - 1: ADC1 IN1 + - 2: ADC1 IN2 + - 3: ADC1 IN3 + - 4: ADC1 IN4 + - 5: ADC1 IN6 + - 6: ADC1 IN7 + - 7: ADC1 IN8 + if ADC2 is used (i.e. adc2-{avdd,vref}-supply present): + - 8: ADC2 IN0 + - 9: ADC2 IN1 + - 10: ADC2 IN2 + - 11: ADC2 IN3 + - 12: ADC2 IN4 + - 13: ADC2 IN6 + - 14: ADC2 IN7 + - 15: ADC2 IN8 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#io-channel-cells' + +# At least one of avvd/vref supplies +anyOf: + - required: + - adc1-vref-supply + - adc1-avdd-supply + - required: + - adc2-vref-supply + - adc2-avdd-supply + +additionalProperties: false + +examples: + - | + #include + + adc: adc@40065000 { + compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc"; + reg = <0x40065000 0x200>; + clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; + clock-names = "pclk", "adc"; + power-domains = <&sysctrl>; + adc1-avdd-supply = <&adc1_avdd>; + adc1-vref-supply = <&adc1_vref>; + #io-channel-cells = <1>; + }; +... diff --git a/dts/upstream/Bindings/iio/adc/rockchip-saradc.yaml b/dts/upstream/Bindings/iio/adc/rockchip-saradc.yaml index f776041fd08..6769d679c90 100644 --- a/dts/upstream/Bindings/iio/adc/rockchip-saradc.yaml +++ b/dts/upstream/Bindings/iio/adc/rockchip-saradc.yaml @@ -16,6 +16,9 @@ properties: - const: rockchip,rk3066-tsadc - const: rockchip,rk3399-saradc - const: rockchip,rk3528-saradc + - items: + - const: rockchip,rk3506-saradc + - const: rockchip,rk3528-saradc - const: rockchip,rk3562-saradc - const: rockchip,rk3588-saradc - items: diff --git a/dts/upstream/Bindings/iio/adc/st,stm32-adc.yaml b/dts/upstream/Bindings/iio/adc/st,stm32-adc.yaml index 17bb60e18a1..c4c4575d3fa 100644 --- a/dts/upstream/Bindings/iio/adc/st,stm32-adc.yaml +++ b/dts/upstream/Bindings/iio/adc/st,stm32-adc.yaml @@ -456,7 +456,6 @@ patternProperties: items: minimum: 40 - - if: properties: compatible: diff --git a/dts/upstream/Bindings/iio/adc/x-powers,axp209-adc.yaml b/dts/upstream/Bindings/iio/adc/x-powers,axp209-adc.yaml index 1caa896fce8..de91cb03fdc 100644 --- a/dts/upstream/Bindings/iio/adc/x-powers,axp209-adc.yaml +++ b/dts/upstream/Bindings/iio/adc/x-powers,axp209-adc.yaml @@ -57,7 +57,6 @@ description: | 4 | batt_dischrg_i 5 | ts_v - properties: compatible: oneOf: diff --git a/dts/upstream/Bindings/iio/afe/voltage-divider.yaml b/dts/upstream/Bindings/iio/afe/voltage-divider.yaml index 4151f99b42a..9752d145006 100644 --- a/dts/upstream/Bindings/iio/afe/voltage-divider.yaml +++ b/dts/upstream/Bindings/iio/afe/voltage-divider.yaml @@ -29,7 +29,6 @@ description: | | GND - properties: compatible: const: voltage-divider diff --git a/dts/upstream/Bindings/iio/dac/adi,ad5446.yaml b/dts/upstream/Bindings/iio/dac/adi,ad5446.yaml new file mode 100644 index 00000000000..2669d2c4948 --- /dev/null +++ b/dts/upstream/Bindings/iio/dac/adi,ad5446.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5446.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5446 and similar DACs + +maintainers: + - Michael Hennerich + - Nuno Sá + +description: + Digital to Analog Converter devices supporting both SPI and I2C interfaces. + These devices feature a range of resolutions from 8-bit to 16-bit. + +properties: + compatible: + oneOf: + - description: SPI DACs + enum: + - adi,ad5300 + - adi,ad5310 + - adi,ad5320 + - adi,ad5444 + - adi,ad5446 + - adi,ad5450 + - adi,ad5451 + - adi,ad5452 + - adi,ad5453 + - adi,ad5512a + - adi,ad5541a + - adi,ad5542 + - adi,ad5542a + - adi,ad5543 + - adi,ad5553 + - adi,ad5600 + - adi,ad5601 + - adi,ad5611 + - adi,ad5621 + - adi,ad5641 + - adi,ad5620-2500 + - adi,ad5620-1250 + - adi,ad5640-2500 + - adi,ad5640-1250 + - adi,ad5660-2500 + - adi,ad5660-1250 + - adi,ad5662 + - ti,dac081s101 + - ti,dac101s101 + - ti,dac121s101 + - description: I2C DACs + enum: + - adi,ad5301 + - adi,ad5311 + - adi,ad5321 + - adi,ad5602 + - adi,ad5612 + - adi,ad5622 + + reg: + maxItems: 1 + + vcc-supply: + description: + Reference voltage supply. If not supplied, devices with internal + voltage reference will use that. + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - adi,ad5300 + - adi,ad5310 + - adi,ad5320 + - adi,ad5444 + - adi,ad5446 + - adi,ad5450 + - adi,ad5451 + - adi,ad5452 + - adi,ad5453 + - adi,ad5512a + - adi,ad5541a + - adi,ad5542 + - adi,ad5542a + - adi,ad5543 + - adi,ad5553 + - adi,ad5600 + - adi,ad5601 + - adi,ad5611 + - adi,ad5621 + - adi,ad5641 + - adi,ad5620-2500 + - adi,ad5620-1250 + - adi,ad5640-2500 + - adi,ad5640-1250 + - adi,ad5660-2500 + - adi,ad5660-1250 + - adi,ad5662 + - ti,dac081s101 + - ti,dac101s101 + - ti,dac121s101 + then: + allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "adi,ad5446"; + reg = <0>; + vcc-supply = <&dac_vref>; + }; + }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dac@42 { + compatible = "adi,ad5622"; + reg = <0x42>; + vcc-supply = <&dac_vref>; + }; + }; +... diff --git a/dts/upstream/Bindings/iio/frequency/adi,admv4420.yaml b/dts/upstream/Bindings/iio/frequency/adi,admv4420.yaml index 64f2352aac3..ca40359a394 100644 --- a/dts/upstream/Bindings/iio/frequency/adi,admv4420.yaml +++ b/dts/upstream/Bindings/iio/frequency/adi,admv4420.yaml @@ -37,7 +37,6 @@ required: - compatible - reg - allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# diff --git a/dts/upstream/Bindings/iio/gyroscope/invensense,mpu3050.yaml b/dts/upstream/Bindings/iio/gyroscope/invensense,mpu3050.yaml index f3242dc0e7e..3a307ac50aa 100644 --- a/dts/upstream/Bindings/iio/gyroscope/invensense,mpu3050.yaml +++ b/dts/upstream/Bindings/iio/gyroscope/invensense,mpu3050.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Invensense MPU-3050 Gyroscope maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/iio/health/maxim,max30100.yaml b/dts/upstream/Bindings/iio/health/maxim,max30100.yaml index 967778fb0ce..d4753c85ecc 100644 --- a/dts/upstream/Bindings/iio/health/maxim,max30100.yaml +++ b/dts/upstream/Bindings/iio/health/maxim,max30100.yaml @@ -27,6 +27,14 @@ properties: LED current whilst the engine is running. First indexed value is the configuration for the RED LED, and second value is for the IR LED. + maxim,pulse-width-us: + description: | + LED pulse width in microseconds. Appropriate pulse width depends on + factors such as optical window absorption, LED-to-sensor distance, + and expected reflectivity of the skin or contact surface. + enum: [200, 400, 800, 1600] + default: 1600 + additionalProperties: false required: diff --git a/dts/upstream/Bindings/iio/imu/bosch,smi330.yaml b/dts/upstream/Bindings/iio/imu/bosch,smi330.yaml new file mode 100644 index 00000000000..0270ca456d2 --- /dev/null +++ b/dts/upstream/Bindings/iio/imu/bosch,smi330.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/bosch,smi330.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch SMI330 6-Axis IMU + +maintainers: + - Stefan Gutmann + +description: + SMI330 is a 6-axis inertial measurement unit that supports acceleration and + gyroscopic measurements with hardware fifo buffering. Sensor also provides + events information such as motion, no-motion and tilt detection. + +properties: + compatible: + const: bosch,smi330 + + reg: + maxItems: 1 + + vdd-supply: + description: provide VDD power to the sensor. + + vddio-supply: + description: provide VDD IO power to the sensor. + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: + - INT1 + - INT2 + + drive-open-drain: + type: boolean + description: + set if the interrupt pin(s) should be configured as + open drain. If not set, defaults to push-pull. + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + // Example for I2C + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imu@68 { + compatible = "bosch,smi330"; + reg = <0x68>; + vddio-supply = <&vddio>; + vdd-supply = <&vdd>; + interrupt-parent = <&gpio>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + }; + }; + + // Example for SPI + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + imu@0 { + compatible = "bosch,smi330"; + reg = <0>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + }; + }; diff --git a/dts/upstream/Bindings/iio/imu/invensense,icm45600.yaml b/dts/upstream/Bindings/iio/imu/invensense,icm45600.yaml new file mode 100644 index 00000000000..e0b78d14420 --- /dev/null +++ b/dts/upstream/Bindings/iio/imu/invensense,icm45600.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/invensense,icm45600.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: InvenSense ICM-45600 Inertial Measurement Unit + +maintainers: + - Remi Buisson + +description: | + 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis + accelerometer. + + It has a configurable host interface that supports I3C, I2C and SPI serial + communication, features up to 8kB FIFO and 2 programmable interrupts with + ultra-low-power wake-on-motion support to minimize system power consumption. + + Other industry-leading features include InvenSense on-chip APEX Motion + Processing engine for gesture recognition, activity classification, and + pedometer, along with programmable digital filters, and an embedded + temperature sensor. + + https://invensense.tdk.com/wp-content/uploads/documentation/DS-000576_ICM-45605.pdf + +properties: + compatible: + enum: + - invensense,icm45605 + - invensense,icm45606 + - invensense,icm45608 + - invensense,icm45634 + - invensense,icm45686 + - invensense,icm45687 + - invensense,icm45688p + - invensense,icm45689 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - enum: [int1, int2] + - const: int2 + description: Choose chip interrupt pin to be used as interrupt input. + + drive-open-drain: + type: boolean + + vdd-supply: true + + vddio-supply: true + + mount-matrix: true + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imu@68 { + compatible = "invensense,icm45605"; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupt-names = "int1"; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; + }; diff --git a/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml b/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml index 0bce71529e3..1af0855c33e 100644 --- a/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml +++ b/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml @@ -86,7 +86,6 @@ unevaluatedProperties: false required: - compatible - reg - - interrupts examples: - | diff --git a/dts/upstream/Bindings/iio/light/capella,cm3605.yaml b/dts/upstream/Bindings/iio/light/capella,cm3605.yaml index c63b79c3351..01376c386a0 100644 --- a/dts/upstream/Bindings/iio/light/capella,cm3605.yaml +++ b/dts/upstream/Bindings/iio/light/capella,cm3605.yaml @@ -8,7 +8,7 @@ title: Capella Microsystems CM3605 Ambient Light and Short Distance Proximity Sensor maintainers: - - Linus Walleij + - Linus Walleij - Kevin Tsai description: | diff --git a/dts/upstream/Bindings/iio/light/sharp,gp2ap002.yaml b/dts/upstream/Bindings/iio/light/sharp,gp2ap002.yaml index f8a932be0d1..99bddf31cbe 100644 --- a/dts/upstream/Bindings/iio/light/sharp,gp2ap002.yaml +++ b/dts/upstream/Bindings/iio/light/sharp,gp2ap002.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sharp GP2AP002A00F and GP2AP002S00F proximity and ambient light sensors maintainers: - - Linus Walleij + - Linus Walleij description: | Proximity and ambient light sensor with IR LED for the proximity diff --git a/dts/upstream/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml b/dts/upstream/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml index cefb70def18..f6b4d987419 100644 --- a/dts/upstream/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml +++ b/dts/upstream/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Asahi Kasei AK8974 magnetometer sensor maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/iio/magnetometer/yamaha,yas530.yaml b/dts/upstream/Bindings/iio/magnetometer/yamaha,yas530.yaml index 877226e9219..5cbf60f3b08 100644 --- a/dts/upstream/Bindings/iio/magnetometer/yamaha,yas530.yaml +++ b/dts/upstream/Bindings/iio/magnetometer/yamaha,yas530.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Yamaha YAS530 family of magnetometer sensors maintainers: - - Linus Walleij + - Linus Walleij description: The Yamaha YAS530 magnetometers is a line of 3-axis magnetometers diff --git a/dts/upstream/Bindings/iio/pressure/aosong,adp810.yaml b/dts/upstream/Bindings/iio/pressure/aosong,adp810.yaml new file mode 100644 index 00000000000..ad5f26ce504 --- /dev/null +++ b/dts/upstream/Bindings/iio/pressure/aosong,adp810.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/aosong,adp810.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: aosong adp810 differential pressure sensor + +maintainers: + - Akhilesh Patil + +description: + ADP810 is differential pressure and temperature sensor. It has I2C bus + interface with fixed address of 0x25. This sensor supports 8 bit CRC for + reliable data transfer. It can measure differential pressure in the + range -500 to 500Pa and temperate in the range -40 to +85 degree celsius. + +properties: + compatible: + enum: + - aosong,adp810 + + reg: + maxItems: 1 + + vdd-supply: true + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + pressure-sensor@25 { + compatible = "aosong,adp810"; + reg = <0x25>; + vdd-supply = <&vdd_regulator>; + }; + }; diff --git a/dts/upstream/Bindings/iio/pressure/fsl,mpl3115.yaml b/dts/upstream/Bindings/iio/pressure/fsl,mpl3115.yaml new file mode 100644 index 00000000000..2933c2e1069 --- /dev/null +++ b/dts/upstream/Bindings/iio/pressure/fsl,mpl3115.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/fsl,mpl3115.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MPL3115 precision pressure sensor with altimetry + +maintainers: + - Antoni Pokusinski + +description: | + MPL3115 is a pressure/altitude and temperature sensor with I2C interface. + It features two programmable interrupt lines which indicate events such as + data ready or pressure/temperature threshold reached. + https://www.nxp.com/docs/en/data-sheet/MPL3115A2.pdf + +properties: + compatible: + const: fsl,mpl3115 + + reg: + maxItems: 1 + + vdd-supply: true + + vddio-supply: true + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: + - INT1 + - INT2 + + drive-open-drain: + type: boolean + description: + set if the specified interrupt pins should be configured as + open drain. If not set, defaults to push-pull. + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pressure@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT2"; + }; + }; diff --git a/dts/upstream/Bindings/iio/pressure/infineon,dps310.yaml b/dts/upstream/Bindings/iio/pressure/infineon,dps310.yaml new file mode 100644 index 00000000000..e5d1e6c4893 --- /dev/null +++ b/dts/upstream/Bindings/iio/pressure/infineon,dps310.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/pressure/infineon,dps310.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Infineon DPS310 barometric pressure and temperature sensor + +maintainers: + - Eddie James + +description: + The DPS310 is a barometric pressure and temperature sensor with an I2C + interface. + +properties: + compatible: + enum: + - infineon,dps310 + + reg: + maxItems: 1 + + "#io-channel-cells": + const: 0 + + vdd-supply: + description: + Voltage supply for the chip's analog blocks. + + vddio-supply: + description: + Digital voltage supply for the chip's digital blocks and I/O interface. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dps: pressure-sensor@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + vdd-supply = <&vref1>; + vddio-supply = <&vref2>; + }; + }; diff --git a/dts/upstream/Bindings/iio/pressure/murata,zpa2326.yaml b/dts/upstream/Bindings/iio/pressure/murata,zpa2326.yaml index c33640ddde5..886f4129c30 100644 --- a/dts/upstream/Bindings/iio/pressure/murata,zpa2326.yaml +++ b/dts/upstream/Bindings/iio/pressure/murata,zpa2326.yaml @@ -12,7 +12,6 @@ maintainers: description: | Pressure sensor from Murata with SPI and I2C bus interfaces. - properties: compatible: const: murata,zpa2326 diff --git a/dts/upstream/Bindings/iio/proximity/semtech,sx9324.yaml b/dts/upstream/Bindings/iio/proximity/semtech,sx9324.yaml index 48f22146316..8fed45ee557 100644 --- a/dts/upstream/Bindings/iio/proximity/semtech,sx9324.yaml +++ b/dts/upstream/Bindings/iio/proximity/semtech,sx9324.yaml @@ -78,7 +78,6 @@ properties: minItems: 3 maxItems: 3 - semtech,ph01-resolution: $ref: /schemas/types.yaml#/definitions/uint32 enum: [8, 16, 32, 64, 128, 256, 512, 1024] diff --git a/dts/upstream/Bindings/iio/st,st-sensors.yaml b/dts/upstream/Bindings/iio/st,st-sensors.yaml index e955eb8e879..a1a958215cd 100644 --- a/dts/upstream/Bindings/iio/st,st-sensors.yaml +++ b/dts/upstream/Bindings/iio/st,st-sensors.yaml @@ -14,7 +14,7 @@ description: The STMicroelectronics sensor devices are pretty straight-forward maintainers: - Denis Ciocca - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/iio/temperature/adi,ltc2983.yaml b/dts/upstream/Bindings/iio/temperature/adi,ltc2983.yaml index 312febeeb3b..a22725f7619 100644 --- a/dts/upstream/Bindings/iio/temperature/adi,ltc2983.yaml +++ b/dts/upstream/Bindings/iio/temperature/adi,ltc2983.yaml @@ -39,7 +39,6 @@ $defs: - reg - adi,sensor-type - properties: compatible: oneOf: @@ -88,7 +87,7 @@ properties: const: 0 patternProperties: - "^thermocouple@": + '^thermocouple@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false @@ -146,7 +145,7 @@ patternProperties: required: - adi,custom-thermocouple - "^diode@": + '^diode@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false @@ -191,7 +190,7 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 default: 0 - "^rtd@": + '^rtd@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false description: RTD sensor. @@ -280,7 +279,7 @@ patternProperties: type: boolean dependencies: - adi,current-rotate: [ "adi,rsense-share" ] + adi,current-rotate: [ 'adi,rsense-share' ] - if: properties: @@ -290,7 +289,7 @@ patternProperties: required: - adi,custom-rtd - "^thermistor@": + '^thermistor@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false description: Thermistor sensor. @@ -364,7 +363,7 @@ patternProperties: - adi,rsense-handle dependencies: - adi,current-rotate: [ "adi,rsense-share" ] + adi,current-rotate: [ 'adi,rsense-share' ] allOf: - if: @@ -392,7 +391,7 @@ patternProperties: required: - adi,custom-thermistor - "^adc@": + '^adc@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false description: Direct ADC sensor. @@ -407,7 +406,7 @@ patternProperties: description: Whether the sensor is single-ended. type: boolean - "^temp@": + '^temp@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false description: Active analog temperature sensor. @@ -437,7 +436,7 @@ patternProperties: required: - adi,custom-temp - "^rsense@": + '^rsense@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false description: Sense resistor sensor. @@ -476,7 +475,7 @@ allOf: - adi,ltc2984 then: patternProperties: - "^temp@": false + '^temp@': false examples: - | diff --git a/dts/upstream/Bindings/input/atmel,maxtouch.yaml b/dts/upstream/Bindings/input/atmel,maxtouch.yaml index d79b254f1cd..9bf07acea59 100644 --- a/dts/upstream/Bindings/input/atmel,maxtouch.yaml +++ b/dts/upstream/Bindings/input/atmel,maxtouch.yaml @@ -8,7 +8,7 @@ title: Atmel maXTouch touchscreen/touchpad maintainers: - Nick Dyer - - Linus Walleij + - Linus Walleij description: | Atmel maXTouch touchscreen or touchpads such as the mXT244 diff --git a/dts/upstream/Bindings/input/cypress,cyapa.yaml b/dts/upstream/Bindings/input/cypress,cyapa.yaml index 29515151abe..da629d511da 100644 --- a/dts/upstream/Bindings/input/cypress,cyapa.yaml +++ b/dts/upstream/Bindings/input/cypress,cyapa.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cypress All Points Addressable (APA) I2C Touchpad / Trackpad maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski properties: compatible: diff --git a/dts/upstream/Bindings/input/ti,drv266x.yaml b/dts/upstream/Bindings/input/ti,drv266x.yaml index da181882437..1bce389d0e5 100644 --- a/dts/upstream/Bindings/input/ti,drv266x.yaml +++ b/dts/upstream/Bindings/input/ti,drv266x.yaml @@ -37,7 +37,6 @@ examples: - | #include - i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/Bindings/input/ti,twl4030-keypad.yaml b/dts/upstream/Bindings/input/ti,twl4030-keypad.yaml new file mode 100644 index 00000000000..c69aa7f5cca --- /dev/null +++ b/dts/upstream/Bindings/input/ti,twl4030-keypad.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/ti,twl4030-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TWL4030-family Keypad Controller + +maintainers: + - Peter Ujfalusi + +description: + TWL4030's Keypad controller is used to interface a SoC with a matrix-type + keypad device. The keypad controller supports multiple row and column lines. + A key can be placed at each intersection of a unique row and a unique column. + The keypad controller can sense a key-press and key-release and report the + event using a interrupt to the cpu. + +allOf: + - $ref: matrix-keymap.yaml# + +properties: + compatible: + const: ti,twl4030-keypad + + interrupts: + maxItems: 1 + +required: + - compatible + - interrupts + - keypad,num-rows + - keypad,num-columns + - linux,keymap + +unevaluatedProperties: false + +examples: + - | + #include + + keypad { + compatible = "ti,twl4030-keypad"; + interrupts = <1>; + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + /* row 0 */ + MATRIX_KEY(0, 0, KEY_1) + MATRIX_KEY(0, 1, KEY_2) + MATRIX_KEY(0, 2, KEY_3) + + /* ...and so on for a full 8x8 matrix... */ + + /* row 7 */ + MATRIX_KEY(7, 6, KEY_Y) + MATRIX_KEY(7, 7, KEY_Z) + >; + }; diff --git a/dts/upstream/Bindings/input/touchscreen/ar1021.txt b/dts/upstream/Bindings/input/touchscreen/ar1021.txt deleted file mode 100644 index 82019bd6094..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/ar1021.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Microchip AR1020 and AR1021 touchscreen interface (I2C) - -Required properties: -- compatible : "microchip,ar1021-i2c" -- reg : I2C slave address -- interrupts : touch controller interrupt - -Example: - - touchscreen@4d { - compatible = "microchip,ar1021-i2c"; - reg = <0x4d>; - interrupt-parent = <&gpio3>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/dts/upstream/Bindings/input/touchscreen/azoteq,iqs5xx.yaml b/dts/upstream/Bindings/input/touchscreen/azoteq,iqs5xx.yaml deleted file mode 100644 index b5f377215c0..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/azoteq,iqs5xx.yaml +++ /dev/null @@ -1,75 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/input/touchscreen/azoteq,iqs5xx.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Azoteq IQS550/572/525 Trackpad/Touchscreen Controller - -maintainers: - - Jeff LaBundy - -description: | - The Azoteq IQS550, IQS572 and IQS525 trackpad and touchscreen controllers - employ projected-capacitance sensing and can track up to five independent - contacts. - - Link to datasheet: https://www.azoteq.com/ - -allOf: - - $ref: touchscreen.yaml# - -properties: - compatible: - enum: - - azoteq,iqs550 - - azoteq,iqs572 - - azoteq,iqs525 - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - reset-gpios: - maxItems: 1 - - wakeup-source: true - - touchscreen-size-x: true - touchscreen-size-y: true - touchscreen-inverted-x: true - touchscreen-inverted-y: true - touchscreen-swapped-x-y: true - -required: - - compatible - - reg - - interrupts - -additionalProperties: false - -examples: - - | - #include - #include - - i2c { - #address-cells = <1>; - #size-cells = <0>; - - touchscreen@74 { - compatible = "azoteq,iqs550"; - reg = <0x74>; - interrupt-parent = <&gpio>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&gpio 22 (GPIO_ACTIVE_LOW | - GPIO_PUSH_PULL)>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - }; - }; - -... diff --git a/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma140.yaml b/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma140.yaml index 86a6d18f952..afeab49a954 100644 --- a/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma140.yaml +++ b/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma140.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cypress CY8CTMA140 series touchscreen controller maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: touchscreen.yaml# diff --git a/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma340.yaml b/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma340.yaml index 4dfbb93678b..a0b8c12977a 100644 --- a/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma340.yaml +++ b/dts/upstream/Bindings/input/touchscreen/cypress,cy8ctma340.yaml @@ -12,7 +12,7 @@ description: The Cypress CY8CTMA340 series (also known as "CYTTSP" after maintainers: - Javier Martinez Canillas - - Linus Walleij + - Linus Walleij allOf: - $ref: touchscreen.yaml# diff --git a/dts/upstream/Bindings/input/touchscreen/himax,hx83112b.yaml b/dts/upstream/Bindings/input/touchscreen/himax,hx83112b.yaml deleted file mode 100644 index f5cfacb5e96..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/himax,hx83112b.yaml +++ /dev/null @@ -1,64 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/input/touchscreen/himax,hx83112b.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Himax hx83112b touchscreen controller - -maintainers: - - Job Noorman - -allOf: - - $ref: touchscreen.yaml# - -properties: - compatible: - enum: - - himax,hx83100a - - himax,hx83112b - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - reset-gpios: - maxItems: 1 - - touchscreen-inverted-x: true - touchscreen-inverted-y: true - touchscreen-size-x: true - touchscreen-size-y: true - touchscreen-swapped-x-y: true - -additionalProperties: false - -required: - - compatible - - reg - - interrupts - - reset-gpios - - touchscreen-size-x - - touchscreen-size-y - -examples: - - | - #include - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; - touchscreen@48 { - compatible = "himax,hx83112b"; - reg = <0x48>; - interrupt-parent = <&tlmm>; - interrupts = <65 IRQ_TYPE_LEVEL_LOW>; - touchscreen-size-x = <1080>; - touchscreen-size-y = <2160>; - reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; - }; - }; - -... diff --git a/dts/upstream/Bindings/input/touchscreen/hynitron,cstxxx.yaml b/dts/upstream/Bindings/input/touchscreen/hynitron,cstxxx.yaml deleted file mode 100644 index 9cb5d4af00f..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/hynitron,cstxxx.yaml +++ /dev/null @@ -1,65 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/input/touchscreen/hynitron,cstxxx.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Hynitron cstxxx series touchscreen controller - -description: | - Bindings for Hynitron cstxxx series multi-touch touchscreen - controllers. - -maintainers: - - Chris Morgan - -allOf: - - $ref: touchscreen.yaml# - -properties: - compatible: - enum: - - hynitron,cst340 - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - reset-gpios: - maxItems: 1 - - touchscreen-size-x: true - touchscreen-size-y: true - touchscreen-inverted-x: true - touchscreen-inverted-y: true - touchscreen-swapped-x-y: true - -additionalProperties: false - -required: - - compatible - - reg - - interrupts - - reset-gpios - -examples: - - | - #include - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; - touchscreen@1a { - compatible = "hynitron,cst340"; - reg = <0x1a>; - interrupt-parent = <&gpio4>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <640>; - touchscreen-size-y = <480>; - }; - }; - -... diff --git a/dts/upstream/Bindings/input/touchscreen/ilitek_ts_i2c.yaml b/dts/upstream/Bindings/input/touchscreen/ilitek_ts_i2c.yaml deleted file mode 100644 index 9f732899975..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/ilitek_ts_i2c.yaml +++ /dev/null @@ -1,76 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/input/touchscreen/ilitek_ts_i2c.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Ilitek I2C Touchscreen Controller - -maintainers: - - Dmitry Torokhov - -allOf: - - $ref: touchscreen.yaml# - -properties: - compatible: - enum: - - ilitek,ili210x - - ilitek,ili2117 - - ilitek,ili2120 - - ilitek,ili2130 - - ilitek,ili2131 - - ilitek,ili2132 - - ilitek,ili2316 - - ilitek,ili2322 - - ilitek,ili2323 - - ilitek,ili2326 - - ilitek,ili251x - - ilitek,ili2520 - - ilitek,ili2521 - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - reset-gpios: - maxItems: 1 - - wakeup-source: - type: boolean - description: touchscreen can be used as a wakeup source. - - touchscreen-size-x: true - touchscreen-size-y: true - touchscreen-inverted-x: true - touchscreen-inverted-y: true - touchscreen-swapped-x-y: true - -additionalProperties: false - -required: - - compatible - - reg - - interrupts - -examples: - - | - #include - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; - - touchscreen@41 { - compatible = "ilitek,ili2520"; - reg = <0x41>; - - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - touchscreen-inverted-y; - wakeup-source; - }; - }; diff --git a/dts/upstream/Bindings/input/touchscreen/maxim,max11801.yaml b/dts/upstream/Bindings/input/touchscreen/maxim,max11801.yaml deleted file mode 100644 index 4f528d22019..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/maxim,max11801.yaml +++ /dev/null @@ -1,46 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/input/touchscreen/maxim,max11801.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MAXI MAX11801 Resistive touch screen controller with i2c interface - -maintainers: - - Frank Li - -properties: - compatible: - const: maxim,max11801 - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - -allOf: - - $ref: touchscreen.yaml - -required: - - compatible - - reg - - interrupts - -unevaluatedProperties: false - -examples: - - | - #include - - i2c { - #address-cells = <1>; - #size-cells = <0>; - - touchscreen@48 { - compatible = "maxim,max11801"; - reg = <0x48>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - }; - }; diff --git a/dts/upstream/Bindings/input/touchscreen/melfas,mip4_ts.yaml b/dts/upstream/Bindings/input/touchscreen/melfas,mip4_ts.yaml new file mode 100644 index 00000000000..314be65c56c --- /dev/null +++ b/dts/upstream/Bindings/input/touchscreen/melfas,mip4_ts.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/melfas,mip4_ts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MELFAS MIP4 Touchscreen + +maintainers: + - Ariel D'Alessandro + +properties: + compatible: + const: melfas,mip4_ts + + reg: + description: I2C address of the chip (0x48 or 0x34) + maxItems: 1 + + interrupts: + maxItems: 1 + + ce-gpios: + description: + GPIO connected to the CE (chip enable) pin of the chip (active high) + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@34 { + compatible = "melfas,mip4_ts"; + reg = <0x34>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + ce-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + }; + }; + +... diff --git a/dts/upstream/Bindings/input/touchscreen/melfas,mms114.yaml b/dts/upstream/Bindings/input/touchscreen/melfas,mms114.yaml index 90ebd4f8354..a8a93f75545 100644 --- a/dts/upstream/Bindings/input/touchscreen/melfas,mms114.yaml +++ b/dts/upstream/Bindings/input/touchscreen/melfas,mms114.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Melfas MMS114 family touchscreen controller maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: touchscreen.yaml# diff --git a/dts/upstream/Bindings/input/touchscreen/melfas_mip4.txt b/dts/upstream/Bindings/input/touchscreen/melfas_mip4.txt deleted file mode 100644 index b2ab5498e51..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/melfas_mip4.txt +++ /dev/null @@ -1,20 +0,0 @@ -* MELFAS MIP4 Touchscreen - -Required properties: -- compatible: must be "melfas,mip4_ts" -- reg: I2C slave address of the chip (0x48 or 0x34) -- interrupts: interrupt to which the chip is connected - -Optional properties: -- ce-gpios: GPIO connected to the CE (chip enable) pin of the chip - -Example: - i2c@00000000 { - touchscreen: melfas_mip4@48 { - compatible = "melfas,mip4_ts"; - reg = <0x48>; - interrupt-parent = <&gpio>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - ce-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/dts/upstream/Bindings/input/touchscreen/semtech,sx8654.yaml b/dts/upstream/Bindings/input/touchscreen/semtech,sx8654.yaml deleted file mode 100644 index b2554064b68..00000000000 --- a/dts/upstream/Bindings/input/touchscreen/semtech,sx8654.yaml +++ /dev/null @@ -1,52 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/input/touchscreen/semtech,sx8654.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Semtech SX8654 I2C Touchscreen Controller - -maintainers: - - Frank Li - -properties: - compatible: - enum: - - semtech,sx8650 - - semtech,sx8654 - - semtech,sx8655 - - semtech,sx8656 - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - reset-gpios: - maxItems: 1 - -required: - - compatible - - reg - - interrupts - -additionalProperties: false - -examples: - - | - #include - #include - - i2c { - #address-cells = <1>; - #size-cells = <0>; - - touchscreen@48 { - compatible = "semtech,sx8654"; - reg = <0x48>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - }; - }; diff --git a/dts/upstream/Bindings/input/touchscreen/st,stmfts.yaml b/dts/upstream/Bindings/input/touchscreen/st,stmfts.yaml index c593ae63d0e..12256ae7df9 100644 --- a/dts/upstream/Bindings/input/touchscreen/st,stmfts.yaml +++ b/dts/upstream/Bindings/input/touchscreen/st,stmfts.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST-Microelectronics FingerTip touchscreen controller maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The ST-Microelectronics FingerTip device provides a basic touchscreen diff --git a/dts/upstream/Bindings/input/touchscreen/trivial-touch.yaml b/dts/upstream/Bindings/input/touchscreen/trivial-touch.yaml new file mode 100644 index 00000000000..fa27c6754ca --- /dev/null +++ b/dts/upstream/Bindings/input/touchscreen/trivial-touch.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/trivial-touch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trivial touch screen controller with i2c interface + +maintainers: + - Frank Li + +properties: + compatible: + enum: + # The Azoteq IQS550, IQS572 and IQS525 trackpad and touchscreen controllers + - azoteq,iqs550 + - azoteq,iqs572 + - azoteq,iqs525 + # Himax hx83100a touchscreen controller + - himax,hx83100a + # Himax hx83112b touchscreen controller + - himax,hx83112b + # Hynitron cstxxx series touchscreen controller + - hynitron,cst340 + # Ilitek I2C Touchscreen Controller + - ilitek,ili210x + - ilitek,ili2117 + - ilitek,ili2120 + - ilitek,ili2130 + - ilitek,ili2131 + - ilitek,ili2132 + - ilitek,ili2316 + - ilitek,ili2322 + - ilitek,ili2323 + - ilitek,ili2326 + - ilitek,ili251x + - ilitek,ili2520 + - ilitek,ili2521 + # MAXI MAX11801 Resistive touch screen controller with i2c interface + - maxim,max11801 + # Microchip AR1020 and AR1021 touchscreen interface (I2C) + - microchip,ar1021-i2c + # Trivial touch screen controller with i2c interface + - semtech,sx8650 + - semtech,sx8654 + - semtech,sx8655 + - semtech,sx8656 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + wakeup-source: true + +allOf: + - $ref: touchscreen.yaml + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/dts/upstream/Bindings/input/touchscreen/zinitix,bt400.yaml b/dts/upstream/Bindings/input/touchscreen/zinitix,bt400.yaml index 3f663ce3e44..f1ce837b16d 100644 --- a/dts/upstream/Bindings/input/touchscreen/zinitix,bt400.yaml +++ b/dts/upstream/Bindings/input/touchscreen/zinitix,bt400.yaml @@ -12,7 +12,7 @@ description: The Zinitix BT4xx and BT5xx series of touchscreen controllers maintainers: - Michael Srba - - Linus Walleij + - Linus Walleij allOf: - $ref: touchscreen.yaml# diff --git a/dts/upstream/Bindings/input/twl4030-keypad.txt b/dts/upstream/Bindings/input/twl4030-keypad.txt deleted file mode 100644 index e4be2f76a71..00000000000 --- a/dts/upstream/Bindings/input/twl4030-keypad.txt +++ /dev/null @@ -1,27 +0,0 @@ -* TWL4030's Keypad Controller device tree bindings - -TWL4030's Keypad controller is used to interface a SoC with a matrix-type -keypad device. The keypad controller supports multiple row and column lines. -A key can be placed at each intersection of a unique row and a unique column. -The keypad controller can sense a key-press and key-release and report the -event using a interrupt to the cpu. - -This binding is based on the matrix-keymap binding with the following -changes: - - * keypad,num-rows and keypad,num-columns are required. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "ti,twl4030-keypad": For controllers compatible with twl4030 keypad - controller. -- interrupt: should be one of the following - - <1>: For controllers compatible with twl4030 keypad controller. - -Example: - twl_keypad: keypad { - compatible = "ti,twl4030-keypad"; - interrupts = <1>; - keypad,num-rows = <8>; - keypad,num-columns = <8>; - }; diff --git a/dts/upstream/Bindings/interconnect/qcom,kaanapali-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,kaanapali-rpmh.yaml new file mode 100644 index 00000000000..2c3b2fd81a7 --- /dev/null +++ b/dts/upstream/Bindings/interconnect/qcom,kaanapali-rpmh.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,kaanapali-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Kaanapali + +maintainers: + - Raviteja Laggyshetty + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h + +properties: + compatible: + enum: + - qcom,kaanapali-aggre-noc + - qcom,kaanapali-clk-virt + - qcom,kaanapali-cnoc-main + - qcom,kaanapali-cnoc-cfg + - qcom,kaanapali-gem-noc + - qcom,kaanapali-lpass-ag-noc + - qcom,kaanapali-lpass-lpiaon-noc + - qcom,kaanapali-lpass-lpicx-noc + - qcom,kaanapali-mc-virt + - qcom,kaanapali-mmss-noc + - qcom,kaanapali-nsp-noc + - qcom,kaanapali-pcie-anoc + - qcom,kaanapali-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-clk-virt + - qcom,kaanapali-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-aggre-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-aggre-noc + - qcom,kaanapali-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + clk_virt: interconnect-0 { + compatible = "qcom,kaanapali-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@16e0000 { + compatible = "qcom,kaanapali-aggre-noc"; + reg = <0x016e0000 0x42400>; + #interconnect-cells = <2>; + clocks = <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml index 256de140c03..17b09292000 100644 --- a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Interconnect Bandwidth Monitor maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: | Bandwidth Monitor measures current throughput on buses between various NoC @@ -25,6 +25,7 @@ properties: - const: qcom,msm8998-bwmon # BWMON v4 - items: - enum: + - qcom,kaanapali-cpu-bwmon - qcom,qcm2290-cpu-bwmon - qcom,qcs615-cpu-bwmon - qcom,qcs8300-cpu-bwmon diff --git a/dts/upstream/Bindings/interconnect/qcom,rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,rpmh.yaml index dad3ad2fd93..da16d8e9bdc 100644 --- a/dts/upstream/Bindings/interconnect/qcom,rpmh.yaml +++ b/dts/upstream/Bindings/interconnect/qcom,rpmh.yaml @@ -122,7 +122,6 @@ allOf: required: - reg - unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/interconnect/qcom,sa8775p-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sa8775p-rpmh.yaml index db19fd5c570..3dbe83e2de3 100644 --- a/dts/upstream/Bindings/interconnect/qcom,sa8775p-rpmh.yaml +++ b/dts/upstream/Bindings/interconnect/qcom,sa8775p-rpmh.yaml @@ -33,18 +33,97 @@ properties: - qcom,sa8775p-pcie-anoc - qcom,sa8775p-system-noc + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 5 + required: - compatible allOf: - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre QUP PRIM AXI clock + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre UFS CARD AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-config-noc + - qcom,sa8775p-dc-noc + - qcom,sa8775p-gem-noc + - qcom,sa8775p-gpdsp-anoc + - qcom,sa8775p-lpass-ag-noc + - qcom,sa8775p-mmss-noc + - qcom,sa8775p-nspa-noc + - qcom,sa8775p-nspb-noc + - qcom,sa8775p-pcie-anoc + - qcom,sa8775p-system-noc + then: + properties: + clocks: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-clk-virt + - qcom,sa8775p-mc-virt + then: + properties: + reg: false + clocks: false unevaluatedProperties: false examples: - | - aggre1_noc: interconnect-aggre1-noc { - compatible = "qcom,sa8775p-aggre1-noc"; + #include + clk_virt: interconnect-clk-virt { + compatible = "qcom,sa8775p-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; + + aggre1_noc: interconnect@16c0000 { + compatible = "qcom,sa8775p-aggre1-noc"; + reg = <0x016c0000 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; diff --git a/dts/upstream/Bindings/interconnect/qcom,sm6350-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sm6350-rpmh.yaml index 49eb156b08e..2dc16e4293a 100644 --- a/dts/upstream/Bindings/interconnect/qcom,sm6350-rpmh.yaml +++ b/dts/upstream/Bindings/interconnect/qcom,sm6350-rpmh.yaml @@ -12,9 +12,6 @@ maintainers: description: Qualcomm RPMh-based interconnect provider on SM6350. -allOf: - - $ref: qcom,rpmh-common.yaml# - properties: compatible: enum: @@ -30,7 +27,9 @@ properties: reg: maxItems: 1 - '#interconnect-cells': true + clocks: + minItems: 1 + maxItems: 2 patternProperties: '^interconnect-[a-z0-9\-]+$': @@ -46,8 +45,6 @@ patternProperties: - qcom,sm6350-clk-virt - qcom,sm6350-compute-noc - '#interconnect-cells': true - required: - compatible @@ -57,10 +54,54 @@ required: - compatible - reg +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6350-aggre1-noc + - qcom,sm6350-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false examples: - | + #include + #include + config_noc: interconnect@1500000 { compatible = "qcom,sm6350-config-noc"; reg = <0x01500000 0x28000>; @@ -68,14 +109,16 @@ examples: qcom,bcm-voters = <&apps_bcm_voter>; }; - system_noc: interconnect@1620000 { - compatible = "qcom,sm6350-system-noc"; - reg = <0x01620000 0x17080>; + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm6350-aggre2-noc"; + reg = <0x01700000 0x1f880>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; - clk_virt: interconnect-clk-virt { - compatible = "qcom,sm6350-clk-virt"; + compute_noc: interconnect-compute-noc { + compatible = "qcom,sm6350-compute-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; diff --git a/dts/upstream/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/dts/upstream/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml index 3d60d9e9e20..d0fad930de9 100644 --- a/dts/upstream/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml +++ b/dts/upstream/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -39,6 +39,9 @@ properties: - amlogic,a4-gpio-ao-intc - amlogic,a5-gpio-intc - amlogic,c3-gpio-intc + - amlogic,s6-gpio-intc + - amlogic,s7-gpio-intc + - amlogic,s7d-gpio-intc - amlogic,t7-gpio-intc - const: amlogic,meson-gpio-intc diff --git a/dts/upstream/Bindings/interrupt-controller/arm,gic-v3.yaml b/dts/upstream/Bindings/interrupt-controller/arm,gic-v3.yaml index f3247a47f9e..bfd30aae682 100644 --- a/dts/upstream/Bindings/interrupt-controller/arm,gic-v3.yaml +++ b/dts/upstream/Bindings/interrupt-controller/arm,gic-v3.yaml @@ -305,7 +305,6 @@ examples: }; }; - device@0 { reg = <0 4>; interrupts = <1 1 4 &part0>; diff --git a/dts/upstream/Bindings/interrupt-controller/arm,versatile-fpga-irq.yaml b/dts/upstream/Bindings/interrupt-controller/arm,versatile-fpga-irq.yaml index 8d581b3aac3..42ab873665e 100644 --- a/dts/upstream/Bindings/interrupt-controller/arm,versatile-fpga-irq.yaml +++ b/dts/upstream/Bindings/interrupt-controller/arm,versatile-fpga-irq.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Versatile FPGA IRQ Controller maintainers: - - Linus Walleij + - Linus Walleij description: One or more FPGA IRQ controllers can be synthesized in an ARM reference board diff --git a/dts/upstream/Bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/dts/upstream/Bindings/interrupt-controller/aspeed,ast2700-intc.yaml index 55636d06a67..258d21fe6e3 100644 --- a/dts/upstream/Bindings/interrupt-controller/aspeed,ast2700-intc.yaml +++ b/dts/upstream/Bindings/interrupt-controller/aspeed,ast2700-intc.yaml @@ -25,13 +25,14 @@ properties: interrupt-controller: true '#interrupt-cells': - const: 2 + const: 1 description: The first cell is the IRQ number, the second cell is the trigger type as defined in interrupt.txt in this directory. interrupts: - maxItems: 6 + minItems: 1 + maxItems: 10 description: | Depend to which INTC0 or INTC1 used. INTC0 and INTC1 are two kinds of interrupt controller with enable and raw @@ -53,7 +54,6 @@ properties: | |---... +---------+---module31 - required: - compatible - reg @@ -74,13 +74,17 @@ examples: interrupt-controller@12101b00 { compatible = "aspeed,ast2700-intc-ic"; reg = <0 0x12101b00 0 0x10>; - #interrupt-cells = <2>; + #interrupt-cells = <1>; interrupt-controller; interrupts = , , , , , - ; + , + , + , + , + ; }; }; diff --git a/dts/upstream/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml b/dts/upstream/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml index 5fda626c80c..2ff390c1705 100644 --- a/dts/upstream/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml +++ b/dts/upstream/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.yaml @@ -34,8 +34,6 @@ properties: required: - compatible - reg - - interrupt-controller - - '#interrupt-cells' additionalProperties: false diff --git a/dts/upstream/Bindings/interrupt-controller/faraday,ftintc010.yaml b/dts/upstream/Bindings/interrupt-controller/faraday,ftintc010.yaml index 980e5c45f25..e6495acea03 100644 --- a/dts/upstream/Bindings/interrupt-controller/faraday,ftintc010.yaml +++ b/dts/upstream/Bindings/interrupt-controller/faraday,ftintc010.yaml @@ -6,7 +6,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FTINTC010 interrupt controller maintainers: - - Linus Walleij + - Linus Walleij description: This interrupt controller is a stock IP block from Faraday Technology found diff --git a/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml b/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml index c49688be105..5c768c1e159 100644 --- a/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml +++ b/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml @@ -20,6 +20,7 @@ properties: - fsl,imx8qm-irqsteer - fsl,imx8qxp-irqsteer - fsl,imx94-irqsteer + - fsl,imx95-irqsteer - const: fsl,imx-irqsteer reg: @@ -87,6 +88,7 @@ allOf: - fsl,imx8mp-irqsteer - fsl,imx8qm-irqsteer - fsl,imx8qxp-irqsteer + - fsl,imx95-irqsteer then: required: - power-domains diff --git a/dts/upstream/Bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml b/dts/upstream/Bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml index fdc254f8d01..55b1ae863b9 100644 --- a/dts/upstream/Bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml +++ b/dts/upstream/Bindings/interrupt-controller/fsl,vf610-mscm-ir.yaml @@ -14,7 +14,6 @@ description: Vybrid SoC's but is only really useful in dual core configurations (VF6xx which comes with a Cortex-A5/Cortex-M4 combination). - maintainers: - Frank Li diff --git a/dts/upstream/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/dts/upstream/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml index a02a6b5af20..c375e08ba41 100644 --- a/dts/upstream/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml +++ b/dts/upstream/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx XScale Networking Processors Interrupt Controller maintainers: - - Linus Walleij + - Linus Walleij description: | This interrupt controller is found in the Intel IXP4xx processors. diff --git a/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml b/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml index 60441f0c5d7..f63b23f48d8 100644 --- a/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml +++ b/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml @@ -78,7 +78,6 @@ required: - '#interrupt-cells' - loongson,parent_int_map - unevaluatedProperties: false if: diff --git a/dts/upstream/Bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/dts/upstream/Bindings/interrupt-controller/mediatek,mtk-cirq.yaml index fdcb4d8db81..20dfffb34f0 100644 --- a/dts/upstream/Bindings/interrupt-controller/mediatek,mtk-cirq.yaml +++ b/dts/upstream/Bindings/interrupt-controller/mediatek,mtk-cirq.yaml @@ -18,7 +18,6 @@ description: flush command is executed. With CIRQ, MCUSYS can be completely turned off to improve the system power consumption without losing interrupts. - properties: compatible: items: diff --git a/dts/upstream/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/dts/upstream/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml index 4ff609faba3..d943ea820cd 100644 --- a/dts/upstream/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +++ b/dts/upstream/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -26,7 +26,6 @@ properties: - mscc,ocelot-icpu-intr - mscc,serval-icpu-intr - '#interrupt-cells': const: 1 diff --git a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f683d696909..388fc2c620c 100644 --- a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -58,12 +58,15 @@ properties: - const: andestech,nceplic100 - items: - enum: + - anlogic,dr1v90-plic - canaan,k210-plic - eswin,eic7700-plic + - microchip,pic64gx-plic - sifive,fu540-c000-plic - spacemit,k1-plic - starfive,jh7100-plic - starfive,jh7110-plic + - tenstorrent,blackhole-plic - const: sifive,plic-1.0.0 - items: - enum: @@ -75,6 +78,9 @@ properties: - sophgo,sg2044-plic - thead,th1520-plic - const: thead,c900-plic + - items: + - const: ultrarisc,dp1000-plic + - const: ultrarisc,cp100-plic - items: - const: sifive,plic-1.0.0 - const: riscv,plic0 diff --git a/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-mswi.yaml index d6fb08a5416..62fd220e126 100644 --- a/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-mswi.yaml +++ b/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-mswi.yaml @@ -4,18 +4,23 @@ $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device +title: ACLINT Machine-level Software Interrupt Device maintainers: - Inochi Amaoto properties: compatible: - items: - - enum: - - sophgo,sg2042-aclint-mswi - - sophgo,sg2044-aclint-mswi - - const: thead,c900-aclint-mswi + oneOf: + - items: + - enum: + - sophgo,sg2042-aclint-mswi + - sophgo,sg2044-aclint-mswi + - const: thead,c900-aclint-mswi + - items: + - enum: + - anlogic,dr1v90-aclint-mswi + - const: nuclei,ux900-aclint-mswi reg: maxItems: 1 diff --git a/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-sswi.yaml index c1ab865fcd6..d02c6886283 100644 --- a/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-sswi.yaml +++ b/dts/upstream/Bindings/interrupt-controller/thead,c900-aclint-sswi.yaml @@ -30,6 +30,10 @@ properties: - const: thead,c900-aclint-sswi - items: - const: mips,p8700-aclint-sswi + - items: + - enum: + - anlogic,dr1v90-aclint-sswi + - const: nuclei,ux900-aclint-sswi reg: maxItems: 1 diff --git a/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml b/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml index 6e3d6e6d9e0..61b30a7732e 100644 --- a/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml +++ b/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI OMAP4 Wake-up Generator maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: > All TI OMAP4/5 (and their derivatives) are interrupt controllers that route diff --git a/dts/upstream/Bindings/iommu/arm,smmu.yaml b/dts/upstream/Bindings/iommu/arm,smmu.yaml index 89495f094d5..cdbd23b5c08 100644 --- a/dts/upstream/Bindings/iommu/arm,smmu.yaml +++ b/dts/upstream/Bindings/iommu/arm,smmu.yaml @@ -35,6 +35,8 @@ properties: - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: + - qcom,glymur-smmu-500 + - qcom,kaanapali-smmu-500 - qcom,milos-smmu-500 - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 @@ -89,6 +91,8 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: + - qcom,glymur-smmu-500 + - qcom,kaanapali-smmu-500 - qcom,milos-smmu-500 - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 @@ -638,7 +642,6 @@ examples: <&smmu1 7>; }; - /* SMMU with stream matching */ smmu2: iommu@ba5f0000 { compatible = "arm,smmu-v1"; @@ -664,7 +667,6 @@ examples: iommus = <&smmu2 1 0x30>; }; - /* ARM MMU-500 with 10-bit stream ID input configuration */ smmu3: iommu@ba600000 { compatible = "arm,mmu-500", "arm,smmu-v2"; @@ -685,8 +687,6 @@ examples: /* bus whose child devices emit one unique 10-bit stream ID each, but may master through multiple SMMU TBUs */ iommu-map = <0 &smmu3 0 0x400>; - - }; - |+ diff --git a/dts/upstream/Bindings/iommu/mediatek,iommu.yaml b/dts/upstream/Bindings/iommu/mediatek,iommu.yaml index f49ed8ac477..79c573c47b0 100644 --- a/dts/upstream/Bindings/iommu/mediatek,iommu.yaml +++ b/dts/upstream/Bindings/iommu/mediatek,iommu.yaml @@ -82,6 +82,9 @@ properties: - mediatek,mt8188-iommu-vdo # generation two - mediatek,mt8188-iommu-vpp # generation two - mediatek,mt8188-iommu-infra # generation two + - mediatek,mt8189-iommu-apu # generation two + - mediatek,mt8189-iommu-infra # generation two + - mediatek,mt8189-iommu-mm # generation two - mediatek,mt8192-m4u # generation two - mediatek,mt8195-iommu-vdo # generation two - mediatek,mt8195-iommu-vpp # generation two @@ -128,6 +131,7 @@ properties: This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as defined in dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188, + dt-binding/memory/mediatek,mt8189-memory-port.h for mt8189, dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, @@ -164,6 +168,7 @@ allOf: - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo - mediatek,mt8188-iommu-vpp + - mediatek,mt8189-iommu-mm - mediatek,mt8192-m4u - mediatek,mt8195-iommu-vdo - mediatek,mt8195-iommu-vpp @@ -180,6 +185,7 @@ allOf: - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo - mediatek,mt8188-iommu-vpp + - mediatek,mt8189-iommu-mm - mediatek,mt8192-m4u - mediatek,mt8195-iommu-vdo - mediatek,mt8195-iommu-vpp @@ -208,6 +214,8 @@ allOf: contains: enum: - mediatek,mt8188-iommu-infra + - mediatek,mt8189-iommu-apu + - mediatek,mt8189-iommu-infra - mediatek,mt8195-iommu-infra then: diff --git a/dts/upstream/Bindings/iommu/qcom,iommu.yaml b/dts/upstream/Bindings/iommu/qcom,iommu.yaml index 3e5623edd20..93a48902531 100644 --- a/dts/upstream/Bindings/iommu/qcom,iommu.yaml +++ b/dts/upstream/Bindings/iommu/qcom,iommu.yaml @@ -32,14 +32,18 @@ properties: - const: qcom,msm-iommu-v2 clocks: + minItems: 2 items: - description: Clock required for IOMMU register group access - description: Clock required for underlying bus access + - description: Clock required for Translation Buffer Unit access clock-names: + minItems: 2 items: - const: iface - const: bus + - const: tbu power-domains: maxItems: 1 diff --git a/dts/upstream/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/dts/upstream/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt deleted file mode 100644 index 25f86da804b..00000000000 --- a/dts/upstream/Bindings/ipmi/aspeed,ast2400-ibt-bmc.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Aspeed BT (Block Transfer) IPMI interface - -The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs -(BaseBoard Management Controllers) and the BT interface can be used to -perform in-band IPMI communication with their host. - -Required properties: - -- compatible : should be one of - "aspeed,ast2400-ibt-bmc" - "aspeed,ast2500-ibt-bmc" - "aspeed,ast2600-ibt-bmc" -- reg: physical address and size of the registers -- clocks: clock for the device - -Optional properties: - -- interrupts: interrupt generated by the BT interface. without an - interrupt, the driver will operate in poll mode. - -Example: - - ibt@1e789140 { - compatible = "aspeed,ast2400-ibt-bmc"; - reg = <0x1e789140 0x18>; - interrupts = <8>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - }; diff --git a/dts/upstream/Bindings/ipmi/aspeed,ast2400-ibt-bmc.yaml b/dts/upstream/Bindings/ipmi/aspeed,ast2400-ibt-bmc.yaml new file mode 100644 index 00000000000..c4f7cdbbe16 --- /dev/null +++ b/dts/upstream/Bindings/ipmi/aspeed,ast2400-ibt-bmc.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-ibt-bmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Block Transfer (BT) IPMI interface + +maintainers: + - Joel Stanley + +properties: + compatible: + enum: + - aspeed,ast2400-ibt-bmc + - aspeed,ast2500-ibt-bmc + - aspeed,ast2600-ibt-bmc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + + bt@1e789140 { + compatible = "aspeed,ast2400-ibt-bmc"; + reg = <0x1e789140 0x18>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + }; diff --git a/dts/upstream/Bindings/ipmi/npcm7xx-kcs-bmc.txt b/dts/upstream/Bindings/ipmi/npcm7xx-kcs-bmc.txt deleted file mode 100644 index 4fda76e6339..00000000000 --- a/dts/upstream/Bindings/ipmi/npcm7xx-kcs-bmc.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Nuvoton NPCM KCS (Keyboard Controller Style) IPMI interface - -The Nuvoton SOCs (NPCM) are commonly used as BMCs -(Baseboard Management Controllers) and the KCS interface can be -used to perform in-band IPMI communication with their host. - -Required properties: -- compatible : should be one of - "nuvoton,npcm750-kcs-bmc" - "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc" -- interrupts : interrupt generated by the controller -- kcs_chan : The KCS channel number in the controller - -Example: - - lpc_kcs: lpc_kcs@f0007000 { - compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; - reg = <0xf0007000 0x40>; - reg-io-width = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf0007000 0x40>; - - kcs1: kcs1@0 { - compatible = "nuvoton,npcm750-kcs-bmc"; - reg = <0x0 0x40>; - interrupts = <0 9 4>; - kcs_chan = <1>; - status = "disabled"; - }; - - kcs2: kcs2@0 { - compatible = "nuvoton,npcm750-kcs-bmc"; - reg = <0x0 0x40>; - interrupts = <0 9 4>; - kcs_chan = <2>; - status = "disabled"; - }; - }; diff --git a/dts/upstream/Bindings/ipmi/nuvoton,npcm750-kcs-bmc.yaml b/dts/upstream/Bindings/ipmi/nuvoton,npcm750-kcs-bmc.yaml new file mode 100644 index 00000000000..fc5df1c5e3b --- /dev/null +++ b/dts/upstream/Bindings/ipmi/nuvoton,npcm750-kcs-bmc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ipmi/nuvoton,npcm750-kcs-bmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM KCS BMC + +maintainers: + - Avi Fishman + - Tomer Maimon + - Tali Perry + +description: + The Nuvoton SOCs (NPCM) are commonly used as BMCs (Baseboard Management + Controllers) and the KCS interface can be used to perform in-band IPMI + communication with their host. + +properties: + compatible: + oneOf: + - const: nuvoton,npcm750-kcs-bmc + - items: + - enum: + - nuvoton,npcm845-kcs-bmc + - const: nuvoton,npcm750-kcs-bmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + kcs_chan: + description: The KCS channel number in the controller + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 3 + +required: + - compatible + - reg + - interrupts + - kcs_chan + +additionalProperties: false + +examples: + - | + kcs@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = <9 4>; + kcs_chan = <1>; + }; diff --git a/dts/upstream/Bindings/leds/backlight/arc,arc2c0608.yaml b/dts/upstream/Bindings/leds/backlight/arc,arc2c0608.yaml new file mode 100644 index 00000000000..786beced559 --- /dev/null +++ b/dts/upstream/Bindings/leds/backlight/arc,arc2c0608.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/arc,arc2c0608.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ArcticSand arc2c0608 LED driver + +description: | + The ArcticSand arc2c0608 LED driver provides ultra + efficient notebook backlighting. Optional properties not + specified will default to values in IC EPROM. + + Datasheet: + https://www.murata.com/-/media/webrenewal/products/power/power-semiconductor/overview/lineup/led-boost/arc2/arc2c0608.ashx. + +maintainers: + - Brian Dodge + +allOf: + - $ref: /schemas/leds/common.yaml + +properties: + compatible: + const: arc,arc2c0608 + + reg: + maxItems: 1 + + default-brightness: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4095 + + led-sources: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: List of enabled channels + items: + enum: [0, 1, 2, 3, 4, 5] + minItems: 1 + uniqueItems: true + + arc,led-config-0: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Fading speed (period between intensity + steps) + + arc,led-config-1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: If set, sets ILED_CONFIG register. Used for + fine tuning the maximum LED current. + + arc,dim-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PWM mode frequency setting (bits [3:0] used) + + arc,comp-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Setting for register CONFIG_COMP which + controls internal resitances, feed forward freqs, + and initial VOUT at startup. Consult the datasheet. + + arc,filter-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: RC and PWM Filter settings. + Bit Assignment + 7654 3 2 1 0 + xxxx RCF1 RCF0 PWM1 PWM0 + RCF statuses PWM Filter Statues + 00 = OFF (default) 00 = OFF (default) + 01 = LOW 01 = 2 STEPS + 10 - MEDIUM 10 = 4 STEPS + 11 = HIGH 11 = 8 STEPS + + arc,trim-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Sets percentage increase of Maximum LED + Current. + 0x00 = 0% increase. + 0x20 = 20.2%. + 0x3F = 41.5% + + label: true + + linux,default-trigger: true + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@30 { + compatible = "arc,arc2c0608"; + reg = <0x30>; + default-brightness = <500>; + label = "lcd-backlight"; + linux,default-trigger = "backlight"; + led-sources = <0 1 2 5>; + }; + }; +... diff --git a/dts/upstream/Bindings/leds/backlight/arcxcnn_bl.txt b/dts/upstream/Bindings/leds/backlight/arcxcnn_bl.txt deleted file mode 100644 index 230abdefd6e..00000000000 --- a/dts/upstream/Bindings/leds/backlight/arcxcnn_bl.txt +++ /dev/null @@ -1,33 +0,0 @@ -Binding for ArcticSand arc2c0608 LED driver - -Required properties: -- compatible: should be "arc,arc2c0608" -- reg: slave address - -Optional properties: -- default-brightness: brightness value on boot, value from: 0-4095 -- label: The name of the backlight device - See Documentation/devicetree/bindings/leds/common.txt -- led-sources: List of enabled channels from 0 to 5. - See Documentation/devicetree/bindings/leds/common.txt - -- arc,led-config-0: setting for register ILED_CONFIG_0 -- arc,led-config-1: setting for register ILED_CONFIG_1 -- arc,dim-freq: PWM mode frequence setting (bits [3:0] used) -- arc,comp-config: setting for register CONFIG_COMP -- arc,filter-config: setting for register FILTER_CONFIG -- arc,trim-config: setting for register IMAXTUNE - -Note: Optional properties not specified will default to values in IC EPROM - -Example: - -arc2c0608@30 { - compatible = "arc,arc2c0608"; - reg = <0x30>; - default-brightness = <500>; - label = "lcd-backlight"; - linux,default-trigger = "backlight"; - led-sources = <0 1 2 5>; -}; - diff --git a/dts/upstream/Bindings/leds/backlight/awinic,aw99706.yaml b/dts/upstream/Bindings/leds/backlight/awinic,aw99706.yaml new file mode 100644 index 00000000000..f48ce7a3434 --- /dev/null +++ b/dts/upstream/Bindings/leds/backlight/awinic,aw99706.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/awinic,aw99706.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW99706 6-channel WLED Backlight Driver + +maintainers: + - Junjie Cao + +allOf: + - $ref: common.yaml# + +properties: + compatible: + const: awinic,aw99706 + + reg: + maxItems: 1 + + enable-gpios: + description: GPIO to use to enable/disable the backlight (HWEN pin). + maxItems: 1 + + awinic,dim-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Select dimming mode of the device. + 0 = Bypass mode. + 1 = DC mode. + 2 = MIX mode(PWM at low brightness and DC at high brightness). + 3 = MIX-26k mode(MIX mode with different PWM frequency). + enum: [ 0, 1, 2, 3 ] + default: 1 + + awinic,sw-freq-hz: + description: Boost switching frequency in Hz. + enum: [ 300000, 400000, 500000, 600000, 660000, 750000, 850000, 1000000, + 1200000, 1330000, 1500000, 1700000 ] + default: 750000 + + awinic,sw-ilmt-microamp: + description: Switching current limitation in uA. + enum: [ 1500000, 2000000, 2500000, 3000000 ] + default: 3000000 + + awinic,iled-max-microamp: + description: Maximum LED current setting in uA. + minimum: 5000 + maximum: 50000 + multipleOf: 500 + default: 20000 + + awinic,uvlo-thres-microvolt: + description: UVLO(Under Voltage Lock Out) in uV. + enum: [ 2200000, 5000000 ] + default: 2200000 + + awinic,ramp-ctl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Select ramp control and filter of the device. + 0 = Fade in/fade out. + 1 = Light filter. + 2 = Medium filter. + 3 = Heavy filter. + enum: [ 0, 1, 2, 3 ] + default: 2 + +required: + - compatible + - reg + - enable-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + backlight@76 { + compatible = "awinic,aw99706"; + reg = <0x76>; + enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + default-brightness = <2047>; + max-brightness = <4095>; + awinic,dim-mode = <1>; + awinic,sw-freq-hz = <750000>; + awinic,sw-ilmt-microamp = <3000000>; + awinic,uvlo-thres-microvolt = <2200000>; + awinic,iled-max-microamp = <20000>; + awinic,ramp-ctl = <2>; + }; + }; + +... diff --git a/dts/upstream/Bindings/leds/backlight/kinetic,ktd253.yaml b/dts/upstream/Bindings/leds/backlight/kinetic,ktd253.yaml index 73fa59e6218..e7207eb2658 100644 --- a/dts/upstream/Bindings/leds/backlight/kinetic,ktd253.yaml +++ b/dts/upstream/Bindings/leds/backlight/kinetic,ktd253.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Kinetic Technologies KTD253 and KTD259 one-wire backlight maintainers: - - Linus Walleij + - Linus Walleij description: | The Kinetic Technologies KTD253 and KTD259 are white LED backlights diff --git a/dts/upstream/Bindings/leds/common.yaml b/dts/upstream/Bindings/leds/common.yaml index 274f83288a9..f4e44b33f56 100644 --- a/dts/upstream/Bindings/leds/common.yaml +++ b/dts/upstream/Bindings/leds/common.yaml @@ -173,6 +173,12 @@ properties: led-max-microamp. $ref: /schemas/types.yaml#/definitions/uint32 + default-brightness: + description: + Brightness to be set if LED's default state is on. Used only during + initialization. If the option is not set then max brightness is used. + $ref: /schemas/types.yaml#/definitions/uint32 + panic-indicator: description: This property specifies that the LED should be used, if at all possible, diff --git a/dts/upstream/Bindings/leds/leds-pwm.yaml b/dts/upstream/Bindings/leds/leds-pwm.yaml index 61b97e8bc36..6c4fcefbe25 100644 --- a/dts/upstream/Bindings/leds/leds-pwm.yaml +++ b/dts/upstream/Bindings/leds/leds-pwm.yaml @@ -40,6 +40,13 @@ patternProperties: initialization. If the option is not set then max brightness is used. $ref: /schemas/types.yaml#/definitions/uint32 + enable-gpios: + description: + GPIO for LED hardware enable control. Set active when brightness is + non-zero and inactive when brightness is zero. + The GPIO default state follows the "default-state" property. + maxItems: 1 + required: - pwms - max-brightness diff --git a/dts/upstream/Bindings/leds/leds-qcom-lpg.yaml b/dts/upstream/Bindings/leds/leds-qcom-lpg.yaml index 841a0229c47..c4b7e57b251 100644 --- a/dts/upstream/Bindings/leds/leds-qcom-lpg.yaml +++ b/dts/upstream/Bindings/leds/leds-qcom-lpg.yaml @@ -13,6 +13,11 @@ description: > The Qualcomm Light Pulse Generator consists of three different hardware blocks; a ramp generator with lookup table (LUT), the light pulse generator and a three channel current sink. These blocks are found in a wide range of Qualcomm PMICs. + The light pulse generator (LPG) can also be used independently to output PWM + signal for standard PWM applications. In this scenario, the LPG output should + be routed to a specific PMIC GPIO by setting the GPIO pin mux to the special + functions indicated in the datasheet, the TRILED driver for the channel will + not be enabled in this configuration. properties: compatible: diff --git a/dts/upstream/Bindings/leds/qcom,pm8058-led.yaml b/dts/upstream/Bindings/leds/qcom,pm8058-led.yaml index fa03e73622d..b409b2a8b5c 100644 --- a/dts/upstream/Bindings/leds/qcom,pm8058-led.yaml +++ b/dts/upstream/Bindings/leds/qcom,pm8058-led.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PM8058 PMIC LED maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: | The Qualcomm PM8058 contains an LED block for up to six LEDs:: three normal diff --git a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml index bcf0ad4ea57..05250aefd38 100644 --- a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml +++ b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml @@ -24,6 +24,7 @@ properties: - enum: - qcom,pm6150l-flash-led - qcom,pm660l-flash-led + - qcom,pm7550-flash-led - qcom,pm8150c-flash-led - qcom,pm8150l-flash-led - qcom,pm8350c-flash-led diff --git a/dts/upstream/Bindings/leds/register-bit-led.yaml b/dts/upstream/Bindings/leds/register-bit-led.yaml index 20930d327ae..a6bafc96bd0 100644 --- a/dts/upstream/Bindings/leds/register-bit-led.yaml +++ b/dts/upstream/Bindings/leds/register-bit-led.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Register Bit LEDs maintainers: - - Linus Walleij + - Linus Walleij description: |+ Register bit leds are used with syscon multifunctional devices where single diff --git a/dts/upstream/Bindings/leds/regulator-led.yaml b/dts/upstream/Bindings/leds/regulator-led.yaml index 4ef7b96e9a0..75ee87d4a78 100644 --- a/dts/upstream/Bindings/leds/regulator-led.yaml +++ b/dts/upstream/Bindings/leds/regulator-led.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Regulator LEDs maintainers: - - Linus Walleij + - Linus Walleij description: | Regulator LEDs are powered by a single regulator such that they can diff --git a/dts/upstream/Bindings/leds/richtek,rt8515.yaml b/dts/upstream/Bindings/leds/richtek,rt8515.yaml index 68c328eec03..0356371a6b0 100644 --- a/dts/upstream/Bindings/leds/richtek,rt8515.yaml +++ b/dts/upstream/Bindings/leds/richtek,rt8515.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Richtek RT8515 1.5A dual channel LED driver maintainers: - - Linus Walleij + - Linus Walleij description: | The Richtek RT8515 is a dual channel (two mode) LED driver that diff --git a/dts/upstream/Bindings/mailbox/apm,xgene-slimpro-mbox.yaml b/dts/upstream/Bindings/mailbox/apm,xgene-slimpro-mbox.yaml new file mode 100644 index 00000000000..815f08d61de --- /dev/null +++ b/dts/upstream/Bindings/mailbox/apm,xgene-slimpro-mbox.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/apm,xgene-slimpro-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SLIMpro mailbox + +maintainers: + - Khuong Dinh + +description: + The APM X-Gene SLIMpro mailbox is used to communicate messages between + the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple + interrupt based door bell mechanism and can exchange simple messages using the + internal registers. + +properties: + compatible: + const: apm,xgene-slimpro-mbox + + reg: + maxItems: 1 + + interrupts: + items: + - description: mailbox channel 0 doorbell + - description: mailbox channel 1 doorbell + - description: mailbox channel 2 doorbell + - description: mailbox channel 3 doorbell + - description: mailbox channel 4 doorbell + - description: mailbox channel 5 doorbell + - description: mailbox channel 6 doorbell + - description: mailbox channel 7 doorbell + + '#mbox-cells': + description: Number of mailbox channel. + const: 1 + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + mailbox@10540000 { + compatible = "apm,xgene-slimpro-mbox"; + reg = <0x10540000 0xa000>; + #mbox-cells = <1>; + interrupts = <0x0 0x0 0x4>, + <0x0 0x1 0x4>, + <0x0 0x2 0x4>, + <0x0 0x3 0x4>, + <0x0 0x4 0x4>, + <0x0 0x5 0x4>, + <0x0 0x6 0x4>, + <0x0 0x7 0x4>; + }; diff --git a/dts/upstream/Bindings/mailbox/arm,mhu.yaml b/dts/upstream/Bindings/mailbox/arm,mhu.yaml index d9a4f4a02d7..e45b661e8b4 100644 --- a/dts/upstream/Bindings/mailbox/arm,mhu.yaml +++ b/dts/upstream/Bindings/mailbox/arm,mhu.yaml @@ -52,7 +52,6 @@ properties: - const: arm,mhu-doorbell - const: arm,primecell - reg: maxItems: 1 diff --git a/dts/upstream/Bindings/mailbox/arm,mhuv2.yaml b/dts/upstream/Bindings/mailbox/arm,mhuv2.yaml index 02f06314d85..3828d77f631 100644 --- a/dts/upstream/Bindings/mailbox/arm,mhuv2.yaml +++ b/dts/upstream/Bindings/mailbox/arm,mhuv2.yaml @@ -127,7 +127,6 @@ properties: - minimum: 0 maximum: 124 - '#mbox-cells': description: | It is always set to 2. The first argument in the consumers 'mboxes' diff --git a/dts/upstream/Bindings/mailbox/mtk,adsp-mbox.yaml b/dts/upstream/Bindings/mailbox/mtk,adsp-mbox.yaml index 8a1369df4ec..4ca0d5e49c7 100644 --- a/dts/upstream/Bindings/mailbox/mtk,adsp-mbox.yaml +++ b/dts/upstream/Bindings/mailbox/mtk,adsp-mbox.yaml @@ -26,7 +26,6 @@ properties: - mediatek,mt8188-adsp-mbox - const: mediatek,mt8186-adsp-mbox - "#mbox-cells": const: 0 diff --git a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml index 615ed103b7e..f40dc904832 100644 --- a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -187,10 +187,10 @@ allOf: enum: - qcom,msm8916-apcs-kpss-global then: - $ref: "#/$defs/msm8916-apcs-clock-controller" + $ref: '#/$defs/msm8916-apcs-clock-controller' properties: clock-controller: - $ref: "#/$defs/msm8916-apcs-clock-controller" + $ref: '#/$defs/msm8916-apcs-clock-controller' - if: properties: @@ -199,10 +199,10 @@ allOf: enum: - qcom,msm8939-apcs-kpss-global then: - $ref: "#/$defs/msm8939-apcs-clock-controller" + $ref: '#/$defs/msm8939-apcs-clock-controller' properties: clock-controller: - $ref: "#/$defs/msm8939-apcs-clock-controller" + $ref: '#/$defs/msm8939-apcs-clock-controller' - if: properties: @@ -211,10 +211,10 @@ allOf: enum: - qcom,sdx55-apcs-gcc then: - $ref: "#/$defs/sdx55-apcs-clock-controller" + $ref: '#/$defs/sdx55-apcs-clock-controller' properties: clock-controller: - $ref: "#/$defs/sdx55-apcs-clock-controller" + $ref: '#/$defs/sdx55-apcs-clock-controller' - if: properties: @@ -223,10 +223,10 @@ allOf: enum: - qcom,ipq6018-apcs-apps-global then: - $ref: "#/$defs/ipq6018-apcs-clock-controller" + $ref: '#/$defs/ipq6018-apcs-clock-controller' properties: clock-controller: - $ref: "#/$defs/ipq6018-apcs-clock-controller" + $ref: '#/$defs/ipq6018-apcs-clock-controller' - if: properties: diff --git a/dts/upstream/Bindings/mailbox/xgene-slimpro-mailbox.txt b/dts/upstream/Bindings/mailbox/xgene-slimpro-mailbox.txt deleted file mode 100644 index e46451bb242..00000000000 --- a/dts/upstream/Bindings/mailbox/xgene-slimpro-mailbox.txt +++ /dev/null @@ -1,35 +0,0 @@ -The APM X-Gene SLIMpro mailbox is used to communicate messages between -the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple -interrupt based door bell mechanism and can exchange simple messages using the -internal registers. - -There are total of 8 interrupts in this mailbox. Each used for an individual -door bell (or mailbox channel). - -Required properties: -- compatible: Should be as "apm,xgene-slimpro-mbox". - -- reg: Contains the mailbox register address range. - -- interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the - the interrupt for mailbox channel 0 and interrupt 1 for - mailbox channel 1 and so likewise for the reminder. - -- #mbox-cells: only one to specify the mailbox channel number. - -Example: - -Mailbox Node: - mailbox: mailbox@10540000 { - compatible = "apm,xgene-slimpro-mbox"; - reg = <0x0 0x10540000 0x0 0xa000>; - #mbox-cells = <1>; - interrupts = <0x0 0x0 0x4>, - <0x0 0x1 0x4>, - <0x0 0x2 0x4>, - <0x0 0x3 0x4>, - <0x0 0x4 0x4>, - <0x0 0x5 0x4>, - <0x0 0x6 0x4>, - <0x0 0x7 0x4>, - }; diff --git a/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml index fe83b5cb127..04d6473d666 100644 --- a/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml +++ b/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml @@ -142,7 +142,7 @@ patternProperties: - compatible - reg - reg-names - - "#mbox-cells" + - '#mbox-cells' - xlnx,ipi-id required: diff --git a/dts/upstream/Bindings/media/amphion,vpu.yaml b/dts/upstream/Bindings/media/amphion,vpu.yaml index 5a920d9e78c..fa18013d705 100644 --- a/dts/upstream/Bindings/media/amphion,vpu.yaml +++ b/dts/upstream/Bindings/media/amphion,vpu.yaml @@ -45,7 +45,6 @@ patternProperties: between driver and firmware. Implement via mailbox on driver. $ref: /schemas/mailbox/fsl,mu.yaml# - "^vpu-core@[0-9a-f]+$": description: Each core correspond a decoder or encoder, need to configure them diff --git a/dts/upstream/Bindings/media/arm,mali-c55.yaml b/dts/upstream/Bindings/media/arm,mali-c55.yaml new file mode 100644 index 00000000000..fc4fcd19922 --- /dev/null +++ b/dts/upstream/Bindings/media/arm,mali-c55.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/arm,mali-c55.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Mali-C55 Image Signal Processor + +maintainers: + - Daniel Scally + - Jacopo Mondi + +properties: + compatible: + const: arm,mali-c55 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ISP Video Clock + - description: ISP AXI clock + - description: ISP AHB-lite clock + + clock-names: + items: + - const: vclk + - const: aclk + - const: hclk + + resets: + items: + - description: vclk domain reset + - description: aclk domain reset + - description: hclk domain reset + + reset-names: + items: + - const: vresetn + - const: aresetn + - const: hresetn + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Input parallel video bus + + properties: + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - port + +additionalProperties: false + +examples: + - | + #include + + isp@400000 { + compatible = "arm,mali-c55"; + reg = <0x400000 0x200000>; + clocks = <&clk 0>, <&clk 1>, <&clk 2>; + clock-names = "vclk", "aclk", "hclk"; + resets = <&resets 0>, <&resets 1>, <&resets 2>; + reset-names = "vresetn", "aresetn", "hresetn"; + interrupts = ; + + port { + isp_in: endpoint { + remote-endpoint = <&csi2_rx_out>; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/media/fsl,imx6q-vdoa.yaml b/dts/upstream/Bindings/media/fsl,imx6q-vdoa.yaml index 511ac0d67a7..988a5b3a62b 100644 --- a/dts/upstream/Bindings/media/fsl,imx6q-vdoa.yaml +++ b/dts/upstream/Bindings/media/fsl,imx6q-vdoa.yaml @@ -16,7 +16,7 @@ maintainers: properties: compatible: - const: "fsl,imx6q-vdoa" + const: fsl,imx6q-vdoa reg: maxItems: 1 diff --git a/dts/upstream/Bindings/media/i2c/adi,adv7604.yaml b/dts/upstream/Bindings/media/i2c/adi,adv7604.yaml index 2dc2829d42a..f8d9889dbc2 100644 --- a/dts/upstream/Bindings/media/i2c/adi,adv7604.yaml +++ b/dts/upstream/Bindings/media/i2c/adi,adv7604.yaml @@ -154,7 +154,5 @@ examples: }; }; }; - - }; }; diff --git a/dts/upstream/Bindings/media/i2c/dongwoon,dw9719.yaml b/dts/upstream/Bindings/media/i2c/dongwoon,dw9719.yaml new file mode 100644 index 00000000000..8e8d62436e0 --- /dev/null +++ b/dts/upstream/Bindings/media/i2c/dongwoon,dw9719.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/dongwoon,dw9719.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dongwoon Anatech DW9719 Voice Coil Motor (VCM) Controller + +maintainers: + - André Apitzsch + +description: + The Dongwoon DW9718S/9719/9761 is a single 10-bit digital-to-analog converter + with 100 mA output current sink capability, designed for linear control of + voice coil motors (VCM) in camera lenses. This chip provides a Smart Actuator + Control (SAC) mode intended for driving voice coil lenses in camera modules. + +properties: + compatible: + enum: + - dongwoon,dw9718s + - dongwoon,dw9719 + - dongwoon,dw9761 + - dongwoon,dw9800k + + reg: + maxItems: 1 + + vdd-supply: + description: VDD power supply + + dongwoon,sac-mode: + description: | + Slew Rate Control mode to use: direct, LSC (Linear Slope Control) or + SAC1-SAC6 (Smart Actuator Control). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # Direct mode + - 1 # LSC mode + - 2 # SAC1 mode (operation time# 0.32 x Tvib) + - 3 # SAC2 mode (operation time# 0.48 x Tvib) + - 4 # SAC3 mode (operation time# 0.72 x Tvib) + - 5 # SAC4 mode (operation time# 1.20 x Tvib) + - 6 # SAC5 mode (operation time# 1.64 x Tvib) + - 7 # SAC6 mode (operation time# 1.88 x Tvib) + default: 4 + + dongwoon,vcm-prescale: + description: + Indication of VCM switching frequency dividing rate select. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - vdd-supply + +allOf: + - if: + properties: + compatible: + contains: + const: dongwoon,dw9718s + then: + properties: + dongwoon,vcm-prescale: + description: + The final frequency is 10 MHz divided by (value + 2). + maximum: 15 + default: 0 + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + actuator@c { + compatible = "dongwoon,dw9718s"; + reg = <0x0c>; + + vdd-supply = <&pm8937_l17>; + + dongwoon,sac-mode = <4>; + dongwoon,vcm-prescale = <0>; + }; + }; diff --git a/dts/upstream/Bindings/media/i2c/nxp,tda19971.yaml b/dts/upstream/Bindings/media/i2c/nxp,tda19971.yaml new file mode 100644 index 00000000000..477e59316df --- /dev/null +++ b/dts/upstream/Bindings/media/i2c/nxp,tda19971.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/nxp,tda19971.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP TDA1997x HDMI receiver + +maintainers: + - Frank Li + +description: | + The TDA19971/73 are HDMI video receivers. + + The TDA19971 Video port output pins can be used as follows: + - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4] + - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4] + - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4] + - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2] + - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0] + - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles) + - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles) + - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) + + The TDA19973 Video port output pins can be used as follows: + - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0] + - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0] + - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0] + - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) + + The Video port output pins are mapped via 4-bit 'pin groups' allowing + for a variety of connection possibilities including swapping pin order within + pin groups. The video_portcfg device-tree property consists of register mapping + pairs which map a chip-specific VP output register to a 4-bit pin group. If + the pin group needs to be bit-swapped you can use the *_S pin-group defines. + +properties: + compatible: + enum: + - nxp,tda19971 + - nxp,tda19973 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + DOVDD-supply: true + + DVDD-supply: true + + AVDD-supply: true + + '#sound-dai-cells': + const: 0 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + nxp,vidout-portcfg: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 4 + items: + items: + - description: Video Port control registers index. + maximum: 8 + minimum: 0 + - description: pin(pinswapped) groups + + description: + array of pairs mapping VP output pins to pin groups. + + nxp,audout-format: + enum: + - i2s + - spdif + + nxp,audout-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 24, 32] + description: + width of audio output data bus. + + nxp,audout-layout: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used). + + nxp,audout-mclk-fs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Multiplication factor between stream rate and codec mclk. + +required: + - compatible + - reg + - interrupts + - DOVDD-supply + - AVDD-supply + - DVDD-supply + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hdmi-receiver@48 { + compatible = "nxp,tda19971"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + /* audio */ + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same pixclk cycle. + */ + nxp,vidout-portcfg = + /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/media/i2c/nxp,tda1997x.txt b/dts/upstream/Bindings/media/i2c/nxp,tda1997x.txt deleted file mode 100644 index e76167999d7..00000000000 --- a/dts/upstream/Bindings/media/i2c/nxp,tda1997x.txt +++ /dev/null @@ -1,178 +0,0 @@ -Device-Tree bindings for the NXP TDA1997x HDMI receiver - -The TDA19971/73 are HDMI video receivers. - -The TDA19971 Video port output pins can be used as follows: - - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4] - - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4] - - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4] - - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2] - - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0] - - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles) - - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles) - - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) - -The TDA19973 Video port output pins can be used as follows: - - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0] - - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0] - - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0] - - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) - -The Video port output pins are mapped via 4-bit 'pin groups' allowing -for a variety of connection possibilities including swapping pin order within -pin groups. The video_portcfg device-tree property consists of register mapping -pairs which map a chip-specific VP output register to a 4-bit pin group. If -the pin group needs to be bit-swapped you can use the *_S pin-group defines. - -Required Properties: - - compatible : - - "nxp,tda19971" for the TDA19971 - - "nxp,tda19973" for the TDA19973 - - reg : I2C slave address - - interrupts : The interrupt number - - DOVDD-supply : Digital I/O supply - - DVDD-supply : Digital Core supply - - AVDD-supply : Analog supply - - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups. - -Optional Properties: - - nxp,audout-format : DAI bus format: "i2s" or "spdif". - - nxp,audout-width : width of audio output data bus (1-4). - - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used). - - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec - mclk. - -The port node shall contain one endpoint child node for its digital -output video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Optional Endpoint Properties: - The following three properties are defined in video-interfaces.txt and - are valid for the output parallel bus endpoint: - - hsync-active: Horizontal synchronization polarity. Defaults to active high. - - vsync-active: Vertical synchronization polarity. Defaults to active high. - - data-active: Data polarity. Defaults to active high. - -Examples: - - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422 - 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) - hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <®_1p8v>; - DVDD-supply = <®_1p8v>; - /* audio */ - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same pixclk cycle. - */ - nxp,vidout-portcfg = - /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; - - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 - 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) - hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <®_1p8v>; - DVDD-supply = <®_1p8v>; - /* audio */ - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] - * and Y[11:4] across 16bits in the same pixclk cycle. - */ - nxp,vidout-portcfg = - /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ - < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, - /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ - < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, - /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ - < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, - /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ - < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; - - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 - 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) - hdmi-receiver@48 { - compatible = "nxp,tda19971"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tda1997x>; - reg = <0x48>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - DOVDD-supply = <®_3p3v>; - AVDD-supply = <®_1p8v>; - DVDD-supply = <®_1p8v>; - /* audio */ - #sound-dai-cells = <0>; - nxp,audout-format = "i2s"; - nxp,audout-layout = <0>; - nxp,audout-width = <16>; - nxp,audout-mclk-fs = <128>; - /* - * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over - * 2 pixclk cycles. - */ - nxp,vidout-portcfg = - /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ - < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >, - /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ - < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >, - - port { - tda1997x_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <16>; - hsync-active = <1>; - vsync-active = <1>; - data-active = <1>; - }; - }; - }; diff --git a/dts/upstream/Bindings/media/i2c/samsung,s5k5baf.yaml b/dts/upstream/Bindings/media/i2c/samsung,s5k5baf.yaml index ebd95a8d9b2..4cb0f5aa130 100644 --- a/dts/upstream/Bindings/media/i2c/samsung,s5k5baf.yaml +++ b/dts/upstream/Bindings/media/i2c/samsung,s5k5baf.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC ISP maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski properties: compatible: diff --git a/dts/upstream/Bindings/media/i2c/samsung,s5k6a3.yaml b/dts/upstream/Bindings/media/i2c/samsung,s5k6a3.yaml index e563e35920c..9df1e0f872f 100644 --- a/dts/upstream/Bindings/media/i2c/samsung,s5k6a3.yaml +++ b/dts/upstream/Bindings/media/i2c/samsung,s5k6a3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S5K6A3(YX) raw image sensor maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data diff --git a/dts/upstream/Bindings/media/i2c/sony,imx111.yaml b/dts/upstream/Bindings/media/i2c/sony,imx111.yaml new file mode 100644 index 00000000000..20f48d5e9b2 --- /dev/null +++ b/dts/upstream/Bindings/media/i2c/sony,imx111.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx111.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX111 8MP CMOS Digital Image Sensor + +maintainers: + - Svyatoslav Ryhel + +description: + IMX111 sensor is a Sony CMOS active pixel digital image sensor with an active + array size of 2464H x 3280V. It is programmable through I2C interface. Image + data is sent through MIPI CSI-2, through 1 or 2 lanes. + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + - $ref: /schemas/nvmem/nvmem-consumer.yaml# + +properties: + compatible: + const: sony,imx111 + + reg: + maxItems: 1 + + clocks: + description: EXTCLK with possible frequency from 6 to 54 MHz + maxItems: 1 + + reset-gpios: + maxItems: 1 + + iovdd-supply: + description: Digital IO power supply (1.8V) + + dvdd-supply: + description: Digital power supply (1.2V) + + avdd-supply: + description: Analog power supply (2.7V) + + port: + additionalProperties: false + $ref: /schemas/graph.yaml#/$defs/port-base + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - data-lanes + - link-frequencies + + required: + - endpoint + +required: + - compatible + - reg + - clocks + - port + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@10 { + compatible = "sony,imx111"; + reg = <0x10>; + + clocks = <&imx111_clk>; + + iovdd-supply = <&camera_vddio_1v8>; + dvdd-supply = <&camera_vddd_1v2>; + avdd-supply = <&camera_vdda_2v7>; + + orientation = <1>; + rotation = <90>; + + nvmem = <&eeprom>; + flash-leds = <&led>; + lens-focus = <&vcm>; + + reset-gpios = <&gpio 84 GPIO_ACTIVE_LOW>; + + port { + imx111_output: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <542400000>; + remote-endpoint = <&csi_input>; + }; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/media/i2c/st,vd55g1.yaml b/dts/upstream/Bindings/media/i2c/st,vd55g1.yaml index 3c071e6fbea..060ac6829b6 100644 --- a/dts/upstream/Bindings/media/i2c/st,vd55g1.yaml +++ b/dts/upstream/Bindings/media/i2c/st,vd55g1.yaml @@ -25,7 +25,11 @@ allOf: properties: compatible: - const: st,vd55g1 + enum: + - st,vd55g1 + - st,vd65g4 + description: + VD55G1 is the monochrome variant, while VD65G4 is the color one. reg: maxItems: 1 diff --git a/dts/upstream/Bindings/media/i2c/techwell,tw9900.yaml b/dts/upstream/Bindings/media/i2c/techwell,tw9900.yaml index c9673391afd..0592d0b9af9 100644 --- a/dts/upstream/Bindings/media/i2c/techwell,tw9900.yaml +++ b/dts/upstream/Bindings/media/i2c/techwell,tw9900.yaml @@ -70,7 +70,6 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Video port for the decoder output. - required: - port@0 - port@1 diff --git a/dts/upstream/Bindings/media/i2c/ti,tvp5150.txt b/dts/upstream/Bindings/media/i2c/ti,tvp5150.txt deleted file mode 100644 index 94b908ace53..00000000000 --- a/dts/upstream/Bindings/media/i2c/ti,tvp5150.txt +++ /dev/null @@ -1,157 +0,0 @@ -* Texas Instruments TVP5150 and TVP5151 video decoders - -The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL -(and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV -with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats. - -Required Properties: -==================== -- compatible: Value must be "ti,tvp5150". -- reg: I2C slave address. - -Optional Properties: -==================== -- pdn-gpios: Phandle for the GPIO connected to the PDN pin, if any. -- reset-gpios: Phandle for the GPIO connected to the RESETB pin, if any. - -The device node must contain one 'port' child node per device physical input -and output port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes -are numbered as follows - - Name Type Port - -------------------------------------- - AIP1A sink 0 - AIP1B sink 1 - Y-OUT src 2 - -The device node must contain at least one sink port and the src port. Each input -port must be linked to an endpoint defined in [1]. The port/connector layout is -as follows - -tvp-5150 port@0 (AIP1A) - endpoint@0 -----------> Comp0-Con port - endpoint@1 ------+----> Svideo-Con port -tvp-5150 port@1 (AIP1B) | - endpoint@1 ------+ - endpoint@0 -----------> Comp1-Con port -tvp-5150 port@2 - endpoint (video bitstream output at YOUT[0-7] parallel bus) - -Required Endpoint Properties for parallel synchronization on output port: -========================================================================= - -- hsync-active: Active state of the HSYNC signal. Must be <1> (HIGH). -- vsync-active: Active state of the VSYNC signal. Must be <1> (HIGH). -- field-even-active: Field signal level during the even field data - transmission. Must be <0>. - -Note: Do not specify any of these properties if you want to use the embedded - BT.656 synchronization. - -Optional Connector Properties: -============================== - -- sdtv-standards: Set the possible signals to which the hardware tries to lock - instead of using the autodetection mechanism. Please look at - [1] for more information. - -[1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml. - -Example - three input sources: -#include - -comp_connector_0 { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; /* limit to pal-m signals */ - - port { - composite0_to_tvp5150: endpoint { - remote-endpoint = <&tvp5150_to_composite0>; - }; - }; -}; - -comp_connector_1 { - compatible = "composite-video-connector"; - label = "Composite1"; - sdtv-standards = ; /* limit to ntsc-m signals */ - - port { - composite1_to_tvp5150: endpoint { - remote-endpoint = <&tvp5150_to_composite1>; - }; - }; -}; - -svideo_connector { - compatible = "svideo-connector"; - label = "S-Video"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - svideo_luma_to_tvp5150: endpoint@0 { - reg = <0>; - remote-endpoint = <&tvp5150_to_svideo_luma>; - }; - - svideo_chroma_to_tvp5150: endpoint@1 { - reg = <1>; - remote-endpoint = <&tvp5150_to_svideo_chroma>; - }; - }; -}; - -&i2c2 { - tvp5150@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tvp5150_to_composite0: endpoint@0 { - reg = <0>; - remote-endpoint = <&composite0_to_tvp5150>; - }; - - tvp5150_to_svideo_luma: endpoint@1 { - reg = <1>; - remote-endpoint = <&svideo_luma_to_tvp5150>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tvp5150_to_composite1: endpoint@0 { - reg = <0>; - remote-endpoint = <&composite1_to_tvp5150>; - }; - - tvp5150_to_svideo_chroma: endpoint@1 { - reg = <1>; - remote-endpoint = <&svideo_chroma_to_tvp5150>; - }; - }; - - port@2 { - reg = <2>; - - tvp5150_1: endpoint { - remote-endpoint = <&ccdc_ep>; - }; - }; - }; -}; diff --git a/dts/upstream/Bindings/media/i2c/ti,tvp5150.yaml b/dts/upstream/Bindings/media/i2c/ti,tvp5150.yaml new file mode 100644 index 00000000000..382a29652a0 --- /dev/null +++ b/dts/upstream/Bindings/media/i2c/ti,tvp5150.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ti,tvp5150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TVP5150 and TVP5151 video decoders + +maintainers: + - Frank Li + +description: + The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL + (and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV + with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats. + +properties: + compatible: + const: ti,tvp5150 + + reg: + maxItems: 1 + + pdn-gpios: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + sink port node, AIP1A + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + sink port node, AIP1B + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + source port node, Y-OUT + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - port@2 + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&composite0_to_tvp5150>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&svideo_luma_to_tvp5150>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&composite1_to_tvp5150>; + }; + + endpoint@1 { + reg = <1>; + remote-endpoint = <&svideo_chroma_to_tvp5150>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&ccdc_ep>; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/media/mediatek,mt8173-mdp.yaml b/dts/upstream/Bindings/media/mediatek,mt8173-mdp.yaml new file mode 100644 index 00000000000..8ca33a733c4 --- /dev/null +++ b/dts/upstream/Bindings/media/mediatek,mt8173-mdp.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8173 Media Data Path + +maintainers: + - Ariel D'Alessandro + +description: + Media Data Path is used for scaling and color space conversion. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt8173-mdp-rdma + - mediatek,mt8173-mdp-rsz + - mediatek,mt8173-mdp-wdma + - mediatek,mt8173-mdp-wrot + - items: + - const: mediatek,mt8173-mdp-rdma + - const: mediatek,mt8173-mdp + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + mediatek,vpu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to Mediatek Video Processor Unit for HW Codec encode/decode and + image processing. + +required: + - compatible + - reg + - clocks + - power-domains + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-mdp-rdma + then: + properties: + clocks: + items: + - description: Main clock + - description: Mutex clock + else: + properties: + clocks: + items: + - description: Main clock + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8173-mdp-rdma + - mediatek,mt8173-mdp-wdma + - mediatek,mt8173-mdp-wrot + then: + required: + - iommus + + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-mdp + then: + required: + - mediatek,vpu + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + mdp_rdma0: rdma@14001000 { + compatible = "mediatek,mt8173-mdp-rdma", + "mediatek,mt8173-mdp"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,vpu = <&vpu>; + }; + + mdp_rdma1: rdma@14002000 { + compatible = "mediatek,mt8173-mdp-rdma"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA1>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA1>; + }; + + mdp_rsz0: rsz@14003000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz1: rsz@14004000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz2: rsz@14005000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ2>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_wdma0: wdma@14006000 { + compatible = "mediatek,mt8173-mdp-wdma"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WDMA>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WDMA>; + }; + + mdp_wrot0: wrot@14007000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp_wrot1: wrot@14008000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14008000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT1>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT1>; + }; + }; + +... diff --git a/dts/upstream/Bindings/media/mediatek-mdp.txt b/dts/upstream/Bindings/media/mediatek-mdp.txt deleted file mode 100644 index 253a93eabb5..00000000000 --- a/dts/upstream/Bindings/media/mediatek-mdp.txt +++ /dev/null @@ -1,96 +0,0 @@ -* Mediatek Media Data Path - -Media Data Path is used for scaling and color space conversion. - -Required properties (controller node): -- compatible: "mediatek,mt8173-mdp" -- mediatek,vpu: the node of video processor unit, see - Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml for - details. - -Required properties (all function blocks, child node): -- compatible: Should be one of - "mediatek,mt8173-mdp-rdma" - read DMA - "mediatek,mt8173-mdp-rsz" - resizer - "mediatek,mt8173-mdp-wdma" - write DMA - "mediatek,mt8173-mdp-wrot" - write DMA with rotation -- reg: Physical base address and length of the function block register space -- clocks: device clocks, see - Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- power-domains: a phandle to the power domain, see - Documentation/devicetree/bindings/power/power_domain.txt for details. - -Required properties (DMA function blocks, child node): -- compatible: Should be one of - "mediatek,mt8173-mdp-rdma" - "mediatek,mt8173-mdp-wdma" - "mediatek,mt8173-mdp-wrot" -- iommus: should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml - for details. - -Example: - mdp_rdma0: rdma@14001000 { - compatible = "mediatek,mt8173-mdp-rdma"; - "mediatek,mt8173-mdp"; - reg = <0 0x14001000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,vpu = <&vpu>; - }; - - mdp_rdma1: rdma@14002000 { - compatible = "mediatek,mt8173-mdp-rdma"; - reg = <0 0x14002000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA1>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA1>; - }; - - mdp_rsz0: rsz@14003000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14003000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz1: rsz@14004000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14004000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz2: rsz@14005000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14005000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_wdma0: wdma@14006000 { - compatible = "mediatek,mt8173-mdp-wdma"; - reg = <0 0x14006000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WDMA>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WDMA>; - }; - - mdp_wrot0: wrot@14007000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14007000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT0>; - }; - - mdp_wrot1: wrot@14008000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14008000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT1>; - }; diff --git a/dts/upstream/Bindings/media/nxp,imx8-isi.yaml b/dts/upstream/Bindings/media/nxp,imx8-isi.yaml index f43b91984f0..001a0d9b71e 100644 --- a/dts/upstream/Bindings/media/nxp,imx8-isi.yaml +++ b/dts/upstream/Bindings/media/nxp,imx8-isi.yaml @@ -22,6 +22,7 @@ properties: - fsl,imx8mn-isi - fsl,imx8mp-isi - fsl,imx8ulp-isi + - fsl,imx91-isi - fsl,imx93-isi reg: @@ -66,7 +67,6 @@ required: - interrupts - clocks - clock-names - - fsl,blk-ctrl - ports allOf: @@ -77,6 +77,7 @@ allOf: enum: - fsl,imx8mn-isi - fsl,imx8ulp-isi + - fsl,imx91-isi - fsl,imx93-isi then: properties: @@ -109,6 +110,16 @@ allOf: - port@0 - port@1 + - if: + properties: + compatible: + not: + contains: + const: fsl,imx91-isi + then: + required: + - fsl,blk-ctrl + additionalProperties: false examples: diff --git a/dts/upstream/Bindings/media/nxp,imx8-jpeg.yaml b/dts/upstream/Bindings/media/nxp,imx8-jpeg.yaml index 4cba42ba7cf..b5aca3d2cc5 100644 --- a/dts/upstream/Bindings/media/nxp,imx8-jpeg.yaml +++ b/dts/upstream/Bindings/media/nxp,imx8-jpeg.yaml @@ -79,7 +79,6 @@ allOf: power-domains: minItems: 2 # Wrapper and 1 slot - additionalProperties: false examples: diff --git a/dts/upstream/Bindings/media/qcom,msm8939-camss.yaml b/dts/upstream/Bindings/media/qcom,msm8939-camss.yaml new file mode 100644 index 00000000000..77b389d76a4 --- /dev/null +++ b/dts/upstream/Bindings/media/qcom,msm8939-camss.yaml @@ -0,0 +1,254 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,msm8939-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8939 Camera Subsystem (CAMSS) + +maintainers: + - Vincent Knecht + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms + +properties: + compatible: + const: qcom,msm8939-camss + + reg: + maxItems: 11 + + reg-names: + items: + - const: csiphy0 + - const: csiphy0_clk_mux + - const: csiphy1 + - const: csiphy1_clk_mux + - const: csid0 + - const: csid1 + - const: ispif + - const: csi_clk_mux + - const: vfe0 + - const: csid2 + - const: vfe0_vbif + + clocks: + maxItems: 24 + + clock-names: + items: + - const: top_ahb + - const: ispif_ahb + - const: csiphy0_timer + - const: csiphy1_timer + - const: csi0_ahb + - const: csi0 + - const: csi0_phy + - const: csi0_pix + - const: csi0_rdi + - const: csi1_ahb + - const: csi1 + - const: csi1_phy + - const: csi1_pix + - const: csi1_rdi + - const: ahb + - const: vfe0 + - const: csi_vfe0 + - const: vfe_ahb + - const: vfe_axi + - const: csi2_ahb + - const: csi2 + - const: csi2_phy + - const: csi2_pix + - const: csi2_rdi + + interrupts: + maxItems: 7 + + interrupt-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csid0 + - const: csid1 + - const: ispif + - const: vfe0 + - const: csid2 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: VFE GDSC - Video Front End, Global Distributed Switch + Controller. + + vdda-supply: + description: + Definition of the regulator used as 1.2V analog power supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-1]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - power-domains + - vdda-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + isp@1b0ac00 { + compatible = "qcom,msm8939-camss"; + + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>, + <0x01b08800 0x100>, + <0x01b40000 0x200>; + + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "ispif", + "csi_clk_mux", + "vfe0", + "csid2", + "vfe0_vbif"; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PHY_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>; + + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi"; + + interrupts = , + , + , + , + , + , + ; + + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "ispif", + "vfe0", + "csid2"; + + iommus = <&apps_iommu 3>; + + power-domains = <&gcc VFE_GDSC>; + + vdda-supply = <®_1v2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 2>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml b/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml index d195f1bfb23..c99fe4106ee 100644 --- a/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml +++ b/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml @@ -484,7 +484,6 @@ examples: "gcc_axi_hf", "gcc_axi_sf"; - iommus = <&apps_smmu 0x2000 0x4e0>, <&apps_smmu 0x2020 0x4e0>, <&apps_smmu 0x2040 0x4e0>, diff --git a/dts/upstream/Bindings/media/qcom,sm8650-camss.yaml b/dts/upstream/Bindings/media/qcom,sm8650-camss.yaml new file mode 100644 index 00000000000..9c8de722601 --- /dev/null +++ b/dts/upstream/Bindings/media/qcom,sm8650-camss.yaml @@ -0,0 +1,375 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 Camera Subsystem (CAMSS) + +maintainers: + - Vladimir Zapolskiy + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8650-camss + + reg: + maxItems: 17 + + reg-names: + items: + - const: csid_wrapper + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 33 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: cpas_vfe_lite + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: qdss_debug_xo + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 16 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + + iommus: + maxItems: 3 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + + vdd-csiphy01-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. + + vdd-csiphy01-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks. + + vdd-csiphy24-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. + + vdd-csiphy24-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks. + + vdd-csiphy35-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. + + vdd-csiphy35-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb6000 { + compatible = "qcom,sm8650-camss"; + reg = <0 0x0acb6000 0 0x1000>, + <0 0x0acb8000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbc000 0 0x1000>, + <0 0x0accb000 0 0x1000>, + <0 0x0acd0000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accc000 0 0x2000>, + <0 0x0acd1000 0 0x2000>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy_rx", + "gcc_axi_hf", + "qdss_debug_xo", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 + &mc_virt SLAVE_EBI1 0>; + interconnect-names = "ahb", "hf_mnoc"; + iommus = <&apps_smmu 0x800 0x20>, + <&apps_smmu 0x18a0 0x40>, + <&apps_smmu 0x1860 0x00>; + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", "ife1", "ife2", "top"; + vdd-csiphy01-0p9-supply = <&vreg_0p9>; + vdd-csiphy01-1p2-supply = <&vreg_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&camera_sensor>; + }; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/media/qcom,sm8750-iris.yaml b/dts/upstream/Bindings/media/qcom,sm8750-iris.yaml index c9a0fcafe53..c42d3470bda 100644 --- a/dts/upstream/Bindings/media/qcom,sm8750-iris.yaml +++ b/dts/upstream/Bindings/media/qcom,sm8750-iris.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SM8750 SoC Iris video encoder and decoder maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The Iris video processing unit on Qualcomm SM8750 SoC is a video encode and diff --git a/dts/upstream/Bindings/media/qcom,x1e80100-camss.yaml b/dts/upstream/Bindings/media/qcom,x1e80100-camss.yaml index b075341caaf..b87a13479a4 100644 --- a/dts/upstream/Bindings/media/qcom,x1e80100-camss.yaml +++ b/dts/upstream/Bindings/media/qcom,x1e80100-camss.yaml @@ -124,7 +124,7 @@ properties: vdd-csiphy-1p2-supply: description: - Phandle to 1.8V regulator supply to a PHY. + Phandle to 1.2V regulator supply to a PHY. ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/upstream/Bindings/media/renesas,r9a09g057-ivc.yaml b/dts/upstream/Bindings/media/renesas,r9a09g057-ivc.yaml new file mode 100644 index 00000000000..c09cbd8c9e3 --- /dev/null +++ b/dts/upstream/Bindings/media/renesas,r9a09g057-ivc.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/renesas,r9a09g057-ivc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) Input Video Control Block + +maintainers: + - Daniel Scally + +description: + The IVC block is a module that takes video frames from memory and feeds them + to the Image Signal Processor for processing. + +properties: + compatible: + const: renesas,r9a09g057-ivc # RZ/V2H(P) + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Input Video Control block register access clock + - description: Video input data AXI bus clock + - description: ISP system clock + + clock-names: + items: + - const: reg + - const: axi + - const: isp + + power-domains: + maxItems: 1 + + resets: + items: + - description: Input Video Control block register access reset + - description: Video input data AXI bus reset + - description: ISP core reset + + reset-names: + items: + - const: reg + - const: axi + - const: isp + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Output parallel video bus + + properties: + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + - reset-names + - port + +additionalProperties: false + +examples: + - | + #include + #include + + isp-input@16040000 { + compatible = "renesas,r9a09g057-ivc"; + reg = <0x16040000 0x230>; + + clocks = <&cpg CPG_MOD 0xe3>, + <&cpg CPG_MOD 0xe4>, + <&cpg CPG_MOD 0xe5>; + clock-names = "reg", "axi", "isp"; + + power-domains = <&cpg>; + + resets = <&cpg 0xd4>, + <&cpg 0xd1>, + <&cpg 0xd3>; + reset-names = "reg", "axi", "isp"; + + interrupts = ; + + port { + ivc_out: endpoint { + remote-endpoint = <&isp_in>; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/media/rockchip,px30-vip.yaml b/dts/upstream/Bindings/media/rockchip,px30-vip.yaml new file mode 100644 index 00000000000..cc08ce94bef --- /dev/null +++ b/dts/upstream/Bindings/media/rockchip,px30-vip.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PX30 Video Input Processor (VIP) + +maintainers: + - Mehdi Djait + - Michael Riesch + +description: + The Rockchip PX30 Video Input Processor (VIP) receives the data from a camera + sensor or CCIR656 encoder and transfers it into system main memory by AXI bus. + +properties: + compatible: + const: rockchip,px30-vip + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: PCLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: pclk + + resets: + items: + - description: AXI + - description: AHB + - description: PCLK IN + + reset-names: + items: + - const: axi + - const: ahb + - const: pclkin + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: input port on the parallel interface + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: + - 5 # MEDIA_BUS_TYPE_PARALLEL + - 6 # MEDIA_BUS_TYPE_BT656 + + required: + - bus-type + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - clocks + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + video-capture@ff490000 { + compatible = "rockchip,px30-vip"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names = "aclk", "hclk", "pclk"; + power-domains = <&power PX30_PD_VI>; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "axi", "ahb", "pclkin"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + cif_in: endpoint { + remote-endpoint = <&tw9900_out>; + bus-type = ; + }; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/media/rockchip,rk3568-vicap.yaml b/dts/upstream/Bindings/media/rockchip,rk3568-vicap.yaml new file mode 100644 index 00000000000..18cd0a5a531 --- /dev/null +++ b/dts/upstream/Bindings/media/rockchip,rk3568-vicap.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,rk3568-vicap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Video Capture (VICAP) + +maintainers: + - Michael Riesch + +description: + The Rockchip RK3568 Video Capture (VICAP) block features a digital video + port (DVP, a parallel video interface) and a MIPI CSI-2 port. It receives + the data from camera sensors, video decoders, or other companion ICs and + transfers it into system main memory by AXI bus. + +properties: + compatible: + const: rockchip,rk3568-vicap + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: DCLK + - description: ICLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: dclk + - const: iclk + + iommus: + maxItems: 1 + + resets: + items: + - description: ARST + - description: HRST + - description: DRST + - description: PRST + - description: IRST + + reset-names: + items: + - const: arst + - const: hrst + - const: drst + - const: prst + - const: irst + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to general register file used for video input block control. + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: The digital video port (DVP, a parallel video interface). + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-type: + enum: + - 5 # MEDIA_BUS_TYPE_PARALLEL + - 6 # MEDIA_BUS_TYPE_BT656 + + rockchip,dvp-clk-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + minimum: 0 + maximum: 127 + description: + Delay the DVP path clock input to align the sampling phase, + only valid in dual edge sampling mode. Delay is zero by + default and can be adjusted optionally. + + required: + - bus-type + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + vicap: video-capture@fdfe0000 { + compatible = "rockchip,rk3568-vicap"; + reg = <0x0 0xfdfe0000 0x0 0x200>; + interrupts = ; + assigned-clocks = <&cru DCLK_VICAP>; + assigned-clock-rates = <300000000>; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; + clock-names = "aclk", "hclk", "dclk", "iclk"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3568_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, + <&cru SRST_I_VICAP>; + reset-names = "arst", "hrst", "drst", "prst", "irst"; + rockchip,grf = <&grf>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@0 { + reg = <0>; + + vicap_dvp_input: endpoint { + bus-type = ; + bus-width = <16>; + pclk-sample = ; + remote-endpoint = <&it6801_output>; + }; + }; + + vicap_mipi: port@1 { + reg = <1>; + + vicap_mipi_input: endpoint { + remote-endpoint = <&csi_output>; + }; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/media/rockchip,vdec.yaml b/dts/upstream/Bindings/media/rockchip,vdec.yaml index 96b6c893876..809fda45b3b 100644 --- a/dts/upstream/Bindings/media/rockchip,vdec.yaml +++ b/dts/upstream/Bindings/media/rockchip,vdec.yaml @@ -16,6 +16,7 @@ description: |- properties: compatible: oneOf: + - const: rockchip,rk3288-vdec - const: rockchip,rk3399-vdec - const: rockchip,rk3576-vdec - const: rockchip,rk3588-vdec diff --git a/dts/upstream/Bindings/media/samsung,exynos4210-csis.yaml b/dts/upstream/Bindings/media/samsung,exynos4210-csis.yaml index dd6cc7ac1f7..2ddca4167b0 100644 --- a/dts/upstream/Bindings/media/samsung,exynos4210-csis.yaml +++ b/dts/upstream/Bindings/media/samsung,exynos4210-csis.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Sylwester Nawrocki properties: diff --git a/dts/upstream/Bindings/media/samsung,exynos4210-fimc.yaml b/dts/upstream/Bindings/media/samsung,exynos4210-fimc.yaml index 2ba27b23055..17ece4eb300 100644 --- a/dts/upstream/Bindings/media/samsung,exynos4210-fimc.yaml +++ b/dts/upstream/Bindings/media/samsung,exynos4210-fimc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S5P/Exynos SoC Fully Integrated Mobile Camera maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Sylwester Nawrocki description: diff --git a/dts/upstream/Bindings/media/samsung,exynos4212-fimc-is.yaml b/dts/upstream/Bindings/media/samsung,exynos4212-fimc-is.yaml index 71d63bb9abb..c8894358c46 100644 --- a/dts/upstream/Bindings/media/samsung,exynos4212-fimc-is.yaml +++ b/dts/upstream/Bindings/media/samsung,exynos4212-fimc-is.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung Exynos4212/4412 SoC Imaging Subsystem (FIMC-IS) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Sylwester Nawrocki description: @@ -111,7 +111,6 @@ patternProperties: reg: maxItems: 1 - clocks: maxItems: 1 diff --git a/dts/upstream/Bindings/media/samsung,exynos4212-fimc-lite.yaml b/dts/upstream/Bindings/media/samsung,exynos4212-fimc-lite.yaml index f80eca0a4f4..bda72489729 100644 --- a/dts/upstream/Bindings/media/samsung,exynos4212-fimc-lite.yaml +++ b/dts/upstream/Bindings/media/samsung,exynos4212-fimc-lite.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung Exynos SoC series camera host interface (FIMC-LITE) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Sylwester Nawrocki description: diff --git a/dts/upstream/Bindings/media/samsung,fimc.yaml b/dts/upstream/Bindings/media/samsung,fimc.yaml index 2a54379d950..1bfba84f885 100644 --- a/dts/upstream/Bindings/media/samsung,fimc.yaml +++ b/dts/upstream/Bindings/media/samsung,fimc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S5P/Exynos SoC Camera Subsystem (FIMC) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Sylwester Nawrocki description: | diff --git a/dts/upstream/Bindings/media/samsung,s5c73m3.yaml b/dts/upstream/Bindings/media/samsung,s5c73m3.yaml index 1b75390fdaa..1af5d7ac382 100644 --- a/dts/upstream/Bindings/media/samsung,s5c73m3.yaml +++ b/dts/upstream/Bindings/media/samsung,s5c73m3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S5C73M3 8Mp camera ISP maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Sylwester Nawrocki description: diff --git a/dts/upstream/Bindings/media/samsung,s5pv210-jpeg.yaml b/dts/upstream/Bindings/media/samsung,s5pv210-jpeg.yaml index e28d6ec56c0..5c969e764d4 100644 --- a/dts/upstream/Bindings/media/samsung,s5pv210-jpeg.yaml +++ b/dts/upstream/Bindings/media/samsung,s5pv210-jpeg.yaml @@ -42,7 +42,6 @@ properties: reg: maxItems: 1 - required: - compatible - clocks diff --git a/dts/upstream/Bindings/media/snps,dw-hdmi-rx.yaml b/dts/upstream/Bindings/media/snps,dw-hdmi-rx.yaml index 510e94e9ca3..b7f6c87d0e0 100644 --- a/dts/upstream/Bindings/media/snps,dw-hdmi-rx.yaml +++ b/dts/upstream/Bindings/media/snps,dw-hdmi-rx.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys DesignWare HDMI RX Controller maintainers: - - Shreeya Patel + - Dmitry Osipenko description: Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs diff --git a/dts/upstream/Bindings/media/st,stm32-dma2d.yaml b/dts/upstream/Bindings/media/st,stm32-dma2d.yaml index 4afa4a24b86..b9f7d84f38c 100644 --- a/dts/upstream/Bindings/media/st,stm32-dma2d.yaml +++ b/dts/upstream/Bindings/media/st,stm32-dma2d.yaml @@ -21,7 +21,6 @@ description: format and copy the result into a part or the whole of a destination image with a different color format. (TODO) - maintainers: - Dillon Min diff --git a/dts/upstream/Bindings/media/stih407-c8sectpfe.txt b/dts/upstream/Bindings/media/stih407-c8sectpfe.txt deleted file mode 100644 index 880d4d70c9f..00000000000 --- a/dts/upstream/Bindings/media/stih407-c8sectpfe.txt +++ /dev/null @@ -1,88 +0,0 @@ -STMicroelectronics STi c8sectpfe binding -============================================ - -This document describes the c8sectpfe device bindings that is used to get transport -stream data into the SoC on the TS pins, and into DDR for further processing. - -It is typically used in conjunction with one or more demodulator and tuner devices -which converts from the RF to digital domain. Demodulators and tuners are usually -located on an external DVB frontend card connected to SoC TS input pins. - -Currently 7 TS input (tsin) channels are supported on the stih407 family SoC. - -Required properties (controller (parent) node): -- compatible : Should be "stih407-c8sectpfe" - -- reg : Address and length of register sets for each device in - "reg-names" - -- reg-names : The names of the register addresses corresponding to the - registers filled in "reg": - - c8sectpfe: c8sectpfe registers - - c8sectpfe-ram: c8sectpfe internal sram - -- clocks : phandle list of c8sectpfe clocks -- clock-names : should be "c8sectpfe" -See: Documentation/devicetree/bindings/clock/clock-bindings.txt - -- pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num) - must be defined for each tsin child node. -- pinctrl-0 : phandle referencing pin configuration for this tsin configuration -See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - -Required properties (tsin (child) node): - -- tsin-num : tsin id of the InputBlock (must be between 0 to 6) -- i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected. -- reset-gpios : reset gpio for this tsin channel. - -Optional properties (tsin (child) node): - -- invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk). -- serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>). -- async-not-sync : Bool property to control if data is received in asynchronous mode - (all bits/bytes with ts_valid or ts_packet asserted are valid). - -- dvb-card : Describes the NIM card connected to this tsin channel. - -Example: - -/* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */ - - c8sectpfe@8a20000 { - compatible = "st,stih407-c8sectpfe"; - reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>; - reg-names = "stfe", "stfe-ram"; - interrupts = , ; - interrupt-names = "stfe-error-irq", "stfe-idle-irq"; - pinctrl-0 = <&pinctrl_tsin0_serial>; - pinctrl-1 = <&pinctrl_tsin0_parallel>; - pinctrl-2 = <&pinctrl_tsin3_serial>; - pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; - pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; - pinctrl-names = "tsin0-serial", - "tsin0-parallel", - "tsin3-serial", - "tsin4-serial", - "tsin5-serial"; - clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; - clock-names = "c8sectpfe"; - - /* tsin0 is TSA on NIMA */ - tsin0: port@0 { - tsin-num = <0>; - serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; - dvb-card = ; - }; - - tsin3: port@3 { - tsin-num = <3>; - serial-not-parallel; - i2c-bus = <&ssc3>; - reset-gpios = <&pio15 7 GPIO_ACTIVE_HIGH>; - dvb-card = ; - }; - }; diff --git a/dts/upstream/Bindings/media/video-interface-devices.yaml b/dts/upstream/Bindings/media/video-interface-devices.yaml index 3ad1590b049..a81d2a155fe 100644 --- a/dts/upstream/Bindings/media/video-interface-devices.yaml +++ b/dts/upstream/Bindings/media/video-interface-devices.yaml @@ -128,7 +128,6 @@ properties: 0 degrees camera rotation: - Y-Rp ^ Y-Rc ! @@ -145,7 +144,6 @@ properties: 0 +-------------------------------------> 0 X-Rc - X-Rc 0 <------------------------------------+ 0 X-Rp 0 ! @@ -228,7 +226,6 @@ properties: V X-Rc - Example one - Webcam A camera module installed on the user facing part of a laptop screen @@ -273,7 +270,6 @@ properties: optical inversion, the two reference systems will not be aligned, with 'Rp' being rotated 180 degrees relatively to 'Rc': - X-Rc 0 <------------------------------------+ 0 ! diff --git a/dts/upstream/Bindings/media/video-interfaces.yaml b/dts/upstream/Bindings/media/video-interfaces.yaml index 038e85b45be..6ed4695cacf 100644 --- a/dts/upstream/Bindings/media/video-interfaces.yaml +++ b/dts/upstream/Bindings/media/video-interfaces.yaml @@ -95,7 +95,7 @@ properties: - 6 # BT.656 - 7 # DPI description: - Data bus type. + Data bus type. See include/dt-bindings/media/video-interfaces.h. bus-width: $ref: /schemas/types.yaml#/definitions/uint32 @@ -229,7 +229,7 @@ properties: Imaging. The length of the array must be the same length as the data-lanes property. If the line-orders property is omitted, the value shall be interpreted as 0 (ABC). This property is valid for CSI-2 C-PHY - busses only. + busses only. See include/dt-bindings/media/video-interfaces.h. strobe: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml b/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml index 3049d6bb0b1..2a4bf905a36 100644 --- a/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml +++ b/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml @@ -12,7 +12,7 @@ description: | including IXP42x, IXP43x, IXP45x and IXP46x. maintainers: - - Linus Walleij + - Linus Walleij properties: $nodename: diff --git a/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml b/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml index d1479a7b9c8..020fa49c345 100644 --- a/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml +++ b/dts/upstream/Bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml @@ -12,7 +12,7 @@ description: including IXP42x, IXP43x, IXP45x and IXP46x. maintainers: - - Linus Walleij + - Linus Walleij properties: intel,ixp4xx-eb-t1: diff --git a/dts/upstream/Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml b/dts/upstream/Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml index 29f8c30e8a8..aec88cd2df7 100644 --- a/dts/upstream/Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml +++ b/dts/upstream/Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml @@ -62,7 +62,6 @@ properties: minimum: 0 maximum: 15 - # FAST chip selects qcom,xmem-address-hold-enable: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/upstream/Bindings/mfd/apple,smc.yaml b/dts/upstream/Bindings/mfd/apple,smc.yaml index 5429538f7e2..0410e712c90 100644 --- a/dts/upstream/Bindings/mfd/apple,smc.yaml +++ b/dts/upstream/Bindings/mfd/apple,smc.yaml @@ -46,6 +46,9 @@ properties: reboot: $ref: /schemas/power/reset/apple,smc-reboot.yaml + rtc: + $ref: /schemas/rtc/apple,smc-rtc.yaml + additionalProperties: false required: @@ -80,5 +83,11 @@ examples: nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; }; diff --git a/dts/upstream/Bindings/mfd/arm,dev-platforms-syscon.yaml b/dts/upstream/Bindings/mfd/arm,dev-platforms-syscon.yaml index 46b164ae083..7f3b1b77293 100644 --- a/dts/upstream/Bindings/mfd/arm,dev-platforms-syscon.yaml +++ b/dts/upstream/Bindings/mfd/arm,dev-platforms-syscon.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Arm Ltd Developer Platforms System Controllers maintainers: - - Linus Walleij + - Linus Walleij description: The Arm Ltd Integrator, Realview, and Versatile families of developer diff --git a/dts/upstream/Bindings/mfd/aspeed-lpc.yaml b/dts/upstream/Bindings/mfd/aspeed-lpc.yaml index f329223cec0..cbc3a2485a2 100644 --- a/dts/upstream/Bindings/mfd/aspeed-lpc.yaml +++ b/dts/upstream/Bindings/mfd/aspeed-lpc.yaml @@ -48,16 +48,16 @@ properties: reg: maxItems: 1 - "#address-cells": + '#address-cells': const: 1 - "#size-cells": + '#size-cells': const: 1 ranges: true patternProperties: - "^lpc-ctrl@[0-9a-f]+$": + '^lpc-ctrl@[0-9a-f]+$': type: object additionalProperties: false @@ -92,7 +92,7 @@ patternProperties: - compatible - clocks - "^reset-controller@[0-9a-f]+$": + '^reset-controller@[0-9a-f]+$': type: object additionalProperties: false @@ -118,7 +118,7 @@ patternProperties: - compatible - '#reset-cells' - "^lpc-snoop@[0-9a-f]+$": + '^lpc-snoop@[0-9a-f]+$': type: object additionalProperties: false @@ -152,15 +152,15 @@ patternProperties: - interrupts - snoop-ports - "^uart-routing@[0-9a-f]+$": + '^uart-routing@[0-9a-f]+$': $ref: /schemas/soc/aspeed/uart-routing.yaml# description: The UART routing control under LPC register space required: - compatible - reg - - "#address-cells" - - "#size-cells" + - '#address-cells' + - '#size-cells' - ranges additionalProperties: diff --git a/dts/upstream/Bindings/mfd/da9052-i2c.txt b/dts/upstream/Bindings/mfd/da9052-i2c.txt deleted file mode 100644 index 07c69c0c662..00000000000 --- a/dts/upstream/Bindings/mfd/da9052-i2c.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Dialog DA9052/53 Power Management Integrated Circuit (PMIC) - -Required properties: -- compatible : Should be "dlg,da9052", "dlg,da9053-aa", - "dlg,da9053-ab", or "dlg,da9053-bb" - -Optional properties: -- dlg,tsi-as-adc : Boolean, if set the X+, X-, Y+, Y- touchscreen - input lines are used as general purpose analogue - input. -- tsiref-supply: Phandle to the regulator, which provides the reference - voltage for the TSIREF pin. Must be provided when the - touchscreen pins are used for ADC purposes. - -Sub-nodes: -- regulators : Contain the regulator nodes. The DA9052/53 regulators are - bound using their names as listed below: - - buck1 : regulator BUCK CORE - buck2 : regulator BUCK PRO - buck3 : regulator BUCK MEM - buck4 : regulator BUCK PERI - ldo1 : regulator LDO1 - ldo2 : regulator LDO2 - ldo3 : regulator LDO3 - ldo4 : regulator LDO4 - ldo5 : regulator LDO5 - ldo6 : regulator LDO6 - ldo7 : regulator LDO7 - ldo8 : regulator LDO8 - ldo9 : regulator LDO9 - ldo10 : regulator LDO10 - - The bindings details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -Examples: - -i2c@63fc8000 { /* I2C1 */ - - pmic: dialog@48 { - compatible = "dlg,da9053-aa"; - reg = <0x48>; - - regulators { - buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - }; - - buck2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2075000>; - }; - - buck3 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - }; - - buck4 { - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <2500000>; - }; - }; - }; -}; diff --git a/dts/upstream/Bindings/mfd/dlg,da9052.yaml b/dts/upstream/Bindings/mfd/dlg,da9052.yaml new file mode 100644 index 00000000000..1103a8cc5ce --- /dev/null +++ b/dts/upstream/Bindings/mfd/dlg,da9052.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/dlg,da9052.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dialog DA9052/53 Power Management Integrated Circuit (PMIC) + +maintainers: + - Frank Li + +properties: + compatible: + oneOf: + - enum: + - dlg,da9053-aa + - dlg,da9053-ab + - dlg,da9053-bb + - dlg,da9053-bc + - dlg,da9052 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dlg,tsi-as-adc: + type: boolean + description: + if set the X+, X-, Y+, Y- touchscreen input lines are used as general + purpose analogue input. + + tsiref-supply: + description: The reference voltage for the TSIREF pin. + + regulators: + type: object + additionalProperties: false + + patternProperties: + "^(ldo([1-9]|10)|buck[1-4])$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - regulators + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@48 { + compatible = "dlg,da9053-aa"; + reg = <0x48>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2075000>; + }; + + buck3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <2500000>; + }; + + buck4 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <2500000>; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/mfd/dlg,da9063.yaml b/dts/upstream/Bindings/mfd/dlg,da9063.yaml index 51612dc2274..4f08e9ac7e5 100644 --- a/dts/upstream/Bindings/mfd/dlg,da9063.yaml +++ b/dts/upstream/Bindings/mfd/dlg,da9063.yaml @@ -81,6 +81,8 @@ properties: watchdog: $ref: /schemas/watchdog/dlg,da9062-watchdog.yaml + wakeup-source: true + patternProperties: "^(.+-hog(-[0-9]+)?)$": type: object diff --git a/dts/upstream/Bindings/mfd/fsl,mc13xxx.yaml b/dts/upstream/Bindings/mfd/fsl,mc13xxx.yaml index d2886f2686a..cfa69f1f380 100644 --- a/dts/upstream/Bindings/mfd/fsl,mc13xxx.yaml +++ b/dts/upstream/Bindings/mfd/fsl,mc13xxx.yaml @@ -93,38 +93,14 @@ properties: leds: type: object - $ref: /schemas/leds/common.yaml# + additionalProperties: false properties: - reg: - description: | - One of - MC13783 LED IDs - 0: Main display - 1: AUX display - 2: Keypad - 3: Red 1 - 4: Green 1 - 5: Blue 1 - 6: Red 2 - 7: Green 2 - 8: Blue 2 - 9: Red 3 - 10: Green 3 - 11: Blue 3 + '#address-cells': + const: 1 - MC13892 LED IDs - 0: Main display - 1: AUX display - 2: Keypad - 3: Red - 4: Green - 5: Blue - - MC34708 LED IDs - 0: Charger Red - 1: Charger Green - maxItems: 1 + '#size-cells': + const: 0 led-control: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -132,6 +108,42 @@ properties: Setting for LED-Control register array length depends on model, mc13783: 6, mc13892: 4, mc34708: 1 + patternProperties: + '^led@[0-9a-b]$': + $ref: /schemas/leds/common.yaml# + unevaluatedProperties: false + + properties: + reg: + description: | + One of + MC13783 LED IDs + 0: Main display + 1: AUX display + 2: Keypad + 3: Red 1 + 4: Green 1 + 5: Blue 1 + 6: Red 2 + 7: Green 2 + 8: Blue 2 + 9: Red 3 + 10: Green 3 + 11: Blue 3 + + MC13892 LED IDs + 0: Main display + 1: AUX display + 2: Keypad + 3: Red + 4: Green + 5: Blue + + MC34708 LED IDs + 0: Charger Red + 1: Charger Green + maxItems: 1 + regulators: type: object @@ -262,7 +274,7 @@ examples: #size-cells = <0>; led-control = <0x000 0x000 0x0e0 0x000>; - sysled@3 { + led@3 { reg = <3>; label = "system:red:live"; linux,default-trigger = "heartbeat"; diff --git a/dts/upstream/Bindings/mfd/maxim,max77705.yaml b/dts/upstream/Bindings/mfd/maxim,max77705.yaml index 0ec89f0adc6..8b62aadb421 100644 --- a/dts/upstream/Bindings/mfd/maxim,max77705.yaml +++ b/dts/upstream/Bindings/mfd/maxim,max77705.yaml @@ -26,6 +26,18 @@ properties: interrupts: maxItems: 1 + interrupt-controller: + description: + The driver implements an interrupt controller for the sub devices. + The interrupt number mapping is as follows + 0 - charger + 1 - topsys + 2 - fuelgauge + 3 - usb type-c management block. + + '#interrupt-cells': + const: 1 + haptic: type: object additionalProperties: false @@ -118,8 +130,10 @@ examples: pmic@66 { compatible = "maxim,max77705"; reg = <0x66>; + #interrupt-cells = <1>; interrupt-parent = <&pm8998_gpios>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; pinctrl-0 = <&chg_int_default>; pinctrl-names = "default"; diff --git a/dts/upstream/Bindings/mfd/nxp,pf1550.yaml b/dts/upstream/Bindings/mfd/nxp,pf1550.yaml new file mode 100644 index 00000000000..e50dc44252c --- /dev/null +++ b/dts/upstream/Bindings/mfd/nxp,pf1550.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/nxp,pf1550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PF1550 Power Management IC + +maintainers: + - Samuel Kayode + +description: + PF1550 PMIC provides battery charging and power supply for low power IoT and + wearable applications. This device consists of an i2c controlled MFD that + includes regulators, battery charging and an onkey/power button. + +$ref: /schemas/power/supply/power-supply.yaml + +properties: + compatible: + const: nxp,pf1550 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + wakeup-source: true + + regulators: + type: object + additionalProperties: false + + patternProperties: + "^(ldo[1-3]|sw[1-3]|vrefddr)$": + type: object + $ref: /schemas/regulator/regulator.yaml + description: + regulator configuration for ldo1-3, buck converters(sw1-3) + and DDR termination reference voltage (vrefddr) + unevaluatedProperties: false + + monitored-battery: + description: | + A phandle to a monitored battery node that contains a valid value + for: + constant-charge-voltage-max-microvolt. + + nxp,thermal-regulation-celsius: + description: + Temperature threshold for thermal regulation of charger in celsius. + enum: [ 80, 95, 110, 125 ] + + nxp,min-system-microvolt: + description: + System specific lower limit voltage. + enum: [ 3500000, 3700000, 4300000 ] + + nxp,disable-key-power: + type: boolean + description: + Disable power-down using a long key-press. The onkey driver will remove + support for the KEY_POWER key press when triggered using a long press of + the onkey. + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + battery: battery-cell { + compatible = "simple-battery"; + constant-charge-voltage-max-microvolt = <4400000>; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@8 { + compatible = "nxp,pf1550"; + reg = <0x8>; + + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + monitored-battery = <&battery>; + nxp,min-system-microvolt = <4300000>; + nxp,thermal-regulation-celsius = <80>; + + regulators { + sw1_reg: sw1 { + regulator-name = "sw1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-always-on; + regulator-ramp-delay = <6250>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-min-microvolt = <1270000>; + }; + }; + + sw2_reg: sw2 { + regulator-name = "sw2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + sw3_reg: sw3 { + regulator-name = "sw3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vldo1_reg: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2_reg: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vldo3_reg: ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml b/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml index 078a6886f8b..65c80e3b450 100644 --- a/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml +++ b/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml @@ -43,6 +43,7 @@ properties: - qcom,pm7250b - qcom,pm7550ba - qcom,pm7325 + - qcom,pm7550 - qcom,pm8004 - qcom,pm8005 - qcom,pm8009 @@ -84,6 +85,7 @@ properties: - qcom,pmi8994 - qcom,pmi8998 - qcom,pmih0108 + - qcom,pmiv0104 - qcom,pmk8002 - qcom,pmk8350 - qcom,pmk8550 diff --git a/dts/upstream/Bindings/mfd/renesas,r2a11302ft.yaml b/dts/upstream/Bindings/mfd/renesas,r2a11302ft.yaml new file mode 100644 index 00000000000..7b96619ebd8 --- /dev/null +++ b/dts/upstream/Bindings/mfd/renesas,r2a11302ft.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,r2a11302ft.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R2A11302FT Power Supply ICs for R-Car + +maintainers: + - Wolfram Sang + +description: | + The Renesas R2A11302FT PMIC is used with Renesas R-Car Gen1/Gen2 + based SoCs. + + FIXME: The binding is incomplete and resembles the information gathered + so far. + +properties: + compatible: + const: renesas,r2a11302ft + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 6000000 + + spi-cpol: true + + spi-cpha: true + +required: + - compatible + - reg + - spi-cpol + - spi-cpha + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; + }; +... diff --git a/dts/upstream/Bindings/mfd/rohm,bd96801-pmic.yaml b/dts/upstream/Bindings/mfd/rohm,bd96801-pmic.yaml index 0e06570483a..adb491bcc8d 100644 --- a/dts/upstream/Bindings/mfd/rohm,bd96801-pmic.yaml +++ b/dts/upstream/Bindings/mfd/rohm,bd96801-pmic.yaml @@ -57,8 +57,7 @@ properties: - prstb - intb-only - timeout-sec: - maxItems: 2 + timeout-sec: true regulators: $ref: /schemas/regulator/rohm,bd96801-regulator.yaml @@ -72,7 +71,10 @@ required: - interrupt-names - regulators -additionalProperties: false +allOf: + - $ref: /schemas/watchdog/watchdog.yaml + +unevaluatedProperties: false examples: - | diff --git a/dts/upstream/Bindings/mfd/silergy,sy7636a.yaml b/dts/upstream/Bindings/mfd/silergy,sy7636a.yaml index ee0be32ac02..4f829fe75d4 100644 --- a/dts/upstream/Bindings/mfd/silergy,sy7636a.yaml +++ b/dts/upstream/Bindings/mfd/silergy,sy7636a.yaml @@ -32,6 +32,17 @@ properties: Specifying the power good GPIOs. maxItems: 1 + enable-gpios: + maxItems: 1 + + vcom-en-gpios: + maxItems: 1 + + vin-supply: + description: + Supply for the whole chip. Some vendor kernels and devicetrees + declare this as a non-existing GPIO named "pwrall". + regulators: type: object diff --git a/dts/upstream/Bindings/mfd/st,stmpe.yaml b/dts/upstream/Bindings/mfd/st,stmpe.yaml index b77cc3f3075..df43878fbe1 100644 --- a/dts/upstream/Bindings/mfd/st,stmpe.yaml +++ b/dts/upstream/Bindings/mfd/st,stmpe.yaml @@ -12,7 +12,7 @@ description: STMicroelectronics Port Expander (STMPE) is a series of slow peripherals connected to SPI or I2C. maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# diff --git a/dts/upstream/Bindings/mfd/stericsson,ab8500.yaml b/dts/upstream/Bindings/mfd/stericsson,ab8500.yaml index b2cfa4120b8..0fdfbfdfe88 100644 --- a/dts/upstream/Bindings/mfd/stericsson,ab8500.yaml +++ b/dts/upstream/Bindings/mfd/stericsson,ab8500.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST-Ericsson Analog Baseband AB8500 and AB8505 maintainers: - - Linus Walleij + - Linus Walleij description: the AB8500 "Analog Baseband" is the mixed-signals integrated circuit @@ -444,7 +444,6 @@ properties: additionalProperties: false - regulator-external: description: Node describing the AB8500 external regulators. This concerns the autonomous regulators VSMPS1, VSMPS2 and VSMPS3 diff --git a/dts/upstream/Bindings/mfd/stericsson,db8500-prcmu.yaml b/dts/upstream/Bindings/mfd/stericsson,db8500-prcmu.yaml index d6c13779d44..4edd4a3bab8 100644 --- a/dts/upstream/Bindings/mfd/stericsson,db8500-prcmu.yaml +++ b/dts/upstream/Bindings/mfd/stericsson,db8500-prcmu.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit maintainers: - - Linus Walleij + - Linus Walleij description: The DB8500 Power Reset and Control Management Unit is an XP70 8-bit diff --git a/dts/upstream/Bindings/mfd/syscon-common.yaml b/dts/upstream/Bindings/mfd/syscon-common.yaml index 451cbad467a..14a08e7bc8b 100644 --- a/dts/upstream/Bindings/mfd/syscon-common.yaml +++ b/dts/upstream/Bindings/mfd/syscon-common.yaml @@ -35,9 +35,6 @@ properties: minItems: 2 maxItems: 5 # Should be enough - reg: - maxItems: 1 - reg-io-width: description: The size (in bytes) of the IO accesses that should be performed diff --git a/dts/upstream/Bindings/mfd/syscon.yaml b/dts/upstream/Bindings/mfd/syscon.yaml index 657c38175fb..55efb83b149 100644 --- a/dts/upstream/Bindings/mfd/syscon.yaml +++ b/dts/upstream/Bindings/mfd/syscon.yaml @@ -85,6 +85,7 @@ select: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt7981-topmisc - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg @@ -133,111 +134,126 @@ select: properties: compatible: - items: - - enum: - - airoha,en7581-pbus-csr - - al,alpine-sysfabric-service - - allwinner,sun8i-a83t-system-controller - - allwinner,sun8i-h3-system-controller - - allwinner,sun8i-v3s-system-controller - - allwinner,sun50i-a64-system-controller - - altr,l3regs - - altr,sdr-ctl - - amd,pensando-elba-syscon - - amlogic,meson-mx-assist - - amlogic,meson-mx-bootrom - - amlogic,meson8-analog-top - - amlogic,meson8b-analog-top - - amlogic,meson8-pmu - - amlogic,meson8b-pmu - - apm,merlin-poweroff-mailbox - - apm,mustang-poweroff-mailbox - - apm,xgene-csw - - apm,xgene-efuse - - apm,xgene-mcb - - apm,xgene-rb - - apm,xgene-scu - - atmel,sama5d2-sfrbu - - atmel,sama5d3-nfc-io - - atmel,sama5d3-sfrbu - - atmel,sama5d4-sfrbu - - axis,artpec6-syscon - - brcm,cru-clkset - - brcm,sr-cdru - - brcm,sr-mhb - - cirrus,ep7209-syscon1 - - cirrus,ep7209-syscon2 - - cirrus,ep7209-syscon3 - - cnxt,cx92755-uc - - freecom,fsg-cs2-system-controller - - fsl,imx93-aonmix-ns-syscfg - - fsl,imx93-wakeupmix-syscfg - - fsl,ls1088a-reset - - fsl,vf610-anatop - - fsl,vf610-mscm-cpucfg - - hisilicon,dsa-subctrl - - hisilicon,hi6220-sramctrl - - hisilicon,hip04-ppe - - hisilicon,pcie-sas-subctrl - - hisilicon,peri-subctrl - - hpe,gxp-sysreg - - loongson,ls1b-syscon - - loongson,ls1c-syscon - - lsi,axxia-syscon - - marvell,armada-3700-cpu-misc - - marvell,armada-3700-nb-pm - - marvell,armada-3700-avs - - marvell,armada-3700-usb2-host-device-misc - - marvell,armada-3700-usb2-host-misc - - marvell,dove-global-config - - mediatek,mt2701-pctl-a-syscfg - - mediatek,mt2712-pctl-a-syscfg - - mediatek,mt6397-pctl-pmic-syscfg - - mediatek,mt7988-topmisc - - mediatek,mt8135-pctl-a-syscfg - - mediatek,mt8135-pctl-b-syscfg - - mediatek,mt8173-pctl-a-syscfg - - mediatek,mt8365-infracfg-nao - - mediatek,mt8365-syscfg - - microchip,lan966x-cpu-syscon - - microchip,mpfs-control-scb - - microchip,mpfs-sysreg-scb - - microchip,sam9x60-sfr - - microchip,sama7d65-ddr3phy - - microchip,sama7d65-sfrbu - - microchip,sama7g5-ddr3phy - - mscc,ocelot-cpu-syscon - - mstar,msc313-pmsleep - - nuvoton,ma35d1-sys - - nuvoton,wpcm450-shm - - qcom,apq8064-mmss-sfpb - - qcom,apq8064-sps-sic - - rockchip,px30-qos - - rockchip,rk3036-qos - - rockchip,rk3066-qos - - rockchip,rk3128-qos - - rockchip,rk3228-qos - - rockchip,rk3288-qos - - rockchip,rk3368-qos - - rockchip,rk3399-qos - - rockchip,rk3528-qos - - rockchip,rk3562-qos - - rockchip,rk3568-qos - - rockchip,rk3576-qos - - rockchip,rk3588-qos - - rockchip,rv1126-qos - - st,spear1340-misc - - stericsson,nomadik-pmu - - starfive,jh7100-sysmain - - ti,am62-opp-efuse-table - - ti,am62-usb-phy-ctrl - - ti,am625-dss-oldi-io-ctrl - - ti,am62p-cpsw-mac-efuse - - ti,am654-dss-oldi-io-ctrl - - ti,j784s4-acspcie-proxy-ctrl - - ti,j784s4-pcie-ctrl - - ti,keystone-pllctrl - - const: syscon + oneOf: + - items: + - enum: + - airoha,en7581-pbus-csr + - al,alpine-sysfabric-service + - allwinner,sun8i-a83t-system-controller + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - altr,l3regs + - altr,sdr-ctl + - amd,pensando-elba-syscon + - amlogic,meson-mx-assist + - amlogic,meson-mx-bootrom + - amlogic,meson8-analog-top + - amlogic,meson8b-analog-top + - amlogic,meson8-pmu + - amlogic,meson8b-pmu + - apm,merlin-poweroff-mailbox + - apm,mustang-poweroff-mailbox + - apm,xgene-csw + - apm,xgene-efuse + - apm,xgene-mcb + - apm,xgene-rb + - apm,xgene-scu + - atmel,sama5d2-sfrbu + - atmel,sama5d3-nfc-io + - atmel,sama5d3-sfrbu + - atmel,sama5d4-sfrbu + - axis,artpec6-syscon + - brcm,cru-clkset + - brcm,sr-cdru + - brcm,sr-mhb + - cirrus,ep7209-syscon1 + - cirrus,ep7209-syscon2 + - cirrus,ep7209-syscon3 + - cnxt,cx92755-uc + - freecom,fsg-cs2-system-controller + - fsl,imx93-aonmix-ns-syscfg + - fsl,imx93-wakeupmix-syscfg + - fsl,ls1088a-reset + - fsl,vf610-anatop + - fsl,vf610-mscm-cpucfg + - hisilicon,dsa-subctrl + - hisilicon,hi6220-sramctrl + - hisilicon,hip04-ppe + - hisilicon,pcie-sas-subctrl + - hisilicon,peri-subctrl + - hpe,gxp-sysreg + - loongson,ls1b-syscon + - loongson,ls1c-syscon + - lsi,axxia-syscon + - marvell,armada-3700-cpu-misc + - marvell,armada-3700-nb-pm + - marvell,armada-3700-avs + - marvell,armada-3700-usb2-host-device-misc + - marvell,armada-3700-usb2-host-misc + - marvell,dove-global-config + - mediatek,mt2701-pctl-a-syscfg + - mediatek,mt2712-pctl-a-syscfg + - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt7988-topmisc + - mediatek,mt8135-pctl-a-syscfg + - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8173-pctl-a-syscfg + - mediatek,mt8365-infracfg-nao + - mediatek,mt8365-syscfg + - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb + - microchip,mpfs-sysreg-scb + - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy + - microchip,sama7d65-sfrbu + - microchip,sama7g5-ddr3phy + - mscc,ocelot-cpu-syscon + - mstar,msc313-pmsleep + - nuvoton,ma35d1-sys + - nuvoton,wpcm450-shm + - qcom,apq8064-mmss-sfpb + - qcom,apq8064-sps-sic + - rockchip,px30-qos + - rockchip,rk3036-qos + - rockchip,rk3066-qos + - rockchip,rk3128-qos + - rockchip,rk3228-qos + - rockchip,rk3288-qos + - rockchip,rk3368-qos + - rockchip,rk3399-qos + - rockchip,rk3528-qos + - rockchip,rk3562-qos + - rockchip,rk3568-qos + - rockchip,rk3576-qos + - rockchip,rk3588-qos + - rockchip,rv1126-qos + - st,spear1340-misc + - stericsson,nomadik-pmu + - starfive,jh7100-sysmain + - ti,am62-opp-efuse-table + - ti,am62-usb-phy-ctrl + - ti,am625-dss-oldi-io-ctrl + - ti,am62p-cpsw-mac-efuse + - ti,am654-dss-oldi-io-ctrl + - ti,j784s4-acspcie-proxy-ctrl + - ti,j784s4-pcie-ctrl + - ti,keystone-pllctrl + - const: syscon + - items: + - enum: + - microchip,sama7g5-sfrbu + - microchip,sama7d65-sfrbu + - const: atmel,sama5d2-sfrbu + - const: syscon + - items: + - const: microchip,pic64gx-control-scb + - const: microchip,mpfs-control-scb + - const: syscon + - items: + - const: microchip,pic64gx-sysreg-scb + - const: microchip,mpfs-sysreg-scb + - const: syscon reg: maxItems: 1 diff --git a/dts/upstream/Bindings/mfd/ti,tps65910.yaml b/dts/upstream/Bindings/mfd/ti,tps65910.yaml index a2668fc30a7..f1a76f88fc0 100644 --- a/dts/upstream/Bindings/mfd/ti,tps65910.yaml +++ b/dts/upstream/Bindings/mfd/ti,tps65910.yaml @@ -166,9 +166,6 @@ patternProperties: required: - compatible - reg - - interrupts - - interrupt-controller - - '#interrupt-cells' - gpio-controller - '#gpio-cells' - regulators diff --git a/dts/upstream/Bindings/mfd/ti,twl.yaml b/dts/upstream/Bindings/mfd/ti,twl.yaml index 776b04e182c..9cc3e472161 100644 --- a/dts/upstream/Bindings/mfd/ti,twl.yaml +++ b/dts/upstream/Bindings/mfd/ti,twl.yaml @@ -55,6 +55,15 @@ allOf: gpadc: false + pwrbutton: + properties: + compatible: + const: ti,twl4030-pwrbutton + interrupts: + items: + - items: + const: 8 + usb-comparator: false - if: @@ -95,7 +104,14 @@ allOf: compatible: const: ti,twl6030-gpadc - pwrbutton: false + pwrbutton: + properties: + compatible: + const: ti,twl6030-pwrbutton + interrupts: + items: + - items: + const: 0 madc: false @@ -146,7 +162,14 @@ allOf: compatible: const: ti,twl6032-gpadc - pwrbutton: false + pwrbutton: + properties: + compatible: + const: ti,twl6030-pwrbutton + interrupts: + items: + - items: + const: 0 madc: false @@ -226,11 +249,11 @@ properties: properties: compatible: - const: ti,twl4030-pwrbutton + enum: + - ti,twl4030-pwrbutton + - ti,twl6030-pwrbutton interrupts: - items: - - items: - const: 8 + maxItems: 1 watchdog: type: object @@ -400,7 +423,7 @@ properties: - '#pwm-cells' patternProperties: - "^regulator-": + '^regulator-': type: object unevaluatedProperties: false $ref: /schemas/regulator/regulator.yaml @@ -429,7 +452,7 @@ required: - reg - interrupts - interrupt-controller - - "#interrupt-cells" + - '#interrupt-cells' examples: - | @@ -459,6 +482,11 @@ examples: #io-channel-cells = <1>; }; + pwrbutton { + compatible = "ti,twl6030-pwrbutton"; + interrupts = <0>; + }; + rtc { compatible = "ti,twl4030-rtc"; interrupts = <8>; diff --git a/dts/upstream/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml b/dts/upstream/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml index aab89946b04..1198d87d0ab 100644 --- a/dts/upstream/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml +++ b/dts/upstream/Bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx AHB Queue Manager maintainers: - - Linus Walleij + - Linus Walleij description: | The IXP4xx AHB Queue Manager maintains queues as circular buffers in diff --git a/dts/upstream/Bindings/misc/pci1de4,1.yaml b/dts/upstream/Bindings/misc/pci1de4,1.yaml index 2f9a7a554ed..17a8c19af8c 100644 --- a/dts/upstream/Bindings/misc/pci1de4,1.yaml +++ b/dts/upstream/Bindings/misc/pci1de4,1.yaml @@ -25,6 +25,10 @@ properties: items: - const: pci1de4,1 + reg: + maxItems: 1 + description: The PCI Bus-Device-Function address. + '#interrupt-cells': const: 2 description: | @@ -101,6 +105,7 @@ unevaluatedProperties: false required: - compatible + - reg - '#interrupt-cells' - interrupt-controller - pci-ep-bus@1 @@ -111,8 +116,9 @@ examples: #address-cells = <3>; #size-cells = <2>; - rp1@0,0 { + dev@0,0 { compatible = "pci1de4,1"; + reg = <0x10000 0x0 0x0 0x0 0x0>; ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>; #address-cells = <3>; #size-cells = <2>; diff --git a/dts/upstream/Bindings/mmc/arm,pl18x.yaml b/dts/upstream/Bindings/mmc/arm,pl18x.yaml index 8f62e2c7fa6..f90fd73904a 100644 --- a/dts/upstream/Bindings/mmc/arm,pl18x.yaml +++ b/dts/upstream/Bindings/mmc/arm,pl18x.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181 maintainers: - - Linus Walleij + - Linus Walleij - Ulf Hansson description: diff --git a/dts/upstream/Bindings/mmc/aspeed,sdhci.yaml b/dts/upstream/Bindings/mmc/aspeed,sdhci.yaml index 9fce8cd7b0b..d24950ccea9 100644 --- a/dts/upstream/Bindings/mmc/aspeed,sdhci.yaml +++ b/dts/upstream/Bindings/mmc/aspeed,sdhci.yaml @@ -41,7 +41,7 @@ properties: patternProperties: "^sdhci@[0-9a-f]+$": type: object - $ref: mmc-controller.yaml + $ref: sdhci-common.yaml unevaluatedProperties: false properties: diff --git a/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml b/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml index 493655a38b3..0936bfef8c7 100644 --- a/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -21,9 +21,11 @@ properties: - items: - enum: - brcm,bcm2712-sdhci + - brcm,bcm72116-sdhci - brcm,bcm74165b0-sdhci - brcm,bcm7445-sdhci - brcm,bcm7425-sdhci + - brcm,bcm74371-sdhci - const: brcm,sdhci-brcmstb reg: diff --git a/dts/upstream/Bindings/mmc/davinci_mmc.txt b/dts/upstream/Bindings/mmc/davinci_mmc.txt deleted file mode 100644 index 516fb0143d4..00000000000 --- a/dts/upstream/Bindings/mmc/davinci_mmc.txt +++ /dev/null @@ -1,32 +0,0 @@ -* TI Highspeed MMC host controller for DaVinci - -The Highspeed MMC Host Controller on TI DaVinci family -provides an interface for MMC, SD and SDIO types of memory cards. - -This file documents the properties used by the davinci_mmc driver. - -Required properties: -- compatible: - Should be "ti,da830-mmc": for da830, da850, dm365 - Should be "ti,dm355-mmc": for dm355, dm644x - -Optional properties: -- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1> -- max-frequency: Maximum operating clock frequency, default 25MHz. -- dmas: List of DMA specifiers with the controller specific format - as described in the generic DMA client binding. A tx and rx - specifier is required. -- dma-names: RX and TX DMA request names. These strings correspond - 1:1 with the DMA specifiers listed in dmas. - -Example: -mmc0: mmc@1c40000 { - compatible = "ti,da830-mmc", - reg = <0x40000 0x1000>; - interrupts = <16>; - bus-width = <4>; - max-frequency = <50000000>; - dmas = <&edma 16 - &edma 17>; - dma-names = "rx", "tx"; -}; diff --git a/dts/upstream/Bindings/mmc/rockchip-dw-mshc.yaml b/dts/upstream/Bindings/mmc/rockchip-dw-mshc.yaml index bf273115235..acb9fb9a92c 100644 --- a/dts/upstream/Bindings/mmc/rockchip-dw-mshc.yaml +++ b/dts/upstream/Bindings/mmc/rockchip-dw-mshc.yaml @@ -38,6 +38,7 @@ properties: - rockchip,rk3328-dw-mshc - rockchip,rk3368-dw-mshc - rockchip,rk3399-dw-mshc + - rockchip,rk3506-dw-mshc - rockchip,rk3528-dw-mshc - rockchip,rk3562-dw-mshc - rockchip,rk3568-dw-mshc diff --git a/dts/upstream/Bindings/mmc/sdhci-am654.yaml b/dts/upstream/Bindings/mmc/sdhci-am654.yaml index 676a7469538..242a3c6b925 100644 --- a/dts/upstream/Bindings/mmc/sdhci-am654.yaml +++ b/dts/upstream/Bindings/mmc/sdhci-am654.yaml @@ -50,8 +50,7 @@ properties: - const: clk_ahb - const: clk_xin - dma-coherent: - type: boolean + dma-coherent: true # PHY output tap delays: # Used to delay the data valid window and align it to the sampling clock. diff --git a/dts/upstream/Bindings/mmc/sdhci-milbeaut.txt b/dts/upstream/Bindings/mmc/sdhci-milbeaut.txt deleted file mode 100644 index 627ee89c125..00000000000 --- a/dts/upstream/Bindings/mmc/sdhci-milbeaut.txt +++ /dev/null @@ -1,30 +0,0 @@ -* SOCIONEXT Milbeaut SDHCI controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci_milbeaut driver. - -Required properties: -- compatible: "socionext,milbeaut-m10v-sdhci-3.0" -- clocks: Must contain an entry for each entry in clock-names. It is a - list of phandles and clock-specifier pairs. - See ../clocks/clock-bindings.txt for details. -- clock-names: Should contain the following two entries: - "iface" - clock used for sdhci interface - "core" - core clock for sdhci controller - -Optional properties: -- fujitsu,cmd-dat-delay-select: boolean property indicating that this host - requires the CMD_DAT_DELAY control to be enabled. - -Example: - sdhci3: mmc@1b010000 { - compatible = "socionext,milbeaut-m10v-sdhci-3.0"; - reg = <0x1b010000 0x10000>; - interrupts = <0 265 0x4>; - voltage-ranges = <3300 3300>; - bus-width = <4>; - clocks = <&clk 7>, <&ahb_clk>; - clock-names = "core", "iface"; - cap-sdio-irq; - fujitsu,cmd-dat-delay-select; - }; diff --git a/dts/upstream/Bindings/mmc/sdhci-msm.yaml b/dts/upstream/Bindings/mmc/sdhci-msm.yaml index 594bd174ff2..938be8228d6 100644 --- a/dts/upstream/Bindings/mmc/sdhci-msm.yaml +++ b/dts/upstream/Bindings/mmc/sdhci-msm.yaml @@ -42,6 +42,7 @@ properties: - qcom,ipq5424-sdhci - qcom,ipq6018-sdhci - qcom,ipq9574-sdhci + - qcom,kaanapali-sdhci - qcom,milos-sdhci - qcom,qcm2290-sdhci - qcom,qcs404-sdhci @@ -70,6 +71,7 @@ properties: - qcom,sm8450-sdhci - qcom,sm8550-sdhci - qcom,sm8650-sdhci + - qcom,sm8750-sdhci - qcom,x1e80100-sdhci - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 diff --git a/dts/upstream/Bindings/mmc/sdhci-omap.txt b/dts/upstream/Bindings/mmc/sdhci-omap.txt deleted file mode 100644 index f91e341e6b3..00000000000 --- a/dts/upstream/Bindings/mmc/sdhci-omap.txt +++ /dev/null @@ -1,43 +0,0 @@ -* TI OMAP SDHCI Controller - -Refer to mmc.txt for standard MMC bindings. - -For UHS devices which require tuning, the device tree should have a "cpu_thermal" node which maps to the appropriate thermal zone. This is used to get the temperature of the zone during tuning. - -Required properties: -- compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers - Should be "ti,omap3-sdhci" for omap3 controllers - Should be "ti,omap4-sdhci" for omap4 and ti81 controllers - Should be "ti,omap5-sdhci" for omap5 controllers - Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers - Should be "ti,k2g-sdhci" for K2G - Should be "ti,am335-sdhci" for am335x controllers - Should be "ti,am437-sdhci" for am437x controllers -- ti,hwmods: Must be "mmc", is controller instance starting 1 - (Not required for K2G). -- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50", - "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104", - "ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11", - "hs200_1_8v", -- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt - -Optional properties: -- dmas: List of DMA specifiers with the controller specific format as described - in the generic DMA client binding. A tx and rx specifier is required. -- dma-names: List of DMA request names. These strings correspond 1:1 with the - DMA specifiers listed in dmas. The string naming is to be "tx" - and "rx" for TX and RX DMA requests, respectively. - -Deprecated properties: -- ti,non-removable: Compatible with the generic non-removable property - -Example: - mmc1: mmc@4809c000 { - compatible = "ti,dra7-sdhci"; - reg = <0x4809c000 0x400>; - ti,hwmods = "mmc1"; - bus-width = <4>; - vmmc-supply = <&vmmc>; /* phandle to regulator node */ - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; diff --git a/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml b/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml index f882219a0a2..7e7c55dc244 100644 --- a/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -30,6 +30,7 @@ properties: - sophgo,sg2002-dwcmshc - sophgo,sg2042-dwcmshc - thead,th1520-dwcmshc + - eswin,eic7700-dwcmshc reg: maxItems: 1 @@ -52,17 +53,30 @@ properties: maxItems: 5 reset-names: - items: - - const: core - - const: bus - - const: axi - - const: block - - const: timer + maxItems: 5 rockchip,txclk-tapnum: description: Specify the number of delay for tx sampling. $ref: /schemas/types.yaml#/definitions/uint8 + eswin,hsp-sp-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to HSP(High-Speed Peripheral) device + - description: Offset of the stability status register for internal + clock. + - description: Offset of the stability register for host regulator + voltage. + description: + HSP CSR is to control and get status of different high-speed peripherals + (such as Ethernet, USB, SATA, etc.) via register, which can tune + board-level's parameters of PHY, etc. + + eswin,drive-impedance-ohms: + description: Specifies the drive impedance in Ohm. + enum: [33, 40, 50, 66, 100] + required: - compatible - reg @@ -110,6 +124,37 @@ allOf: - const: block - const: timer + - if: + properties: + compatible: + contains: + const: eswin,eic7700-dwcmshc + then: + properties: + resets: + minItems: 4 + maxItems: 4 + reset-names: + items: + - const: axi + - const: phy + - const: prstn + - const: txrx + required: + - eswin,hsp-sp-csr + - eswin,drive-impedance-ohms + else: + properties: + resets: + maxItems: 5 + reset-names: + items: + - const: core + - const: bus + - const: axi + - const: block + - const: timer + - if: properties: compatible: diff --git a/dts/upstream/Bindings/mmc/socionext,milbeaut-m10v-sdhci-3.0.yaml b/dts/upstream/Bindings/mmc/socionext,milbeaut-m10v-sdhci-3.0.yaml new file mode 100644 index 00000000000..2ba53626a95 --- /dev/null +++ b/dts/upstream/Bindings/mmc/socionext,milbeaut-m10v-sdhci-3.0.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/socionext,milbeaut-m10v-sdhci-3.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SOCIONEXT Milbeaut SDHCI controller + +maintainers: + - Taichi Sugaya + - Takao Orito + +description: + The SOCIONEXT Milbeaut SDHCI controller is a specialized SD Host + Controller found in some of Socionext's Milbeaut image processing SoCs. + It features a dedicated "bridge controller." This bridge controller + implements special functions like reset control, clock management for + various SDR modes (SDR12, SDR25, SDR50) and physical pin property settings. + +allOf: + - $ref: sdhci-common.yaml# + +properties: + compatible: + const: socionext,milbeaut-m10v-sdhci-3.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: iface + + fujitsu,cmd-dat-delay-select: + description: + Its presence indicates that the controller requires a specific command + and data line delay selection mechanism for proper operation, particularly + when dealing with high-speed SD/eMMC modes. + type: boolean + + voltage-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: minimum slot voltage (mV). + - description: maximum slot voltage (mV). + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + mmc@1b010000 { + compatible = "socionext,milbeaut-m10v-sdhci-3.0"; + reg = <0x1b010000 0x10000>; + interrupts = ; + voltage-ranges = <3300 3300>; + bus-width = <4>; + clocks = <&clk 7>, <&ahb_clk>; + clock-names = "core", "iface"; + cap-sdio-irq; + fujitsu,cmd-dat-delay-select; + }; +... diff --git a/dts/upstream/Bindings/mmc/ti,da830-mmc.yaml b/dts/upstream/Bindings/mmc/ti,da830-mmc.yaml new file mode 100644 index 00000000000..36b33dde086 --- /dev/null +++ b/dts/upstream/Bindings/mmc/ti,da830-mmc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/ti,da830-mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Highspeed MMC host controller for DaVinci + +description: + The Highspeed MMC Host Controller on TI DaVinci family + provides an interface for MMC, SD and SDIO types of memory cards. + +allOf: + - $ref: mmc-controller.yaml + +maintainers: + - Kishon Vijay Abraham I + +properties: + compatible: + enum: + - ti,da830-mmc + - ti,dm355-mmc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 2 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + mmc@1c40000 { + compatible = "ti,da830-mmc"; + reg = <0x40000 0x1000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, + <17 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <4>; + max-frequency = <50000000>; + dmas = <&edma 16>, <&edma 17>; + dma-names = "rx", "tx"; + }; +... diff --git a/dts/upstream/Bindings/mmc/ti,omap2430-sdhci.yaml b/dts/upstream/Bindings/mmc/ti,omap2430-sdhci.yaml new file mode 100644 index 00000000000..34e288f3ef1 --- /dev/null +++ b/dts/upstream/Bindings/mmc/ti,omap2430-sdhci.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/ti,omap2430-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP SDHCI Controller + +maintainers: + - Kishon Vijay Abraham I + +description: + For UHS devices which require tuning, the device tree should have a + cpu_thermal node which maps to the appropriate thermal zone. This + is used to get the temperature of the zone during tuning. + +properties: + compatible: + enum: + - ti,omap2430-sdhci + - ti,omap3-sdhci + - ti,omap4-sdhci + - ti,omap5-sdhci + - ti,dra7-sdhci + - ti,k2g-sdhci + - ti,am335-sdhci + - ti,am437-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: fck + - const: mmchsdb_fck + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + pinctrl-names: + minItems: 1 + maxItems: 14 + items: + enum: + - default + - default-rev11 + - hs + - sdr12 + - sdr12-rev11 + - sdr25 + - sdr25-rev11 + - sdr50 + - ddr50-rev11 + - sdr104-rev11 + - ddr50 + - sdr104 + - ddr_1_8v-rev11 + - ddr_1_8v + - ddr_3_3v + - hs-rev11 + - hs200_1_8v-rev11 + - hs200_1_8v + - sleep + + pinctrl-0: + maxItems: 1 + + pinctrl-1: + maxItems: 1 + + pinctrl-2: + maxItems: 1 + + pinctrl-3: + maxItems: 1 + + pinctrl-4: + maxItems: 1 + + pinctrl-5: + maxItems: 1 + + pinctrl-6: + maxItems: 1 + + pinctrl-7: + maxItems: 1 + + pinctrl-8: + maxItems: 1 + + power-domains: + maxItems: 1 + + pbias-supply: + description: + It is used to specify the voltage regulator that provides the bias + voltage for certain analog or I/O pads. + + ti,non-removable: + description: + It indicates that a component is not meant to be easily removed or + replaced by the user, such as an embedded battery or a non-removable + storage slot like eMMC. + type: boolean + deprecated: true + + clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + It represents the speed at which a clock signal associated with a device + or bus operates, measured in Hertz (Hz). This value is crucial for configuring + hardware components that require a specific clock speed. + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: sdhci-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,dra7-sdhci + - ti,k2g-sdhci + then: + required: + - max-frequency + - if: + properties: + compatible: + contains: + const: ti,k2g-sdhci + then: + required: + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + mmc@4809c000 { + compatible = "ti,dra7-sdhci"; + reg = <0x4809c000 0x400>; + interrupts = ; + max-frequency = <192000000>; + sdhci-caps-mask = <0x0 0x400000>; + bus-width = <4>; + vmmc-supply = <&vmmc>; /* phandle to regulator node */ + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + }; +... diff --git a/dts/upstream/Bindings/mtd/allwinner,sun4i-a10-nand.yaml b/dts/upstream/Bindings/mtd/allwinner,sun4i-a10-nand.yaml index 054b6b8bf9b..9d061e2216c 100644 --- a/dts/upstream/Bindings/mtd/allwinner,sun4i-a10-nand.yaml +++ b/dts/upstream/Bindings/mtd/allwinner,sun4i-a10-nand.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A10 NAND Controller -allOf: - - $ref: nand-controller.yaml - maintainers: - Chen-Yu Tsai - Maxime Ripard @@ -18,6 +15,8 @@ properties: enum: - allwinner,sun4i-a10-nand - allwinner,sun8i-a23-nand-controller + - allwinner,sun50i-h616-nand-controller + reg: maxItems: 1 @@ -25,14 +24,20 @@ properties: maxItems: 1 clocks: + minItems: 2 items: - description: Bus Clock - description: Module Clock + - description: ECC Clock + - description: MBus Clock clock-names: + minItems: 2 items: - const: ahb - const: mod + - const: ecc + - const: mbus resets: maxItems: 1 @@ -85,6 +90,36 @@ required: unevaluatedProperties: false +allOf: + - $ref: nand-controller.yaml + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun4i-a10-nand + - allwinner,sun8i-a23-nand-controller + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h616-nand-controller + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + examples: - | #include diff --git a/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml b/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml index 284f0f882c3..fa2aa29be79 100644 --- a/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml +++ b/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml @@ -88,7 +88,6 @@ patternProperties: amlogic,boot-pages: [nand-is-boot-medium, "amlogic,boot-page-step"] amlogic,boot-page-step: [nand-is-boot-medium, "amlogic,boot-pages"] - required: - compatible - reg diff --git a/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml b/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml index e1f4d7c35a8..73dc69cee4d 100644 --- a/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml +++ b/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml @@ -40,6 +40,9 @@ properties: dmas: maxItems: 1 + iommus: + maxItems: 1 + cdns,board-delay-ps: description: | Estimated Board delay. The value includes the total round trip diff --git a/dts/upstream/Bindings/mtd/marvell,nand-controller.yaml b/dts/upstream/Bindings/mtd/marvell,nand-controller.yaml index 1ecea848e8b..bc89cbf8193 100644 --- a/dts/upstream/Bindings/mtd/marvell,nand-controller.yaml +++ b/dts/upstream/Bindings/mtd/marvell,nand-controller.yaml @@ -145,7 +145,6 @@ allOf: clock-names: minItems: 1 - unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/mtd/mtd-physmap.yaml b/dts/upstream/Bindings/mtd/mtd-physmap.yaml index 1b375dee83b..a9ec3ca002c 100644 --- a/dts/upstream/Bindings/mtd/mtd-physmap.yaml +++ b/dts/upstream/Bindings/mtd/mtd-physmap.yaml @@ -69,6 +69,16 @@ properties: minItems: 1 maxItems: 8 + clocks: + description: | + Chips may need clocks to be enabled for themselves or for transparent + bridges. + + power-domains: + description: | + Chips may need power domains to be enabled for themselves or for + transparent bridges. + bank-width: description: Width (in bytes) of the bank. Equal to the device width times the number of interleaved chips. diff --git a/dts/upstream/Bindings/mtd/partitions/arm,arm-firmware-suite.yaml b/dts/upstream/Bindings/mtd/partitions/arm,arm-firmware-suite.yaml index 97618847ee3..e9b1a686991 100644 --- a/dts/upstream/Bindings/mtd/partitions/arm,arm-firmware-suite.yaml +++ b/dts/upstream/Bindings/mtd/partitions/arm,arm-firmware-suite.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Firmware Suite (AFS) Partitions maintainers: - - Linus Walleij + - Linus Walleij select: false diff --git a/dts/upstream/Bindings/mtd/partitions/redboot-fis.yaml b/dts/upstream/Bindings/mtd/partitions/redboot-fis.yaml index ba7445cd69e..e3978d2bc05 100644 --- a/dts/upstream/Bindings/mtd/partitions/redboot-fis.yaml +++ b/dts/upstream/Bindings/mtd/partitions/redboot-fis.yaml @@ -14,7 +14,7 @@ description: The FLASH Image System (FIS) directory is a flash description 32 KB in size. maintainers: - - Linus Walleij + - Linus Walleij select: false diff --git a/dts/upstream/Bindings/mtd/partitions/seama.yaml b/dts/upstream/Bindings/mtd/partitions/seama.yaml index 4c1cbf43e81..4af185204b4 100644 --- a/dts/upstream/Bindings/mtd/partitions/seama.yaml +++ b/dts/upstream/Bindings/mtd/partitions/seama.yaml @@ -18,7 +18,7 @@ allOf: - $ref: partition.yaml# maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/mux/mux-controller.yaml b/dts/upstream/Bindings/mux/mux-controller.yaml index 571ad9e13ec..78340bbe4df 100644 --- a/dts/upstream/Bindings/mux/mux-controller.yaml +++ b/dts/upstream/Bindings/mux/mux-controller.yaml @@ -20,7 +20,6 @@ description: | space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer, 0-7 for an 8-way multiplexer, etc. - Mux controller nodes -------------------- diff --git a/dts/upstream/Bindings/net/airoha,en7581-eth.yaml b/dts/upstream/Bindings/net/airoha,en7581-eth.yaml index 6d22131ac2f..fbe2ddcdd90 100644 --- a/dts/upstream/Bindings/net/airoha,en7581-eth.yaml +++ b/dts/upstream/Bindings/net/airoha,en7581-eth.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - airoha,en7581-eth + - airoha,an7583-eth reg: items: @@ -44,6 +45,7 @@ properties: - description: PDMA irq resets: + minItems: 7 maxItems: 8 reset-names: @@ -54,8 +56,9 @@ properties: - const: xsi-mac - const: hsi0-mac - const: hsi1-mac - - const: hsi-mac + - enum: [ hsi-mac, xfp-mac ] - const: xfp-mac + minItems: 7 memory-region: items: @@ -81,6 +84,36 @@ properties: interface to implement hardware flow offloading programming Packet Processor Engine (PPE) flow table. +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - airoha,en7581-eth + then: + properties: + resets: + minItems: 8 + + reset-names: + minItems: 8 + + - if: + properties: + compatible: + contains: + enum: + - airoha,an7583-eth + then: + properties: + resets: + maxItems: 7 + + reset-names: + maxItems: 7 + patternProperties: "^ethernet@[1-4]$": type: object diff --git a/dts/upstream/Bindings/net/airoha,en7581-npu.yaml b/dts/upstream/Bindings/net/airoha,en7581-npu.yaml index c7644e6586d..59c57f58116 100644 --- a/dts/upstream/Bindings/net/airoha,en7581-npu.yaml +++ b/dts/upstream/Bindings/net/airoha,en7581-npu.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - airoha,en7581-npu + - airoha,an7583-npu reg: maxItems: 1 diff --git a/dts/upstream/Bindings/net/allwinner,sun8i-a83t-emac.yaml b/dts/upstream/Bindings/net/allwinner,sun8i-a83t-emac.yaml index fc62fb2a68a..323a669fa98 100644 --- a/dts/upstream/Bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/dts/upstream/Bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -201,7 +201,6 @@ allOf: - clocks - resets - mdio@2: $ref: mdio.yaml# unevaluatedProperties: false @@ -251,7 +250,6 @@ allOf: maxItems: 1 power-domains: false - unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/net/amd,xgbe-seattle-v1a.yaml b/dts/upstream/Bindings/net/amd,xgbe-seattle-v1a.yaml new file mode 100644 index 00000000000..006add8b641 --- /dev/null +++ b/dts/upstream/Bindings/net/amd,xgbe-seattle-v1a.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/amd,xgbe-seattle-v1a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD XGBE Seattle v1a + +maintainers: + - Shyam Sundar S K + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + +properties: + compatible: + const: amd,xgbe-seattle-v1a + + reg: + items: + - description: MAC registers + - description: PCS registers + - description: SerDes Rx/Tx registers + - description: SerDes integration registers (1/2) + - description: SerDes integration registers (2/2) + + interrupts: + description: Device interrupts. The first entry is the general device + interrupt. If amd,per-channel-interrupt is specified, each DMA channel + interrupt must be specified. The last entry is the PCS auto-negotiation + interrupt. + minItems: 2 + maxItems: 6 + + clocks: + items: + - description: DMA clock for the device + - description: PTP clock for the device + + clock-names: + items: + - const: dma_clk + - const: ptp_clk + + iommus: + maxItems: 1 + + phy-mode: true + + dma-coherent: true + + amd,per-channel-interrupt: + description: Indicates that Rx and Tx complete will generate a unique + interrupt for each DMA channel. + type: boolean + + amd,speed-set: + description: > + Speed capabilities of the device. + 0 = 1GbE and 10GbE + 1 = 2.5GbE and 10GbE + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + amd,serdes-blwc: + description: Baseline wandering correction enablement for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + enum: [0, 1] + + amd,serdes-cdr-rate: + description: CDR rate speed selection for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: CDR rate for 1GbE + - description: CDR rate for 2.5GbE + - description: CDR rate for 10GbE + + amd,serdes-pq-skew: + description: PQ data sampling skew for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: PQ skew for 1GbE + - description: PQ skew for 2.5GbE + - description: PQ skew for 10GbE + + amd,serdes-tx-amp: + description: TX amplitude boost for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: TX amplitude for 1GbE + - description: TX amplitude for 2.5GbE + - description: TX amplitude for 10GbE + + amd,serdes-dfe-tap-config: + description: DFE taps available to run for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: DFE taps available for 1GbE + - description: DFE taps available for 2.5GbE + - description: DFE taps available for 10GbE + + amd,serdes-dfe-tap-enable: + description: DFE taps to enable for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: DFE taps to enable for 1GbE + - description: DFE taps to enable for 2.5GbE + - description: DFE taps to enable for 10GbE + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phy-mode + +unevaluatedProperties: false + +examples: + - | + ethernet@e0700000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0xe0700000 0x80000>, + <0xe0780000 0x80000>, + <0xe1240800 0x00400>, + <0xe1250000 0x00060>, + <0xe1250080 0x00004>; + interrupts = <0 325 4>, + <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, + <0 323 4>; + amd,per-channel-interrupt; + clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; + clock-names = "dma_clk", "ptp_clk"; + phy-mode = "xgmii"; + mac-address = [ 02 a1 a2 a3 a4 a5 ]; + amd,speed-set = <0>; + amd,serdes-blwc = <1>, <1>, <0>; + amd,serdes-cdr-rate = <2>, <2>, <7>; + amd,serdes-pq-skew = <10>, <10>, <30>; + amd,serdes-tx-amp = <15>, <15>, <10>; + amd,serdes-dfe-tap-config = <3>, <3>, <1>; + amd,serdes-dfe-tap-enable = <0>, <0>, <127>; + }; diff --git a/dts/upstream/Bindings/net/amd-xgbe.txt b/dts/upstream/Bindings/net/amd-xgbe.txt deleted file mode 100644 index 9c27dfcd113..00000000000 --- a/dts/upstream/Bindings/net/amd-xgbe.txt +++ /dev/null @@ -1,76 +0,0 @@ -* AMD 10GbE driver (amd-xgbe) - -Required properties: -- compatible: Should be "amd,xgbe-seattle-v1a" -- reg: Address and length of the register sets for the device - - MAC registers - - PCS registers - - SerDes Rx/Tx registers - - SerDes integration registers (1/2) - - SerDes integration registers (2/2) -- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt - listed is required and is the general device interrupt. If the optional - amd,per-channel-interrupt property is specified, then one additional - interrupt for each DMA channel supported by the device should be specified. - The last interrupt listed should be the PCS auto-negotiation interrupt. -- clocks: - - DMA clock for the amd-xgbe device (used for calculating the - correct Rx interrupt watchdog timer value on a DMA channel - for coalescing) - - PTP clock for the amd-xgbe device -- clock-names: Should be the names of the clocks - - "dma_clk" for the DMA clock - - "ptp_clk" for the PTP clock -- phy-mode: See ethernet.txt file in the same directory - -Optional properties: -- dma-coherent: Present if dma operations are coherent -- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate - a unique interrupt for each DMA channel - this requires an additional - interrupt be configured for each DMA channel -- amd,speed-set: Speed capabilities of the device - 0 - 1GbE and 10GbE (default) - 1 - 2.5GbE and 10GbE - -The MAC address will be determined using the optional properties defined in -ethernet.txt. - -The following optional properties are represented by an array with each -value corresponding to a particular speed. The first array value represents -the setting for the 1GbE speed, the second value for the 2.5GbE speed and -the third value for the 10GbE speed. All three values are required if the -property is used. -- amd,serdes-blwc: Baseline wandering correction enablement - 0 - Off - 1 - On -- amd,serdes-cdr-rate: CDR rate speed selection -- amd,serdes-pq-skew: PQ (data sampling) skew -- amd,serdes-tx-amp: TX amplitude boost -- amd,serdes-dfe-tap-config: DFE taps available to run -- amd,serdes-dfe-tap-enable: DFE taps to enable - -Example: - xgbe@e0700000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>, - <0 0xe1240800 0 0x00400>, - <0 0xe1250000 0 0x00060>, - <0 0xe1250080 0 0x00004>; - interrupt-parent = <&gic>; - interrupts = <0 325 4>, - <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, - <0 323 4>; - amd,per-channel-interrupt; - clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - mac-address = [ 02 a1 a2 a3 a4 a5 ]; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <30>; - amd,serdes-tx-amp = <15>, <15>, <10>; - amd,serdes-dfe-tap-config = <3>, <3>, <1>; - amd,serdes-dfe-tap-enable = <0>, <0>, <127>; - }; diff --git a/dts/upstream/Bindings/net/aspeed,ast2600-mdio.yaml b/dts/upstream/Bindings/net/aspeed,ast2600-mdio.yaml index d6ef468495c..a105dc07ed1 100644 --- a/dts/upstream/Bindings/net/aspeed,ast2600-mdio.yaml +++ b/dts/upstream/Bindings/net/aspeed,ast2600-mdio.yaml @@ -19,7 +19,12 @@ allOf: properties: compatible: - const: aspeed,ast2600-mdio + oneOf: + - const: aspeed,ast2600-mdio + - items: + - enum: + - aspeed,ast2700-mdio + - const: aspeed,ast2600-mdio reg: maxItems: 1 diff --git a/dts/upstream/Bindings/net/bluetooth/brcm,bluetooth.yaml b/dts/upstream/Bindings/net/bluetooth/brcm,bluetooth.yaml index 3c410cadff2..95501e858e6 100644 --- a/dts/upstream/Bindings/net/bluetooth/brcm,bluetooth.yaml +++ b/dts/upstream/Bindings/net/bluetooth/brcm,bluetooth.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Broadcom Bluetooth Chips maintainers: - - Linus Walleij + - Linus Walleij description: This binding describes Broadcom UART-attached bluetooth chips. diff --git a/dts/upstream/Bindings/net/bluetooth/marvell,sd8897-bt.yaml b/dts/upstream/Bindings/net/bluetooth/marvell,sd8897-bt.yaml new file mode 100644 index 00000000000..a307c64cfa4 --- /dev/null +++ b/dts/upstream/Bindings/net/bluetooth/marvell,sd8897-bt.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/bluetooth/marvell,sd8897-bt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO) + +maintainers: + - Ariel D'Alessandro + +allOf: + - $ref: /schemas/net/bluetooth/bluetooth-controller.yaml# + +properties: + compatible: + enum: + - marvell,sd8897-bt + - marvell,sd8997-bt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + marvell,cal-data: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Calibration data downloaded to the device during initialization. + maxItems: 28 + + marvell,wakeup-pin: + $ref: /schemas/types.yaml#/definitions/uint16 + description: + Wakeup pin number of the bluetooth chip. Used by firmware to wakeup host + system. + + marvell,wakeup-gap-ms: + $ref: /schemas/types.yaml#/definitions/uint16 + description: + Wakeup latency of the host platform. Required by the chip sleep feature. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + mmc { + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + + bluetooth@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&pio>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + + marvell,cal-data = /bits/ 8 < + 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 + 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0xf0 0x00>; + marvell,wakeup-pin = /bits/ 16 <0x0d>; + marvell,wakeup-gap-ms = /bits/ 16 <0x64>; + }; + }; + +... diff --git a/dts/upstream/Bindings/net/brcm,bcmgenet.yaml b/dts/upstream/Bindings/net/brcm,bcmgenet.yaml index 0e3fb4e42e3..a1119c47e29 100644 --- a/dts/upstream/Bindings/net/brcm,bcmgenet.yaml +++ b/dts/upstream/Bindings/net/brcm,bcmgenet.yaml @@ -31,7 +31,6 @@ properties: - description: RX and TX rings interrupt line - description: Wake-on-LAN interrupt line - clocks: minItems: 1 items: diff --git a/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml b/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml index 3f27746d9a5..d544f785e6b 100644 --- a/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml +++ b/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml @@ -29,7 +29,6 @@ properties: maxItems: 1 description: core clock driving the MDIO block - required: - compatible - reg diff --git a/dts/upstream/Bindings/net/btusb.txt b/dts/upstream/Bindings/net/btusb.txt index f546b1f7dd6..a68022a57c5 100644 --- a/dts/upstream/Bindings/net/btusb.txt +++ b/dts/upstream/Bindings/net/btusb.txt @@ -14,7 +14,7 @@ Required properties: Also, vendors that use btusb may have device additional properties, e.g: -Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt +Documentation/devicetree/bindings/net/bluetooth/marvell,sd8897-bt.yaml Optional properties: diff --git a/dts/upstream/Bindings/net/can/bosch,m_can.yaml b/dts/upstream/Bindings/net/can/bosch,m_can.yaml index 61ef60d8f1c..2c9d37975be 100644 --- a/dts/upstream/Bindings/net/can/bosch,m_can.yaml +++ b/dts/upstream/Bindings/net/can/bosch,m_can.yaml @@ -109,6 +109,26 @@ properties: maximum: 32 minItems: 1 + pinctrl-0: + description: Default pinctrl state + + pinctrl-1: + description: Can be "sleep" or "wakeup" pinctrl state + + pinctrl-2: + description: Can be "sleep" or "wakeup" pinctrl state + + pinctrl-names: + description: + When present should contain at least "default" describing the default pin + states. Other states are "sleep" which describes the pinstate when + sleeping and "wakeup" describing the pins if wakeup is enabled. + minItems: 1 + items: + - const: default + - enum: [ sleep, wakeup ] + - const: wakeup + power-domains: description: Power domain provider node and an args specifier containing @@ -125,6 +145,11 @@ properties: minItems: 1 maxItems: 2 + wakeup-source: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + List of phandles to system idle states in which mcan can wakeup the system. + required: - compatible - reg diff --git a/dts/upstream/Bindings/net/can/microchip,mcp251xfd.yaml b/dts/upstream/Bindings/net/can/microchip,mcp251xfd.yaml index c155c9c6db3..2d13638ebc6 100644 --- a/dts/upstream/Bindings/net/can/microchip,mcp251xfd.yaml +++ b/dts/upstream/Bindings/net/can/microchip,mcp251xfd.yaml @@ -49,6 +49,11 @@ properties: Must be half or less of "clocks" frequency. maximum: 20000000 + gpio-controller: true + + "#gpio-cells": + const: 2 + required: - compatible - reg diff --git a/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml b/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml index 1219c5cb601..519a11fbe97 100644 --- a/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml +++ b/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml @@ -32,11 +32,15 @@ properties: - description: AHB peripheral clock - description: CAN bus clock + resets: + maxItems: 1 + required: - compatible - reg - interrupts - clocks + - resets additionalProperties: false @@ -46,6 +50,7 @@ examples: compatible = "microchip,mpfs-can"; reg = <0x2010c000 0x1000>; clocks = <&clkcfg 17>, <&clkcfg 37>; + resets = <&clkcfg 17>; interrupt-parent = <&plic>; interrupts = <56>; }; diff --git a/dts/upstream/Bindings/net/cdns,macb.yaml b/dts/upstream/Bindings/net/cdns,macb.yaml index 1029786a855..cb14c35ba99 100644 --- a/dts/upstream/Bindings/net/cdns,macb.yaml +++ b/dts/upstream/Bindings/net/cdns,macb.yaml @@ -38,7 +38,10 @@ properties: - cdns,sam9x60-macb # Microchip sam9x60 SoC - microchip,mpfs-macb # Microchip PolarFire SoC - const: cdns,macb # Generic - + - items: + - const: microchip,pic64gx-macb # Microchip PIC64GX SoC + - const: microchip,mpfs-macb # Microchip PolarFire SoC + - const: cdns,macb # Generic - items: - enum: - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs @@ -47,18 +50,19 @@ properties: - const: cdns,macb # Generic - enum: - - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs + - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs - - cdns,np4-macb # NP4 SoC devices - - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface - - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface - - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface - - sifive,fu540-c000-gem # SiFive FU540-C000 SoC - cdns,emac # Generic - cdns,gem # Generic - cdns,macb # Generic + - cdns,np4-macb # NP4 SoC devices + - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface + - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + - mobileye,eyeq5-gem # Mobileye EyeQ5 SoCs + - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface + - sifive,fu540-c000-gem # SiFive FU540-C000 SoC - items: - enum: @@ -183,6 +187,15 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-gem + then: + required: + - phys + unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/net/cortina,gemini-ethernet.yaml b/dts/upstream/Bindings/net/cortina,gemini-ethernet.yaml index 44fd23a5fa2..f0b5bea2458 100644 --- a/dts/upstream/Bindings/net/cortina,gemini-ethernet.yaml +++ b/dts/upstream/Bindings/net/cortina,gemini-ethernet.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cortina Systems Gemini Ethernet Controller maintainers: - - Linus Walleij + - Linus Walleij description: | This ethernet controller is found in the Gemini SoC family: @@ -100,7 +100,6 @@ examples: }; }; - ethernet@60000000 { compatible = "cortina,gemini-ethernet"; reg = <0x60000000 0x4000>, /* Global registers, queue */ diff --git a/dts/upstream/Bindings/net/dsa/lantiq,gswip.yaml b/dts/upstream/Bindings/net/dsa/lantiq,gswip.yaml index f3154b19af7..205b683849a 100644 --- a/dts/upstream/Bindings/net/dsa/lantiq,gswip.yaml +++ b/dts/upstream/Bindings/net/dsa/lantiq,gswip.yaml @@ -4,10 +4,14 @@ $id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Lantiq GSWIP Ethernet switches +title: Lantiq GSWIP and MaxLinear GSW1xx Ethernet switches -allOf: - - $ref: dsa.yaml#/$defs/ethernet-ports +description: + Lantiq GSWIP and MaxLinear GSW1xx switches share the same hardware IP. + Lantiq switches are embedded in SoCs and accessed via memory-mapped I/O, + while MaxLinear switches are standalone ICs connected via MDIO. + +$ref: dsa.yaml# maintainers: - Hauke Mehrtens @@ -18,9 +22,14 @@ properties: - lantiq,xrx200-gswip - lantiq,xrx300-gswip - lantiq,xrx330-gswip + - maxlinear,gsw120 + - maxlinear,gsw125 + - maxlinear,gsw140 + - maxlinear,gsw141 + - maxlinear,gsw145 reg: - minItems: 3 + minItems: 1 maxItems: 3 reg-names: @@ -37,9 +46,6 @@ properties: compatible: const: lantiq,xrx200-mdio - required: - - compatible - gphy-fw: type: object properties: @@ -91,10 +97,63 @@ properties: additionalProperties: false +patternProperties: + "^(ethernet-)?ports$": + type: object + patternProperties: + "^(ethernet-)?port@[0-6]$": + $ref: dsa-port.yaml# + unevaluatedProperties: false + + properties: + maxlinear,rmii-refclk-out: + type: boolean + description: + Configure the RMII reference clock to be a clock output + rather than an input. Only applicable for RMII mode. + tx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII TX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. + rx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII RX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. + required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - lantiq,xrx200-gswip + - lantiq,xrx300-gswip + - lantiq,xrx330-gswip + then: + properties: + reg: + minItems: 3 + maxItems: 3 + mdio: + required: + - compatible + else: + properties: + reg: + maxItems: 1 + reg-names: false + gphy-fw: false + unevaluatedProperties: false examples: @@ -113,8 +172,10 @@ examples: port@0 { reg = <0>; label = "lan3"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; }; port@1 { @@ -200,3 +261,90 @@ examples: }; }; }; + + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "maxlinear,gsw125"; + reg = <0x1f>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&switchphy0>; + phy-mode = "internal"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switchphy1>; + phy-mode = "internal"; + }; + + port@4 { + reg = <4>; + label = "wan"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + ethernet = <ð0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + }; + }; + }; + + switchphy1: switchphy@1 { + reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + }; + }; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/net/dsa/micrel,ks8995.yaml b/dts/upstream/Bindings/net/dsa/micrel,ks8995.yaml index 854808ff5ad..e9ce3606703 100644 --- a/dts/upstream/Bindings/net/dsa/micrel,ks8995.yaml +++ b/dts/upstream/Bindings/net/dsa/micrel,ks8995.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Micrel KS8995 Family DSA Switches maintainers: - - Linus Walleij + - Linus Walleij description: The Micrel KS8995 DSA Switches are 100 Mbit switches that were produced in diff --git a/dts/upstream/Bindings/net/dsa/motorcomm,yt921x.yaml b/dts/upstream/Bindings/net/dsa/motorcomm,yt921x.yaml new file mode 100644 index 00000000000..33a6552e46f --- /dev/null +++ b/dts/upstream/Bindings/net/dsa/motorcomm,yt921x.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/motorcomm,yt921x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Motorcomm YT921x Ethernet switch family + +maintainers: + - David Yang + +description: | + The Motorcomm YT921x series is a family of Ethernet switches with up to 8 + internal GbE PHYs and up to 2 GMACs, including: + + - YT9215S / YT9215RB / YT9215SC: 5 GbE PHYs (Port 0-4) + 2 GMACs (Port 8-9) + - YT9213NB: 2 GbE PHYs (Port 1/3) + 1 GMAC (Port 9) + - YT9214NB: 2 GbE PHYs (Port 1/3) + 2 GMACs (Port 8-9) + - YT9218N: 8 GbE PHYs (Port 0-7) + - YT9218MB: 8 GbE PHYs (Port 0-7) + 2 GMACs (Port 8-9) + + Any port can be used as the CPU port. + +properties: + compatible: + const: motorcomm,yt9215 + + reg: + enum: [0x0, 0x1d] + + reset-gpios: + maxItems: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: + Internal MDIO bus for the internal GbE PHYs. PHY 0-7 are used for Port + 0-7 respectively. + + mdio-external: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: + External MDIO bus to access external components. External PHYs for GMACs + (Port 8-9) are expected to be connected to the external MDIO bus in + vendor's reference design, but that is not a hard limitation from the + chip. + +required: + - compatible + - reg + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@1d { + compatible = "motorcomm,yt9215"; + /* default 0x1d, alternate 0x0 */ + reg = <0x1d>; + reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: phy@0 { + reg = <0x0>; + }; + + sw_phy1: phy@1 { + reg = <0x1>; + }; + + sw_phy2: phy@2 { + reg = <0x2>; + }; + + sw_phy3: phy@3 { + reg = <0x3>; + }; + + sw_phy4: phy@4 { + reg = <0x4>; + }; + }; + + mdio-external { + #address-cells = <1>; + #size-cells = <0>; + + phy1: phy@b { + reg = <0xb>; + }; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&sw_phy0>; + }; + + ethernet-port@1 { + reg = <1>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&sw_phy1>; + }; + + ethernet-port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&sw_phy2>; + }; + + ethernet-port@3 { + reg = <3>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&sw_phy3>; + }; + + ethernet-port@4 { + reg = <4>; + label = "lan5"; + phy-mode = "internal"; + phy-handle = <&sw_phy4>; + }; + + /* CPU port */ + ethernet-port@8 { + reg = <8>; + phy-mode = "2500base-x"; + ethernet = <ð0>; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + /* if external phy is connected to a MAC */ + ethernet-port@9 { + reg = <9>; + label = "wan"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/net/dsa/nxp,sja1105.yaml b/dts/upstream/Bindings/net/dsa/nxp,sja1105.yaml index e9dd914b073..607b7fe8d28 100644 --- a/dts/upstream/Bindings/net/dsa/nxp,sja1105.yaml +++ b/dts/upstream/Bindings/net/dsa/nxp,sja1105.yaml @@ -41,6 +41,9 @@ properties: therefore discouraged. maxItems: 1 + clocks: + maxItems: 1 + spi-cpha: true spi-cpol: true diff --git a/dts/upstream/Bindings/net/dsa/realtek.yaml b/dts/upstream/Bindings/net/dsa/realtek.yaml index f348e66fb51..473facd87a6 100644 --- a/dts/upstream/Bindings/net/dsa/realtek.yaml +++ b/dts/upstream/Bindings/net/dsa/realtek.yaml @@ -10,7 +10,7 @@ allOf: - $ref: dsa.yaml#/$defs/ethernet-ports maintainers: - - Linus Walleij + - Linus Walleij description: Realtek advertises these chips as fast/gigabit switches or unmanaged diff --git a/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.yaml b/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.yaml index 51cf574249b..c41f479bdee 100644 --- a/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.yaml +++ b/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Vitesse VSC73xx DSA Switches maintainers: - - Linus Walleij + - Linus Walleij description: The Vitesse DSA Switches were produced in the early-to-mid 2000s. diff --git a/dts/upstream/Bindings/net/eswin,eic7700-eth.yaml b/dts/upstream/Bindings/net/eswin,eic7700-eth.yaml new file mode 100644 index 00000000000..91e8cd1db67 --- /dev/null +++ b/dts/upstream/Bindings/net/eswin,eic7700-eth.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SOC Eth Controller + +maintainers: + - Shuang Liang + - Zhi Li + - Shangjuan Wei + +description: + Platform glue layer implementation for STMMAC Ethernet driver. + +select: + properties: + compatible: + contains: + enum: + - eswin,eic7700-qos-eth + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - const: eswin,eic7700-qos-eth + - const: snps,dwmac-5.20 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + + clocks: + items: + - description: AXI clock + - description: Configuration clock + - description: GMAC main clock + - description: Tx clock + + clock-names: + items: + - const: axi + - const: cfg + - const: stmmaceth + - const: tx + + resets: + maxItems: 1 + + reset-names: + items: + - const: stmmaceth + + rx-internal-delay-ps: + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + + tx-internal-delay-ps: + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + + eswin,hsp-sp-csr: + description: + HSP CSR is to control and get status of different high-speed peripherals + (such as Ethernet, USB, SATA, etc.) via register, which can tune + board-level's parameters of PHY, etc. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to HSP(High-Speed Peripheral) device + - description: Offset of phy control register for internal + or external clock selection + - description: Offset of AXI clock controller Low-Power request + register + - description: Offset of register controlling TX/RX clock delay + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phy-mode + - resets + - reset-names + - rx-internal-delay-ps + - tx-internal-delay-ps + - eswin,hsp-sp-csr + +unevaluatedProperties: false + +examples: + - | + ethernet@50400000 { + compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; + reg = <0x50400000 0x10000>; + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 193>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + interrupt-parent = <&plic>; + interrupts = <61>; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + resets = <&reset 95>; + reset-names = "stmmaceth"; + rx-internal-delay-ps = <200>; + tx-internal-delay-ps = <200>; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>; + snps,axi-config = <&stmmac_axi_setup>; + snps,aal; + snps,fixed-burst; + snps,tso; + stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; diff --git a/dts/upstream/Bindings/net/ethernet-phy.yaml b/dts/upstream/Bindings/net/ethernet-phy.yaml index 2ec2d9fda7e..bb4c49fc5fd 100644 --- a/dts/upstream/Bindings/net/ethernet-phy.yaml +++ b/dts/upstream/Bindings/net/ethernet-phy.yaml @@ -35,9 +35,13 @@ properties: description: PHYs that implement IEEE802.3 clause 45 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" description: - If the PHY reports an incorrect ID (or none at all) then the - compatible list may contain an entry with the correct PHY ID - in the above form. + PHYs contain identification registers. These will be read to + identify the PHY. If the PHY reports an incorrect ID, or the + PHY requires a specific initialization sequence (like a + particular order of clocks, resets, power supplies), in + order to be able to read the ID registers, then the + compatible list must contain an entry with the correct PHY + ID in the above form. The first group of digits is the 16 bit Phy Identifier 1 register, this is the chip vendor OUI bits 3:18. The second group of digits is the Phy Identifier 2 register, diff --git a/dts/upstream/Bindings/net/ethernet-switch.yaml b/dts/upstream/Bindings/net/ethernet-switch.yaml index b3b7e1a1b12..6bb68f7dbc7 100644 --- a/dts/upstream/Bindings/net/ethernet-switch.yaml +++ b/dts/upstream/Bindings/net/ethernet-switch.yaml @@ -35,14 +35,14 @@ allOf: then: properties: $nodename: - pattern: "switch[0-3]@[0-3]+$" + pattern: 'switch[0-3]@[0-3]+$' else: properties: $nodename: - pattern: "^(ethernet-)?switch(@.*)?$" + pattern: '^(ethernet-)?switch(@.*)?$' patternProperties: - "^(ethernet-)?ports$": + '^(ethernet-)?ports$': type: object unevaluatedProperties: false @@ -53,13 +53,13 @@ patternProperties: const: 0 patternProperties: - "^(ethernet-)?port@[0-9a-f]+$": + '^(ethernet-)?port@[0-9a-f]+$': type: object description: Ethernet switch ports required: - - "#address-cells" - - "#size-cells" + - '#address-cells' + - '#size-cells' oneOf: - required: @@ -75,9 +75,9 @@ $defs: $ref: '#' patternProperties: - "^(ethernet-)?ports$": + '^(ethernet-)?ports$': patternProperties: - "^(ethernet-)?port@[0-9a-f]+$": + '^(ethernet-)?port@[0-9a-f]+$': description: Ethernet switch ports $ref: ethernet-switch-port.yaml# unevaluatedProperties: false diff --git a/dts/upstream/Bindings/net/fsl,enetc.yaml b/dts/upstream/Bindings/net/fsl,enetc.yaml index ca70f005017..aac20ab72ac 100644 --- a/dts/upstream/Bindings/net/fsl,enetc.yaml +++ b/dts/upstream/Bindings/net/fsl,enetc.yaml @@ -27,6 +27,7 @@ properties: - const: fsl,enetc - enum: - pci1131,e101 + - pci1131,e110 reg: maxItems: 1 diff --git a/dts/upstream/Bindings/net/fsl,gianfar.yaml b/dts/upstream/Bindings/net/fsl,gianfar.yaml index f92f284aa05..0d8909770cc 100644 --- a/dts/upstream/Bindings/net/fsl,gianfar.yaml +++ b/dts/upstream/Bindings/net/fsl,gianfar.yaml @@ -167,8 +167,6 @@ allOf: - description: Receive interrupt - description: Error interrupt - - unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/net/intel,ixp46x-ptp-timer.yaml b/dts/upstream/Bindings/net/intel,ixp46x-ptp-timer.yaml index f92730b1d2f..80336b7e64e 100644 --- a/dts/upstream/Bindings/net/intel,ixp46x-ptp-timer.yaml +++ b/dts/upstream/Bindings/net/intel,ixp46x-ptp-timer.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP46x PTP Timer (TSYNC) maintainers: - - Linus Walleij + - Linus Walleij description: | The Intel IXP46x PTP timer is known in the manual as IEEE1588 Hardware diff --git a/dts/upstream/Bindings/net/intel,ixp4xx-ethernet.yaml b/dts/upstream/Bindings/net/intel,ixp4xx-ethernet.yaml index 8689de1aaea..3b8f83b7099 100644 --- a/dts/upstream/Bindings/net/intel,ixp4xx-ethernet.yaml +++ b/dts/upstream/Bindings/net/intel,ixp4xx-ethernet.yaml @@ -11,7 +11,7 @@ allOf: - $ref: ethernet-controller.yaml# maintainers: - - Linus Walleij + - Linus Walleij description: | The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network diff --git a/dts/upstream/Bindings/net/intel,ixp4xx-hss.yaml b/dts/upstream/Bindings/net/intel,ixp4xx-hss.yaml index 7a405e9b37b..1d952735c81 100644 --- a/dts/upstream/Bindings/net/intel,ixp4xx-hss.yaml +++ b/dts/upstream/Bindings/net/intel,ixp4xx-hss.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx V.35 WAN High Speed Serial Link (HSS) maintainers: - - Linus Walleij + - Linus Walleij description: | The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network diff --git a/dts/upstream/Bindings/net/marvell-bt-8xxx.txt b/dts/upstream/Bindings/net/marvell-bt-8xxx.txt deleted file mode 100644 index 957e5e5c292..00000000000 --- a/dts/upstream/Bindings/net/marvell-bt-8xxx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based) ------- -The 8997 devices supports multiple interfaces. When used on SDIO interfaces, -the btmrvl driver is used and when used on USB interface, the btusb driver is -used. - -Required properties: - - - compatible : should be one of the following: - * "marvell,sd8897-bt" (for SDIO) - * "marvell,sd8997-bt" (for SDIO) - * "usb1286,204e" (for USB) - -Optional properties: - - - marvell,cal-data: Calibration data downloaded to the device during - initialization. This is an array of 28 values(u8). - This is only applicable to SDIO devices. - - - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip. - firmware will use the pin to wakeup host system (u16). - - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host - platform. The value will be configured to firmware. This - is needed to work chip's sleep feature as expected (u16). - - interrupt-names: Used only for USB based devices (See below) - - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the - driver will use the first interrupt specified in the interrupt - array. For USB based devices, the driver will use the interrupt - named "wakeup" from the interrupt-names and interrupt arrays. - The driver will request an irq based on this interrupt number. - During system suspend, the irq will be enabled so that the - bluetooth chip can wakeup host platform under certain - conditions. During system resume, the irq will be disabled - to make sure unnecessary interrupt is not received. - -Example: - -IRQ pin 119 is used as system wakeup source interrupt. -wakeup pin 13 and gap 100ms are configured so that firmware can wakeup host -using this device side pin and wakeup latency. - -Example for SDIO device follows (calibration data is also available in -below example). - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - btmrvl: bluetooth@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&pio>; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - - marvell,cal-data = /bits/ 8 < - 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 - 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0xf0 0x00>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; - -Example for USB device: - -&usb_host1_ohci { - #address-cells = <1>; - #size-cells = <0>; - - mvl_bt1: bt@1 { - compatible = "usb1286,204e"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupt-names = "wakeup"; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; diff --git a/dts/upstream/Bindings/net/mdio-mux-multiplexer.yaml b/dts/upstream/Bindings/net/mdio-mux-multiplexer.yaml index 282987074ee..23947ba6aea 100644 --- a/dts/upstream/Bindings/net/mdio-mux-multiplexer.yaml +++ b/dts/upstream/Bindings/net/mdio-mux-multiplexer.yaml @@ -14,7 +14,6 @@ description: |+ of a mux producer device. The mux producer can be of any type like mmio mux producer, gpio mux producer or generic register based mux producer. - allOf: - $ref: /schemas/net/mdio-mux.yaml# diff --git a/dts/upstream/Bindings/net/mediatek,net.yaml b/dts/upstream/Bindings/net/mediatek,net.yaml index b45f67f92e8..cc346946291 100644 --- a/dts/upstream/Bindings/net/mediatek,net.yaml +++ b/dts/upstream/Bindings/net/mediatek,net.yaml @@ -112,7 +112,7 @@ properties: mediatek,wed: $ref: /schemas/types.yaml#/definitions/phandle-array - minItems: 2 + minItems: 1 maxItems: 2 items: maxItems: 1 @@ -249,6 +249,9 @@ allOf: minItems: 1 maxItems: 1 + mediatek,wed: + minItems: 2 + mediatek,wed-pcie: false else: properties: @@ -338,12 +341,13 @@ allOf: - const: netsys0 - const: netsys1 - mediatek,infracfg: false - mediatek,sgmiisys: minItems: 2 maxItems: 2 + mediatek,wed: + maxItems: 1 + - if: properties: compatible: @@ -385,6 +389,9 @@ allOf: minItems: 2 maxItems: 2 + mediatek,wed: + minItems: 2 + - if: properties: compatible: @@ -429,6 +436,19 @@ allOf: - const: xgp2 - const: xgp3 + mediatek,wed: + minItems: 2 + + - if: + properties: + compatible: + contains: + const: ralink,rt5350-eth + then: + properties: + mediatek,wed: + minItems: 2 + patternProperties: "^mac@[0-2]$": type: object diff --git a/dts/upstream/Bindings/net/mscc-phy-vsc8531.txt b/dts/upstream/Bindings/net/mscc-phy-vsc8531.txt deleted file mode 100644 index 0a3647fe331..00000000000 --- a/dts/upstream/Bindings/net/mscc-phy-vsc8531.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Microsemi - vsc8531 Giga bit ethernet phy - -Optional properties: -- vsc8531,vddmac : The vddmac in mV. Allowed values is listed - in the first row of Table 1 (below). - This property is only used in combination - with the 'edge-slowdown' property. - Default value is 3300. -- vsc8531,edge-slowdown : % the edge should be slowed down relative to - the fastest possible edge time. - Edge rate sets the drive strength of the MAC - interface output signals. Changing the - drive strength will affect the edge rate of - the output signal. The goal of this setting - is to help reduce electrical emission (EMI) - by being able to reprogram drive strength - and in effect slow down the edge rate if - desired. - To adjust the edge-slowdown, the 'vddmac' - must be specified. Table 1 lists the - supported edge-slowdown values for a given - 'vddmac'. - Default value is 0%. - Ref: Table:1 - Edge rate change (below). -- vsc8531,led-[N]-mode : LED mode. Specify how the LED[N] should behave. - N depends on the number of LEDs supported by a - PHY. - Allowed values are defined in - "include/dt-bindings/net/mscc-phy-vsc8531.h". - Default values are VSC8531_LINK_1000_ACTIVITY (1), - VSC8531_LINK_100_ACTIVITY (2), - VSC8531_LINK_ACTIVITY (0) and - VSC8531_DUPLEX_COLLISION (8). -- load-save-gpios : GPIO used for the load/save operation of the PTP - hardware clock (PHC). - - -Table: 1 - Edge rate change -----------------------------------------------------------------| -| Edge Rate Change (VDDMAC) | -| | -| 3300 mV 2500 mV 1800 mV 1500 mV | -|---------------------------------------------------------------| -| 0% 0% 0% 0% | -| (Fastest) (recommended) (recommended) | -|---------------------------------------------------------------| -| 2% 3% 5% 6% | -|---------------------------------------------------------------| -| 4% 6% 9% 14% | -|---------------------------------------------------------------| -| 7% 10% 16% 21% | -|(recommended) (recommended) | -|---------------------------------------------------------------| -| 10% 14% 23% 29% | -|---------------------------------------------------------------| -| 17% 23% 35% 42% | -|---------------------------------------------------------------| -| 29% 37% 52% 58% | -|---------------------------------------------------------------| -| 53% 63% 76% 77% | -| (slowest) | -|---------------------------------------------------------------| - -Example: - - vsc8531_0: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.0570"; - vsc8531,vddmac = <3300>; - vsc8531,edge-slowdown = <7>; - vsc8531,led-0-mode = ; - vsc8531,led-1-mode = ; - load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; - }; diff --git a/dts/upstream/Bindings/net/mscc-phy-vsc8531.yaml b/dts/upstream/Bindings/net/mscc-phy-vsc8531.yaml new file mode 100644 index 00000000000..0afbd0ff126 --- /dev/null +++ b/dts/upstream/Bindings/net/mscc-phy-vsc8531.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mscc-phy-vsc8531.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi VSC8531 Gigabit Ethernet PHY + +maintainers: + - Lad Prabhakar + +description: + The VSC8531 is a Gigabit Ethernet PHY with configurable MAC interface + drive strength and LED modes. + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-id0007.0570 # VSC8531 + - ethernet-phy-id0007.0772 # VSC8541 + required: + - compatible + +properties: + compatible: + items: + - enum: + - ethernet-phy-id0007.0570 # VSC8531 + - ethernet-phy-id0007.0772 # VSC8541 + - const: ethernet-phy-ieee802.3-c22 + + vsc8531,vddmac: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The VDDMAC voltage in millivolts. This property is used in combination + with the edge-slowdown property to control the drive strength of the + MAC interface output signals. + enum: [3300, 2500, 1800, 1500] + default: 3300 + + vsc8531,edge-slowdown: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Percentage by which the edge rate should be slowed down relative to + the fastest possible edge time. This setting helps reduce electromagnetic + interference (EMI) by adjusting the drive strength of the MAC interface + output signals. Valid values depend on the vddmac voltage setting + according to the edge rate change table in the datasheet. + + - When vsc8531,vddmac = 3300 mV: allowed values are 0, 2, 4, 7, 10, 17, 29, and 53. + (Recommended: 7) + - When vsc8531,vddmac = 2500 mV: allowed values are 0, 3, 6, 10, 14, 23, 37, and 63. + (Recommended: 10) + - When vsc8531,vddmac = 1800 mV: allowed values are 0, 5, 9, 16, 23, 35, 52, and 76. + (Recommended: 0) + - When vsc8531,vddmac = 1500 mV: allowed values are 0, 6, 14, 21, 29, 42, 58, and 77. + (Recommended: 0) + enum: [0, 2, 3, 4, 5, 6, 7, 9, 10, 14, 16, 17, 21, 23, 29, 35, 37, 42, 52, 53, 58, 63, 76, 77] + default: 0 + + vsc8531,led-0-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[0] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 1 + + vsc8531,led-1-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[1] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 2 + + vsc8531,led-2-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[2] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 0 + + vsc8531,led-3-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[3] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 8 + + load-save-gpios: + description: GPIO phandle used for the load/save operation of the PTP hardware + clock (PHC). + maxItems: 1 + +dependencies: + vsc8531,edge-slowdown: + - vsc8531,vddmac + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + vsc8531,vddmac = <3300>; + vsc8531,edge-slowdown = <7>; + vsc8531,led-0-mode = ; + vsc8531,led-1-mode = ; + load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/dts/upstream/Bindings/net/nxp,netc-blk-ctrl.yaml b/dts/upstream/Bindings/net/nxp,netc-blk-ctrl.yaml index 97389fd5dbb..deea4fd73d7 100644 --- a/dts/upstream/Bindings/net/nxp,netc-blk-ctrl.yaml +++ b/dts/upstream/Bindings/net/nxp,netc-blk-ctrl.yaml @@ -21,6 +21,7 @@ maintainers: properties: compatible: enum: + - nxp,imx94-netc-blk-ctrl - nxp,imx95-netc-blk-ctrl reg: diff --git a/dts/upstream/Bindings/net/pse-pd/ti,tps23881.yaml b/dts/upstream/Bindings/net/pse-pd/ti,tps23881.yaml index bb1ee339865..0b3803f647b 100644 --- a/dts/upstream/Bindings/net/pse-pd/ti,tps23881.yaml +++ b/dts/upstream/Bindings/net/pse-pd/ti,tps23881.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - ti,tps23881 + - ti,tps23881b reg: maxItems: 1 diff --git a/dts/upstream/Bindings/net/qcom,ethqos.yaml b/dts/upstream/Bindings/net/qcom,ethqos.yaml index e7ee0d9efed..423959cb928 100644 --- a/dts/upstream/Bindings/net/qcom,ethqos.yaml +++ b/dts/upstream/Bindings/net/qcom,ethqos.yaml @@ -73,6 +73,14 @@ properties: dma-coherent: true + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-mac + - const: mac-mem + phys: true phy-names: diff --git a/dts/upstream/Bindings/net/qcom,ipa.yaml b/dts/upstream/Bindings/net/qcom,ipa.yaml index b4a79912d47..c7f5f2ef745 100644 --- a/dts/upstream/Bindings/net/qcom,ipa.yaml +++ b/dts/upstream/Bindings/net/qcom,ipa.yaml @@ -24,7 +24,6 @@ description: iommu/iommu.txt and iommu/arm,smmu.yaml for more information about SMMU bindings. - - | -------- --------- | | | | diff --git a/dts/upstream/Bindings/net/rockchip-dwmac.yaml b/dts/upstream/Bindings/net/rockchip-dwmac.yaml index 0ac7c4b47d6..d17112527da 100644 --- a/dts/upstream/Bindings/net/rockchip-dwmac.yaml +++ b/dts/upstream/Bindings/net/rockchip-dwmac.yaml @@ -24,6 +24,7 @@ select: - rockchip,rk3366-gmac - rockchip,rk3368-gmac - rockchip,rk3399-gmac + - rockchip,rk3506-gmac - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac @@ -50,6 +51,7 @@ properties: - rockchip,rv1108-gmac - items: - enum: + - rockchip,rk3506-gmac - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac @@ -148,6 +150,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3506-gmac - rockchip,rk3528-gmac then: properties: diff --git a/dts/upstream/Bindings/net/snps,dwmac.yaml b/dts/upstream/Bindings/net/snps,dwmac.yaml index 658c004e6a5..dd3c72e8363 100644 --- a/dts/upstream/Bindings/net/snps,dwmac.yaml +++ b/dts/upstream/Bindings/net/snps,dwmac.yaml @@ -86,10 +86,14 @@ properties: - rockchip,rk3328-gmac - rockchip,rk3366-gmac - rockchip,rk3368-gmac + - rockchip,rk3399-gmac + - rockchip,rk3506-gmac + - rockchip,rk3528-gmac + - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac - - rockchip,rk3399-gmac - rockchip,rv1108-gmac + - rockchip,rv1126-gmac - snps,dwmac - snps,dwmac-3.40a - snps,dwmac-3.50a diff --git a/dts/upstream/Bindings/net/sophgo,sg2044-dwmac.yaml b/dts/upstream/Bindings/net/sophgo,sg2044-dwmac.yaml index ce21979a2d9..e8d3814db0e 100644 --- a/dts/upstream/Bindings/net/sophgo,sg2044-dwmac.yaml +++ b/dts/upstream/Bindings/net/sophgo,sg2044-dwmac.yaml @@ -70,6 +70,25 @@ required: allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: sophgo,sg2042-dwmac + then: + properties: + phy-mode: + enum: + - rgmii-rxid + - rgmii-id + else: + properties: + phy-mode: + enum: + - rgmii + - rgmii-rxid + - rgmii-txid + - rgmii-id unevaluatedProperties: false diff --git a/dts/upstream/Bindings/net/ti,cpsw-switch.yaml b/dts/upstream/Bindings/net/ti,cpsw-switch.yaml index d14ca81f70e..8b5da602a2e 100644 --- a/dts/upstream/Bindings/net/ti,cpsw-switch.yaml +++ b/dts/upstream/Bindings/net/ti,cpsw-switch.yaml @@ -156,7 +156,6 @@ patternProperties: CPSW MDIO bus. $ref: ti,davinci-mdio.yaml# - required: - compatible - reg diff --git a/dts/upstream/Bindings/net/wireless/mediatek,mt76.yaml b/dts/upstream/Bindings/net/wireless/mediatek,mt76.yaml index eabceb84953..ae6b97cdc44 100644 --- a/dts/upstream/Bindings/net/wireless/mediatek,mt76.yaml +++ b/dts/upstream/Bindings/net/wireless/mediatek,mt76.yaml @@ -151,6 +151,12 @@ properties: - ETSI - JP + country: + $ref: /schemas/types.yaml#/definitions/string + pattern: '^[A-Z]{2}$' + description: + ISO 3166-1 alpha-2 country code for power limits + patternProperties: "^txpower-[256]g$": type: object @@ -210,6 +216,66 @@ properties: minItems: 13 maxItems: 13 + paths-cck: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 4 + maxItems: 4 + description: + 4 half-dBm backoff values (1 - 4 antennas, single spacial + stream) + + paths-ofdm: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 4 + maxItems: 4 + description: + 4 half-dBm backoff values (1 - 4 antennas, single spacial + stream) + + paths-ofdm-bf: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 4 + maxItems: 4 + description: + 4 half-dBm backoff values for beamforming + (1 - 4 antennas, single spacial stream) + + paths-ru: + $ref: /schemas/types.yaml#/definitions/uint8-matrix + description: + Sets of half-dBm backoff values for 802.11ax rates for + 1T1ss (aka 1 transmitting antenna with 1 spacial stream), + 2T1ss, 3T1ss, 4T1ss, 2T2ss, 3T2ss, 4T2ss, 3T3ss, 4T3ss + and 4T4ss. + Each set starts with the number of channel bandwidth or + resource unit settings for which the rate set applies, + followed by 10 power limit values. The order of the + channel resource unit settings is RU26, RU52, RU106, + RU242/SU20, RU484/SU40, RU996/SU80 and RU2x996/SU160. + minItems: 1 + maxItems: 7 + items: + minItems: 11 + maxItems: 11 + + paths-ru-bf: + $ref: /schemas/types.yaml#/definitions/uint8-matrix + description: + Sets of half-dBm backoff (beamforming) values for 802.11ax + rates for 1T1ss (aka 1 transmitting antenna with 1 spacial + stream), 2T1ss, 3T1ss, 4T1ss, 2T2ss, 3T2ss, 4T2ss, 3T3ss, + 4T3ss and 4T4ss. + Each set starts with the number of channel bandwidth or + resource unit settings for which the rate set applies, + followed by 10 power limit values. The order of the + channel resource unit settings is RU26, RU52, RU106, + RU242/SU20, RU484/SU40, RU996/SU80 and RU2x996/SU160. + minItems: 1 + maxItems: 7 + items: + minItems: 11 + maxItems: 11 + txs-delta: $ref: /schemas/types.yaml#/definitions/uint32-array description: diff --git a/dts/upstream/Bindings/net/wireless/ti,wlcore.yaml b/dts/upstream/Bindings/net/wireless/ti,wlcore.yaml index 75c9489f319..9de5fdefcbc 100644 --- a/dts/upstream/Bindings/net/wireless/ti,wlcore.yaml +++ b/dts/upstream/Bindings/net/wireless/ti,wlcore.yaml @@ -50,7 +50,6 @@ properties: Points to the node of the regulator that powers/enable the wl12xx/wl18xx chip. This is required when connected via SPI. - ref-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 description: Reference clock frequency. diff --git a/dts/upstream/Bindings/npu/arm,ethos.yaml b/dts/upstream/Bindings/npu/arm,ethos.yaml new file mode 100644 index 00000000000..716c4997f97 --- /dev/null +++ b/dts/upstream/Bindings/npu/arm,ethos.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/npu/arm,ethos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Ethos U65/U85 + +maintainers: + - Rob Herring + +description: > + The Arm Ethos-U NPUs are designed for IoT inference applications. The NPUs + can accelerate 8-bit and 16-bit integer quantized networks: + + Transformer networks (U85 only) + Convolutional Neural Networks (CNN) + Recurrent Neural Networks (RNN) + + Further documentation is available here: + + U65 TRM: https://developer.arm.com/documentation/102023/ + U85 TRM: https://developer.arm.com/documentation/102685/ + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx93-npu + - const: arm,ethos-u65 + - items: + - {} + - const: arm,ethos-u85 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: apb + + power-domains: + maxItems: 1 + + sram: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + + npu@4a900000 { + compatible = "fsl,imx93-npu", "arm,ethos-u65"; + reg = <0x4a900000 0x1000>; + interrupts = ; + power-domains = <&mlmix>; + clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + clock-names = "core", "apb"; + sram = <&sram>; + }; +... diff --git a/dts/upstream/Bindings/nvmem/brcm,ocotp.txt b/dts/upstream/Bindings/nvmem/brcm,ocotp.txt deleted file mode 100644 index 0415265c215..00000000000 --- a/dts/upstream/Bindings/nvmem/brcm,ocotp.txt +++ /dev/null @@ -1,17 +0,0 @@ -Broadcom OTP memory controller - -Required Properties: -- compatible: "brcm,ocotp" for the first generation Broadcom OTPC which is used - in Cygnus and supports 32 bit read/write. Use "brcm,ocotp-v2" for the second - generation Broadcom OTPC which is used in SoC's such as Stingray and supports - 64-bit read/write. -- reg: Base address of the OTP controller. -- brcm,ocotp-size: Amount of memory available, in 32 bit words - -Example: - -otp: otp@301c800 { - compatible = "brcm,ocotp"; - reg = <0x0301c800 0x2c>; - brcm,ocotp-size = <2048>; -}; diff --git a/dts/upstream/Bindings/nvmem/brcm,ocotp.yaml b/dts/upstream/Bindings/nvmem/brcm,ocotp.yaml new file mode 100644 index 00000000000..ffad2841748 --- /dev/null +++ b/dts/upstream/Bindings/nvmem/brcm,ocotp.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/brcm,ocotp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom OTP memory controller + +maintainers: + - Ray Jui + - Scott Branden + +properties: + compatible: + enum: + - brcm,ocotp + - brcm,ocotp-v2 + + reg: + maxItems: 1 + + brcm,ocotp-size: + description: Amount of memory available, in 32-bit words + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - brcm,ocotp-size + +additionalProperties: false + +examples: + - | + otp@301c800 { + compatible = "brcm,ocotp"; + reg = <0x0301c800 0x2c>; + brcm,ocotp-size = <2048>; + }; diff --git a/dts/upstream/Bindings/nvmem/imx-ocotp.yaml b/dts/upstream/Bindings/nvmem/imx-ocotp.yaml index b2cb76cf905..a8076d0e273 100644 --- a/dts/upstream/Bindings/nvmem/imx-ocotp.yaml +++ b/dts/upstream/Bindings/nvmem/imx-ocotp.yaml @@ -14,7 +14,8 @@ maintainers: description: | This binding represents the on-chip eFuse OTP controller found on i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, - i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP and i.MX93/5 SoCs. + i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN i.MX8MP, i.MX93, i.MX94, + and i.MX95. allOf: - $ref: nvmem.yaml# @@ -36,6 +37,7 @@ properties: - fsl,imx8mq-ocotp - fsl,imx8mm-ocotp - fsl,imx93-ocotp + - fsl,imx94-ocotp - fsl,imx95-ocotp - const: syscon - items: diff --git a/dts/upstream/Bindings/nvmem/layouts/u-boot,env.yaml b/dts/upstream/Bindings/nvmem/layouts/u-boot,env.yaml index 56a8f55d4a0..e9e75c38bd1 100644 --- a/dts/upstream/Bindings/nvmem/layouts/u-boot,env.yaml +++ b/dts/upstream/Bindings/nvmem/layouts/u-boot,env.yaml @@ -46,6 +46,12 @@ properties: type: object description: Command to use for automatic booting + env-size: + description: + Size in bytes of the environment data used by U-Boot for CRC + calculation. If omitted, the full NVMEM region size is used. + $ref: /schemas/types.yaml#/definitions/uint32 + ethaddr: type: object description: Ethernet interfaces base MAC address. @@ -104,6 +110,7 @@ examples: partition-u-boot-env { compatible = "brcm,env"; + env-size = <0x20000>; ethaddr { }; diff --git a/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml b/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml index 4dc0d42df3e..c9bf34ee0ef 100644 --- a/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml +++ b/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml @@ -25,7 +25,9 @@ properties: compatible: oneOf: - items: - - const: mediatek,mt8188-efuse + - enum: + - mediatek,mt8188-efuse + - mediatek,mt8189-efuse - const: mediatek,mt8186-efuse - const: mediatek,mt8186-efuse @@ -48,6 +50,7 @@ properties: - mediatek,mt7988-efuse - mediatek,mt8173-efuse - mediatek,mt8183-efuse + - mediatek,mt8189-efuse - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse diff --git a/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml b/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml index 3f6dc6a3a9f..7d1612acca4 100644 --- a/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml +++ b/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml @@ -39,6 +39,7 @@ properties: - qcom,qcs404-qfprom - qcom,qcs615-qfprom - qcom,qcs8300-qfprom + - qcom,sa8775p-qfprom - qcom,sar2130p-qfprom - qcom,sc7180-qfprom - qcom,sc7280-qfprom diff --git a/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml b/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml index 3b2aa605a55..ab4cdc4e361 100644 --- a/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml +++ b/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml @@ -31,7 +31,7 @@ properties: maxItems: 1 patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]+$": type: object $ref: layouts/fixed-cell.yaml unevaluatedProperties: false diff --git a/dts/upstream/Bindings/pci/altr,pcie-root-port.yaml b/dts/upstream/Bindings/pci/altr,pcie-root-port.yaml index 5d3f48a001b..f516db47ab2 100644 --- a/dts/upstream/Bindings/pci/altr,pcie-root-port.yaml +++ b/dts/upstream/Bindings/pci/altr,pcie-root-port.yaml @@ -93,7 +93,6 @@ allOf: reg-names: minItems: 3 - unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/pci/amlogic,axg-pcie.yaml b/dts/upstream/Bindings/pci/amlogic,axg-pcie.yaml index 79a21ba0f9f..d67cb7a850a 100644 --- a/dts/upstream/Bindings/pci/amlogic,axg-pcie.yaml +++ b/dts/upstream/Bindings/pci/amlogic,axg-pcie.yaml @@ -20,9 +20,10 @@ allOf: select: properties: compatible: - enum: - - amlogic,axg-pcie - - amlogic,g12a-pcie + contains: + enum: + - amlogic,axg-pcie + - amlogic,g12a-pcie required: - compatible @@ -36,13 +37,13 @@ properties: reg: items: - - description: External local bus interface registers + - description: Data Bus Interface registers - description: Meson designed configuration registers - description: PCIe configuration space reg-names: items: - - const: elbi + - const: dbi - const: cfg - const: config @@ -51,15 +52,15 @@ properties: clocks: items: + - description: PCIe PHY clock - description: PCIe GEN 100M PLL clock - description: PCIe RC clock gate - - description: PCIe PHY clock clock-names: items: + - const: general - const: pclk - const: port - - const: general phys: maxItems: 1 @@ -88,7 +89,7 @@ required: - reg - reg-names - interrupts - - clock + - clocks - clock-names - "#address-cells" - "#size-cells" @@ -113,10 +114,10 @@ examples: pcie: pcie@f9800000 { compatible = "amlogic,axg-pcie", "snps,dw-pcie"; reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>; - reg-names = "elbi", "cfg", "config"; + reg-names = "dbi", "cfg", "config"; interrupts = ; - clocks = <&pclk>, <&clk_port>, <&clk_phy>; - clock-names = "pclk", "port", "general"; + clocks = <&clk_phy>, <&pclk>, <&clk_port>; + clock-names = "general", "pclk", "port"; resets = <&reset_pcie_port>, <&reset_pcie_apb>; reset-names = "port", "apb"; phys = <&pcie_phy>; diff --git a/dts/upstream/Bindings/pci/cix,sky1-pcie-host.yaml b/dts/upstream/Bindings/pci/cix,sky1-pcie-host.yaml new file mode 100644 index 00000000000..b910a42e084 --- /dev/null +++ b/dts/upstream/Bindings/pci/cix,sky1-pcie-host.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 PCIe Root Complex + +maintainers: + - Hans Zhang + +description: + PCIe root complex controller based on the Cadence PCIe core. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + const: cix,sky1-pcie-host + + reg: + items: + - description: PCIe controller registers. + - description: ECAM registers. + - description: Remote CIX System Unit strap registers. + - description: Remote CIX System Unit status registers. + - description: Region for sending messages registers. + + reg-names: + items: + - const: reg + - const: cfg + - const: rcsu_strap + - const: rcsu_status + - const: msg + + ranges: + maxItems: 3 + +required: + - compatible + - ranges + - bus-range + - device_type + - interrupt-map + - interrupt-map-mask + - msi-map + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@a010000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000300 0x00 0x100>, + <0x00 0x0a000400 0x00 0x100>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x00100000>, + <0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0xc0 0xff>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0xc000 &gic_its 0xc000 0x4000>; + }; + }; diff --git a/dts/upstream/Bindings/pci/faraday,ftpci100.yaml b/dts/upstream/Bindings/pci/faraday,ftpci100.yaml index 378dd1c8e2e..fed393a8956 100644 --- a/dts/upstream/Bindings/pci/faraday,ftpci100.yaml +++ b/dts/upstream/Bindings/pci/faraday,ftpci100.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FTPCI100 PCI Host Bridge maintainers: - - Linus Walleij + - Linus Walleij description: | This PCI bridge is found inside that Cortina Systems Gemini SoC platform and diff --git a/dts/upstream/Bindings/pci/intel,ixp4xx-pci.yaml b/dts/upstream/Bindings/pci/intel,ixp4xx-pci.yaml index 3cae2e0f7f5..c1806aef7ba 100644 --- a/dts/upstream/Bindings/pci/intel,ixp4xx-pci.yaml +++ b/dts/upstream/Bindings/pci/intel,ixp4xx-pci.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx PCI controller maintainers: - - Linus Walleij + - Linus Walleij description: PCI host controller found in the Intel IXP4xx SoC series. diff --git a/dts/upstream/Bindings/pci/loongson.yaml b/dts/upstream/Bindings/pci/loongson.yaml index 1988465e73a..e5bba63aa94 100644 --- a/dts/upstream/Bindings/pci/loongson.yaml +++ b/dts/upstream/Bindings/pci/loongson.yaml @@ -32,7 +32,6 @@ properties: minItems: 1 maxItems: 3 - required: - compatible - reg diff --git a/dts/upstream/Bindings/pci/mediatek-pcie-mt7623.yaml b/dts/upstream/Bindings/pci/mediatek-pcie-mt7623.yaml new file mode 100644 index 00000000000..e33bcc216e3 --- /dev/null +++ b/dts/upstream/Bindings/pci/mediatek-pcie-mt7623.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-mt7623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + enum: + - mediatek,mt2701-pcie + - mediatek,mt7623-pcie + + reg: + minItems: 4 + maxItems: 4 + + reg-names: + items: + - const: subsys + - const: port0 + - const: port1 + - const: port2 + + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: free_ck + - const: sys_ck0 + - const: sys_ck1 + - const: sys_ck2 + + resets: + minItems: 3 + maxItems: 3 + + reset-names: + items: + - const: pcie-rst0 + - const: pcie-rst1 + - const: pcie-rst2 + + phys: + minItems: 3 + maxItems: 3 + + phy-names: + items: + - const: pcie-phy0 + - const: pcie-phy1 + - const: pcie-phy2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - resets + - reset-names + - phys + - phy-names + - power-domains + - pcie@0,0 + - pcie@1,0 + - pcie@2,0 + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + # MT7623 + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ + <0 0x1a142000 0 0x1000>, /* Port0 registers */ + <0 0x1a143000 0 0x1000>, /* Port1 registers */ + <0 0x1a144000 0 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, + <&hifsys MT2701_HIFSYS_PCIE1_RST>, + <&hifsys MT2701_HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>, /* I/O space */ + <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ + + pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@1,0 { + device_type = "pci"; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@2,0 { + device_type = "pci"; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + }; + }; diff --git a/dts/upstream/Bindings/pci/mediatek-pcie.txt b/dts/upstream/Bindings/pci/mediatek-pcie.txt deleted file mode 100644 index 68422752226..00000000000 --- a/dts/upstream/Bindings/pci/mediatek-pcie.txt +++ /dev/null @@ -1,289 +0,0 @@ -MediaTek Gen2 PCIe controller - -Required properties: -- compatible: Should contain one of the following strings: - "mediatek,mt2701-pcie" - "mediatek,mt2712-pcie" - "mediatek,mt7622-pcie" - "mediatek,mt7623-pcie" - "mediatek,mt7629-pcie" - "airoha,en7523-pcie" -- device_type: Must be "pci" -- reg: Base addresses and lengths of the root ports. -- reg-names: Names of the above areas to use during resource lookup. -- #address-cells: Address representation for root ports (must be 3) -- #size-cells: Size representation for root ports (must be 2) -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: - Mandatory entries: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys - Required entries for MT2712/MT7622: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access - Required entries for MT7622: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off - - obff_ckN :OBFF functional block operating clock - - pipe_ckN :LTSSM and PHY/MAC layer operating clock - where N starting from 0 to one less than the number of root ports. -- phys: List of PHY specifiers (used by generic PHY framework). -- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - number of PHYs as specified in *phys* property. -- power-domains: A phandle and power domain specifier pair to the power domain - which is responsible for collapsing and restoring power to the peripheral. -- bus-range: Range of bus numbers associated with this controller. -- ranges: Ranges for the PCI memory and I/O regions. - -Required properties for MT7623/MT2701: -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - -Required properties for MT2712/MT7622/MT7629: --interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port -- interrupt-names: Must include the following entries: - - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received -- linux,pci-domain: PCI domain ID. Should be unique for each host controller - -In addition, the device tree node must have sub-nodes describing each -PCIe port interface, having the following mandatory properties: - -Required properties: -- device_type: Must be "pci" -- reg: Only the first four bytes are used to refer to the correct bus number - and device number. -- #address-cells: Must be 3 -- #size-cells: Must be 2 -- #interrupt-cells: Must be 1 -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. -- ranges: Sub-ranges distributed from the PCIe controller node. An empty - property is sufficient. - -Examples for MT7623: - - hifsys: syscon@1a000000 { - compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7623-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ - <0 0x1a142000 0 0x1000>, /* Port0 registers */ - <0 0x1a143000 0 0x1000>, /* Port1 registers */ - <0 0x1a144000 0 0x1000>; /* Port2 registers */ - reg-names = "subsys", "port0", "port1", "port2"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 0>; - interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, - <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, - <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <&hifsys CLK_HIFSYS_PCIE0>, - <&hifsys CLK_HIFSYS_PCIE1>, - <&hifsys CLK_HIFSYS_PCIE2>; - clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; - resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>, - <&hifsys MT2701_HIFSYS_PCIE1_RST>, - <&hifsys MT2701_HIFSYS_PCIE2_RST>; - reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, - <&pcie2_phy PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */ - 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ - - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - - pcie@2,0 { - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; - ranges; - }; - }; - -Examples for MT2712: - - pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; - reg = <0 0x112ff000 0 0x1000>; - reg-names = "port1"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - interrupt-names = "pcie_irq"; - clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; - clock-names = "sys_ck1", "ahb_ck1"; - phys = <&u3port1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie0: pcie@11700000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; - reg = <0 0x11700000 0 0x1000>; - reg-names = "port0"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - interrupt-names = "pcie_irq"; - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&pericfg CLK_PERI_PCIE0>; - clock-names = "sys_ck0", "ahb_ck0"; - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy0"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - -Examples for MT7622: - - pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0 0x1a143000 0 0x1000>; - reg-names = "port0"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>; - clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", - "axi_ck0", "obff_ck0", "pipe_ck0"; - - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1a145000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0 0x1a145000 0 0x1000>; - reg-names = "port1"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - /* designer has connect RC1 with p0_ahb clock */ - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", - "axi_ck1", "obff_ck1", "pipe_ck1"; - - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; diff --git a/dts/upstream/Bindings/pci/mediatek-pcie.yaml b/dts/upstream/Bindings/pci/mediatek-pcie.yaml new file mode 100644 index 00000000000..0b8c78ec4f9 --- /dev/null +++ b/dts/upstream/Bindings/pci/mediatek-pcie.yaml @@ -0,0 +1,438 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe controller on MediaTek SoCs + +maintainers: + - Christian Marangi + +properties: + compatible: + oneOf: + - enum: + - airoha,an7583-pcie + - mediatek,mt2712-pcie + - mediatek,mt7622-pcie + - mediatek,mt7629-pcie + - items: + - const: airoha,en7523-pcie + - const: mediatek,mt7622-pcie + + reg: + maxItems: 1 + + reg-names: + enum: [ port0, port1 ] + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + items: + - enum: [ sys_ck0, sys_ck1 ] + - enum: [ ahb_ck0, ahb_ck1 ] + - enum: [ aux_ck0, aux_ck1 ] + - enum: [ axi_ck0, axi_ck1 ] + - enum: [ obff_ck0, obff_ck1 ] + - enum: [ pipe_ck0, pipe_ck1 ] + + resets: + maxItems: 1 + + reset-names: + const: pcie-rst1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: pcie_irq + + phys: + maxItems: 1 + + phy-names: + enum: [ pcie-phy0, pcie-phy1 ] + + power-domains: + maxItems: 1 + + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupts + - interrupt-names + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + + - if: + properties: + compatible: + const: airoha,an7583-pcie + then: + properties: + reg-names: + const: port1 + + clocks: + maxItems: 1 + + clock-names: + const: sys_ck1 + + phy-names: + const: pcie-phy1 + + power-domain: false + + required: + - resets + - reset-names + - phys + - phy-names + - mediatek,pbus-csr + + - if: + properties: + compatible: + const: mediatek,mt2712-pcie + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + minItems: 2 + maxItems: 2 + + reset: false + + reset-names: false + + power-domains: false + + mediatek,pbus-csr: false + + required: + - phys + - phy-names + + - if: + properties: + compatible: + const: mediatek,mt7622-pcie + then: + properties: + clocks: + minItems: 6 + + reset: false + + reset-names: false + + phys: false + + phy-names: false + + mediatek,pbus-csr: false + + required: + - power-domains + + - if: + properties: + compatible: + const: mediatek,mt7629-pcie + then: + properties: + clocks: + minItems: 6 + + reset: false + + reset-names: false + + mediatek,pbus-csr: false + + required: + - power-domains + + - if: + properties: + compatible: + contains: + const: airoha,en7523-pcie + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + reset: false + + reset-names: false + + phys: false + + phy-names: false + + power-domain: false + + mediatek,pbus-csr: false + +unevaluatedProperties: false + +examples: + # MT2712 + - | + #include + #include + #include + + soc_1 { + #address-cells = <2>; + #size-cells = <2>; + + pcie@112ff000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x112ff000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ + <&pericfg>; /* CLK_PERI_PCIE1 */ + clock-names = "sys_ck1", "ahb_ck1"; + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie@11700000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x11700000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ + <&pericfg>; /* CLK_PERI_PCIE0 */ + clock-names = "sys_ck0", "ahb_ck0"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + # MT7622 + - | + #include + #include + #include + + soc_2 { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1a143000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0 0x1a143000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", + "axi_ck0", "obff_ck0", "pipe_ck0"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0_1 0>, + <0 0 0 2 &pcie_intc0_1 1>, + <0 0 0 3 &pcie_intc0_1 2>, + <0 0 0 4 &pcie_intc0_1 3>; + pcie_intc0_1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie@1a145000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0 0x1a145000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ + /* designer has connect RC1 with p0_ahb clock */ + <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ + <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ + <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ + <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ + <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", + "axi_ck1", "obff_ck1", "pipe_ck1"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1_1 0>, + <0 0 0 2 &pcie_intc1_1 1>, + <0 0 0 3 &pcie_intc1_1 2>, + <0 0 0 4 &pcie_intc1_1 3>; + pcie_intc1_1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + # AN7583 + - | + #include + #include + #include + + soc_3 { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1fa92000 { + compatible = "airoha,an7583-pcie"; + device_type = "pci"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + + reg = <0x0 0x1fa92000 0x0 0x1670>; + reg-names = "port1"; + + clocks = <&scuclk EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + + phys = <&pciephy>; + phy-names = "pcie-phy1"; + + ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>; + + resets = <&scuclk>; /* AN7583_PCIE1_RST */ + reset-names = "pcie-rst1"; + + mediatek,pbus-csr = <&pbus_csr 0x8 0xc>; + + interrupts = ; + interrupt-names = "pcie_irq"; + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1_4: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; diff --git a/dts/upstream/Bindings/pci/nxp,s32g-pcie.yaml b/dts/upstream/Bindings/pci/nxp,s32g-pcie.yaml new file mode 100644 index 00000000000..66a05002827 --- /dev/null +++ b/dts/upstream/Bindings/pci/nxp,s32g-pcie.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller + +maintainers: + - Bogdan Hamciuc + - Ionut Vicovan + +description: + This PCIe controller is based on the Synopsys DesignWare PCIe IP. + The S32G SoC family has two PCIe controllers, which can be configured as + either Root Complex or Endpoint. + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-pcie + - items: + - const: nxp,s32g3-pcie + - const: nxp,s32g2-pcie + + reg: + maxItems: 6 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: ctrl + - const: config + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: msi + - const: dma + minItems: 1 + + pcie@0: + description: + Describe the S32G Root Port. + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + required: + - reg + - phys + + unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - ranges + - pcie@0 + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@40400000 { + compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie"; + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */ + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */ + <0x00 0x40460000 0x0 0x00001000>, /* atu registers */ + <0x00 0x40470000 0x0 0x00001000>, /* dma registers */ + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */ + <0x5f 0xffffe000 0x0 0x00002000>; /* config space */ + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config"; + dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = + <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>, + <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>, + <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>; + + bus-range = <0x0 0xff>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + device_type = "pci"; + phys = <&serdes0 PHY_TYPE_PCIE 0 0>; + }; + }; + }; diff --git a/dts/upstream/Bindings/pci/pci-ep.yaml b/dts/upstream/Bindings/pci/pci-ep.yaml index 1868a10d5b1..baeb583e0bc 100644 --- a/dts/upstream/Bindings/pci/pci-ep.yaml +++ b/dts/upstream/Bindings/pci/pci-ep.yaml @@ -11,7 +11,7 @@ description: | maintainers: - Kishon Vijay Abraham I - - Manivannan Sadhasivam + - Manivannan Sadhasivam properties: $nodename: diff --git a/dts/upstream/Bindings/pci/plda,xpressrich3-axi-common.yaml b/dts/upstream/Bindings/pci/plda,xpressrich3-axi-common.yaml index 039eecdbd6a..fe2e8beb5ba 100644 --- a/dts/upstream/Bindings/pci/plda,xpressrich3-axi-common.yaml +++ b/dts/upstream/Bindings/pci/plda,xpressrich3-axi-common.yaml @@ -72,7 +72,7 @@ required: - reg-names - interrupts - msi-controller - - "#interrupt-cells" + - '#interrupt-cells' - interrupt-map-mask - interrupt-map diff --git a/dts/upstream/Bindings/pci/qcom,pcie-common.yaml b/dts/upstream/Bindings/pci/qcom,pcie-common.yaml index ab2509ec1c4..77f8faf5473 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-common.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-common.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI Express Root Complex Common Properties maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam properties: reg: diff --git a/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml b/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml index ac3414203d3..bed9a40b186 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PCIe Endpoint Controller maintainers: - - Manivannan Sadhasivam + - Manivannan Sadhasivam properties: compatible: diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sa8255p.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sa8255p.yaml index bdddd4f499d..1f2d098b863 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sa8255p.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sa8255p.yaml @@ -8,7 +8,7 @@ title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Comp maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sa8775p.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sa8775p.yaml index 19afe2a0340..63630a814f2 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sa8775p.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sa8775p.yaml @@ -8,7 +8,7 @@ title: Qualcomm SA8775p PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys @@ -78,6 +78,9 @@ properties: required: - interconnects - interconnect-names + - power-domains + - resets + - reset-names allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sc7280.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sc7280.yaml index 4d0a9155660..1f942b3075f 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sc7280.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sc7280.yaml @@ -8,7 +8,7 @@ title: Qualcomm SC7280 PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys @@ -76,6 +76,11 @@ properties: items: - const: pci +required: + - power-domains + - resets + - reset-names + allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sc8180x.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sc8180x.yaml index 34a4d7b2c84..6a7c410c9fc 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sc8180x.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sc8180x.yaml @@ -8,7 +8,7 @@ title: Qualcomm SC8180x PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sc8280xp.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sc8280xp.yaml index 15ba2385eb7..bc0e71dc06a 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sc8280xp.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sc8280xp.yaml @@ -8,7 +8,7 @@ title: Qualcomm SC8280XP PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys @@ -61,6 +61,9 @@ properties: required: - interconnects - interconnect-names + - power-domains + - resets + - reset-names allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8150.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8150.yaml index 26b247a4178..6a5421e4f19 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sm8150.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8150.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8150 PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys @@ -74,6 +74,11 @@ properties: items: - const: pci +required: + - power-domains + - resets + - reset-names + allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8250.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8250.yaml index af4dae68d50..adbeaa8f2c1 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sm8250.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8250.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8250 PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys @@ -83,6 +83,11 @@ properties: items: - const: pci +required: + - power-domains + - resets + - reset-names + allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8350.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8350.yaml index dde3079adbb..5744d5e969f 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sm8350.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8350.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8350 PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys @@ -73,6 +73,11 @@ properties: items: - const: pci +required: + - power-domains + - resets + - reset-names + allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml index 6e0a6d8f0ed..28b8ffb7412 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8450 PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys @@ -77,6 +77,11 @@ properties: items: - const: pci +required: + - power-domains + - resets + - reset-names + allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml index 38b561e23c1..3a94a9c1bb1 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8550 PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sm8550 - items: - enum: + - qcom,kaanapali-pcie - qcom,sar2130p-pcie - qcom,pcie-sm8650 - qcom,pcie-sm8750 @@ -83,6 +84,11 @@ properties: - const: pci # PCIe core reset - const: link_down # PCIe link down reset +required: + - power-domains + - resets + - reset-names + allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml b/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml index 61581ffbfb2..62c674ca0cf 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml @@ -8,7 +8,7 @@ title: Qualcomm X1E80100 PCI Express Root Complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on @@ -73,6 +73,11 @@ properties: - const: pci # PCIe core reset - const: link_down # PCIe link down reset +required: + - power-domains + - resets + - reset-names + allOf: - $ref: qcom,pcie-common.yaml# diff --git a/dts/upstream/Bindings/pci/qcom,pcie.yaml b/dts/upstream/Bindings/pci/qcom,pcie.yaml index 0e1808105a8..c61930441be 100644 --- a/dts/upstream/Bindings/pci/qcom,pcie.yaml +++ b/dts/upstream/Bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex maintainers: - Bjorn Andersson - - Manivannan Sadhasivam + - Manivannan Sadhasivam description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare diff --git a/dts/upstream/Bindings/pci/renesas,r9a08g045-pcie.yaml b/dts/upstream/Bindings/pci/renesas,r9a08g045-pcie.yaml new file mode 100644 index 00000000000..d668782546a --- /dev/null +++ b/dts/upstream/Bindings/pci/renesas,r9a08g045-pcie.yaml @@ -0,0 +1,249 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S PCIe host controller + +maintainers: + - Claudiu Beznea + +description: + Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification + 4.0 and supports up to 5 GT/s (Gen2). + +properties: + compatible: + const: renesas,r9a08g045-pcie # RZ/G3S + + reg: + maxItems: 1 + + interrupts: + items: + - description: System error interrupt + - description: System error on correctable error interrupt + - description: System error on non-fatal error interrupt + - description: System error on fatal error interrupt + - description: AXI error interrupt + - description: INTA interrupt + - description: INTB interrupt + - description: INTC interrupt + - description: INTD interrupt + - description: MSI interrupt + - description: Link bandwidth interrupt + - description: PME interrupt + - description: DMA interrupt + - description: PCIe event interrupt + - description: Message interrupt + - description: All interrupts + + interrupt-names: + items: + - description: serr + - description: ser_cor + - description: serr_nonfatal + - description: serr_fatal + - description: axi_err + - description: inta + - description: intb + - description: intc + - description: intd + - description: msi + - description: link_bandwidth + - description: pm_pme + - description: dma + - description: pcie_evt + - description: msg + - description: all + + interrupt-controller: true + + clocks: + items: + - description: System clock + - description: PM control clock + + clock-names: + items: + - description: aclk + - description: pm + + resets: + items: + - description: AXI2PCIe Bridge reset + - description: Data link layer/transaction layer reset + - description: Transaction layer (ACLK domain) reset + - description: Transaction layer (PCLK domain) reset + - description: Physical layer reset + - description: Configuration register reset + - description: Configuration register reset + + reset-names: + items: + - description: aresetn + - description: rst_b + - description: rst_gp_b + - description: rst_ps_b + - description: rst_rsm_b + - description: rst_cfg_b + - description: rst_load_b + + power-domains: + maxItems: 1 + + dma-ranges: + description: + A single range for the inbound memory region. + maxItems: 1 + + renesas,sysc: + description: | + System controller registers control and monitor various PCIe + functionalities. + + Control: + - transition to L1 state + - receiver termination settings + - RST_RSM_B signal + + Monitor: + - clkl1pm clock request state + - power off information in L2 state + - errors (fatal, non-fatal, correctable) + $ref: /schemas/types.yaml#/definitions/phandle + +patternProperties: + "^pcie@0,[0-0]$": + type: object + allOf: + - $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + vendor-id: + const: 0x1912 + + device-id: + const: 0x0033 + + clocks: + items: + - description: Reference clock + + clock-names: + items: + - const: ref + + required: + - device_type + - vendor-id + - device-id + - clocks + - clock-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-names + - interrupt-map + - interrupt-map-mask + - interrupt-controller + - power-domains + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - renesas,sysc + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@11e40000 { + compatible = "renesas,r9a08g045-pcie"; + reg = <0 0x11e40000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names = "aclk", "pm"; + resets = <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + renesas,sysc = <&sysc>; + + pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + clocks = <&versa3 5>; + clock-names = "ref"; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x0033>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + }; + +... diff --git a/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml b/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml index 6c6d828ce96..355c4a46bd3 100644 --- a/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml +++ b/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml @@ -22,6 +22,7 @@ properties: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3528-pcie - rockchip,rk3562-pcie - rockchip,rk3576-pcie - rockchip,rk3588-pcie @@ -78,6 +79,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-pcie - rockchip,rk3562-pcie - rockchip,rk3576-pcie then: @@ -89,6 +91,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-pcie - rockchip,rk3562-pcie - rockchip,rk3576-pcie then: @@ -121,7 +124,6 @@ allOf: - const: dma2 - const: dma3 - unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/pci/snps,dw-pcie-common.yaml b/dts/upstream/Bindings/pci/snps,dw-pcie-common.yaml index 34594972d8d..6339a76499b 100644 --- a/dts/upstream/Bindings/pci/snps,dw-pcie-common.yaml +++ b/dts/upstream/Bindings/pci/snps,dw-pcie-common.yaml @@ -115,11 +115,11 @@ properties: above for new bindings. oneOf: - description: See native 'dbi' clock for details - enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ] + enum: [ pcie, pcie_apb_sys, aclk_dbi, reg, port ] - description: See native 'mstr/slv' clock for details enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ] - description: See native 'pipe' clock for details - enum: [ pcie_phy, pcie_phy_ref, link ] + enum: [ pcie_phy, pcie_phy_ref, link, general ] - description: See native 'aux' clock for details enum: [ pcie_aux ] - description: See native 'ref' clock for details. @@ -176,7 +176,7 @@ properties: - description: See native 'phy' reset for details enum: [ pciephy, link ] - description: See native 'pwr' reset for details - enum: [ turnoff ] + enum: [ turnoff, port ] phys: description: diff --git a/dts/upstream/Bindings/pci/spacemit,k1-pcie-host.yaml b/dts/upstream/Bindings/pci/spacemit,k1-pcie-host.yaml new file mode 100644 index 00000000000..c4c00b5fcdc --- /dev/null +++ b/dts/upstream/Bindings/pci/spacemit,k1-pcie-host.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PCI Express Host Controller + +maintainers: + - Alex Elder + +description: > + The SpacemiT K1 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP. The controller uses the DesignWare built-in MSI interrupt + controller, and supports 256 MSIs. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: spacemit,k1-pcie + + reg: + items: + - description: DesignWare PCIe registers + - description: ATU address space + - description: PCIe configuration space + - description: Link control registers + + reg-names: + items: + - const: dbi + - const: atu + - const: config + - const: link + + clocks: + items: + - description: DWC PCIe Data Bus Interface (DBI) clock + - description: DWC PCIe application AXI-bus master interface clock + - description: DWC PCIe application AXI-bus slave interface clock + + clock-names: + items: + - const: dbi + - const: mstr + - const: slv + + resets: + items: + - description: DWC PCIe Data Bus Interface (DBI) reset + - description: DWC PCIe application AXI-bus master interface reset + - description: DWC PCIe application AXI-bus slave interface reset + + reset-names: + items: + - const: dbi + - const: mstr + - const: slv + + interrupts: + items: + - description: Interrupt used for MSIs + + interrupt-names: + const: msi + + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle that refers to the APMU system controller, whose regmap is + used in managing resets and link state, along with and offset of its + reset control register. + items: + - items: + - description: phandle to APMU system controller + - description: register offset + +patternProperties: + '^pcie@': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + phys: + maxItems: 1 + + vpcie3v3-supply: + description: + A phandle for 3.3v regulator to use for PCIe + + required: + - phys + - vpcie3v3-supply + + unevaluatedProperties: false + +required: + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-names + - spacemit,apmu + +unevaluatedProperties: false + +examples: + - | + #include + pcie@ca400000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0xca400000 0x00001000>, + <0xca700000 0x0001ff24>, + <0x9f000000 0x00002000>, + <0xc0c20000 0x00001000>; + reg-names = "dbi", + "atu", + "config", + "link"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x90000000 0x0 0x0f000000>; + interrupts = <142>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names = "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>; + reset-names = "dbi", + "mstr", + "slv"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + spacemit,apmu = <&syscon_apmu 0x3d4>; + + pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; + }; + }; diff --git a/dts/upstream/Bindings/pci/starfive,jh7110-pcie.yaml b/dts/upstream/Bindings/pci/starfive,jh7110-pcie.yaml index 5f432452c81..33c80626e8e 100644 --- a/dts/upstream/Bindings/pci/starfive,jh7110-pcie.yaml +++ b/dts/upstream/Bindings/pci/starfive,jh7110-pcie.yaml @@ -16,7 +16,6 @@ properties: compatible: const: starfive,jh7110-pcie - reg: maxItems: 2 diff --git a/dts/upstream/Bindings/pci/toshiba,tc9563.yaml b/dts/upstream/Bindings/pci/toshiba,tc9563.yaml new file mode 100644 index 00000000000..fae46606478 --- /dev/null +++ b/dts/upstream/Bindings/pci/toshiba,tc9563.yaml @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/toshiba,tc9563.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9563 PCIe switch + +maintainers: + - Krishna Chaitanya Chundru + +description: | + Toshiba TC9563 PCIe switch has one upstream and three downstream ports. + The 3rd downstream port has integrated endpoint device of Ethernet MAC. + Other two downstream ports are supposed to connect to external device. + + The TC9563 PCIe switch can be configured through I2C interface before + PCIe link is established to change FTS, ASPM related entry delays, + tx amplitude etc for better power efficiency and functionality. + +properties: + compatible: + enum: + - pci1179,0623 + + reg: + maxItems: 1 + + resx-gpios: + maxItems: 1 + description: + GPIO controlling the RESX# pin. + + vdd18-supply: true + + vdd09-supply: true + + vddc-supply: true + + vddio1-supply: true + + vddio2-supply: true + + vddio18-supply: true + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle to the parent I2C node and the slave address of the device + used to configure tc9563 to change FTS, tx amplitude etc. + items: + - description: Phandle to the I2C controller node + - description: I2C slave address + +patternProperties: + "^pcie@[1-3],0$": + description: + child nodes describing the internal downstream ports of + the tc9563 switch. + type: object + allOf: + - $ref: "#/$defs/tc9563-node" + - $ref: /schemas/pci/pci-pci-bridge.yaml# + unevaluatedProperties: false + +$defs: + tc9563-node: + type: object + + properties: + toshiba,tx-amplitude-microvolt: + description: + Change Tx Margin setting for low power consumption. + + toshiba,no-dfe-support: + type: boolean + description: + Disable DFE (Decision Feedback Equalizer), which mitigates + intersymbol interference and some reflections caused by + impedance mismatches. + +required: + - resx-gpios + - vdd18-supply + - vdd09-supply + - vddc-supply + - vddio1-supply + - vddio2-supply + - vddio18-supply + - i2c-parent + +allOf: + - $ref: "#/$defs/tc9563-node" + - $ref: /schemas/pci/pci-bus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + pcie { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + bus-range = <0x01 0xff>; + + pcie@0,0 { + compatible = "pci1179,0623"; + + reg = <0x10000 0x0 0x0 0x0 0x0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + bus-range = <0x02 0xff>; + + i2c-parent = <&qup_i2c 0x77>; + + vdd18-supply = <&vdd>; + vdd09-supply = <&vdd>; + vddc-supply = <&vdd>; + vddio1-supply = <&vdd>; + vddio2-supply = <&vdd>; + vddio18-supply = <&vdd>; + + resx-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + compatible = "pciclass,0604"; + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x03 0xff>; + + toshiba,no-dfe-support; + }; + + pcie@2,0 { + compatible = "pciclass,0604"; + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x04 0xff>; + }; + + pcie@3,0 { + compatible = "pciclass,0604"; + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x05 0xff>; + + toshiba,tx-amplitude-microvolt = <10>; + + ethernet@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + }; + + ethernet@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + }; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/pci/v3,v360epc-pci.yaml b/dts/upstream/Bindings/pci/v3,v360epc-pci.yaml index 38cac88f17b..0e2ac2f8fae 100644 --- a/dts/upstream/Bindings/pci/v3,v360epc-pci.yaml +++ b/dts/upstream/Bindings/pci/v3,v360epc-pci.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: V3 Semiconductor V360 EPC PCI bridge maintainers: - - Linus Walleij + - Linus Walleij description: This bridge is found in the ARM Integrator/AP (Application Platform) diff --git a/dts/upstream/Bindings/pci/versatile.yaml b/dts/upstream/Bindings/pci/versatile.yaml index 294c7cd84b3..d30b8849db9 100644 --- a/dts/upstream/Bindings/pci/versatile.yaml +++ b/dts/upstream/Bindings/pci/versatile.yaml @@ -90,5 +90,4 @@ examples: <0x0000 0 0 4 &sic 28>; }; - ... diff --git a/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml b/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml index d2e578d6b83..103e4aec243 100644 --- a/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml +++ b/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - fsl,imx8-ddr-pmu + - fsl,imx8dxl-db-pmu - fsl,imx8m-ddr-pmu - fsl,imx8mq-ddr-pmu - fsl,imx8mm-ddr-pmu @@ -28,7 +29,10 @@ properties: - fsl,imx8mp-ddr-pmu - const: fsl,imx8m-ddr-pmu - items: - - const: fsl,imx8dxl-ddr-pmu + - enum: + - fsl,imx8dxl-ddr-pmu + - fsl,imx8qm-ddr-pmu + - fsl,imx8qxp-ddr-pmu - const: fsl,imx8-ddr-pmu - items: - enum: @@ -43,6 +47,14 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: cnt + required: - compatible - reg @@ -50,6 +62,21 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8dxl-db-pmu + then: + required: + - clocks + - clock-names + else: + properties: + clocks: false + clock-names: false + examples: - | #include diff --git a/dts/upstream/Bindings/phy/fsl,imx8mq-usb-phy.yaml b/dts/upstream/Bindings/phy/fsl,imx8mq-usb-phy.yaml index f9cffbb2df0..8a00a6c58ed 100644 --- a/dts/upstream/Bindings/phy/fsl,imx8mq-usb-phy.yaml +++ b/dts/upstream/Bindings/phy/fsl,imx8mq-usb-phy.yaml @@ -27,11 +27,16 @@ properties: const: 0 clocks: - maxItems: 1 + minItems: 1 + items: + - description: PHY configuration clock + - description: Alternate PHY reference clock clock-names: + minItems: 1 items: - const: phy + - const: alt power-domains: maxItems: 1 diff --git a/dts/upstream/Bindings/phy/mediatek,tphy.yaml b/dts/upstream/Bindings/phy/mediatek,tphy.yaml index b2218c15193..ff5c77ef117 100644 --- a/dts/upstream/Bindings/phy/mediatek,tphy.yaml +++ b/dts/upstream/Bindings/phy/mediatek,tphy.yaml @@ -80,6 +80,7 @@ properties: - mediatek,mt2712-tphy - mediatek,mt6893-tphy - mediatek,mt7629-tphy + - mediatek,mt7981-tphy - mediatek,mt7986-tphy - mediatek,mt8183-tphy - mediatek,mt8186-tphy diff --git a/dts/upstream/Bindings/phy/mediatek,ufs-phy.yaml b/dts/upstream/Bindings/phy/mediatek,ufs-phy.yaml index 3e62b5d4da6..6e2edd43fc2 100644 --- a/dts/upstream/Bindings/phy/mediatek,ufs-phy.yaml +++ b/dts/upstream/Bindings/phy/mediatek,ufs-phy.yaml @@ -8,8 +8,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek Universal Flash Storage (UFS) M-PHY maintainers: - - Stanley Chu - Chunfeng Yun + - Peter Wang + - Chaotian Jing description: | UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro. diff --git a/dts/upstream/Bindings/phy/motorola,cpcap-usb-phy.yaml b/dts/upstream/Bindings/phy/motorola,cpcap-usb-phy.yaml index 0febd04a61f..dd345cbd0a0 100644 --- a/dts/upstream/Bindings/phy/motorola,cpcap-usb-phy.yaml +++ b/dts/upstream/Bindings/phy/motorola,cpcap-usb-phy.yaml @@ -67,8 +67,8 @@ properties: mode-gpios: description: Optional GPIOs for configuring alternate modes items: - - description: "mode selection GPIO #0" - - description: "mode selection GPIO #1" + - description: mode selection GPIO#0 + - description: mode selection GPIO#1 required: - compatible diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 119b4ff36db..f5068df20cf 100644 --- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,glymur-qmp-gen5x4-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy @@ -55,7 +56,7 @@ properties: clocks: minItems: 5 - maxItems: 7 + maxItems: 6 clock-names: minItems: 5 @@ -66,7 +67,6 @@ properties: - enum: [rchng, refgen] - const: pipe - const: pipediv2 - - const: phy_aux power-domains: maxItems: 1 @@ -178,6 +178,8 @@ allOf: compatible: contains: enum: + - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy @@ -200,30 +202,26 @@ allOf: compatible: contains: enum: - - qcom,qcs8300-qmp-gen4x2-pcie-phy - then: - properties: - clocks: - minItems: 7 - clock-names: - minItems: 7 - - - if: - properties: - compatible: - contains: - enum: + - qcom,glymur-qmp-gen5x4-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy - qcom,x1e80100-qmp-gen4x8-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy then: properties: resets: minItems: 2 reset-names: minItems: 2 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 - if: properties: diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index a1b55168e05..863a1a44673 100644 --- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -35,7 +35,6 @@ properties: - qcom,sm8350-qmp-usb3-uni-phy - qcom,x1e80100-qmp-usb3-uni-phy - reg: maxItems: 1 diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index c8bc512df08..e0ec45b96bf 100644 --- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -78,10 +78,77 @@ properties: ports: $ref: /schemas/graph.yaml#/properties/ports + properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base description: Output endpoint of the PHY + unevaluatedProperties: false + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + endpoint@0: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: Display Port Output lanes of the PHY when used with static mapping, + The entry index is the DP lanes index, and the number is the PHY + signal in the order RX0, TX0, TX1, RX1. + unevaluatedProperties: false + + properties: + # Static lane mappings are mutually exclusive with typec-mux/orientation-mux + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 4 + oneOf: + - items: # DisplayPort 1 lane, normal orientation + - const: 3 + - items: # DisplayPort 1 lane, flipped orientation + - const: 0 + - items: # DisplayPort 2 lanes, normal orientation + - const: 3 + - const: 2 + - items: # DisplayPort 2 lanes, flipped orientation + - const: 0 + - const: 1 + - items: # DisplayPort 4 lanes, normal orientation + - const: 3 + - const: 2 + - const: 1 + - const: 0 + - items: # DisplayPort 4 lanes, flipped orientation + - const: 0 + - const: 1 + - const: 2 + - const: 3 + required: + - data-lanes + + endpoint@1: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: USB Output lanes of the PHY when used with static mapping. + The entry index is the USB3 lane in the order TX then RX, and the + number is the PHY signal in the order RX0, TX0, TX1, RX1. + unevaluatedProperties: false + + properties: + # Static lane mappings are mutually exclusive with typec-mux/orientation-mux + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + oneOf: + - items: # USB3, normal orientation + - const: 1 + - const: 0 + - items: # USB3, flipped orientation + - const: 2 + - const: 3 + + required: + - data-lanes port@1: $ref: /schemas/graph.yaml#/properties/port diff --git a/dts/upstream/Bindings/phy/renesas,rzg3e-usb3-phy.yaml b/dts/upstream/Bindings/phy/renesas,rzg3e-usb3-phy.yaml new file mode 100644 index 00000000000..b86dc7a291a --- /dev/null +++ b/dts/upstream/Bindings/phy/renesas,rzg3e-usb3-phy.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E USB 3.0 PHY + +maintainers: + - Biju Das + +properties: + compatible: + const: renesas,r9a09g047-usb3-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: APB bus clock + - description: USB 2.0 PHY reference clock + - description: USB 3.0 PHY reference clock + + clock-names: + items: + - const: pclk + - const: core + - const: ref_alt_clk_p + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - resets + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + + usb-phy@15870000 { + compatible = "renesas,r9a09g047-usb3-phy"; + reg = <0x15870000 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + }; diff --git a/dts/upstream/Bindings/phy/renesas,usb2-phy.yaml b/dts/upstream/Bindings/phy/renesas,usb2-phy.yaml index 179cb4bfc42..2bbec8702a1 100644 --- a/dts/upstream/Bindings/phy/renesas,usb2-phy.yaml +++ b/dts/upstream/Bindings/phy/renesas,usb2-phy.yaml @@ -118,6 +118,7 @@ allOf: contains: enum: - renesas,usb2-phy-r9a09g057 + - renesas,usb2-phy-r9a08g045 - renesas,rzg2l-usb2-phy then: properties: diff --git a/dts/upstream/Bindings/phy/rockchip,px30-dsi-dphy.yaml b/dts/upstream/Bindings/phy/rockchip,px30-dsi-dphy.yaml index 46e64fa293d..83e7c825860 100644 --- a/dts/upstream/Bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/dts/upstream/Bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -18,6 +18,7 @@ properties: - rockchip,px30-dsi-dphy - rockchip,rk3128-dsi-dphy - rockchip,rk3368-dsi-dphy + - rockchip,rk3506-dsi-dphy - rockchip,rk3568-dsi-dphy - rockchip,rv1126-dsi-dphy diff --git a/dts/upstream/Bindings/phy/ti,tcan104x-can.yaml b/dts/upstream/Bindings/phy/ti,tcan104x-can.yaml index 138923ffedf..c686d06f5f5 100644 --- a/dts/upstream/Bindings/phy/ti,tcan104x-can.yaml +++ b/dts/upstream/Bindings/phy/ti,tcan104x-can.yaml @@ -23,15 +23,25 @@ properties: - enum: - ti,tcan1042 - ti,tcan1043 + - nxp,tja1048 + - nxp,tja1051 + - nxp,tja1057 - nxp,tjr1443 '#phy-cells': - const: 0 + enum: [0, 1] + + silent-gpios: + description: + gpio node to toggle silent signal on transceiver + maxItems: 1 standby-gpios: description: - gpio node to toggle standby signal on transceiver - maxItems: 1 + gpio node to toggle standby signal on transceiver. For two Items, item 1 + is for stbn1, item 2 is for stbn2. + minItems: 1 + maxItems: 2 enable-gpios: description: @@ -54,6 +64,59 @@ required: - compatible - '#phy-cells' +allOf: + - if: + properties: + compatible: + enum: + - nxp,tjr1443 + - ti,tcan1042 + - ti,tcan1043 + then: + properties: + '#phy-cells': + const: 0 + silent-gpios: false + standby-gpios: + maxItems: 1 + + - if: + properties: + compatible: + contains: + const: nxp,tja1048 + then: + properties: + '#phy-cells': + const: 1 + enable-gpios: false + silent-gpios: false + standby-gpios: + minItems: 2 + + - if: + properties: + compatible: + contains: + const: nxp,tja1051 + then: + properties: + '#phy-cells': + const: 0 + standby-gpios: false + + - if: + properties: + compatible: + contains: + const: nxp,tja1057 + then: + properties: + '#phy-cells': + const: 0 + enable-gpios: false + standby-gpios: false + additionalProperties: false examples: diff --git a/dts/upstream/Bindings/pinctrl/actions,s700-pinctrl.txt b/dts/upstream/Bindings/pinctrl/actions,s700-pinctrl.txt deleted file mode 100644 index d13ff82f851..00000000000 --- a/dts/upstream/Bindings/pinctrl/actions,s700-pinctrl.txt +++ /dev/null @@ -1,170 +0,0 @@ -Actions Semi S700 Pin Controller - -This binding describes the pin controller found in the S700 SoC. - -Required Properties: - -- compatible: Should be "actions,s700-pinctrl" -- reg: Should contain the register base address and size of - the pin controller. -- clocks: phandle of the clock feeding the pin controller -- gpio-controller: Marks the device node as a GPIO controller. -- gpio-ranges: Specifies the mapping between gpio controller and - pin-controller pins. -- #gpio-cells: Should be two. The first cell is the gpio pin number - and the second cell is used for optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell - defines the interrupt number, the second encodes - the trigger flags described in - bindings/interrupt-controller/interrupts.txt -- interrupts: The interrupt outputs from the controller. There is one GPIO - interrupt per GPIO bank. The number of interrupts listed depends - on the number of GPIO banks on the SoC. The interrupts must be - ordered by bank, starting with bank 0. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -Pinmux functions are available only for the pin groups while pinconf -parameters are available for both pin groups and individual pins. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -Required Properties: - -- pins: An array of strings, each string containing the name of a pin. - These pins are used for selecting the pull control and schmitt - trigger parameters. The following are the list of pins - available: - - eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, - eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, - eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, - i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, - pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, - ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, - lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, - lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, - lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, - lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, - dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, - sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, - sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, - uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, - uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, - i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, - csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3, - sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2, - dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb, - dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0, - dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2, - dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3 - -- groups: An array of strings, each string containing the name of a pin - group. These pin groups are used for selecting the pinmux - functions. - rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, - rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, - rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, - i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, - i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, - ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, - dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, - lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp, - dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp, - uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, - sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, - uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp, - i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp, - pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp, - nand_ceb2_mfp, nand_ceb3_mfp - - These pin groups are used for selecting the drive strength - parameters. - - sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, - rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, - smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, - pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, - dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv, - uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv, - sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv - -- function: An array of strings, each string containing the name of the - pinmux functions. These functions can only be selected by - the corresponding pin groups. The following are the list of - pinmux functions available: - - nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, - uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, - pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, - sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, - clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 - -Optional Properties: - -- bias-pull-down: No arguments. The specified pins should be configured as - pull down. -- bias-pull-up: No arguments. The specified pins should be configured as - pull up. -- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified - pins -- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified - pins -- drive-strength: Integer. Selects the drive strength for the specified - pins in mA. - Valid values are: - <2> - <4> - <8> - <12> - -Example: - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s700-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 136>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - ; - - uart3-default: uart3-default { - pinmux { - groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; - function = "uart3"; - }; - pinconf { - groups = "uart3_all_drv"; - drive-strength = <2>; - }; - }; - }; diff --git a/dts/upstream/Bindings/pinctrl/actions,s700-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/actions,s700-pinctrl.yaml new file mode 100644 index 00000000000..9597b983c33 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/actions,s700-pinctrl.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s700-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S700 Pin Controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: actions,s700-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-line-names: + maxItems: 136 + + gpio-ranges: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 5 + description: + The interrupt outputs from the controller. There is one GPIO interrupt per + GPIO bank. The interrupts must be ordered by bank, starting with + bank 0. + +additionalProperties: + type: object + description: Pin configuration subnode + additionalProperties: false + + properties: + pinmux: + description: Configure pin multiplexing. + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, + rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, + rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, + i2c1_dummy, i2c2_dummy, i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, + i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, + ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, + lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, + dsi_dnp1_cp_d2_mfp, dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, + dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, + uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, + pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, + dnand_acle_ce0_mfp, nand_ceb2_mfp, nand_ceb3_mfp + ] + + function: + items: + enum: [ + nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, pcm1, + pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, sd0, sd1, + sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, clko_25m, mipi_csi, + nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 + ] + + required: + - groups + - function + + pinconf: + description: Configure pin-specific parameters. + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, + rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, + pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, + dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, + spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, + i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, sens0_ckout_drv, + uart3_all_drv + ] + + pins: + items: + enum: [ + eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, + eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, + ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, + lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, + lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, + lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, + dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, + sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, + sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, uart2_rx, + uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, + uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, + i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, csi_cn, csi_cp, + csi_dn2, csi_dp2, csi_dn3, csi_dp3, sensor0_pclk, sensor0_ckout, + dnand_d0, dnand_d1, dnand_d2, dnand_d3, dnand_d4, dnand_d5, + dnand_d6, dnand_d7, dnand_wrb, dnand_rdb, dnand_rdbn, dnand_dqs, + dnand_dqsn, dnand_rb0, dnand_ale, dnand_cle, dnand_ceb0, + dnand_ceb1, dnand_ceb2, dnand_ceb3, porb, clko_25m, bsel, pkg0, + pkg1, pkg2, pkg3 + ] + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + description: Selects the drive strength for the specified pins in mA. + enum: [2, 4, 8, 12] + + input-schmitt-enable: true + input-schmitt-disable: true + + oneOf: + - required: + - groups + - required: + - pins + + anyOf: + - required: [ pinmux ] + - required: [ pinconf ] + +required: + - compatible + - reg + - clocks + - gpio-controller + - gpio-ranges + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupts + +examples: + - | + #include + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s700-pinctrl"; + reg = <0xe01b0000 0x1000>; + clocks = <&cmu 1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 136>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + ; + + uart3-default { + pinmux { + groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; + function = "uart3"; + }; + pinconf { + groups = "uart3_all_drv"; + drive-strength = <2>; + }; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/actions,s900-pinctrl.txt b/dts/upstream/Bindings/pinctrl/actions,s900-pinctrl.txt deleted file mode 100644 index 81b58dddd3e..00000000000 --- a/dts/upstream/Bindings/pinctrl/actions,s900-pinctrl.txt +++ /dev/null @@ -1,204 +0,0 @@ -Actions Semi S900 Pin Controller - -This binding describes the pin controller found in the S900 SoC. - -Required Properties: - -- compatible: Should be "actions,s900-pinctrl" -- reg: Should contain the register base address and size of - the pin controller. -- clocks: phandle of the clock feeding the pin controller -- gpio-controller: Marks the device node as a GPIO controller. -- gpio-ranges: Specifies the mapping between gpio controller and - pin-controller pins. -- #gpio-cells: Should be two. The first cell is the gpio pin number - and the second cell is used for optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell - defines the interrupt number, the second encodes - the trigger flags described in - bindings/interrupt-controller/interrupts.txt -- interrupts: The interrupt outputs from the controller. There is one GPIO - interrupt per GPIO bank. The number of interrupts listed depends - on the number of GPIO banks on the SoC. The interrupts must be - ordered by bank, starting with bank 0. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -Pinmux functions are available only for the pin groups while pinconf -parameters are available for both pin groups and individual pins. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -Required Properties: - -- pins: An array of strings, each string containing the name of a pin. - These pins are used for selecting the pull control and schmitt - trigger parameters. The following are the list of pins - available: - - eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, - eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, - sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, - i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, - pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5, - eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, - lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, - lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, - lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, - lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, - sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, - sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, - spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, - uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, - uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx, - uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, - i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1, - csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3, - csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, - dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, - csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, - sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, - nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs, - nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1, - nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2, - nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs, - nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1, - nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3 - -- groups: An array of strings, each string containing the name of a pin - group. These pin groups are used for selecting the pinmux - functions. - - lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, - sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, - rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, - rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, - i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, - pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, - eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp, - eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp, - lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp, - spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, - uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, - sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp, - uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp, - csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp, - dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, - nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, - csi1_dn0_dp0_mfp, uart4_rx_tx_mfp - - - These pin groups are used for selecting the drive strength - parameters. - - sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, - rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv, - rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv, - sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv, - i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv, - lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, - sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, - spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, - uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv - - These pin groups are used for selecting the slew rate - parameters. - - sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, - rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, - rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, - i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, - pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, - spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, - uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, - sensor0_sr - -- function: An array of strings, each string containing the name of the - pinmux functions. These functions can only be selected by - the corresponding pin groups. The following are the list of - pinmux functions available: - - eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, - uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, - pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, - sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, - usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, - nand1, spdif, sirq0, sirq1, sirq2 - -Optional Properties: - -- bias-bus-hold: No arguments. The specified pins should retain the previous - state value. -- bias-high-impedance: No arguments. The specified pins should be configured - as high impedance. -- bias-pull-down: No arguments. The specified pins should be configured as - pull down. -- bias-pull-up: No arguments. The specified pins should be configured as - pull up. -- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified - pins -- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified - pins -- slew-rate: Integer. Sets slew rate for the specified pins. - Valid values are: - <0> - Slow - <1> - Fast -- drive-strength: Integer. Selects the drive strength for the specified - pins in mA. - Valid values are: - <2> - <4> - <8> - <12> - -Example: - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s900-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - ; - - uart2-default: uart2-default { - pinmux { - groups = "lvds_oep_odn_mfp"; - function = "uart2"; - }; - pinconf { - groups = "lvds_oep_odn_drv"; - drive-strength = <12>; - }; - }; - }; diff --git a/dts/upstream/Bindings/pinctrl/actions,s900-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/actions,s900-pinctrl.yaml new file mode 100644 index 00000000000..5c7b9f13226 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/actions,s900-pinctrl.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s900-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S900 Pin Controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: actions,s900-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 6 + description: The interrupt outputs from the controller. There is one GPIO + interrupt per GPIO bank. The number of interrupts listed depends on the + number of GPIO banks on the SoC. The interrupts must be ordered by bank, + starting with bank 0. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-line-names: + maxItems: 146 + + gpio-ranges: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - clocks + - gpio-controller + - gpio-ranges + - "#gpio-cells" + +additionalProperties: + type: object + description: Pin configuration subnode + additionalProperties: false + + properties: + pinmux: + type: object + description: Pin mux configuration + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, + sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, + rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, + rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, + i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, pcm1_clk_mfp, + pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, eram_a7_mfp, eram_a8_mfp, + eram_a9_mfp, eram_a10_mfp, eram_a11_mfp, lvds_oep_odn_mfp, + lvds_ocp_obn_mfp, lvds_oap_oan_mfp, lvds_e_mfp, + spi0_sclk_mosi_mfp, spi0_ss_mfp, spi0_miso_mfp, uart2_rtsb_mfp, + uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, + sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, + sd0_clk_mfp, sd1_cmd_clk_mfp, uart0_rx_mfp, nand0_d0_ceb3_mfp, + uart0_tx_mfp, i2c0_mfp, csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, + csi1_dn0_cp_mfp, dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, + nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, + csi1_dn0_dp0_mfp, uart4_rx_tx_mfp + ] + + function: + items: + enum: [ + eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, + sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, + usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, + nand1, spdif, sirq0, sirq1, sirq2 + ] + + required: + - groups + - function + + pinconf: + type: object + description: Pin configuration parameters + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + additionalProperties: false + + properties: + groups: + items: + enum: [ + # pin groups for drive strength + sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, rmii_tx_d0_d1_drv, + rmii_txen_rxer_drv, rmii_crs_dv_drv, rmii_rx_d1_d0_drv, + rmii_ref_clk_drv, rmii_mdc_mdio_drv, sirq_0_1_drv, sirq2_drv, + i2s_d0_d1_drv, i2s_lr_m_clk0_drv, i2s_blk1_mclk1_drv, + pcm1_in_out_drv, lvds_oap_oan_drv, lvds_oep_odn_drv, + lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, sd1_d3_d0_drv, + sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, spi0_ss_miso_drv, + uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, uart3_drv, i2c0_drv, + i2c1_drv, i2c2_drv, sensor0_drv, + # pin groups for slew rate + sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, + rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, + rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, + i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, + pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, + spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, + uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, + sensor0_sr + ] + + pins: + items: + enum: [ + eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, eth_rxd1, + eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, sirq0, sirq1, sirq2, + i2s_d0, i2s_bclk0, i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, + i2s_lrclk1, i2s_mclk1, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, + eram_a5, eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, + lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, lvds_ocn, + lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, lvds_een, + lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn, + lvds_eap, lvds_ean, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, + sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, uart0_tx, + uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, + uart3_rtsb, uart3_ctsb, uart4_rx, uart4_tx, i2c0_sclk, i2c0_sdata, + i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, + csi0_dn1, csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, + csi0_dn3, csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, + dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, + csi1_dn0, csi1_dp0, csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, + sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, nand0_d4, + nand0_d5, nand0_d6, nand0_d7, nand0_dqs, nand0_dqsn, nand0_ale, + nand0_cle, nand0_ceb0, nand0_ceb1, nand0_ceb2, nand0_ceb3, + nand1_d0, nand1_d1, nand1_d2, nand1_d3, nand1_d4, nand1_d5, + nand1_d6, nand1_d7, nand1_dqs, nand1_dqsn, nand1_ale, nand1_cle, + nand1_ceb0, nand1_ceb1, nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, + sgpio2, sgpio3 + ] + + bias-bus-hold: true + bias-high-impedance: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + input-schmitt-enable: true + input-schmitt-disable: true + slew-rate: true + drive-strength: true + + oneOf: + - required: + - groups + - required: + - pins + +examples: + - | + #include + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s900-pinctrl"; + reg = <0xe01b0000 0x1000>; + clocks = <&cmu 1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + ; + + uart2-default { + pinmux { + groups = "lvds_oep_odn_mfp"; + function = "uart2"; + }; + + pinconf { + groups = "lvds_oep_odn_drv"; + drive-strength = <12>; + }; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/airoha,an7583-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/airoha,an7583-pinctrl.yaml new file mode 100644 index 00000000000..79910214d9b --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -0,0 +1,402 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,an7583-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 Pin Controller + +maintainers: + - Lorenzo Bianconi + +description: + The Airoha's AN7583 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,an7583-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, + uart4, uart5] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc] + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, + spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, + gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, + gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, + pcie_reset0, pcie_reset1, pcie_reset2] + minItems: 1 + maxItems: 58 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + + pinctrl { + compatible = "airoha,an7583-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2", "uart2_cts_rts"; + }; + }; + + uar5-pins { + mux { + function = "uart"; + groups = "uart5"; + }; + }; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index 80974c46f3e..af8979af9b4 100644 --- a/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -141,6 +141,7 @@ additionalProperties: - NRTS3 - NRTS4 - OSCCLK + - PCIERC1 - PEWAKE - PWM0 - PWM1 @@ -369,6 +370,7 @@ additionalProperties: - NRTS3 - NRTS4 - OSCCLK + - PCIERC1 - PEWAKE - PWM0 - PWM1 diff --git a/dts/upstream/Bindings/pinctrl/berlin,pinctrl.txt b/dts/upstream/Bindings/pinctrl/berlin,pinctrl.txt deleted file mode 100644 index 0a2d5516e1f..00000000000 --- a/dts/upstream/Bindings/pinctrl/berlin,pinctrl.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Pin-controller driver for the Marvell Berlin SoCs - -Pin control registers are part of both chip controller and system -controller register sets. Pin controller nodes should be a sub-node of -either the chip controller or system controller node. The pins -controlled are organized in groups, so no actual pin information is -needed. - -A pin-controller node should contain subnodes representing the pin group -configurations, one per function. Each subnode has the group name and -the muxing function used. - -Be aware the Marvell Berlin datasheets use the keyword 'mode' for what -is called a 'function' in the pin-controller subsystem. - -Required properties: -- compatible: should be one of: - "marvell,berlin2-soc-pinctrl", - "marvell,berlin2-system-pinctrl", - "marvell,berlin2cd-soc-pinctrl", - "marvell,berlin2cd-system-pinctrl", - "marvell,berlin2q-soc-pinctrl", - "marvell,berlin2q-system-pinctrl", - "marvell,berlin4ct-avio-pinctrl", - "marvell,berlin4ct-soc-pinctrl", - "marvell,berlin4ct-system-pinctrl", - "syna,as370-soc-pinctrl" - -Required subnode-properties: -- groups: a list of strings describing the group names. -- function: a string describing the function used to mux the groups. - -Example: - -sys_pinctrl: pin-controller { - compatible = "marvell,berlin2q-system-pinctrl"; - - uart0_pmux: uart0-pmux { - groups = "GSM12"; - function = "uart0"; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; -}; diff --git a/dts/upstream/Bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/dts/upstream/Bindings/pinctrl/bitmain,bm1880-pinctrl.txt deleted file mode 100644 index 4980776122c..00000000000 --- a/dts/upstream/Bindings/pinctrl/bitmain,bm1880-pinctrl.txt +++ /dev/null @@ -1,126 +0,0 @@ -Bitmain BM1880 Pin Controller - -This binding describes the pin controller found in the BM1880 SoC. - -Required Properties: - -- compatible: Should be "bitmain,bm1880-pinctrl" -- reg: Offset and length of pinctrl space in SCTRL. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration for BM1880 SoC -includes pinmux and various pin configuration parameters, such as pull-up, -slew rate etc... - -Each configuration node can consist of multiple nodes describing the pinmux -options. The name of each subnode is not important; all subnodes should be -enumerated and processed purely based on their content. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pinmux subnode: - -Required Properties: - -- pins: An array of strings, each string containing the name of a pin. - Valid values for pins are: - - MIO0 - MIO111 - -- groups: An array of strings, each string containing the name of a pin - group. Valid values for groups are: - - nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp, - pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp, - pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp, - pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp, - pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp, - pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp, - pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp, - pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp, - i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp, - uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp, - uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp, - uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp, - gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp, - gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp, - gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp, - gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp, - gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp, - gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp, - gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp, - gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp, - gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp, - gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp, - gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp, - gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp, - gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp, - gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp, - i2s1_grp, i2s1_mclkin_grp, spi0_grp - -- function: An array of strings, each string containing the name of the - pinmux functions. The following are the list of pinmux - functions available: - - nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4, - pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13, - pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22, - pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31, - pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3, - i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7, - uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15, - gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, - gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16, - gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, - gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, - gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, - gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, - gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51, - gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58, - gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65, - gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, - spi0 - -Optional Properties: - -- bias-disable: No arguments. Disable pin bias. -- bias-pull-down: No arguments. The specified pins should be configured as - pull down. -- bias-pull-up: No arguments. The specified pins should be configured as - pull up. -- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified - pins -- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified - pins -- slew-rate: Integer. Sets slew rate for the specified pins. - Valid values are: - <0> - Slow - <1> - Fast -- drive-strength: Integer. Selects the drive strength for the specified - pins in mA. - Valid values are: - <4> - <8> - <12> - <16> - <20> - <24> - <28> - <32> - -Example: - pinctrl: pinctrl@400 { - compatible = "bitmain,bm1880-pinctrl"; - reg = <0x400 0x120>; - - pinctrl_uart0_default: uart0-default { - pinmux { - groups = "uart0_grp"; - function = "uart0"; - }; - }; - }; diff --git a/dts/upstream/Bindings/pinctrl/bitmain,bm1880-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/bitmain,bm1880-pinctrl.yaml new file mode 100644 index 00000000000..542be987083 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/bitmain,bm1880-pinctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/bitmain,bm1880-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 Pin Controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: bitmain,bm1880-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + description: A pin configuration node. + type: object + additionalProperties: false + + properties: + pinmux: + type: object + description: Pin multiplexing parameters. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + pins: + items: + pattern: '^MIO[0-9]+$' + + groups: + items: + enum: [ + nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp, + pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp, + pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp, + pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp, + pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp, + pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp, + pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp, + pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp, + i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp, + uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp, + uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp, + uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp, + gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp, + gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp, + gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp, + gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp, + gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp, + gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp, + gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp, + gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp, + gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp, + gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp, + gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp, + gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp, + gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp, + gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp, + i2s1_grp, i2s1_mclkin_grp, spi0_grp + ] + + function: + items: + enum: [ + nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4, + pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13, + pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22, + pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31, + pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3, + i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7, + uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15, + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, + gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16, + gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, + gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, + gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, + gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, + gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51, + gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58, + gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65, + gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, + spi0 + ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + + slew-rate: + description: > + Sets slew rate. Valid values: 0 = Slow, 1 = Fast. + enum: [0, 1] + + drive-strength: + enum: [4, 8, 12, 16, 20, 24, 28, 32] + + oneOf: + - required: + - pins + - required: + - groups + + required: + - function + +required: + - compatible + - reg + +examples: + - | + pinctrl@400 { + compatible = "bitmain,bm1880-pinctrl"; + reg = <0x400 0x120>; + + uart0-default { + pinmux { + groups = "uart0_grp"; + function = "uart0"; + }; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml index 1283a588416..a2e609b066e 100644 --- a/dts/upstream/Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml @@ -116,7 +116,6 @@ patternProperties: input-schmitt-enable: false input-schmitt-disable: false - required: - compatible - reg diff --git a/dts/upstream/Bindings/pinctrl/brcm,ns2-pinmux.txt b/dts/upstream/Bindings/pinctrl/brcm,ns2-pinmux.txt deleted file mode 100644 index 40e0a9a1952..00000000000 --- a/dts/upstream/Bindings/pinctrl/brcm,ns2-pinmux.txt +++ /dev/null @@ -1,102 +0,0 @@ -Broadcom Northstar2 IOMUX Controller - -The Northstar2 IOMUX controller supports group based mux configuration. There -are some individual pins that support modifying the pinconf parameters. - -Required properties: - -- compatible: - Must be "brcm,ns2-pinmux" - -- reg: - Define the base and range of the I/O address space that contains the - Northstar2 IOMUX and pin configuration registers. - -Properties in sub nodes: - -- function: - The mux function to select - -- groups: - The list of groups to select with a given function - -- pins: - List of pin names to change configuration - -The generic properties bias-disable, bias-pull-down, bias-pull-up, -drive-strength, slew-rate, input-enable, input-disable are supported -for some individual pins listed at the end. - -For more details, refer to -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -For example: - - pinctrl: pinctrl@6501d130 { - compatible = "brcm,ns2-pinmux"; - reg = <0x6501d130 0x08>, - <0x660a0028 0x04>, - <0x660009b0 0x40>; - - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>, <&uart3_rx>, <&sdio0_d4>; - - /* Select nand function */ - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; - - /* Pull up the uart3 rx pin */ - uart3_rx: uart3_rx { - pins = "uart3_sin"; - bias-pull-up; - }; - - /* Set the drive strength of sdio d4 pin */ - sdio0_d4: sdio0_d4 { - pins = "sdio0_data4"; - drive-strength = <8>; - }; - }; - -List of supported functions and groups in Northstar2: - -"nand": "nand_grp" - -"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp", - "nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp", - "nor_addr_12_15_grp" - -"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp", - "gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp", - "gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp", - "gpio_28_29_grp", "gpio_30_31_grp" - -"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", - "pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp" - -"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp" - -"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", - "uart1_rts_cts_grp", "uart1_in_out_grp" - -"uart2": "uart2_rts_cts_grp" - -"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp" - - -List of pins that support pinconf parameters: - -"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout", -"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck", -"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7", -"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4", -"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1", -"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk", -"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1", -"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk", -"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc", -"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent", -"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc", -"usb2_overcurrent", "sata_led1", "sata_led0" diff --git a/dts/upstream/Bindings/pinctrl/brcm,ns2-pinmux.yaml b/dts/upstream/Bindings/pinctrl/brcm,ns2-pinmux.yaml new file mode 100644 index 00000000000..1de23c06fa4 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/brcm,ns2-pinmux.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,ns2-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar2 IOMUX Controller + +maintainers: + - Ray Jui + - Scott Branden + +properties: + compatible: + const: brcm,ns2-pinmux + + reg: + maxItems: 3 + +additionalProperties: + description: Pin group node properties + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: The mux function to select + $ref: /schemas/types.yaml#/definitions/string + + groups: + items: + enum: [ + nand_grp, nor_data_grp, nor_adv_grp, nor_addr_0_3_grp, + nor_addr_4_5_grp, nor_addr_6_7_grp, nor_addr_8_9_grp, + nor_addr_10_11_grp, nor_addr_12_15_grp, gpio_0_1_grp, gpio_2_5_grp, + gpio_6_7_grp, gpio_8_9_grp, gpio_10_11_grp, gpio_12_13_grp, + gpio_14_17_grp, gpio_18_19_grp, gpio_20_21_grp, gpio_22_23_grp, + gpio_24_25_grp, gpio_26_27_grp, gpio_28_29_grp, gpio_30_31_grp, + pcie_ab1_clk_wak_grp, pcie_a3_clk_wak_grp, pcie_b3_clk_wak_grp, + pcie_b2_clk_wak_grp, pcie_a2_clk_wak_grp, uart0_modem_grp, + uart0_rts_cts_grp, uart0_in_out_grp, uart1_ext_clk_grp, + uart1_dcd_dsr_grp, uart1_ri_dtr_grp, uart1_rts_cts_grp, + uart1_in_out_grp, uart2_rts_cts_grp, pwm_0_grp, pwm_1_grp, pwm_2_grp, + pwm_3_grp + ] + + pins: + items: + enum: [ + qspi_wp, qspi_hold, qspi_cs, qspi_sck, uart3_sin, uart3_sout, + qspi_mosi, qspi_miso, spi0_fss, spi0_rxd, spi0_txd, spi0_sck, + spi1_fss, spi1_rxd, spi1_txd, spi1_sck, sdio0_data7, sdio0_emmc_rst, + sdio0_led_on, sdio0_wp, sdio0_data3, sdio0_data4, sdio0_data5, + sdio0_data6, sdio0_cmd, sdio0_data0, sdio0_data1, sdio0_data2, + sdio1_led_on, sdio1_wp, sdio0_cd_l, sdio0_clk, sdio1_data5, + sdio1_data6, sdio1_data7, sdio1_emmc_rst, sdio1_data1, sdio1_data2, + sdio1_data3, sdio1_data4, sdio1_cd_l, sdio1_clk, sdio1_cmd, + sdio1_data0, ext_mdio_0, ext_mdc_0, usb3_p1_vbus_ppc, + usb3_p1_overcurrent, usb3_p0_vbus_ppc, usb3_p0_overcurrent, + usb2_presence_indication, usb2_vbus_present, usb2_vbus_ppc, + usb2_overcurrent, sata_led1, sata_led0 + ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + slew-rate: true + input-enable: true + input-disable: true + + oneOf: + - required: + - groups + - function + - required: + - pins + +required: + - compatible + - reg + +examples: + - | + pinctrl@6501d130 { + compatible = "brcm,ns2-pinmux"; + reg = <0x6501d130 0x08>, + <0x660a0028 0x04>, + <0x660009b0 0x40>; + + /* Select nand function */ + nand-sel { + function = "nand"; + groups = "nand_grp"; + }; + + /* Pull up the uart3 rx pin */ + uart3-rx { + pins = "uart3_sin"; + bias-pull-up; + }; + + /* Set the drive strength of sdio d4 pin */ + sdio0-d4 { + pins = "sdio0_data4"; + drive-strength = <8>; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/cix,sky1-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/cix,sky1-pinctrl.yaml new file mode 100644 index 00000000000..8ed53496c38 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/cix,sky1-pinctrl.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 Soc Pin Controller + +maintainers: + - Gary Yang + +description: + The pin-controller is used to control Soc pins. There are two pin-controllers + on Cix Sky1 platform. one is used under S0 state, the other one is used under + S0 and S5 state. + +properties: + compatible: + enum: + - cix,sky1-pinctrl + - cix,sky1-pinctrl-s5 + + reg: + items: + - description: gpio base + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + 'pins$': + type: object + additionalProperties: false + + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias pull, + and drive strength. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + Values are constructed from pin number and mux setting, pin + number is left shifted by 8 bits, then ORed with mux setting + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + description: + typical current when output high level. + enum: [ 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23, + 24 ] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0) + pinctrl@4170000 { + compatible = "cix,sky1-pinctrl"; + reg = <0x4170000 0x1000>; + + wifi_vbat_gpio: wifi-vbat-gpio-cfg { + pins { + pinmux = ; + bias-pull-up; + drive-strength = <8>; + }; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/fsl,imx9-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/fsl,imx9-pinctrl.yaml index a438db8884f..96e7b699527 100644 --- a/dts/upstream/Bindings/pinctrl/fsl,imx9-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/fsl,imx9-pinctrl.yaml @@ -58,7 +58,6 @@ patternProperties: - description: | "pad_setting" indicates the pad configuration value to be applied. - required: - fsl,pins diff --git a/dts/upstream/Bindings/pinctrl/marvell,ap806-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/marvell,ap806-pinctrl.yaml new file mode 100644 index 00000000000..00a7e358a8c --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/marvell,ap806-pinctrl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,ap806-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell AP806 pin controller + +maintainers: + - Gregory Clement + - Miquel Raynal + +properties: + compatible: + const: marvell,ap806-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + properties: + marvell,function: + $ref: /schemas/types.yaml#/definitions/string + description: + Indicates the function to select. + enum: [ gpio, i2c0, sdio, spi0, uart0, uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + maxItems: 20 + items: + enum: [ + mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, mpp10, + mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19 + ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "marvell,ap806-pinctrl"; + + uart0_pins: uart0-pins { + marvell,pins = "mpp11", "mpp19"; + marvell,function = "uart0"; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/dts/upstream/Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt deleted file mode 100644 index ecec514b315..00000000000 --- a/dts/upstream/Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt +++ /dev/null @@ -1,195 +0,0 @@ -* Marvell Armada 37xx SoC pin and gpio controller - -Each Armada 37xx SoC come with two pin and gpio controller one for the -south bridge and the other for the north bridge. - -Inside this set of register the gpio latch allows exposing some -configuration of the SoC and especially the clock frequency of the -xtal. Hence, this node is a represent as syscon allowing sharing the -register between multiple hardware block. - -GPIO and pin controller: ------------------------- - -Main node: - -Refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning -of the phrase "pin configuration node". - -Required properties for pinctrl driver: - -- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd" - for the south bridge - "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd" - for the north bridge -- reg: The first set of register are for pinctrl/gpio and the second - set for the interrupt controller -- interrupts: list of the interrupt use by the gpio - -Available groups and functions for the North bridge: - -group: jtag - - pins 20-24 - - functions jtag, gpio - -group sdio0 - - pins 8-10 - - functions sdio, gpio - -group emmc_nb - - pins 27-35 - - functions emmc, gpio - -group pwm0 - - pin 11 (GPIO1-11) - - functions pwm, led, gpio - -group pwm1 - - pin 12 - - functions pwm, led, gpio - -group pwm2 - - pin 13 - - functions pwm, led, gpio - -group pwm3 - - pin 14 - - functions pwm, led, gpio - -group pmic1 - - pin 7 - - functions pmic, gpio - -group pmic0 - - pin 6 - - functions pmic, gpio - -group i2c2 - - pins 2-3 - - functions i2c, gpio - -group i2c1 - - pins 0-1 - - functions i2c, gpio - -group spi_cs1 - - pin 17 - - functions spi, gpio - -group spi_cs2 - - pin 18 - - functions spi, gpio - -group spi_cs3 - - pin 19 - - functions spi, gpio - -group onewire - - pin 4 - - functions onewire, gpio - -group uart1 - - pins 25-26 - - functions uart, gpio - -group spi_quad - - pins 15-16 - - functions spi, gpio - -group uart2 - - pins 9-10 and 18-19 - - functions uart, gpio - -Available groups and functions for the South bridge: - -group usb32_drvvbus0 - - pin 36 - - functions drvbus, gpio - -group usb2_drvvbus1 - - pin 37 - - functions drvbus, gpio - -group sdio_sb - - pins 60-65 - - functions sdio, gpio - -group rgmii - - pins 42-53 - - functions mii, gpio - -group pcie1 - - pins 39 - - functions pcie, gpio - -group pcie1_clkreq - - pins 40 - - functions pcie, gpio - -group pcie1_wakeup - - pins 41 - - functions pcie, gpio - -group smi - - pins 54-55 - - functions smi, gpio - -group ptp - - pins 56 - - functions ptp, gpio - -group ptp_clk - - pin 57 - - functions ptp, mii - -group ptp_trig - - pin 58 - - functions ptp, mii - -group mii_col - - pin 59 - - functions mii, mii_err - -GPIO subnode: - -Please refer to gpio.txt in this directory for details of gpio-ranges property -and the common GPIO bindings used by client devices. - -Required properties for gpio driver under the gpio subnode: -- interrupts: List of interrupt specifier for the controllers interrupt. -- gpio-controller: Marks the device node as a gpio controller. -- #gpio-cells: Should be 2. The first cell is the GPIO number and the - second cell specifies GPIO flags, as defined in - . Only the GPIO_ACTIVE_HIGH and - GPIO_ACTIVE_LOW flags are supported. -- gpio-ranges: Range of pins managed by the GPIO controller. - -Xtal Clock bindings for Marvell Armada 37xx SoCs ------------------------------------------------- - -see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt - - -Example: -pinctrl_sb: pinctrl-sb@18800 { - compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; - reg = <0x18800 0x100>, <0x18C00 0x20>; - gpio { - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; - gpio-controller; - interrupts = - , - , - , - , - ; - }; - - rgmii_pins: mii-pins { - groups = "rgmii"; - function = "mii"; - }; - -}; diff --git a/dts/upstream/Bindings/pinctrl/marvell,armada-7k-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/marvell,armada-7k-pinctrl.yaml new file mode 100644 index 00000000000..88910ad170e --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/marvell,armada-7k-pinctrl.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,armada-7k-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K pin controller + +maintainers: + - Gregory Clement + - Miquel Raynal + +properties: + compatible: + enum: + - marvell,armada-7k-pinctrl + - marvell,armada-8k-cpm-pinctrl + - marvell,armada-8k-cps-pinctrl + - marvell,cp115-standalone-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins(-.+)?$': + type: object + additionalProperties: false + + properties: + marvell,function: + $ref: /schemas/types.yaml#/definitions/string + description: + Indicates the function to select. + enum: [ + au, dev, ge, ge0, ge1, gpio, i2c0, i2c1, led, link, mii, mss_gpio0, + mss_gpio1, mss_gpio2, mss_gpio3, mss_gpio4, mss_gpio5, mss_gpio6, + mss_gpio7, mss_i2c, mss_spi, mss_uart, nf, pcie, pcie0, pcie1, pcie2, + ptp, rei, sata0, sata1, sdio, sdio_cd, sdio_wp, sei, spi0, spi1, + synce1, synce2, tdm, uart0, uart1, uart2, uart3, wakeup, xg + ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + maxItems: 63 + items: + pattern: '^mpp([1-5]?[0-9]|6[0-2])$' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function = "dev"; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml new file mode 100644 index 00000000000..4f9013d3687 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 37xx SoC pin and gpio controller + +maintainers: + - Gregory CLEMENT + - Marek Behún + - Miquel Raynal + +description: > + Each Armada 37xx SoC come with two pin and gpio controller one for the south + bridge and the other for the north bridge. + + Inside this set of register the gpio latch allows exposing some configuration + of the SoC and especially the clock frequency of the xtal. Hence, this node is + a represent as syscon allowing sharing the register between multiple hardware + block. + +properties: + compatible: + items: + - enum: + - marvell,armada3710-sb-pinctrl + - marvell,armada3710-nb-pinctrl + - const: syscon + - const: simple-mfd + + reg: + items: + - description: pinctrl and GPIO controller registers + - description: interrupt controller registers + + gpio: + description: GPIO controller subnode + type: object + additionalProperties: false + + properties: + '#gpio-cells': + const: 2 + + gpio-controller: true + + gpio-ranges: + description: Range of pins managed by the GPIO controller + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + interrupts: + description: List of interrupt specifiers for the GPIO controller + + required: + - '#gpio-cells' + - gpio-ranges + - gpio-controller + - '#interrupt-cells' + - interrupt-controller + - interrupts + + xtal-clk: + type: object + additionalProperties: false + + properties: + compatible: + const: marvell,armada-3700-xtal-clock + + '#clock-cells': + const: 0 + + clock-output-names: true + +patternProperties: + '-pins$': + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1, + pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk, + ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi, + spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2, + usb2_drvvbus1, usb32_drvvbus0 ] + + function: + enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire, + pcie, pmic, ptp, pwm, sdio, smi, spi, uart ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinctrl_sb: pinctrl@18800 { + compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; + reg = <0x18800 0x100>, <0x18C00 0x20>; + + gpio { + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = + , + , + , + , + ; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml new file mode 100644 index 00000000000..6ace3bf5433 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,berlin2-soc-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Berlin pin-controller driver + +maintainers: + - Antoine Tenart + - Jisheng Zhang + +description: > + Pin control registers are part of both chip controller and system controller + register sets. Pin controller nodes should be a sub-node of either the chip + controller or system controller node. The pins controlled are organized in + groups, so no actual pin information is needed. + + A pin-controller node should contain subnodes representing the pin group + configurations, one per function. Each subnode has the group name and the + muxing function used. + + Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is + called a 'function' in the pin-controller subsystem. + +properties: + compatible: + items: + - enum: + - marvell,berlin2-soc-pinctrl + - marvell,berlin2-system-pinctrl + - marvell,berlin2cd-soc-pinctrl + - marvell,berlin2cd-system-pinctrl + - marvell,berlin2q-soc-pinctrl + - marvell,berlin2q-system-pinctrl + - marvell,berlin4ct-avio-pinctrl + - marvell,berlin4ct-soc-pinctrl + - marvell,berlin4ct-system-pinctrl + - syna,as370-soc-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + description: Pin group configuration subnodes. + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + description: List of pin group names. + $ref: /schemas/types.yaml#/definitions/string-array + + function: + description: Function used to mux the group. + $ref: /schemas/types.yaml#/definitions/string + + required: + - groups + - function + +allOf: + - if: + properties: + compatible: + contains: + enum: + - marvell,berlin4ct-avio-pinctrl + - marvell,berlin4ct-soc-pinctrl + - marvell,berlin4ct-system-pinctrl + - syna,as370-soc-pinctrl + then: + required: + - reg + +examples: + - | + pinctrl { + compatible = "marvell,berlin2q-system-pinctrl"; + + uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/mediatek,mt6878-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/mediatek,mt6878-pinctrl.yaml new file mode 100644 index 00000000000..8d44194a793 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/mediatek,mt6878-pinctrl.yaml @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6878 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno + - Igor Belwon + +description: + The MediaTek MT6878 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6878-pinctrl + + reg: + items: + - description: pin controller base + - description: bl group IO + - description: bm group IO + - description: br group IO + - description: bl1 group IO + - description: br1 group IO + - description: lm group IO + - description: lt group IO + - description: rm group IO + - description: rt group IO + - description: EINT controller E block + - description: EINT controller S block + - description: EINT controller W block + - description: EINT controller C block + + reg-names: + items: + - const: base + - const: bl + - const: bm + - const: br + - const: bl1 + - const: br1 + - const: lm + - const: lt + - const: rm + - const: rt + - const: eint-e + - const: eint-s + - const: eint-w + - const: eint-c + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + maxItems: 216 + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [75000, 5000] + description: Pull down RSEL type resistance values (in ohms) + description: + For normal pull down type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull down type a resistance value (in ohms) can be added. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [10000, 5000, 4000, 3000] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6878-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11d50000 0x1000>, + <0x11d60000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11eb0000 0x1000>, + <0x11ec0000 0x1000>, + <0x11ce0000 0x1000>, + <0x11de0000 0x1000>, + <0x11e60000 0x1000>, + <0x1c01e000 0x1000>; + reg-names = "base", "bl", "bm", "br", "bl1", "br1", + "lm", "lt", "rm", "rt", "eint-e", "eint-s", + "eint-w", "eint-c"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + gpio-pins { + pins { + pinmux = ; + bias-pull-up = <4000>; + drive-strength = <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux = , + ; + bias-pull-down = <75000>; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml index 26dfe7e7735..1f31b520cb4 100644 --- a/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml @@ -61,6 +61,11 @@ required: - "#gpio-cells" patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins$': type: object additionalProperties: false diff --git a/dts/upstream/Bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml b/dts/upstream/Bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml new file mode 100644 index 00000000000..3c98eb35fb8 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC iomux0 + +maintainers: + - Conor Dooley + +description: + iomux0 is responsible for routing some functions to either the FPGA fabric, + or to MSSIOs. It only performs muxing, and has no IO configuration role, as + fabric IOs are configured separately and just routing a function to MSSIOs is + not sufficient for it to actually get mapped to an MSSIO, just makes it + possible. + +properties: + compatible: + oneOf: + - const: microchip,mpfs-pinctrl-iomux0 + - items: + - const: microchip,pic64gx-pinctrl-iomux0 + - const: microchip,mpfs-pinctrl-iomux0 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, uart2, + uart3, uart4, mdio0, mdio1 ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_fabric, + i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_mssio, + can1_fabric, can1_mssio, qspi_fabric, qspi_mssio, + uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio, + uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio, + uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio, + mdio1_fabric, mdio1_mssio ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #size-cells = <1>; + #address-cells = <1>; + + pinctrl@200 { + compatible = "microchip,mpfs-pinctrl-iomux0"; + reg = <0x200 0x4>; + + mux-spi0-fabric { + function = "spi0"; + groups = "spi0_fabric"; + }; + + mux-spi1-mssio { + function = "spi1"; + groups = "spi1_mssio"; + }; + }; + }; + +... diff --git a/dts/upstream/Bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml b/dts/upstream/Bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml new file mode 100644 index 00000000000..e3792679de5 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64GX GPIO2 Mux + +maintainers: + - Conor Dooley + +description: + The "GPIO2 Mux" determines whether GPIO2 or select other functions are + available on package pins on PIC64GX. Some of these functions must be + mapped to this mux via iomux0 for settings here to have any impact. + +properties: + compatible: + const: microchip,pic64gx-pinctrl-gpio2 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, gpio ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, + gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie, + gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2 ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@41000000 { + compatible = "microchip,pic64gx-pinctrl-gpio2"; + reg = <0x41000000 0x4>; + pinctrl-use-default; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_gpio2>, + <&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gpio2>, + <&uart2_gpio2>; + + mux-gpio2 { + function = "gpio"; + groups = "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1"; + }; + }; + +... diff --git a/dts/upstream/Bindings/pinctrl/microchip,sparx5-sgpio.yaml b/dts/upstream/Bindings/pinctrl/microchip,sparx5-sgpio.yaml index 0df4e114fdd..fa47732d7ce 100644 --- a/dts/upstream/Bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/dts/upstream/Bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -18,7 +18,7 @@ description: | properties: $nodename: - pattern: "^gpio@[0-9a-f]+$" + pattern: '^gpio@[0-9a-f]+$' compatible: enum: @@ -26,10 +26,10 @@ properties: - mscc,ocelot-sgpio - mscc,luton-sgpio - "#address-cells": + '#address-cells': const: 1 - "#size-cells": + '#size-cells': const: 0 reg: @@ -76,7 +76,7 @@ properties: - const: switch patternProperties: - "^gpio@[0-1]$": + '^gpio@[0-1]$': type: object properties: compatible: @@ -132,8 +132,8 @@ required: - reg - clocks - microchip,sgpio-port-ranges - - "#address-cells" - - "#size-cells" + - '#address-cells' + - '#size-cells' examples: - | diff --git a/dts/upstream/Bindings/pinctrl/pincfg-node.yaml b/dts/upstream/Bindings/pinctrl/pincfg-node.yaml index cbfcf215e57..a916d0fc79a 100644 --- a/dts/upstream/Bindings/pinctrl/pincfg-node.yaml +++ b/dts/upstream/Bindings/pinctrl/pincfg-node.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic Pin Configuration Node maintainers: - - Linus Walleij + - Linus Walleij description: Many data items that are represented in a pin configuration node are common @@ -153,4 +153,21 @@ properties: pin. Typically indicates how many double-inverters are used to delay the signal. + skew-delay-input-ps: + description: + this affects the expected clock skew in ps on an input pin. + + skew-delay-output-ps: + description: + this affects the expected delay in ps before latching a value to + an output pin. + +if: + required: + - skew-delay +then: + properties: + skew-delay-input-ps: false + skew-delay-output-ps: false + additionalProperties: true diff --git a/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml b/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml index f83dbf32ad1..9135788cf62 100644 --- a/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml +++ b/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml @@ -24,6 +24,7 @@ properties: - items: - enum: - ti,am437-padconf + - ti,am62l-padconf - ti,am654-padconf - ti,dra7-padconf - ti,omap2420-padconf diff --git a/dts/upstream/Bindings/pinctrl/pinctrl.yaml b/dts/upstream/Bindings/pinctrl/pinctrl.yaml index d471563119a..290438826c5 100644 --- a/dts/upstream/Bindings/pinctrl/pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Pin controller device maintainers: - - Linus Walleij + - Linus Walleij - Rafał Miłecki description: | diff --git a/dts/upstream/Bindings/pinctrl/pinmux-node.yaml b/dts/upstream/Bindings/pinctrl/pinmux-node.yaml index ca9d246d46f..7ba26271c4d 100644 --- a/dts/upstream/Bindings/pinctrl/pinmux-node.yaml +++ b/dts/upstream/Bindings/pinctrl/pinmux-node.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic Pin Multiplexing Node maintainers: - - Linus Walleij + - Linus Walleij description: | The contents of the pin configuration child nodes are defined by the binding diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml index 23300606547..96635b2f6a2 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml @@ -8,7 +8,7 @@ title: Qualcomm IPQ5018 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml index e571cd64418..22685c47998 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml @@ -8,7 +8,7 @@ title: Qualcomm IPQ5332 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: | Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml index 6f90dbbdbdc..40def3ac3bf 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm IPQ8074 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml index bca903b5da6..7afec315b63 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml @@ -8,7 +8,7 @@ title: Qualcomm Technologies, Inc. IPQ9574 TLMM block maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,kaanapali-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,kaanapali-tlmm.yaml new file mode 100644 index 00000000000..53534a07a1f --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/qcom,kaanapali-tlmm.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kaanapali-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kaanapali TLMM block + +maintainers: + - Jingyi Wang + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Kaanapali SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kaanapali-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 109 + + gpio-line-names: + maxItems: 217 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-kaanapali-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kaanapali-tlmm-state" + additionalProperties: false + +$defs: + qcom-kaanapali-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-6])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_asc_mclk2, cam_asc_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2, + ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, + gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3, + i2chub0_se4, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, + mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup3_se0, qup3_se1, qup3_se2, + qup3_se3, qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, + qup4_se3, qup4_se4, sd_write_protect, sdc40, sdc41, sdc42, sdc43, + sdc4_clk, sdc4_cmd, sys_throttle, tb_trig_sdc2, tb_trig_sdc4, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, tsense_pwm5, tsense_pwm6, + tsense_pwm7, uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, + vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,kaanapali-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 218>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + }; + }; +... diff --git a/dts/upstream/Bindings/pinctrl/qcom,lpass-lpi-common.yaml b/dts/upstream/Bindings/pinctrl/qcom,lpass-lpi-common.yaml index 3b504573047..619341dd637 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,lpass-lpi-common.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,lpass-lpi-common.yaml @@ -9,7 +9,7 @@ title: Qualcomm SoC LPASS LPI TLMM Common Properties maintainers: - Bjorn Andersson - Srinivas Kandagatla - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Common properties for the Top Level Mode Multiplexer pin controllers in the diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml index 61f5be21f30..203ad69e99e 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8660 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml index 904af87f9ea..9bf098cf18e 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8916 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8916 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml index 46618740bd3..7301318094c 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8960 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8960 SoC. @@ -107,12 +107,12 @@ examples: - | #include - msmgpio: pinctrl@800000 { + tlmm: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; reg = <0x800000 0x4000>; #gpio-cells = <2>; gpio-controller; - gpio-ranges = <&msmgpio 0 0 152>; + gpio-ranges = <&tlmm 0 0 152>; interrupts = ; interrupt-controller; #interrupt-cells = <2>; diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml index 840fdaabde1..a9aff442824 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8974 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8974 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml index d4391c194ff..501329bff90 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8976 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8976 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml index fa90981db40..2ec10908d55 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8994 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml index c5010c175b2..496f38009c7 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8996 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8996 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml index bcaa231adaf..3b098a226a6 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM8998 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm MSM8998 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml b/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml index 5e6dfcc3fe9..386c31e9c52 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml @@ -59,7 +59,11 @@ properties: - qcom,pmc8180-gpio - qcom,pmc8180c-gpio - qcom,pmc8380-gpio + - qcom,pmcx0102-gpio - qcom,pmd8028-gpio + - qcom,pmh0101-gpio + - qcom,pmh0104-gpio + - qcom,pmh0110-gpio - qcom,pmi632-gpio - qcom,pmi8950-gpio - qcom,pmi8994-gpio @@ -68,6 +72,7 @@ properties: - qcom,pmiv0104-gpio - qcom,pmk8350-gpio - qcom,pmk8550-gpio + - qcom,pmk8850-gpio - qcom,pmm8155au-gpio - qcom,pmm8654au-gpio - qcom,pmp8074-gpio @@ -191,6 +196,8 @@ allOf: - qcom,pm8950-gpio - qcom,pm8953-gpio - qcom,pmi632-gpio + - qcom,pmh0104-gpio + - qcom,pmk8850-gpio then: properties: gpio-line-names: @@ -303,6 +310,8 @@ allOf: compatible: contains: enum: + - qcom,pmcx0102-gpio + - qcom,pmh0110-gpio - qcom,pmi8998-gpio then: properties: @@ -318,6 +327,7 @@ allOf: compatible: contains: enum: + - qcom,pmh0101-gpio - qcom,pmih0108-gpio then: properties: @@ -424,13 +434,13 @@ allOf: patternProperties: '-state$': oneOf: - - $ref: "#/$defs/qcom-pmic-gpio-state" + - $ref: '#/$defs/qcom-pmic-gpio-state' - patternProperties: - "(pinconf|-pins)$": - $ref: "#/$defs/qcom-pmic-gpio-state" + '(pinconf|-pins)$': + $ref: '#/$defs/qcom-pmic-gpio-state' additionalProperties: false - "-hog(-[0-9]+)?$": + '-hog(-[0-9]+)?$': type: object required: - gpio-hog @@ -481,13 +491,18 @@ $defs: - gpio1-gpio22 for pm8994 - gpio1-gpio26 for pm8998 - gpio1-gpio22 for pma8084 + - gpio1-gpio14 for pmcx0102 - gpio1-gpio4 for pmd8028 + - gpio1-gpio18 for pmh0101 + - gpio1-gpio8 for pmh0104 + - gpio1-gpio14 for pmh0110 - gpio1-gpio8 for pmi632 - gpio1-gpio2 for pmi8950 - gpio1-gpio10 for pmi8994 - gpio1-gpio18 for pmih0108 - gpio1-gpio4 for pmk8350 - gpio1-gpio6 for pmk8550 + - gpio1-gpio8 for pmk8850 - gpio1-gpio10 for pmm8155au - gpio1-gpio12 for pmm8654au - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12) @@ -503,7 +518,7 @@ $defs: - gpio1-gpio12 for pmxr2230 items: - pattern: "^gpio([0-9]+)$" + pattern: '^gpio([0-9]+)$' function: items: diff --git a/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml b/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml index 9364ae05f3e..daf4c1c0371 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml @@ -74,10 +74,10 @@ required: patternProperties: '-state$': oneOf: - - $ref: "#/$defs/qcom-pmic-mpp-state" + - $ref: '#/$defs/qcom-pmic-mpp-state' - patternProperties: '-pins$': - $ref: "#/$defs/qcom-pmic-mpp-state" + $ref: '#/$defs/qcom-pmic-mpp-state' additionalProperties: false $defs: @@ -100,7 +100,7 @@ $defs: - mpp1-mpp4 for pma8084 items: - pattern: "^mpp([0-9]+)$" + pattern: '^mpp([0-9]+)$' function: items: diff --git a/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml index 4009501b341..91b8dcec3f0 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm QCS404 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC. @@ -142,7 +142,6 @@ examples: interrupt-controller; #interrupt-cells = <2>; - blsp1-i2c1-default-state { pins = "gpio24", "gpio25"; function = "blsp_i2c1"; diff --git a/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml index 5606f2136ad..ec0bf4fdfa4 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm SC7180 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml index a00cb43df14..80627a1ad66 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm SDM630 and SDM660 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml index 0f331844608..4fcac2e55b5 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm SDM845 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml index f4cf2ce86fc..d2a036ead84 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml @@ -16,7 +16,13 @@ description: properties: compatible: - const: qcom,sm6115-lpass-lpi-pinctrl + oneOf: + - enum: + - qcom,sm6115-lpass-lpi-pinctrl + - items: + - enum: + - qcom,qcm2290-lpass-lpi-pinctrl + - const: qcom,sm6115-lpass-lpi-pinctrl reg: items: @@ -66,7 +72,6 @@ $defs: Specify the alternative function to be configured for the specified pins. - allOf: - $ref: qcom,lpass-lpi-common.yaml# diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml index ddeaeaa9a45..5a57a59cc1e 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml @@ -88,7 +88,6 @@ $defs: uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ] - required: - pins diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml index bdb7ed4be02..c4542e2d710 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml @@ -8,7 +8,7 @@ title: Qualcomm SM8150 TLMM pin controller maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC. diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml index 9d782f910b3..46aec071377 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SM8350 SoC LPASS LPI TLMM maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla description: diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml index bf4a72facae..89821871c60 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SM8550 SoC LPASS LPI TLMM maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla description: diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml index e90a5274647..74df912e60a 100644 --- a/dts/upstream/Bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SM8650 SoC LPASS LPI TLMM maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla description: diff --git a/dts/upstream/Bindings/pinctrl/renesas,pfc.yaml b/dts/upstream/Bindings/pinctrl/renesas,pfc.yaml index cfe00457336..075f3abdfbe 100644 --- a/dts/upstream/Bindings/pinctrl/renesas,pfc.yaml +++ b/dts/upstream/Bindings/pinctrl/renesas,pfc.yaml @@ -129,7 +129,7 @@ additionalProperties: - type: object additionalProperties: - $ref: "#/additionalProperties/anyOf/0" + $ref: '#/additionalProperties/anyOf/0' examples: - | diff --git a/dts/upstream/Bindings/pinctrl/renesas,rza1-ports.yaml b/dts/upstream/Bindings/pinctrl/renesas,rza1-ports.yaml index 2bd7d47d0fd..8203c3c46cc 100644 --- a/dts/upstream/Bindings/pinctrl/renesas,rza1-ports.yaml +++ b/dts/upstream/Bindings/pinctrl/renesas,rza1-ports.yaml @@ -65,7 +65,6 @@ patternProperties: - '#gpio-cells' - gpio-ranges - additionalProperties: anyOf: - type: object @@ -118,7 +117,7 @@ additionalProperties: - type: object additionalProperties: - $ref: "#/additionalProperties/anyOf/0" + $ref: '#/additionalProperties/anyOf/0' examples: - | @@ -150,7 +149,6 @@ examples: pinmux = , ; }; - /* * I2c master: both SDA and SCL pins need bi-directional operations * Pin #4 on port #1 is configured as alternate function #1. @@ -162,7 +160,6 @@ examples: pinmux = , ; }; - /* * Multi-function timer input and output compare pins. */ diff --git a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 5156d54b240..00c05243b9a 100644 --- a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -135,7 +135,7 @@ additionalProperties: - type: object additionalProperties: - $ref: "#/additionalProperties/anyOf/0" + $ref: '#/additionalProperties/anyOf/0' allOf: - $ref: pinctrl.yaml# diff --git a/dts/upstream/Bindings/pinctrl/renesas,rzv2m-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/renesas,rzv2m-pinctrl.yaml index 5fa5d31f886..88b2fa5e684 100644 --- a/dts/upstream/Bindings/pinctrl/renesas,rzv2m-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/renesas,rzv2m-pinctrl.yaml @@ -88,7 +88,7 @@ additionalProperties: - type: object additionalProperties: - $ref: "#/additionalProperties/anyOf/0" + $ref: '#/additionalProperties/anyOf/0' allOf: - $ref: pinctrl.yaml# diff --git a/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml b/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml index 125af766b99..76e60728171 100644 --- a/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml @@ -44,6 +44,7 @@ properties: - rockchip,rk3328-pinctrl - rockchip,rk3368-pinctrl - rockchip,rk3399-pinctrl + - rockchip,rk3506-pinctrl - rockchip,rk3528-pinctrl - rockchip,rk3562-pinctrl - rockchip,rk3568-pinctrl diff --git a/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index dd11c73a55d..f3c433015b1 100644 --- a/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -41,6 +41,7 @@ properties: - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint + - samsung,exynos8890-wakeup-eint - samsung,exynos8895-wakeup-eint - const: samsung,exynos7-wakeup-eint - items: diff --git a/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml b/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml index f1094d65e84..ddc5e2efff2 100644 --- a/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml @@ -36,6 +36,7 @@ properties: compatible: enum: - axis,artpec8-pinctrl + - axis,artpec9-pinctrl - google,gs101-pinctrl - samsung,s3c64xx-pinctrl - samsung,s5pv210-pinctrl @@ -52,6 +53,7 @@ properties: - samsung,exynos7870-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl + - samsung,exynos8890-pinctrl - samsung,exynos8895-pinctrl - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl @@ -133,7 +135,9 @@ allOf: properties: compatible: contains: - const: google,gs101-pinctrl + enum: + - google,gs101-pinctrl + - samsung,exynos8890-pinctrl then: required: - clocks diff --git a/dts/upstream/Bindings/pinctrl/sprd,pinctrl.txt b/dts/upstream/Bindings/pinctrl/sprd,pinctrl.txt deleted file mode 100644 index 779b8ef0f6e..00000000000 --- a/dts/upstream/Bindings/pinctrl/sprd,pinctrl.txt +++ /dev/null @@ -1,83 +0,0 @@ -* Spreadtrum Pin Controller - -The Spreadtrum pin controller are organized in 3 blocks (types). - -The first block comprises some global control registers, and each -register contains several bit fields with one bit or several bits -to configure for some global common configuration, such as domain -pad driving level, system control select and so on ("domain pad -driving level": One pin can output 3.0v or 1.8v, depending on the -related domain pad driving selection, if the related domain pad -select 3.0v, then the pin can output 3.0v. "system control" is used -to choose one function (like: UART0) for which system, since we -have several systems (AP/CP/CM4) on one SoC.). - -There are too much various configuration that we can not list all -of them, so we can not make every Spreadtrum-special configuration -as one generic configuration, and maybe it will add more strange -global configuration in future. Then we add one "sprd,control" to -set these various global control configuration, and we need use -magic number for this property. - -Moreover we recognise every fields comprising one bit or several -bits in one global control register as one pin, thus we should -record every pin's bit offset, bit width and register offset to -configure this field (pin). - -The second block comprises some common registers which have unified -register definition, and each register described one pin is used -to configure the pin sleep mode, function select and sleep related -configuration. - -Now we have 4 systems for sleep mode on SC9860 SoC: AP system, -PUBCP system, TGLDSP system and AGDSP system. And the pin sleep -related configuration are: -- input-enable -- input-disable -- output-high -- output-low -- bias-pull-up -- bias-pull-down - -In some situation we need set the pin sleep mode and pin sleep related -configuration, to set the pin sleep related configuration automatically -by hardware when the system specified by sleep mode goes into deep -sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP -and set the pin sleep related configuration as "input-enable", which -means when PUBCP system goes into deep sleep mode, this pin will be set -input enable automatically. - -Moreover we can not use the "sleep" state, since some systems (like: -PUBCP system) do not run linux kernel OS (only AP system run linux -kernel on SC9860 platform), then we can not select "sleep" state -when the PUBCP system goes into deep sleep mode. Thus we introduce -"sprd,sleep-mode" property to set pin sleep mode. - -The last block comprises some misc registers which also have unified -register definition, and each register described one pin is used to -configure drive strength, pull up/down and so on. Especially for pull -up, we have two kind pull up resistor: 20K and 4.7K. - -Required properties for Spreadtrum pin controller: -- compatible: "sprd,-pinctrl" - Please refer to each sprd,-pinctrl.txt binding doc for supported SoCs. -- reg: The register address of pin controller device. -- pins : An array of pin names. - -Optional properties: -- function: Specified the function name. -- drive-strength: Drive strength in mA. -- input-schmitt-disable: Enable schmitt-trigger mode. -- input-schmitt-enable: Disable schmitt-trigger mode. -- bias-disable: Disable pin bias. -- bias-pull-down: Pull down on pin. -- bias-pull-up: Pull up on pin. -- input-enable: Enable pin input. -- input-disable: Enable pin output. -- output-high: Set the pin as an output level high. -- output-low: Set the pin as an output level low. -- sleep-hardware-state: Indicate these configs in this state are sleep related. -- sprd,control: Control values referring to databook for global control pins. -- sprd,sleep-mode: Sleep mode selection. - -Please refer to each sprd,-pinctrl.txt binding doc for supported values. diff --git a/dts/upstream/Bindings/pinctrl/sprd,sc9860-pinctrl.txt b/dts/upstream/Bindings/pinctrl/sprd,sc9860-pinctrl.txt deleted file mode 100644 index 5a628333d52..00000000000 --- a/dts/upstream/Bindings/pinctrl/sprd,sc9860-pinctrl.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Spreadtrum SC9860 Pin Controller - -Please refer to sprd,pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: Must be "sprd,sc9860-pinctrl". -- reg: The register address of pin controller device. -- pins : An array of strings, each string containing the name of a pin. - -Optional properties: -- function: A string containing the name of the function, values must be - one of: "func1", "func2", "func3" and "func4". -- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10, - 12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33. -- input-schmitt-disable: Enable schmitt-trigger mode. -- input-schmitt-enable: Disable schmitt-trigger mode. -- bias-disable: Disable pin bias. -- bias-pull-down: Pull down on pin. -- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor - is 20K and 4700 for pull-up resistor is 4.7K. -- input-enable: Enable pin input. -- input-disable: Enable pin output. -- output-high: Set the pin as an output level high. -- output-low: Set the pin as an output level low. -- sleep-hardware-state: Indicate these configs in this state are sleep related. -- sprd,control: Control values referring to databook for global control pins. -- sprd,sleep-mode: Choose the pin sleep mode, and supported values are: - AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP. - -Pin sleep mode definition: -enum pin_sleep_mode { - AP_SLEEP = BIT(0), - PUBCP_SLEEP = BIT(1), - TGLDSP_SLEEP = BIT(2), - AGDSP_SLEEP = BIT(3), -}; - -Example: -pin_controller: pinctrl@402a0000 { - compatible = "sprd,sc9860-pinctrl"; - reg = <0x402a0000 0x10000>; - - grp1: sd0 { - pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE"; - sprd,control = <0x1>; - }; - - grp2: rfctl_33 { - pins = "SC9860_RFCTL33"; - function = "func2"; - sprd,sleep-mode = ; - grp2_sleep_mode: rfctl_33_sleep { - pins = "SC9860_RFCTL33"; - sleep-hardware-state; - output-low; - } - }; - - grp3: rfctl_misc_20 { - pins = "SC9860_RFCTL20_MISC"; - drive-strength = <10>; - bias-pull-up = <4700>; - grp3_sleep_mode: rfctl_misc_sleep { - pins = "SC9860_RFCTL20_MISC"; - sleep-hardware-state; - bias-pull-up; - } - }; -}; diff --git a/dts/upstream/Bindings/pinctrl/sprd,sc9860-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/sprd,sc9860-pinctrl.yaml new file mode 100644 index 00000000000..59d23eb8aa9 --- /dev/null +++ b/dts/upstream/Bindings/pinctrl/sprd,sc9860-pinctrl.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sprd,sc9860-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 Pin Controller + +maintainers: + - Baolin Wang + +description: > + The Spreadtrum pin controller are organized in 3 blocks (types). + + The first block comprises some global control registers, and each + register contains several bit fields with one bit or several bits + to configure for some global common configuration, such as domain + pad driving level, system control select and so on ("domain pad + driving level": One pin can output 3.0v or 1.8v, depending on the + related domain pad driving selection, if the related domain pad + select 3.0v, then the pin can output 3.0v. "system control" is used + to choose one function (like: UART0) for which system, since we + have several systems (AP/CP/CM4) on one SoC.). + + There are too much various configuration that we can not list all + of them, so we can not make every Spreadtrum-special configuration + as one generic configuration, and maybe it will add more strange + global configuration in future. Then we add one "sprd,control" to + set these various global control configuration, and we need use + magic number for this property. + + Moreover we recognize every fields comprising one bit or several + bits in one global control register as one pin, thus we should + record every pin's bit offset, bit width and register offset to + configure this field (pin). + + The second block comprises some common registers which have unified + register definition, and each register described one pin is used + to configure the pin sleep mode, function select and sleep related + configuration. + + Now we have 4 systems for sleep mode on SC9860 SoC: AP system, + PUBCP system, TGLDSP system and AGDSP system. And the pin sleep + related configuration are: + - input-enable + - input-disable + - output-high + - output-low + - bias-pull-up + - bias-pull-down + + In some situation we need set the pin sleep mode and pin sleep related + configuration, to set the pin sleep related configuration automatically + by hardware when the system specified by sleep mode goes into deep + sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP + and set the pin sleep related configuration as "input-enable", which + means when PUBCP system goes into deep sleep mode, this pin will be set + input enable automatically. + + Moreover we can not use the "sleep" state, since some systems (like: + PUBCP system) do not run linux kernel OS (only AP system run linux + kernel on SC9860 platform), then we can not select "sleep" state + when the PUBCP system goes into deep sleep mode. Thus we introduce + "sprd,sleep-mode" property to set pin sleep mode. + + The last block comprises some misc registers which also have unified + register definition, and each register described one pin is used to + configure drive strength, pull up/down and so on. Especially for pull + up, we have two kind pull up resistor: 20K and 4.7K. + +properties: + compatible: + const: sprd,sc9860-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + $ref: '#/$defs/pin-node' + unevaluatedProperties: false + + properties: + function: + description: Function to assign to the pins. + enum: + - func1 + - func2 + - func3 + - func4 + + drive-strength: + description: Drive strength in mA. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4, 6, 8, 10, 12, 14, 16, 20, 21, 24, 25, 27, 29, 31, 33] + + input-schmitt-disable: true + + input-schmitt-enable: true + + bias-pull-up: + enum: [20000, 4700] + + sprd,sleep-mode: + description: Pin sleep mode selection. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x1f + + sprd,control: + description: Control values referring to databook for global control pins. + $ref: /schemas/types.yaml#/definitions/uint32 + + patternProperties: + 'sleep$': + $ref: '#/$defs/pin-node' + unevaluatedProperties: false + + properties: + bias-pull-up: + type: boolean + + sleep-hardware-state: + description: Indicate these configs in sleep related state. + type: boolean + +$defs: + pin-node: + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + properties: + pins: + description: Names of pins to configure. + $ref: /schemas/types.yaml#/definitions/string-array + + bias-disable: + description: Disable pin bias. + type: boolean + + bias-pull-down: + description: Pull down on pin. + type: boolean + + bias-pull-up: true + + input-enable: + description: Enable pin input. + type: boolean + + input-disable: + description: Enable pin output. + type: boolean + + output-high: + description: Set the pin as an output level high. + type: boolean + + output-low: + description: Set the pin as an output level low. + type: boolean + +required: + - compatible + - reg + +examples: + - | + pin_controller: pinctrl@402a0000 { + compatible = "sprd,sc9860-pinctrl"; + reg = <0x402a0000 0x10000>; + + grp1: sd0 { + pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE"; + sprd,control = <0x1>; + }; + + grp2: rfctl_33 { + pins = "SC9860_RFCTL33"; + function = "func2"; + sprd,sleep-mode = <3>; + grp2_sleep_mode: rfctl_33_sleep { + pins = "SC9860_RFCTL33"; + sleep-hardware-state; + output-low; + }; + }; + + grp3: rfctl_misc_20 { + pins = "SC9860_RFCTL20_MISC"; + drive-strength = <10>; + bias-pull-up = <4700>; + grp3_sleep_mode: rfctl_misc_sleep { + pins = "SC9860_RFCTL20_MISC"; + sleep-hardware-state; + bias-pull-up; + }; + }; + }; diff --git a/dts/upstream/Bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/st,stm32-pinctrl.yaml index 961161c2ab6..76d956b4a53 100644 --- a/dts/upstream/Bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/st,stm32-pinctrl.yaml @@ -151,6 +151,8 @@ patternProperties: pinctrl group available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive, output high/low and output speed. + $ref: /schemas/pinctrl/pincfg-node.yaml + properties: pinmux: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -195,26 +197,19 @@ patternProperties: pinmux = ; }; - bias-disable: - type: boolean + bias-disable: true - bias-pull-down: - type: boolean + bias-pull-down: true - bias-pull-up: - type: boolean + bias-pull-up: true - drive-push-pull: - type: boolean + drive-push-pull: true - drive-open-drain: - type: boolean + drive-open-drain: true - output-low: - type: boolean + output-low: true - output-high: - type: boolean + output-high: true slew-rate: description: | @@ -222,15 +217,68 @@ patternProperties: 1: Medium speed 2: Fast speed 3: High speed - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] + minimum: 0 + maximum: 3 + + skew-delay-input-ps: + description: | + IO synchronization skew rate applied to the input path + enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250] + + skew-delay-output-ps: + description: | + IO synchronization latch delay applied to the output path + enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250] + + st,io-sync: + $ref: /schemas/types.yaml#/definitions/string + enum: + - pass-through + - clock inverted + - data on rising edge + - data on falling edge + - data on both edges + description: | + IO synchronization through re-sampling or inversion + "pass-through" - data or clock GPIO pass-through + "clock inverted" - clock GPIO inverted + "data on rising edge" - data GPIO re-sampled on clock rising edge + "data on falling edge" - data GPIO re-sampled on clock falling edge + "data on both edges" - data GPIO re-sampled on both clock edges + default: pass-through required: - pinmux + # Not allowed both skew-delay-input-ps and skew-delay-output-ps + if: + required: + - skew-delay-input-ps + then: + properties: + skew-delay-output-ps: false + allOf: - $ref: pinctrl.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - st,stm32mp257-pinctrl + - st,stm32mp257-z-pinctrl + then: + patternProperties: + '-[0-9]*$': + patternProperties: + '^pins': + properties: + skew-delay-input-ps: false + skew-delay-output-ps: false + st,io-sync: false + required: - compatible - '#address-cells' @@ -311,4 +359,25 @@ examples: pinctrl-names = "default"; }; + - | + #include + //Example 4 skew-delay and st,io-sync + pinctrl: pinctrl@44240000 { + compatible = "st,stm32mp257-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44240000 0xa0400>; + + eth3_rgmii_pins_a: eth3-rgmii-0 { + pins1 { + pinmux = ; + st,io-sync = "data on both edges"; + }; + pins2 { + pinmux = ; + skew-delay-output-ps = <500>; + }; + }; + }; + ... diff --git a/dts/upstream/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml index f3258f2fd3a..3f14eab01c5 100644 --- a/dts/upstream/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml @@ -32,7 +32,6 @@ description: | | | | | | | ------- UART0 UART1 -- - The big MUX in the diagram only has 7 different ways of mapping peripherals on the left to pins on the right. StarFive calls the 7 configurations "signal groups". diff --git a/dts/upstream/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml index ce04d2eadec..0eff0a0ee9e 100644 --- a/dts/upstream/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml +++ b/dts/upstream/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -42,7 +42,6 @@ patternProperties: function: description: Function to mux. - $ref: /schemas/types.yaml#/definitions/string enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, spi0, spi1, spi2, spi3, spi4, spi5, spi6, uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] diff --git a/dts/upstream/Bindings/power/actions,owl-sps.txt b/dts/upstream/Bindings/power/actions,owl-sps.txt deleted file mode 100644 index a3571937b01..00000000000 --- a/dts/upstream/Bindings/power/actions,owl-sps.txt +++ /dev/null @@ -1,21 +0,0 @@ -Actions Semi Owl Smart Power System (SPS) - -Required properties: -- compatible : "actions,s500-sps" for S500 - "actions,s700-sps" for S700 - "actions,s900-sps" for S900 -- reg : Offset and length of the register set for the device. -- #power-domain-cells : Must be 1. - See macros in: - include/dt-bindings/power/owl-s500-powergate.h for S500 - include/dt-bindings/power/owl-s700-powergate.h for S700 - include/dt-bindings/power/owl-s900-powergate.h for S900 - - -Example: - - sps: power-controller@b01b0100 { - compatible = "actions,s500-sps"; - reg = <0xb01b0100 0x100>; - #power-domain-cells = <1>; - }; diff --git a/dts/upstream/Bindings/power/actions,s500-sps.yaml b/dts/upstream/Bindings/power/actions,s500-sps.yaml new file mode 100644 index 00000000000..bb942817b3d --- /dev/null +++ b/dts/upstream/Bindings/power/actions,s500-sps.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/actions,s500-sps.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi Owl Smart Power System (SPS) + +maintainers: + - Andreas Färber + - Manivannan Sadhasivam + +properties: + compatible: + enum: + - actions,s500-sps + - actions,s700-sps + - actions,s900-sps + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + power-controller@b01b0100 { + compatible = "actions,s500-sps"; + reg = <0xb01b0100 0x100>; + #power-domain-cells = <1>; + }; diff --git a/dts/upstream/Bindings/power/mediatek,mt8196-gpufreq.yaml b/dts/upstream/Bindings/power/mediatek,mt8196-gpufreq.yaml new file mode 100644 index 00000000000..b9e43abaf8a --- /dev/null +++ b/dts/upstream/Bindings/power/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Power and Frequency Controller + +maintainers: + - Nicolas Frattaroli + +description: + A special-purpose embedded MCU to control power and frequency of GPU devices + using MediaTek Flexible Graphics integration hardware. + +properties: + $nodename: + pattern: '^power-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: hw-revision + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: core + - const: stack0 + - const: stack1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: FastDVFS control + + mbox-names: + items: + - const: fast-dvfs-event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: fast-dvfs + + memory-region: + items: + - description: phandle to the GPUEB shared memory + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - memory-region + - "#clock-cells" + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + #include + + power-controller@4b09fd00 { + compatible = "mediatek,mt8196-gpufreq"; + reg = <0x4b09fd00 0x80>, + <0x4b800000 0x1000>, + <0x4b860128 0x4>; + reg-names = "gpr", "rpc", "hw-revision"; + clocks = <&topckgen CLK_TOP_MFG_EB>, + <&mfgpll CLK_MFG_AO_MFGPLL>, + <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>, + <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>; + clock-names = "eb", "core", "stack0", "stack1"; + mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>, + <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>, + <&gpueb_mbox 7>; + mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl", + "ccf", "fast-dvfs"; + memory-region = <&gpueb_shared_memory>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; diff --git a/dts/upstream/Bindings/power/mediatek,power-controller.yaml b/dts/upstream/Bindings/power/mediatek,power-controller.yaml index 500d9892158..f8a13928f61 100644 --- a/dts/upstream/Bindings/power/mediatek,power-controller.yaml +++ b/dts/upstream/Bindings/power/mediatek,power-controller.yaml @@ -33,6 +33,9 @@ properties: - mediatek,mt8188-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8196-hwv-hfrp-power-controller + - mediatek,mt8196-hwv-scp-power-controller + - mediatek,mt8196-power-controller - mediatek,mt8365-power-controller '#power-domain-cells': @@ -157,6 +160,7 @@ allOf: contains: enum: - mediatek,mt8183-power-controller + - mediatek,mt8196-power-controller then: properties: access-controllers: diff --git a/dts/upstream/Bindings/power/qcom,rpmpd.yaml b/dts/upstream/Bindings/power/qcom,rpmpd.yaml index af5fef87252..27af5b8aa13 100644 --- a/dts/upstream/Bindings/power/qcom,rpmpd.yaml +++ b/dts/upstream/Bindings/power/qcom,rpmpd.yaml @@ -18,6 +18,7 @@ properties: oneOf: - enum: - qcom,glymur-rpmhpd + - qcom,kaanapali-rpmhpd - qcom,mdm9607-rpmpd - qcom,milos-rpmhpd - qcom,msm8226-rpmpd diff --git a/dts/upstream/Bindings/power/renesas,sysc-rmobile.yaml b/dts/upstream/Bindings/power/renesas,sysc-rmobile.yaml index fba6914ec40..948a9da111d 100644 --- a/dts/upstream/Bindings/power/renesas,sysc-rmobile.yaml +++ b/dts/upstream/Bindings/power/renesas,sysc-rmobile.yaml @@ -45,7 +45,7 @@ properties: const: 0 additionalProperties: - $ref: "#/$defs/pd-node" + $ref: '#/$defs/pd-node' required: - compatible @@ -83,7 +83,7 @@ $defs: - '#power-domain-cells' additionalProperties: - $ref: "#/$defs/pd-node" + $ref: '#/$defs/pd-node' examples: - | diff --git a/dts/upstream/Bindings/power/rockchip,power-controller.yaml b/dts/upstream/Bindings/power/rockchip,power-controller.yaml index a884e49c995..b41db576f95 100644 --- a/dts/upstream/Bindings/power/rockchip,power-controller.yaml +++ b/dts/upstream/Bindings/power/rockchip,power-controller.yaml @@ -46,6 +46,7 @@ properties: - rockchip,rk3576-power-controller - rockchip,rk3588-power-controller - rockchip,rv1126-power-controller + - rockchip,rv1126b-power-controller "#power-domain-cells": const: 1 @@ -126,6 +127,7 @@ $defs: "include/dt-bindings/power/rk3568-power.h" "include/dt-bindings/power/rk3588-power.h" "include/dt-bindings/power/rockchip,rv1126-power.h" + "include/dt-bindings/power/rockchip,rv1126b-power-controller.h" clocks: minItems: 1 diff --git a/dts/upstream/Bindings/power/supply/mt6360_charger.yaml b/dts/upstream/Bindings/power/supply/mt6360_charger.yaml index 4c74cc78729..3e868901925 100644 --- a/dts/upstream/Bindings/power/supply/mt6360_charger.yaml +++ b/dts/upstream/Bindings/power/supply/mt6360_charger.yaml @@ -21,7 +21,6 @@ properties: description: Maximum CHGIN regulation voltage in uV. enum: [ 5500000, 6500000, 11000000, 14500000 ] - usb-otg-vbus-regulator: type: object description: OTG boost regulator. diff --git a/dts/upstream/Bindings/power/supply/richtek,rt9756.yaml b/dts/upstream/Bindings/power/supply/richtek,rt9756.yaml new file mode 100644 index 00000000000..a88bf6cd192 --- /dev/null +++ b/dts/upstream/Bindings/power/supply/richtek,rt9756.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/richtek,rt9756.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT9756 Smart Cap Divider Charger + +maintainers: + - ChiYuan Huang + +description: | + The RT9756/RT9757 is a high efficiency and high charge current charger. + + The efficiency is up to 98.2% when VBAT = 4V, IBAT = 2A in DIV2 mode and 99.1% + when VBAT=4V, IBAT=1A in bypass mode. The maximum charger current is up to 8A + in DIV2 mode and 5A in bypass mode. The device integrates smart cap divider + topology, direct charging mode, external over-voltage protection control, an + input reverse blocking NFET and 2-way regulation, a dual phase charge pump + core, 8-Channel high speed ADCs and USB BC 1.2 detection. + + RT9770 is almost the same with RT9756/57, only BC 1.2 detection function is + removed to shrink the die size. + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + oneOf: + - enum: + - richtek,rt9756 + - richtek,rt9770 + - items: + - enum: + - richtek,rt9757 + - const: richtek,rt9756 + + reg: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + + shunt-resistor-micro-ohms: + description: Battery current sense resistor mounted. + default: 2000 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@6f { + compatible = "richtek,rt9756"; + reg = <0x6f>; + wakeup-source; + interrupts-extended = <&gpio_intc 32 IRQ_TYPE_EDGE_FALLING>; + shunt-resistor-micro-ohms = <5000>; + }; + }; diff --git a/dts/upstream/Bindings/power/supply/samsung,battery.yaml b/dts/upstream/Bindings/power/supply/samsung,battery.yaml index 40292d581b1..fa1ccff043b 100644 --- a/dts/upstream/Bindings/power/supply/samsung,battery.yaml +++ b/dts/upstream/Bindings/power/supply/samsung,battery.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung SDI Batteries maintainers: - - Linus Walleij + - Linus Walleij description: | Samsung SDI (Samsung Digital Interface) batteries are all different versions diff --git a/dts/upstream/Bindings/power/supply/stericsson,ab8500-charger.yaml b/dts/upstream/Bindings/power/supply/stericsson,ab8500-charger.yaml index 994fac12c8d..4f19744844e 100644 --- a/dts/upstream/Bindings/power/supply/stericsson,ab8500-charger.yaml +++ b/dts/upstream/Bindings/power/supply/stericsson,ab8500-charger.yaml @@ -65,7 +65,6 @@ properties: - const: vbus_v - const: usb_charger_c - required: - compatible - monitored-battery diff --git a/dts/upstream/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/dts/upstream/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 1b192e197b1..1197858e431 100644 --- a/dts/upstream/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/dts/upstream/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -55,7 +55,6 @@ properties: resets: maxItems: 1 - allOf: - $ref: pwm.yaml# diff --git a/dts/upstream/Bindings/pwm/thead,th1520-pwm.yaml b/dts/upstream/Bindings/pwm/thead,th1520-pwm.yaml new file mode 100644 index 00000000000..855aec59ac5 --- /dev/null +++ b/dts/upstream/Bindings/pwm/thead,th1520-pwm.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/thead,th1520-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 PWM controller + +maintainers: + - Michal Wilczynski + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: thead,th1520-pwm + + reg: + maxItems: 1 + + clocks: + items: + - description: SoC PWM clock + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + pwm@ffec01c000 { + compatible = "thead,th1520-pwm"; + reg = <0xff 0xec01c000 0x0 0x4000>; + clocks = <&clk CLK_PWM>; + #pwm-cells = <3>; + }; + }; diff --git a/dts/upstream/Bindings/regulator/da9211.txt b/dts/upstream/Bindings/regulator/da9211.txt deleted file mode 100644 index eb871447d50..00000000000 --- a/dts/upstream/Bindings/regulator/da9211.txt +++ /dev/null @@ -1,205 +0,0 @@ -* Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 - Voltage Regulator - -Required properties: -- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213" or "dlg,da9223" - or "dlg,da9214" or "dlg,da9224" or "dlg,da9215" or "dlg,da9225" -- reg: I2C slave address, usually 0x68. -- interrupts: the interrupt outputs of the controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name, with valid - values listed below. The content of each sub-node is defined by the - standard binding for regulators; see regulator.txt. - BUCKA and BUCKB. - -Optional properties: -- enable-gpios: platform gpio for control of BUCKA/BUCKB. -- Any optional property defined in regulator.txt - - regulator-initial-mode and regulator-allowed-modes may be specified using - mode values from dt-bindings/regulator/dlg,da9211-regulator.h - -Example 1) DA9211 - pmic: da9211@68 { - compatible = "dlg,da9211"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 27 0>; - regulator-allowed-modes = ; - }; - }; - }; - -Example 2) DA9212 - pmic: da9212@68 { - compatible = "dlg,da9212"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <5000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 3) DA9213 - pmic: da9213@68 { - compatible = "dlg,da9213"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - }; - }; - -Example 4) DA9223 - pmic: da9223@68 { - compatible = "dlg,da9223"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - }; - }; - -Example 5) DA9214 - pmic: da9214@68 { - compatible = "dlg,da9214"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 6) DA9224 - pmic: da9224@68 { - compatible = "dlg,da9224"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <6000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 7) DA9215 - pmic: da9215@68 { - compatible = "dlg,da9215"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; - -Example 8) DA9225 - pmic: da9225@68 { - compatible = "dlg,da9225"; - reg = <0x68>; - interrupts = <3 27>; - - regulators { - BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 27 0>; - }; - BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 300000>; - regulator-max-microvolt = <1570000>; - regulator-min-microamp = <4000000>; - regulator-max-microamp = <7000000>; - enable-gpios = <&gpio 17 0>; - }; - }; - }; diff --git a/dts/upstream/Bindings/regulator/dlg,da9211.yaml b/dts/upstream/Bindings/regulator/dlg,da9211.yaml new file mode 100644 index 00000000000..4d7e495a6f5 --- /dev/null +++ b/dts/upstream/Bindings/regulator/dlg,da9211.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/dlg,da9211.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: + Dialog Semiconductor DA9211-9215, DA9223-9225 Voltage Regulators + +maintainers: + - Ariel D'Alessandro + +properties: + compatible: + enum: + - dlg,da9211 + - dlg,da9212 + - dlg,da9213 + - dlg,da9214 + - dlg,da9215 + - dlg,da9223 + - dlg,da9224 + - dlg,da9225 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + description: + List of regulators provided by the device + + patternProperties: + "^BUCK([AB])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single BUCK regulator + + properties: + regulator-initial-mode: + items: + enum: [ 1, 2, 3 ] + description: + Defined in include/dt-bindings/regulator/dlg,da9211-regulator.h + + regulator-allowed-modes: + items: + enum: [ 1, 2, 3 ] + description: + Defined in include/dt-bindings/regulator/dlg,da9211-regulator.h + + enable-gpios: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@68 { + compatible = "dlg,da9212"; + reg = <0x68>; + interrupts = <3 27>; + + regulators { + BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <5000000>; + enable-gpios = <&gpio 27 0>; + }; + BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 300000>; + regulator-max-microvolt = <1570000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <5000000>; + enable-gpios = <&gpio 17 0>; + }; + }; + }; + }; + +... diff --git a/dts/upstream/Bindings/regulator/fitipower,fp9931.yaml b/dts/upstream/Bindings/regulator/fitipower,fp9931.yaml new file mode 100644 index 00000000000..c6585e3bacb --- /dev/null +++ b/dts/upstream/Bindings/regulator/fitipower,fp9931.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/fitipower,fp9931.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FitiPower FP9931/JD9930 Power Management Integrated Circuit + +maintainers: + - Andreas Kemnade + +description: + FP9931 is a Power Management IC to provide Power for EPDs with one 3.3V + switch, 2 symmetric LDOs behind 2 DC/DC converters, and one unsymmetric + regulator for a compensation voltage. + JD9930 has in addition some kind of night mode. + +properties: + compatible: + oneOf: + - const: fitipower,fp9931 + + - items: + - const: fitipower,jd9930 + - const: fitipower,fp9931 + + reg: + maxItems: 1 + + enable-gpios: + maxItems: 1 + + pg-gpios: + maxItems: 1 + + en-ts-gpios: + maxItems: 1 + + xon-gpios: + maxItems: 1 + + vin-supply: + description: + Supply for the whole chip. Some vendor kernels and devicetrees + declare this as a non-existing GPIO named "pwrall". + + fitipower,tdly-ms: + description: + Power up soft start delay settings tDLY1-4 bitfields in the + POWERON_DELAY register + items: + - enum: [0, 1, 2, 4] + - enum: [0, 1, 2, 4] + - enum: [0, 1, 2, 4] + - enum: [0, 1, 2, 4] + + regulators: + type: object + additionalProperties: false + patternProperties: + "^(vcom|vposneg|v3p3)$": + unevaluatedProperties: false + type: object + $ref: /schemas/regulator/regulator.yaml + +required: + - compatible + - reg + - pg-gpios + - enable-gpios + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@18 { + compatible = "fitipower,fp9931"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fp9931_gpio>; + vin-supply = <&epd_pmic_supply>; + pg-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + en-ts-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + fitipower,tdly-ms = <2 2 4 4>; + + regulators { + vcom { + regulator-name = "vcom"; + regulator-min-microvolt = <2352840>; + regulator-max-microvolt = <2352840>; + }; + + vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15060000>; + regulator-max-microvolt = <15060000>; + }; + + v3p3 { + regulator-name = "v3p3"; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/regulator/mediatek,mt6316b-regulator.yaml b/dts/upstream/Bindings/regulator/mediatek,mt6316b-regulator.yaml new file mode 100644 index 00000000000..ea595935f4c --- /dev/null +++ b/dts/upstream/Bindings/regulator/mediatek,mt6316b-regulator.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6316b-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6316 BP/VP SPMI PMIC Regulators + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MediaTek MT6316BP/VP PMICs are fully controlled by SPMI interface, both + feature four step-down DC/DC (buck) converters, and provides 2+2 Phases, + joining Buck 1+2 for the first phase, and Buck 3+4 for the second phase. + +properties: + compatible: + const: mediatek,mt6316b-regulator + + reg: + maxItems: 1 + +patternProperties: + "^vbuck(12|34)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + regulator-allowed-modes: + description: | + Allowed Buck regulator operating modes allowed. Valid values below. + 0 - Normal mode with automatic power saving, reducing the switching + frequency when light load conditions are detected + 1 - Forced Continuous Conduction mode (FCCM) for improved voltage + regulation accuracy with constant switching frequency but lower + regulator efficiency + 2 - Forced Low Power mode for improved regulator efficiency, used + when no heavy load is expected, will shut down unnecessary IP + blocks and secondary phases to reduce quiescent current. + This mode does not limit the maximum output current but unless + only a light load is applied, there will be regulation accuracy + and efficiency losses. + minItems: 1 + maxItems: 3 + items: + enum: [ 0, 1, 2 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + spmi { + #address-cells = <2>; + #size-cells = <0>; + + pmic@8 { + compatible = "mediatek,mt6316b-regulator"; + reg = <0x8 SPMI_USID>; + + vbuck12 { + regulator-name = "dvdd_core"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <965000>; + regulator-allowed-modes = <0 1 2>; + regulator-enable-ramp-delay = <256>; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/regulator/mediatek,mt6316c-regulator.yaml b/dts/upstream/Bindings/regulator/mediatek,mt6316c-regulator.yaml new file mode 100644 index 00000000000..186dcd3f11e --- /dev/null +++ b/dts/upstream/Bindings/regulator/mediatek,mt6316c-regulator.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6316c-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6316 CP/HP/KP SPMI PMIC Regulators + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MediaTek MT6316CP/HP/KP PMICs are fully controlled by SPMI interface, + features four step-down DC/DC (buck) converters, and provides 3+1 Phases, + joining Buck 1+2+4 for the first phase, and uses Buck 3 for the second. + +properties: + compatible: + const: mediatek,mt6316c-regulator + + reg: + maxItems: 1 + +patternProperties: + "^vbuck(124|3)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + regulator-allowed-modes: + description: | + Allowed Buck regulator operating modes allowed. Valid values below. + 0 - Normal mode with automatic power saving, reducing the switching + frequency when light load conditions are detected + 1 - Forced Continuous Conduction mode (FCCM) for improved voltage + regulation accuracy with constant switching frequency but lower + regulator efficiency + 2 - Forced Low Power mode for improved regulator efficiency, used + when no heavy load is expected, will shut down unnecessary IP + blocks and secondary phases to reduce quiescent current. + This mode does not limit the maximum output current but unless + only a light load is applied, there will be regulation accuracy + and efficiency losses. + minItems: 1 + maxItems: 3 + items: + enum: [ 0, 1, 2 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + spmi { + #address-cells = <2>; + #size-cells = <0>; + + pmic@6 { + compatible = "mediatek,mt6316c-regulator"; + reg = <0x6 SPMI_USID>; + + vbuck124 { + regulator-name = "dvdd_proc_m"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1277500>; + regulator-allowed-modes = <0 1 2>; + regulator-enable-ramp-delay = <256>; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/regulator/mediatek,mt6316d-regulator.yaml b/dts/upstream/Bindings/regulator/mediatek,mt6316d-regulator.yaml new file mode 100644 index 00000000000..aa9e9ef3b52 --- /dev/null +++ b/dts/upstream/Bindings/regulator/mediatek,mt6316d-regulator.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6316d-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6316 DP/TP SPMI PMIC Regulators + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MediaTek MT6316DP/TP PMICs are fully controlled by SPMI interface, both + feature four step-down DC/DC (buck) converters, and provides a single Phase, + joining Buck 1+2+3+4. + +properties: + compatible: + const: mediatek,mt6316d-regulator + + reg: + maxItems: 1 + + vbuck1234: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + regulator-allowed-modes: + description: | + Allowed Buck regulator operating modes allowed. Valid values below. + 0 - Normal mode with automatic power saving, reducing the switching + frequency when light load conditions are detected + 1 - Forced Continuous Conduction mode (FCCM) for improved voltage + regulation accuracy with constant switching frequency but lower + regulator efficiency + 2 - Forced Low Power mode for improved regulator efficiency, used + when no heavy load is expected, will shut down unnecessary IP + blocks and secondary phases to reduce quiescent current. + This mode does not limit the maximum output current but unless + only a light load is applied, there will be regulation accuracy + and efficiency losses. + minItems: 1 + maxItems: 3 + items: + enum: [ 0, 1, 2 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + spmi { + #address-cells = <2>; + #size-cells = <0>; + + pmic@7 { + compatible = "mediatek,mt6316d-regulator"; + reg = <0x7 SPMI_USID>; + + vbuck1234 { + regulator-name = "dvdd_gpustack"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1277500>; + regulator-allowed-modes = <0 1 2>; + regulator-enable-ramp-delay = <256>; + }; + }; + }; +... diff --git a/dts/upstream/Bindings/regulator/mediatek,mt6363-regulator.yaml b/dts/upstream/Bindings/regulator/mediatek,mt6363-regulator.yaml new file mode 100644 index 00000000000..4f79d4f81d4 --- /dev/null +++ b/dts/upstream/Bindings/regulator/mediatek,mt6363-regulator.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6363-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6363 PMIC Regulators + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MT6363 SPMI PMIC provides 10 BUCK and 25 LDO (Low DropOut) regulators + and can optionally provide overcurrent warnings with one ocp interrupt + for each voltage regulator. + +properties: + compatible: + const: mediatek,mt6363-regulator + + reg: + maxItems: 1 + + vsys-vbuck1-supply: + description: Input supply for vbuck1 + + vsys-vbuck2-supply: + description: Input supply for vbuck2 + + vsys-vbuck3-supply: + description: Input supply for vbuck3 + + vsys-vbuck4-supply: + description: Input supply for vbuck4 + + vsys-vbuck5-supply: + description: Input supply for vbuck5 + + vsys-vbuck6-supply: + description: Input supply for vbuck6 + + vsys-vbuck7-supply: + description: Input supply for vbuck7 + + vsys-vs1-supply: + description: Input supply for vs1 + + vsys-vs2-supply: + description: Input supply for vs2 + + vsys-vs3-supply: + description: Input supply for vs3 + + vs1-ldo1-supply: + description: Input supply for va15, vio0p75, vm18, vrf18, vrf-io18 + + vs1-ldo2-supply: + description: Input supply for vcn15, vio18, vufs18 + + vs2-ldo1-supply: + description: Input supply for vsram-cpub, vsram-cpum, vrf12, vrf13, vufs12 + + vs2-ldo2-supply: + description: Input supply for va12-1, va12-2, vcn13, vsram-cpul + + vs3-ldo1-supply: + description: Input supply for vsram-apu, vsram-digrf, vsram-mdfe + + vs3-ldo2-supply: + description: Input supply for vsram-modem, vrf0p9 + + vsys-ldo1-supply: + description: Input supply for vaux18, vemc, vtref18 + +patternProperties: + "^v(buck[1-7]|s[1-3])$": + description: Buck regulators + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + regulator-allowed-modes: + description: | + Allowed Buck regulator operating modes allowed. Valid values below. + 0 - Normal mode with automatic power saving, reducing the switching + frequency when light load conditions are detected + 1 - Forced Continuous Conduction mode (FCCM) for improved voltage + regulation accuracy with constant switching frequency but lower + regulator efficiency + 2 - Forced Low Power mode for improved regulator efficiency, used + when no heavy load is expected, does not limit the maximum out + current but unless only a light load is applied, there will be + regulation accuracy and efficiency losses. + 3 - Forced Ultra Low Power mode for ultra low load, this greatly + reduces the maximum output power, makes the regulator to be + efficient only for ultra light load, and greatly reduces the + quiescent current (Iq) of the buck. + maxItems: 3 + items: + enum: [ 0, 1, 2, 3 ] + + "^va(12-1|12-2|15)$": + $ref: "#/$defs/ldo-common" + + "^v(aux|m|rf-io|tref)18$": + $ref: "#/$defs/ldo-common" + + "^v(cn13|cn15|emc)$": + $ref: "#/$defs/ldo-common" + + "^vio(0p75|18)$": + $ref: "#/$defs/ldo-common" + + "^vrf(0p9|12|13|18)$": + $ref: "#/$defs/ldo-common" + + "^vsram-(apu|cpub|cpum|cpul|digrf|mdfe|modem)$": + $ref: "#/$defs/ldo-common" + + "^vufs(12|18)$": + $ref: "#/$defs/ldo-common" + +$defs: + ldo-common: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + properties: + regulator-allowed-modes: + description: | + Allowed LDO regulator operating modes allowed. Valid values below. + 0 - Normal mode with automatic power saving, reducing the switching + frequency when light load conditions are detected + 2 - Forced Low Power mode for improved regulator efficiency, used + when no heavy load is expected, does not limit the maximum out + current but unless only a light load is applied, there will be + regulation accuracy and efficiency losses. + maxItems: 2 + items: + enum: [ 0, 2 ] + +required: + - compatible + - reg + +additionalProperties: false diff --git a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml index a5486c36830..ec04adfb9d1 100644 --- a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml +++ b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml @@ -41,6 +41,21 @@ properties: interrupts: maxItems: 1 + inl1-supply: + description: Regulator supply for the INL1 pin group, powering LDOx + + inb13-supply: + description: + Regulator supply for the INB13 pin group, powering BUCK1 and BUCK3. + + inb26-supply: + description: + Regulator supply for the INB26 pin group, powering BUCK2 and BUCK6. + + inb45-supply: + description: + Regulator supply for the INB45 pin group, powering BUCK4 and BUCK5. + regulators: type: object description: | @@ -124,6 +139,30 @@ properties: When WDOG_B signal is asserted a warm reset will be done instead of cold reset. + nxp,pmic-on-req-on-debounce-us: + enum: [ 120, 20000, 100000, 750000 ] + description: Debounce time for PMIC_ON_REQ high. + + nxp,pmic-on-req-off-debounce-us: + enum: [ 120, 2000 ] + description: Debounce time for PMIC_ON_REQ is asserted low + + nxp,power-on-step-ms: + enum: [ 1, 2, 4, 8] + description: Time step configuration during power on sequence + + nxp,power-down-step-ms: + enum: [ 2, 4, 8, 16 ] + description: Time step configuration during power down sequence + + nxp,restart-ms: + enum: [ 250, 500 ] + description: Time to stay off regulators during Cold reset + + npx,pmic-rst-b-debounce-ms: + enum: [ 10, 50, 100, 500, 1000, 2000, 4000, 8000 ] + description: PMIC_RST_B debounce time + required: - compatible - reg diff --git a/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml b/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml index 4c5b0629aa3..58bb0ad5dda 100644 --- a/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml +++ b/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml @@ -8,7 +8,7 @@ title: Qualcomm Technologies, Inc. RPMh Regulators maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: | rpmh-regulator devices support PMIC regulator management via the Voltage @@ -51,10 +51,15 @@ description: | For PM8450, smps1 - smps6, ldo1 - ldo4 For PM8550, smps1 - smps6, ldo1 - ldo17, bob1 - bob2 For PM8998, smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2 + For PMH0101, ldo1 - ldo18, bob1 - bob2 + For PMH0104, smps1 - smps4 + For PMH0110, smps1 - smps10, ldo1 - ldo4 For PMI8998, bob For PMC8380, smps1 - smps8, ldo1 - lodo3 + For PMCX0102, smps1 - smps10, ldo1 - ldo4 For PMR735A, smps1 - smps3, ldo1 - ldo7 For PMR735B, ldo1 - ldo12 + For PMR735D, ldo1 - ldo7 For PMX55, smps1 - smps7, ldo1 - ldo16 For PMX65, smps1 - smps8, ldo1 - ldo21 For PMX75, smps1 - smps10, ldo1 - ldo21 @@ -85,12 +90,17 @@ properties: - qcom,pmc8180-rpmh-regulators - qcom,pmc8180c-rpmh-regulators - qcom,pmc8380-rpmh-regulators + - qcom,pmcx0102-rpmh-regulators - qcom,pmg1110-rpmh-regulators + - qcom,pmh0101-rpmh-regulators + - qcom,pmh0104-rpmh-regulators + - qcom,pmh0110-rpmh-regulators - qcom,pmi8998-rpmh-regulators - qcom,pmm8155au-rpmh-regulators - qcom,pmm8654au-rpmh-regulators - qcom,pmr735a-rpmh-regulators - qcom,pmr735b-rpmh-regulators + - qcom,pmr735d-rpmh-regulators - qcom,pmx55-rpmh-regulators - qcom,pmx65-rpmh-regulators - qcom,pmx75-rpmh-regulators @@ -100,7 +110,7 @@ properties: RPMh resource name suffix used for the regulators found on this PMIC. $ref: /schemas/types.yaml#/definitions/string - enum: [a, b, c, d, e, f, g, h, i, j, k, l, m, n] + pattern: "^[a-n]|[A-N]_E[0-3]+$" qcom,always-wait-for-ack: description: | @@ -246,6 +256,7 @@ allOf: compatible: enum: - qcom,pm8005-rpmh-regulators + - qcom,pmh0104-rpmh-regulators then: patternProperties: "^vdd-s[1-4]-supply$": true @@ -422,6 +433,34 @@ allOf: properties: vdd-s1-supply: true + - if: + properties: + compatible: + enum: + - qcom,pmh0101-rpmh-regulators + then: + properties: + vdd-l1-l4-l10-supply: true + vdd-l2-l13-l14-supply: true + vdd-l3-l11-supply: true + vdd-l5-l16-supply: true + vdd-l6-l7-supply: true + vdd-l8-l9-supply: true + patternProperties: + "^vdd-l(1[2578])-supply$": true + "^vdd-bob[1-2]-supply$": true + + - if: + properties: + compatible: + enum: + - qcom,pmcx0102-rpmh-regulators + - qcom,pmh0110-rpmh-regulators + then: + patternProperties: + "^vdd-l[1-4]-supply$": true + "^vdd-s([1-9]|10)-supply$": true + - if: properties: compatible: @@ -459,6 +498,18 @@ allOf: patternProperties: "^vdd-l([3-6]|9|1[0-2])-supply$": true + - if: + properties: + compatible: + enum: + - qcom,pmr735d-rpmh-regulators + then: + properties: + vdd-l1-l2-l5-supply: true + vdd-l3-l4-supply: true + patternProperties: + "^vdd-l[6-7]-supply$": true + - if: properties: compatible: diff --git a/dts/upstream/Bindings/regulator/richtek,rt6245-regulator.yaml b/dts/upstream/Bindings/regulator/richtek,rt6245-regulator.yaml index b73762e151b..84546fec3b1 100644 --- a/dts/upstream/Bindings/regulator/richtek,rt6245-regulator.yaml +++ b/dts/upstream/Bindings/regulator/richtek,rt6245-regulator.yaml @@ -55,7 +55,6 @@ properties: delay time 0us, 10us, 20us, 40us. If this property is missing then keep in chip default. - richtek,switch-freq-select: $ref: /schemas/types.yaml#/definitions/uint8 enum: [0, 1, 2] diff --git a/dts/upstream/Bindings/remoteproc/qcom,adsp.yaml b/dts/upstream/Bindings/remoteproc/qcom,adsp.yaml index 661c2b425da..137f9502831 100644 --- a/dts/upstream/Bindings/remoteproc/qcom,adsp.yaml +++ b/dts/upstream/Bindings/remoteproc/qcom,adsp.yaml @@ -24,6 +24,7 @@ properties: - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - qcom,sdm660-adsp-pas + - qcom,sdm660-cdsp-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sdm845-slpi-pas @@ -31,9 +32,6 @@ properties: reg: maxItems: 1 - cx-supply: - description: Phandle to the CX regulator - px-supply: description: Phandle to the PX regulator @@ -69,6 +67,8 @@ allOf: - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas + - qcom,sdm660-adsp-pas + - qcom,sdm660-cdsp-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sdm845-slpi-pas @@ -93,6 +93,8 @@ allOf: - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas + - qcom,sdm660-adsp-pas + - qcom,sdm660-cdsp-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sdm845-slpi-pas @@ -103,16 +105,6 @@ allOf: interrupt-names: maxItems: 5 - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8974-adsp-pil - then: - required: - - cx-supply - - if: properties: compatible: @@ -120,8 +112,11 @@ allOf: enum: - qcom,msm8226-adsp-pil - qcom,msm8953-adsp-pil + - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8998-adsp-pas + - qcom,sdm660-adsp-pas + - qcom,sdm660-cdsp-pas then: properties: power-domains: @@ -178,6 +173,7 @@ allOf: - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - qcom,sdm660-adsp-pas + - qcom,sdm660-cdsp-pas then: properties: qcom,qmp: false @@ -187,6 +183,7 @@ examples: #include #include #include + #include adsp { compatible = "qcom,msm8974-adsp-pil"; @@ -204,7 +201,8 @@ examples: clocks = <&rpmcc RPM_CXO_CLK>; clock-names = "xo"; - cx-supply = <&pm8841_s2>; + power-domains = <&rpmpd MSM8974_VDDCX>; + power-domain-names = "cx"; memory-region = <&adsp_region>; diff --git a/dts/upstream/Bindings/remoteproc/qcom,sc8280xp-pas.yaml b/dts/upstream/Bindings/remoteproc/qcom,sc8280xp-pas.yaml index 96d53baf6e0..5dbda3a5504 100644 --- a/dts/upstream/Bindings/remoteproc/qcom,sc8280xp-pas.yaml +++ b/dts/upstream/Bindings/remoteproc/qcom,sc8280xp-pas.yaml @@ -91,9 +91,13 @@ allOf: power-domains: items: - description: NSP power domain + - description: CX power domain + - description: MXC power domain power-domain-names: items: - const: nsp + - const: cx + - const: mxc unevaluatedProperties: false diff --git a/dts/upstream/Bindings/remoteproc/ti,k3-r5f-rproc.yaml b/dts/upstream/Bindings/remoteproc/ti,k3-r5f-rproc.yaml index a492f74a860..a927551356e 100644 --- a/dts/upstream/Bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ b/dts/upstream/Bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -79,7 +79,6 @@ properties: It should be set as 3 (Single-Core mode) which is also the default if omitted. - # R5F Processor Child Nodes: # ========================== @@ -167,7 +166,6 @@ patternProperties: - description: region reserved for firmware image sections additionalItems: true - # Optional properties: # -------------------- # The following properties are optional properties for each of the R5F cores: diff --git a/dts/upstream/Bindings/reset/eswin,eic7700-reset.yaml b/dts/upstream/Bindings/reset/eswin,eic7700-reset.yaml new file mode 100644 index 00000000000..cf2fdb90757 --- /dev/null +++ b/dts/upstream/Bindings/reset/eswin,eic7700-reset.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN EIC7700 SoC reset controller + +maintainers: + - Yifeng Huang + - Xuyang Dong + +description: + The system reset controller can be used to reset various peripheral + controllers in ESWIN eic7700 SoC. + +properties: + compatible: + const: eswin,eic7700-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + reset-controller@51828300 { + compatible = "eswin,eic7700-reset"; + reg = <0x51828300 0x200>; + #reset-cells = <1>; + }; diff --git a/dts/upstream/Bindings/reset/microchip,rst.yaml b/dts/upstream/Bindings/reset/microchip,rst.yaml index f2da0693b05..e190e526f3e 100644 --- a/dts/upstream/Bindings/reset/microchip,rst.yaml +++ b/dts/upstream/Bindings/reset/microchip,rst.yaml @@ -20,9 +20,14 @@ properties: pattern: "^reset-controller@[0-9a-f]+$" compatible: - enum: - - microchip,sparx5-switch-reset - - microchip,lan966x-switch-reset + oneOf: + - enum: + - microchip,sparx5-switch-reset + - microchip,lan966x-switch-reset + - items: + - enum: + - microchip,lan9691-switch-reset + - const: microchip,lan966x-switch-reset reg: items: diff --git a/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index b0b20af1531..c83469a1b37 100644 --- a/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -15,12 +15,14 @@ description: properties: compatible: - items: - - enum: - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L - - const: renesas,rzg2l-usbphy-ctrl + oneOf: + - items: + - enum: + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - const: renesas,rzg2l-usbphy-ctrl + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S reg: maxItems: 1 @@ -48,6 +50,20 @@ properties: $ref: /schemas/regulator/regulator.yaml# unevaluatedProperties: false + renesas,sysc-pwrrdy: + description: + The system controller PWRRDY indicates to the USB PHY if the power supply + is ready. PWRRDY needs to be set during power-on before applying any + other settings. It also needs to be set before powering off the USB. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: + System controller phandle required by USB PHY CTRL driver to set + PWRRDY + - description: Register offset associated with PWRRDY + - description: Register bitmask associated with PWRRDY + required: - compatible - reg @@ -57,6 +73,19 @@ required: - '#reset-cells' - regulator-vbus +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-usbphy-ctrl + then: + required: + - renesas,sysc-pwrrdy + else: + properties: + renesas,sysc-pwrrdy: false + additionalProperties: false examples: diff --git a/dts/upstream/Bindings/reset/thead,th1520-reset.yaml b/dts/upstream/Bindings/reset/thead,th1520-reset.yaml index f2e91d0add7..7b5053c177f 100644 --- a/dts/upstream/Bindings/reset/thead,th1520-reset.yaml +++ b/dts/upstream/Bindings/reset/thead,th1520-reset.yaml @@ -16,7 +16,13 @@ maintainers: properties: compatible: enum: - - thead,th1520-reset + - thead,th1520-reset # Reset controller for VO subsystem + - thead,th1520-reset-ao + - thead,th1520-reset-ap + - thead,th1520-reset-dsp + - thead,th1520-reset-misc + - thead,th1520-reset-vi + - thead,th1520-reset-vp reg: maxItems: 1 diff --git a/dts/upstream/Bindings/reset/ti,sci-reset.yaml b/dts/upstream/Bindings/reset/ti,sci-reset.yaml index 1db08ce9ae2..68640abacd9 100644 --- a/dts/upstream/Bindings/reset/ti,sci-reset.yaml +++ b/dts/upstream/Bindings/reset/ti,sci-reset.yaml @@ -40,7 +40,6 @@ properties: Please see https://software-dl.ti.com/tisci/esd/latest/index.html for protocol documentation for the values to be used for different devices. - additionalProperties: false examples: diff --git a/dts/upstream/Bindings/riscv/anlogic.yaml b/dts/upstream/Bindings/riscv/anlogic.yaml new file mode 100644 index 00000000000..91b1526c99a --- /dev/null +++ b/dts/upstream/Bindings/riscv/anlogic.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/anlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anlogic SoC-based boards + +maintainers: + - Junhui Liu + +description: + Anlogic SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milianke,mlkpai-fs01 + - const: anlogic,dr1v90 + +additionalProperties: true + +... diff --git a/dts/upstream/Bindings/riscv/cpus.yaml b/dts/upstream/Bindings/riscv/cpus.yaml index 153d0dac57f..d733c0bd534 100644 --- a/dts/upstream/Bindings/riscv/cpus.yaml +++ b/dts/upstream/Bindings/riscv/cpus.yaml @@ -48,6 +48,7 @@ properties: - amd,mbv64 - andestech,ax45mp - canaan,k210 + - nuclei,ux900 - sifive,bullet0 - sifive,e5 - sifive,e7 @@ -70,6 +71,7 @@ properties: - enum: - sifive,e51 - sifive,u54-mc + - sifive,x280 - const: sifive,rocket0 - const: riscv - const: riscv # Simulator only diff --git a/dts/upstream/Bindings/riscv/extensions.yaml b/dts/upstream/Bindings/riscv/extensions.yaml index 543ac94718e..5bab356addc 100644 --- a/dts/upstream/Bindings/riscv/extensions.yaml +++ b/dts/upstream/Bindings/riscv/extensions.yaml @@ -217,6 +217,12 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: svrsw60t59b + description: + The Svrsw60t59b extension for providing two more bits[60:59] to + PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved + for SW bits 60:59") of riscv-non-isa/riscv-iommu. + - const: svvptc description: The standard Svvptc supervisor-level extension for @@ -242,6 +248,11 @@ properties: is supported as ratified at commit 5059e0ca641c ("update to ratified") of the riscv-zacas. + - const: zalasr + description: | + The standard Zalasr extension for load-acquire/store-release as frozen + at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. + - const: zalrsc description: | The standard Zalrsc extension for load-reserved/store-conditional as @@ -366,6 +377,20 @@ properties: guarantee on LR/SC sequences, as ratified in commit b1d806605f87 ("Updated to ratified state.") of the riscv profiles specification. + - const: zilsd + description: + The standard Zilsd extension which provides support for aligned + register-pair load and store operations in 32-bit instruction + encodings, as ratified in commit f88abf1 ("Integrating + load/store pair for RV32 with the main manual") of riscv-isa-manual. + + - const: zclsd + description: + The Zclsd extension implements the compressed (16-bit) version of the + Load/Store Pair for RV32. As with Zilsd, this extension was ratified + in commit f88abf1 ("Integrating load/store pair for RV32 with the + main manual") of riscv-isa-manual. + - const: zk description: The standard Zk Standard Scalar cryptography extension as ratified @@ -871,6 +896,16 @@ properties: anyOf: - const: v - const: zve32x + # Zclsd depends on Zilsd and Zca + - if: + contains: + anyOf: + - const: zclsd + then: + contains: + allOf: + - const: zilsd + - const: zca allOf: # Zcf extension does not exist on rv64 @@ -888,6 +923,18 @@ allOf: not: contains: const: zcf + # Zilsd extension does not exist on rv64 + - if: + properties: + riscv,isa-base: + contains: + const: rv64i + then: + properties: + riscv,isa-extensions: + not: + contains: + const: zilsd additionalProperties: true ... diff --git a/dts/upstream/Bindings/riscv/spacemit.yaml b/dts/upstream/Bindings/riscv/spacemit.yaml index c56b62a6299..9c49482002f 100644 --- a/dts/upstream/Bindings/riscv/spacemit.yaml +++ b/dts/upstream/Bindings/riscv/spacemit.yaml @@ -22,6 +22,8 @@ properties: - enum: - bananapi,bpi-f3 - milkv,jupiter + - spacemit,musepi-pro + - xunlong,orangepi-r2s - xunlong,orangepi-rv2 - const: spacemit,k1 diff --git a/dts/upstream/Bindings/riscv/starfive.yaml b/dts/upstream/Bindings/riscv/starfive.yaml index 04510341a71..9253aab2151 100644 --- a/dts/upstream/Bindings/riscv/starfive.yaml +++ b/dts/upstream/Bindings/riscv/starfive.yaml @@ -33,8 +33,15 @@ properties: - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b + - xunlong,orangepi-rv - const: starfive,jh7110 + - items: + - enum: + - starfive,visionfive-2-lite + - starfive,visionfive-2-lite-emmc + - const: starfive,jh7110s + additionalProperties: true ... diff --git a/dts/upstream/Bindings/riscv/tenstorrent.yaml b/dts/upstream/Bindings/riscv/tenstorrent.yaml new file mode 100644 index 00000000000..e15359b2aab --- /dev/null +++ b/dts/upstream/Bindings/riscv/tenstorrent.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/tenstorrent.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tenstorrent SoC-based boards + +maintainers: + - Drew Fustini + - Joel Stanley + +description: + Tenstorrent SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Tenstorrent Blackhole PCIe card + items: + - const: tenstorrent,blackhole-card + - const: tenstorrent,blackhole + +additionalProperties: true + +... diff --git a/dts/upstream/Bindings/rng/inside-secure,safexcel-eip76.yaml b/dts/upstream/Bindings/rng/inside-secure,safexcel-eip76.yaml index 0877eb44f9e..f501fc7691c 100644 --- a/dts/upstream/Bindings/rng/inside-secure,safexcel-eip76.yaml +++ b/dts/upstream/Bindings/rng/inside-secure,safexcel-eip76.yaml @@ -44,7 +44,6 @@ properties: - const: core - const: reg - allOf: - if: properties: @@ -58,7 +57,6 @@ allOf: required: - interrupts - required: - compatible - reg diff --git a/dts/upstream/Bindings/rng/intel,ixp46x-rng.yaml b/dts/upstream/Bindings/rng/intel,ixp46x-rng.yaml index 9f7590ce6b3..146593a669d 100644 --- a/dts/upstream/Bindings/rng/intel,ixp46x-rng.yaml +++ b/dts/upstream/Bindings/rng/intel,ixp46x-rng.yaml @@ -12,7 +12,7 @@ description: | 32 bit random number. maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/rng/microchip,pic32-rng.txt b/dts/upstream/Bindings/rng/microchip,pic32-rng.txt deleted file mode 100644 index c6d1003befb..00000000000 --- a/dts/upstream/Bindings/rng/microchip,pic32-rng.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Microchip PIC32 Random Number Generator - -The PIC32 RNG provides a pseudo random number generator which can be seeded by -another true random number generator. - -Required properties: -- compatible : should be "microchip,pic32mzda-rng" -- reg : Specifies base physical address and size of the registers. -- clocks: clock phandle. - -Example: - - rng: rng@1f8e6000 { - compatible = "microchip,pic32mzda-rng"; - reg = <0x1f8e6000 0x1000>; - clocks = <&PBCLK5>; - }; diff --git a/dts/upstream/Bindings/rng/microchip,pic32-rng.yaml b/dts/upstream/Bindings/rng/microchip,pic32-rng.yaml new file mode 100644 index 00000000000..1f6f6fb81dd --- /dev/null +++ b/dts/upstream/Bindings/rng/microchip,pic32-rng.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/microchip,pic32-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 Random Number Generator + +description: | + The PIC32 RNG provides a pseudo random number generator which can be seeded + by another true random number generator. + +maintainers: + - Joshua Henderson + +properties: + compatible: + enum: + - microchip,pic32mzda-rng + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + rng: rng@1f8e6000 { + compatible = "microchip,pic32mzda-rng"; + reg = <0x1f8e6000 0x1000>; + clocks = <&PBCLK5>; + }; diff --git a/dts/upstream/Bindings/rtc/andestech,atcrtc100.yaml b/dts/upstream/Bindings/rtc/andestech,atcrtc100.yaml new file mode 100644 index 00000000000..ec0a736793c --- /dev/null +++ b/dts/upstream/Bindings/rtc/andestech,atcrtc100.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/andestech,atcrtc100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes ATCRTC100 Real-Time Clock + +maintainers: + - CL Wang + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - andestech,atcrtc100 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Periodic timekeeping interrupt + - description: RTC alarm interrupt + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + rtc@f0300000 { + compatible = "andestech,atcrtc100"; + reg = <0xf0300000 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, <2 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/dts/upstream/Bindings/rtc/apple,smc-rtc.yaml b/dts/upstream/Bindings/rtc/apple,smc-rtc.yaml new file mode 100644 index 00000000000..607b610665a --- /dev/null +++ b/dts/upstream/Bindings/rtc/apple,smc-rtc.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/apple,smc-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SMC RTC + +description: + Apple Silicon Macs (M1, etc.) have an RTC that is part of the PMU IC, + but most of the PMU functionality is abstracted out by the SMC. + An additional RTC offset stored inside NVMEM is required to compute + the current date/time. + +maintainers: + - Sven Peter + +properties: + compatible: + const: apple,smc-rtc + + nvmem-cells: + items: + - description: 48bit RTC offset, specified in 32768 (2^15) Hz clock ticks + + nvmem-cell-names: + items: + - const: rtc_offset + +required: + - compatible + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false diff --git a/dts/upstream/Bindings/rtc/faraday,ftrtc010.yaml b/dts/upstream/Bindings/rtc/faraday,ftrtc010.yaml index b1c1a0e2131..2b1215b4958 100644 --- a/dts/upstream/Bindings/rtc/faraday,ftrtc010.yaml +++ b/dts/upstream/Bindings/rtc/faraday,ftrtc010.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FTRTC010 Real Time Clock maintainers: - - Linus Walleij + - Linus Walleij description: | This RTC appears in for example the Storlink Gemini family of SoCs. diff --git a/dts/upstream/Bindings/rtc/nvidia,vrs-10.yaml b/dts/upstream/Bindings/rtc/nvidia,vrs-10.yaml new file mode 100644 index 00000000000..c7dbc8b83c0 --- /dev/null +++ b/dts/upstream/Bindings/rtc/nvidia,vrs-10.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nvidia,vrs-10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Voltage Regulator Specification Real Time Clock + +maintainers: + - Shubhi Garg + +description: + NVIDIA VRS-10 (Voltage Regulator Specification) is a Power Management IC + (PMIC) that implements a power sequencing solution with I2C interface. + The device includes a real-time clock (RTC) with 32kHz clock output and + backup battery support, alarm functionality for system wake-up from + suspend and shutdown states, OTP memory for power sequencing configuration, + and an interrupt controller for managing VRS events. + +properties: + compatible: + const: nvidia,vrs-10 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@3c { + compatible = "nvidia,vrs-10"; + reg = <0x3c>; + interrupt-parent = <&pmc>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; diff --git a/dts/upstream/Bindings/rtc/renesas,rz-rtca3.yaml b/dts/upstream/Bindings/rtc/renesas,rz-rtca3.yaml index e70eeb66aa6..ccb1638c35b 100644 --- a/dts/upstream/Bindings/rtc/renesas,rz-rtca3.yaml +++ b/dts/upstream/Bindings/rtc/renesas,rz-rtca3.yaml @@ -9,14 +9,12 @@ title: Renesas RTCA-3 Real Time Clock maintainers: - Claudiu Beznea -allOf: - - $ref: rtc.yaml# - properties: compatible: items: - enum: - renesas,r9a08g045-rtca3 # RZ/G3S + - renesas,r9a09g057-rtca3 # RZ/V2H - const: renesas,rz-rtca3 reg: @@ -48,8 +46,12 @@ properties: maxItems: 1 resets: - items: - - description: VBATTB module reset + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 required: - compatible @@ -61,6 +63,39 @@ required: - power-domains - resets +allOf: + - $ref: rtc.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-rtca3 + then: + properties: + resets: + items: + - description: VBATTB module reset + reset-names: + const: vbattb + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-rtca3 + then: + properties: + resets: + items: + - description: RTC reset + - description: Reset for the RTEST registers + reset-names: + items: + - const: rtc + - const: rtest + required: + - reset-names + additionalProperties: false examples: @@ -81,4 +116,5 @@ examples: clock-names = "bus", "counter"; power-domains = <&cpg>; resets = <&cpg R9A08G045_VBAT_BRESETN>; + reset-names = "vbattb"; }; diff --git a/dts/upstream/Bindings/serial/8250.yaml b/dts/upstream/Bindings/serial/8250.yaml index b243afa69a1..167ddcbd880 100644 --- a/dts/upstream/Bindings/serial/8250.yaml +++ b/dts/upstream/Bindings/serial/8250.yaml @@ -125,6 +125,8 @@ properties: - nxp,lpc1850-uart - opencores,uart16550-rtlsvn105 - ti,da830-uart + - loongson,ls2k0500-uart + - loongson,ls2k1500-uart - const: ns16550a - items: - enum: @@ -169,6 +171,18 @@ properties: - nvidia,tegra194-uart - nvidia,tegra234-uart - const: nvidia,tegra20-uart + - items: + - enum: + - loongson,ls2k1000-uart + - const: loongson,ls2k0500-uart + - const: ns16550a + - items: + - enum: + - loongson,ls3a5000-uart + - loongson,ls3a6000-uart + - loongson,ls2k2000-uart + - const: loongson,ls2k1500-uart + - const: ns16550a reg: maxItems: 1 diff --git a/dts/upstream/Bindings/serial/qcom,msm-uart.yaml b/dts/upstream/Bindings/serial/qcom,msm-uart.yaml index ea6abfe2d95..bc2e4875480 100644 --- a/dts/upstream/Bindings/serial/qcom,msm-uart.yaml +++ b/dts/upstream/Bindings/serial/qcom,msm-uart.yaml @@ -8,7 +8,7 @@ title: Qualcomm MSM SoC Serial UART maintainers: - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The MSM serial UART hardware is designed for low-speed use cases where a diff --git a/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml b/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml index e0fa363ad7e..788ef5c1c44 100644 --- a/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml +++ b/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml @@ -9,7 +9,7 @@ title: Qualcomm MSM Serial UARTDM maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: | The MSM serial UARTDM hardware is designed for high-speed use cases where the diff --git a/dts/upstream/Bindings/serial/renesas,rsci.yaml b/dts/upstream/Bindings/serial/renesas,rsci.yaml index f50d8e02f47..6b1f827a335 100644 --- a/dts/upstream/Bindings/serial/renesas,rsci.yaml +++ b/dts/upstream/Bindings/serial/renesas,rsci.yaml @@ -54,8 +54,6 @@ properties: power-domains: maxItems: 1 - uart-has-rtscts: false - required: - compatible - reg diff --git a/dts/upstream/Bindings/serial/samsung_uart.yaml b/dts/upstream/Bindings/serial/samsung_uart.yaml index 1a1f991d536..75ac2a08f25 100644 --- a/dts/upstream/Bindings/serial/samsung_uart.yaml +++ b/dts/upstream/Bindings/serial/samsung_uart.yaml @@ -48,7 +48,9 @@ properties: - const: samsung,exynos850-uart - items: - enum: + - axis,artpec9-uart - samsung,exynos7870-uart + - samsung,exynos8890-uart - const: samsung,exynos8895-uart reg: diff --git a/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml b/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml index cb9da6c97af..6efe43089a7 100644 --- a/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml +++ b/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart @@ -64,6 +65,7 @@ properties: - rockchip,rk3328-uart - rockchip,rk3368-uart - rockchip,rk3399-uart + - rockchip,rk3506-uart - rockchip,rk3528-uart - rockchip,rk3562-uart - rockchip,rk3568-uart diff --git a/dts/upstream/Bindings/slimbus/qcom,slim-ngd.yaml b/dts/upstream/Bindings/slimbus/qcom,slim-ngd.yaml index abf61c15246..27a92b79c72 100644 --- a/dts/upstream/Bindings/slimbus/qcom,slim-ngd.yaml +++ b/dts/upstream/Bindings/slimbus/qcom,slim-ngd.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SoC SLIMBus Non Generic Device (NGD) Controller maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla description: diff --git a/dts/upstream/Bindings/slimbus/slimbus.yaml b/dts/upstream/Bindings/slimbus/slimbus.yaml index 89017d9cda1..5a941610ce4 100644 --- a/dts/upstream/Bindings/slimbus/slimbus.yaml +++ b/dts/upstream/Bindings/slimbus/slimbus.yaml @@ -75,16 +75,22 @@ examples: #size-cells = <1>; ranges; - slim@28080000 { + controller@28080000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x091c0000 0x2c000>; interrupts = ; - #address-cells = <2>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; #size-cells = <0>; - - audio-codec@1,0 { + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + codec@1,0 { compatible = "slim217,1a0"; reg = <1 0>; + }; }; + }; }; - }; diff --git a/dts/upstream/Bindings/soc/bcm/brcm,bcm2835-pm.yaml b/dts/upstream/Bindings/soc/bcm/brcm,bcm2835-pm.yaml index e28ef198a80..039c8e4a4c5 100644 --- a/dts/upstream/Bindings/soc/bcm/brcm,bcm2835-pm.yaml +++ b/dts/upstream/Bindings/soc/bcm/brcm,bcm2835-pm.yaml @@ -13,23 +13,21 @@ description: | maintainers: - Nicolas Saenz Julienne -allOf: - - $ref: /schemas/watchdog/watchdog.yaml# - properties: compatible: items: - enum: - brcm,bcm2835-pm - brcm,bcm2711-pm + - brcm,bcm2712-pm - const: brcm,bcm2835-pm-wdt reg: - minItems: 2 + minItems: 1 maxItems: 3 reg-names: - minItems: 2 + minItems: 1 items: - const: pm - const: asb @@ -62,7 +60,35 @@ required: - reg - "#power-domain-cells" - "#reset-cells" - - clocks + +allOf: + - $ref: /schemas/watchdog/watchdog.yaml# + + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm2835-pm + - brcm,bcm2711-pm + then: + required: + - clocks + + properties: + reg: + minItems: 2 + + reg-names: + minItems: 2 + + else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 additionalProperties: false diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml index cf0f38dbbe0..2c06d869fdb 100644 --- a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml +++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml @@ -30,7 +30,6 @@ properties: $ref: /schemas/types.yaml#/definitions/string enum: [host, slave] - patternProperties: '^data\-only@[a-f0-9]+$': type: object diff --git a/dts/upstream/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/dts/upstream/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml index b77ce8c6a93..721a67e84c1 100644 --- a/dts/upstream/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml +++ b/dts/upstream/Bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -51,6 +51,22 @@ properties: type: object $ref: /schemas/mux/reg-mux.yaml +patternProperties: + "^ipu[12]_csi[01]_mux$": + type: object + $ref: /schemas/media/video-mux.yaml + +allOf: + - if: + properties: + compatible: + not: + contains: + const: fsl,imx6q-iomuxc-gpr + then: + patternProperties: + '^ipu[12]_csi[01]_mux$': false + additionalProperties: false required: diff --git a/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml b/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml index a10326a9683..5267cfe9257 100644 --- a/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml +++ b/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml @@ -91,7 +91,6 @@ allOf: required: - clocks - required: - compatible - reg diff --git a/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml b/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml index 54c0cd64d30..e7c4a3984c6 100644 --- a/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml @@ -52,6 +52,7 @@ properties: - items: - enum: - mediatek,mt8188-pwrap + - mediatek,mt8189-pwrap - const: mediatek,mt8195-pwrap - const: syscon diff --git a/dts/upstream/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/dts/upstream/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index 2c7275c4503..668b943db17 100644 --- a/dts/upstream/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/dts/upstream/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -57,7 +57,7 @@ properties: const: 0 patternProperties: - "^timer@[0-2]$": + '^timer@[0-2]$': description: The timer block channels that are used as timers or counters. type: object additionalProperties: false @@ -80,7 +80,7 @@ patternProperties: - compatible - reg - "^pwm@[0-2]$": + '^pwm@[0-2]$': description: The timer block channels that are used as PWMs. $ref: /schemas/pwm/pwm.yaml# type: object @@ -92,7 +92,7 @@ patternProperties: TCB channel to use for this PWM. enum: [ 0, 1, 2 ] - "#pwm-cells": + '#pwm-cells': description: The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -101,11 +101,10 @@ patternProperties: required: - compatible - reg - - "#pwm-cells" + - '#pwm-cells' additionalProperties: false - allOf: - if: properties: diff --git a/dts/upstream/Bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml b/dts/upstream/Bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 00000000000..39987f72241 --- /dev/null +++ b/dts/upstream/Bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region + +maintainers: + - Conor Dooley + +description: + An wide assortment of registers that control elements of the MSS on PolarFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list + of PolarFire clock/reset IDs. + const: 1 + + pinctrl@200: + type: object + $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@20002000 { + compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg = <0x20002000 0x1000>; + #reset-cells = <1>; + }; + diff --git a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml index 851a1260f8d..c5c1bac2db0 100644 --- a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -25,6 +25,8 @@ properties: compatible: items: - enum: + - qcom,glymur-aoss-qmp + - qcom,kaanapali-aoss-qmp - qcom,milos-aoss-qmp - qcom,qcs615-aoss-qmp - qcom,qcs8300-aoss-qmp diff --git a/dts/upstream/Bindings/soc/qcom/qcom,gsbi.yaml b/dts/upstream/Bindings/soc/qcom/qcom,gsbi.yaml index c33704333e4..d9f6d34a61c 100644 --- a/dts/upstream/Bindings/soc/qcom/qcom,gsbi.yaml +++ b/dts/upstream/Bindings/soc/qcom/qcom,gsbi.yaml @@ -9,7 +9,7 @@ title: Qualcomm General Serial Bus Interface (GSBI) maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The GSBI controller is modeled as a node with zero or more child nodes, each diff --git a/dts/upstream/Bindings/soc/qcom/qcom,smd.yaml b/dts/upstream/Bindings/soc/qcom/qcom,smd.yaml index d9fabefc814..b667f4afdb5 100644 --- a/dts/upstream/Bindings/soc/qcom/qcom,smd.yaml +++ b/dts/upstream/Bindings/soc/qcom/qcom,smd.yaml @@ -9,7 +9,7 @@ title: Qualcomm Shared Memory Driver maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The Qualcomm Shared Memory Driver is a FIFO based communication channel for diff --git a/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml b/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml index 1ba1d419e83..f9127682285 100644 --- a/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml +++ b/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml @@ -9,7 +9,7 @@ title: Qualcomm Shared Memory Point 2 Point maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The Shared Memory Point to Point (SMP2P) protocol facilitates communication diff --git a/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml b/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml index 4900215f26a..67d4a7cb9ee 100644 --- a/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml +++ b/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml @@ -9,7 +9,7 @@ title: Qualcomm Shared Memory State Machine maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The Shared Memory State Machine facilitates broadcasting of single bit state diff --git a/dts/upstream/Bindings/soc/rockchip/grf.yaml b/dts/upstream/Bindings/soc/rockchip/grf.yaml index dca5e27b823..0b8e3294c83 100644 --- a/dts/upstream/Bindings/soc/rockchip/grf.yaml +++ b/dts/upstream/Bindings/soc/rockchip/grf.yaml @@ -317,7 +317,6 @@ allOf: properties: clocks: false - examples: - | #include diff --git a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml index f0fb24156da..6de47489ee4 100644 --- a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml +++ b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml @@ -55,6 +55,7 @@ properties: - samsung,exynos2200-pmu - samsung,exynos7870-pmu - samsung,exynos7885-pmu + - samsung,exynos8890-pmu - samsung,exynos8895-pmu - samsung,exynos9810-pmu - samsung,exynos990-pmu @@ -172,6 +173,7 @@ allOf: - samsung,exynos5250-pmu - samsung,exynos5420-pmu - samsung,exynos5433-pmu + - samsung,exynos7870-pmu then: properties: mipi-phy: true diff --git a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml index d8b302f9754..5e1e155510b 100644 --- a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -15,7 +15,9 @@ properties: - items: - enum: - google,gs101-apm-sysreg + - google,gs101-hsi0-sysreg - google,gs101-hsi2-sysreg + - google,gs101-misc-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos2200-cmgp-sysreg @@ -26,10 +28,14 @@ properties: - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg + - samsung,exynos7870-cam0-sysreg + - samsung,exynos7870-disp-sysreg - samsung,exynos8895-fsys0-sysreg - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynos990-peric0-sysreg + - samsung,exynos990-peric1-sysreg - samsung,exynosautov920-hsi2-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg @@ -73,6 +79,9 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -83,7 +92,9 @@ allOf: compatible: contains: enum: + - google,gs101-hsi0-sysreg - google,gs101-hsi2-sysreg + - google,gs101-misc-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos850-cmgp-sysreg @@ -93,6 +104,8 @@ allOf: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynos990-peric0-sysreg + - samsung,exynos990-peric1-sysreg then: required: - clocks @@ -100,6 +113,16 @@ allOf: properties: clocks: false + - if: + properties: + compatible: + not: + contains: + pattern: "^google,gs101-[^-]+-sysreg$" + then: + properties: + power-domains: false + additionalProperties: false examples: diff --git a/dts/upstream/Bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml b/dts/upstream/Bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml new file mode 100644 index 00000000000..b2e8e0cb4ea --- /dev/null +++ b/dts/upstream/Bindings/soc/sophgo/sophgo,cv1800b-top-syscon.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,cv1800b-top-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV18XX/SG200X SoC top system controller + +maintainers: + - Inochi Amaoto + +description: + The Sophgo CV18XX/SG200X SoC top misc system controller provides + register access to configure related modules. + +properties: + compatible: + oneOf: + - items: + - const: sophgo,cv1800b-top-syscon + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + dma-router@154: + $ref: /schemas/dma/sophgo,cv1800b-dmamux.yaml# + unevaluatedProperties: false + + phy@48: + $ref: /schemas/phy/sophgo,cv1800b-usb2-phy.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + syscon@3000000 { + compatible = "sophgo,cv1800b-top-syscon", "syscon", "simple-mfd"; + reg = <0x03000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + phy@48 { + compatible = "sophgo,cv1800b-usb2-phy"; + reg = <0x48 0x4>; + #phy-cells = <0>; + clocks = <&clk CLK_USB_125M>, + <&clk CLK_USB_33K>, + <&clk CLK_USB_12M>; + clock-names = "app", "stb", "lpm"; + resets = <&rst 58>; + }; + + dma-router@154 { + compatible = "sophgo,cv1800b-dmamux"; + reg = <0x154 0x8>, <0x298 0x4>; + #dma-cells = <2>; + dma-masters = <&dmac>; + }; + }; + +... diff --git a/dts/upstream/Bindings/soc/tegra/nvidia,tegra20-pmc.yaml b/dts/upstream/Bindings/soc/tegra/nvidia,tegra20-pmc.yaml index 7140c312d89..f516960dbbe 100644 --- a/dts/upstream/Bindings/soc/tegra/nvidia,tegra20-pmc.yaml +++ b/dts/upstream/Bindings/soc/tegra/nvidia,tegra20-pmc.yaml @@ -133,12 +133,12 @@ properties: property. The supported-hw is a bitfield indicating SoC speedo or process ID mask. - "#power-domain-cells": + '#power-domain-cells': const: 0 required: - operating-points-v2 - - "#power-domain-cells" + - '#power-domain-cells' i2c-thermtrip: type: object @@ -220,7 +220,7 @@ properties: xusbc USB Partition C Tegra114/124/210 patternProperties: - "^[a-z0-9]+$": + '^[a-z0-9]+$': type: object additionalProperties: false properties: @@ -365,9 +365,9 @@ allOf: additionalProperties: false dependencies: - nvidia,suspend-mode: ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] - nvidia,core-pwr-off-time: ["nvidia,core-pwr-good-time"] - nvidia,cpu-pwr-off-time: ["nvidia,cpu-pwr-good-time"] + nvidia,suspend-mode: ['nvidia,core-pwr-off-time', 'nvidia,cpu-pwr-off-time'] + nvidia,core-pwr-off-time: ['nvidia,core-pwr-good-time'] + nvidia,cpu-pwr-off-time: ['nvidia,cpu-pwr-good-time'] examples: - | diff --git a/dts/upstream/Bindings/soc/ti/ti,pruss.yaml b/dts/upstream/Bindings/soc/ti/ti,pruss.yaml index b5336bcbfb0..d97e88433d2 100644 --- a/dts/upstream/Bindings/soc/ti/ti,pruss.yaml +++ b/dts/upstream/Bindings/soc/ti/ti,pruss.yaml @@ -11,7 +11,6 @@ maintainers: - Suman Anna description: |+ - The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC @@ -44,7 +43,6 @@ description: |+ integration within the IP and the SoC. These nodes are described in the following sections. - PRU-ICSS Node ============== Each PRU-ICSS instance is represented as its own node with the individual PRU @@ -54,7 +52,6 @@ description: |+ See ../../mfd/syscon.yaml for generic SysCon binding details. - properties: $nodename: pattern: "^(pruss|icssg)@[0-9a-f]+$" diff --git a/dts/upstream/Bindings/sound/adi,adau1372.yaml b/dts/upstream/Bindings/sound/adi,adau1372.yaml index ea62e51aba9..9a7ff50a0a2 100644 --- a/dts/upstream/Bindings/sound/adi,adau1372.yaml +++ b/dts/upstream/Bindings/sound/adi,adau1372.yaml @@ -4,7 +4,6 @@ $id: http://devicetree.org/schemas/sound/adi,adau1372.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# - title: Analog Devices ADAU1372 CODEC maintainers: diff --git a/dts/upstream/Bindings/sound/adi,adau7002.yaml b/dts/upstream/Bindings/sound/adi,adau7002.yaml index fcca0fde7d8..7858f3f8ec2 100644 --- a/dts/upstream/Bindings/sound/adi,adau7002.yaml +++ b/dts/upstream/Bindings/sound/adi,adau7002.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski allOf: - $ref: dai-common.yaml# diff --git a/dts/upstream/Bindings/sound/adi,adau7118.yaml b/dts/upstream/Bindings/sound/adi,adau7118.yaml index 12f60507aed..11f59c29b57 100644 --- a/dts/upstream/Bindings/sound/adi,adau7118.yaml +++ b/dts/upstream/Bindings/sound/adi,adau7118.yaml @@ -4,7 +4,6 @@ $id: http://devicetree.org/schemas/sound/adi,adau7118.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# - title: Analog Devices ADAU7118 8 Channel PDM to I2S/TDM Converter maintainers: diff --git a/dts/upstream/Bindings/sound/adi,max98363.yaml b/dts/upstream/Bindings/sound/adi,max98363.yaml deleted file mode 100644 index c388cda5601..00000000000 --- a/dts/upstream/Bindings/sound/adi,max98363.yaml +++ /dev/null @@ -1,60 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/adi,max98363.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Analog Devices MAX98363 SoundWire Amplifier - -maintainers: - - Ryan Lee - -description: - The MAX98363 is a SoundWire input Class D mono amplifier that - supports MIPI SoundWire v1.2-compatible digital interface for - audio and control data. - SoundWire peripheral device ID of MAX98363 is 0x3*019f836300 - where * is the peripheral device unique ID decoded from pin. - It supports up to 10 peripheral devices(0x0 to 0x9). - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: sdw3019f836300 - - reg: - maxItems: 1 - - '#sound-dai-cells': - const: 0 - -required: - - compatible - - reg - - "#sound-dai-cells" - -unevaluatedProperties: false - -examples: - - | - soundwire@3250000 { - #address-cells = <2>; - #size-cells = <0>; - reg = <0x3250000 0x2000>; - - speaker@0,0 { - compatible = "sdw3019f836300"; - reg = <0 0>; - #sound-dai-cells = <0>; - sound-name-prefix = "Speaker Left"; - }; - - speaker@0,1 { - compatible = "sdw3019f836300"; - reg = <0 1>; - #sound-dai-cells = <0>; - sound-name-prefix = "Speaker Right"; - }; - }; diff --git a/dts/upstream/Bindings/sound/adi,ssm2602.txt b/dts/upstream/Bindings/sound/adi,ssm2602.txt deleted file mode 100644 index 3b3302fe399..00000000000 --- a/dts/upstream/Bindings/sound/adi,ssm2602.txt +++ /dev/null @@ -1,19 +0,0 @@ -Analog Devices SSM2602, SSM2603 and SSM2604 I2S audio CODEC devices - -SSM2602 support both I2C and SPI as the configuration interface, -the selection is made by the MODE strap-in pin. -SSM2603 and SSM2604 only support I2C as the configuration interface. - -Required properties: - - - compatible : One of "adi,ssm2602", "adi,ssm2603" or "adi,ssm2604" - - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - - Example: - - ssm2602: ssm2602@1a { - compatible = "adi,ssm2602"; - reg = <0x1a>; - }; diff --git a/dts/upstream/Bindings/sound/adi,ssm3515.yaml b/dts/upstream/Bindings/sound/adi,ssm3515.yaml deleted file mode 100644 index 144450df586..00000000000 --- a/dts/upstream/Bindings/sound/adi,ssm3515.yaml +++ /dev/null @@ -1,49 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/adi,ssm3515.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Analog Devices SSM3515 Audio Amplifier - -maintainers: - - Martin Povišer - -description: | - SSM3515 is a mono Class-D audio amplifier with digital input. - - https://www.analog.com/media/en/technical-documentation/data-sheets/SSM3515.pdf - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - enum: - - adi,ssm3515 - - reg: - maxItems: 1 - - '#sound-dai-cells': - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - codec@14 { - compatible = "adi,ssm3515"; - reg = <0x14>; - #sound-dai-cells = <0>; - sound-name-prefix = "Left Tweeter"; - }; - }; diff --git a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-i2s.yaml b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-i2s.yaml index 739114fb654..ae86cb5f0a7 100644 --- a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -33,7 +33,9 @@ properties: - const: allwinner,sun50i-h6-i2s - const: allwinner,sun50i-r329-i2s - items: - - const: allwinner,sun20i-d1-i2s + - enum: + - allwinner,sun20i-d1-i2s + - allwinner,sun55i-a523-i2s - const: allwinner,sun50i-r329-i2s reg: diff --git a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml index aa32dc950e7..1d089ba70f4 100644 --- a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml +++ b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml @@ -23,6 +23,7 @@ properties: - const: allwinner,sun8i-h3-spdif - const: allwinner,sun50i-h6-spdif - const: allwinner,sun50i-h616-spdif + - const: allwinner,sun55i-a523-spdif - items: - const: allwinner,sun8i-a83t-spdif - const: allwinner,sun8i-h3-spdif @@ -37,14 +38,12 @@ properties: maxItems: 1 clocks: - items: - - description: Bus Clock - - description: Module Clock + minItems: 2 + maxItems: 3 clock-names: - items: - - const: apb - - const: spdif + minItems: 2 + maxItems: 3 # Even though it only applies to subschemas under the conditionals, # not listing them here will trigger a warning because of the @@ -65,6 +64,7 @@ allOf: - allwinner,sun8i-h3-spdif - allwinner,sun50i-h6-spdif - allwinner,sun50i-h616-spdif + - allwinner,sun55i-a523-spdif then: required: @@ -98,6 +98,38 @@ allOf: - const: rx - const: tx + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun55i-a523-spdif + + then: + properties: + clocks: + items: + - description: Bus Clock + - description: TX Clock + - description: RX Clock + + clock-names: + items: + - const: apb + - const: tx + - const: rx + else: + properties: + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: apb + - const: spdif + required: - "#sound-dai-cells" - compatible diff --git a/dts/upstream/Bindings/sound/cirrus,cs4271.yaml b/dts/upstream/Bindings/sound/cirrus,cs4271.yaml index 68fbf5cc208..d286eb16991 100644 --- a/dts/upstream/Bindings/sound/cirrus,cs4271.yaml +++ b/dts/upstream/Bindings/sound/cirrus,cs4271.yaml @@ -25,6 +25,16 @@ properties: reg: maxItems: 1 + clocks: + items: + - description: + Master clock connected to the MCLK pin if MCLK is an input (i.e. no + crystal used). + + clock-names: + items: + - const: mclk + spi-cpha: true spi-cpol: true diff --git a/dts/upstream/Bindings/sound/cirrus,cs42xx8.yaml b/dts/upstream/Bindings/sound/cirrus,cs42xx8.yaml index cd47905eb20..7ae72bd901f 100644 --- a/dts/upstream/Bindings/sound/cirrus,cs42xx8.yaml +++ b/dts/upstream/Bindings/sound/cirrus,cs42xx8.yaml @@ -9,6 +9,9 @@ title: Cirrus Logic CS42448/CS42888 audio CODEC maintainers: - patches@opensource.cirrus.com +allOf: + - $ref: dai-common.yaml# + properties: compatible: enum: @@ -63,7 +66,7 @@ then: - VLC-supply - VLS-supply -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/upstream/Bindings/sound/cirrus,cs530x.yaml b/dts/upstream/Bindings/sound/cirrus,cs530x.yaml index 9582eb8eb41..7600fff0e3b 100644 --- a/dts/upstream/Bindings/sound/cirrus,cs530x.yaml +++ b/dts/upstream/Bindings/sound/cirrus,cs530x.yaml @@ -15,10 +15,15 @@ description: allOf: - $ref: dai-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: enum: + - cirrus,cs4282 + - cirrus,cs4302 + - cirrus,cs4304 + - cirrus,cs4308 - cirrus,cs5302 - cirrus,cs5304 - cirrus,cs5308 @@ -26,6 +31,9 @@ properties: reg: maxItems: 1 + spi-max-frequency: + maximum: 24000000 + '#sound-dai-cells': const: 1 diff --git a/dts/upstream/Bindings/sound/cix,sky1-ipbloq-hda.yaml b/dts/upstream/Bindings/sound/cix,sky1-ipbloq-hda.yaml new file mode 100644 index 00000000000..02ac5f1aa92 --- /dev/null +++ b/dts/upstream/Bindings/sound/cix,sky1-ipbloq-hda.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cix,sky1-ipbloq-hda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX IPBLOQ HDA controller + +description: + CIX IPBLOQ High Definition Audio (HDA) Controller + +maintainers: + - Joakim Zhang + +allOf: + - $ref: sound-card-common.yaml# + +properties: + compatible: + const: cix,sky1-ipbloq-hda + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: ipg + - const: per + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + + hda@70c0000 { + compatible = "cix,sky1-ipbloq-hda"; + reg = <0x70c0000 0x10000>; + interrupts = ; + clocks = <&audss_clk 7>, + <&audss_clk 8>; + clock-names = "ipg", "per"; + resets = <&audss_rst 14>; + model = "CIX SKY1 EVB HDA"; + }; diff --git a/dts/upstream/Bindings/sound/cs4265.txt b/dts/upstream/Bindings/sound/cs4265.txt deleted file mode 100644 index 380fff8e4e8..00000000000 --- a/dts/upstream/Bindings/sound/cs4265.txt +++ /dev/null @@ -1,29 +0,0 @@ -CS4265 audio CODEC - -This device supports I2C only. - -Required properties: - - - compatible : "cirrus,cs4265" - - - reg : the I2C address of the device for I2C. The I2C address depends on - the state of the AD0 pin. If AD0 is high, the i2c address is 0x4f. - If it is low, the i2c address is 0x4e. - -Optional properties: - - - reset-gpios : a GPIO spec for the reset pin. If specified, it will be - deasserted before communication to the codec starts. - -Examples: - -codec_ad0_high: cs4265@4f { /* AD0 Pin is high */ - compatible = "cirrus,cs4265"; - reg = <0x4f>; -}; - - -codec_ad0_low: cs4265@4e { /* AD0 Pin is low */ - compatible = "cirrus,cs4265"; - reg = <0x4e>; -}; diff --git a/dts/upstream/Bindings/sound/cs4341.txt b/dts/upstream/Bindings/sound/cs4341.txt deleted file mode 100644 index c1d5c8ad1a3..00000000000 --- a/dts/upstream/Bindings/sound/cs4341.txt +++ /dev/null @@ -1,22 +0,0 @@ -Cirrus Logic CS4341 audio DAC - -This device supports both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - compatible: "cirrus,cs4341a" - - reg : the I2C address of the device for I2C, the chip select - number for SPI. - -For required properties on I2C-bus, please consult -dtschema schemas/i2c/i2c-controller.yaml -For required properties on SPI-bus, please consult -Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - codec: cs4341@0 { - #sound-dai-cells = <0>; - compatible = "cirrus,cs4341a"; - reg = <0>; - spi-max-frequency = <6000000>; - }; diff --git a/dts/upstream/Bindings/sound/cs4349.txt b/dts/upstream/Bindings/sound/cs4349.txt deleted file mode 100644 index 54c117b59db..00000000000 --- a/dts/upstream/Bindings/sound/cs4349.txt +++ /dev/null @@ -1,19 +0,0 @@ -CS4349 audio CODEC - -Required properties: - - - compatible : "cirrus,cs4349" - - - reg : the I2C address of the device for I2C - -Optional properties: - - - reset-gpios : a GPIO spec for the reset pin. - -Example: - -codec: cs4349@48 { - compatible = "cirrus,cs4349"; - reg = <0x48>; - reset-gpios = <&gpio 54 0>; -}; diff --git a/dts/upstream/Bindings/sound/da9055.txt b/dts/upstream/Bindings/sound/da9055.txt deleted file mode 100644 index 75c6338b6ae..00000000000 --- a/dts/upstream/Bindings/sound/da9055.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Dialog DA9055 Audio CODEC - -DA9055 provides Audio CODEC support (I2C only). - -The Audio CODEC device in DA9055 has its own I2C address which is configurable, -so the device is instantiated separately from the PMIC (MFD) device. - -For details on accompanying PMIC I2C device, see the following: -Documentation/devicetree/bindings/mfd/da9055.txt - -Required properties: - - - compatible: "dlg,da9055-codec" - - reg: Specifies the I2C slave address - - -Example: - - codec: da9055-codec@1a { - compatible = "dlg,da9055-codec"; - reg = <0x1a>; - }; diff --git a/dts/upstream/Bindings/sound/everest,es8316.yaml b/dts/upstream/Bindings/sound/everest,es8316.yaml index 81a0215050e..fe5d938ca31 100644 --- a/dts/upstream/Bindings/sound/everest,es8316.yaml +++ b/dts/upstream/Bindings/sound/everest,es8316.yaml @@ -49,6 +49,10 @@ properties: items: - const: mclk + interrupts: + maxItems: 1 + description: Headphone detect interrupt + port: $ref: audio-graph-port.yaml# unevaluatedProperties: false diff --git a/dts/upstream/Bindings/sound/fsl,sai.yaml b/dts/upstream/Bindings/sound/fsl,sai.yaml index 0d733e5b08a..d838ee0b61c 100644 --- a/dts/upstream/Bindings/sound/fsl,sai.yaml +++ b/dts/upstream/Bindings/sound/fsl,sai.yaml @@ -44,6 +44,7 @@ properties: - items: - enum: - fsl,imx94-sai + - fsl,imx952-sai - const: fsl,imx95-sai reg: diff --git a/dts/upstream/Bindings/sound/maxim,max98090.yaml b/dts/upstream/Bindings/sound/maxim,max98090.yaml index 65e4c516912..9df1296aacb 100644 --- a/dts/upstream/Bindings/sound/maxim,max98090.yaml +++ b/dts/upstream/Bindings/sound/maxim,max98090.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Maxim Integrated MAX98090/MAX98091 audio codecs maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: | Pins on the device (for linking into audio routes): diff --git a/dts/upstream/Bindings/sound/maxim,max98095.yaml b/dts/upstream/Bindings/sound/maxim,max98095.yaml index 77544a9e158..76ea4fe711d 100644 --- a/dts/upstream/Bindings/sound/maxim,max98095.yaml +++ b/dts/upstream/Bindings/sound/maxim,max98095.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Maxim Integrated MAX98095 audio codec maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski allOf: - $ref: dai-common.yaml# diff --git a/dts/upstream/Bindings/sound/maxim,max98504.yaml b/dts/upstream/Bindings/sound/maxim,max98504.yaml index 23f19a9d2c0..6d33bb4a98a 100644 --- a/dts/upstream/Bindings/sound/maxim,max98504.yaml +++ b/dts/upstream/Bindings/sound/maxim,max98504.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Maxim Integrated MAX98504 class D mono speaker amplifier maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: Maxim Integrated MAX98504 speaker amplifier supports I2C control interface diff --git a/dts/upstream/Bindings/sound/mediatek,mt8189-afe-pcm.yaml b/dts/upstream/Bindings/sound/mediatek,mt8189-afe-pcm.yaml new file mode 100644 index 00000000000..9c9f21652af --- /dev/null +++ b/dts/upstream/Bindings/sound/mediatek,mt8189-afe-pcm.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8189-afe-pcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Audio Front End PCM controller for MT8189 + +maintainers: + - Darren Ye + - Cyril Chao + +properties: + compatible: + const: mediatek,mt8189-afe-pcm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + + mediatek,apmixedsys: + $ref: /schemas/types.yaml#/definitions/phandle + description: To set up the apll12 tuner + + power-domains: + maxItems: 1 + + clocks: + items: + - description: mux for audio intbus + - description: mux for audio engen1 + - description: mux for audio engen2 + - description: mux for audio h + - description: audio apll1 clock + - description: audio apll2 clock + - description: audio apll1 divide4 + - description: audio apll2 divide4 + - description: audio apll12 divide for i2sin0 + - description: audio apll12 divide for i2sin1 + - description: audio apll12 divide for i2sout0 + - description: audio apll12 divide for i2sout1 + - description: audio apll12 divide for fmi2s + - description: audio apll12 divide for tdmout mck + - description: audio apll12 divide for tdmout bck + - description: mux for audio apll1 + - description: mux for audio apll2 + - description: mux for i2sin0 mck + - description: mux for i2sin1 mck + - description: mux for i2sout0 mck + - description: mux for i2sout1 mck + - description: mux for fmi2s mck + - description: mux for tdmout mck + - description: 26m clock + - description: audio slv clock + - description: audio mst clock + - description: audio intbus clock + + clock-names: + items: + - const: top_aud_intbus + - const: top_aud_eng1 + - const: top_aud_eng2 + - const: top_aud_h + - const: apll1 + - const: apll2 + - const: apll1_d4 + - const: apll2_d4 + - const: apll12_div_i2sin0 + - const: apll12_div_i2sin1 + - const: apll12_div_i2sout0 + - const: apll12_div_i2sout1 + - const: apll12_div_fmi2s + - const: apll12_div_tdmout_m + - const: apll12_div_tdmout_b + - const: top_apll1 + - const: top_apll2 + - const: top_i2sin0 + - const: top_i2sin1 + - const: top_i2sout0 + - const: top_i2sout1 + - const: top_fmi2s + - const: top_dptx + - const: clk26m + - const: aud_slv_ck_peri + - const: aud_mst_ck_peri + - const: aud_intbus_ck_peri + +required: + - compatible + - reg + - interrupts + - memory-region + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + afe@11050000 { + compatible = "mediatek,mt8189-afe-pcm"; + reg = <0 0x11050000 0 0x10000>; + interrupts = ; + memory-region = <&afe_dma_mem_reserved>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + power-domains = <&scpsys 1>; //MT8189_POWER_DOMAIN_AUDIO + clocks = <&topckgen_clk 23>, //CLK_TOP_AUD_INTBUS_SEL + <&topckgen_clk 39>, //CLK_TOP_AUD_ENGEN1_SEL + <&topckgen_clk 40>, //CLK_TOP_AUD_ENGEN2_SEL + <&topckgen_clk 49>, //CLK_TOP_AUDIO_H_SEL + <&topckgen_clk 146>, //CLK_TOP_APLL1 + <&topckgen_clk 151>, //CLK_TOP_APLL2 + <&topckgen_clk 148>, //CLK_TOP_APLL1_D4 + <&topckgen_clk 153>, //CLK_TOP_APLL2_D4 + <&topckgen_clk 93>, //CLK_TOP_APLL12_CK_DIV_I2SIN0 + <&topckgen_clk 94>, //CLK_TOP_APLL12_CK_DIV_I2SIN1 + <&topckgen_clk 95>, //CLK_TOP_APLL12_CK_DIV_I2SOUT0 + <&topckgen_clk 96>, //CLK_TOP_APLL12_CK_DIV_I2SOUT1 + <&topckgen_clk 97>, //CLK_TOP_APLL12_CK_DIV_FMI2S + <&topckgen_clk 98>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M + <&topckgen_clk 99>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_B + <&topckgen_clk 44>, //CLK_TOP_AUD_1_SEL + <&topckgen_clk 45>, //CLK_TOP_AUD_2_SEL + <&topckgen_clk 78>, //CLK_TOP_APLL_I2SIN0_MCK_SEL + <&topckgen_clk 79>, //CLK_TOP_APLL_I2SIN1_MCK_SEL + <&topckgen_clk 84>, //CLK_TOP_APLL_I2SOUT0_MCK_SEL + <&topckgen_clk 85>, //CLK_TOP_APLL_I2SOUT1_MCK_SEL + <&topckgen_clk 90>, //CLK_TOP_APLL_FMI2S_MCK_SEL + <&topckgen_clk 91>, //CLK_TOP_APLL_TDMOUT_MCK_SEL + <&topckgen_clk 191>, //CLK_TOP_TCK_26M_MX9 + <&pericfg_ao_clk 77>, //CLK_PERAO_AUDIO0 + <&pericfg_ao_clk 78>, //CLK_PERAO_AUDIO1 + <&pericfg_ao_clk 79>; //CLK_PERAO_AUDIO2 + clock-names = "top_aud_intbus", + "top_aud_eng1", + "top_aud_eng2", + "top_aud_h", + "apll1", + "apll2", + "apll1_d4", + "apll2_d4", + "apll12_div_i2sin0", + "apll12_div_i2sin1", + "apll12_div_i2sout0", + "apll12_div_i2sout1", + "apll12_div_fmi2s", + "apll12_div_tdmout_m", + "apll12_div_tdmout_b", + "top_apll1", + "top_apll2", + "top_i2sin0", + "top_i2sin1", + "top_i2sout0", + "top_i2sout1", + "top_fmi2s", + "top_dptx", + "clk26m", + "aud_slv_ck_peri", + "aud_mst_ck_peri", + "aud_intbus_ck_peri"; + }; + }; + +... diff --git a/dts/upstream/Bindings/sound/mediatek,mt8189-nau8825.yaml b/dts/upstream/Bindings/sound/mediatek,mt8189-nau8825.yaml new file mode 100644 index 00000000000..dd9ee0a3b29 --- /dev/null +++ b/dts/upstream/Bindings/sound/mediatek,mt8189-nau8825.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8189-nau8825.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8189 ASoC sound card + +maintainers: + - Darren Ye + - Cyril Chao + +allOf: + - $ref: sound-card-common.yaml# + +properties: + compatible: + enum: + - mediatek,mt8189-nau8825 + - mediatek,mt8189-rt5650 + - mediatek,mt8189-rt5682s + - mediatek,mt8189-rt5682i + - mediatek,mt8189-es8326 + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of MT8189 ASoC platform. + +patternProperties: + "^dai-link-[0-9]+$": + type: object + description: + Container for dai-link level properties and CODEC sub-nodes. + + properties: + link-name: + description: + This property corresponds to the name of the BE dai-link to which + we are going to update parameters in this node. + enum: + - TDM_DPTX_BE + - I2SOUT0_BE + - I2SIN0_BE + - I2SOUT1_BE + + codec: + description: Holds subnode which indicates codec dai. + type: object + additionalProperties: false + + properties: + sound-dai: + minItems: 1 + maxItems: 2 + required: + - sound-dai + + dai-format: + description: audio format. + enum: + - i2s + - right_j + - left_j + - dsp_a + - dsp_b + + mediatek,clk-provider: + $ref: /schemas/types.yaml#/definitions/string + description: Indicates dai-link clock master. + enum: + - cpu + - codec + + additionalProperties: false + + required: + - link-name + +required: + - compatible + - mediatek,platform + +unevaluatedProperties: false + +examples: + - | + sound { + compatible = "mediatek,mt8189-nau8825"; + model = "mt8189_rt9123_8825"; + mediatek,platform = <&afe>; + dai-link-0 { + link-name = "I2SOUT1_BE"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&nau8825>; + }; + }; + }; + +... diff --git a/dts/upstream/Bindings/sound/nuvoton,nau8540.yaml b/dts/upstream/Bindings/sound/nuvoton,nau8540.yaml deleted file mode 100644 index 7ccfbb8d8b0..00000000000 --- a/dts/upstream/Bindings/sound/nuvoton,nau8540.yaml +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/nuvoton,nau8540.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Nuvoton Technology Corporation NAU85L40 Audio CODEC - -maintainers: - - John Hsu - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: nuvoton,nau8540 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1c { - compatible = "nuvoton,nau8540"; - reg = <0x1c>; - }; - }; diff --git a/dts/upstream/Bindings/sound/nuvoton,nau8810.yaml b/dts/upstream/Bindings/sound/nuvoton,nau8810.yaml deleted file mode 100644 index d9696f6c75e..00000000000 --- a/dts/upstream/Bindings/sound/nuvoton,nau8810.yaml +++ /dev/null @@ -1,45 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/nuvoton,nau8810.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NAU8810/NAU8812/NAU8814 audio CODEC - -maintainers: - - David Lin - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - enum: - - nuvoton,nau8810 - - nuvoton,nau8812 - - nuvoton,nau8814 - - reg: - maxItems: 1 - - '#sound-dai-cells': - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - codec@1a { - #sound-dai-cells = <0>; - compatible = "nuvoton,nau8810"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/nvidia,tegra210-admaif.yaml b/dts/upstream/Bindings/sound/nvidia,tegra210-admaif.yaml index b32f33214ba..2ce4049f94a 100644 --- a/dts/upstream/Bindings/sound/nvidia,tegra210-admaif.yaml +++ b/dts/upstream/Bindings/sound/nvidia,tegra210-admaif.yaml @@ -67,46 +67,72 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false -if: - properties: - compatible: - contains: - const: nvidia,tegra210-admaif +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-admaif + then: + properties: + dmas: + description: + DMA channel specifiers, equally divided for Tx and Rx. + minItems: 1 + maxItems: 20 + dma-names: + items: + pattern: "^[rt]x(10|[1-9])$" + description: + Should be "rx1", "rx2" ... "rx10" for DMA Rx channel + Should be "tx1", "tx2" ... "tx10" for DMA Tx channel + minItems: 1 + maxItems: 20 + interconnects: false + interconnect-names: false + iommus: false -then: - properties: - dmas: - description: - DMA channel specifiers, equally divided for Tx and Rx. - minItems: 1 - maxItems: 20 - dma-names: - items: - pattern: "^[rt]x(10|[1-9])$" - description: - Should be "rx1", "rx2" ... "rx10" for DMA Rx channel - Should be "tx1", "tx2" ... "tx10" for DMA Tx channel - minItems: 1 - maxItems: 20 - interconnects: false - interconnect-names: false - iommus: false + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-admaif + then: + properties: + dmas: + description: + DMA channel specifiers, equally divided for Tx and Rx. + minItems: 1 + maxItems: 40 + dma-names: + items: + pattern: "^[rt]x(1[0-9]|[1-9]|20)$" + description: + Should be "rx1", "rx2" ... "rx20" for DMA Rx channel + Should be "tx1", "tx2" ... "tx20" for DMA Tx channel + minItems: 1 + maxItems: 40 -else: - properties: - dmas: - description: - DMA channel specifiers, equally divided for Tx and Rx. - minItems: 1 - maxItems: 40 - dma-names: - items: - pattern: "^[rt]x(1[0-9]|[1-9]|20)$" - description: - Should be "rx1", "rx2" ... "rx20" for DMA Rx channel - Should be "tx1", "tx2" ... "tx20" for DMA Tx channel - minItems: 1 - maxItems: 40 + - if: + properties: + compatible: + contains: + const: nvidia,tegra264-admaif + then: + properties: + dmas: + description: + DMA channel specifiers, equally divided for Tx and Rx. + minItems: 1 + maxItems: 64 + dma-names: + items: + pattern: "^[rt]x(3[0-2]|[1-2][0-9]|[1-9])$" + description: + Should be "rx1", "rx2" ... "rx32" for DMA Rx channel + Should be "tx1", "tx2" ... "tx32" for DMA Tx channel + minItems: 1 + maxItems: 64 required: - compatible diff --git a/dts/upstream/Bindings/sound/nxp,tfa9879.yaml b/dts/upstream/Bindings/sound/nxp,tfa9879.yaml deleted file mode 100644 index df26248573a..00000000000 --- a/dts/upstream/Bindings/sound/nxp,tfa9879.yaml +++ /dev/null @@ -1,44 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/nxp,tfa9879.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NXP TFA9879 class-D audio amplifier - -maintainers: - - Peter Rosin - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: nxp,tfa9879 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - - '#sound-dai-cells' - -unevaluatedProperties: false - -examples: - - | - i2c1 { - #address-cells = <1>; - #size-cells = <0>; - amplifier@6c { - compatible = "nxp,tfa9879"; - reg = <0x6c>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - #sound-dai-cells = <0>; - }; - }; diff --git a/dts/upstream/Bindings/sound/nxp,uda1342.yaml b/dts/upstream/Bindings/sound/nxp,uda1342.yaml deleted file mode 100644 index 71c6a5a2f5b..00000000000 --- a/dts/upstream/Bindings/sound/nxp,uda1342.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/nxp,uda1342.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: NXP uda1342 audio CODECs - -maintainers: - - Binbin Zhou - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: nxp,uda1342 - - reg: - maxItems: 1 - - '#sound-dai-cells': - const: 0 - -required: - - compatible - - reg - - '#sound-dai-cells' - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1a { - compatible = "nxp,uda1342"; - reg = <0x1a>; - #sound-dai-cells = <0>; - }; - }; diff --git a/dts/upstream/Bindings/sound/pcm1789.txt b/dts/upstream/Bindings/sound/pcm1789.txt deleted file mode 100644 index 3c74ed220ac..00000000000 --- a/dts/upstream/Bindings/sound/pcm1789.txt +++ /dev/null @@ -1,22 +0,0 @@ -Texas Instruments pcm1789 DT bindings - -PCM1789 is a simple audio codec that can be connected via -I2C or SPI. Currently, only I2C bus is supported. - -Required properties: - - - compatible: "ti,pcm1789" - -Required properties on I2C: - - - reg: the I2C address - - reset-gpios: GPIO to control the RESET pin - -Examples: - - audio-codec@4c { - compatible = "ti,pcm1789"; - reg = <0x4c>; - reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - }; diff --git a/dts/upstream/Bindings/sound/pcm179x.txt b/dts/upstream/Bindings/sound/pcm179x.txt deleted file mode 100644 index 436c2b24769..00000000000 --- a/dts/upstream/Bindings/sound/pcm179x.txt +++ /dev/null @@ -1,27 +0,0 @@ -Texas Instruments pcm179x DT bindings - -This driver supports both the I2C and SPI bus. - -Required properties: - - - compatible: "ti,pcm1792a" - -For required properties on SPI, please consult -Documentation/devicetree/bindings/spi/spi-bus.txt - -Required properties on I2C: - - - reg: the I2C address - - -Examples: - - codec_spi: 1792a@0 { - compatible = "ti,pcm1792a"; - spi-max-frequency = <600000>; - }; - - codec_i2c: 1792a@4c { - compatible = "ti,pcm1792a"; - reg = <0x4c>; - }; diff --git a/dts/upstream/Bindings/sound/pcm186x.txt b/dts/upstream/Bindings/sound/pcm186x.txt deleted file mode 100644 index 1087f485598..00000000000 --- a/dts/upstream/Bindings/sound/pcm186x.txt +++ /dev/null @@ -1,42 +0,0 @@ -Texas Instruments PCM186x Universal Audio ADC - -These devices support both I2C and SPI (configured with pin strapping -on the board). - -Required properties: - - - compatible : "ti,pcm1862", - "ti,pcm1863", - "ti,pcm1864", - "ti,pcm1865" - - - reg : The I2C address of the device for I2C, the chip select - number for SPI. - - - avdd-supply: Analog core power supply (3.3v) - - dvdd-supply: Digital core power supply - - iovdd-supply: Digital IO power supply - See regulator/regulator.txt for more information - -CODEC input pins: - * VINL1 - * VINR1 - * VINL2 - * VINR2 - * VINL3 - * VINR3 - * VINL4 - * VINR4 - -The pins can be used in referring sound node's audio-routing property. - -Example: - - pcm186x: audio-codec@4a { - compatible = "ti,pcm1865"; - reg = <0x4a>; - - avdd-supply = <®_3v3_analog>; - dvdd-supply = <®_3v3>; - iovdd-supply = <®_1v8>; - }; diff --git a/dts/upstream/Bindings/sound/pcm5102a.txt b/dts/upstream/Bindings/sound/pcm5102a.txt deleted file mode 100644 index c63ab0b6ee1..00000000000 --- a/dts/upstream/Bindings/sound/pcm5102a.txt +++ /dev/null @@ -1,13 +0,0 @@ -PCM5102a audio CODECs - -These devices does not use I2C or SPI. - -Required properties: - - - compatible : set as "ti,pcm5102a" - -Examples: - - pcm5102a: pcm5102a { - compatible = "ti,pcm5102a"; - }; diff --git a/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml index 92f95eb74b1..2eed2277511 100644 --- a/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml +++ b/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml @@ -14,12 +14,14 @@ properties: oneOf: - enum: - qcom,sc7280-lpass-rx-macro + - qcom,sm6115-lpass-rx-macro - qcom,sm8250-lpass-rx-macro - qcom,sm8450-lpass-rx-macro - qcom,sm8550-lpass-rx-macro - qcom,sc8280xp-lpass-rx-macro - items: - enum: + - qcom,kaanapali-lpass-rx-macro - qcom,sm8650-lpass-rx-macro - qcom,sm8750-lpass-rx-macro - qcom,x1e80100-lpass-rx-macro @@ -80,6 +82,23 @@ allOf: - const: npl - const: fsgen + - if: + properties: + compatible: + enum: + - qcom,sm6115-lpass-rx-macro + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: mclk + - const: npl + - const: dcodec + - const: fsgen + - if: properties: compatible: diff --git a/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml index 914798a8987..e5e65e226a0 100644 --- a/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml +++ b/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8280xp-lpass-tx-macro - items: - enum: + - qcom,kaanapali-lpass-tx-macro - qcom,sm8650-lpass-tx-macro - qcom,sm8750-lpass-tx-macro - qcom,x1e80100-lpass-tx-macro diff --git a/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml index 1c0d78af3c0..5c42b2b323e 100644 --- a/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml +++ b/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sc7280-lpass-va-macro + - qcom,sm6115-lpass-va-macro - qcom,sm8250-lpass-va-macro - qcom,sm8450-lpass-va-macro - qcom,sm8550-lpass-va-macro @@ -21,6 +22,7 @@ properties: - items: - enum: - qcom,glymur-lpass-va-macro + - qcom,kaanapali-lpass-va-macro - qcom,sm8650-lpass-va-macro - qcom,sm8750-lpass-va-macro - qcom,x1e80100-lpass-va-macro @@ -41,11 +43,7 @@ properties: clock-names: minItems: 1 - items: - - const: mclk - - const: macro - - const: dcodec - - const: npl + maxItems: 4 clock-output-names: maxItems: 1 @@ -90,16 +88,33 @@ allOf: clocks: maxItems: 1 clock-names: - maxItems: 1 + items: + - const: mclk else: properties: clocks: minItems: 3 maxItems: 3 clock-names: - minItems: 3 - maxItems: 3 - + items: + - const: mclk + - const: macro + - const: dcodec + - if: + properties: + compatible: + contains: + const: qcom,sm6115-lpass-va-macro + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: mclk + - const: dcodec + - const: npl - if: properties: compatible: @@ -111,8 +126,10 @@ allOf: minItems: 3 maxItems: 3 clock-names: - minItems: 3 - maxItems: 3 + items: + - const: mclk + - const: macro + - const: dcodec - if: properties: @@ -127,8 +144,11 @@ allOf: minItems: 4 maxItems: 4 clock-names: - minItems: 4 - maxItems: 4 + items: + - const: mclk + - const: macro + - const: dcodec + - const: npl - if: properties: @@ -142,8 +162,10 @@ allOf: minItems: 3 maxItems: 3 clock-names: - minItems: 3 - maxItems: 3 + items: + - const: mclk + - const: macro + - const: dcodec unevaluatedProperties: false diff --git a/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml index b6f5ba5d132..d5f22b5cf02 100644 --- a/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - qcom,glymur-lpass-wsa-macro + - qcom,kaanapali-lpass-wsa-macro - qcom,sm8650-lpass-wsa-macro - qcom,sm8750-lpass-wsa-macro - qcom,x1e80100-lpass-wsa-macro diff --git a/dts/upstream/Bindings/sound/qcom,q6adm-routing.yaml b/dts/upstream/Bindings/sound/qcom,q6adm-routing.yaml index 3f11d2e183e..26fe8cc66b3 100644 --- a/dts/upstream/Bindings/sound/qcom,q6adm-routing.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6adm-routing.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio Device Manager (Q6ADM) routing maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla description: diff --git a/dts/upstream/Bindings/sound/qcom,q6adm.yaml b/dts/upstream/Bindings/sound/qcom,q6adm.yaml index fe14a97ea61..3c32c5b0fad 100644 --- a/dts/upstream/Bindings/sound/qcom,q6adm.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6adm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio Device Manager (Q6ADM) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla allOf: diff --git a/dts/upstream/Bindings/sound/qcom,q6afe.yaml b/dts/upstream/Bindings/sound/qcom,q6afe.yaml index 268f7073d79..4624b3d461d 100644 --- a/dts/upstream/Bindings/sound/qcom,q6afe.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6afe.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio FrontEnd (Q6AFE) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla allOf: diff --git a/dts/upstream/Bindings/sound/qcom,q6apm-lpass-dais.yaml b/dts/upstream/Bindings/sound/qcom,q6apm-lpass-dais.yaml index 894e653d37d..2fb95544db8 100644 --- a/dts/upstream/Bindings/sound/qcom,q6apm-lpass-dais.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6apm-lpass-dais.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm DSP LPASS (Low Power Audio SubSystem) Audio Ports maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla allOf: diff --git a/dts/upstream/Bindings/sound/qcom,q6apm.yaml b/dts/upstream/Bindings/sound/qcom,q6apm.yaml index ef1965aca25..ec06769a2b6 100644 --- a/dts/upstream/Bindings/sound/qcom,q6apm.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6apm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio Process Manager (Q6APM) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla allOf: diff --git a/dts/upstream/Bindings/sound/qcom,q6asm-dais.yaml b/dts/upstream/Bindings/sound/qcom,q6asm-dais.yaml index ce811942a9f..47a105a97ec 100644 --- a/dts/upstream/Bindings/sound/qcom,q6asm-dais.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6asm-dais.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio Stream Manager (Q6ASM) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla description: diff --git a/dts/upstream/Bindings/sound/qcom,q6asm.yaml b/dts/upstream/Bindings/sound/qcom,q6asm.yaml index cb49f9667cc..a6f88ce9229 100644 --- a/dts/upstream/Bindings/sound/qcom,q6asm.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6asm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio Stream Manager (Q6ASM) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla allOf: diff --git a/dts/upstream/Bindings/sound/qcom,q6core.yaml b/dts/upstream/Bindings/sound/qcom,q6core.yaml index e240712de9c..8642ef9f914 100644 --- a/dts/upstream/Bindings/sound/qcom,q6core.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6core.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Audio Core (Q6Core) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla allOf: diff --git a/dts/upstream/Bindings/sound/qcom,q6prm.yaml b/dts/upstream/Bindings/sound/qcom,q6prm.yaml index f6dbb1267bf..3eafe189e69 100644 --- a/dts/upstream/Bindings/sound/qcom,q6prm.yaml +++ b/dts/upstream/Bindings/sound/qcom,q6prm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Proxy Resource Manager (Q6PRM) maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla allOf: diff --git a/dts/upstream/Bindings/sound/qcom,sm8250.yaml b/dts/upstream/Bindings/sound/qcom,sm8250.yaml index b49a920af70..15f38622b98 100644 --- a/dts/upstream/Bindings/sound/qcom,sm8250.yaml +++ b/dts/upstream/Bindings/sound/qcom,sm8250.yaml @@ -23,6 +23,7 @@ properties: - const: qcom,sdm845-sndcard - items: - enum: + - qcom,kaanapali-sndcard - qcom,sm8550-sndcard - qcom,sm8650-sndcard - qcom,sm8750-sndcard @@ -38,6 +39,7 @@ properties: - qcom,qcs8275-sndcard - qcom,qcs9075-sndcard - qcom,qcs9100-sndcard + - qcom,qrb2210-sndcard - qcom,qrb4210-rb2-sndcard - qcom,qrb5165-rb5-sndcard - qcom,sc7180-qdsp6-sndcard diff --git a/dts/upstream/Bindings/sound/qcom,wcd934x.yaml b/dts/upstream/Bindings/sound/qcom,wcd934x.yaml index a65b1d1d5fd..3a7334e41fd 100644 --- a/dts/upstream/Bindings/sound/qcom,wcd934x.yaml +++ b/dts/upstream/Bindings/sound/qcom,wcd934x.yaml @@ -132,7 +132,7 @@ properties: $ref: /schemas/gpio/qcom,wcd934x-gpio.yaml# patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]+$": type: object additionalProperties: true description: | diff --git a/dts/upstream/Bindings/sound/qcom,wsa8840.yaml b/dts/upstream/Bindings/sound/qcom,wsa8840.yaml index 83e0360301e..866c5e780fb 100644 --- a/dts/upstream/Bindings/sound/qcom,wsa8840.yaml +++ b/dts/upstream/Bindings/sound/qcom,wsa8840.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm WSA8840/WSA8845/WSA8845H smart speaker amplifier maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - Srinivas Kandagatla description: diff --git a/dts/upstream/Bindings/sound/realtek,rt5640.yaml b/dts/upstream/Bindings/sound/realtek,rt5640.yaml index 3f4f59287c1..2eb63195096 100644 --- a/dts/upstream/Bindings/sound/realtek,rt5640.yaml +++ b/dts/upstream/Bindings/sound/realtek,rt5640.yaml @@ -47,6 +47,12 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + const: mclk + interrupts: maxItems: 1 description: The CODEC's interrupt output. @@ -98,6 +104,7 @@ properties: - 4 # Use GPIO2 for jack-detect - 5 # Use GPIO3 for jack-detect - 6 # Use GPIO4 for jack-detect + - 7 # Use HDA header for jack-detect realtek,jack-detect-not-inverted: description: @@ -121,6 +128,10 @@ properties: - 2 # Scale current by 1.0 - 3 # Scale current by 1.5 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/dts/upstream/Bindings/sound/rockchip,i2s-tdm.yaml b/dts/upstream/Bindings/sound/rockchip,i2s-tdm.yaml index 7bb6c5dff78..9435f395403 100644 --- a/dts/upstream/Bindings/sound/rockchip,i2s-tdm.yaml +++ b/dts/upstream/Bindings/sound/rockchip,i2s-tdm.yaml @@ -135,7 +135,6 @@ properties: the direction (input/output) needs to be dynamically adjusted. type: boolean - required: - compatible - reg diff --git a/dts/upstream/Bindings/sound/rockchip,rk3328-codec.yaml b/dts/upstream/Bindings/sound/rockchip,rk3328-codec.yaml index 5cdb8bcc687..52e3f1f900c 100644 --- a/dts/upstream/Bindings/sound/rockchip,rk3328-codec.yaml +++ b/dts/upstream/Bindings/sound/rockchip,rk3328-codec.yaml @@ -8,10 +8,10 @@ title: Rockchip rk3328 internal codec maintainers: - Heiko Stuebner + allOf: - $ref: dai-common.yaml# - properties: compatible: const: rockchip,rk3328-codec diff --git a/dts/upstream/Bindings/sound/rockchip-spdif.yaml b/dts/upstream/Bindings/sound/rockchip-spdif.yaml index 32dea7392e8..56c755c2294 100644 --- a/dts/upstream/Bindings/sound/rockchip-spdif.yaml +++ b/dts/upstream/Bindings/sound/rockchip-spdif.yaml @@ -70,6 +70,9 @@ properties: "#sound-dai-cells": const: 0 + port: + $ref: /schemas/graph.yaml#/properties/port + required: - compatible - reg diff --git a/dts/upstream/Bindings/sound/samsung,tm2.yaml b/dts/upstream/Bindings/sound/samsung,tm2.yaml index cbc7ba37362..67586ba3e0a 100644 --- a/dts/upstream/Bindings/sound/samsung,tm2.yaml +++ b/dts/upstream/Bindings/sound/samsung,tm2.yaml @@ -30,7 +30,6 @@ properties: - items: - description: Phandle to the HDMI transmitter node. - samsung,audio-routing: description: | List of the connections between audio components; each entry is diff --git a/dts/upstream/Bindings/sound/spacemit,k1-i2s.yaml b/dts/upstream/Bindings/sound/spacemit,k1-i2s.yaml new file mode 100644 index 00000000000..55bd0b307d2 --- /dev/null +++ b/dts/upstream/Bindings/sound/spacemit,k1-i2s.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: K1 I2S controller + +description: + The I2S bus (Inter-IC sound bus) is a serial link for digital + audio data transfer between devices in the system. + +maintainers: + - Troy Mitchell + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: spacemit,k1-i2s + + reg: + maxItems: 1 + + clocks: + items: + - description: clock for I2S sysclk + - description: clock for I2S bclk + - description: clock for I2S bus + - description: clock for I2S controller + + clock-names: + items: + - const: sysclk + - const: bclk + - const: bus + - const: func + + dmas: + minItems: 1 + maxItems: 2 + + dma-names: + minItems: 1 + items: + - const: tx + - const: rx + + resets: + maxItems: 1 + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - dmas + - dma-names + - resets + - "#sound-dai-cells" + +unevaluatedProperties: false + +examples: + - | + #include + i2s@d4026000 { + compatible = "spacemit,k1-i2s"; + reg = <0xd4026000 0x30>; + clocks = <&syscon_mpmu CLK_I2S_SYSCLK>, + <&syscon_mpmu CLK_I2S_BCLK>, + <&syscon_apbc CLK_SSPA0_BUS>, + <&syscon_apbc CLK_SSPA0>; + clock-names = "sysclk", "bclk", "bus", "func"; + dmas = <&pdma0 21>, <&pdma0 22>; + dma-names = "tx", "rx"; + resets = <&syscon_apbc RESET_SSPA0>; + #sound-dai-cells = <0>; + }; diff --git a/dts/upstream/Bindings/sound/ti,pcm1862.yaml b/dts/upstream/Bindings/sound/ti,pcm1862.yaml new file mode 100644 index 00000000000..0f0e254a242 --- /dev/null +++ b/dts/upstream/Bindings/sound/ti,pcm1862.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,pcm1862.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PCM186x Universal Audio ADC + +maintainers: + - Ranganath V N + +description: | + The Texas Instruments PCM186x family are multi-channel audio ADCs + that support both I2C and SPI control interfaces, selected by + pin strapping. These devices include on-chip programmable gain + amplifiers and support differential or single-ended analog inputs. + + CODEC input pins: + * VINL1 + * VINR1 + * VINL2 + * VINR2 + * VINL3 + * VINR3 + * VINL4 + * VINR4 + + The pins can be used in referring sound node's audio-routing property. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - ti,pcm1862 + - ti,pcm1863 + - ti,pcm1864 + - ti,pcm1865 + + reg: + maxItems: 1 + + avdd-supply: true + + dvdd-supply: true + + iovdd-supply: true + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - reg + - avdd-supply + - dvdd-supply + - iovdd-supply + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + audio-codec@4a { + compatible = "ti,pcm1865"; + reg = <0x4a>; + + avdd-supply = <®_3v3_analog>; + dvdd-supply = <®_3v3>; + iovdd-supply = <®_1v8>; + }; + }; diff --git a/dts/upstream/Bindings/sound/ti,tas2781.yaml b/dts/upstream/Bindings/sound/ti,tas2781.yaml index 7f84f506013..f3a5638f423 100644 --- a/dts/upstream/Bindings/sound/ti,tas2781.yaml +++ b/dts/upstream/Bindings/sound/ti,tas2781.yaml @@ -24,21 +24,26 @@ description: | Instruments Smart Amp speaker protection algorithm. The integrated speaker voltage and current sense provides for real time monitoring of loudspeaker behavior. - The TAS5802/TAS5815/TAS5825/TAS5827/TAS5828 is a stereo, digital input - Class-D audio amplifier optimized for efficiently driving high peak - power into small loudspeakers. An integrated on-chip DSP supports - Texas Instruments Smart Amp speaker protection algorithm. + The TAS5802/TAS5815/TAS5822/TAS5825/TAS5827/TAS5828 is a stereo, + digital input Class-D audio amplifier optimized for efficiently driving + high peak power into small loudspeakers. An integrated on-chip DSP + supports Texas Instruments Smart Amp speaker protection algorithm. Specifications about the audio amplifier can be found at: https://www.ti.com/lit/gpn/tas2120 https://www.ti.com/lit/gpn/tas2320 https://www.ti.com/lit/gpn/tas2563 https://www.ti.com/lit/gpn/tas2572 + https://www.ti.com/lit/gpn/tas2574 https://www.ti.com/lit/gpn/tas2781 + https://www.ti.com/lit/gpn/tas5806m + https://www.ti.com/lit/gpn/tas5806md https://www.ti.com/lit/gpn/tas5815 + https://www.ti.com/lit/gpn/tas5822m https://www.ti.com/lit/gpn/tas5825m https://www.ti.com/lit/gpn/tas5827 https://www.ti.com/lit/gpn/tas5828m + https://www.ti.com/lit/gpn/tas5830 properties: compatible: @@ -57,12 +62,18 @@ properties: ti,tas2563: 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP and IV Sense, 16/20/24/32bit stereo I2S or multichannel TDM. + ti,tas2568: 5.3-W Digital Input Smart Amp with I/V Sense and Integrated + 10.75-V Class-H Boost + ti,tas2570: 5.8-W Digital Input smart amp with I/V sense and integrated 11-V Class-H Boost ti,tas2572: 6.6-W Digital Input smart amp with I/V sense and integrated 13-V Class-H Boost + ti,tas2574: 8.5-W Digital Input smart amp with I/V sense and integrated + 15-V Class-H Boost + ti,tas2781: 24-V Class-D Amplifier with Real Time Integrated Speaker Protection and Audio Processing, 16/20/24/32bit stereo I2S or multichannel TDM. @@ -71,9 +82,20 @@ properties: Audio Amplifier with 96-Khz Extended Processing and Low Idle Power Dissipation. + ti,tas5806m: 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop + Class-D Audio Amplifier with Enhanced Processing and Low Power + Dissipation. + + ti,tas5806md: 23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop + Class-D Audio Amplifier with Enhanced Processing and DirectPath(TM) + HP Driver + ti,tas5815: 30-W, Digital Input, Stereo, Closed-loop Class-D Audio Amplifier with 96 kHz Enhanced Processing + ti,tas5822: 35-W, Digital Input, Stereo, Closed-Loop Class-D Audio + Amplifier with 96 kHz Enhanced Processing + ti,tas5825: 38-W Stereo, Inductor-Less, Digital Input, Closed-Loop 4.5V to 26.4V Class-D Audio Amplifier with 192-kHz Extended Audio Processing. @@ -82,6 +104,9 @@ properties: ti,tas5828: 50-W Stereo, Digital Input, High Efficiency Closed-Loop Class-D Amplifier with Hybrid-Pro Algorithm + + ti,tas5830: 65-W Stereo, Digital Input, High Efficiency Closed-Loop + Class-D Amplifier with Class-H Algorithm oneOf: - items: - enum: @@ -90,13 +115,19 @@ properties: - ti,tas2120 - ti,tas2320 - ti,tas2563 + - ti,tas2568 - ti,tas2570 - ti,tas2572 + - ti,tas2574 - ti,tas5802 + - ti,tas5806m + - ti,tas5806md - ti,tas5815 + - ti,tas5822 - ti,tas5825 - ti,tas5827 - ti,tas5828 + - ti,tas5830 - const: ti,tas2781 - enum: - ti,tas2781 @@ -132,6 +163,8 @@ allOf: - ti,tas2118 - ti,tas2120 - ti,tas2320 + - ti,tas2568 + - ti,tas2574 then: properties: reg: @@ -207,6 +240,22 @@ allOf: minimum: 0x54 maximum: 0x57 + - if: + properties: + compatible: + contains: + enum: + - ti,tas5806m + - ti,tas5806md + - ti,tas5822 + then: + properties: + reg: + maxItems: 4 + items: + minimum: 0x2c + maximum: 0x2f + - if: properties: compatible: @@ -214,6 +263,7 @@ allOf: enum: - ti,tas5827 - ti,tas5828 + - ti,tas5830 then: properties: reg: diff --git a/dts/upstream/Bindings/sound/ti,tlv320aic3x.yaml b/dts/upstream/Bindings/sound/ti,tlv320aic3x.yaml index 206f6d61e36..50088698ada 100644 --- a/dts/upstream/Bindings/sound/ti,tlv320aic3x.yaml +++ b/dts/upstream/Bindings/sound/ti,tlv320aic3x.yaml @@ -46,6 +46,7 @@ maintainers: properties: compatible: enum: + - ti,tlv320aic23 - ti,tlv320aic3x - ti,tlv320aic33 - ti,tlv320aic3007 diff --git a/dts/upstream/Bindings/sound/ti,tlv320dac3100.yaml b/dts/upstream/Bindings/sound/ti,tlv320dac3100.yaml index 85e937e3496..10299064cbc 100644 --- a/dts/upstream/Bindings/sound/ti,tlv320dac3100.yaml +++ b/dts/upstream/Bindings/sound/ti,tlv320dac3100.yaml @@ -84,7 +84,6 @@ properties: description: gpio pin number used for codec reset deprecated: true - required: - compatible - reg diff --git a/dts/upstream/Bindings/sound/trivial-codec.yaml b/dts/upstream/Bindings/sound/trivial-codec.yaml new file mode 100644 index 00000000000..9a35dfb1734 --- /dev/null +++ b/dts/upstream/Bindings/sound/trivial-codec.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/trivial-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trivial Audio Codec + +maintainers: + - Rob Herring + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + # Analog Devices SSM2602 I2S audio CODEC devices + - adi,ssm2602 + - adi,ssm2603 + - adi,ssm2604 + - adi,ssm3515 + # Cirrus Logic CS4265 audio DAC + - cirrus,cs4265 + - cirrus,cs4341a + - cirrus,cs4349 + - dlg,da9055-codec + # Nuvoton Technology Corporation NAU85L40 Audio CODEC + - nuvoton,nau8540 + - nuvoton,nau8810 + - nuvoton,nau8812 + - nuvoton,nau8814 + # NXP TFA9879 class-D audio amplifier + - nxp,tfa9879 + - nxp,uda1342 + - sdw3019f836300 + - ti,pcm1789 + - ti,pcm1792a + - ti,pcm5102a + - wlf,wm8510 + - wlf,wm8523 + - wlf,wm8580 + - wlf,wm8581 + - wlf,wm8711 + - wlf,wm8728 + - wlf,wm8737 + - wlf,wm8750 + - wlf,wm8753 + - wlf,wm8770 + - wlf,wm8776 + - wlf,wm8961 + - wlf,wm8974 + - wlf,wm8987 + + reg: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + codec@1a { + compatible = "wlf,wm8523"; + reg = <0x1a>; + }; + }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8510.yaml b/dts/upstream/Bindings/sound/wlf,wm8510.yaml deleted file mode 100644 index 6d12b0ac37e..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8510.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8510.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8510 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8510 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - codec@1a { - compatible = "wlf,wm8510"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8523.yaml b/dts/upstream/Bindings/sound/wlf,wm8523.yaml deleted file mode 100644 index decc395bb87..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8523.yaml +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8523.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8523 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8523 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1a { - compatible = "wlf,wm8523"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8580.yaml b/dts/upstream/Bindings/sound/wlf,wm8580.yaml deleted file mode 100644 index 2f27852cdc2..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8580.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8580.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8580 and WM8581 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - enum: - - wlf,wm8580 - - wlf,wm8581 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1a { - compatible = "wlf,wm8580"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8711.yaml b/dts/upstream/Bindings/sound/wlf,wm8711.yaml deleted file mode 100644 index ecaac2818b4..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8711.yaml +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8711.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8711 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8711 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1a { - compatible = "wlf,wm8711"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8728.yaml b/dts/upstream/Bindings/sound/wlf,wm8728.yaml deleted file mode 100644 index fc89475a051..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8728.yaml +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8728.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8728 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8728 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1a { - compatible = "wlf,wm8728"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8737.yaml b/dts/upstream/Bindings/sound/wlf,wm8737.yaml deleted file mode 100644 index 12d8765726d..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8737.yaml +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8737.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8737 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8737 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1a { - compatible = "wlf,wm8737"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8750.yaml b/dts/upstream/Bindings/sound/wlf,wm8750.yaml deleted file mode 100644 index 96859e38315..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8750.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8750.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8750 and WM8987 audio CODECs - -description: | - These devices support both I2C and SPI (configured with pin strapping - on the board). - -maintainers: - - Mark Brown - -properties: - compatible: - enum: - - wlf,wm8750 - - wlf,wm8987 - - reg: - description: - The I2C address of the device for I2C, the chip select number for SPI - maxItems: 1 - -additionalProperties: false - -required: - - reg - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - codec@1a { - compatible = "wlf,wm8750"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8753.yaml b/dts/upstream/Bindings/sound/wlf,wm8753.yaml deleted file mode 100644 index 9eebe7d7f0b..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8753.yaml +++ /dev/null @@ -1,62 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8753.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8753 audio CODEC - -description: | - Pins on the device (for linking into audio routes): - * LOUT1 - * LOUT2 - * ROUT1 - * ROUT2 - * MONO1 - * MONO2 - * OUT3 - * OUT4 - * LINE1 - * LINE2 - * RXP - * RXN - * ACIN - * ACOP - * MIC1N - * MIC1 - * MIC2N - * MIC2 - * Mic Bias - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8753 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - codec@1a { - compatible = "wlf,wm8753"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8776.yaml b/dts/upstream/Bindings/sound/wlf,wm8776.yaml deleted file mode 100644 index 7bbc96ee81b..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8776.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8776.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8776 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8776 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - codec@1a { - compatible = "wlf,wm8776"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8903.yaml b/dts/upstream/Bindings/sound/wlf,wm8903.yaml index 4cfa66f6268..089b6738479 100644 --- a/dts/upstream/Bindings/sound/wlf,wm8903.yaml +++ b/dts/upstream/Bindings/sound/wlf,wm8903.yaml @@ -75,7 +75,6 @@ properties: DCVDD-supply: description: Digital core supply regulator for the DCVDD pin. - required: - compatible - reg diff --git a/dts/upstream/Bindings/sound/wlf,wm8961.yaml b/dts/upstream/Bindings/sound/wlf,wm8961.yaml deleted file mode 100644 index f5807854556..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8961.yaml +++ /dev/null @@ -1,43 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8961.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Wolfson WM8961 Ultra-Low Power Stereo CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8961 - - reg: - maxItems: 1 - - '#sound-dai-cells': - const: 0 - -required: - - compatible - - reg - - '#sound-dai-cells' - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - wm8961: codec@4a { - compatible = "wlf,wm8961"; - reg = <0x4a>; - #sound-dai-cells = <0>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8974.yaml b/dts/upstream/Bindings/sound/wlf,wm8974.yaml deleted file mode 100644 index d27300207c6..00000000000 --- a/dts/upstream/Bindings/sound/wlf,wm8974.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/sound/wlf,wm8974.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: WM8974 audio CODEC - -maintainers: - - patches@opensource.cirrus.com - -allOf: - - $ref: dai-common.yaml# - -properties: - compatible: - const: wlf,wm8974 - - reg: - maxItems: 1 - - "#sound-dai-cells": - const: 0 - -required: - - compatible - - reg - -unevaluatedProperties: false - -examples: - - | - i2c { - #address-cells = <1>; - #size-cells = <0>; - - codec@1a { - compatible = "wlf,wm8974"; - reg = <0x1a>; - }; - }; diff --git a/dts/upstream/Bindings/sound/wlf,wm8994.yaml b/dts/upstream/Bindings/sound/wlf,wm8994.yaml index 8f045de0285..0db04a90ac6 100644 --- a/dts/upstream/Bindings/sound/wlf,wm8994.yaml +++ b/dts/upstream/Bindings/sound/wlf,wm8994.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Wolfson WM1811/WM8994/WM8958 audio codecs maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski - patches@opensource.cirrus.com description: | diff --git a/dts/upstream/Bindings/sound/wm8770.txt b/dts/upstream/Bindings/sound/wm8770.txt deleted file mode 100644 index cac762a1105..00000000000 --- a/dts/upstream/Bindings/sound/wm8770.txt +++ /dev/null @@ -1,16 +0,0 @@ -WM8770 audio CODEC - -This device supports SPI. - -Required properties: - - - compatible : "wlf,wm8770" - - - reg : the chip select number. - -Example: - -wm8770: codec@1 { - compatible = "wlf,wm8770"; - reg = <1>; -}; diff --git a/dts/upstream/Bindings/soundwire/qcom,soundwire.yaml b/dts/upstream/Bindings/soundwire/qcom,soundwire.yaml index 95d947fda6a..003023729fb 100644 --- a/dts/upstream/Bindings/soundwire/qcom,soundwire.yaml +++ b/dts/upstream/Bindings/soundwire/qcom,soundwire.yaml @@ -23,6 +23,7 @@ properties: - qcom,soundwire-v1.6.0 - qcom,soundwire-v1.7.0 - qcom,soundwire-v2.0.0 + - qcom,soundwire-v3.1.0 - items: - enum: - qcom,soundwire-v2.1.0 @@ -73,10 +74,12 @@ properties: qcom,din-ports: $ref: /schemas/types.yaml#/definitions/uint32 description: count of data in ports + deprecated: true qcom,dout-ports: $ref: /schemas/types.yaml#/definitions/uint32 description: count of data out ports + deprecated: true qcom,ports-word-length: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -223,8 +226,6 @@ required: - '#sound-dai-cells' - '#address-cells' - '#size-cells' - - qcom,dout-ports - - qcom,din-ports - qcom,ports-offset1 - qcom,ports-offset2 @@ -257,9 +258,6 @@ examples: clocks = <&lpass_rx_macro>; clock-names = "iface"; - qcom,din-ports = <0>; - qcom,dout-ports = <5>; - resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; reset-names = "swr_audio_cgcr"; diff --git a/dts/upstream/Bindings/spi/airoha,en7581-snand.yaml b/dts/upstream/Bindings/spi/airoha,en7581-snand.yaml index b820c5613dc..855aa08995b 100644 --- a/dts/upstream/Bindings/spi/airoha,en7581-snand.yaml +++ b/dts/upstream/Bindings/spi/airoha,en7581-snand.yaml @@ -14,7 +14,12 @@ allOf: properties: compatible: - const: airoha,en7581-snand + oneOf: + - const: airoha,en7581-snand + - items: + - enum: + - airoha,en7523-snand + - const: airoha,en7581-snand reg: items: diff --git a/dts/upstream/Bindings/spi/allwinner,sun6i-a31-spi.yaml b/dts/upstream/Bindings/spi/allwinner,sun6i-a31-spi.yaml index 3b47b68b92c..1b91d1566c9 100644 --- a/dts/upstream/Bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/dts/upstream/Bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - const: allwinner,sun50i-r329-spi + - const: allwinner,sun55i-a523-spi - const: allwinner,sun6i-a31-spi - const: allwinner,sun8i-h3-spi - items: @@ -35,6 +36,9 @@ properties: - const: allwinner,sun20i-d1-spi-dbi - const: allwinner,sun50i-r329-spi-dbi - const: allwinner,sun50i-r329-spi + - items: + - const: allwinner,sun55i-a523-spi-dbi + - const: allwinner,sun55i-a523-spi reg: maxItems: 1 diff --git a/dts/upstream/Bindings/spi/arm,pl022-peripheral-props.yaml b/dts/upstream/Bindings/spi/arm,pl022-peripheral-props.yaml index bb8b6863b10..f976e416395 100644 --- a/dts/upstream/Bindings/spi/arm,pl022-peripheral-props.yaml +++ b/dts/upstream/Bindings/spi/arm,pl022-peripheral-props.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Peripheral-specific properties for Arm PL022 SPI controller maintainers: - - Linus Walleij + - Linus Walleij select: false diff --git a/dts/upstream/Bindings/spi/aspeed,ast2600-fmc.yaml b/dts/upstream/Bindings/spi/aspeed,ast2600-fmc.yaml index 57d932af450..80e542624cc 100644 --- a/dts/upstream/Bindings/spi/aspeed,ast2600-fmc.yaml +++ b/dts/upstream/Bindings/spi/aspeed,ast2600-fmc.yaml @@ -12,7 +12,7 @@ maintainers: description: | This binding describes the Aspeed Static Memory Controllers (FMC and - SPI) of the AST2400, AST2500 and AST2600 SOCs. + SPI) of the AST2400, AST2500, AST2600 and AST2700 SOCs. allOf: - $ref: spi-controller.yaml# @@ -20,6 +20,8 @@ allOf: properties: compatible: enum: + - aspeed,ast2700-fmc + - aspeed,ast2700-spi - aspeed,ast2600-fmc - aspeed,ast2600-spi - aspeed,ast2500-fmc diff --git a/dts/upstream/Bindings/spi/fsl,spi-fsl-qspi.yaml b/dts/upstream/Bindings/spi/fsl,spi-fsl-qspi.yaml index f2dd20370db..1d10cfbad86 100644 --- a/dts/upstream/Bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/dts/upstream/Bindings/spi/fsl,spi-fsl-qspi.yaml @@ -9,9 +9,6 @@ title: Freescale Quad Serial Peripheral Interface (QuadSPI) maintainers: - Han Xu -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -22,6 +19,7 @@ properties: - fsl,imx6ul-qspi - fsl,ls1021a-qspi - fsl,ls2080a-qspi + - spacemit,k1-qspi - items: - enum: - fsl,ls1043a-qspi @@ -54,6 +52,11 @@ properties: - const: qspi_en - const: qspi + resets: + items: + - description: SoC QSPI reset + - description: SoC QSPI bus reset + required: - compatible - reg @@ -62,6 +65,18 @@ required: - clocks - clock-names +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + not: + contains: + const: spacemit,k1-qspi + then: + properties: + resets: false + unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml b/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml index 62a568bdbfa..636338d24bd 100644 --- a/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml +++ b/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml @@ -21,11 +21,13 @@ properties: - microchip,mpfs-qspi - microchip,pic64gx-qspi - const: microchip,coreqspi-rtl-v2 - - const: microchip,coreqspi-rtl-v2 # FPGA QSPI + - enum: + - microchip,coreqspi-rtl-v2 # FPGA QSPI + - microchip,corespi-rtl-v5 # FPGA CoreSPI + - microchip,mpfs-spi - items: - const: microchip,pic64gx-spi - const: microchip,mpfs-spi - - const: microchip,mpfs-spi reg: maxItems: 1 @@ -39,6 +41,45 @@ properties: clocks: maxItems: 1 + microchip,apb-datawidth: + description: APB bus data width in bits. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 32] + default: 8 + + microchip,frame-size: + description: | + Number of bits per SPI frame, as configured in Libero. + In Motorola and TI modes, this corresponds directly + to the requested frame size. For NSC mode this is set + to 9 + the required data frame size. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 4 + maximum: 32 + default: 8 + + microchip,protocol-configuration: + description: CoreSPI protocol selection. Determines operating mode + $ref: /schemas/types.yaml#/definitions/string + enum: + - motorola + - ti + - nsc + default: motorola + + microchip,motorola-mode: + description: Motorola SPI mode selection + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 3 + + microchip,ssel-active: + description: | + Keep SSEL asserted between frames when using the Motorola protocol. + When present, the controller keeps SSEL active across contiguous + transfers and deasserts only when the overall transfer completes. + type: boolean + required: - compatible - reg @@ -71,6 +112,31 @@ allOf: num-cs: maximum: 1 + - if: + properties: + compatible: + contains: + const: microchip,corespi-rtl-v5 + then: + properties: + num-cs: + minimum: 1 + maximum: 8 + default: 8 + + fifo-depth: + minimum: 1 + maximum: 32 + default: 4 + + else: + properties: + microchip,apb-datawidth: false + microchip,frame-size: false + microchip,protocol-configuration: false + microchip,motorola-mode: false + microchip,ssel-active: false + unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/spi/nuvoton,npcm-pspi.txt b/dts/upstream/Bindings/spi/nuvoton,npcm-pspi.txt deleted file mode 100644 index a4e72e52af5..00000000000 --- a/dts/upstream/Bindings/spi/nuvoton,npcm-pspi.txt +++ /dev/null @@ -1,36 +0,0 @@ -Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver - -Nuvoton NPCM7xx SOC support two PSPI channels. - -Required properties: - - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX. - "nuvoton,npcm845-pspi" for Arbel NPCM8XX. - - #address-cells : should be 1. see spi-bus.txt - - #size-cells : should be 0. see spi-bus.txt - - specifies physical base address and size of the register. - - interrupts : contain PSPI interrupt. - - clocks : phandle of PSPI reference clock. - - clock-names: Should be "clk_apb5". - - pinctrl-names : a pinctrl state named "default" must be defined. - - pinctrl-0 : phandle referencing pin configuration of the device. - - resets : phandle to the reset control for this device. - - cs-gpios: Specifies the gpio pins to be used for chipselects. - See: Documentation/devicetree/bindings/spi/spi-bus.txt - -Optional properties: -- clock-frequency : Input clock frequency to the PSPI block in Hz. - Default is 25000000 Hz. - -spi0: spi@f0200000 { - compatible = "nuvoton,npcm750-pspi"; - reg = <0xf0200000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pspi1_pins>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk NPCM7XX_CLK_APB5>; - clock-names = "clk_apb5"; - resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1> - cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; -}; diff --git a/dts/upstream/Bindings/spi/nuvoton,npcm-pspi.yaml b/dts/upstream/Bindings/spi/nuvoton,npcm-pspi.yaml new file mode 100644 index 00000000000..db0fb872020 --- /dev/null +++ b/dts/upstream/Bindings/spi/nuvoton,npcm-pspi.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,npcm-pspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Peripheral SPI (PSPI) Controller + +maintainers: + - Tomer Maimon + +allOf: + - $ref: spi-controller.yaml# + +description: + Nuvoton NPCM Peripheral Serial Peripheral Interface (PSPI) controller. + Nuvoton NPCM7xx SOC supports two PSPI channels. + Nuvoton NPCM8xx SOC support one PSPI channel. + +properties: + compatible: + enum: + - nuvoton,npcm750-pspi # Poleg NPCM7XX + - nuvoton,npcm845-pspi # Arbel NPCM8XX + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: PSPI reference clock. + + clock-names: + items: + - const: clk_apb5 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include "dt-bindings/gpio/gpio.h" + spi0: spi@f0200000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0xf0200000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi1_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + diff --git a/dts/upstream/Bindings/spi/qcom,spi-geni-qcom.yaml b/dts/upstream/Bindings/spi/qcom,spi-geni-qcom.yaml index d12c5a060ed..edf399681d7 100644 --- a/dts/upstream/Bindings/spi/qcom,spi-geni-qcom.yaml +++ b/dts/upstream/Bindings/spi/qcom,spi-geni-qcom.yaml @@ -9,7 +9,7 @@ title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interfac maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The QUP v3 core is a GENI based AHB slave that provides a common data path diff --git a/dts/upstream/Bindings/spi/qcom,spi-qpic-snand.yaml b/dts/upstream/Bindings/spi/qcom,spi-qpic-snand.yaml index cb1f15224b4..7d0571feb46 100644 --- a/dts/upstream/Bindings/spi/qcom,spi-qpic-snand.yaml +++ b/dts/upstream/Bindings/spi/qcom,spi-qpic-snand.yaml @@ -25,6 +25,8 @@ properties: - items: - enum: - qcom,ipq5018-snand + - qcom,ipq5332-snand + - qcom,ipq5424-snand - const: qcom,ipq9574-snand - const: qcom,ipq9574-snand diff --git a/dts/upstream/Bindings/spi/qcom,spi-qup.yaml b/dts/upstream/Bindings/spi/qcom,spi-qup.yaml index 88be1326896..7df21b15a0d 100644 --- a/dts/upstream/Bindings/spi/qcom,spi-qup.yaml +++ b/dts/upstream/Bindings/spi/qcom,spi-qup.yaml @@ -9,7 +9,7 @@ title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) maintainers: - Andy Gross - Bjorn Andersson - - Krzysztof Kozlowski + - Krzysztof Kozlowski description: The QUP core is an AHB slave that provides a common data path (an output FIFO diff --git a/dts/upstream/Bindings/spi/renesas,rzv2h-rspi.yaml b/dts/upstream/Bindings/spi/renesas,rzv2h-rspi.yaml index ab27fefc3c3..069557a587b 100644 --- a/dts/upstream/Bindings/spi/renesas,rzv2h-rspi.yaml +++ b/dts/upstream/Bindings/spi/renesas,rzv2h-rspi.yaml @@ -9,12 +9,18 @@ title: Renesas RZ/V2H(P) Renesas Serial Peripheral Interface (RSPI) maintainers: - Fabrizio Castro -allOf: - - $ref: spi-controller.yaml# - properties: compatible: - const: renesas,r9a09g057-rspi # RZ/V2H(P) + oneOf: + - enum: + - renesas,r9a09g057-rspi # RZ/V2H(P) + - renesas,r9a09g077-rspi # RZ/T2H + - items: + - const: renesas,r9a09g056-rspi # RZ/V2N + - const: renesas,r9a09g057-rspi + - items: + - const: renesas,r9a09g087-rspi # RZ/N2H + - const: renesas,r9a09g077-rspi # RZ/T2H reg: maxItems: 1 @@ -36,13 +42,12 @@ properties: - const: tx clocks: + minItems: 2 maxItems: 3 clock-names: - items: - - const: pclk - - const: pclk_sfr - - const: tclk + minItems: 2 + maxItems: 3 resets: maxItems: 2 @@ -62,12 +67,52 @@ required: - interrupt-names - clocks - clock-names - - resets - - reset-names - power-domains - '#address-cells' - '#size-cells' +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g057-rspi + then: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: pclk + - const: pclk_sfr + - const: tclk + + required: + - resets + - reset-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-rspi + then: + properties: + clocks: + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: pclkspi + + resets: false + reset-names: false + unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml b/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml index 0543c526b78..81838577cf9 100644 --- a/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml +++ b/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml @@ -121,7 +121,7 @@ properties: num-cs: default: 4 minimum: 1 - maximum: 4 + maximum: 16 dmas: items: @@ -153,14 +153,14 @@ properties: provides an interface to override the native DWC SSI CS control. patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]$": type: object additionalProperties: true properties: reg: minimum: 0 - maximum: 3 + maximum: 0xf unevaluatedProperties: false diff --git a/dts/upstream/Bindings/spi/spi-cadence.yaml b/dts/upstream/Bindings/spi/spi-cadence.yaml index 27414b78d61..347bed0c495 100644 --- a/dts/upstream/Bindings/spi/spi-cadence.yaml +++ b/dts/upstream/Bindings/spi/spi-cadence.yaml @@ -21,6 +21,7 @@ properties: - enum: - xlnx,zynqmp-spi-r1p6 - xlnx,versal-net-spi-r1p6 + - cix,sky1-spi-r1p6 - const: cdns,spi-r1p6 reg: diff --git a/dts/upstream/Bindings/spi/spi-controller.yaml b/dts/upstream/Bindings/spi/spi-controller.yaml index 82d051f7bd6..3b8e990e30c 100644 --- a/dts/upstream/Bindings/spi/spi-controller.yaml +++ b/dts/upstream/Bindings/spi/spi-controller.yaml @@ -111,7 +111,7 @@ properties: - compatible patternProperties: - "^.*@[0-9a-f]+$": + "@[0-9a-f]+$": type: object $ref: spi-peripheral-props.yaml additionalProperties: true diff --git a/dts/upstream/Bindings/spi/spi-pl022.yaml b/dts/upstream/Bindings/spi/spi-pl022.yaml index 7f174b7d0a2..680fdfa184d 100644 --- a/dts/upstream/Bindings/spi/spi-pl022.yaml +++ b/dts/upstream/Bindings/spi/spi-pl022.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM PL022 SPI controller maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: spi-controller.yaml# diff --git a/dts/upstream/Bindings/thermal/amazon,al-thermal.txt b/dts/upstream/Bindings/thermal/amazon,al-thermal.txt deleted file mode 100644 index 12fc4ef0483..00000000000 --- a/dts/upstream/Bindings/thermal/amazon,al-thermal.txt +++ /dev/null @@ -1,33 +0,0 @@ -Amazon's Annapurna Labs Thermal Sensor - -Simple thermal device that allows temperature reading by a single MMIO -transaction. - -Required properties: -- compatible: "amazon,al-thermal". -- reg: The physical base address and length of the sensor's registers. -- #thermal-sensor-cells: Must be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description. - -Example: - thermal: thermal { - compatible = "amazon,al-thermal"; - reg = <0x0 0x05002860 0x0 0x1>; - #thermal-sensor-cells = <0x1>; - }; - - thermal-zones { - thermal-z0 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - trips { - critical { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - }; - }; - diff --git a/dts/upstream/Bindings/thermal/amazon,al-thermal.yaml b/dts/upstream/Bindings/thermal/amazon,al-thermal.yaml new file mode 100644 index 00000000000..6b5884d74dd --- /dev/null +++ b/dts/upstream/Bindings/thermal/amazon,al-thermal.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/amazon,al-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amazon Annapurna Labs Thermal Sensor + +maintainers: + - Talel Shenhar + +description: + Simple thermal device that allows temperature reading by a single MMIO + transaction. + +properties: + compatible: + items: + - const: amazon,al-thermal + + reg: + maxItems: 1 + + '#thermal-sensor-cells': + const: 1 + +additionalProperties: false + +examples: + - | + thermal: thermal@5002860 { + compatible = "amazon,al-thermal"; + reg = <0x05002860 0x1>; + #thermal-sensor-cells = <0x1>; + }; + + thermal-zones { + z0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + trips { + critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/thermal/brcm,sr-thermal.txt b/dts/upstream/Bindings/thermal/brcm,sr-thermal.txt deleted file mode 100644 index 3ab330219d4..00000000000 --- a/dts/upstream/Bindings/thermal/brcm,sr-thermal.txt +++ /dev/null @@ -1,105 +0,0 @@ -* Broadcom Stingray Thermal - -This binding describes thermal sensors that is part of Stingray SoCs. - -Required properties: -- compatible : Must be "brcm,sr-thermal" -- reg : Memory where tmon data will be available. -- brcm,tmon-mask: A one cell bit mask of valid TMON sources. - Each bit represents single TMON source. -- #thermal-sensor-cells : Thermal sensor phandler -- polling-delay: Max number of milliseconds to wait between polls. -- thermal-sensors: A list of thermal sensor phandles and specifier. - specifier value is tmon ID and it should be - in correspond with brcm,tmon-mask. -- temperature: trip temperature threshold in millicelsius. - -Example: - tmons { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x8f100000 0x100>; - - tmon: tmon@0 { - compatible = "brcm,sr-thermal"; - reg = <0x0 0x40>; - brcm,tmon-mask = <0x3f>; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - ihost0_thermal: ihost0-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 0>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost1_thermal: ihost1-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 1>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost2_thermal: ihost2-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 2>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost3_thermal: ihost3-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 3>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - crmu_thermal: crmu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 4>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - nitro_thermal: nitro-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 5>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; diff --git a/dts/upstream/Bindings/thermal/brcm,sr-thermal.yaml b/dts/upstream/Bindings/thermal/brcm,sr-thermal.yaml new file mode 100644 index 00000000000..576a627cd59 --- /dev/null +++ b/dts/upstream/Bindings/thermal/brcm,sr-thermal.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/brcm,sr-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Stingray Thermal Sensors + +maintainers: + - Ray Jui + - Scott Branden + +allOf: + - $ref: thermal-sensor.yaml# + +properties: + compatible: + const: brcm,sr-thermal + + reg: + maxItems: 1 + + brcm,tmon-mask: + description: + A one-cell bit mask of valid TMON sources. Each bit represents a single + TMON source. + $ref: /schemas/types.yaml#/definitions/uint32 + + '#thermal-sensor-cells': + const: 1 + +required: + - compatible + - reg + - brcm,tmon-mask + +additionalProperties: false + +examples: + - | + tmon: thermal-sensor@0 { + compatible = "brcm,sr-thermal"; + reg = <0x0 0x40>; + brcm,tmon-mask = <0x3f>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + ihost0_thermal: ihost0-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 0>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost1_thermal: ihost1-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 1>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost2_thermal: ihost2-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 2>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost3_thermal: ihost3-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 3>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + crmu_thermal: crmu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 4>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + nitro_thermal: nitro-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 5>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; diff --git a/dts/upstream/Bindings/thermal/db8500-thermal.txt b/dts/upstream/Bindings/thermal/db8500-thermal.txt deleted file mode 100644 index 2e1c06fad81..00000000000 --- a/dts/upstream/Bindings/thermal/db8500-thermal.txt +++ /dev/null @@ -1,44 +0,0 @@ -* ST-Ericsson DB8500 Thermal - -** Thermal node properties: - -- compatible : "stericsson,db8500-thermal"; -- reg : address range of the thermal sensor registers; -- interrupts : interrupts generated from PRCMU; -- interrupt-names : "IRQ_HOTMON_LOW" and "IRQ_HOTMON_HIGH"; -- num-trips : number of total trip points, this is required, set it 0 if none, - if greater than 0, the following properties must be defined; -- tripN-temp : temperature of trip point N, should be in ascending order; -- tripN-type : type of trip point N, should be one of "active" "passive" "hot" - "critical"; -- tripN-cdev-num : number of the cooling devices which can be bound to trip - point N, this is required if trip point N is defined, set it 0 if none, - otherwise the following cooling device names must be defined; -- tripN-cdev-nameM : name of the No. M cooling device of trip point N; - -Usually the num-trips and tripN-*** are separated in board related dts files. - -Example: -thermal@801573c0 { - compatible = "stericsson,db8500-thermal"; - reg = <0x801573c0 0x40>; - interrupts = <21 0x4>, <22 0x4>; - interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; - - num-trips = <3>; - - trip0-temp = <75000>; - trip0-type = "active"; - trip0-cdev-num = <1>; - trip0-cdev-name0 = "thermal-cpufreq-0"; - - trip1-temp = <80000>; - trip1-type = "active"; - trip1-cdev-num = <2>; - trip1-cdev-name0 = "thermal-cpufreq-0"; - trip1-cdev-name1 = "thermal-fan"; - - trip2-temp = <85000>; - trip2-type = "critical"; - trip2-cdev-num = <0>; -} diff --git a/dts/upstream/Bindings/thermal/fsl,imx91-tmu.yaml b/dts/upstream/Bindings/thermal/fsl,imx91-tmu.yaml new file mode 100644 index 00000000000..7fd1a86d728 --- /dev/null +++ b/dts/upstream/Bindings/thermal/fsl,imx91-tmu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/fsl,imx91-tmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX91 Thermal + +maintainers: + - Pengfei Li + +description: + i.MX91 features a new temperature sensor. It includes programmable + temperature threshold comparators for both normal and privileged + accesses and allows a programmable measurement frequency for the + Periodic One-Shot Measurement mode. Additionally, it provides + status registers for indicating the end of measurement and threshold + violation events. + +properties: + compatible: + items: + - const: fsl,imx91-tmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: Comparator 1 irq + - description: Comparator 2 irq + - description: Data ready irq + + interrupt-names: + items: + - const: thr1 + - const: thr2 + - const: ready + + nvmem-cells: + items: + - description: Phandle to the trim control 1 provided by ocotp + - description: Phandle to the trim control 2 provided by ocotp + + nvmem-cell-names: + items: + - const: trim1 + - const: trim2 + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - interrupts + - interrupt-names + +allOf: + - $ref: thermal-sensor.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + + thermal-sensor@44482000 { + compatible = "fsl,imx91-tmu"; + reg = <0x44482000 0x1000>; + #thermal-sensor-cells = <0>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + interrupt-names = "thr1", "thr2", "ready"; + nvmem-cells = <&tmu_trim1>, <&tmu_trim2>; + nvmem-cell-names = "trim1", "trim2"; + }; + +... diff --git a/dts/upstream/Bindings/thermal/qcom-tsens.yaml b/dts/upstream/Bindings/thermal/qcom-tsens.yaml index 78e2f6573b9..3c5256b0cd9 100644 --- a/dts/upstream/Bindings/thermal/qcom-tsens.yaml +++ b/dts/upstream/Bindings/thermal/qcom-tsens.yaml @@ -36,10 +36,15 @@ properties: - qcom,msm8974-tsens - const: qcom,tsens-v0_1 + - description: + v1 of TSENS without RPM which requires to be explicitly reset + and enabled in the driver. + enum: + - qcom,ipq5018-tsens + - description: v1 of TSENS items: - enum: - - qcom,ipq5018-tsens - qcom,msm8937-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens @@ -50,11 +55,13 @@ properties: items: - enum: - qcom,glymur-tsens + - qcom,kaanapali-tsens - qcom,milos-tsens - qcom,msm8953-tsens - qcom,msm8996-tsens - qcom,msm8998-tsens - qcom,qcm2290-tsens + - qcom,qcs8300-tsens - qcom,qcs615-tsens - qcom,sa8255p-tsens - qcom,sa8775p-tsens diff --git a/dts/upstream/Bindings/thermal/renesas,r9a09g047-tsu.yaml b/dts/upstream/Bindings/thermal/renesas,r9a09g047-tsu.yaml index 8d3f3c24f0f..befdc8b7a08 100644 --- a/dts/upstream/Bindings/thermal/renesas,r9a09g047-tsu.yaml +++ b/dts/upstream/Bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -16,7 +16,11 @@ description: properties: compatible: - const: renesas,r9a09g047-tsu + oneOf: + - const: renesas,r9a09g047-tsu # RZ/G3E + - items: + - const: renesas,r9a09g057-tsu # RZ/V2H + - const: renesas,r9a09g047-tsu # RZ/G3E reg: maxItems: 1 diff --git a/dts/upstream/Bindings/timer/faraday,fttmr010.yaml b/dts/upstream/Bindings/timer/faraday,fttmr010.yaml index 39506323556..e93c20243db 100644 --- a/dts/upstream/Bindings/timer/faraday,fttmr010.yaml +++ b/dts/upstream/Bindings/timer/faraday,fttmr010.yaml @@ -8,7 +8,7 @@ title: Faraday FTTMR010 timer maintainers: - Joel Stanley - - Linus Walleij + - Linus Walleij description: This timer is a generic IP block from Faraday Technology, embedded in the diff --git a/dts/upstream/Bindings/timer/intel,ixp4xx-timer.yaml b/dts/upstream/Bindings/timer/intel,ixp4xx-timer.yaml index 526b8db4d57..c92e6b9cd5e 100644 --- a/dts/upstream/Bindings/timer/intel,ixp4xx-timer.yaml +++ b/dts/upstream/Bindings/timer/intel,ixp4xx-timer.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx XScale Networking Processors Timers maintainers: - - Linus Walleij + - Linus Walleij description: This timer is found in the Intel IXP4xx processors. diff --git a/dts/upstream/Bindings/timer/mrvl,mmp-timer.yaml b/dts/upstream/Bindings/timer/mrvl,mmp-timer.yaml index fe6bc417378..0643cfcc6bc 100644 --- a/dts/upstream/Bindings/timer/mrvl,mmp-timer.yaml +++ b/dts/upstream/Bindings/timer/mrvl,mmp-timer.yaml @@ -8,7 +8,7 @@ title: Marvell MMP Timer maintainers: - Daniel Lezcano - - Thomas Gleixner + - Thomas Gleixner - Rob Herring properties: diff --git a/dts/upstream/Bindings/timer/nvidia,tegra-timer.yaml b/dts/upstream/Bindings/timer/nvidia,tegra-timer.yaml index 9ea2ea3a759..adf208b7a5b 100644 --- a/dts/upstream/Bindings/timer/nvidia,tegra-timer.yaml +++ b/dts/upstream/Bindings/timer/nvidia,tegra-timer.yaml @@ -100,7 +100,6 @@ properties: items: - const: timer - required: - compatible - reg diff --git a/dts/upstream/Bindings/timer/nvidia,tegra186-timer.yaml b/dts/upstream/Bindings/timer/nvidia,tegra186-timer.yaml index 76516e18e04..1d0bd36907e 100644 --- a/dts/upstream/Bindings/timer/nvidia,tegra186-timer.yaml +++ b/dts/upstream/Bindings/timer/nvidia,tegra186-timer.yaml @@ -15,7 +15,6 @@ description: > reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. - properties: compatible: oneOf: diff --git a/dts/upstream/Bindings/timer/realtek,rtd1625-systimer.yaml b/dts/upstream/Bindings/timer/realtek,rtd1625-systimer.yaml new file mode 100644 index 00000000000..e08d3d2d306 --- /dev/null +++ b/dts/upstream/Bindings/timer/realtek,rtd1625-systimer.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/realtek,rtd1625-systimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek System Timer + +maintainers: + - Hao-Wen Ting + +description: + The Realtek SYSTIMER (System Timer) is a 64-bit global hardware counter operating + at a fixed 1MHz frequency. Thanks to its compare match interrupt capability, + the timer natively supports oneshot mode for tick broadcast functionality. + +properties: + compatible: + oneOf: + - const: realtek,rtd1625-systimer + - items: + - const: realtek,rtd1635-systimer + - const: realtek,rtd1625-systimer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + timer@89420 { + compatible = "realtek,rtd1635-systimer", + "realtek,rtd1625-systimer"; + reg = <0x89420 0x18>; + interrupts = ; + }; diff --git a/dts/upstream/Bindings/timer/sifive,clint.yaml b/dts/upstream/Bindings/timer/sifive,clint.yaml index d85a1a088b3..0d3b8dc362b 100644 --- a/dts/upstream/Bindings/timer/sifive,clint.yaml +++ b/dts/upstream/Bindings/timer/sifive,clint.yaml @@ -36,6 +36,7 @@ properties: - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 + - tenstorrent,blackhole-clint # Tenstorrent Blackhole - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - {} diff --git a/dts/upstream/Bindings/timer/st,nomadik-mtu.yaml b/dts/upstream/Bindings/timer/st,nomadik-mtu.yaml index fa65878b357..873a01c287f 100644 --- a/dts/upstream/Bindings/timer/st,nomadik-mtu.yaml +++ b/dts/upstream/Bindings/timer/st,nomadik-mtu.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ST Microelectronics Nomadik Multi-Timer Unit MTU Timer maintainers: - - Linus Walleij + - Linus Walleij description: This timer is found in the ST Microelectronics Nomadik SoCs STn8800, STn8810 and STn8815 as well as in ST-Ericsson DB8500. diff --git a/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml b/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml index 4ed30efe405..cf7c82e980f 100644 --- a/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml @@ -4,18 +4,23 @@ $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sophgo CLINT Timer +title: ACLINT Machine-level Timer Device maintainers: - Inochi Amaoto properties: compatible: - items: - - enum: - - sophgo,sg2042-aclint-mtimer - - sophgo,sg2044-aclint-mtimer - - const: thead,c900-aclint-mtimer + oneOf: + - items: + - enum: + - sophgo,sg2042-aclint-mtimer + - sophgo,sg2044-aclint-mtimer + - const: thead,c900-aclint-mtimer + - items: + - enum: + - anlogic,dr1v90-aclint-mtimer + - const: nuclei,ux900-aclint-mtimer reg: items: diff --git a/dts/upstream/Bindings/trivial-devices.yaml b/dts/upstream/Bindings/trivial-devices.yaml index 58ff948d93c..d0f7dbf15d6 100644 --- a/dts/upstream/Bindings/trivial-devices.yaml +++ b/dts/upstream/Bindings/trivial-devices.yaml @@ -43,8 +43,14 @@ properties: - adi,ad5110 # Temperature sensor with integrated fan control - adi,adm1027 + # Analog Devices ADT7410 High Accuracy Digital Temperature Sensor + - adi,adt7410 # Analog Devices ADT7411 Temperature Sensor and 8-channel ADC - adi,adt7411 + # Analog Devices ADT7420 High Accuracy Digital Temperature Sensor + - adi,adt7420 + # Analog Devices ADT7422 High Accuracy Digital Temperature Sensor + - adi,adt7422 # Temperature sensor with integrated fan control - adi,adt7463 # Temperature sensor with integrated fan control @@ -53,6 +59,8 @@ properties: - adi,lt7182s # AMS iAQ-Core VOC Sensor - ams,iaq-core + # Arduino microcontroller interface over SPI on UnoQ board + - arduino,unoq-mcu # Temperature monitoring of Astera Labs PT5161L PCIe retimer - asteralabs,pt5161l # i2c h/w elliptic curve crypto module @@ -113,8 +121,6 @@ properties: - fsl,mma7660 # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer - fsl,mma8450 - # MPL3115: Absolute Digital Pressure Sensor - - fsl,mpl3115 # MPR121: Proximity Capacitive Touch Sensor Controller - fsl,mpr121 # Honeywell Humidicon HIH-6130 humidity/temperature sensor @@ -127,8 +133,6 @@ properties: - ibm,cffps2 # IBM On-Chip Controller hwmon device - ibm,p8-occ-hwmon - # Infineon barometric pressure and temperature sensor - - infineon,dps310 # Infineon IR36021 digital POL buck controller - infineon,ir36021 # Infineon IRPS5401 Voltage Regulator (PMIC) @@ -297,6 +301,10 @@ properties: - mps,mp2888 # Monolithic Power Systems Inc. multi-phase controller mp2891 - mps,mp2891 + # Monolithic Power Systems Inc. multi-phase controller mp2925 + - mps,mp2925 + # Monolithic Power Systems Inc. multi-phase controller mp2929 + - mps,mp2929 # Monolithic Power Systems Inc. multi-phase controller mp29502 - mps,mp29502 # Monolithic Power Systems Inc. multi-phase controller mp29608 @@ -317,6 +325,8 @@ properties: - mps,mp5998 # Monolithic Power Systems Inc. digital step-down converter mp9941 - mps,mp9941 + # Monolithic Power Systems Inc. digital step-down converter mp9945 + - mps,mp9945 # Temperature sensor with integrated fan control - national,lm63 # Temperature sensor with integrated fan control diff --git a/dts/upstream/Bindings/ufs/amd,versal2-ufs.yaml b/dts/upstream/Bindings/ufs/amd,versal2-ufs.yaml new file mode 100644 index 00000000000..c00ec342d57 --- /dev/null +++ b/dts/upstream/Bindings/ufs/amd,versal2-ufs.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/amd,versal2-ufs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Versal Gen 2 UFS Host Controller + +maintainers: + - Sai Krishna Potthuri + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: amd,versal2-ufs + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: host + - const: phy + +required: + - reg + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + ufs@f10b0000 { + compatible = "amd,versal2-ufs"; + reg = <0xf10b0000 0x1000>; + clocks = <&ufs_core_clk>; + clock-names = "core"; + resets = <&scmi_reset 4>, <&scmi_reset 35>; + reset-names = "host", "phy"; + interrupts = ; + freq-table-hz = <0 0>; + }; diff --git a/dts/upstream/Bindings/ufs/mediatek,ufs.yaml b/dts/upstream/Bindings/ufs/mediatek,ufs.yaml index 1dec54fb00f..15c347f5e66 100644 --- a/dts/upstream/Bindings/ufs/mediatek,ufs.yaml +++ b/dts/upstream/Bindings/ufs/mediatek,ufs.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek Universal Flash Storage (UFS) Controller maintainers: - - Stanley Chu + - Peter Wang + - Chaotian Jing properties: compatible: diff --git a/dts/upstream/Bindings/ufs/qcom,ufs.yaml b/dts/upstream/Bindings/ufs/qcom,ufs.yaml index 1dd41f6d525..516bb61a462 100644 --- a/dts/upstream/Bindings/ufs/qcom,ufs.yaml +++ b/dts/upstream/Bindings/ufs/qcom,ufs.yaml @@ -88,7 +88,6 @@ allOf: - const: ice_core_clk reg: minItems: 2 - maxItems: 2 reg-names: minItems: 2 required: @@ -117,7 +116,6 @@ allOf: - const: tx_lane0_sync_clk - const: rx_lane0_sync_clk reg: - minItems: 1 maxItems: 1 reg-names: maxItems: 1 @@ -147,7 +145,6 @@ allOf: - const: ice_core_clk reg: minItems: 2 - maxItems: 2 reg-names: minItems: 2 required: diff --git a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml index b4e744ebffd..a7eb7ad85a9 100644 --- a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml +++ b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml @@ -61,6 +61,9 @@ properties: phy-names: const: ufs-phy + power-domains: + maxItems: 1 + samsung,sysreg: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/dts/upstream/Bindings/ufs/ufs-common.yaml b/dts/upstream/Bindings/ufs/ufs-common.yaml index 9f04f34d8c5..ed97f568250 100644 --- a/dts/upstream/Bindings/ufs/ufs-common.yaml +++ b/dts/upstream/Bindings/ufs/ufs-common.yaml @@ -48,8 +48,8 @@ properties: enum: [1, 2] default: 2 description: - Number of lanes available per direction. Note that it is assume same - number of lanes is used both directions at once. + Number of lanes available per direction. Note that it is assumed that + the same number of lanes are used in both directions at once. vdd-hba-supply: description: diff --git a/dts/upstream/Bindings/usb/apple,dwc3.yaml b/dts/upstream/Bindings/usb/apple,dwc3.yaml new file mode 100644 index 00000000000..f70c33f32c5 --- /dev/null +++ b/dts/upstream/Bindings/usb/apple,dwc3.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/apple,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple Silicon DWC3 USB controller + +maintainers: + - Sven Peter + +description: + Apple Silicon SoCs use a Synopsys DesignWare DWC3 based controller for each of + their Type-C ports. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - apple,t6000-dwc3 + - apple,t6020-dwc3 + - apple,t8112-dwc3 + - const: apple,t8103-dwc3 + - const: apple,t8103-dwc3 + + reg: + items: + - description: Core DWC3 region + - description: Apple-specific DWC3 region + + reg-names: + items: + - const: dwc3-core + - const: dwc3-apple + + interrupts: + maxItems: 1 + + iommus: + maxItems: 2 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - iommus + - resets + - power-domains + - usb-role-switch + +unevaluatedProperties: false + +examples: + - | + #include + #include + + usb@82280000 { + compatible = "apple,t8103-dwc3"; + reg = <0x82280000 0xcd00>, <0x8228cd00 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupts = ; + iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + + power-domains = <&ps_atc0_usb>; + resets = <&atcphy0>; + + usb-role-switch; + }; diff --git a/dts/upstream/Bindings/usb/dwc3-xilinx.yaml b/dts/upstream/Bindings/usb/dwc3-xilinx.yaml index 36f5c644d95..d6823ef5f9a 100644 --- a/dts/upstream/Bindings/usb/dwc3-xilinx.yaml +++ b/dts/upstream/Bindings/usb/dwc3-xilinx.yaml @@ -47,6 +47,7 @@ properties: - const: ref_clk resets: + minItems: 1 description: A list of phandles for resets listed in reset-names. @@ -56,6 +57,7 @@ properties: - description: USB APB reset reset-names: + minItems: 1 items: - const: usb_crst - const: usb_hibrst @@ -95,6 +97,26 @@ required: - resets - reset-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-dwc3 + then: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + else: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + additionalProperties: false examples: diff --git a/dts/upstream/Bindings/usb/eswin,eic7700-usb.yaml b/dts/upstream/Bindings/usb/eswin,eic7700-usb.yaml new file mode 100644 index 00000000000..41c3b1b9899 --- /dev/null +++ b/dts/upstream/Bindings/usb/eswin,eic7700-usb.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/eswin,eic7700-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN EIC7700 SoC Usb Controller + +maintainers: + - Wei Yang + - Senchuan Zhang + - Hang Cao + +description: + The Usb controller on EIC7700 SoC. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: eswin,eic7700-dwc3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: peripheral + + clocks: + maxItems: 3 + + clock-names: + items: + - const: aclk + - const: cfg + - const: usb_en + + resets: + maxItems: 2 + + reset-names: + items: + - const: vaux + - const: usb_rst + + eswin,hsp-sp-csr: + description: + HSP CSR is to control and get status of different high-speed peripherals + (such as Ethernet, USB, SATA, etc.) via register, which can tune + board-level's parameters of PHY, etc. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to HSP Register Controller hsp_sp_csr node. + - description: USB bus register offset. + - description: AXI low power register offset. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - resets + - reset-names + - eswin,hsp-sp-csr + +unevaluatedProperties: false + +examples: + - | + usb@50480000 { + compatible = "eswin,eic7700-dwc3"; + reg = <0x50480000 0x10000>; + clocks = <&clock 135>, + <&clock 136>, + <&hspcrg 18>; + clock-names = "aclk", "cfg", "usb_en"; + interrupt-parent = <&plic>; + interrupts = <85>; + interrupt-names = "peripheral"; + resets = <&reset 84>, <&hspcrg 2>; + reset-names = "vaux", "usb_rst"; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phy_type = "utmi"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>; + }; diff --git a/dts/upstream/Bindings/usb/faraday,fotg210.yaml b/dts/upstream/Bindings/usb/faraday,fotg210.yaml index 3fe4d1564df..b97ba535087 100644 --- a/dts/upstream/Bindings/usb/faraday,fotg210.yaml +++ b/dts/upstream/Bindings/usb/faraday,fotg210.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FOTG200 series HS OTG USB 2.0 controller maintainers: - - Linus Walleij + - Linus Walleij allOf: - $ref: usb-drd.yaml# diff --git a/dts/upstream/Bindings/usb/fsl,ls1028a.yaml b/dts/upstream/Bindings/usb/fsl,ls1028a.yaml index a44bdf39188..4784f057264 100644 --- a/dts/upstream/Bindings/usb/fsl,ls1028a.yaml +++ b/dts/upstream/Bindings/usb/fsl,ls1028a.yaml @@ -9,21 +9,19 @@ title: Freescale layerscape SuperSpeed DWC3 USB SoC controller maintainers: - Frank Li -select: - properties: - compatible: - contains: - enum: - - fsl,ls1028a-dwc3 - required: - - compatible - properties: compatible: - items: - - enum: - - fsl,ls1028a-dwc3 - - const: snps,dwc3 + oneOf: + - items: + - enum: + - fsl,ls1012a-dwc3 + - fsl,ls1043a-dwc3 + - fsl,ls1046a-dwc3 + - fsl,ls1088a-dwc3 + - fsl,ls208xa-dwc3 + - fsl,lx2160a-dwc3 + - const: fsl,ls1028a-dwc3 + - const: fsl,ls1028a-dwc3 reg: maxItems: 1 @@ -31,6 +29,11 @@ properties: interrupts: maxItems: 1 + iommus: + maxItems: 1 + + dma-coherent: true + unevaluatedProperties: false required: @@ -39,14 +42,14 @@ required: - interrupts allOf: - - $ref: snps,dwc3.yaml# + - $ref: snps,dwc3-common.yaml# examples: - | #include usb@fe800000 { - compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; + compatible = "fsl,ls1028a-dwc3"; reg = <0xfe800000 0x100000>; interrupts = ; }; diff --git a/dts/upstream/Bindings/usb/fsl,usbmisc.yaml b/dts/upstream/Bindings/usb/fsl,usbmisc.yaml index ca677d1a827..d06efe4dbb3 100644 --- a/dts/upstream/Bindings/usb/fsl,usbmisc.yaml +++ b/dts/upstream/Bindings/usb/fsl,usbmisc.yaml @@ -36,6 +36,7 @@ properties: - fsl,imx8mm-usbmisc - fsl,imx8mn-usbmisc - fsl,imx8ulp-usbmisc + - fsl,imx94-usbmisc - fsl,imx95-usbmisc - const: fsl,imx7d-usbmisc - const: fsl,imx6q-usbmisc diff --git a/dts/upstream/Bindings/usb/generic-ehci.yaml b/dts/upstream/Bindings/usb/generic-ehci.yaml index 508d958e698..4e84bead023 100644 --- a/dts/upstream/Bindings/usb/generic-ehci.yaml +++ b/dts/upstream/Bindings/usb/generic-ehci.yaml @@ -46,6 +46,7 @@ properties: - aspeed,ast2400-ehci - aspeed,ast2500-ehci - aspeed,ast2600-ehci + - aspeed,ast2700-ehci - brcm,bcm3384-ehci - brcm,bcm63268-ehci - brcm,bcm6328-ehci diff --git a/dts/upstream/Bindings/usb/generic-xhci.yaml b/dts/upstream/Bindings/usb/generic-xhci.yaml index a2b94a13899..62678abd74b 100644 --- a/dts/upstream/Bindings/usb/generic-xhci.yaml +++ b/dts/upstream/Bindings/usb/generic-xhci.yaml @@ -14,12 +14,15 @@ properties: oneOf: - description: Generic xHCI device const: generic-xhci - - description: Armada 37xx/375/38x/8k SoCs + - description: Armada 375/38x SoCs + items: + - enum: + - marvell,armada-375-xhci + - marvell,armada-380-xhci + - description: Armada 37xx/8k SoCs items: - enum: - marvell,armada3700-xhci - - marvell,armada-375-xhci - - marvell,armada-380-xhci - marvell,armada-8k-xhci - const: generic-xhci - description: Broadcom SoCs with power domains @@ -53,6 +56,14 @@ properties: dma-coherent: true + dr_mode: + enum: + - host + - otg + + iommus: + maxItems: 1 + power-domains: maxItems: 1 diff --git a/dts/upstream/Bindings/usb/intel,ixp4xx-udc.yaml b/dts/upstream/Bindings/usb/intel,ixp4xx-udc.yaml index 4ed60274689..91a149ad3ad 100644 --- a/dts/upstream/Bindings/usb/intel,ixp4xx-udc.yaml +++ b/dts/upstream/Bindings/usb/intel,ixp4xx-udc.yaml @@ -10,7 +10,7 @@ description: The IXP4xx SoCs has a full-speed USB Device Controller with 16 endpoints and a built-in transceiver. maintainers: - - Linus Walleij + - Linus Walleij properties: compatible: diff --git a/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml b/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml index 004d3ebec09..231e6f35a98 100644 --- a/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml +++ b/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8183-xhci - mediatek,mt8186-xhci - mediatek,mt8188-xhci + - mediatek,mt8189-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci - mediatek,mt8365-xhci @@ -168,7 +169,8 @@ properties: 104 - used by mt8195, IP1, specific 1.04; 105 - used by mt8195, IP2, specific 1.05; 106 - used by mt8195, IP3, specific 1.06; - enum: [1, 2, 101, 102, 103, 104, 105, 106] + 110 - used by mt8189, IP4, specific 1.10; + enum: [1, 2, 101, 102, 103, 104, 105, 106, 110] mediatek,u3p-dis-msk: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/upstream/Bindings/usb/nvidia,tegra234-xusb.yaml b/dts/upstream/Bindings/usb/nvidia,tegra234-xusb.yaml index db761dcbf72..ec0993497fb 100644 --- a/dts/upstream/Bindings/usb/nvidia,tegra234-xusb.yaml +++ b/dts/upstream/Bindings/usb/nvidia,tegra234-xusb.yaml @@ -32,9 +32,35 @@ properties: - const: bar2 interrupts: + minItems: 2 items: - description: xHCI host interrupt - description: mailbox interrupt + - description: USB wake event 0 + - description: USB wake event 1 + - description: USB wake event 2 + - description: USB wake event 3 + - description: USB wake event 4 + - description: USB wake event 5 + - description: USB wake event 6 + description: | + The first two interrupts are required for the USB host controller. The + remaining USB wake event interrupts are optional. Each USB wake event is + independent; it is not necessary to use all of these events on a + platform. The USB host controller can function even if no wake-up events + are defined. The USB wake event interrupts are handled by the Tegra PMC; + hence, the interrupt controller for these is the PMC and the interrupt + IDs correspond to the PMC wake event IDs. A complete list of wake event + IDs is provided below, and this information is also present in the Tegra + TRM document. + + PMC wake-up 76 for USB3 port 0 wakeup + PMC wake-up 77 for USB3 port 1 wakeup + PMC wake-up 78 for USB3 port 2 and port 3 wakeup + PMC wake-up 79 for USB2 port 0 wakeup + PMC wake-up 80 for USB2 port 1 wakeup + PMC wake-up 81 for USB2 port 2 wakeup + PMC wake-up 82 for USB2 port 3 wakeup clocks: items: @@ -127,8 +153,9 @@ examples: <0x03650000 0x10000>; reg-names = "hcd", "fpci", "bar2"; - interrupts = , - ; + interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, <&bpmp TEGRA234_CLK_XUSB_FALCON>, diff --git a/dts/upstream/Bindings/usb/qcom,dwc3.yaml b/dts/upstream/Bindings/usb/qcom,dwc3.yaml index a792434c59d..a7f58114c02 100644 --- a/dts/upstream/Bindings/usb/qcom,dwc3.yaml +++ b/dts/upstream/Bindings/usb/qcom,dwc3.yaml @@ -406,7 +406,6 @@ allOf: compatible: contains: enum: - - qcom,ipq5018-dwc3 - qcom,ipq6018-dwc3 - qcom,ipq8074-dwc3 - qcom,msm8953-dwc3 @@ -428,6 +427,7 @@ allOf: compatible: contains: enum: + - qcom,msm8994-dwc3 - qcom,msm8996-dwc3 - qcom,qcs404-dwc3 - qcom,sdm660-dwc3 @@ -451,6 +451,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5018-dwc3 - qcom,ipq5332-dwc3 then: properties: @@ -488,7 +489,6 @@ allOf: enum: - qcom,ipq4019-dwc3 - qcom,ipq8064-dwc3 - - qcom,msm8994-dwc3 - qcom,qcs615-dwc3 - qcom,qcs8300-dwc3 - qcom,qdu1000-dwc3 diff --git a/dts/upstream/Bindings/usb/qcom,pmic-typec.yaml b/dts/upstream/Bindings/usb/qcom,pmic-typec.yaml index 6d3ef364672..6d3fa2bc9ce 100644 --- a/dts/upstream/Bindings/usb/qcom,pmic-typec.yaml +++ b/dts/upstream/Bindings/usb/qcom,pmic-typec.yaml @@ -28,7 +28,6 @@ properties: - qcom,pm4125-typec - const: qcom,pmi632-typec - connector: type: object $ref: /schemas/connector/usb-connector.yaml# diff --git a/dts/upstream/Bindings/usb/qcom,snps-dwc3.yaml b/dts/upstream/Bindings/usb/qcom,snps-dwc3.yaml index d49a58d5478..7d784a648b7 100644 --- a/dts/upstream/Bindings/usb/qcom,snps-dwc3.yaml +++ b/dts/upstream/Bindings/usb/qcom,snps-dwc3.yaml @@ -24,6 +24,8 @@ properties: compatible: items: - enum: + - qcom,glymur-dwc3 + - qcom,glymur-dwc3-mp - qcom,ipq4019-dwc3 - qcom,ipq5018-dwc3 - qcom,ipq5332-dwc3 @@ -32,6 +34,7 @@ properties: - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 - qcom,ipq9574-dwc3 + - qcom,kaanapali-dwc3 - qcom,milos-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 @@ -67,6 +70,7 @@ properties: - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 + - qcom,sm8750-dwc3 - qcom,x1e80100-dwc3 - qcom,x1e80100-dwc3-mp - const: qcom,snps-dwc3 @@ -200,6 +204,7 @@ allOf: contains: enum: - qcom,ipq9574-dwc3 + - qcom,kaanapali-dwc3 - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 @@ -213,6 +218,7 @@ allOf: - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - qcom,sm6350-dwc3 + - qcom,sm8750-dwc3 then: properties: clocks: @@ -392,7 +398,28 @@ allOf: compatible: contains: enum: - - qcom,ipq5018-dwc3 + - qcom,glymur-dwc3 + - qcom,glymur-dwc3-mp + + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: noc_aggr_north + - const: noc_aggr_south + + - if: + properties: + compatible: + contains: + enum: - qcom,ipq6018-dwc3 - qcom,ipq8074-dwc3 - qcom,msm8953-dwc3 @@ -415,6 +442,7 @@ allOf: compatible: contains: enum: + - qcom,msm8994-dwc3 - qcom,msm8996-dwc3 - qcom,qcs404-dwc3 - qcom,sdm660-dwc3 @@ -439,6 +467,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5018-dwc3 - qcom,ipq5332-dwc3 then: properties: @@ -456,6 +485,7 @@ allOf: compatible: contains: enum: + - qcom,glymur-dwc3 - qcom,milos-dwc3 - qcom,x1e80100-dwc3 then: @@ -479,7 +509,7 @@ allOf: enum: - qcom,ipq4019-dwc3 - qcom,ipq8064-dwc3 - - qcom,msm8994-dwc3 + - qcom,kaanapali-dwc3 - qcom,qcs615-dwc3 - qcom,qcs8300-dwc3 - qcom,qdu1000-dwc3 @@ -501,6 +531,7 @@ allOf: - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 + - qcom,sm8750-dwc3 then: properties: interrupts: @@ -521,6 +552,7 @@ allOf: compatible: contains: enum: + - qcom,glymur-dwc3-mp - qcom,sc8180x-dwc3-mp - qcom,x1e80100-dwc3-mp then: diff --git a/dts/upstream/Bindings/usb/renesas,rzg3e-xhci.yaml b/dts/upstream/Bindings/usb/renesas,rzg3e-xhci.yaml index 98260f9fb44..3f4b09e48ce 100644 --- a/dts/upstream/Bindings/usb/renesas,rzg3e-xhci.yaml +++ b/dts/upstream/Bindings/usb/renesas,rzg3e-xhci.yaml @@ -4,14 +4,22 @@ $id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G3E USB 3.2 Gen2 Host controller +title: Renesas USB 3.2 Gen2 Host controller maintainers: - Biju Das properties: compatible: - const: renesas,r9a09g047-xhci + oneOf: + - items: + - enum: + - renesas,r9a09g056-xhci # RZ/V2N + - renesas,r9a09g057-xhci # RZ/V2H(P) + - const: renesas,r9a09g047-xhci + + - items: + - const: renesas,r9a09g047-xhci # RZ/G3E reg: maxItems: 1 diff --git a/dts/upstream/Bindings/usb/samsung,exynos-dwc3.yaml b/dts/upstream/Bindings/usb/samsung,exynos-dwc3.yaml index 6d39e506694..8af0143c3e4 100644 --- a/dts/upstream/Bindings/usb/samsung,exynos-dwc3.yaml +++ b/dts/upstream/Bindings/usb/samsung,exynos-dwc3.yaml @@ -21,6 +21,9 @@ properties: - samsung,exynos7870-dwusb3 - samsung,exynos850-dwusb3 - samsung,exynosautov920-dwusb3 + - items: + - const: samsung,exynos8890-dwusb3 + - const: samsung,exynos7-dwusb3 - items: - const: samsung,exynos990-dwusb3 - const: samsung,exynos850-dwusb3 @@ -36,6 +39,9 @@ properties: minItems: 1 maxItems: 4 + power-domains: + maxItems: 1 + ranges: true '#size-cells': diff --git a/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml b/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml index bec1c8047bc..06099e93c6c 100644 --- a/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml +++ b/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml @@ -25,6 +25,14 @@ properties: interrupts: maxItems: 1 + id-gpios: + description: + An input gpio for USB ID pin. Upon detecting a UFP device, HD3SS3220 + will keep ID pin high if VBUS is not at VSafe0V. Once VBUS is at VSafe0V, + the HD3SS3220 will assert ID pin low. This is done to enforce Type-C + requirement that VBUS must be at VSafe0V before re-enabling VBUS. + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports description: OF graph bindings (specified in bindings/graph.txt) that model diff --git a/dts/upstream/Bindings/usb/usb-uhci.yaml b/dts/upstream/Bindings/usb/usb-uhci.yaml index d8336f72dc1..e050ca20394 100644 --- a/dts/upstream/Bindings/usb/usb-uhci.yaml +++ b/dts/upstream/Bindings/usb/usb-uhci.yaml @@ -20,6 +20,7 @@ properties: - aspeed,ast2400-uhci - aspeed,ast2500-uhci - aspeed,ast2600-uhci + - aspeed,ast2700-uhci - const: generic-uhci reg: @@ -28,6 +29,9 @@ properties: interrupts: maxItems: 1 + resets: + maxItems: 1 + '#ports': $ref: /schemas/types.yaml#/definitions/uint32 @@ -50,6 +54,15 @@ allOf: required: - clocks + - if: + properties: + compatible: + contains: + const: aspeed,ast2700-uhci + then: + required: + - resets + unevaluatedProperties: false examples: diff --git a/dts/upstream/Bindings/vendor-prefixes.yaml b/dts/upstream/Bindings/vendor-prefixes.yaml index f1d1882009b..c7591b2aec2 100644 --- a/dts/upstream/Bindings/vendor-prefixes.yaml +++ b/dts/upstream/Bindings/vendor-prefixes.yaml @@ -20,7 +20,7 @@ patternProperties: "^(keypad|m25p|max8952|max8997|max8998|mpmc),.*": true "^(pciclass|pinctrl-single|#pinctrl-single|PowerPC),.*": true "^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true - "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true + "^(simple-audio-card|st-plgpio|st-spics|ts|vsc8531),.*": true "^pool[0-3],.*": true # Keep list in alphabetical order. @@ -30,6 +30,8 @@ patternProperties: description: 70mai Co., Ltd. "^8dev,.*": description: 8devices, UAB + "^9tripod,.*": + description: Shenzhen 9Tripod Innovation and Development CO., LTD. "^abb,.*": description: ABB "^abilis,.*": @@ -132,6 +134,8 @@ patternProperties: description: Anbernic "^andestech,.*": description: Andes Technology Corporation + "^anlogic,.*": + description: Shanghai Anlogic Infotech Co., Ltd. "^anvo,.*": description: Anvo-Systems Dresden GmbH "^aoly,.*": @@ -176,6 +180,8 @@ patternProperties: description: All Sensors Corporation "^asix,.*": description: ASIX Electronics Corporation + "^asl-tek,.*": + description: ASL Xiamen Technology Co., Ltd. "^aspeed,.*": description: ASPEED Technology Inc. "^asrock,.*": @@ -251,6 +257,8 @@ patternProperties: description: Shanghai Broadmobi Communication Technology Co.,Ltd. "^bsh,.*": description: BSH Hausgeraete GmbH + "^bst,.*": + description: Black Sesame Technologies Co., Ltd. "^bticino,.*": description: Bticino International "^buffalo,.*": @@ -570,6 +578,8 @@ patternProperties: description: Foxconn Industrial Internet "^firefly,.*": description: Firefly + "^fitipower,.*": + description: Fitipower Integrated Technology Inc. "^flipkart,.*": description: Flipkart Inc. "^focaltech,.*": @@ -835,6 +845,8 @@ patternProperties: description: JOZ BV "^jty,.*": description: JTY + "^jutouch,.*": + description: JuTouch Technology Co., Ltd. "^kam,.*": description: Kamstrup A/S "^karo,.*": @@ -907,6 +919,8 @@ patternProperties: description: Lincoln Technology Solutions "^lineartechnology,.*": description: Linear Technology + "^linkease,.*": + description: Shenzhen LinkEase Network Technology Co., Ltd. "^linksprite,.*": description: LinkSprite Technologies, Inc. "^linksys,.*": @@ -1023,6 +1037,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milianke,.*": + description: Changzhou Milianke Electronic Technology Co., Ltd "^milkv,.*": description: MilkV Technology Co., Ltd "^miniand,.*": @@ -1140,6 +1156,8 @@ patternProperties: description: Novatek "^novtech,.*": description: NovTech, Inc. + "^nuclei,.*": + description: Nuclei System Technology "^numonyx,.*": description: Numonyx (deprecated, use micron) deprecated: true @@ -1323,6 +1341,8 @@ patternProperties: description: Raumfeld GmbH "^raydium,.*": description: Raydium Semiconductor Corp. + "^raystar,.*": + description: Raystar Optronics, Inc. "^rda,.*": description: Unisoc Communications, Inc. "^realtek,.*": @@ -1610,6 +1630,8 @@ patternProperties: description: Tempo Semiconductor "^tenda,.*": description: Shenzhen Tenda Technology Co., Ltd. + "^tenstorrent,.*": + description: Tenstorrent AI ULC "^terasic,.*": description: Terasic Inc. "^tesla,.*": @@ -1705,6 +1727,8 @@ patternProperties: description: Universal Scientific Industrial Co., Ltd. "^usr,.*": description: U.S. Robotics Corporation + "^ultrarisc,.*": + description: UltraRISC Technology Co., Ltd. "^ultratronik,.*": description: Ultratronik GmbH "^utoo,.*": diff --git a/dts/upstream/Bindings/watchdog/airoha,en7581-wdt.yaml b/dts/upstream/Bindings/watchdog/airoha,en7581-wdt.yaml index 6bbab3cb28e..6259478bdae 100644 --- a/dts/upstream/Bindings/watchdog/airoha,en7581-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/airoha,en7581-wdt.yaml @@ -14,7 +14,11 @@ allOf: properties: compatible: - const: airoha,en7581-wdt + oneOf: + - items: + - const: airoha,an7583-wdt + - const: airoha,en7581-wdt + - const: airoha,en7581-wdt reg: maxItems: 1 diff --git a/dts/upstream/Bindings/watchdog/aspeed,ast2400-wdt.yaml b/dts/upstream/Bindings/watchdog/aspeed,ast2400-wdt.yaml index be78a986558..9322cb5b462 100644 --- a/dts/upstream/Bindings/watchdog/aspeed,ast2400-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/aspeed,ast2400-wdt.yaml @@ -15,6 +15,7 @@ properties: - aspeed,ast2400-wdt - aspeed,ast2500-wdt - aspeed,ast2600-wdt + - aspeed,ast2700-wdt reg: maxItems: 1 @@ -87,13 +88,15 @@ properties: aspeed,reset-mask: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 - maxItems: 2 + maxItems: 5 description: > A bitmask indicating which peripherals will be reset if the watchdog timer expires. On AST2500 SoCs this should be a single word defined using the AST2500_WDT_RESET_* macros; on AST2600 SoCs this should be a two-word array with the first word defined using the AST2600_WDT_RESET1_* macros, - and the second word defined using the AST2600_WDT_RESET2_* macros. + and the second word defined using the AST2600_WDT_RESET2_* macros; on + AST2700 SoCs, this should be five-word array from AST2700_WDT_RESET1_* + macros to AST2700_WDT_RESET5_* macros. required: - compatible @@ -114,6 +117,7 @@ allOf: enum: - aspeed,ast2500-wdt - aspeed,ast2600-wdt + - aspeed,ast2700-wdt - if: required: - aspeed,ext-active-high diff --git a/dts/upstream/Bindings/watchdog/faraday,ftwdt010.yaml b/dts/upstream/Bindings/watchdog/faraday,ftwdt010.yaml index 726dc872ad0..3eb35f325f4 100644 --- a/dts/upstream/Bindings/watchdog/faraday,ftwdt010.yaml +++ b/dts/upstream/Bindings/watchdog/faraday,ftwdt010.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Faraday Technology FTWDT010 watchdog maintainers: - - Linus Walleij + - Linus Walleij - Corentin Labbe description: | diff --git a/dts/upstream/Bindings/watchdog/lantiq,wdt.yaml b/dts/upstream/Bindings/watchdog/lantiq,wdt.yaml new file mode 100644 index 00000000000..a7edae9ca05 --- /dev/null +++ b/dts/upstream/Bindings/watchdog/lantiq,wdt.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/lantiq,wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq WTD watchdog + +maintainers: + - Hauke Mehrtens + +properties: + compatible: + oneOf: + - enum: + - lantiq,falcon-wdt + - lantiq,wdt + - lantiq,xrx100-wdt + - items: + - enum: + - lantiq,xrx200-wdt + - const: lantiq,xrx100-wdt + + reg: + maxItems: 1 + + lantiq,rcu: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the RCU syscon node + +required: + - compatible + - reg + +allOf: + - $ref: watchdog.yaml# + - if: + properties: + compatible: + contains: + enum: + - lantiq,xrx100-wdt + - lantiq,falcon-wdt + then: + required: + - lantiq,rcu + +unevaluatedProperties: false + +examples: + - | + watchdog@803f0 { + compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt"; + reg = <0x803f0 0x10>; + + lantiq,rcu = <&rcu0>; + }; diff --git a/dts/upstream/Bindings/watchdog/lantiq-wdt.txt b/dts/upstream/Bindings/watchdog/lantiq-wdt.txt deleted file mode 100644 index 18d4d830270..00000000000 --- a/dts/upstream/Bindings/watchdog/lantiq-wdt.txt +++ /dev/null @@ -1,24 +0,0 @@ -Lantiq WTD watchdog binding -============================ - -This describes the binding of the Lantiq watchdog driver. - -------------------------------------------------------------------------------- -Required properties: -- compatible : Should be one of - "lantiq,wdt" - "lantiq,xrx100-wdt" - "lantiq,xrx200-wdt", "lantiq,xrx100-wdt" - "lantiq,falcon-wdt" -- reg : Address of the watchdog block -- lantiq,rcu : A phandle to the RCU syscon (required for - "lantiq,falcon-wdt" and "lantiq,xrx100-wdt") - -------------------------------------------------------------------------------- -Example for the watchdog on the xRX200 SoCs: - watchdog@803f0 { - compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt"; - reg = <0x803f0 0x10>; - - lantiq,rcu = <&rcu0>; - }; diff --git a/dts/upstream/Bindings/watchdog/loongson,ls1x-wdt.yaml b/dts/upstream/Bindings/watchdog/loongson,ls1x-wdt.yaml index 81690d4b62a..50a9b468c4a 100644 --- a/dts/upstream/Bindings/watchdog/loongson,ls1x-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/loongson,ls1x-wdt.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/watchdog/loongson,ls1x-wdt.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Loongson-1 Watchdog Timer +title: Loongson Watchdog Timer maintainers: - Keguang Zhang @@ -17,6 +17,7 @@ properties: enum: - loongson,ls1b-wdt - loongson,ls1c-wdt + - loongson,ls2k0300-wdt reg: maxItems: 1 diff --git a/dts/upstream/Bindings/watchdog/marvel.txt b/dts/upstream/Bindings/watchdog/marvel.txt deleted file mode 100644 index c1b67a78f00..00000000000 --- a/dts/upstream/Bindings/watchdog/marvel.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Marvell Orion Watchdog Time - -Required Properties: - -- Compatibility : "marvell,orion-wdt" - "marvell,armada-370-wdt" - "marvell,armada-xp-wdt" - "marvell,armada-375-wdt" - "marvell,armada-380-wdt" - -- reg : Should contain two entries: first one with the - timer control address, second one with the - rstout enable address. - -For "marvell,armada-375-wdt" and "marvell,armada-380-wdt": - -- reg : A third entry is mandatory and should contain the - shared mask/unmask RSTOUT address. - -Clocks required for compatibles = "marvell,orion-wdt", - "marvell,armada-370-wdt": -- clocks : Must contain a single entry describing the clock input - -Clocks required for compatibles = "marvell,armada-xp-wdt" - "marvell,armada-375-wdt" - "marvell,armada-380-wdt": -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "nbclk" (L2/coherency fabric clock), - "fixed" (Reference 25 MHz fixed-clock). - -Optional properties: - -- interrupts : Contains the IRQ for watchdog expiration -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - - wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupts = <3>; - timeout-sec = <10>; - clocks = <&gate_clk 7>; - }; diff --git a/dts/upstream/Bindings/watchdog/marvell,orion-wdt.yaml b/dts/upstream/Bindings/watchdog/marvell,orion-wdt.yaml new file mode 100644 index 00000000000..fdc7bc45dfd --- /dev/null +++ b/dts/upstream/Bindings/watchdog/marvell,orion-wdt.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/marvell,orion-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion Watchdog Timer + +maintainers: + - Andrew Lunn + - Gregory Clement + +properties: + compatible: + enum: + - marvell,orion-wdt + - marvell,armada-370-wdt + - marvell,armada-xp-wdt + - marvell,armada-375-wdt + - marvell,armada-380-wdt + + reg: + minItems: 2 + items: + - description: Timer control register address + - description: RSTOUT enable register address + - description: Shared mask/unmask RSTOUT register address + + clocks: + minItems: 1 + items: + - description: L2/coherency fabric clock input + - description: Reference 25 MHz fixed-clock supply + + clock-names: + minItems: 1 + items: + - const: nbclk + - const: fixed + + interrupts: + minItems: 1 + items: + - description: timeout + - description: pre-timeout + +allOf: + - $ref: watchdog.yaml# + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-375-wdt + - marvell,armada-380-wdt + then: + properties: + reg: + minItems: 3 + else: + properties: + reg: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-xp-wdt + - marvell,armada-375-wdt + - marvell,armada-380-wdt + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + interrupts: + minItems: 2 + + required: + - clock-names + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + watchdog@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>, <0x20108 0x4>; + interrupts = <3>; + timeout-sec = <10>; + clocks = <&gate_clk 7>; + }; diff --git a/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml b/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml index 442c21f12a3..defe0401ded 100644 --- a/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml +++ b/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml @@ -8,7 +8,7 @@ title: Maxim 63xx Watchdog Timers maintainers: - Marc Zyngier - - Linus Walleij + - Linus Walleij allOf: - $ref: watchdog.yaml# diff --git a/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml b/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml index ba0bfd73ab6..953629cb955 100644 --- a/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml @@ -41,6 +41,8 @@ properties: - mediatek,mt7623-wdt - mediatek,mt7629-wdt - mediatek,mt8173-wdt + - mediatek,mt8188-wdt + - mediatek,mt8189-wdt - mediatek,mt8365-wdt - mediatek,mt8516-wdt - const: mediatek,mt6589-wdt diff --git a/dts/upstream/Bindings/watchdog/omap-wdt.txt b/dts/upstream/Bindings/watchdog/omap-wdt.txt deleted file mode 100644 index 1fa20e453a2..00000000000 --- a/dts/upstream/Bindings/watchdog/omap-wdt.txt +++ /dev/null @@ -1,15 +0,0 @@ -TI Watchdog Timer (WDT) Controller for OMAP - -Required properties: -- compatible : "ti,omap3-wdt" for OMAP3 or "ti,omap4-wdt" for OMAP4 -- ti,hwmods : Name of the hwmod associated to the WDT - -Optional properties: -- timeout-sec : default watchdog timeout in seconds - -Examples: - -wdt2: wdt@4a314000 { - compatible = "ti,omap4-wdt", "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; -}; diff --git a/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml b/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml index dc6af204e8a..a519422c371 100644 --- a/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm PM8916 watchdog timer controller maintainers: - - Krzysztof Kozlowski + - Krzysztof Kozlowski allOf: - $ref: watchdog.yaml# diff --git a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml index 49e2b807db0..54f5311ed01 100644 --- a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml @@ -22,6 +22,7 @@ properties: - qcom,apss-wdt-ipq5332 - qcom,apss-wdt-ipq5424 - qcom,apss-wdt-ipq9574 + - qcom,apss-wdt-kaanapali - qcom,apss-wdt-msm8226 - qcom,apss-wdt-msm8974 - qcom,apss-wdt-msm8994 diff --git a/dts/upstream/Bindings/watchdog/renesas,r9a09g057-wdt.yaml b/dts/upstream/Bindings/watchdog/renesas,r9a09g057-wdt.yaml new file mode 100644 index 00000000000..099200c4f13 --- /dev/null +++ b/dts/upstream/Bindings/watchdog/renesas,r9a09g057-wdt.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/renesas,r9a09g057-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) Watchdog Timer (WDT) Controller + +maintainers: + - Lad Prabhakar + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a09g047-wdt # RZ/G3E + - renesas,r9a09g056-wdt # RZ/V2N + - const: renesas,r9a09g057-wdt # RZ/V2H(P) + + - items: + - const: renesas,r9a09g087-wdt # RZ/N2H + - const: renesas,r9a09g077-wdt # RZ/T2H + + - enum: + - renesas,r9a09g057-wdt # RZ/V2H(P) + - renesas,r9a09g077-wdt # RZ/T2H + + reg: + minItems: 1 + maxItems: 2 + + clocks: + minItems: 1 + items: + - description: Register access clock + - description: Main clock + + clock-names: + minItems: 1 + items: + - const: pclk + - const: oscclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +allOf: + - $ref: watchdog.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-wdt + then: + properties: + reg: + maxItems: 1 + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + reg: + minItems: 2 + resets: false + +additionalProperties: false + +examples: + - | + #include + + watchdog@11c00400 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0x11c00400 0x400>; + clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x75>; + power-domains = <&cpg>; + }; diff --git a/dts/upstream/Bindings/watchdog/renesas,rcar-gen3-wwdt.yaml b/dts/upstream/Bindings/watchdog/renesas,rcar-gen3-wwdt.yaml new file mode 100644 index 00000000000..ffafe9a6d3f --- /dev/null +++ b/dts/upstream/Bindings/watchdog/renesas,rcar-gen3-wwdt.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/renesas,rcar-gen3-wwdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Window Watchdog Timer (WWDT) Controller + +maintainers: + - Wolfram Sang + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r8a77970-wwdt # R-Car V3M + - renesas,r8a77980-wwdt # R-Car V3H + - const: renesas,rcar-gen3-wwdt + + - items: + - enum: + - renesas,r8a779a0-wwdt # R-Car V3U + - renesas,r8a779f0-wwdt # R-Car S4 + - renesas,r8a779g0-wwdt # R-Car V4H + - renesas,r8a779h0-wwdt # R-Car V4M + - const: renesas,rcar-gen4-wwdt + + reg: + maxItems: 1 + + interrupts: + items: + - description: Pretimeout, 75% of overflow reached + - description: Error occurred + + interrupt-names: + items: + - const: pretimeout + - const: error + + clocks: + items: + - description: Counting clock + - description: Bus clock + + clock-names: + items: + - const: cnt + - const: bus + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: cnt + - const: bus + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + +allOf: + - $ref: watchdog.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,r8a779a0-wwdt + - renesas,r8a779f0-wwdt + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 + +additionalProperties: false + +examples: + - | + #include + #include + #include + + watchdog@ffc90000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0xffc90000 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1200>; + reset-names = "cnt"; + }; diff --git a/dts/upstream/Bindings/watchdog/renesas,rza-wdt.yaml b/dts/upstream/Bindings/watchdog/renesas,rza-wdt.yaml new file mode 100644 index 00000000000..ba922c3f7b1 --- /dev/null +++ b/dts/upstream/Bindings/watchdog/renesas,rza-wdt.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/renesas,rza-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A Watchdog Timer (WDT) Controller + +maintainers: + - Wolfram Sang + +properties: + compatible: + items: + - enum: + - renesas,r7s72100-wdt # RZ/A1 + - renesas,r7s9210-wdt # RZ/A2 + - const: renesas,rza-wdt # RZ/A + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - reg + - clocks + +allOf: + - $ref: watchdog.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + watchdog@fcfe0000 { + compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; + reg = <0xfcfe0000 0x6>; + interrupts = ; + clocks = <&p0_clk>; + }; diff --git a/dts/upstream/Bindings/watchdog/renesas,rzg2l-wdt.yaml b/dts/upstream/Bindings/watchdog/renesas,rzg2l-wdt.yaml new file mode 100644 index 00000000000..a4d06c9c8b8 --- /dev/null +++ b/dts/upstream/Bindings/watchdog/renesas,rzg2l-wdt.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/renesas,rzg2l-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Watchdog Timer (WDT) Controller + +maintainers: + - Biju Das + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a07g043-wdt # RZ/G2UL and RZ/Five + - renesas,r9a07g044-wdt # RZ/G2{L,LC} + - renesas,r9a07g054-wdt # RZ/V2L + - renesas,r9a08g045-wdt # RZ/G3S + - const: renesas,rzg2l-wdt + + - items: + - const: renesas,r9a09g011-wdt # RZ/V2M + - const: renesas,rzv2m-wdt # RZ/V2M + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + items: + - description: Timeout + - description: Parity error + + interrupt-names: + minItems: 1 + items: + - const: wdt + - const: perrout + + clocks: + items: + - description: Register access clock + - description: Main clock + + clock-names: + items: + - const: pclk + - const: oscclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +allOf: + - $ref: watchdog.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,rzg2l-wdt + then: + properties: + interrupts: + minItems: 2 + interrupt-names: + minItems: 2 + required: + - interrupt-names + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + + watchdog@12800800 { + compatible = "renesas,r9a07g044-wdt", + "renesas,rzg2l-wdt"; + reg = <0x12800800 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G044_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G044_WDT0_PRESETN>; + power-domains = <&cpg>; + }; diff --git a/dts/upstream/Bindings/watchdog/renesas,rzn1-wdt.yaml b/dts/upstream/Bindings/watchdog/renesas,rzn1-wdt.yaml new file mode 100644 index 00000000000..7e3ee533cd5 --- /dev/null +++ b/dts/upstream/Bindings/watchdog/renesas,rzn1-wdt.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/renesas,rzn1-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Watchdog Timer (WDT) Controller + +maintainers: + - Wolfram Sang + +properties: + compatible: + items: + - const: renesas,r9a06g032-wdt # RZ/N1D + - const: renesas,rzn1-wdt # RZ/N1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - $ref: watchdog.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + + watchdog@40008000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40008000 0x1000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + }; diff --git a/dts/upstream/Bindings/watchdog/renesas,wdt.yaml b/dts/upstream/Bindings/watchdog/renesas,wdt.yaml index b6e60162c26..7aebc5a5cf1 100644 --- a/dts/upstream/Bindings/watchdog/renesas,wdt.yaml +++ b/dts/upstream/Bindings/watchdog/renesas,wdt.yaml @@ -13,30 +13,6 @@ maintainers: properties: compatible: oneOf: - - items: - - enum: - - renesas,r7s72100-wdt # RZ/A1 - - renesas,r7s9210-wdt # RZ/A2 - - const: renesas,rza-wdt # RZ/A - - - items: - - enum: - - renesas,r9a06g032-wdt # RZ/N1D - - const: renesas,rzn1-wdt # RZ/N1 - - - items: - - enum: - - renesas,r9a07g043-wdt # RZ/G2UL and RZ/Five - - renesas,r9a07g044-wdt # RZ/G2{L,LC} - - renesas,r9a07g054-wdt # RZ/V2L - - renesas,r9a08g045-wdt # RZ/G3S - - const: renesas,rzg2l-wdt - - - items: - - enum: - - renesas,r9a09g011-wdt # RZ/V2M - - const: renesas,rzv2m-wdt # RZ/V2M - - items: - enum: - renesas,r8a7742-wdt # RZ/G1H @@ -75,47 +51,14 @@ properties: - renesas,r8a779h0-wdt # R-Car V4M - const: renesas,rcar-gen4-wdt # R-Car Gen4 - - items: - - enum: - - renesas,r9a09g047-wdt # RZ/G3E - - renesas,r9a09g056-wdt # RZ/V2N - - const: renesas,r9a09g057-wdt # RZ/V2H(P) - - - enum: - - renesas,r9a09g057-wdt # RZ/V2H(P) - - renesas,r9a09g077-wdt # RZ/T2H - - - items: - - const: renesas,r9a09g087-wdt # RZ/N2H - - const: renesas,r9a09g077-wdt # RZ/T2H - reg: - minItems: 1 - maxItems: 2 + maxItems: 1 interrupts: - minItems: 1 - items: - - description: Timeout - - description: Parity error - - interrupt-names: - minItems: 1 - items: - - const: wdt - - const: perrout + maxItems: 1 clocks: - minItems: 1 - items: - - description: Register access clock - - description: Main clock - - clock-names: - minItems: 1 - items: - - const: pclk - - const: oscclk + maxItems: 1 power-domains: maxItems: 1 @@ -129,6 +72,8 @@ required: - compatible - reg - clocks + - interrupts + - power-domains allOf: - $ref: watchdog.yaml# @@ -138,90 +83,11 @@ allOf: properties: compatible: contains: - enum: - - renesas,r9a09g077-wdt - - renesas,rza-wdt - - renesas,rzn1-wdt + const: renesas,r8a77980-wdt then: required: - - power-domains - resets - - if: - properties: - compatible: - contains: - enum: - - renesas,r9a09g057-wdt - - renesas,rzg2l-wdt - - renesas,rzv2m-wdt - then: - properties: - clocks: - minItems: 2 - clock-names: - minItems: 2 - required: - - clock-names - else: - properties: - clocks: - maxItems: 1 - - - if: - properties: - compatible: - contains: - enum: - - renesas,rzg2l-wdt - then: - properties: - interrupts: - minItems: 2 - interrupt-names: - minItems: 2 - required: - - interrupt-names - else: - properties: - interrupts: - maxItems: 1 - - - if: - properties: - compatible: - contains: - enum: - - renesas,r9a09g057-wdt - - renesas,r9a09g077-wdt - then: - properties: - interrupts: false - interrupt-names: false - else: - required: - - interrupts - - - if: - properties: - compatible: - contains: - const: renesas,r9a09g077-wdt - then: - properties: - resets: false - clock-names: - maxItems: 1 - reg: - minItems: 2 - required: - - clock-names - - power-domains - else: - properties: - reg: - maxItems: 1 - additionalProperties: false examples: diff --git a/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml b/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml index ef088e0f691..609e98cdaaf 100644 --- a/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml +++ b/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml @@ -28,6 +28,7 @@ properties: - rockchip,rk3328-wdt - rockchip,rk3368-wdt - rockchip,rk3399-wdt + - rockchip,rk3506-wdt - rockchip,rk3562-wdt - rockchip,rk3568-wdt - rockchip,rk3576-wdt diff --git a/dts/upstream/Bindings/watchdog/ti,omap2-wdt.yaml b/dts/upstream/Bindings/watchdog/ti,omap2-wdt.yaml new file mode 100644 index 00000000000..913b55222f2 --- /dev/null +++ b/dts/upstream/Bindings/watchdog/ti,omap2-wdt.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/ti,omap2-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP Watchdog Timer Controller + +maintainers: + - Aaro Koskinen + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - enum: + - ti,omap2-wdt + - ti,omap3-wdt + - items: + - enum: + - ti,am4372-wdt + - ti,omap4-wdt + - ti,omap5-wdt + - const: ti,omap3-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ti,hwmods: + description: Name of the hardware module associated with the watchdog. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@48314000 { + compatible = "ti,omap3-wdt"; + reg = <0x48314000 0x80>; + ti,hwmods = "wd_timer2"; + }; diff --git a/dts/upstream/Bindings/watchdog/watchdog.yaml b/dts/upstream/Bindings/watchdog/watchdog.yaml index f0a584af122..77ac23516d6 100644 --- a/dts/upstream/Bindings/watchdog/watchdog.yaml +++ b/dts/upstream/Bindings/watchdog/watchdog.yaml @@ -21,9 +21,10 @@ select: properties: $nodename: - pattern: "^(timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$" + pattern: "^(pmic|timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$" timeout-sec: + maxItems: 1 description: Contains the watchdog timeout in seconds. diff --git a/dts/upstream/include/dt-bindings/arm/qcom,ids.h b/dts/upstream/include/dt-bindings/arm/qcom,ids.h index cb8ce53146f..8776844e0ee 100644 --- a/dts/upstream/include/dt-bindings/arm/qcom,ids.h +++ b/dts/upstream/include/dt-bindings/arm/qcom,ids.h @@ -240,6 +240,7 @@ #define QCOM_ID_SC7280 487 #define QCOM_ID_SC7180P 495 #define QCOM_ID_QCM6490 497 +#define QCOM_ID_QCS6490 498 #define QCOM_ID_SM7325P 499 #define QCOM_ID_IPQ5000 503 #define QCOM_ID_IPQ0509 504 @@ -286,6 +287,7 @@ #define QCOM_ID_IPQ5424 651 #define QCOM_ID_QCM6690 657 #define QCOM_ID_QCS6690 658 +#define QCOM_ID_SM8850 660 #define QCOM_ID_IPQ5404 671 #define QCOM_ID_QCS9100 667 #define QCOM_ID_QCS8300 674 diff --git a/dts/upstream/include/dt-bindings/clock/google,gs101-acpm.h b/dts/upstream/include/dt-bindings/clock/google,gs101-acpm.h new file mode 100644 index 00000000000..e2ba89e09fa --- /dev/null +++ b/dts/upstream/include/dt-bindings/clock/google,gs101-acpm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025 Linaro Ltd. + * + * Device Tree binding constants for Google gs101 ACPM clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H +#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H + +#define GS101_CLK_ACPM_DVFS_MIF 0 +#define GS101_CLK_ACPM_DVFS_INT 1 +#define GS101_CLK_ACPM_DVFS_CPUCL0 2 +#define GS101_CLK_ACPM_DVFS_CPUCL1 3 +#define GS101_CLK_ACPM_DVFS_CPUCL2 4 +#define GS101_CLK_ACPM_DVFS_G3D 5 +#define GS101_CLK_ACPM_DVFS_G3DL2 6 +#define GS101_CLK_ACPM_DVFS_TPU 7 +#define GS101_CLK_ACPM_DVFS_INTCAM 8 +#define GS101_CLK_ACPM_DVFS_TNR 9 +#define GS101_CLK_ACPM_DVFS_CAM 10 +#define GS101_CLK_ACPM_DVFS_MFC 11 +#define GS101_CLK_ACPM_DVFS_DISP 12 +#define GS101_CLK_ACPM_DVFS_BO 13 + +#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */ diff --git a/dts/upstream/include/dt-bindings/clock/imx8ulp-clock.h b/dts/upstream/include/dt-bindings/clock/imx8ulp-clock.h index 827404fadf5..c62d84d093a 100644 --- a/dts/upstream/include/dt-bindings/clock/imx8ulp-clock.h +++ b/dts/upstream/include/dt-bindings/clock/imx8ulp-clock.h @@ -255,4 +255,9 @@ #define IMX8ULP_CLK_PCC5_END 56 +/* LPAV SIM */ +#define IMX8ULP_CLK_SIM_LPAV_HIFI_CORE 0 +#define IMX8ULP_CLK_SIM_LPAV_HIFI_PBCLK 1 +#define IMX8ULP_CLK_SIM_LPAV_HIFI_PLAT 2 + #endif diff --git a/dts/upstream/include/dt-bindings/clock/qcom,dispcc-sm6350.h b/dts/upstream/include/dt-bindings/clock/qcom,dispcc-sm6350.h index cb54aae2723..61426a80e62 100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,dispcc-sm6350.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,dispcc-sm6350.h @@ -42,6 +42,10 @@ #define DISP_CC_SLEEP_CLK 31 #define DISP_CC_XO_CLK 32 +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + /* GDSCs */ #define MDSS_GDSC 0 diff --git a/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h index c15ad16923b..3ae33a0fa00 100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H @@ -152,5 +152,6 @@ #define GCC_PCIE3_RCHNG_CLK 143 #define GCC_IM_SLEEP_CLK 144 #define GCC_XO_CLK 145 +#define GPLL0_OUT_AUX 146 #endif diff --git a/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-nsscc.h b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-nsscc.h new file mode 100644 index 00000000000..eeae0dc3804 --- /dev/null +++ b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-nsscc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H + +/* NSS_CC clocks */ +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_DEBUG_CLK 4 +#define NSS_CC_EIP_BFDCD_CLK_SRC 5 +#define NSS_CC_EIP_CLK 6 +#define NSS_CC_NSS_CSR_CLK 7 +#define NSS_CC_NSSNOC_CE_APB_CLK 8 +#define NSS_CC_NSSNOC_CE_AXI_CLK 9 +#define NSS_CC_NSSNOC_EIP_CLK 10 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 11 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 12 +#define NSS_CC_NSSNOC_PPE_CLK 13 +#define NSS_CC_PORT1_MAC_CLK 14 +#define NSS_CC_PORT1_RX_CLK 15 +#define NSS_CC_PORT1_RX_CLK_SRC 16 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 +#define NSS_CC_PORT1_TX_CLK 18 +#define NSS_CC_PORT1_TX_CLK_SRC 19 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 +#define NSS_CC_PORT2_MAC_CLK 21 +#define NSS_CC_PORT2_RX_CLK 22 +#define NSS_CC_PORT2_RX_CLK_SRC 23 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 +#define NSS_CC_PORT2_TX_CLK 25 +#define NSS_CC_PORT2_TX_CLK_SRC 26 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 +#define NSS_CC_PORT3_MAC_CLK 28 +#define NSS_CC_PORT3_RX_CLK 29 +#define NSS_CC_PORT3_RX_CLK_SRC 30 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 31 +#define NSS_CC_PORT3_TX_CLK 32 +#define NSS_CC_PORT3_TX_CLK_SRC 33 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_CC_PPE_CLK_SRC 35 +#define NSS_CC_PPE_EDMA_CFG_CLK 36 +#define NSS_CC_PPE_EDMA_CLK 37 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 38 +#define NSS_CC_PPE_SWITCH_CFG_CLK 39 +#define NSS_CC_PPE_SWITCH_CLK 40 +#define NSS_CC_PPE_SWITCH_IPE_CLK 41 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 42 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 43 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 44 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 45 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 46 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 47 +#define NSS_CC_XGMAC0_PTP_REF_CLK 48 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49 +#define NSS_CC_XGMAC1_PTP_REF_CLK 50 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51 +#define NSS_CC_XGMAC2_PTP_REF_CLK 52 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53 + +#endif diff --git a/dts/upstream/include/dt-bindings/clock/qcom,kaanapali-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,kaanapali-gcc.h new file mode 100644 index 00000000000..890e48709f0 --- /dev/null +++ b/dts/upstream/include/dt-bindings/clock/qcom,kaanapali-gcc.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 1 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2 +#define GCC_BOOT_ROM_AHB_CLK 3 +#define GCC_CAM_BIST_MCLK_AHB_CLK 4 +#define GCC_CAMERA_AHB_CLK 5 +#define GCC_CAMERA_HF_AXI_CLK 6 +#define GCC_CAMERA_SF_AXI_CLK 7 +#define GCC_CAMERA_XO_CLK 8 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 +#define GCC_CNOC_PCIE_SF_AXI_CLK 11 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 12 +#define GCC_QMIP_CAMERA_CMD_AHB_CLK 13 +#define GCC_DISP_HF_AXI_CLK 14 +#define GCC_DISP_SF_AXI_CLK 15 +#define GCC_EVA_AHB_CLK 16 +#define GCC_EVA_AXI0_CLK 17 +#define GCC_EVA_AXI0C_CLK 18 +#define GCC_EVA_XO_CLK 19 +#define GCC_GP1_CLK 20 +#define GCC_GP1_CLK_SRC 21 +#define GCC_GP2_CLK 22 +#define GCC_GP2_CLK_SRC 23 +#define GCC_GP3_CLK 24 +#define GCC_GP3_CLK_SRC 25 +#define GCC_GPLL0 26 +#define GCC_GPLL0_OUT_EVEN 27 +#define GCC_GPLL1 28 +#define GCC_GPLL4 29 +#define GCC_GPLL7 30 +#define GCC_GPLL9 31 +#define GCC_GPU_CFG_AHB_CLK 32 +#define GCC_GPU_GEMNOC_GFX_CLK 33 +#define GCC_GPU_GPLL0_CLK_SRC 34 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 35 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 36 +#define GCC_QMIP_GPU_AHB_CLK 37 +#define GCC_PCIE_0_AUX_CLK 38 +#define GCC_PCIE_0_AUX_CLK_SRC 39 +#define GCC_PCIE_0_CFG_AHB_CLK 40 +#define GCC_PCIE_0_MSTR_AXI_CLK 41 +#define GCC_PCIE_0_PHY_AUX_CLK 42 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 43 +#define GCC_PCIE_0_PHY_RCHNG_CLK 44 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45 +#define GCC_PCIE_0_PIPE_CLK 46 +#define GCC_PCIE_0_PIPE_CLK_SRC 47 +#define GCC_PCIE_0_SLV_AXI_CLK 48 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49 +#define GCC_PCIE_RSCC_CFG_AHB_CLK 50 +#define GCC_PCIE_RSCC_XO_CLK 51 +#define GCC_PDM2_CLK 52 +#define GCC_PDM2_CLK_SRC 53 +#define GCC_PDM_AHB_CLK 54 +#define GCC_PDM_XO4_CLK 55 +#define GCC_QUPV3_I2C_CORE_CLK 56 +#define GCC_QUPV3_I2C_S0_CLK 57 +#define GCC_QUPV3_I2C_S0_CLK_SRC 58 +#define GCC_QUPV3_I2C_S1_CLK 59 +#define GCC_QUPV3_I2C_S1_CLK_SRC 60 +#define GCC_QUPV3_I2C_S2_CLK 61 +#define GCC_QUPV3_I2C_S2_CLK_SRC 62 +#define GCC_QUPV3_I2C_S3_CLK 63 +#define GCC_QUPV3_I2C_S3_CLK_SRC 64 +#define GCC_QUPV3_I2C_S4_CLK 65 +#define GCC_QUPV3_I2C_S4_CLK_SRC 66 +#define GCC_QUPV3_I2C_S_AHB_CLK 67 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 68 +#define GCC_QUPV3_WRAP1_CORE_CLK 69 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 70 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 71 +#define GCC_QUPV3_WRAP1_S0_CLK 72 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 +#define GCC_QUPV3_WRAP1_S1_CLK 74 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S2_CLK 76 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S3_CLK 78 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S4_CLK 80 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S5_CLK 82 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_S6_CLK 84 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_S7_CLK 86 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 87 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 88 +#define GCC_QUPV3_WRAP2_CORE_CLK 89 +#define GCC_QUPV3_WRAP2_S0_CLK 90 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 91 +#define GCC_QUPV3_WRAP2_S1_CLK 92 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 93 +#define GCC_QUPV3_WRAP2_S2_CLK 94 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 95 +#define GCC_QUPV3_WRAP2_S3_CLK 96 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 97 +#define GCC_QUPV3_WRAP2_S4_CLK 98 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 99 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 100 +#define GCC_QUPV3_WRAP3_CORE_CLK 101 +#define GCC_QUPV3_WRAP3_IBI_CTRL_0_CLK_SRC 102 +#define GCC_QUPV3_WRAP3_IBI_CTRL_1_CLK 103 +#define GCC_QUPV3_WRAP3_IBI_CTRL_2_CLK 104 +#define GCC_QUPV3_WRAP3_S0_CLK 105 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 106 +#define GCC_QUPV3_WRAP3_S1_CLK 107 +#define GCC_QUPV3_WRAP3_S1_CLK_SRC 108 +#define GCC_QUPV3_WRAP3_S2_CLK 109 +#define GCC_QUPV3_WRAP3_S2_CLK_SRC 110 +#define GCC_QUPV3_WRAP3_S3_CLK 111 +#define GCC_QUPV3_WRAP3_S3_CLK_SRC 112 +#define GCC_QUPV3_WRAP3_S4_CLK 113 +#define GCC_QUPV3_WRAP3_S4_CLK_SRC 114 +#define GCC_QUPV3_WRAP3_S5_CLK 115 +#define GCC_QUPV3_WRAP3_S5_CLK_SRC 116 +#define GCC_QUPV3_WRAP4_CORE_2X_CLK 117 +#define GCC_QUPV3_WRAP4_CORE_CLK 118 +#define GCC_QUPV3_WRAP4_S0_CLK 119 +#define GCC_QUPV3_WRAP4_S0_CLK_SRC 120 +#define GCC_QUPV3_WRAP4_S1_CLK 121 +#define GCC_QUPV3_WRAP4_S1_CLK_SRC 122 +#define GCC_QUPV3_WRAP4_S2_CLK 123 +#define GCC_QUPV3_WRAP4_S2_CLK_SRC 124 +#define GCC_QUPV3_WRAP4_S3_CLK 125 +#define GCC_QUPV3_WRAP4_S3_CLK_SRC 126 +#define GCC_QUPV3_WRAP4_S4_CLK 127 +#define GCC_QUPV3_WRAP4_S4_CLK_SRC 128 +#define GCC_QUPV3_WRAP_1_M_AXI_CLK 129 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 130 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 131 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 132 +#define GCC_QUPV3_WRAP_3_IBI_1_AHB_CLK 133 +#define GCC_QUPV3_WRAP_3_IBI_2_AHB_CLK 134 +#define GCC_QUPV3_WRAP_3_M_AHB_CLK 135 +#define GCC_QUPV3_WRAP_3_S_AHB_CLK 136 +#define GCC_QUPV3_WRAP_4_M_AHB_CLK 137 +#define GCC_QUPV3_WRAP_4_S_AHB_CLK 138 +#define GCC_SDCC2_AHB_CLK 139 +#define GCC_SDCC2_APPS_CLK 140 +#define GCC_SDCC2_APPS_CLK_SRC 141 +#define GCC_SDCC4_AHB_CLK 142 +#define GCC_SDCC4_APPS_CLK 143 +#define GCC_SDCC4_APPS_CLK_SRC 144 +#define GCC_UFS_PHY_AHB_CLK 145 +#define GCC_UFS_PHY_AXI_CLK 146 +#define GCC_UFS_PHY_AXI_CLK_SRC 147 +#define GCC_UFS_PHY_ICE_CORE_CLK 148 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 149 +#define GCC_UFS_PHY_PHY_AUX_CLK 150 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 151 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 152 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 153 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 154 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 155 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 156 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 157 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 158 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 159 +#define GCC_USB30_PRIM_MASTER_CLK 160 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 161 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 162 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 163 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 164 +#define GCC_USB30_PRIM_SLEEP_CLK 165 +#define GCC_USB3_PRIM_PHY_AUX_CLK 166 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 167 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 168 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 169 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 170 +#define GCC_VIDEO_AHB_CLK 171 +#define GCC_VIDEO_AXI0_CLK 172 +#define GCC_VIDEO_AXI1_CLK 173 +#define GCC_VIDEO_XO_CLK 174 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 175 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 176 +#define GCC_QMIP_DISP_DCP_SF_AHB_CLK 177 +#define GCC_QMIP_PCIE_AHB_CLK 178 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 179 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 180 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 181 +#define GCC_DISP_AHB_CLK 182 + +/* GCC power domains */ +#define GCC_PCIE_0_GDSC 0 +#define GCC_PCIE_0_PHY_GDSC 1 +#define GCC_UFS_MEM_PHY_GDSC 2 +#define GCC_UFS_PHY_GDSC 3 +#define GCC_USB30_PRIM_GDSC 4 +#define GCC_USB3_PHY_GDSC 5 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_EVA_AXI0_CLK_ARES 2 +#define GCC_EVA_AXI0C_CLK_ARES 3 +#define GCC_EVA_BCR 4 +#define GCC_GPU_BCR 5 +#define GCC_PCIE_0_BCR 6 +#define GCC_PCIE_0_LINK_DOWN_BCR 7 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_0_PHY_BCR 9 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_PHY_BCR 11 +#define GCC_PCIE_PHY_CFG_AHB_BCR 12 +#define GCC_PCIE_PHY_COM_BCR 13 +#define GCC_PCIE_RSCC_BCR 14 +#define GCC_PDM_BCR 15 +#define GCC_QUPV3_WRAPPER_1_BCR 16 +#define GCC_QUPV3_WRAPPER_2_BCR 17 +#define GCC_QUPV3_WRAPPER_3_BCR 18 +#define GCC_QUPV3_WRAPPER_4_BCR 19 +#define GCC_QUPV3_WRAPPER_I2C_BCR 20 +#define GCC_QUSB2PHY_PRIM_BCR 21 +#define GCC_QUSB2PHY_SEC_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_SDCC4_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_PRIM_BCR 27 +#define GCC_USB3_DP_PHY_SEC_BCR 28 +#define GCC_USB3_PHY_PRIM_BCR 29 +#define GCC_USB3_PHY_SEC_BCR 30 +#define GCC_USB3PHY_PHY_PRIM_BCR 31 +#define GCC_USB3PHY_PHY_SEC_BCR 32 +#define GCC_VIDEO_AXI0_CLK_ARES 33 +#define GCC_VIDEO_AXI1_CLK_ARES 34 +#define GCC_VIDEO_BCR 35 +#define GCC_VIDEO_XO_CLK_ARES 36 + +#endif diff --git a/dts/upstream/include/dt-bindings/clock/qcom,mmcc-sdm660.h b/dts/upstream/include/dt-bindings/clock/qcom,mmcc-sdm660.h index f9dbc21cb5c..ee2a89dae72 100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,mmcc-sdm660.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,mmcc-sdm660.h @@ -157,6 +157,7 @@ #define BIMC_SMMU_GDSC 7 #define CAMSS_MICRO_BCR 0 +#define MDSS_BCR 1 #endif diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-dispcc.h index fc1fefe8fd7..1e4e6432d50 100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,sm7150-dispcc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-dispcc.h @@ -53,6 +53,9 @@ #define DISPCC_SLEEP_CLK 41 #define DISPCC_SLEEP_CLK_SRC 42 +/* DISPCC resets */ +#define DISPCC_MDSS_CORE_BCR 0 + /* DISPCC GDSCR */ #define MDSS_GDSC 0 diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8750-videocc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-videocc.h new file mode 100644 index 00000000000..f3bfa2ba516 --- /dev/null +++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-videocc.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0_FREERUN_CLK 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_FREERUN_CLK 9 +#define VIDEO_CC_MVS0C_SHIFT_CLK 10 +#define VIDEO_CC_PLL0 11 +#define VIDEO_CC_SLEEP_CLK 12 +#define VIDEO_CC_SLEEP_CLK_SRC 13 +#define VIDEO_CC_XO_CLK 14 +#define VIDEO_CC_XO_CLK_SRC 15 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4 +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 5 +#define VIDEO_CC_XO_CLK_ARES 6 + +#endif diff --git a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-dispcc.h b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-dispcc.h index d4a83e4fd0d..49b3a9e5ce4 100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-dispcc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-dispcc.h @@ -90,6 +90,9 @@ #define DISP_CC_MDSS_CORE_BCR 0 #define DISP_CC_MDSS_CORE_INT2_BCR 1 #define DISP_CC_MDSS_RSCC_BCR 2 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK_ARES 3 +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK_ARES 4 +#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK_ARES 5 /* DISP_CC GDSCR */ #define MDSS_GDSC 0 diff --git a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gcc.h index 710c340f24a..62aa1242559 100644 --- a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gcc.h +++ b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gcc.h @@ -363,6 +363,30 @@ #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354 #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355 +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356 +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357 +#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358 +#define GCC_USB4_0_PHY_DP0_CLK_SRC 359 +#define GCC_USB4_0_PHY_DP1_CLK_SRC 360 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361 +#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362 +#define GCC_USB4_0_PHY_RX0_CLK_SRC 363 +#define GCC_USB4_0_PHY_RX1_CLK_SRC 364 +#define GCC_USB4_0_PHY_SYS_CLK_SRC 365 +#define GCC_USB4_1_PHY_DP0_CLK_SRC 366 +#define GCC_USB4_1_PHY_DP1_CLK_SRC 367 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368 +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369 +#define GCC_USB4_1_PHY_RX0_CLK_SRC 370 +#define GCC_USB4_1_PHY_RX1_CLK_SRC 371 +#define GCC_USB4_1_PHY_SYS_CLK_SRC 372 +#define GCC_USB4_2_PHY_DP0_CLK_SRC 373 +#define GCC_USB4_2_PHY_DP1_CLK_SRC 374 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375 +#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376 +#define GCC_USB4_2_PHY_RX0_CLK_SRC 377 +#define GCC_USB4_2_PHY_RX1_CLK_SRC 378 +#define GCC_USB4_2_PHY_SYS_CLK_SRC 379 /* GCC power domains */ #define GCC_PCIE_0_TUNNEL_GDSC 0 @@ -484,4 +508,41 @@ #define GCC_VIDEO_BCR 87 #define GCC_VIDEO_AXI0_CLK_ARES 88 #define GCC_VIDEO_AXI1_CLK_ARES 89 +#define GCC_USB4_0_MISC_USB4_SYS_BCR 90 +#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91 +#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92 +#define GCC_USB4_0_MISC_USB_PIPE_BCR 93 +#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94 +#define GCC_USB4_0_MISC_TMU_BCR 95 +#define GCC_USB4_0_MISC_SB_IF_BCR 96 +#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97 +#define GCC_USB4_0_MISC_AHB_BCR 98 +#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99 +#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100 +#define GCC_USB4_1_MISC_USB4_SYS_BCR 101 +#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102 +#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103 +#define GCC_USB4_1_MISC_USB_PIPE_BCR 104 +#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105 +#define GCC_USB4_1_MISC_TMU_BCR 106 +#define GCC_USB4_1_MISC_SB_IF_BCR 107 +#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108 +#define GCC_USB4_1_MISC_AHB_BCR 109 +#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110 +#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111 +#define GCC_USB4_2_MISC_USB4_SYS_BCR 112 +#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113 +#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114 +#define GCC_USB4_2_MISC_USB_PIPE_BCR 115 +#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116 +#define GCC_USB4_2_MISC_TMU_BCR 117 +#define GCC_USB4_2_MISC_SB_IF_BCR 118 +#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119 +#define GCC_USB4_2_MISC_AHB_BCR 120 +#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121 +#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122 +#define GCC_USB4PHY_PHY_PRIM_BCR 123 +#define GCC_USB4PHY_PHY_SEC_BCR 124 +#define GCC_USB4PHY_PHY_TERT_BCR 125 + #endif diff --git a/dts/upstream/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/dts/upstream/include/dt-bindings/clock/r8a779a0-cpg-mssr.h index f1d737ca7ca..124a6b8856d 100644 --- a/dts/upstream/include/dt-bindings/clock/r8a779a0-cpg-mssr.h +++ b/dts/upstream/include/dt-bindings/clock/r8a779a0-cpg-mssr.h @@ -51,5 +51,6 @@ #define R8A779A0_CLK_CBFUSA 40 #define R8A779A0_CLK_R 41 #define R8A779A0_CLK_OSC 42 +#define R8A779A0_CLK_ZG 43 #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ diff --git a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h index f165df8a6f5..dab24740de3 100644 --- a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h +++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -22,5 +22,7 @@ #define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 #define R9A09G047_USB3_0_REF_ALT_CLK_P 12 #define R9A09G047_USB3_0_CLKCORE 13 +#define R9A09G047_USB2_0_CLK_CORE0 14 +#define R9A09G047_USB2_0_CLK_CORE1 15 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ diff --git a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g056-cpg.h index a9af5af9e3a..234dcf4f0f9 100644 --- a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g056-cpg.h +++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g056-cpg.h @@ -21,5 +21,7 @@ #define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 #define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 #define R9A09G056_SPI_CLK_SPI 12 +#define R9A09G056_USB3_0_REF_ALT_CLK_P 13 +#define R9A09G056_USB3_0_CLKCORE 14 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ diff --git a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g057-cpg.h index 5346a898ab6..f91d7f72922 100644 --- a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g057-cpg.h +++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g057-cpg.h @@ -22,5 +22,9 @@ #define R9A09G057_GBETH_0_CLK_PTP_REF_I 11 #define R9A09G057_GBETH_1_CLK_PTP_REF_I 12 #define R9A09G057_SPI_CLK_SPI 13 +#define R9A09G057_USB3_0_REF_ALT_CLK_P 14 +#define R9A09G057_USB3_0_CLKCORE 15 +#define R9A09G057_USB3_1_REF_ALT_CLK_P 16 +#define R9A09G057_USB3_1_CLKCORE 17 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ diff --git a/dts/upstream/include/dt-bindings/clock/rk3568-cru.h b/dts/upstream/include/dt-bindings/clock/rk3568-cru.h index 5263085c5b2..1e0aef8a645 100644 --- a/dts/upstream/include/dt-bindings/clock/rk3568-cru.h +++ b/dts/upstream/include/dt-bindings/clock/rk3568-cru.h @@ -483,7 +483,11 @@ #define PCLK_CORE_PVTM 450 -#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) +/* scmi-clocks indices */ + +#define SCMI_CLK_CPU 0 +#define SCMI_CLK_GPU 1 +#define SCMI_CLK_NPU 2 /* pmu soft-reset indices */ /* pmucru_softrst_con0 */ diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3506-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3506-cru.h new file mode 100644 index 00000000000..71d7dda23cc --- /dev/null +++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3506-cru.h @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H + +/* cru plls */ +#define PLL_GPLL 0 +#define PLL_V0PLL 1 +#define PLL_V1PLL 2 + +/* cru-clocks indices */ +#define ARMCLK 3 +#define CLK_DDR 4 +#define XIN24M_GATE 5 +#define CLK_GPLL_GATE 6 +#define CLK_V0PLL_GATE 7 +#define CLK_V1PLL_GATE 8 +#define CLK_GPLL_DIV 9 +#define CLK_GPLL_DIV_100M 10 +#define CLK_V0PLL_DIV 11 +#define CLK_V1PLL_DIV 12 +#define CLK_INT_VOICE_MATRIX0 13 +#define CLK_INT_VOICE_MATRIX1 14 +#define CLK_INT_VOICE_MATRIX2 15 +#define CLK_FRAC_UART_MATRIX0_MUX 16 +#define CLK_FRAC_UART_MATRIX1_MUX 17 +#define CLK_FRAC_VOICE_MATRIX0_MUX 18 +#define CLK_FRAC_VOICE_MATRIX1_MUX 19 +#define CLK_FRAC_COMMON_MATRIX0_MUX 20 +#define CLK_FRAC_COMMON_MATRIX1_MUX 21 +#define CLK_FRAC_COMMON_MATRIX2_MUX 22 +#define CLK_FRAC_UART_MATRIX0 23 +#define CLK_FRAC_UART_MATRIX1 24 +#define CLK_FRAC_VOICE_MATRIX0 25 +#define CLK_FRAC_VOICE_MATRIX1 26 +#define CLK_FRAC_COMMON_MATRIX0 27 +#define CLK_FRAC_COMMON_MATRIX1 28 +#define CLK_FRAC_COMMON_MATRIX2 29 +#define CLK_REF_USBPHY_TOP 30 +#define CLK_REF_DPHY_TOP 31 +#define ACLK_CORE_ROOT 32 +#define PCLK_CORE_ROOT 33 +#define PCLK_DBG 34 +#define PCLK_CORE_GRF 35 +#define PCLK_CORE_CRU 36 +#define CLK_CORE_EMA_DETECT 37 +#define CLK_REF_PVTPLL_CORE 38 +#define PCLK_GPIO1 39 +#define DBCLK_GPIO1 40 +#define ACLK_CORE_PERI_ROOT 41 +#define HCLK_CORE_PERI_ROOT 42 +#define PCLK_CORE_PERI_ROOT 43 +#define CLK_DSMC 44 +#define ACLK_DSMC 45 +#define PCLK_DSMC 46 +#define CLK_FLEXBUS_TX 47 +#define CLK_FLEXBUS_RX 48 +#define ACLK_FLEXBUS 49 +#define HCLK_FLEXBUS 50 +#define ACLK_DSMC_SLV 51 +#define HCLK_DSMC_SLV 52 +#define ACLK_BUS_ROOT 53 +#define HCLK_BUS_ROOT 54 +#define PCLK_BUS_ROOT 55 +#define ACLK_SYSRAM 56 +#define HCLK_SYSRAM 57 +#define ACLK_DMAC0 58 +#define ACLK_DMAC1 59 +#define HCLK_M0 60 +#define PCLK_BUS_GRF 61 +#define PCLK_TIMER 62 +#define CLK_TIMER0_CH0 63 +#define CLK_TIMER0_CH1 64 +#define CLK_TIMER0_CH2 65 +#define CLK_TIMER0_CH3 66 +#define CLK_TIMER0_CH4 67 +#define CLK_TIMER0_CH5 68 +#define PCLK_WDT0 69 +#define TCLK_WDT0 70 +#define PCLK_WDT1 71 +#define TCLK_WDT1 72 +#define PCLK_MAILBOX 73 +#define PCLK_INTMUX 74 +#define PCLK_SPINLOCK 75 +#define PCLK_DDRC 76 +#define HCLK_DDRPHY 77 +#define PCLK_DDRMON 78 +#define CLK_DDRMON_OSC 79 +#define PCLK_STDBY 80 +#define HCLK_USBOTG0 81 +#define HCLK_USBOTG0_PMU 82 +#define CLK_USBOTG0_ADP 83 +#define HCLK_USBOTG1 84 +#define HCLK_USBOTG1_PMU 85 +#define CLK_USBOTG1_ADP 86 +#define PCLK_USBPHY 87 +#define ACLK_DMA2DDR 88 +#define PCLK_DMA2DDR 89 +#define STCLK_M0 90 +#define CLK_DDRPHY 91 +#define CLK_DDRC_SRC 92 +#define ACLK_DDRC_0 93 +#define ACLK_DDRC_1 94 +#define CLK_DDRC 95 +#define CLK_DDRMON 96 +#define HCLK_LSPERI_ROOT 97 +#define PCLK_LSPERI_ROOT 98 +#define PCLK_UART0 99 +#define PCLK_UART1 100 +#define PCLK_UART2 101 +#define PCLK_UART3 102 +#define PCLK_UART4 103 +#define SCLK_UART0 104 +#define SCLK_UART1 105 +#define SCLK_UART2 106 +#define SCLK_UART3 107 +#define SCLK_UART4 108 +#define PCLK_I2C0 109 +#define CLK_I2C0 110 +#define PCLK_I2C1 111 +#define CLK_I2C1 112 +#define PCLK_I2C2 113 +#define CLK_I2C2 114 +#define PCLK_PWM1 115 +#define CLK_PWM1 116 +#define CLK_OSC_PWM1 117 +#define CLK_RC_PWM1 118 +#define CLK_FREQ_PWM1 119 +#define CLK_COUNTER_PWM1 120 +#define PCLK_SPI0 121 +#define CLK_SPI0 122 +#define PCLK_SPI1 123 +#define CLK_SPI1 124 +#define PCLK_GPIO2 125 +#define DBCLK_GPIO2 126 +#define PCLK_GPIO3 127 +#define DBCLK_GPIO3 128 +#define PCLK_GPIO4 129 +#define DBCLK_GPIO4 130 +#define HCLK_CAN0 131 +#define CLK_CAN0 132 +#define HCLK_CAN1 133 +#define CLK_CAN1 134 +#define HCLK_PDM 135 +#define MCLK_PDM 136 +#define CLKOUT_PDM 137 +#define MCLK_SPDIFTX 138 +#define HCLK_SPDIFTX 139 +#define HCLK_SPDIFRX 140 +#define MCLK_SPDIFRX 141 +#define MCLK_SAI0 142 +#define HCLK_SAI0 143 +#define MCLK_OUT_SAI0 144 +#define MCLK_SAI1 145 +#define HCLK_SAI1 146 +#define MCLK_OUT_SAI1 147 +#define HCLK_ASRC0 148 +#define CLK_ASRC0 149 +#define HCLK_ASRC1 150 +#define CLK_ASRC1 151 +#define PCLK_CRU 152 +#define PCLK_PMU_ROOT 153 +#define MCLK_ASRC0 154 +#define MCLK_ASRC1 155 +#define MCLK_ASRC2 156 +#define MCLK_ASRC3 157 +#define LRCK_ASRC0_SRC 158 +#define LRCK_ASRC0_DST 159 +#define LRCK_ASRC1_SRC 160 +#define LRCK_ASRC1_DST 161 +#define ACLK_HSPERI_ROOT 162 +#define HCLK_HSPERI_ROOT 163 +#define PCLK_HSPERI_ROOT 164 +#define CCLK_SRC_SDMMC 165 +#define HCLK_SDMMC 166 +#define HCLK_FSPI 167 +#define SCLK_FSPI 168 +#define PCLK_SPI2 169 +#define ACLK_MAC0 170 +#define ACLK_MAC1 171 +#define PCLK_MAC0 172 +#define PCLK_MAC1 173 +#define CLK_MAC_ROOT 174 +#define CLK_MAC0 175 +#define CLK_MAC1 176 +#define MCLK_SAI2 177 +#define HCLK_SAI2 178 +#define MCLK_OUT_SAI2 179 +#define MCLK_SAI3_SRC 180 +#define HCLK_SAI3 181 +#define MCLK_SAI3 182 +#define MCLK_OUT_SAI3 183 +#define MCLK_SAI4_SRC 184 +#define HCLK_SAI4 185 +#define MCLK_SAI4 186 +#define HCLK_DSM 187 +#define MCLK_DSM 188 +#define PCLK_AUDIO_ADC 189 +#define MCLK_AUDIO_ADC 190 +#define MCLK_AUDIO_ADC_DIV4 191 +#define PCLK_SARADC 192 +#define CLK_SARADC 193 +#define PCLK_OTPC_NS 194 +#define CLK_SBPI_OTPC_NS 195 +#define CLK_USER_OTPC_NS 196 +#define PCLK_UART5 197 +#define SCLK_UART5 198 +#define PCLK_GPIO234_IOC 199 +#define CLK_MAC_PTP_ROOT 200 +#define CLK_MAC0_PTP 201 +#define CLK_MAC1_PTP 202 +#define CLK_SPI2 203 +#define ACLK_VIO_ROOT 204 +#define HCLK_VIO_ROOT 205 +#define PCLK_VIO_ROOT 206 +#define HCLK_RGA 207 +#define ACLK_RGA 208 +#define CLK_CORE_RGA 209 +#define ACLK_VOP 210 +#define HCLK_VOP 211 +#define DCLK_VOP 212 +#define PCLK_DPHY 213 +#define PCLK_DSI_HOST 214 +#define PCLK_TSADC 215 +#define CLK_TSADC 216 +#define CLK_TSADC_TSEN 217 +#define PCLK_GPIO1_IOC 218 +#define PCLK_OTPC_S 219 +#define CLK_SBPI_OTPC_S 220 +#define CLK_USER_OTPC_S 221 +#define PCLK_OTP_MASK 222 +#define PCLK_KEYREADER 223 +#define HCLK_BOOTROM 224 +#define PCLK_DDR_SERVICE 225 +#define HCLK_CRYPTO_S 226 +#define HCLK_KEYLAD 227 +#define CLK_CORE_CRYPTO 228 +#define CLK_PKA_CRYPTO 229 +#define CLK_CORE_CRYPTO_S 230 +#define CLK_PKA_CRYPTO_S 231 +#define ACLK_CRYPTO_S 232 +#define HCLK_RNG_S 233 +#define CLK_CORE_CRYPTO_NS 234 +#define CLK_PKA_CRYPTO_NS 235 +#define ACLK_CRYPTO_NS 236 +#define HCLK_CRYPTO_NS 237 +#define HCLK_RNG 238 +#define CLK_PMU 239 +#define PCLK_PMU 240 +#define CLK_PMU_32K 241 +#define PCLK_PMU_CRU 242 +#define PCLK_PMU_GRF 243 +#define PCLK_GPIO0_IOC 244 +#define PCLK_GPIO0 245 +#define DBCLK_GPIO0 246 +#define PCLK_GPIO1_SHADOW 247 +#define DBCLK_GPIO1_SHADOW 248 +#define PCLK_PMU_HP_TIMER 249 +#define CLK_PMU_HP_TIMER 250 +#define CLK_PMU_HP_TIMER_32K 251 +#define PCLK_PWM0 252 +#define CLK_PWM0 253 +#define CLK_OSC_PWM0 254 +#define CLK_RC_PWM0 255 +#define CLK_MAC_OUT 256 +#define CLK_REF_OUT0 257 +#define CLK_REF_OUT1 258 +#define CLK_32K_FRAC 259 +#define CLK_32K_RC 260 +#define CLK_32K 261 +#define CLK_32K_PMU 262 +#define PCLK_TOUCH_KEY 263 +#define CLK_TOUCH_KEY 264 +#define CLK_REF_PHY_PLL 265 +#define CLK_REF_PHY_PMU_MUX 266 +#define CLK_WIFI_OUT 267 +#define CLK_V0PLL_REF 268 +#define CLK_V1PLL_REF 269 +#define CLK_32K_FRAC_MUX 270 + +#endif diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rv1126b-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rv1126b-cru.h new file mode 100644 index 00000000000..721d50a1419 --- /dev/null +++ b/dts/upstream/include/dt-bindings/clock/rockchip,rv1126b-cru.h @@ -0,0 +1,392 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H + +/* pll clocks */ +#define PLL_GPLL 0 +#define PLL_CPLL 1 +#define PLL_AUPLL 2 +#define ARMCLK 3 +#define SCLK_DDR 4 + +/* clk (clocks) */ +#define CLK_CPLL_DIV20 5 +#define CLK_CPLL_DIV10 6 +#define CLK_CPLL_DIV8 7 +#define CLK_GPLL_DIV8 8 +#define CLK_GPLL_DIV6 9 +#define CLK_GPLL_DIV4 10 +#define CLK_CPLL_DIV3 11 +#define CLK_GPLL_DIV3 12 +#define CLK_CPLL_DIV2 13 +#define CLK_GPLL_DIV2 14 +#define CLK_CM_FRAC0 15 +#define CLK_CM_FRAC1 16 +#define CLK_CM_FRAC2 17 +#define CLK_UART_FRAC0 18 +#define CLK_UART_FRAC1 19 +#define CLK_AUDIO_FRAC0 20 +#define CLK_AUDIO_FRAC1 21 +#define CLK_AUDIO_INT0 22 +#define CLK_AUDIO_INT1 23 +#define SCLK_UART0_SRC 24 +#define SCLK_UART1 25 +#define SCLK_UART2 26 +#define SCLK_UART3 27 +#define SCLK_UART4 28 +#define SCLK_UART5 29 +#define SCLK_UART6 30 +#define SCLK_UART7 31 +#define MCLK_SAI0 32 +#define MCLK_SAI1 33 +#define MCLK_SAI2 34 +#define MCLK_PDM 35 +#define CLKOUT_PDM 36 +#define MCLK_ASRC0 37 +#define MCLK_ASRC1 38 +#define MCLK_ASRC2 39 +#define MCLK_ASRC3 40 +#define CLK_ASRC0 41 +#define CLK_ASRC1 42 +#define CLK_CORE_PLL 43 +#define CLK_NPU_PLL 44 +#define CLK_VEPU_PLL 45 +#define CLK_ISP_PLL 46 +#define CLK_AISP_PLL 47 +#define CLK_SARADC0_SRC 48 +#define CLK_SARADC1_SRC 49 +#define CLK_SARADC2_SRC 50 +#define HCLK_NPU_ROOT 51 +#define PCLK_NPU_ROOT 52 +#define ACLK_VEPU_ROOT 53 +#define HCLK_VEPU_ROOT 54 +#define PCLK_VEPU_ROOT 55 +#define CLK_CORE_RGA_SRC 56 +#define ACLK_GMAC_ROOT 57 +#define ACLK_VI_ROOT 58 +#define HCLK_VI_ROOT 59 +#define PCLK_VI_ROOT 60 +#define DCLK_VICAP_ROOT 61 +#define CLK_SYS_DSMC_ROOT 62 +#define ACLK_VDO_ROOT 63 +#define ACLK_RKVDEC_ROOT 64 +#define HCLK_VDO_ROOT 65 +#define PCLK_VDO_ROOT 66 +#define DCLK_OOC_SRC 67 +#define DCLK_VOP 68 +#define DCLK_DECOM_SRC 69 +#define PCLK_DDR_ROOT 70 +#define ACLK_SYSMEM_SRC 71 +#define ACLK_TOP_ROOT 72 +#define ACLK_BUS_ROOT 73 +#define HCLK_BUS_ROOT 74 +#define PCLK_BUS_ROOT 75 +#define CCLK_SDMMC0 76 +#define CCLK_SDMMC1 77 +#define CCLK_EMMC 78 +#define SCLK_2X_FSPI0 79 +#define CLK_GMAC_PTP_REF_SRC 80 +#define CLK_GMAC_125M 81 +#define CLK_TIMER_ROOT 82 +#define TCLK_WDT_NS_SRC 83 +#define TCLK_WDT_S_SRC 84 +#define TCLK_WDT_HPMCU 85 +#define CLK_CAN0 86 +#define CLK_CAN1 87 +#define PCLK_PERI_ROOT 88 +#define ACLK_PERI_ROOT 89 +#define CLK_I2C_BUS_SRC 90 +#define CLK_SPI0 91 +#define CLK_SPI1 92 +#define BUSCLK_PMU_SRC 93 +#define CLK_PWM0 94 +#define CLK_PWM2 95 +#define CLK_PWM3 96 +#define CLK_PKA_RKCE_SRC 97 +#define ACLK_RKCE_SRC 98 +#define ACLK_VCP_ROOT 99 +#define HCLK_VCP_ROOT 100 +#define PCLK_VCP_ROOT 101 +#define CLK_CORE_FEC_SRC 102 +#define CLK_CORE_AVSP_SRC 103 +#define CLK_50M_GMAC_IOBUF_VI 104 +#define PCLK_TOP_ROOT 105 +#define CLK_MIPI0_OUT2IO 106 +#define CLK_MIPI1_OUT2IO 107 +#define CLK_MIPI2_OUT2IO 108 +#define CLK_MIPI3_OUT2IO 109 +#define CLK_CIF_OUT2IO 110 +#define CLK_MAC_OUT2IO 111 +#define MCLK_SAI0_OUT2IO 112 +#define MCLK_SAI1_OUT2IO 113 +#define MCLK_SAI2_OUT2IO 114 +#define CLK_CM_FRAC0_SRC 115 +#define CLK_CM_FRAC1_SRC 116 +#define CLK_CM_FRAC2_SRC 117 +#define CLK_UART_FRAC0_SRC 118 +#define CLK_UART_FRAC1_SRC 119 +#define CLK_AUDIO_FRAC0_SRC 120 +#define CLK_AUDIO_FRAC1_SRC 121 +#define ACLK_NPU_ROOT 122 +#define HCLK_RKNN 123 +#define ACLK_RKNN 124 +#define PCLK_GPIO3 125 +#define DBCLK_GPIO3 126 +#define PCLK_IOC_VCCIO3 127 +#define PCLK_SARADC0 128 +#define CLK_SARADC0 129 +#define HCLK_SDMMC1 130 +#define HCLK_VEPU 131 +#define ACLK_VEPU 132 +#define CLK_CORE_VEPU 133 +#define HCLK_FEC 134 +#define ACLK_FEC 135 +#define CLK_CORE_FEC 136 +#define HCLK_AVSP 137 +#define ACLK_AVSP 138 +#define BUSCLK_PMU1_ROOT 139 +#define HCLK_AISP 140 +#define ACLK_AISP 141 +#define CLK_CORE_AISP 142 +#define CLK_CORE_ISP_ROOT 143 +#define PCLK_DSMC 144 +#define ACLK_DSMC 145 +#define HCLK_CAN0 146 +#define HCLK_CAN1 147 +#define PCLK_GPIO2 148 +#define DBCLK_GPIO2 149 +#define PCLK_GPIO4 150 +#define DBCLK_GPIO4 151 +#define PCLK_GPIO5 152 +#define DBCLK_GPIO5 153 +#define PCLK_GPIO6 154 +#define DBCLK_GPIO6 155 +#define PCLK_GPIO7 156 +#define DBCLK_GPIO7 157 +#define PCLK_IOC_VCCIO2 158 +#define PCLK_IOC_VCCIO4 159 +#define PCLK_IOC_VCCIO5 160 +#define PCLK_IOC_VCCIO6 161 +#define PCLK_IOC_VCCIO7 162 +#define HCLK_ISP 163 +#define ACLK_ISP 164 +#define CLK_CORE_ISP 165 +#define HCLK_VICAP 166 +#define ACLK_VICAP 167 +#define DCLK_VICAP 168 +#define ISP0CLK_VICAP 169 +#define HCLK_VPSS 170 +#define ACLK_VPSS 171 +#define CLK_CORE_VPSS 172 +#define PCLK_CSI2HOST0 173 +#define DCLK_CSI2HOST0 174 +#define PCLK_CSI2HOST1 175 +#define DCLK_CSI2HOST1 176 +#define PCLK_CSI2HOST2 177 +#define DCLK_CSI2HOST2 178 +#define PCLK_CSI2HOST3 179 +#define DCLK_CSI2HOST3 180 +#define HCLK_SDMMC0 181 +#define ACLK_GMAC 182 +#define PCLK_GMAC 183 +#define CLK_GMAC_PTP_REF 184 +#define PCLK_CSIPHY0 185 +#define PCLK_CSIPHY1 186 +#define PCLK_MACPHY 187 +#define PCLK_SARADC1 188 +#define CLK_SARADC1 189 +#define PCLK_SARADC2 190 +#define CLK_SARADC2 191 +#define ACLK_RKVDEC 192 +#define HCLK_RKVDEC 193 +#define CLK_HEVC_CA_RKVDEC 194 +#define ACLK_VOP 195 +#define HCLK_VOP 196 +#define HCLK_RKJPEG 197 +#define ACLK_RKJPEG 198 +#define ACLK_RKMMU_DECOM 199 +#define HCLK_RKMMU_DECOM 200 +#define DCLK_DECOM 201 +#define ACLK_DECOM 202 +#define PCLK_DECOM 203 +#define PCLK_MIPI_DSI 204 +#define PCLK_DSIPHY 205 +#define ACLK_OOC 206 +#define ACLK_SYSMEM 207 +#define PCLK_DDRC 208 +#define PCLK_DDRMON 209 +#define CLK_TIMER_DDRMON 210 +#define PCLK_DFICTRL 211 +#define PCLK_DDRPHY 212 +#define PCLK_DMA2DDR 213 +#define CLK_RCOSC_SRC 214 +#define BUSCLK_PMU_MUX 215 +#define BUSCLK_PMU_ROOT 216 +#define PCLK_PMU 217 +#define CLK_XIN_RC_DIV 218 +#define CLK_32K 219 +#define PCLK_PMU_GPIO0 220 +#define DBCLK_PMU_GPIO0 221 +#define PCLK_PMU_HP_TIMER 222 +#define CLK_PMU_HP_TIMER 223 +#define CLK_PMU_32K_HP_TIMER 224 +#define PCLK_PWM1 225 +#define CLK_PWM1 226 +#define CLK_OSC_PWM1 227 +#define CLK_RC_PWM1 228 +#define CLK_FREQ_PWM1 229 +#define CLK_COUNTER_PWM1 230 +#define PCLK_I2C2 231 +#define CLK_I2C2 232 +#define PCLK_UART0 233 +#define SCLK_UART0 234 +#define PCLK_RCOSC_CTRL 235 +#define CLK_OSC_RCOSC_CTRL 236 +#define CLK_REF_RCOSC_CTRL 237 +#define PCLK_IOC_PMUIO0 238 +#define CLK_REFOUT 239 +#define CLK_PREROLL 240 +#define CLK_PREROLL_32K 241 +#define HCLK_PMU_SRAM 242 +#define PCLK_WDT_LPMCU 243 +#define TCLK_WDT_LPMCU 244 +#define CLK_LPMCU 245 +#define CLK_LPMCU_RTC 246 +#define PCLK_LPMCU_MAILBOX 247 +#define HCLK_OOC 248 +#define PCLK_SPI2AHB 249 +#define HCLK_SPI2AHB 250 +#define HCLK_FSPI1 251 +#define HCLK_XIP_FSPI1 252 +#define SCLK_1X_FSPI1 253 +#define PCLK_IOC_PMUIO1 254 +#define PCLK_AUDIO_ADC_PMU 255 +#define MCLK_AUDIO_ADC_PMU 256 +#define MCLK_AUDIO_ADC_DIV4_PMU 257 +#define MCLK_LPSAI 258 +#define ACLK_GIC400 259 +#define PCLK_WDT_NS 260 +#define TCLK_WDT_NS 261 +#define PCLK_WDT_HPMCU 262 +#define HCLK_CACHE 263 +#define PCLK_HPMCU_MAILBOX 264 +#define PCLK_HPMCU_INTMUX 265 +#define CLK_HPMCU 266 +#define CLK_HPMCU_RTC 267 +#define PCLK_RKDMA 268 +#define ACLK_RKDMA 269 +#define PCLK_DCF 270 +#define ACLK_DCF 271 +#define HCLK_RGA 272 +#define ACLK_RGA 273 +#define CLK_CORE_RGA 274 +#define PCLK_TIMER 275 +#define CLK_TIMER0 276 +#define CLK_TIMER1 277 +#define CLK_TIMER2 278 +#define CLK_TIMER3 279 +#define CLK_TIMER4 280 +#define CLK_TIMER5 281 +#define PCLK_I2C0 282 +#define CLK_I2C0 283 +#define PCLK_I2C1 284 +#define CLK_I2C1 285 +#define PCLK_I2C3 286 +#define CLK_I2C3 287 +#define PCLK_I2C4 288 +#define CLK_I2C4 289 +#define PCLK_I2C5 290 +#define CLK_I2C5 291 +#define PCLK_SPI0 292 +#define PCLK_SPI1 293 +#define PCLK_PWM0 294 +#define CLK_OSC_PWM0 295 +#define CLK_RC_PWM0 296 +#define PCLK_PWM2 297 +#define CLK_OSC_PWM2 298 +#define CLK_RC_PWM2 299 +#define PCLK_PWM3 300 +#define CLK_OSC_PWM3 301 +#define CLK_RC_PWM3 302 +#define PCLK_UART1 303 +#define PCLK_UART2 304 +#define PCLK_UART3 305 +#define PCLK_UART4 306 +#define PCLK_UART5 307 +#define PCLK_UART6 308 +#define PCLK_UART7 309 +#define PCLK_TSADC 310 +#define CLK_TSADC 311 +#define HCLK_SAI0 312 +#define HCLK_SAI1 313 +#define HCLK_SAI2 314 +#define HCLK_RKDSM 315 +#define MCLK_RKDSM 316 +#define HCLK_PDM 317 +#define HCLK_ASRC0 318 +#define HCLK_ASRC1 319 +#define PCLK_AUDIO_ADC_BUS 320 +#define MCLK_AUDIO_ADC_BUS 321 +#define MCLK_AUDIO_ADC_DIV4_BUS 322 +#define PCLK_RKCE 323 +#define HCLK_NS_RKCE 324 +#define PCLK_OTPC_NS 325 +#define CLK_SBPI_OTPC_NS 326 +#define CLK_USER_OTPC_NS 327 +#define CLK_OTPC_ARB 328 +#define PCLK_OTP_MASK 329 +#define CLK_TSADC_PHYCTRL 330 +#define LRCK_SRC_ASRC0 331 +#define LRCK_DST_ASRC0 332 +#define LRCK_SRC_ASRC1 333 +#define LRCK_DST_ASRC1 334 +#define PCLK_KEY_READER 335 +#define ACLK_NSRKCE 336 +#define CLK_PKA_NSRKCE 337 +#define PCLK_RTC_ROOT 338 +#define PCLK_GPIO1 339 +#define DBCLK_GPIO1 340 +#define PCLK_IOC_VCCIO1 341 +#define ACLK_USB3OTG 342 +#define CLK_REF_USB3OTG 343 +#define CLK_SUSPEND_USB3OTG 344 +#define HCLK_USB2HOST 345 +#define HCLK_ARB_USB2HOST 346 +#define PCLK_RTC_TEST 347 +#define HCLK_EMMC 348 +#define HCLK_FSPI0 349 +#define HCLK_XIP_FSPI0 350 +#define PCLK_PIPEPHY 351 +#define PCLK_USB2PHY 352 +#define CLK_REF_PIPEPHY_CPLL_SRC 353 +#define CLK_REF_PIPEPHY 354 +#define HCLK_VPSL 355 +#define ACLK_VPSL 356 +#define CLK_CORE_VPSL 357 +#define CLK_MACPHY 358 +#define HCLK_RKRNG_NS 359 +#define HCLK_RKRNG_S_NS 360 +#define CLK_AISP_PLL_SRC 361 + +/* secure clks */ +#define CLK_USER_OTPC_S 362 +#define CLK_SBPI_OTPC_S 363 +#define PCLK_OTPC_S 364 +#define PCLK_KEY_READER_S 365 +#define HCLK_KL_RKCE_S 366 +#define HCLK_RKCE_S 367 +#define PCLK_WDT_S 368 +#define TCLK_WDT_S 369 +#define CLK_STIMER0 370 +#define CLK_STIMER1 371 +#define PLK_STIMER 372 +#define HCLK_RKRNG_S 373 +#define CLK_PKA_RKCE_S 374 +#define ACLK_RKCE_S 375 + +#endif diff --git a/dts/upstream/include/dt-bindings/clock/samsung,exynosautov920.h b/dts/upstream/include/dt-bindings/clock/samsung,exynosautov920.h index 93e6233d135..970d05167fc 100644 --- a/dts/upstream/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/dts/upstream/include/dt-bindings/clock/samsung,exynosautov920.h @@ -295,4 +295,14 @@ #define CLK_DOUT_HSI2_ETHERNET 6 #define CLK_DOUT_HSI2_ETHERNET_PTP 7 +/* CMU_M2M */ +#define CLK_MOUT_M2M_JPEG_USER 1 +#define CLK_MOUT_M2M_NOC_USER 2 +#define CLK_DOUT_M2M_NOCP 3 + +/* CMU_MFC */ +#define CLK_MOUT_MFC_MFC_USER 1 +#define CLK_MOUT_MFC_WFD_USER 2 +#define CLK_DOUT_MFC_NOCP 3 + #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ diff --git a/dts/upstream/include/dt-bindings/clock/toshiba,tmpv770x.h b/dts/upstream/include/dt-bindings/clock/toshiba,tmpv770x.h index 5fce713001f..a36c8926668 100644 --- a/dts/upstream/include/dt-bindings/clock/toshiba,tmpv770x.h +++ b/dts/upstream/include/dt-bindings/clock/toshiba,tmpv770x.h @@ -11,7 +11,6 @@ #define TMPV770X_PLL_PIDDRCPLL 4 #define TMPV770X_PLL_PIVOIFPLL 5 #define TMPV770X_PLL_PIIMGERPLL 6 -#define TMPV770X_NR_PLL 7 /* Clocks */ #define TMPV770X_CLK_PIPLL1_DIV1 0 @@ -141,7 +140,9 @@ #define TMPV770X_CLK_PIREFCLK 124 #define TMPV770X_CLK_SBUS 125 #define TMPV770X_CLK_BUSLCK 126 -#define TMPV770X_NR_CLK 127 +#define TMPV770X_CLK_VIIFBS1_L2ISP 127 +#define TMPV770X_CLK_VIIFBS1_L1ISP 128 +#define TMPV770X_CLK_VIIFBS1_PROC 129 /* Reset */ #define TMPV770X_RESET_PIETHER_2P5M 0 @@ -176,6 +177,13 @@ #define TMPV770X_RESET_PIPCMIF 29 #define TMPV770X_RESET_PICKMON 30 #define TMPV770X_RESET_SBUSCLK 31 -#define TMPV770X_NR_RESET 32 +#define TMPV770X_RESET_VIIFBS0 32 +#define TMPV770X_RESET_VIIFBS0_APB 33 +#define TMPV770X_RESET_VIIFBS0_L2ISP 34 +#define TMPV770X_RESET_VIIFBS0_L1ISP 35 +#define TMPV770X_RESET_VIIFBS1 36 +#define TMPV770X_RESET_VIIFBS1_APB 37 +#define TMPV770X_RESET_VIIFBS1_L2ISP 38 +#define TMPV770X_RESET_VIIFBS1_L1ISP 39 #endif /*_DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ */ diff --git a/dts/upstream/include/dt-bindings/input/linux-event-codes.h b/dts/upstream/include/dt-bindings/input/linux-event-codes.h index 30f3c9eaafa..4bdb6a16598 100644 --- a/dts/upstream/include/dt-bindings/input/linux-event-codes.h +++ b/dts/upstream/include/dt-bindings/input/linux-event-codes.h @@ -891,6 +891,7 @@ #define ABS_VOLUME 0x20 #define ABS_PROFILE 0x21 +#define ABS_SND_PROFILE 0x22 #define ABS_MISC 0x28 @@ -1000,4 +1001,12 @@ #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) +/* + * ABS_SND_PROFILE values + */ + +#define SND_PROFILE_SILENT 0x00 +#define SND_PROFILE_VIBRATE 0x01 +#define SND_PROFILE_RING 0x02 + #endif diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h index afd7e0683a2..07b786bee7d 100644 --- a/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -20,8 +20,41 @@ #define SLAVE_CNOC_PCIE3 15 #define MASTER_CNOC_USB 16 #define SLAVE_CNOC_USB 17 +#define MASTER_NSSNOC_NSSCC 18 +#define SLAVE_NSSNOC_NSSCC 19 +#define MASTER_NSSNOC_SNOC_0 20 +#define SLAVE_NSSNOC_SNOC_0 21 +#define MASTER_NSSNOC_SNOC_1 22 +#define SLAVE_NSSNOC_SNOC_1 23 +#define MASTER_NSSNOC_PCNOC_1 24 +#define SLAVE_NSSNOC_PCNOC_1 25 +#define MASTER_NSSNOC_QOSGEN_REF 26 +#define SLAVE_NSSNOC_QOSGEN_REF 27 +#define MASTER_NSSNOC_TIMEOUT_REF 28 +#define SLAVE_NSSNOC_TIMEOUT_REF 29 +#define MASTER_NSSNOC_XO_DCD 30 +#define SLAVE_NSSNOC_XO_DCD 31 +#define MASTER_NSSNOC_ATB 32 +#define SLAVE_NSSNOC_ATB 33 +#define MASTER_CNOC_LPASS_CFG 34 +#define SLAVE_CNOC_LPASS_CFG 35 +#define MASTER_SNOC_LPASS 36 +#define SLAVE_SNOC_LPASS 37 #define MASTER_CPU 0 #define SLAVE_L3 1 +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_CE_AXI 6 +#define SLAVE_NSSNOC_CE_AXI 7 +#define MASTER_NSSNOC_CE_APB 8 +#define SLAVE_NSSNOC_CE_APB 9 +#define MASTER_NSSNOC_EIP 10 +#define SLAVE_NSSNOC_EIP 11 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h b/dts/upstream/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h new file mode 100644 index 00000000000..dde3f9abd67 --- /dev/null +++ b/dts/upstream/include/dt-bindings/interconnect/qcom,kaanapali-rpmh.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_KAANAPALI_H + +#define MASTER_QSPI_0 0 +#define MASTER_CRYPTO 1 +#define MASTER_QUP_1 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB3 5 +#define MASTER_QUP_2 6 +#define MASTER_QUP_3 7 +#define MASTER_QUP_4 8 +#define MASTER_IPA 9 +#define MASTER_SOCCP_PROC 10 +#define MASTER_SP 11 +#define MASTER_QDSS_ETR 12 +#define MASTER_QDSS_ETR_1 13 +#define MASTER_SDCC_2 14 +#define SLAVE_A1NOC_SNOC 15 +#define SLAVE_A2NOC_SNOC 16 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define MASTER_QUP_CORE_4 4 +#define SLAVE_QUP_CORE_0 5 +#define SLAVE_QUP_CORE_1 6 +#define SLAVE_QUP_CORE_2 7 +#define SLAVE_QUP_CORE_3 8 +#define SLAVE_QUP_CORE_4 9 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_CAMERA_CFG 3 +#define SLAVE_CLK_CTL 4 +#define SLAVE_CRYPTO_0_CFG 5 +#define SLAVE_DISPLAY_CFG 6 +#define SLAVE_EVA_CFG 7 +#define SLAVE_GFX3D_CFG 8 +#define SLAVE_I2C 9 +#define SLAVE_I3C_IBI0_CFG 10 +#define SLAVE_I3C_IBI1_CFG 11 +#define SLAVE_IMEM_CFG 12 +#define SLAVE_IPC_ROUTER_CFG 13 +#define SLAVE_CNOC_MSS 14 +#define SLAVE_PCIE_CFG 15 +#define SLAVE_PRNG 16 +#define SLAVE_QDSS_CFG 17 +#define SLAVE_QSPI_0 18 +#define SLAVE_QUP_1 19 +#define SLAVE_QUP_2 20 +#define SLAVE_QUP_3 21 +#define SLAVE_QUP_4 22 +#define SLAVE_SDCC_2 23 +#define SLAVE_SDCC_4 24 +#define SLAVE_SPSS_CFG 25 +#define SLAVE_TCSR 26 +#define SLAVE_TLMM 27 +#define SLAVE_UFS_MEM_CFG 28 +#define SLAVE_USB3 29 +#define SLAVE_VENUS_CFG 30 +#define SLAVE_VSENSE_CTRL_CFG 31 +#define SLAVE_CNOC_MNOC_CFG 32 +#define SLAVE_PCIE_ANOC_CFG 33 +#define SLAVE_QDSS_STM 34 +#define SLAVE_TCU 35 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_FENCE 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_APPSS 7 +#define SLAVE_CNOC_CFG 8 +#define SLAVE_DDRSS_CFG 9 +#define SLAVE_BOOT_IMEM 10 +#define SLAVE_IMEM 11 +#define SLAVE_PCIE_0 12 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_QPACE 10 +#define MASTER_SNOC_SF_MEM_NOC 11 +#define MASTER_WLAN_Q6 12 +#define MASTER_GIC 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_MEM_NOC_PCIE_SNOC 16 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP 4 +#define MASTER_MDSS_DCP 5 +#define MASTER_CDSP_HCP 6 +#define MASTER_VIDEO_CV_PROC 7 +#define MASTER_VIDEO_EVA 8 +#define MASTER_VIDEO_MVP 9 +#define MASTER_VIDEO_V_PROC 10 +#define MASTER_CNOC_MNOC_CFG 11 +#define SLAVE_MNOC_HF_MEM_NOC 12 +#define SLAVE_MNOC_SF_MEM_NOC 13 +#define SLAVE_SERVICE_MNOC 14 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define SLAVE_ANOC_PCIE_GEM_NOC 2 +#define SLAVE_SERVICE_PCIE_ANOC 3 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_APSS_NOC 2 +#define MASTER_CNOC_SNOC 3 +#define SLAVE_SNOC_GEM_NOC_SF 4 + +#endif diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,sdx75.h b/dts/upstream/include/dt-bindings/interconnect/qcom,sdx75.h index e903f5f3dd8..0e19ee8f168 100644 --- a/dts/upstream/include/dt-bindings/interconnect/qcom,sdx75.h +++ b/dts/upstream/include/dt-bindings/interconnect/qcom,sdx75.h @@ -6,9 +6,7 @@ #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H -#define MASTER_QPIC_CORE 0 #define MASTER_QUP_CORE_0 1 -#define SLAVE_QPIC_CORE 2 #define SLAVE_QUP_CORE_0 3 #define MASTER_LLCC 0 diff --git a/dts/upstream/include/dt-bindings/media/c8sectpfe.h b/dts/upstream/include/dt-bindings/media/c8sectpfe.h deleted file mode 100644 index 6b1fb6f5413..00000000000 --- a/dts/upstream/include/dt-bindings/media/c8sectpfe.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_C8SECTPFE_H -#define __DT_C8SECTPFE_H - -#define STV0367_TDA18212_NIMA_1 0 -#define STV0367_TDA18212_NIMA_2 1 -#define STV0367_TDA18212_NIMB_1 2 -#define STV0367_TDA18212_NIMB_2 3 - -#define STV0903_6110_LNB24_NIMA 4 -#define STV0903_6110_LNB24_NIMB 5 - -#endif /* __DT_C8SECTPFE_H */ diff --git a/dts/upstream/include/dt-bindings/media/video-interfaces.h b/dts/upstream/include/dt-bindings/media/video-interfaces.h index 88b9d05d807..0b19c9b2e62 100644 --- a/dts/upstream/include/dt-bindings/media/video-interfaces.h +++ b/dts/upstream/include/dt-bindings/media/video-interfaces.h @@ -20,4 +20,8 @@ #define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB 4 #define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA 5 +#define MEDIA_PCLK_SAMPLE_FALLING_EDGE 0 +#define MEDIA_PCLK_SAMPLE_RISING_EDGE 1 +#define MEDIA_PCLK_SAMPLE_DUAL_EDGE 2 + #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ diff --git a/dts/upstream/include/dt-bindings/memory/mediatek,mt8189-memory-port.h b/dts/upstream/include/dt-bindings/memory/mediatek,mt8189-memory-port.h new file mode 100644 index 00000000000..849fead3d0f --- /dev/null +++ b/dts/upstream/include/dt-bindings/memory/mediatek,mt8189-memory-port.h @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Zhengnan chen + */ +#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ +#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ + +#include + +#define SMI_L0_ID (0) +#define SMI_L1_ID (1) +#define SMI_L2_ID (2) +#define SMI_L4_ID (3) +#define SMI_L7_ID (4) +#define SMI_L9_ID (5) +#define SMI_L11_ID (6) +#define SMI_L13_ID (7) +#define SMI_L14_ID (8) +#define SMI_L16_ID (9) +#define SMI_L17_ID (10) +#define SMI_L19_ID (11) +#define SMI_L20_ID (12) + +/* + * MM IOMMU supports 16GB dma address. We separate it to four ranges: + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters + * locate in anyone region. BUT: + * a) Make sure all the ports inside a larb are in one range. + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. + * + * This is the suggested mapping in this SoC: + * + * modules dma-address-region larbs-ports + * disp/mdp 0 ~ 4G larb0/1/2 + * vcodec 4G ~ 8G larb4/7 + * imgsys/cam/ipesys 8G ~ 12G the other larbs. + * N/A 12G ~ 16G + */ + +/* Larb0 -- disp */ +#define M4U_L0_P0_DISP_OVL0_4L_HDR MTK_M4U_ID(SMI_L0_ID, 0) +#define M4U_L0_P1_DISP_OVL0_4L_RDMA0 MTK_M4U_ID(SMI_L0_ID, 1) +#define M4U_L0_P2_DISP_OVL1_4L_RDMA1 MTK_M4U_ID(SMI_L0_ID, 2) +#define M4U_L0_P3_DISP_OVL0_4L_RDMA2 MTK_M4U_ID(SMI_L0_ID, 3) +#define M4U_L0_P4_DISP_OVL1_4L_RDMA3 MTK_M4U_ID(SMI_L0_ID, 4) +#define M4U_L0_P5_DISP_RDMA0 MTK_M4U_ID(SMI_L0_ID, 5) +#define M4U_L0_P6_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 6) +#define M4U_L0_P7_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 7) + +/* Larb1 -- disp */ +#define M4U_L1_P0_DISP_OVL1_4L_HDR MTK_M4U_ID(SMI_L1_ID, 0) +#define M4U_L1_P1_DISP_OVL1_4L_RDMA0 MTK_M4U_ID(SMI_L1_ID, 1) +#define M4U_L1_P2_DISP_OVL0_4L_RDMA1 MTK_M4U_ID(SMI_L1_ID, 2) +#define M4U_L1_P3_DISP_OVL1_4L_RDMA2 MTK_M4U_ID(SMI_L1_ID, 3) +#define M4U_L1_P4_DISP_OVL0_4L_RDMA3 MTK_M4U_ID(SMI_L1_ID, 4) +#define M4U_L1_P5_DISP_RDMA1 MTK_M4U_ID(SMI_L1_ID, 5) +#define M4U_L1_P6_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 6) +#define M4U_L1_P7_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 7) + +/* Larb2 -- mmlsys(mdp) */ +#define M4U_L2_P0_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0) +#define M4U_L2_P1_MDP_RDMA1 MTK_M4U_ID(SMI_L2_ID, 1) +#define M4U_L2_P2_MDP_WROT0 MTK_M4U_ID(SMI_L2_ID, 2) +#define M4U_L2_P3_MDP_WROT1 MTK_M4U_ID(SMI_L2_ID, 3) +#define M4U_L2_P4_MDP_DUMMY0 MTK_M4U_ID(SMI_L2_ID, 4) +#define M4U_L2_P5_MDP_DUMMY1 MTK_M4U_ID(SMI_L2_ID, 5) +#define M4U_L2_P6_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 6) +#define M4U_L2_P7_MDP_RDMA3 MTK_M4U_ID(SMI_L2_ID, 7) +#define M4U_L2_P8_MDP_WROT2 MTK_M4U_ID(SMI_L2_ID, 8) +#define M4U_L2_P9_MDP_WROT3 MTK_M4U_ID(SMI_L2_ID, 9) +#define M4U_L2_P10_DISP_FAKE0 MTK_M4U_ID(SMI_L2_ID, 10) + +/* Larb3: null */ + +/* Larb4 -- vdec */ +#define M4U_L4_P0_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L4_ID, 0) +#define M4U_L4_P1_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L4_ID, 1) +#define M4U_L4_P2_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L4_ID, 2) +#define M4U_L4_P3_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L4_ID, 3) +#define M4U_L4_P4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L4_ID, 4) +#define M4U_L4_P5_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L4_ID, 5) +#define M4U_L4_P6_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L4_ID, 6) +#define M4U_L4_P7_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L4_ID, 7) +#define M4U_L4_P8_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L4_ID, 8) +#define M4U_L4_P9_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L4_ID, 9) +#define M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(SMI_L4_ID, 10) +#define M4U_L4_P11_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L4_ID, 11) + +/* Larb5: null */ + +/* Larb6: null */ + +/* Larb7 -- venc */ +#define M4U_L7_P0_VENC_RCPU MTK_M4U_ID(SMI_L7_ID, 0) +#define M4U_L7_P1_VENC_REC MTK_M4U_ID(SMI_L7_ID, 1) +#define M4U_L7_P2_VENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 2) +#define M4U_L7_P3_VENC_SV_COMV MTK_M4U_ID(SMI_L7_ID, 3) +#define M4U_L7_P4_VENC_RD_COMV MTK_M4U_ID(SMI_L7_ID, 4) +#define M4U_L7_P5_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L7_ID, 5) +#define M4U_L7_P6_JPGENC_C_RDMA MTK_M4U_ID(SMI_L7_ID, 6) +#define M4U_L7_P7_JPGENC_Q_RDMA MTK_M4U_ID(SMI_L7_ID, 7) +#define M4U_L7_P8_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L7_ID, 8) +#define M4U_L7_P9_JPGENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 9) +#define M4U_L7_P10_VENC_CUR_LUMA MTK_M4U_ID(SMI_L7_ID, 10) +#define M4U_L7_P11_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L7_ID, 11) +#define M4U_L7_P12_VENC_REF_LUMA MTK_M4U_ID(SMI_L7_ID, 12) +#define M4U_L7_P13_VENC_REF_CHROMA MTK_M4U_ID(SMI_L7_ID, 13) +#define M4U_L7_P14_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L7_ID, 14) +#define M4U_L7_P15_JPGDEC_WDMA MTK_M4U_ID(SMI_L7_ID, 15) +#define M4U_L7_P16_JPGDEC_BSDMA MTK_M4U_ID(SMI_L7_ID, 16) +#define M4U_L7_P17_JPGDEC_HUFF_OFFSET MTK_M4U_ID(SMI_L7_ID, 17) + +/* Larb8: null */ + +/* Larb9 --imgsys */ +#define M4U_L9_P0_IMGI_D1 MTK_M4U_ID(SMI_L9_ID, 0) +#define M4U_L9_P1_IMGBI_D1 MTK_M4U_ID(SMI_L9_ID, 1) +#define M4U_L9_P2_DMGI_D1 MTK_M4U_ID(SMI_L9_ID, 2) +#define M4U_L9_P3_DEPI_D1 MTK_M4U_ID(SMI_L9_ID, 3) +#define M4U_L9_P4_LCE_D1 MTK_M4U_ID(SMI_L9_ID, 4) +#define M4U_L9_P5_SMTI_D1 MTK_M4U_ID(SMI_L9_ID, 5) +#define M4U_L9_P6_SMTO_D2 MTK_M4U_ID(SMI_L9_ID, 6) +#define M4U_L9_P7_SMTO_D1 MTK_M4U_ID(SMI_L9_ID, 7) +#define M4U_L9_P8_CRZO_D1 MTK_M4U_ID(SMI_L9_ID, 8) +#define M4U_L9_P9_IMG3O_D1 MTK_M4U_ID(SMI_L9_ID, 9) +#define M4U_L9_P10_VIPI_D1 MTK_M4U_ID(SMI_L9_ID, 10) +#define M4U_L9_P11_SMTI_D5 MTK_M4U_ID(SMI_L9_ID, 11) +#define M4U_L9_P12_TIMGO_D1 MTK_M4U_ID(SMI_L9_ID, 12) +#define M4U_L9_P13_UFBC_W0 MTK_M4U_ID(SMI_L9_ID, 13) +#define M4U_L9_P14_UFBC_R0 MTK_M4U_ID(SMI_L9_ID, 14) +#define M4U_L9_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L9_ID, 15) +#define M4U_L9_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L9_ID, 16) +#define M4U_L9_P17_WPE_WDMA MTK_M4U_ID(SMI_L9_ID, 17) +#define M4U_L9_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L9_ID, 18) +#define M4U_L9_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L9_ID, 19) +#define M4U_L9_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L9_ID, 20) +#define M4U_L9_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L9_ID, 21) +#define M4U_L9_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L9_ID, 22) +#define M4U_L9_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L9_ID, 23) +#define M4U_L9_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L9_ID, 24) +#define M4U_L9_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L9_ID, 25) +#define M4U_L9_P26_RESERVE6 MTK_M4U_ID(SMI_L9_ID, 26) +#define M4U_L9_P27_RESERVE7 MTK_M4U_ID(SMI_L9_ID, 27) +#define M4U_L9_P28_RESERVE8 MTK_M4U_ID(SMI_L9_ID, 28) + +/* Larb10: null */ + +/* Larb11 -- imgsys */ +#define M4U_L11_P0_IMGI_D1 MTK_M4U_ID(SMI_L11_ID, 0) +#define M4U_L11_P1_IMGBI_D1 MTK_M4U_ID(SMI_L11_ID, 1) +#define M4U_L11_P2_DMGI_D1 MTK_M4U_ID(SMI_L11_ID, 2) +#define M4U_L11_P3_DEPI_D1 MTK_M4U_ID(SMI_L11_ID, 3) +#define M4U_L11_P4_LCE_D1 MTK_M4U_ID(SMI_L11_ID, 4) +#define M4U_L11_P5_SMTI_D1 MTK_M4U_ID(SMI_L11_ID, 5) +#define M4U_L11_P6_SMTO_D2 MTK_M4U_ID(SMI_L11_ID, 6) +#define M4U_L11_P7_SMTO_D1 MTK_M4U_ID(SMI_L11_ID, 7) +#define M4U_L11_P8_CRZO_D1 MTK_M4U_ID(SMI_L11_ID, 8) +#define M4U_L11_P9_IMG3O_D1 MTK_M4U_ID(SMI_L11_ID, 9) +#define M4U_L11_P10_VIPI_D1 MTK_M4U_ID(SMI_L11_ID, 10) +#define M4U_L11_P11_SMTI_D5 MTK_M4U_ID(SMI_L11_ID, 11) +#define M4U_L11_P12_TIMGO_D1 MTK_M4U_ID(SMI_L11_ID, 12) +#define M4U_L11_P13_UFBC_W0 MTK_M4U_ID(SMI_L11_ID, 13) +#define M4U_L11_P14_UFBC_R0 MTK_M4U_ID(SMI_L11_ID, 14) +#define M4U_L11_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L11_ID, 15) +#define M4U_L11_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L11_ID, 16) +#define M4U_L11_P17_WPE_WDMA MTK_M4U_ID(SMI_L11_ID, 17) +#define M4U_L11_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L11_ID, 18) +#define M4U_L11_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L11_ID, 19) +#define M4U_L11_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L11_ID, 20) +#define M4U_L11_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L11_ID, 21) +#define M4U_L11_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L11_ID, 22) +#define M4U_L11_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L11_ID, 23) +#define M4U_L11_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L11_ID, 24) +#define M4U_L11_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L11_ID, 25) +#define M4U_L11_P26_RESERVE6 MTK_M4U_ID(SMI_L11_ID, 26) +#define M4U_L11_P27_RESERVE7 MTK_M4U_ID(SMI_L11_ID, 27) +#define M4U_L11_P28_RESERVE8 MTK_M4U_ID(SMI_L11_ID, 28) + +/* Larb12: null */ + +/* Larb13 -- cam */ +#define M4U_L13_P0_MRAWI MTK_M4U_ID(SMI_L13_ID, 0) +#define M4U_L13_P1_MRAWO_0 MTK_M4U_ID(SMI_L13_ID, 1) +#define M4U_L13_P2_MRAWO_1 MTK_M4U_ID(SMI_L13_ID, 2) +#define M4U_L13_P3_CAMSV_1 MTK_M4U_ID(SMI_L13_ID, 3) +#define M4U_L13_P4_CAMSV_2 MTK_M4U_ID(SMI_L13_ID, 4) +#define M4U_L13_P5_CAMSV_3 MTK_M4U_ID(SMI_L13_ID, 5) +#define M4U_L13_P6_CAMSV_4 MTK_M4U_ID(SMI_L13_ID, 6) +#define M4U_L13_P7_CAMSV_5 MTK_M4U_ID(SMI_L13_ID, 7) +#define M4U_L13_P8_CAMSV_6 MTK_M4U_ID(SMI_L13_ID, 8) +#define M4U_L13_P9_CCUI MTK_M4U_ID(SMI_L13_ID, 9) +#define M4U_L13_P10_CCUO MTK_M4U_ID(SMI_L13_ID, 10) +#define M4U_L13_P11_FAKE MTK_M4U_ID(SMI_L13_ID, 11) +#define M4U_L13_P12_PDAI_0 MTK_M4U_ID(SMI_L13_ID, 12) +#define M4U_L13_P13_PDAI_1 MTK_M4U_ID(SMI_L13_ID, 13) +#define M4U_L13_P14_PDAO MTK_M4U_ID(SMI_L13_ID, 14) + +/* Larb14 -- cam */ +#define M4U_L14_P0_RESERVE MTK_M4U_ID(SMI_L14_ID, 0) +#define M4U_L14_P1_RESERVE MTK_M4U_ID(SMI_L14_ID, 1) +#define M4U_L14_P2_RESERVE MTK_M4U_ID(SMI_L14_ID, 2) +#define M4U_L14_P3_CAMSV_0 MTK_M4U_ID(SMI_L14_ID, 3) +#define M4U_L14_P4_CCUI MTK_M4U_ID(SMI_L14_ID, 4) +#define M4U_L14_P5_CCUO MTK_M4U_ID(SMI_L14_ID, 5) +#define M4U_L14_P6_CAMSV_7 MTK_M4U_ID(SMI_L14_ID, 6) +#define M4U_L14_P7_CAMSV_8 MTK_M4U_ID(SMI_L14_ID, 7) +#define M4U_L14_P8_CAMSV_9 MTK_M4U_ID(SMI_L14_ID, 8) +#define M4U_L14_P9_CAMSV_10 MTK_M4U_ID(SMI_L14_ID, 9) + +/* Larb15: null */ + +/* Larb16 -- cam */ +#define M4U_L16_P0_IMGO_R1_A MTK_M4U_ID(SMI_L16_ID, 0) +#define M4U_L16_P1_RRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 1) +#define M4U_L16_P2_CQI_R1_A MTK_M4U_ID(SMI_L16_ID, 2) +#define M4U_L16_P3_BPCI_R1_A MTK_M4U_ID(SMI_L16_ID, 3) +#define M4U_L16_P4_YUVO_R1_A MTK_M4U_ID(SMI_L16_ID, 4) +#define M4U_L16_P5_UFDI_R2_A MTK_M4U_ID(SMI_L16_ID, 5) +#define M4U_L16_P6_RAWI_R2_A MTK_M4U_ID(SMI_L16_ID, 6) +#define M4U_L16_P7_RAWI_R3_A MTK_M4U_ID(SMI_L16_ID, 7) +#define M4U_L16_P8_AAO_R1_A MTK_M4U_ID(SMI_L16_ID, 8) +#define M4U_L16_P9_AFO_R1_A MTK_M4U_ID(SMI_L16_ID, 9) +#define M4U_L16_P10_FLKO_R1_A MTK_M4U_ID(SMI_L16_ID, 10) +#define M4U_L16_P11_LCESO_R1_A MTK_M4U_ID(SMI_L16_ID, 11) +#define M4U_L16_P12_CRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 12) +#define M4U_L16_P13_LTMSO_R1_A MTK_M4U_ID(SMI_L16_ID, 13) +#define M4U_L16_P14_RSSO_R1_A MTK_M4U_ID(SMI_L16_ID, 14) +#define M4U_L16_P15_AAHO_R1_A MTK_M4U_ID(SMI_L16_ID, 15) +#define M4U_L16_P16_LSCI_R1_A MTK_M4U_ID(SMI_L16_ID, 16) + +/* Larb17 -- cam */ +#define M4U_L17_P0_IMGO_R1_B MTK_M4U_ID(SMI_L17_ID, 0) +#define M4U_L17_P1_RRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 1) +#define M4U_L17_P2_CQI_R1_B MTK_M4U_ID(SMI_L17_ID, 2) +#define M4U_L17_P3_BPCI_R1_B MTK_M4U_ID(SMI_L17_ID, 3) +#define M4U_L17_P4_YUVO_R1_B MTK_M4U_ID(SMI_L17_ID, 4) +#define M4U_L17_P5_UFDI_R2_B MTK_M4U_ID(SMI_L17_ID, 5) +#define M4U_L17_P6_RAWI_R2_B MTK_M4U_ID(SMI_L17_ID, 6) +#define M4U_L17_P7_RAWI_R3_B MTK_M4U_ID(SMI_L17_ID, 7) +#define M4U_L17_P8_AAO_R1_B MTK_M4U_ID(SMI_L17_ID, 8) +#define M4U_L17_P9_AFO_R1_B MTK_M4U_ID(SMI_L17_ID, 9) +#define M4U_L17_P10_FLKO_R1_B MTK_M4U_ID(SMI_L17_ID, 10) +#define M4U_L17_P11_LCESO_R1_B MTK_M4U_ID(SMI_L17_ID, 11) +#define M4U_L17_P12_CRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 12) +#define M4U_L17_P13_LTMSO_R1_B MTK_M4U_ID(SMI_L17_ID, 13) +#define M4U_L17_P14_RSSO_R1_B MTK_M4U_ID(SMI_L17_ID, 14) +#define M4U_L17_P15_AAHO_R1_B MTK_M4U_ID(SMI_L17_ID, 15) +#define M4U_L17_P16_LSCI_R1_B MTK_M4U_ID(SMI_L17_ID, 16) + +/* Larb19 -- ipesys */ +#define M4U_L19_P0_DVS_RDMA MTK_M4U_ID(SMI_L19_ID, 0) +#define M4U_L19_P1_DVS_WDMA MTK_M4U_ID(SMI_L19_ID, 1) +#define M4U_L19_P2_DVP_RDMA MTK_M4U_ID(SMI_L19_ID, 2) +#define M4U_L19_P3_DVP_WDMA MTK_M4U_ID(SMI_L19_ID, 3) + +/* Larb20 -- ipesys */ +#define M4U_L20_P0_FDVT_RDA_0 MTK_M4U_ID(SMI_L20_ID, 0) +#define M4U_L20_P1_FDVT_RDB_0 MTK_M4U_ID(SMI_L20_ID, 1) +#define M4U_L20_P2_FDVT_WRA_0 MTK_M4U_ID(SMI_L20_ID, 2) +#define M4U_L20_P3_FDVT_WRB_0 MTK_M4U_ID(SMI_L20_ID, 3) +#define M4U_L20_P4_RSC_RDMA MTK_M4U_ID(SMI_L20_ID, 4) +#define M4U_L20_P5_RSC_WDMA MTK_M4U_ID(SMI_L20_ID, 5) + +/* fake larb21 for gce */ +#define M4U_L21_GCE_DM MTK_M4U_ID(21, 0) +#define M4U_L21_GCE_MM MTK_M4U_ID(21, 1) + +/* fake larb & port for svp and dual svp and wfd */ +#define M4U_PORT_SVP_HEAP MTK_M4U_ID(22, 0) +#define M4U_PORT_DUAL_SVP_HEAP MTK_M4U_ID(22, 1) +#define M4U_PORT_WFD_HEAP MTK_M4U_ID(22, 2) + +/* fake larb0 for apu */ +#define M4U_L0_APU_DATA MTK_M4U_ID(0, 0) +#define M4U_L0_APU_CODE MTK_M4U_ID(0, 1) +#define M4U_L0_APU_SECURE MTK_M4U_ID(0, 2) +#define M4U_L0_APU_VLM MTK_M4U_ID(0, 3) + +/* infra/peri */ +#define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0, 26) + +#endif diff --git a/dts/upstream/include/dt-bindings/power/mediatek,mt8196-power.h b/dts/upstream/include/dt-bindings/power/mediatek,mt8196-power.h new file mode 100644 index 00000000000..0f622a93c80 --- /dev/null +++ b/dts/upstream/include/dt-bindings/power/mediatek,mt8196-power.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno + */ + +#ifndef _DT_BINDINGS_POWER_MT8196_POWER_H +#define _DT_BINDINGS_POWER_MT8196_POWER_H + +/* SCPSYS Secure Power Manager - Direct Control */ +#define MT8196_POWER_DOMAIN_MD 0 +#define MT8196_POWER_DOMAIN_CONN 1 +#define MT8196_POWER_DOMAIN_SSUSB_P0 2 +#define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0 3 +#define MT8196_POWER_DOMAIN_SSUSB_P1 4 +#define MT8196_POWER_DOMAIN_SSUSB_P23 5 +#define MT8196_POWER_DOMAIN_SSUSB_PHY_P2 6 +#define MT8196_POWER_DOMAIN_PEXTP_MAC0 7 +#define MT8196_POWER_DOMAIN_PEXTP_MAC1 8 +#define MT8196_POWER_DOMAIN_PEXTP_MAC2 9 +#define MT8196_POWER_DOMAIN_PEXTP_PHY0 10 +#define MT8196_POWER_DOMAIN_PEXTP_PHY1 11 +#define MT8196_POWER_DOMAIN_PEXTP_PHY2 12 +#define MT8196_POWER_DOMAIN_AUDIO 13 +#define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT 14 +#define MT8196_POWER_DOMAIN_ADSP_INFRA 15 +#define MT8196_POWER_DOMAIN_ADSP_AO 16 + +/* SCPSYS Secure Power Manager - HW Voter */ +#define MT8196_POWER_DOMAIN_MM_PROC_DORMANT 0 +#define MT8196_POWER_DOMAIN_SSR 1 + +/* HFRPSYS MultiMedia Power Control (MMPC) - HW Voter */ +#define MT8196_POWER_DOMAIN_VDE0 0 +#define MT8196_POWER_DOMAIN_VDE1 1 +#define MT8196_POWER_DOMAIN_VDE_VCORE0 2 +#define MT8196_POWER_DOMAIN_VEN0 3 +#define MT8196_POWER_DOMAIN_VEN1 4 +#define MT8196_POWER_DOMAIN_VEN2 5 +#define MT8196_POWER_DOMAIN_DISP_VCORE 6 +#define MT8196_POWER_DOMAIN_DIS0_DORMANT 7 +#define MT8196_POWER_DOMAIN_DIS1_DORMANT 8 +#define MT8196_POWER_DOMAIN_OVL0_DORMANT 9 +#define MT8196_POWER_DOMAIN_OVL1_DORMANT 10 +#define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT 11 +#define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT 12 +#define MT8196_POWER_DOMAIN_MML0_SHUTDOWN 13 +#define MT8196_POWER_DOMAIN_MML1_SHUTDOWN 14 +#define MT8196_POWER_DOMAIN_MM_INFRA0 15 +#define MT8196_POWER_DOMAIN_MM_INFRA1 16 +#define MT8196_POWER_DOMAIN_MM_INFRA_AO 17 +#define MT8196_POWER_DOMAIN_CSI_BS_RX 18 +#define MT8196_POWER_DOMAIN_CSI_LS_RX 19 +#define MT8196_POWER_DOMAIN_DSI_PHY0 20 +#define MT8196_POWER_DOMAIN_DSI_PHY1 21 +#define MT8196_POWER_DOMAIN_DSI_PHY2 22 + +#endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */ diff --git a/dts/upstream/include/dt-bindings/power/nvidia,tegra264-bpmp.h b/dts/upstream/include/dt-bindings/power/nvidia,tegra264-bpmp.h new file mode 100644 index 00000000000..2eef4a2a02b --- /dev/null +++ b/dts/upstream/include/dt-bindings/power/nvidia,tegra264-bpmp.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H +#define DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H + +#define TEGRA264_POWER_DOMAIN_DISP 1 +#define TEGRA264_POWER_DOMAIN_AUD 2 +/* reserved 3:9 */ +#define TEGRA264_POWER_DOMAIN_XUSB_SS 10 +#define TEGRA264_POWER_DOMAIN_XUSB_DEV 11 +#define TEGRA264_POWER_DOMAIN_XUSB_HOST 12 +#define TEGRA264_POWER_DOMAIN_MGBE0 13 +#define TEGRA264_POWER_DOMAIN_MGBE1 14 +#define TEGRA264_POWER_DOMAIN_MGBE2 15 +#define TEGRA264_POWER_DOMAIN_MGBE3 16 +#define TEGRA264_POWER_DOMAIN_VI 17 +#define TEGRA264_POWER_DOMAIN_VIC 18 +#define TEGRA264_POWER_DOMAIN_ISP0 19 +#define TEGRA264_POWER_DOMAIN_ISP1 20 +#define TEGRA264_POWER_DOMAIN_PVA0 21 +#define TEGRA264_POWER_DOMAIN_GPU 22 + +#endif /* DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H */ diff --git a/dts/upstream/include/dt-bindings/power/qcom,rpmhpd.h b/dts/upstream/include/dt-bindings/power/qcom,rpmhpd.h index 73cceb88953..06851363ae0 100644 --- a/dts/upstream/include/dt-bindings/power/qcom,rpmhpd.h +++ b/dts/upstream/include/dt-bindings/power/qcom,rpmhpd.h @@ -33,11 +33,14 @@ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D3 50 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1 51 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1 54 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 #define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L0 76 #define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 #define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 #define RPMH_REGULATOR_LEVEL_SVS 128 @@ -261,5 +264,6 @@ #define SC8280XP_NSP 13 #define SC8280XP_QPHY 14 #define SC8280XP_XO 15 +#define SC8280XP_MXC_AO 16 #endif diff --git a/dts/upstream/include/dt-bindings/power/rockchip,rv1126b-power-controller.h b/dts/upstream/include/dt-bindings/power/rockchip,rv1126b-power-controller.h new file mode 100644 index 00000000000..48ea87a4423 --- /dev/null +++ b/dts/upstream/include/dt-bindings/power/rockchip,rv1126b-power-controller.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#ifndef __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__ +#define __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__ + +/* VD_NPU */ +#define RV1126B_PD_NPU 0 + +/* VD_LOGIC */ +#define RV1126B_PD_VDO 1 +#define RV1126B_PD_AIISP 2 + +#endif diff --git a/dts/upstream/include/dt-bindings/reset/airoha,en7523-reset.h b/dts/upstream/include/dt-bindings/reset/airoha,en7523-reset.h new file mode 100644 index 00000000000..211e8a23a21 --- /dev/null +++ b/dts/upstream/include/dt-bindings/reset/airoha,en7523-reset.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 iopsys Software Solutions AB. + * Copyright (C) 2025 Genexis AB. + * + * Author: Mikhail Kshevetskiy + * + * based on + * include/dt-bindings/reset/airoha,en7581-reset.h + * by Lorenzo Bianconi + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ + +/* RST_CTRL2 */ +#define EN7523_XPON_PHY_RST 0 +#define EN7523_XSI_MAC_RST 1 +#define EN7523_XSI_PHY_RST 2 +#define EN7523_NPU_RST 3 +#define EN7523_I2S_RST 4 +#define EN7523_TRNG_RST 5 +#define EN7523_TRNG_MSTART_RST 6 +#define EN7523_DUAL_HSI0_RST 7 +#define EN7523_DUAL_HSI1_RST 8 +#define EN7523_HSI_RST 9 +#define EN7523_DUAL_HSI0_MAC_RST 10 +#define EN7523_DUAL_HSI1_MAC_RST 11 +#define EN7523_HSI_MAC_RST 12 +#define EN7523_WDMA_RST 13 +#define EN7523_WOE0_RST 14 +#define EN7523_WOE1_RST 15 +#define EN7523_HSDMA_RST 16 +#define EN7523_I2C2RBUS_RST 17 +#define EN7523_TDMA_RST 18 +/* RST_CTRL1 */ +#define EN7523_PCM1_ZSI_ISI_RST 19 +#define EN7523_FE_PDMA_RST 20 +#define EN7523_FE_QDMA_RST 21 +#define EN7523_PCM_SPIWP_RST 22 +#define EN7523_CRYPTO_RST 23 +#define EN7523_TIMER_RST 24 +#define EN7523_PCM1_RST 25 +#define EN7523_UART_RST 26 +#define EN7523_GPIO_RST 27 +#define EN7523_GDMA_RST 28 +#define EN7523_I2C_MASTER_RST 29 +#define EN7523_PCM2_ZSI_ISI_RST 30 +#define EN7523_SFC_RST 31 +#define EN7523_UART2_RST 32 +#define EN7523_GDMP_RST 33 +#define EN7523_FE_RST 34 +#define EN7523_USB_HOST_P0_RST 35 +#define EN7523_GSW_RST 36 +#define EN7523_SFC2_PCM_RST 37 +#define EN7523_PCIE0_RST 38 +#define EN7523_PCIE1_RST 39 +#define EN7523_PCIE_HB_RST 40 +#define EN7523_XPON_MAC_RST 41 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7523_H_ */ diff --git a/dts/upstream/include/dt-bindings/reset/eswin,eic7700-reset.h b/dts/upstream/include/dt-bindings/reset/eswin,eic7700-reset.h new file mode 100644 index 00000000000..a370c9f7430 --- /dev/null +++ b/dts/upstream/include/dt-bindings/reset/eswin,eic7700-reset.h @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd.. + * All rights reserved. + * + * Device Tree binding constants for EIC7700 reset controller. + * + * Authors: + * Yifeng Huang + * Xuyang Dong + */ + +#ifndef __DT_ESWIN_EIC7700_RESET_H__ +#define __DT_ESWIN_EIC7700_RESET_H__ + +#define EIC7700_RESET_NOC_NSP 0 +#define EIC7700_RESET_NOC_CFG 1 +#define EIC7700_RESET_RNOC_NSP 2 +#define EIC7700_RESET_SNOC_TCU 3 +#define EIC7700_RESET_SNOC_U84 4 +#define EIC7700_RESET_SNOC_PCIE_XSR 5 +#define EIC7700_RESET_SNOC_PCIE_XMR 6 +#define EIC7700_RESET_SNOC_PCIE_PR 7 +#define EIC7700_RESET_SNOC_NPU 8 +#define EIC7700_RESET_SNOC_JTAG 9 +#define EIC7700_RESET_SNOC_DSP 10 +#define EIC7700_RESET_SNOC_DDRC1_P2 11 +#define EIC7700_RESET_SNOC_DDRC1_P1 12 +#define EIC7700_RESET_SNOC_DDRC0_P2 13 +#define EIC7700_RESET_SNOC_DDRC0_P1 14 +#define EIC7700_RESET_SNOC_D2D 15 +#define EIC7700_RESET_SNOC_AON 16 +#define EIC7700_RESET_GPU_AXI 17 +#define EIC7700_RESET_GPU_CFG 18 +#define EIC7700_RESET_GPU_GRAY 19 +#define EIC7700_RESET_GPU_JONES 20 +#define EIC7700_RESET_GPU_SPU 21 +#define EIC7700_RESET_DSP_AXI 22 +#define EIC7700_RESET_DSP_CFG 23 +#define EIC7700_RESET_DSP_DIV4 24 +#define EIC7700_RESET_DSP_DIV0 25 +#define EIC7700_RESET_DSP_DIV1 26 +#define EIC7700_RESET_DSP_DIV2 27 +#define EIC7700_RESET_DSP_DIV3 28 +#define EIC7700_RESET_D2D_AXI 29 +#define EIC7700_RESET_D2D_CFG 30 +#define EIC7700_RESET_D2D_PRST 31 +#define EIC7700_RESET_D2D_RAW_PCS 32 +#define EIC7700_RESET_D2D_RX 33 +#define EIC7700_RESET_D2D_TX 34 +#define EIC7700_RESET_D2D_CORE 35 +#define EIC7700_RESET_DDR1_ARST 36 +#define EIC7700_RESET_DDR1_TRACE 37 +#define EIC7700_RESET_DDR0_ARST 38 +#define EIC7700_RESET_DDR_CFG 39 +#define EIC7700_RESET_DDR0_TRACE 40 +#define EIC7700_RESET_DDR_CORE 41 +#define EIC7700_RESET_DDR_PRST 42 +#define EIC7700_RESET_TCU_AXI 43 +#define EIC7700_RESET_TCU_CFG 44 +#define EIC7700_RESET_TCU_TBU0 45 +#define EIC7700_RESET_TCU_TBU1 46 +#define EIC7700_RESET_TCU_TBU2 47 +#define EIC7700_RESET_TCU_TBU3 48 +#define EIC7700_RESET_TCU_TBU4 49 +#define EIC7700_RESET_TCU_TBU5 50 +#define EIC7700_RESET_TCU_TBU6 51 +#define EIC7700_RESET_TCU_TBU7 52 +#define EIC7700_RESET_TCU_TBU8 53 +#define EIC7700_RESET_TCU_TBU9 54 +#define EIC7700_RESET_TCU_TBU10 55 +#define EIC7700_RESET_TCU_TBU11 56 +#define EIC7700_RESET_TCU_TBU12 57 +#define EIC7700_RESET_TCU_TBU13 58 +#define EIC7700_RESET_TCU_TBU14 59 +#define EIC7700_RESET_TCU_TBU15 60 +#define EIC7700_RESET_TCU_TBU16 61 +#define EIC7700_RESET_NPU_AXI 62 +#define EIC7700_RESET_NPU_CFG 63 +#define EIC7700_RESET_NPU_CORE 64 +#define EIC7700_RESET_NPU_E31CORE 65 +#define EIC7700_RESET_NPU_E31BUS 66 +#define EIC7700_RESET_NPU_E31DBG 67 +#define EIC7700_RESET_NPU_LLC 68 +#define EIC7700_RESET_HSP_AXI 69 +#define EIC7700_RESET_HSP_CFG 70 +#define EIC7700_RESET_HSP_POR 71 +#define EIC7700_RESET_MSHC0_PHY 72 +#define EIC7700_RESET_MSHC1_PHY 73 +#define EIC7700_RESET_MSHC2_PHY 74 +#define EIC7700_RESET_MSHC0_TXRX 75 +#define EIC7700_RESET_MSHC1_TXRX 76 +#define EIC7700_RESET_MSHC2_TXRX 77 +#define EIC7700_RESET_SATA_ASIC0 78 +#define EIC7700_RESET_SATA_OOB 79 +#define EIC7700_RESET_SATA_PMALIVE 80 +#define EIC7700_RESET_SATA_RBC 81 +#define EIC7700_RESET_DMA0 82 +#define EIC7700_RESET_HSP_DMA 83 +#define EIC7700_RESET_USB0_VAUX 84 +#define EIC7700_RESET_USB1_VAUX 85 +#define EIC7700_RESET_HSP_SD1_PRST 86 +#define EIC7700_RESET_HSP_SD0_PRST 87 +#define EIC7700_RESET_HSP_EMMC_PRST 88 +#define EIC7700_RESET_HSP_DMA_PRST 89 +#define EIC7700_RESET_HSP_SD1_ARST 90 +#define EIC7700_RESET_HSP_SD0_ARST 91 +#define EIC7700_RESET_HSP_EMMC_ARST 92 +#define EIC7700_RESET_HSP_DMA_ARST 93 +#define EIC7700_RESET_HSP_ETH1_ARST 94 +#define EIC7700_RESET_HSP_ETH0_ARST 95 +#define EIC7700_RESET_SATA_ARST 96 +#define EIC7700_RESET_PCIE_CFG 97 +#define EIC7700_RESET_PCIE_POWEUP 98 +#define EIC7700_RESET_PCIE_PERST 99 +#define EIC7700_RESET_I2C0 100 +#define EIC7700_RESET_I2C1 101 +#define EIC7700_RESET_I2C2 102 +#define EIC7700_RESET_I2C3 103 +#define EIC7700_RESET_I2C4 104 +#define EIC7700_RESET_I2C5 105 +#define EIC7700_RESET_I2C6 106 +#define EIC7700_RESET_I2C7 107 +#define EIC7700_RESET_I2C8 108 +#define EIC7700_RESET_I2C9 109 +#define EIC7700_RESET_FAN 110 +#define EIC7700_RESET_PVT0 111 +#define EIC7700_RESET_PVT1 112 +#define EIC7700_RESET_MBOX0 113 +#define EIC7700_RESET_MBOX1 114 +#define EIC7700_RESET_MBOX2 115 +#define EIC7700_RESET_MBOX3 116 +#define EIC7700_RESET_MBOX4 117 +#define EIC7700_RESET_MBOX5 118 +#define EIC7700_RESET_MBOX6 119 +#define EIC7700_RESET_MBOX7 120 +#define EIC7700_RESET_MBOX8 121 +#define EIC7700_RESET_MBOX9 122 +#define EIC7700_RESET_MBOX10 123 +#define EIC7700_RESET_MBOX11 124 +#define EIC7700_RESET_MBOX12 125 +#define EIC7700_RESET_MBOX13 126 +#define EIC7700_RESET_MBOX14 127 +#define EIC7700_RESET_MBOX15 128 +#define EIC7700_RESET_UART0 129 +#define EIC7700_RESET_UART1 130 +#define EIC7700_RESET_UART2 131 +#define EIC7700_RESET_UART3 132 +#define EIC7700_RESET_UART4 133 +#define EIC7700_RESET_GPIO0 134 +#define EIC7700_RESET_GPIO1 135 +#define EIC7700_RESET_TIMER 136 +#define EIC7700_RESET_SSI0 137 +#define EIC7700_RESET_SSI1 138 +#define EIC7700_RESET_WDT0 139 +#define EIC7700_RESET_WDT1 140 +#define EIC7700_RESET_WDT2 141 +#define EIC7700_RESET_WDT3 142 +#define EIC7700_RESET_LSP_CFG 143 +#define EIC7700_RESET_U84_CORE0 144 +#define EIC7700_RESET_U84_CORE1 145 +#define EIC7700_RESET_U84_CORE2 146 +#define EIC7700_RESET_U84_CORE3 147 +#define EIC7700_RESET_U84_BUS 148 +#define EIC7700_RESET_U84_DBG 149 +#define EIC7700_RESET_U84_TRACECOM 150 +#define EIC7700_RESET_U84_TRACE0 151 +#define EIC7700_RESET_U84_TRACE1 152 +#define EIC7700_RESET_U84_TRACE2 153 +#define EIC7700_RESET_U84_TRACE3 154 +#define EIC7700_RESET_SCPU_CORE 155 +#define EIC7700_RESET_SCPU_BUS 156 +#define EIC7700_RESET_SCPU_DBG 157 +#define EIC7700_RESET_LPCPU_CORE 158 +#define EIC7700_RESET_LPCPU_BUS 159 +#define EIC7700_RESET_LPCPU_DBG 160 +#define EIC7700_RESET_VC_CFG 161 +#define EIC7700_RESET_VC_AXI 162 +#define EIC7700_RESET_VC_MONCFG 163 +#define EIC7700_RESET_JD_CFG 164 +#define EIC7700_RESET_JD_AXI 165 +#define EIC7700_RESET_JE_CFG 166 +#define EIC7700_RESET_JE_AXI 167 +#define EIC7700_RESET_VD_CFG 168 +#define EIC7700_RESET_VD_AXI 169 +#define EIC7700_RESET_VE_AXI 170 +#define EIC7700_RESET_VE_CFG 171 +#define EIC7700_RESET_G2D_CORE 172 +#define EIC7700_RESET_G2D_CFG 173 +#define EIC7700_RESET_G2D_AXI 174 +#define EIC7700_RESET_VI_AXI 175 +#define EIC7700_RESET_VI_CFG 176 +#define EIC7700_RESET_VI_DWE 177 +#define EIC7700_RESET_DVP 178 +#define EIC7700_RESET_ISP0 179 +#define EIC7700_RESET_ISP1 180 +#define EIC7700_RESET_SHUTTR0 181 +#define EIC7700_RESET_SHUTTR1 182 +#define EIC7700_RESET_SHUTTR2 183 +#define EIC7700_RESET_SHUTTR3 184 +#define EIC7700_RESET_SHUTTR4 185 +#define EIC7700_RESET_SHUTTR5 186 +#define EIC7700_RESET_VO_MIPI 187 +#define EIC7700_RESET_VO_PRST 188 +#define EIC7700_RESET_VO_HDMI_PRST 189 +#define EIC7700_RESET_VO_HDMI_PHY 190 +#define EIC7700_RESET_VO_HDMI 191 +#define EIC7700_RESET_VO_I2S 192 +#define EIC7700_RESET_VO_I2S_PRST 193 +#define EIC7700_RESET_VO_AXI 194 +#define EIC7700_RESET_VO_CFG 195 +#define EIC7700_RESET_VO_DC 196 +#define EIC7700_RESET_VO_DC_PRST 197 +#define EIC7700_RESET_BOOTSPI_HRST 198 +#define EIC7700_RESET_BOOTSPI 199 +#define EIC7700_RESET_ANO1 200 +#define EIC7700_RESET_ANO0 201 +#define EIC7700_RESET_DMA1_ARST 202 +#define EIC7700_RESET_DMA1_HRST 203 +#define EIC7700_RESET_FPRT 204 +#define EIC7700_RESET_HBLOCK 205 +#define EIC7700_RESET_SECSR 206 +#define EIC7700_RESET_OTP 207 +#define EIC7700_RESET_PKA 208 +#define EIC7700_RESET_SPACC 209 +#define EIC7700_RESET_TRNG 210 +#define EIC7700_RESET_TIMER0_0 211 +#define EIC7700_RESET_TIMER0_1 212 +#define EIC7700_RESET_TIMER0_2 213 +#define EIC7700_RESET_TIMER0_3 214 +#define EIC7700_RESET_TIMER0_4 215 +#define EIC7700_RESET_TIMER0_5 216 +#define EIC7700_RESET_TIMER0_6 217 +#define EIC7700_RESET_TIMER0_7 218 +#define EIC7700_RESET_TIMER0_N 219 +#define EIC7700_RESET_TIMER1_0 220 +#define EIC7700_RESET_TIMER1_1 221 +#define EIC7700_RESET_TIMER1_2 222 +#define EIC7700_RESET_TIMER1_3 223 +#define EIC7700_RESET_TIMER1_4 224 +#define EIC7700_RESET_TIMER1_5 225 +#define EIC7700_RESET_TIMER1_6 226 +#define EIC7700_RESET_TIMER1_7 227 +#define EIC7700_RESET_TIMER1_N 228 +#define EIC7700_RESET_TIMER2_0 229 +#define EIC7700_RESET_TIMER2_1 230 +#define EIC7700_RESET_TIMER2_2 231 +#define EIC7700_RESET_TIMER2_3 232 +#define EIC7700_RESET_TIMER2_4 233 +#define EIC7700_RESET_TIMER2_5 234 +#define EIC7700_RESET_TIMER2_6 235 +#define EIC7700_RESET_TIMER2_7 236 +#define EIC7700_RESET_TIMER2_N 237 +#define EIC7700_RESET_TIMER3_0 238 +#define EIC7700_RESET_TIMER3_1 239 +#define EIC7700_RESET_TIMER3_2 240 +#define EIC7700_RESET_TIMER3_3 241 +#define EIC7700_RESET_TIMER3_4 242 +#define EIC7700_RESET_TIMER3_5 243 +#define EIC7700_RESET_TIMER3_6 244 +#define EIC7700_RESET_TIMER3_7 245 +#define EIC7700_RESET_TIMER3_N 246 +#define EIC7700_RESET_RTC 247 +#define EIC7700_RESET_MNOC_SNOC_NSP 248 +#define EIC7700_RESET_MNOC_VC 249 +#define EIC7700_RESET_MNOC_CFG 250 +#define EIC7700_RESET_MNOC_HSP 251 +#define EIC7700_RESET_MNOC_GPU 252 +#define EIC7700_RESET_MNOC_DDRC1_P3 253 +#define EIC7700_RESET_MNOC_DDRC0_P3 254 +#define EIC7700_RESET_RNOC_VO 255 +#define EIC7700_RESET_RNOC_VI 256 +#define EIC7700_RESET_RNOC_SNOC_NSP 257 +#define EIC7700_RESET_RNOC_CFG 258 +#define EIC7700_RESET_MNOC_DDRC1_P4 259 +#define EIC7700_RESET_MNOC_DDRC0_P4 260 +#define EIC7700_RESET_CNOC_VO_CFG 261 +#define EIC7700_RESET_CNOC_VI_CFG 262 +#define EIC7700_RESET_CNOC_VC_CFG 263 +#define EIC7700_RESET_CNOC_TCU_CFG 264 +#define EIC7700_RESET_CNOC_PCIE_CFG 265 +#define EIC7700_RESET_CNOC_NPU_CFG 266 +#define EIC7700_RESET_CNOC_LSP_CFG 267 +#define EIC7700_RESET_CNOC_HSP_CFG 268 +#define EIC7700_RESET_CNOC_GPU_CFG 269 +#define EIC7700_RESET_CNOC_DSPT_CFG 270 +#define EIC7700_RESET_CNOC_DDRT1_CFG 271 +#define EIC7700_RESET_CNOC_DDRT0_CFG 272 +#define EIC7700_RESET_CNOC_D2D_CFG 273 +#define EIC7700_RESET_CNOC_CFG 274 +#define EIC7700_RESET_CNOC_CLMM_CFG 275 +#define EIC7700_RESET_CNOC_AON_CFG 276 +#define EIC7700_RESET_LNOC_CFG 277 +#define EIC7700_RESET_LNOC_NPU_LLC 278 +#define EIC7700_RESET_LNOC_DDRC1_P0 279 +#define EIC7700_RESET_LNOC_DDRC0_P0 280 + +#endif /* __DT_ESWIN_EIC7700_RESET_H__ */ diff --git a/dts/upstream/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h b/dts/upstream/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h new file mode 100644 index 00000000000..adf95bb26d2 --- /dev/null +++ b/dts/upstream/include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H +#define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H + +#define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST 0 +#define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST 1 +#define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL 2 +#define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N 3 +#define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N 4 +#define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N 5 + +#endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */ diff --git a/dts/upstream/include/dt-bindings/reset/qcom,ipq5424-nsscc.h b/dts/upstream/include/dt-bindings/reset/qcom,ipq5424-nsscc.h new file mode 100644 index 00000000000..9627e3b0ad3 --- /dev/null +++ b/dts/upstream/include/dt-bindings/reset/qcom,ipq5424-nsscc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H +#define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H + +#define NSS_CC_CE_APB_CLK_ARES 0 +#define NSS_CC_CE_AXI_CLK_ARES 1 +#define NSS_CC_DEBUG_CLK_ARES 2 +#define NSS_CC_EIP_CLK_ARES 3 +#define NSS_CC_NSS_CSR_CLK_ARES 4 +#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 +#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 +#define NSS_CC_NSSNOC_EIP_CLK_ARES 7 +#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 +#define NSS_CC_NSSNOC_PPE_CLK_ARES 9 +#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 +#define NSS_CC_PORT1_MAC_CLK_ARES 11 +#define NSS_CC_PORT1_RX_CLK_ARES 12 +#define NSS_CC_PORT1_TX_CLK_ARES 13 +#define NSS_CC_PORT2_MAC_CLK_ARES 14 +#define NSS_CC_PORT2_RX_CLK_ARES 15 +#define NSS_CC_PORT2_TX_CLK_ARES 16 +#define NSS_CC_PORT3_MAC_CLK_ARES 17 +#define NSS_CC_PORT3_RX_CLK_ARES 18 +#define NSS_CC_PORT3_TX_CLK_ARES 19 +#define NSS_CC_PPE_BCR 20 +#define NSS_CC_PPE_EDMA_CLK_ARES 21 +#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 22 +#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 23 +#define NSS_CC_PPE_SWITCH_CLK_ARES 24 +#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 25 +#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 26 +#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 27 +#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 28 +#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 29 +#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 30 +#define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES 31 +#define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES 32 +#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 33 +#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 34 +#define NSS_CC_XGMAC2_PTP_REF_CLK_ARES 35 + +#endif diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3506-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3506-cru.h new file mode 100644 index 00000000000..31c0d4aa410 --- /dev/null +++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3506-cru.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H +#define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H + +/* CRU-->SOFTRST_CON00 */ +#define SRST_NCOREPORESET0_AC 0 +#define SRST_NCOREPORESET1_AC 1 +#define SRST_NCOREPORESET2_AC 2 +#define SRST_NCORESET0_AC 3 +#define SRST_NCORESET1_AC 4 +#define SRST_NCORESET2_AC 5 +#define SRST_NL2RESET_AC 6 +#define SRST_A_CORE_BIU_AC 7 +#define SRST_H_M0_AC 8 + +/* CRU-->SOFTRST_CON02 */ +#define SRST_NDBGRESET 9 +#define SRST_P_CORE_BIU 10 +#define SRST_PMU 11 + +/* CRU-->SOFTRST_CON03 */ +#define SRST_P_DBG 12 +#define SRST_POT_DBG 13 +#define SRST_P_CORE_GRF 14 +#define SRST_CORE_EMA_DETECT 15 +#define SRST_REF_PVTPLL_CORE 16 +#define SRST_P_GPIO1 17 +#define SRST_DB_GPIO1 18 + +/* CRU-->SOFTRST_CON04 */ +#define SRST_A_CORE_PERI_BIU 19 +#define SRST_A_DSMC 20 +#define SRST_P_DSMC 21 +#define SRST_FLEXBUS 22 +#define SRST_A_FLEXBUS 23 +#define SRST_H_FLEXBUS 24 +#define SRST_A_DSMC_SLV 25 +#define SRST_H_DSMC_SLV 26 +#define SRST_DSMC_SLV 27 + +/* CRU-->SOFTRST_CON05 */ +#define SRST_A_BUS_BIU 28 +#define SRST_H_BUS_BIU 29 +#define SRST_P_BUS_BIU 30 +#define SRST_A_SYSRAM 31 +#define SRST_H_SYSRAM 32 +#define SRST_A_DMAC0 33 +#define SRST_A_DMAC1 34 +#define SRST_H_M0 35 +#define SRST_M0_JTAG 36 +#define SRST_H_CRYPTO 37 + +/* CRU-->SOFTRST_CON06 */ +#define SRST_H_RNG 38 +#define SRST_P_BUS_GRF 39 +#define SRST_P_TIMER0 40 +#define SRST_TIMER0_CH0 41 +#define SRST_TIMER0_CH1 42 +#define SRST_TIMER0_CH2 43 +#define SRST_TIMER0_CH3 44 +#define SRST_TIMER0_CH4 45 +#define SRST_TIMER0_CH5 46 +#define SRST_P_WDT0 47 +#define SRST_T_WDT0 48 +#define SRST_P_WDT1 49 +#define SRST_T_WDT1 50 +#define SRST_P_MAILBOX 51 +#define SRST_P_INTMUX 52 +#define SRST_P_SPINLOCK 53 + +/* CRU-->SOFTRST_CON07 */ +#define SRST_P_DDRC 54 +#define SRST_H_DDRPHY 55 +#define SRST_P_DDRMON 56 +#define SRST_DDRMON_OSC 57 +#define SRST_P_DDR_LPC 58 +#define SRST_H_USBOTG0 59 +#define SRST_USBOTG0_ADP 60 +#define SRST_H_USBOTG1 61 +#define SRST_USBOTG1_ADP 62 +#define SRST_P_USBPHY 63 +#define SRST_USBPHY_POR 64 +#define SRST_USBPHY_OTG0 65 +#define SRST_USBPHY_OTG1 66 + +/* CRU-->SOFTRST_CON08 */ +#define SRST_A_DMA2DDR 67 +#define SRST_P_DMA2DDR 68 + +/* CRU-->SOFTRST_CON09 */ +#define SRST_USBOTG0_UTMI 69 +#define SRST_USBOTG1_UTMI 70 + +/* CRU-->SOFTRST_CON10 */ +#define SRST_A_DDRC_0 71 +#define SRST_A_DDRC_1 72 +#define SRST_A_DDR_BIU 73 +#define SRST_DDRC 74 +#define SRST_DDRMON 75 + +/* CRU-->SOFTRST_CON11 */ +#define SRST_H_LSPERI_BIU 76 +#define SRST_P_UART0 77 +#define SRST_P_UART1 78 +#define SRST_P_UART2 79 +#define SRST_P_UART3 80 +#define SRST_P_UART4 81 +#define SRST_UART0 82 +#define SRST_UART1 83 +#define SRST_UART2 84 +#define SRST_UART3 85 +#define SRST_UART4 86 +#define SRST_P_I2C0 87 +#define SRST_I2C0 88 + +/* CRU-->SOFTRST_CON12 */ +#define SRST_P_I2C1 89 +#define SRST_I2C1 90 +#define SRST_P_I2C2 91 +#define SRST_I2C2 92 +#define SRST_P_PWM1 93 +#define SRST_PWM1 94 +#define SRST_P_SPI0 95 +#define SRST_SPI0 96 +#define SRST_P_SPI1 97 +#define SRST_SPI1 98 +#define SRST_P_GPIO2 99 +#define SRST_DB_GPIO2 100 + +/* CRU-->SOFTRST_CON13 */ +#define SRST_P_GPIO3 101 +#define SRST_DB_GPIO3 102 +#define SRST_P_GPIO4 103 +#define SRST_DB_GPIO4 104 +#define SRST_H_CAN0 105 +#define SRST_CAN0 106 +#define SRST_H_CAN1 107 +#define SRST_CAN1 108 +#define SRST_H_PDM 109 +#define SRST_M_PDM 110 +#define SRST_PDM 111 +#define SRST_SPDIFTX 112 +#define SRST_H_SPDIFTX 113 +#define SRST_H_SPDIFRX 114 +#define SRST_SPDIFRX 115 +#define SRST_M_SAI0 116 + +/* CRU-->SOFTRST_CON14 */ +#define SRST_H_SAI0 117 +#define SRST_M_SAI1 118 +#define SRST_H_SAI1 119 +#define SRST_H_ASRC0 120 +#define SRST_ASRC0 121 +#define SRST_H_ASRC1 122 +#define SRST_ASRC1 123 + +/* CRU-->SOFTRST_CON17 */ +#define SRST_H_HSPERI_BIU 124 +#define SRST_H_SDMMC 125 +#define SRST_H_FSPI 126 +#define SRST_S_FSPI 127 +#define SRST_P_SPI2 128 +#define SRST_A_MAC0 129 +#define SRST_A_MAC1 130 + +/* CRU-->SOFTRST_CON18 */ +#define SRST_M_SAI2 131 +#define SRST_H_SAI2 132 +#define SRST_H_SAI3 133 +#define SRST_M_SAI3 134 +#define SRST_H_SAI4 135 +#define SRST_M_SAI4 136 +#define SRST_H_DSM 137 +#define SRST_M_DSM 138 +#define SRST_P_AUDIO_ADC 139 +#define SRST_M_AUDIO_ADC 140 + +/* CRU-->SOFTRST_CON19 */ +#define SRST_P_SARADC 141 +#define SRST_SARADC 142 +#define SRST_SARADC_PHY 143 +#define SRST_P_OTPC_NS 144 +#define SRST_SBPI_OTPC_NS 145 +#define SRST_USER_OTPC_NS 146 +#define SRST_P_UART5 147 +#define SRST_UART5 148 +#define SRST_P_GPIO234_IOC 149 + +/* CRU-->SOFTRST_CON21 */ +#define SRST_A_VIO_BIU 150 +#define SRST_H_VIO_BIU 151 +#define SRST_H_RGA 152 +#define SRST_A_RGA 153 +#define SRST_CORE_RGA 154 +#define SRST_A_VOP 155 +#define SRST_H_VOP 156 +#define SRST_VOP 157 +#define SRST_P_DPHY 158 +#define SRST_P_DSI_HOST 159 +#define SRST_P_TSADC 160 +#define SRST_TSADC 161 + +/* CRU-->SOFTRST_CON22 */ +#define SRST_P_GPIO1_IOC 162 + +#endif diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rv1126b-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rv1126b-cru.h new file mode 100644 index 00000000000..a7712db319d --- /dev/null +++ b/dts/upstream/include/dt-bindings/reset/rockchip,rv1126b-cru.h @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H + +/* ==========================list all of reset fields id=========================== */ +/* TOPCRU-->SOFTRST_CON00 */ + +/* TOPCRU-->SOFTRST_CON15 */ +#define SRST_P_CRU 0 +#define SRST_P_CRU_BIU 1 + +/* BUSCRU-->SOFTRST_CON00 */ +#define SRST_A_TOP_BIU 2 +#define SRST_A_RKCE_BIU 3 +#define SRST_A_BUS_BIU 4 +#define SRST_H_BUS_BIU 5 +#define SRST_P_BUS_BIU 6 +#define SRST_P_CRU_BUS 7 +#define SRST_P_SYS_GRF 8 +#define SRST_H_BOOTROM 9 +#define SRST_A_GIC400 10 +#define SRST_A_SPINLOCK 11 +#define SRST_P_WDT_NS 12 +#define SRST_T_WDT_NS 13 + +/* BUSCRU-->SOFTRST_CON01 */ +#define SRST_P_WDT_HPMCU 14 +#define SRST_T_WDT_HPMCU 15 +#define SRST_H_CACHE 16 +#define SRST_P_HPMCU_MAILBOX 17 +#define SRST_P_HPMCU_INTMUX 18 +#define SRST_HPMCU_FULL_CLUSTER 19 +#define SRST_HPMCU_PWUP 20 +#define SRST_HPMCU_ONLY_CORE 21 +#define SRST_T_HPMCU_JTAG 22 +#define SRST_P_RKDMA 23 +#define SRST_A_RKDMA 24 + +/* BUSCRU-->SOFTRST_CON02 */ +#define SRST_P_DCF 25 +#define SRST_A_DCF 26 +#define SRST_H_RGA 27 +#define SRST_A_RGA 28 +#define SRST_CORE_RGA 29 +#define SRST_P_TIMER 30 +#define SRST_TIMER0 31 +#define SRST_TIMER1 32 +#define SRST_TIMER2 33 +#define SRST_TIMER3 34 +#define SRST_TIMER4 35 +#define SRST_TIMER5 36 +#define SRST_A_RKCE 37 +#define SRST_PKA_RKCE 38 +#define SRST_H_RKRNG_S 39 +#define SRST_H_RKRNG_NS 40 + +/* BUSCRU-->SOFTRST_CON03 */ +#define SRST_P_I2C0 41 +#define SRST_I2C0 42 +#define SRST_P_I2C1 43 +#define SRST_I2C1 44 +#define SRST_P_I2C3 45 +#define SRST_I2C3 46 +#define SRST_P_I2C4 47 +#define SRST_I2C4 48 +#define SRST_P_I2C5 49 +#define SRST_I2C5 50 +#define SRST_P_SPI0 51 +#define SRST_SPI0 52 +#define SRST_P_SPI1 53 +#define SRST_SPI1 54 + +/* BUSCRU-->SOFTRST_CON04 */ +#define SRST_P_PWM0 55 +#define SRST_PWM0 56 +#define SRST_P_PWM2 57 +#define SRST_PWM2 58 +#define SRST_P_PWM3 59 +#define SRST_PWM3 60 + +/* BUSCRU-->SOFTRST_CON05 */ +#define SRST_P_UART1 61 +#define SRST_S_UART1 62 +#define SRST_P_UART2 63 +#define SRST_S_UART2 64 +#define SRST_P_UART3 65 +#define SRST_S_UART3 66 +#define SRST_P_UART4 67 +#define SRST_S_UART4 68 +#define SRST_P_UART5 69 +#define SRST_S_UART5 70 +#define SRST_P_UART6 71 +#define SRST_S_UART6 72 +#define SRST_P_UART7 73 +#define SRST_S_UART7 74 + +/* BUSCRU-->SOFTRST_CON06 */ +#define SRST_P_TSADC 75 +#define SRST_TSADC 76 +#define SRST_H_SAI0 77 +#define SRST_M_SAI0 78 +#define SRST_H_SAI1 79 +#define SRST_M_SAI1 80 +#define SRST_H_SAI2 81 +#define SRST_M_SAI2 82 +#define SRST_H_RKDSM 83 +#define SRST_M_RKDSM 84 +#define SRST_H_PDM 85 +#define SRST_M_PDM 86 +#define SRST_PDM 87 + +/* BUSCRU-->SOFTRST_CON07 */ +#define SRST_H_ASRC0 88 +#define SRST_ASRC0 89 +#define SRST_H_ASRC1 90 +#define SRST_ASRC1 91 +#define SRST_P_AUDIO_ADC_BUS 92 +#define SRST_M_AUDIO_ADC_BUS 93 +#define SRST_P_RKCE 94 +#define SRST_H_NS_RKCE 95 +#define SRST_P_OTPC_NS 96 +#define SRST_SBPI_OTPC_NS 97 +#define SRST_USER_OTPC_NS 98 +#define SRST_OTPC_ARB 99 +#define SRST_P_OTP_MASK 100 + +/* PERICRU-->SOFTRST_CON00 */ +#define SRST_A_PERI_BIU 101 +#define SRST_P_PERI_BIU 102 +#define SRST_P_RTC_BIU 103 +#define SRST_P_CRU_PERI 104 +#define SRST_P_PERI_GRF 105 +#define SRST_P_GPIO1 106 +#define SRST_DB_GPIO1 107 +#define SRST_P_IOC_VCCIO1 108 +#define SRST_A_USB3OTG 109 +#define SRST_H_USB2HOST 110 +#define SRST_H_ARB_USB2HOST 111 +#define SRST_P_RTC_TEST 112 + +/* PERICRU-->SOFTRST_CON01 */ +#define SRST_H_EMMC 113 +#define SRST_H_FSPI0 114 +#define SRST_H_XIP_FSPI0 115 +#define SRST_S_2X_FSPI0 116 +#define SRST_UTMI_USB2HOST 117 +#define SRST_REF_PIPEPHY 118 +#define SRST_P_PIPEPHY 119 +#define SRST_P_PIPEPHY_GRF 120 +#define SRST_P_USB2PHY 121 +#define SRST_POR_USB2PHY 122 +#define SRST_OTG_USB2PHY 123 +#define SRST_HOST_USB2PHY 124 + +/* CORECRU-->SOFTRST_CON00 */ +#define SRST_REF_PVTPLL_CORE 125 +#define SRST_NCOREPORESET0 126 +#define SRST_NCORESET0 127 +#define SRST_NCOREPORESET1 128 +#define SRST_NCORESET1 129 +#define SRST_NCOREPORESET2 130 +#define SRST_NCORESET2 131 +#define SRST_NCOREPORESET3 132 +#define SRST_NCORESET3 133 +#define SRST_NDBGRESET 134 +#define SRST_NL2RESET 135 + +/* CORECRU-->SOFTRST_CON01 */ +#define SRST_A_CORE_BIU 136 +#define SRST_P_CORE_BIU 137 +#define SRST_H_CORE_BIU 138 +#define SRST_P_DBG 139 +#define SRST_POT_DBG 140 +#define SRST_NT_DBG 141 +#define SRST_P_CORE_PVTPLL 142 +#define SRST_P_CRU_CORE 143 +#define SRST_P_CORE_GRF 144 +#define SRST_P_DFT2APB 145 + +/* PMUCRU-->SOFTRST_CON00 */ +#define SRST_H_PMU_BIU 146 +#define SRST_P_PMU_GPIO0 147 +#define SRST_DB_PMU_GPIO0 148 +#define SRST_P_PMU_HP_TIMER 149 +#define SRST_PMU_HP_TIMER 150 +#define SRST_PMU_32K_HP_TIMER 151 + +/* PMUCRU-->SOFTRST_CON01 */ +#define SRST_P_PWM1 152 +#define SRST_PWM1 153 +#define SRST_P_I2C2 154 +#define SRST_I2C2 155 +#define SRST_P_UART0 156 +#define SRST_S_UART0 157 + +/* PMUCRU-->SOFTRST_CON02 */ +#define SRST_P_RCOSC_CTRL 158 +#define SRST_REF_RCOSC_CTRL 159 +#define SRST_P_IOC_PMUIO0 160 +#define SRST_P_CRU_PMU 161 +#define SRST_P_PMU_GRF 162 +#define SRST_PREROLL 163 +#define SRST_PREROLL_32K 164 +#define SRST_H_PMU_SRAM 165 + +/* PMUCRU-->SOFTRST_CON03 */ +#define SRST_P_WDT_LPMCU 166 +#define SRST_T_WDT_LPMCU 167 +#define SRST_LPMCU_FULL_CLUSTER 168 +#define SRST_LPMCU_PWUP 169 +#define SRST_LPMCU_ONLY_CORE 170 +#define SRST_T_LPMCU_JTAG 171 +#define SRST_P_LPMCU_MAILBOX 172 + +/* PMU1CRU-->SOFTRST_CON00 */ +#define SRST_P_SPI2AHB 173 +#define SRST_H_SPI2AHB 174 +#define SRST_H_FSPI1 175 +#define SRST_H_XIP_FSPI1 176 +#define SRST_S_1X_FSPI1 177 +#define SRST_P_IOC_PMUIO1 178 +#define SRST_P_CRU_PMU1 179 +#define SRST_P_AUDIO_ADC_PMU 180 +#define SRST_M_AUDIO_ADC_PMU 181 +#define SRST_H_PMU1_BIU 182 + +/* PMU1CRU-->SOFTRST_CON01 */ +#define SRST_P_LPDMA 183 +#define SRST_A_LPDMA 184 +#define SRST_H_LPSAI 185 +#define SRST_M_LPSAI 186 +#define SRST_P_AOA_TDD 187 +#define SRST_P_AOA_FE 188 +#define SRST_P_AOA_AAD 189 +#define SRST_P_AOA_APB 190 +#define SRST_P_AOA_SRAM 191 + +/* DDRCRU-->SOFTRST_CON00 */ +#define SRST_P_DDR_BIU 192 +#define SRST_P_DDRC 193 +#define SRST_P_DDRMON 194 +#define SRST_TIMER_DDRMON 195 +#define SRST_P_DFICTRL 196 +#define SRST_P_DDR_GRF 197 +#define SRST_P_CRU_DDR 198 +#define SRST_P_DDRPHY 199 +#define SRST_P_DMA2DDR 200 + +/* SUBDDRCRU-->SOFTRST_CON00 */ +#define SRST_A_SYSMEM_BIU 201 +#define SRST_A_SYSMEM 202 +#define SRST_A_DDR_BIU 203 +#define SRST_A_DDRSCH0_CPU 204 +#define SRST_A_DDRSCH1_NPU 205 +#define SRST_A_DDRSCH2_POE 206 +#define SRST_A_DDRSCH3_VI 207 +#define SRST_CORE_DDRC 208 +#define SRST_DDRMON 209 +#define SRST_DFICTRL 210 +#define SRST_RS 211 +#define SRST_A_DMA2DDR 212 +#define SRST_DDRPHY 213 + +/* VICRU-->SOFTRST_CON00 */ +#define SRST_REF_PVTPLL_ISP 214 +#define SRST_A_GMAC_BIU 215 +#define SRST_A_VI_BIU 216 +#define SRST_H_VI_BIU 217 +#define SRST_P_VI_BIU 218 +#define SRST_P_CRU_VI 219 +#define SRST_P_VI_GRF 220 +#define SRST_P_VI_PVTPLL 221 +#define SRST_P_DSMC 222 +#define SRST_A_DSMC 223 +#define SRST_H_CAN0 224 +#define SRST_CAN0 225 +#define SRST_H_CAN1 226 +#define SRST_CAN1 227 + +/* VICRU-->SOFTRST_CON01 */ +#define SRST_P_GPIO2 228 +#define SRST_DB_GPIO2 229 +#define SRST_P_GPIO4 230 +#define SRST_DB_GPIO4 231 +#define SRST_P_GPIO5 232 +#define SRST_DB_GPIO5 233 +#define SRST_P_GPIO6 234 +#define SRST_DB_GPIO6 235 +#define SRST_P_GPIO7 236 +#define SRST_DB_GPIO7 237 +#define SRST_P_IOC_VCCIO2 238 +#define SRST_P_IOC_VCCIO4 239 +#define SRST_P_IOC_VCCIO5 240 +#define SRST_P_IOC_VCCIO6 241 +#define SRST_P_IOC_VCCIO7 242 + +/* VICRU-->SOFTRST_CON02 */ +#define SRST_CORE_ISP 243 +#define SRST_H_VICAP 244 +#define SRST_A_VICAP 245 +#define SRST_D_VICAP 246 +#define SRST_ISP0_VICAP 247 +#define SRST_CORE_VPSS 248 +#define SRST_CORE_VPSL 249 +#define SRST_P_CSI2HOST0 250 +#define SRST_P_CSI2HOST1 251 +#define SRST_P_CSI2HOST2 252 +#define SRST_P_CSI2HOST3 253 +#define SRST_H_SDMMC0 254 +#define SRST_A_GMAC 255 +#define SRST_P_CSIPHY0 256 +#define SRST_P_CSIPHY1 257 + +/* VICRU-->SOFTRST_CON03 */ +#define SRST_P_MACPHY 258 +#define SRST_MACPHY 259 +#define SRST_P_SARADC1 260 +#define SRST_SARADC1 261 +#define SRST_P_SARADC2 262 +#define SRST_SARADC2 263 + +/* VEPUCRU-->SOFTRST_CON00 */ +#define SRST_REF_PVTPLL_VEPU 264 +#define SRST_A_VEPU_BIU 265 +#define SRST_H_VEPU_BIU 266 +#define SRST_P_VEPU_BIU 267 +#define SRST_P_CRU_VEPU 268 +#define SRST_P_VEPU_GRF 269 +#define SRST_P_GPIO3 270 +#define SRST_DB_GPIO3 271 +#define SRST_P_IOC_VCCIO3 272 +#define SRST_P_SARADC0 273 +#define SRST_SARADC0 274 +#define SRST_H_SDMMC1 275 + +/* VEPUCRU-->SOFTRST_CON01 */ +#define SRST_P_VEPU_PVTPLL 276 +#define SRST_H_VEPU 277 +#define SRST_A_VEPU 278 +#define SRST_CORE_VEPU 279 + +/* NPUCRU-->SOFTRST_CON00 */ +#define SRST_REF_PVTPLL_NPU 280 +#define SRST_A_NPU_BIU 281 +#define SRST_H_NPU_BIU 282 +#define SRST_P_NPU_BIU 283 +#define SRST_P_CRU_NPU 284 +#define SRST_P_NPU_GRF 285 +#define SRST_P_NPU_PVTPLL 286 +#define SRST_H_RKNN 287 +#define SRST_A_RKNN 288 + +/* VDOCRU-->SOFTRST_CON00 */ +#define SRST_A_RKVDEC_BIU 289 +#define SRST_A_VDO_BIU 290 +#define SRST_H_VDO_BIU 291 +#define SRST_P_VDO_BIU 292 +#define SRST_P_CRU_VDO 293 +#define SRST_P_VDO_GRF 294 +#define SRST_A_RKVDEC 295 +#define SRST_H_RKVDEC 296 +#define SRST_HEVC_CA_RKVDEC 297 +#define SRST_A_VOP 298 +#define SRST_H_VOP 299 +#define SRST_D_VOP 300 +#define SRST_A_OOC 301 +#define SRST_H_OOC 302 +#define SRST_D_OOC 303 + +/* VDOCRU-->SOFTRST_CON01 */ +#define SRST_H_RKJPEG 304 +#define SRST_A_RKJPEG 305 +#define SRST_A_RKMMU_DECOM 306 +#define SRST_H_RKMMU_DECOM 307 +#define SRST_D_DECOM 308 +#define SRST_A_DECOM 309 +#define SRST_P_DECOM 310 +#define SRST_P_MIPI_DSI 311 +#define SRST_P_DSIPHY 312 + +/* VCPCRU-->SOFTRST_CON00 */ +#define SRST_REF_PVTPLL_VCP 313 +#define SRST_A_VCP_BIU 314 +#define SRST_H_VCP_BIU 315 +#define SRST_P_VCP_BIU 316 +#define SRST_P_CRU_VCP 317 +#define SRST_P_VCP_GRF 318 +#define SRST_P_VCP_PVTPLL 319 +#define SRST_A_AISP_BIU 320 +#define SRST_H_AISP_BIU 321 +#define SRST_CORE_AISP 322 + +/* VCPCRU-->SOFTRST_CON01 */ +#define SRST_H_FEC 323 +#define SRST_A_FEC 324 +#define SRST_CORE_FEC 325 +#define SRST_H_AVSP 326 +#define SRST_A_AVSP 327 + +#endif diff --git a/dts/upstream/include/dt-bindings/reset/thead,th1520-reset.h b/dts/upstream/include/dt-bindings/reset/thead,th1520-reset.h index ee799286c17..ba6805b6b12 100644 --- a/dts/upstream/include/dt-bindings/reset/thead,th1520-reset.h +++ b/dts/upstream/include/dt-bindings/reset/thead,th1520-reset.h @@ -7,11 +7,202 @@ #ifndef _DT_BINDINGS_TH1520_RESET_H #define _DT_BINDINGS_TH1520_RESET_H +/* AO Subsystem */ +#define TH1520_RESET_ID_SYSTEM 0 +#define TH1520_RESET_ID_RTC_APB 1 +#define TH1520_RESET_ID_RTC_REF 2 +#define TH1520_RESET_ID_AOGPIO_DB 3 +#define TH1520_RESET_ID_AOGPIO_APB 4 +#define TH1520_RESET_ID_AOI2C_APB 5 +#define TH1520_RESET_ID_PVT_APB 6 +#define TH1520_RESET_ID_E902_CORE 7 +#define TH1520_RESET_ID_E902_HAD 8 +#define TH1520_RESET_ID_AOTIMER_APB 9 +#define TH1520_RESET_ID_AOTIMER_CORE 10 +#define TH1520_RESET_ID_AOWDT_APB 11 +#define TH1520_RESET_ID_APSYS 12 +#define TH1520_RESET_ID_NPUSYS 13 +#define TH1520_RESET_ID_DDRSYS 14 +#define TH1520_RESET_ID_AXI_AP2CP 15 +#define TH1520_RESET_ID_AXI_CP2AP 16 +#define TH1520_RESET_ID_AXI_CP2SRAM 17 +#define TH1520_RESET_ID_AUDSYS_CORE 18 +#define TH1520_RESET_ID_AUDSYS_IOPMP 19 +#define TH1520_RESET_ID_AUDSYS 20 +#define TH1520_RESET_ID_DSP0 21 +#define TH1520_RESET_ID_DSP1 22 +#define TH1520_RESET_ID_GPU_MODULE 23 +#define TH1520_RESET_ID_VDEC 24 +#define TH1520_RESET_ID_VENC 25 +#define TH1520_RESET_ID_ADC_APB 26 +#define TH1520_RESET_ID_AUDGPIO_DB 27 +#define TH1520_RESET_ID_AUDGPIO_APB 28 +#define TH1520_RESET_ID_AOUART_IF 29 +#define TH1520_RESET_ID_AOUART_APB 30 +#define TH1520_RESET_ID_SRAM_AXI_P0 31 +#define TH1520_RESET_ID_SRAM_AXI_P1 32 +#define TH1520_RESET_ID_SRAM_AXI_P2 33 +#define TH1520_RESET_ID_SRAM_AXI_P3 34 +#define TH1520_RESET_ID_SRAM_AXI_P4 35 +#define TH1520_RESET_ID_SRAM_AXI_CORE 36 +#define TH1520_RESET_ID_SE 37 + +/* AP Subsystem */ +#define TH1520_RESET_ID_BROM 0 +#define TH1520_RESET_ID_C910_TOP 1 +#define TH1520_RESET_ID_NPU 2 +#define TH1520_RESET_ID_WDT0 3 +#define TH1520_RESET_ID_WDT1 4 +#define TH1520_RESET_ID_C910_C0 5 +#define TH1520_RESET_ID_C910_C1 6 +#define TH1520_RESET_ID_C910_C2 7 +#define TH1520_RESET_ID_C910_C3 8 +#define TH1520_RESET_ID_CHIP_DBG_CORE 9 +#define TH1520_RESET_ID_CHIP_DBG_AXI 10 +#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11 +#define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12 +#define TH1520_RESET_ID_X2H_CPUSYS 13 +#define TH1520_RESET_ID_AHB2_CPUSYS 14 +#define TH1520_RESET_ID_APB3_CPUSYS 15 +#define TH1520_RESET_ID_MBOX0_APB 16 +#define TH1520_RESET_ID_MBOX1_APB 17 +#define TH1520_RESET_ID_MBOX2_APB 18 +#define TH1520_RESET_ID_MBOX3_APB 19 +#define TH1520_RESET_ID_TIMER0_APB 20 +#define TH1520_RESET_ID_TIMER0_CORE 21 +#define TH1520_RESET_ID_TIMER1_APB 22 +#define TH1520_RESET_ID_TIMER1_CORE 23 +#define TH1520_RESET_ID_PERISYS_AHB 24 +#define TH1520_RESET_ID_PERISYS_APB1 25 +#define TH1520_RESET_ID_PERISYS_APB2 26 +#define TH1520_RESET_ID_GMAC0_APB 27 +#define TH1520_RESET_ID_GMAC0_AHB 28 +#define TH1520_RESET_ID_GMAC0_CLKGEN 29 +#define TH1520_RESET_ID_GMAC0_AXI 30 +#define TH1520_RESET_ID_UART0_APB 31 +#define TH1520_RESET_ID_UART0_IF 32 +#define TH1520_RESET_ID_UART1_APB 33 +#define TH1520_RESET_ID_UART1_IF 34 +#define TH1520_RESET_ID_UART2_APB 35 +#define TH1520_RESET_ID_UART2_IF 36 +#define TH1520_RESET_ID_UART3_APB 37 +#define TH1520_RESET_ID_UART3_IF 38 +#define TH1520_RESET_ID_UART4_APB 39 +#define TH1520_RESET_ID_UART4_IF 40 +#define TH1520_RESET_ID_UART5_APB 41 +#define TH1520_RESET_ID_UART5_IF 42 +#define TH1520_RESET_ID_QSPI0_IF 43 +#define TH1520_RESET_ID_QSPI0_APB 44 +#define TH1520_RESET_ID_QSPI1_IF 45 +#define TH1520_RESET_ID_QSPI1_APB 46 +#define TH1520_RESET_ID_SPI_IF 47 +#define TH1520_RESET_ID_SPI_APB 48 +#define TH1520_RESET_ID_I2C0_APB 49 +#define TH1520_RESET_ID_I2C0_CORE 50 +#define TH1520_RESET_ID_I2C1_APB 51 +#define TH1520_RESET_ID_I2C1_CORE 52 +#define TH1520_RESET_ID_I2C2_APB 53 +#define TH1520_RESET_ID_I2C2_CORE 54 +#define TH1520_RESET_ID_I2C3_APB 55 +#define TH1520_RESET_ID_I2C3_CORE 56 +#define TH1520_RESET_ID_I2C4_APB 57 +#define TH1520_RESET_ID_I2C4_CORE 58 +#define TH1520_RESET_ID_I2C5_APB 59 +#define TH1520_RESET_ID_I2C5_CORE 60 +#define TH1520_RESET_ID_GPIO0_DB 61 +#define TH1520_RESET_ID_GPIO0_APB 62 +#define TH1520_RESET_ID_GPIO1_DB 63 +#define TH1520_RESET_ID_GPIO1_APB 64 +#define TH1520_RESET_ID_GPIO2_DB 65 +#define TH1520_RESET_ID_GPIO2_APB 66 +#define TH1520_RESET_ID_PWM_COUNTER 67 +#define TH1520_RESET_ID_PWM_APB 68 +#define TH1520_RESET_ID_PADCTRL0_APB 69 +#define TH1520_RESET_ID_CPU2PERI_X2H 70 +#define TH1520_RESET_ID_CPU2AON_X2H 71 +#define TH1520_RESET_ID_AON2CPU_A2X 72 +#define TH1520_RESET_ID_NPUSYS_AXI 73 +#define TH1520_RESET_ID_NPUSYS_AXI_APB 74 +#define TH1520_RESET_ID_CPU2VP_X2P 75 +#define TH1520_RESET_ID_CPU2VI_X2H 76 +#define TH1520_RESET_ID_BMU_AXI 77 +#define TH1520_RESET_ID_BMU_APB 78 +#define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79 +#define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80 +#define TH1520_RESET_ID_SPINLOCK 81 +#define TH1520_RESET_ID_CFG2TEE 82 +#define TH1520_RESET_ID_DSMART 83 +#define TH1520_RESET_ID_GPIO3_DB 84 +#define TH1520_RESET_ID_GPIO3_APB 85 +#define TH1520_RESET_ID_PERI_I2S 86 +#define TH1520_RESET_ID_PERI_APB3 87 +#define TH1520_RESET_ID_PERI2PERI1_APB 88 +#define TH1520_RESET_ID_VPSYS_APB 89 +#define TH1520_RESET_ID_PERISYS_APB4 90 +#define TH1520_RESET_ID_GMAC1_APB 91 +#define TH1520_RESET_ID_GMAC1_AHB 92 +#define TH1520_RESET_ID_GMAC1_CLKGEN 93 +#define TH1520_RESET_ID_GMAC1_AXI 94 +#define TH1520_RESET_ID_GMAC_AXI 95 +#define TH1520_RESET_ID_GMAC_AXI_APB 96 +#define TH1520_RESET_ID_PADCTRL1_APB 97 +#define TH1520_RESET_ID_VOSYS_AXI 98 +#define TH1520_RESET_ID_VOSYS_AXI_APB 99 +#define TH1520_RESET_ID_VOSYS_AXI_X2X 100 +#define TH1520_RESET_ID_MISC2VP_X2X 101 +#define TH1520_RESET_ID_DSPSYS 102 +#define TH1520_RESET_ID_VISYS 103 +#define TH1520_RESET_ID_VOSYS 104 +#define TH1520_RESET_ID_VPSYS 105 + +/* DSP Subsystem */ +#define TH1520_RESET_ID_X2X_DSP1 0 +#define TH1520_RESET_ID_X2X_DSP0 1 +#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2 +#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3 +#define TH1520_RESET_ID_DSP0_CORE 4 +#define TH1520_RESET_ID_DSP0_DEBUG 5 +#define TH1520_RESET_ID_DSP0_APB 6 +#define TH1520_RESET_ID_DSP1_CORE 7 +#define TH1520_RESET_ID_DSP1_DEBUG 8 +#define TH1520_RESET_ID_DSP1_APB 9 +#define TH1520_RESET_ID_DSPSYS_APB 10 +#define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11 +#define TH1520_RESET_ID_AXI4_DSPSYS 12 +#define TH1520_RESET_ID_AXI4_DSP_RS 13 + +/* MISC Subsystem */ +#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0 +#define TH1520_RESET_ID_EMMC 1 +#define TH1520_RESET_ID_MISCSYS_AXI 2 +#define TH1520_RESET_ID_MISCSYS_AXI_APB 3 +#define TH1520_RESET_ID_SDIO0 4 +#define TH1520_RESET_ID_SDIO1 5 +#define TH1520_RESET_ID_USB3_APB 6 +#define TH1520_RESET_ID_USB3_PHY 7 +#define TH1520_RESET_ID_USB3_VCC 8 + +/* VI Subsystem */ +#define TH1520_RESET_ID_ISP0 0 +#define TH1520_RESET_ID_ISP1 1 +#define TH1520_RESET_ID_CSI0_APB 2 +#define TH1520_RESET_ID_CSI1_APB 3 +#define TH1520_RESET_ID_CSI2_APB 4 +#define TH1520_RESET_ID_MIPI_FIFO 5 +#define TH1520_RESET_ID_ISP_VENC_APB 6 +#define TH1520_RESET_ID_VIPRE_APB 7 +#define TH1520_RESET_ID_VIPRE_AXI 8 +#define TH1520_RESET_ID_DW200_APB 9 +#define TH1520_RESET_ID_VISYS3_AXI 10 +#define TH1520_RESET_ID_VISYS2_AXI 11 +#define TH1520_RESET_ID_VISYS1_AXI 12 +#define TH1520_RESET_ID_VISYS_AXI 13 +#define TH1520_RESET_ID_VISYS_APB 14 +#define TH1520_RESET_ID_ISP_VENC_AXI 15 + +/* VO Subsystem */ #define TH1520_RESET_ID_GPU 0 #define TH1520_RESET_ID_GPU_CLKGEN 1 -#define TH1520_RESET_ID_NPU 2 -#define TH1520_RESET_ID_WDT0 3 -#define TH1520_RESET_ID_WDT1 4 #define TH1520_RESET_ID_DPU_AHB 5 #define TH1520_RESET_ID_DPU_AXI 6 #define TH1520_RESET_ID_DPU_CORE 7 @@ -19,5 +210,27 @@ #define TH1520_RESET_ID_DSI1_APB 9 #define TH1520_RESET_ID_HDMI 10 #define TH1520_RESET_ID_HDMI_APB 11 +#define TH1520_RESET_ID_VOAXI 12 +#define TH1520_RESET_ID_VOAXI_APB 13 +#define TH1520_RESET_ID_X2H_DPU_AXI 14 +#define TH1520_RESET_ID_X2H_DPU_AHB 15 +#define TH1520_RESET_ID_X2H_DPU1_AXI 16 +#define TH1520_RESET_ID_X2H_DPU1_AHB 17 + +/* VP Subsystem */ +#define TH1520_RESET_ID_VPSYS_AXI_APB 0 +#define TH1520_RESET_ID_VPSYS_AXI 1 +#define TH1520_RESET_ID_FCE_APB 2 +#define TH1520_RESET_ID_FCE_CORE 3 +#define TH1520_RESET_ID_FCE_X2X_MASTER 4 +#define TH1520_RESET_ID_FCE_X2X_SLAVE 5 +#define TH1520_RESET_ID_G2D_APB 6 +#define TH1520_RESET_ID_G2D_ACLK 7 +#define TH1520_RESET_ID_G2D_CORE 8 +#define TH1520_RESET_ID_VDEC_APB 9 +#define TH1520_RESET_ID_VDEC_ACLK 10 +#define TH1520_RESET_ID_VDEC_CORE 11 +#define TH1520_RESET_ID_VENC_APB 12 +#define TH1520_RESET_ID_VENC_CORE 13 #endif /* _DT_BINDINGS_TH1520_RESET_H */ diff --git a/dts/upstream/include/dt-bindings/reset/toshiba,tmpv770x.h b/dts/upstream/include/dt-bindings/reset/toshiba,tmpv770x.h index c1007acb194..9452bef3142 100644 --- a/dts/upstream/include/dt-bindings/reset/toshiba,tmpv770x.h +++ b/dts/upstream/include/dt-bindings/reset/toshiba,tmpv770x.h @@ -36,6 +36,13 @@ #define TMPV770X_RESET_PIPCMIF 29 #define TMPV770X_RESET_PICKMON 30 #define TMPV770X_RESET_SBUSCLK 31 -#define TMPV770X_NR_RESET 32 +#define TMPV770X_RESET_VIIFBS0 32 +#define TMPV770X_RESET_VIIFBS0_APB 33 +#define TMPV770X_RESET_VIIFBS0_L2ISP 34 +#define TMPV770X_RESET_VIIFBS0_L1ISP 35 +#define TMPV770X_RESET_VIIFBS1 36 +#define TMPV770X_RESET_VIIFBS1_APB 37 +#define TMPV770X_RESET_VIIFBS1_L2ISP 38 +#define TMPV770X_RESET_VIIFBS1_L1ISP 39 #endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */ diff --git a/dts/upstream/include/dt-bindings/watchdog/aspeed-wdt.h b/dts/upstream/include/dt-bindings/watchdog/aspeed-wdt.h index 7ae6d84b2bd..89fa31ffce2 100644 --- a/dts/upstream/include/dt-bindings/watchdog/aspeed-wdt.h +++ b/dts/upstream/include/dt-bindings/watchdog/aspeed-wdt.h @@ -89,4 +89,142 @@ #define AST2600_WDT_RESET2_DEFAULT 0x03fffff1 +#define AST2700_WDT_RESET1_CPU (1 << 0) +#define AST2700_WDT_RESET1_DRAM (1 << 1) +#define AST2700_WDT_RESET1_SLI0 (1 << 2) +#define AST2700_WDT_RESET1_EHCI (1 << 3) +#define AST2700_WDT_RESET1_HACE (1 << 4) +#define AST2700_WDT_RESET1_SOC_MISC0 (1 << 5) +#define AST2700_WDT_RESET1_VIDEO (1 << 6) +#define AST2700_WDT_RESET1_2D_GRAPHIC (1 << 7) +#define AST2700_WDT_RESET1_RAVS0 (1 << 8) +#define AST2700_WDT_RESET1_RAVS1 (1 << 9) +#define AST2700_WDT_RESET1_GPIO0 (1 << 10) +#define AST2700_WDT_RESET1_SSP (1 << 11) +#define AST2700_WDT_RESET1_TSP (1 << 12) +#define AST2700_WDT_RESET1_CRT (1 << 13) +#define AST2700_WDT_RESET1_USB20_HOST (1 << 14) +#define AST2700_WDT_RESET1_USB11_HOST (1 << 15) +#define AST2700_WDT_RESET1_UFS (1 << 16) +#define AST2700_WDT_RESET1_EMMC (1 << 17) +#define AST2700_WDT_RESET1_AHB_TO_PCIE1 (1 << 18) +#define AST2700_WDT_RESET1_XDMA0 (1 << 22) +#define AST2700_WDT_RESET1_MCTP1 (1 << 23) +#define AST2700_WDT_RESET1_MCTP0 (1 << 24) +#define AST2700_WDT_RESET1_JTAG0 (1 << 25) +#define AST2700_WDT_RESET1_ECC (1 << 26) +#define AST2700_WDT_RESET1_XDMA1 (1 << 27) +#define AST2700_WDT_RESET1_DP (1 << 28) +#define AST2700_WDT_RESET1_DP_MCU (1 << 29) +#define AST2700_WDT_RESET1_AHB_TO_PCIE0 (1 << 31) + +#define AST2700_WDT_RESET1_DEFAULT 0x8207ff71 + +#define AST2700_WDT_RESET2_USB3_A_HOST (1 << 0) +#define AST2700_WDT_RESET2_USB3_A_VHUB3 (1 << 1) +#define AST2700_WDT_RESET2_USB3_A_VHUB2 (1 << 2) +#define AST2700_WDT_RESET2_USB3_B_HOST (1 << 3) +#define AST2700_WDT_RESET2_USB3_B_VHUB3 (1 << 4) +#define AST2700_WDT_RESET2_USB3_B_VHUB2 (1 << 5) +#define AST2700_WDT_RESET2_SM3 (1 << 6) +#define AST2700_WDT_RESET2_SM4 (1 << 7) +#define AST2700_WDT_RESET2_SHA3 (1 << 8) +#define AST2700_WDT_RESET2_RSA (1 << 9) + +#define AST2700_WDT_RESET2_DEFAULT 0x000003f6 + +#define AST2700_WDT_RESET3_LPC0 (1 << 0) +#define AST2700_WDT_RESET3_LPC1 (1 << 1) +#define AST2700_WDT_RESET3_MDIO (1 << 2) +#define AST2700_WDT_RESET3_PECI (1 << 3) +#define AST2700_WDT_RESET3_PWM (1 << 4) +#define AST2700_WDT_RESET3_MAC0 (1 << 5) +#define AST2700_WDT_RESET3_MAC1 (1 << 6) +#define AST2700_WDT_RESET3_MAC2 (1 << 7) +#define AST2700_WDT_RESET3_ADC (1 << 8) +#define AST2700_WDT_RESET3_SDC (1 << 9) +#define AST2700_WDT_RESET3_ESPI0 (1 << 10) +#define AST2700_WDT_RESET3_ESPI1 (1 << 11) +#define AST2700_WDT_RESET3_JTAG1 (1 << 12) +#define AST2700_WDT_RESET3_SPI0 (1 << 13) +#define AST2700_WDT_RESET3_SPI1 (1 << 14) +#define AST2700_WDT_RESET3_SPI2 (1 << 15) +#define AST2700_WDT_RESET3_I3C0 (1 << 16) +#define AST2700_WDT_RESET3_I3C1 (1 << 17) +#define AST2700_WDT_RESET3_I3C2 (1 << 18) +#define AST2700_WDT_RESET3_I3C3 (1 << 19) +#define AST2700_WDT_RESET3_I3C4 (1 << 20) +#define AST2700_WDT_RESET3_I3C5 (1 << 21) +#define AST2700_WDT_RESET3_I3C6 (1 << 22) +#define AST2700_WDT_RESET3_I3C7 (1 << 23) +#define AST2700_WDT_RESET3_I3C8 (1 << 24) +#define AST2700_WDT_RESET3_I3C9 (1 << 25) +#define AST2700_WDT_RESET3_I3C10 (1 << 26) +#define AST2700_WDT_RESET3_I3C11 (1 << 27) +#define AST2700_WDT_RESET3_I3C12 (1 << 28) +#define AST2700_WDT_RESET3_I3C13 (1 << 29) +#define AST2700_WDT_RESET3_I3C14 (1 << 30) +#define AST2700_WDT_RESET3_I3C15 (1 << 31) + +#define AST2700_WDT_RESET3_DEFAULT 0x000093ec + +#define AST2700_WDT_RESET4_FMC (1 << 0) +#define AST2700_WDT_RESET4_SOC_MISC1 (1 << 1) +#define AST2700_WDT_RESET4_AHB (1 << 2) +#define AST2700_WDT_RESET4_SLI1 (1 << 3) +#define AST2700_WDT_RESET4_UART0 (1 << 4) +#define AST2700_WDT_RESET4_UART1 (1 << 5) +#define AST2700_WDT_RESET4_UART2 (1 << 6) +#define AST2700_WDT_RESET4_UART3 (1 << 7) +#define AST2700_WDT_RESET4_I2C_MONITOR (1 << 8) +#define AST2700_WDT_RESET4_HOST_TO_SPI1 (1 << 9) +#define AST2700_WDT_RESET4_HOST_TO_SPI2 (1 << 10) +#define AST2700_WDT_RESET4_GPIO1 (1 << 11) +#define AST2700_WDT_RESET4_FSI (1 << 12) +#define AST2700_WDT_RESET4_CANBUS (1 << 13) +#define AST2700_WDT_RESET4_MCTP (1 << 14) +#define AST2700_WDT_RESET4_XDMA (1 << 15) +#define AST2700_WDT_RESET4_UART5 (1 << 16) +#define AST2700_WDT_RESET4_UART6 (1 << 17) +#define AST2700_WDT_RESET4_UART7 (1 << 18) +#define AST2700_WDT_RESET4_UART8 (1 << 19) +#define AST2700_WDT_RESET4_BOOT_MCU (1 << 20) +#define AST2700_WDT_RESET4_IO_MCU (1 << 21) +#define AST2700_WDT_RESET4_LTPI0 (1 << 22) +#define AST2700_WDT_RESET4_VGA_LINK (1 << 23) +#define AST2700_WDT_RESET4_LTPI1 (1 << 24) +#define AST2700_WDT_RESET4_LTPI_PHY (1 << 25) +#define AST2700_WDT_RESET4_ACE (1 << 26) +#define AST2700_WDT_RESET4_LTPI_GPIO0 (1 << 28) +#define AST2700_WDT_RESET4_LTPI_GPIO1 (1 << 29) +#define AST2700_WDT_RESET4_AHB_TO_PCIE1 (1 << 30) +#define AST2700_WDT_RESET4_I3C_DMA (1 << 31) + +#define AST2700_WDT_RESET4_DEFAULT 0x40303803 + +#define AST2700_WDT_RESET5_I2C_GLOBAL (1 << 0) +#define AST2700_WDT_RESET5_I2C0 (1 << 1) +#define AST2700_WDT_RESET5_I2C1 (1 << 2) +#define AST2700_WDT_RESET5_I2C2 (1 << 3) +#define AST2700_WDT_RESET5_I2C3 (1 << 4) +#define AST2700_WDT_RESET5_I2C4 (1 << 5) +#define AST2700_WDT_RESET5_I2C5 (1 << 6) +#define AST2700_WDT_RESET5_I2C6 (1 << 7) +#define AST2700_WDT_RESET5_I2C7 (1 << 8) +#define AST2700_WDT_RESET5_I2C8 (1 << 9) +#define AST2700_WDT_RESET5_I2C9 (1 << 10) +#define AST2700_WDT_RESET5_I2C10 (1 << 11) +#define AST2700_WDT_RESET5_I2C11 (1 << 12) +#define AST2700_WDT_RESET5_I2C12 (1 << 13) +#define AST2700_WDT_RESET5_I2C13 (1 << 14) +#define AST2700_WDT_RESET5_I2C14 (1 << 15) +#define AST2700_WDT_RESET5_I2C15 (1 << 16) +#define AST2700_WDT_RESET5_UHCI (1 << 17) +#define AST2700_WDT_RESET5_USB2_C_UART (1 << 18) +#define AST2700_WDT_RESET5_USB2_C (1 << 19) +#define AST2700_WDT_RESET5_USB2_D_UART (1 << 20) +#define AST2700_WDT_RESET5_USB2_D (1 << 21) + +#define AST2700_WDT_RESET5_DEFAULT 0x00320000 + #endif diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-clemente.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-clemente.dts index ecef44d8997..450446913e3 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-clemente.dts @@ -95,6 +95,11 @@ label = "bmc_ready_cpld_noled"; gpios = <&gpio0 ASPEED_GPIO(P, 5) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; }; + + led-hdd { + label = "hdd_led"; + gpios = <&io_expander13 1 GPIO_ACTIVE_LOW>; + }; }; memory@80000000 { @@ -642,12 +647,14 @@ power-monitor@12 { compatible = "ti,lm5066i"; reg = <0x12>; + shunt-resistor-micro-ohms = <183>; }; // PDB power-monitor@14 { compatible = "ti,lm5066i"; reg = <0x14>; + shunt-resistor-micro-ohms = <183>; }; // Module 0 @@ -1197,7 +1204,7 @@ #gpio-cells = <2>; gpio-line-names = "rmc_en_dc_pwr_on", - "", + "HDD_LED_N", "", "", "", diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts index b733efe31e8..1c50e4a367b 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts @@ -240,6 +240,14 @@ &i2c1 { status = "okay"; + mctp-controller; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + temperature-sensor@4b { compatible = "ti,tmp75"; reg = <0x4b>; diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-santabarbara.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-santabarbara.dts index 72c84f31bdf..f74f463cc87 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-santabarbara.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-santabarbara.dts @@ -39,6 +39,38 @@ i2c37 = &i2c12mux0ch5; i2c38 = &i2c12mux0ch6; i2c39 = &i2c12mux0ch7; + i2c48 = &i2c6mux0ch0; + i2c49 = &i2c6mux0ch1; + i2c50 = &i2c6mux0ch2; + i2c51 = &i2c6mux0ch3; + i2c52 = &i2c8mux0ch0; + i2c53 = &i2c8mux0ch1; + i2c54 = &i2c8mux0ch2; + i2c55 = &i2c8mux0ch3; + i2c56 = &i2c10mux0ch0; + i2c57 = &i2c10mux0ch1; + i2c58 = &i2c10mux0ch2; + i2c59 = &i2c10mux0ch3; + i2c60 = &i2c13mux0ch0; + i2c61 = &i2c13mux0ch1; + i2c62 = &i2c13mux0ch2; + i2c63 = &i2c13mux0ch3; + i2c64 = &i2c6mux1ch0; + i2c65 = &i2c6mux1ch1; + i2c66 = &i2c6mux1ch2; + i2c67 = &i2c6mux1ch3; + i2c68 = &i2c8mux1ch0; + i2c69 = &i2c8mux1ch1; + i2c70 = &i2c8mux1ch2; + i2c71 = &i2c8mux1ch3; + i2c72 = &i2c10mux1ch0; + i2c73 = &i2c10mux1ch1; + i2c74 = &i2c10mux1ch2; + i2c75 = &i2c10mux1ch3; + i2c76 = &i2c13mux1ch0; + i2c77 = &i2c13mux1ch1; + i2c78 = &i2c13mux1ch2; + i2c79 = &i2c13mux1ch3; }; chosen { @@ -72,6 +104,11 @@ default-state = "off"; gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; }; + + led-3 { + label = "bmc_ready_noled"; + gpios = <&gpio0 ASPEED_GPIO(B, 3) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; + }; }; memory@80000000 { @@ -171,7 +208,7 @@ "led-postcode-2","led-postcode-3", "led-postcode-4","led-postcode-5", "led-postcode-6","led-postcode-7", - /*O0-O7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","debug-card-mux", /*P0-P7*/ "power-button","","reset-button","", "led-power","","","", /*Q0-Q7*/ "","","","","","","","", @@ -292,6 +329,20 @@ }; }; +&i2c3 { + status = "okay"; + + sbrmi@3c { + compatible = "amd,sbrmi"; + reg = <0x3c>; + }; + + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; +}; + &i2c4 { status = "okay"; @@ -319,16 +370,19 @@ reg = <0x53>; }; }; + i2c4mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -380,16 +434,19 @@ reg = <0x4e>; }; }; + i2c4mux0ch4: i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch5: i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; }; + i2c4mux0ch6: i2c@6 { reg = <6>; #address-cells = <1>; @@ -424,6 +481,7 @@ reg = <0x48>; }; }; + i2c4mux0ch7: i2c@7 { reg = <7>; #address-cells = <1>; @@ -469,16 +527,19 @@ #address-cells = <1>; #size-cells = <0>; }; + i2c5mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; + i2c5mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; + i2c5mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -503,6 +564,7 @@ reg = <0x48>; }; }; + i2c5mux1ch1: i2c@1 { reg = <1>; #address-cells = <1>; @@ -513,6 +575,7 @@ reg = <0x48>; }; }; + i2c5mux1ch2: i2c@2 { reg = <2>; #address-cells = <1>; @@ -542,6 +605,7 @@ shunt-resistor = <2000>; }; }; + i2c5mux1ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -574,6 +638,210 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c6mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c6mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c6mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c6mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c6mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c6mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c7 { @@ -588,6 +856,210 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c8mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c8mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c8mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c8mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c8mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c9 { @@ -604,6 +1076,11 @@ reg = <0x50>; }; + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + // BSM FRU eeprom@56 { compatible = "atmel,24c64"; @@ -619,11 +1096,222 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c10mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c10mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c10mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c10mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c10mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c10mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c11 { + multi-master; + mctp-controller; status = "okay"; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + // OCP NIC TEMP temperature-sensor@1f { compatible = "ti,tmp421"; @@ -663,6 +1351,7 @@ reg = <0x48>; }; }; + i2c12mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; @@ -678,6 +1367,7 @@ reg = <0x43>; }; }; + i2c12mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; @@ -695,6 +1385,7 @@ shunt-resistor = <2000>; }; }; + i2c12mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; @@ -712,6 +1403,7 @@ shunt-resistor = <2000>; }; }; + i2c12mux0ch4: i2c@4 { reg = <4>; #address-cells = <1>; @@ -722,16 +1414,19 @@ reg = <0x49>; }; }; + i2c12mux0ch5: i2c@5 { reg = <5>; #address-cells = <1>; #size-cells = <0>; }; + i2c12mux0ch6: i2c@6 { reg = <6>; #address-cells = <1>; #size-cells = <0>; }; + i2c12mux0ch7: i2c@7 { reg = <7>; #address-cells = <1>; @@ -748,6 +1443,210 @@ compatible = "atmel,24c256"; reg = <0x52>; }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c13mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@64 { + compatible = "microchip,mcp9600"; + reg = <0x64>; + }; + + temperature-sensor@65 { + compatible = "microchip,mcp9600"; + reg = <0x65>; + }; + + temperature-sensor@67 { + compatible = "microchip,mcp9600"; + reg = <0x67>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c13mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + voltage-sensor@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp175"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp175"; + reg = <0x4b>; + }; + + eeprom@56 { + compatible = "atmel,24c256"; + reg = <0x56>; + }; + }; + + i2c13mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c13mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c13mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + potentiometer@2c { + compatible = "adi,ad5272-020"; + reg = <0x2c>; + }; + + potentiometer@2e { + compatible = "adi,ad5272-020"; + reg = <0x2e>; + }; + + potentiometer@2f { + compatible = "adi,ad5272-020"; + reg = <0x2f>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + }; + + i2c13mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + voltage-sensor@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + voltage-sensor@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <1>; + }; + + power-monitor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + power-monitor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp175"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp175"; + reg = <0x49>; + }; + }; + }; }; &i2c14 { @@ -864,7 +1763,9 @@ "FM_IOEXP_U541_INT_N","", /*H4-H7 line 120-127*/ "FM_IOEXP_PDB2_U1003_INT_N","", - "","","","","","", + "","", + "","", + "FM_MAIN_PWREN_RMC_EN_ISO_R","", /*I0-I3 line 128-135*/ "","","","", "PDB_IRQ_PMBUS_ALERT_ISO_R_N","", @@ -873,7 +1774,7 @@ "P12V_SCM_ADC_ALERT","", "CPU0_REGS_I2C_ALERT_N","", "FM_RTC_ALERT_N","", - "APML_CPU0_ALERT_R_N","", + "P0_I3C_APML_ALERT_L","", /*J0-J3 line 144-151*/ "SMB_RJ45_FIO_TMP_ALERT","", "FM_SMB_ALERT_MCIO_0A_N","", @@ -924,11 +1825,17 @@ "PRSNT_LEAK_CABLE_1_R_N","", "PRSNT_LEAK_CABLE_2_R_N","", "PRSNT_HDT_N","", - "","", + "LEAK_SWB_COLDPLATE","", /*P0-P3 line 240-247*/ - "","","","","","","","", + "LEAK_R3_COLDPLATE","", + "LEAK_R2_COLDPLATE","", + "LEAK_R1_COLDPLATE","", + "LEAK_R0_COLDPLATE","", /*P4-P7 line 248-255*/ - "","","","","","","",""; + "LEAK_MB_COLDPLATE","", + "LEAK_PDB1_RIGHT_MANIFOLD","", + "LEAK_PDB1_LEFT_MANIFOLD","", + "LEAK_MB_MANIFOLD",""; status = "okay"; }; diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts index 60b98d602e8..e4172be84e7 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts @@ -49,6 +49,20 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + ramoops@b8dfa000 { + compatible = "ramoops"; + reg = <0xb8dfa000 0x6000>; + record-size = <0x2000>; + console-size = <0x2000>; + pmsg-size = <0x2000>; + max-reason = <1>; + }; + }; + iio-hwmon { compatible = "iio-hwmon"; io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite5.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite5.dts new file mode 100644 index 00000000000..2486981f3d6 --- /dev/null +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite5.dts @@ -0,0 +1,1067 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2025 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Facebook Yosemite 5 BMC"; + compatible = "facebook,yosemite5-bmc", "aspeed,ast2600"; + + aliases { + i2c16 = &i2c5mux0ch0; + i2c17 = &i2c5mux0ch1; + i2c18 = &i2c5mux0ch2; + i2c19 = &i2c5mux0ch3; + i2c20 = &i2c5mux1ch0; + i2c21 = &i2c5mux1ch1; + i2c22 = &i2c5mux1ch2; + i2c23 = &i2c5mux1ch3; + i2c24 = &i2c6mux0ch0; + i2c25 = &i2c6mux0ch1; + i2c26 = &i2c6mux0ch2; + i2c27 = &i2c6mux0ch3; + i2c28 = &i2c8mux0ch0; + i2c29 = &i2c8mux0ch1; + i2c30 = &i2c8mux0ch2; + i2c31 = &i2c8mux0ch3; + i2c32 = &i2c30mux0ch0; + i2c33 = &i2c30mux0ch1; + i2c34 = &i2c30mux0ch2; + i2c35 = &i2c30mux0ch3; + serial0 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "fp_id_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "power_blue"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default>; + status = "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc10_default>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BATTERY_DETECT","","BMC_I2C1_FPGA_ALERT","BMC_READY", + "IOEXP_INT_3V3","FM_ID_LED","","", + /*C0-C7*/ "","","","", + "PMBUS_REQ_N","PSU_FW_UPDATE_REQ_N","","BMC_I2C_SSIF_ALERT", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "FM_BMC_MUX1_SEL","","","", + "","","FM_DEBUG_PORT_PRSNT_N","FM_BMC_DBP_PRESENT_N", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","FLASH_WP_STATUS","BMC_JTAG_MUX_SEL","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "PCIE_EP_RST_EN","BMC_FRU_WP","SCM_HPM_STBY_RST_N", + "SCM_HPM_STBY_EN","STBY_POWER_PG_3V3","TH500_SHDN_OK","","", + /*N0-N7*/ "led-postcode-0","led-postcode-1","led-postcode-2", + "led-postcode-3","led-postcode-4","led-postcode-5", + "led-postcode-6","led-postcode-7", + /*O0-O7*/ "RUN_POWER_PG","PWR_BRAKE","CHASSIS_AC_LOSS","BSM_PRSNT_N", + "PSU_SMB_ALERT","FM_TPM_PRSNT_0_N","PSU_FW_UPDATING_N","", + /*P0-P7*/ "PWR_BTN_BMC_N","IPEX_CABLE_PRSNT","ID_RST_BTN_BMC_N", + "RST_BMC_RSTBTN_OUT_N","BMC_PWR_LED","RUN_POWER_EN","SHDN_FORCE","", + /*Q0-Q7*/ "IRQ_PCH_TPM_SPI_LV3_N","USB_OC0_REAR_N","UART_MUX_SEL", + "I2C_MUX_RESET","RSVD_NV_PLT_DETECT","SPI_TPM_INT", + "CPU_JTAG_MUX_SELECT","THERM_BB_OVERT", + /*R0-R7*/ "THERM_BB_WARN","SPI_BMC_FPGA_INT","CPU_BOOT_DONE","PMBUS_GNT", + "CHASSIS_PWR_BRK","PCIE_WAKE","PDB_THERM_OVERT","SHDN_REQ", + /*S0-S7*/ "","","SYS_BMC_PWRBTN_N","FM_TPM_PRSNT_1_N", + "FM_BMC_DEBUG_SW_N","UID_LED_N","SYS_FAULT_LED_N","RUN_POWER_FAULT", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "FM_DBP_BMC_PRDY_N","","","","","","","", + /*V0-V7*/ "L2_RST_REQ_OUT","L0L1_RST_REQ_OUT","BMC_ID_BEEP_SEL", + "BMC_I2C0_FPGA_ALERT","SMB_BMC_TMP_ALERT","PWR_LED_N", + "SYS_RST_OUT","IRQ_TPM_SPI_N", + /*W0-W7*/ "","","","","","","IRQ_ESPI_LPC_SERIRQ_ALERT0_N","", + /*X0-X7*/ "","FM_DBP_CPU_PREQ_GF_N","","","","","","", + /*Y0-Y7*/ "","","FM_FLASH_LATCH_N","BMC_EMMC_RST_N","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","FM_BOARD_BMC_REV_ID0", + "FM_BOARD_BMC_REV_ID1","FM_BOARD_BMC_REV_ID2","", + /*18C0-18C7*/ "","","SPI_BMC_BIOS_ROM_IRQ0_N","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "FM_BMC_PROT_LS_EN","AC_PWR_BMC_BTN_N","",""; +}; + +/* MB CPLD I2C */ +&i2c0 { + status = "okay"; +}; + +/* CPU I2C */ +&i2c1 { + status = "okay"; +}; + +/* MCIO 2A I2C */ +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + /* Socket 0 SBRMI */ + sbrmi@3c { + compatible = "amd,sbrmi"; + reg = <0x3c>; + }; + + /* Socket 0 SBTSI */ + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; +}; + +&i2c4 { + multi-master; + mctp-controller; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + /* OCP NIC TEMP */ + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + + /* OCP NIC FRU EEPROM */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c5 { + status = "okay"; + + /* I2C MUX for MCIO 1A */ + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + /* I2C MUX for MCIO 0A */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux1ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5mux1ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + /* I2C MUX for PWRPIC #13 ~ #16 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #13 */ + i2c6mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #14 */ + i2c6mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #16 */ + i2c6mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #15 */ + i2c6mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* SCM CPLD I2C */ +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + power-monitor@14 { + compatible = "infineon,xdp710"; + reg = <0x14>; + }; + + adc@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <1>; + }; + + power-sensor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + /* PADDLE BD IOEXP */ + gpio-expander@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "HSC_OC_GPIO0", "HSC_OC_GPIO1", + "HSC_OC_GPIO2", "HSC_OC_GPIO3"; + }; + + power-sensor@42 { + compatible = "ti,ina238"; + reg = <0x42>; + shunt-resistor = <1000>; + }; + + power-monitor@43 { + compatible = "lltc,ltc4287"; + reg = <0x43>; + shunt-resistor-micro-ohms = <250>; + }; + + power-sensor@44 { + compatible = "ti,ina238"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + power-sensor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + power-monitor@47 { + compatible = "ti,tps25990"; + reg = <0x47>; + ti,rimon-micro-ohms = <430000000>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + /* PDB FRU */ + eeprom@56 { + compatible = "atmel,24c128"; + reg = <0x56>; + }; + + /* Paddle BD FRU */ + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + }; + + power-monitor@58 { + compatible = "renesas,isl28022"; + reg = <0x58>; + shunt-resistor-micro-ohms = <1000>; + }; + + power-monitor@59 { + compatible = "renesas,isl28022"; + reg = <0x59>; + shunt-resistor-micro-ohms = <1000>; + }; + + power-monitor@5a { + compatible = "renesas,isl28022"; + reg = <0x5a>; + shunt-resistor-micro-ohms = <1000>; + }; + + power-monitor@5b { + compatible = "renesas,isl28022"; + reg = <0x5b>; + shunt-resistor-micro-ohms = <1000>; + }; + + psu@5c { + compatible = "renesas,raa228006"; + reg = <0x5c>; + }; + + fan-controller@5e{ + compatible = "maxim,max31790"; + reg = <0x5e>; + }; + + /* I2C MUX for PWRPIC #1, #2, #11, #12 */ + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + /* PWRPIC #1 */ + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #2 */ + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* PWRPIC #12 (Connector to CXL BD) */ + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c30mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c30mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c30mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1e { + compatible = "ti,adc128d818"; + reg = <0x1e>; + ti,mode = /bits/ 8 <1>; + }; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + + /* CXL BD IOEXP */ + gpio-expander@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "IRQ_TEMP_0_ALERT_N","IRQ_TEMP_1_ALERT_N", + "ALERT_PMBUS_0_N","ALERT_PMBUS_1_N", + "ALERT_PMBUS_2_N","IRQ_INA230_12V_ALERT_N", + "RST_IOX_CXL_N","DEBUG_UART_SEL_0", + "DEBUG_UART_SEL_1","BMC_REMOTEJTAG_EN_N", + "JTAG_BMC_3V3_CTL_CLR_N","DDR_CH02_I2C_MUX_SEL", + "DDR_CH13_I2C_MUX_SEL","SYS_OK", + "CXL_VRHOT_ALERT_R1_N",""; + }; + + temperature-sensor@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp432"; + reg = <0x4c>; + }; + + power-sensor@4d { + compatible = "ti,ina230"; + reg = <0x4d>; + shunt-resistor = <2000>; + }; + + temperature-sensor@4e { + compatible = "ti,tmp75"; + reg = <0x4e>; + }; + + /* CXL FRU */ + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c30mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* PWRPIC #11 */ + i2c8mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c9 { + status = "okay"; + + temperature-sensor@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + + /* SCM FRU */ + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + /* BSM FRU */ + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +/* MCIO 0A I2C */ +&i2c10 { + status = "okay"; + + /* E1S EB IOEXP0 */ + gpio-expander@21 { + compatible = "nxp,pca9535"; + interrupt-parent = <&sgpiom0>; + interrupts = <172 IRQ_TYPE_EDGE_FALLING>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "RST_SMB_E1S_0","LED_ACTIVE_E1S_0", + "E1S_0_PRSNT_N","RST_PCIE_E1S_0_PERST", + "E1S_0_PWRDIS","ALERT_INA_0", + "","", + "RST_SMB_E1S_1","LED_ACTIVE_E1S_1", + "E1S_1_PRSNT_N","RST_PCIE_E1S_1_PERST", + "E1S_1_PWRDIS","ALERT_INA_1", + "",""; + }; + + /* E1S EB IOEXP1 */ + gpio-expander@22 { + compatible = "nxp,pca9535"; + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_EDGE_FALLING>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "P12V_E1S_EN_0","PWRGD_P12V_E1S_0", + "P12V_E1S_FLTB_0","PWRGD_P3V3_E1S_0", + "FM_P3V3_E1S_0_FAULT","P12V_E1S_EN_1", + "PWRGD_P12V_E1S_1","P12V_E1S_FLTB_1", + "PWRGD_P3V3_E1S_1","FM_P3V3_E1S_1_FAULT", + "","", + "","", + "PWRGD_P3V3_AUX","ALERT_TEMP"; + }; + + power-sensor@40 { + compatible = "ti,ina233"; + reg = <0x40>; + shunt-resistor = <2000>; + ti,maximum-expected-current-microamp = <32768000>; + }; + + power-sensor@45 { + compatible = "ti,ina233"; + reg = <0x45>; + shunt-resistor = <2000>; + ti,maximum-expected-current-microamp = <32768000>; + }; + + adc@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + /* E1S EB FRU */ + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c11 { + status = "okay"; + + /* MB IOEXP */ + gpio-expander@21 { + compatible = "nxp,pca9535"; + interrupt-parent = <&sgpiom0>; + interrupts = <170 IRQ_TYPE_EDGE_FALLING>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "ALERT_CLKMUX_0_LOSS_N","ALERT_CLKMUX_1_LOSS_N", + "ALERT_CLKMUX_2_LOSS_N","ALERT_CLKMUX_3_LOSS_N", + "FM_CLKMUX_0_SEL","FM_CLKMUX_1_SEL", + "FM_CLKMUX_2_SEL","FM_CLKMUX_3_SEL", + "RST_USB_HUB_0_N","FM_CLKGEN_GPIO2", + "","FM_BMC_RTC_RST", + "FM_P3V_BAT_SCALED_EN","", + "FM_CLKGEN_GPIO4","RST_USB_HUB_1_N"; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + + power-sensor@42 { + compatible = "ti,ina230"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + + power-sensor@43 { + compatible = "ti,ina230"; + reg = <0x43>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + adc@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + adc@49 { + compatible = "ti,ads7830"; + reg = <0x49>; + }; + + adc@4b { + compatible = "ti,ads7830"; + reg = <0x4b>; + }; +}; + +/* MCIO 4A I2C */ +&i2c12 { + multi-master; + mctp-controller; + status = "okay"; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; +}; + +&i2c13 { + status = "okay"; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + temperature-sensor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "national,lm75b"; + reg = <0x49>; + }; + + /* CLKGEN FRU */ + eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + }; + + /* MB FRU */ + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + /* CPU FRU */ + eeprom@53 { + compatible = "atmel,24c128"; + reg = <0x53>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +/* PROT reserve */ +&i2c14 { + status = "okay"; +}; + +/* MCIO 3A I2C */ +&i2c15 { + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + status = "okay"; +}; + +&mac2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; + status = "okay"; +}; + +&pinctrl { + pinctrl_ncsi3_default: ncsi3_default { + function = "RMII3"; + groups = "NCSI3"; + }; +}; + +&sgpiom0 { + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*"input pin","output pin"*/ + /*bit0-bit7*/ + "PWRGD_CPU_PWROK","SGPIO_RSTBTN_OUT", + "PWRGD_CPU_PWROK_1","SGPIO_BMC_READY", + "PWRGD_CPU_PWROK_2","IBB_BMC_SRST", + "host0-ready","FM_I3C_SPD_AH_SEL_R", + "PCIe_HP_BOOT","FM_I3C_SPD_IP_SEL_R", + "PCIe_HP_DATA","FM_JTAG_BMC_MUX_S0_R", + "PCIe_HP_NIC","FM_JTAG_BMC_MUX_S1_R", + "","FM_JTAG_BMC_OE_1_R_N", + /*bit8-bit15*/ + "PWRGD_PVDDCR_CPU0_P0","FM_JTAG_BMC_OE_R_N", + "PWRGD_PVDDCR_SOC_P0","FM_REMOTEJTAG_EN_R_N", + "PWRGD_PVDDCR_CPU1_P0","FM_CPU_FORCE_SELFREFRESH_R", + "PWRGD_P3V3_STBY","FM_CPU_NMI_SYNC_FLOOD_R_N", + "PWRGD_PVDD33_S5","FM_CPU_TRIGGERTSC_OE_R_N", + "PWRGD_PVDD18_S5_P0","FM_PASSWORD_CLEAR_R_N", + "PWRGD_PVDDIO_P0","FM_BIOS_USB_RECOVERY_N", + "PWRGD_PVDDIO_MEM_S3_P0","FM_USB_MUX_OE_R_N", + /*bit16-bit23*/ + "PWRGD_P1V8_STBY","FM_USB_MUX_SEL_R", + "PWRGD_P1V0_STBY","RST_SMB_BOOT_R_N", + "PWRGD_P1V2_STBY","RST_SMB_MCIO0A_R_N", + "IBB_BMC_SRST","RST_SMB_NIC_R_N", + "PWRGD_P12V_E1S_0","FM_PPS_NIC_IN_BUF_OE_R_N", + "PWRGD_P12V_E1S_1","FM_PPS_NIC_IN_EN_R", + "RST_PCIE_BOOT_PERST_N","FM_PPS_NIC_IN_OE_R_N", + "PWRGD_P12V_NIC","FM_PPS_NIC_IN_S0_R", + /*bit24-bit31*/ + "PWRGD_P12V_SCM","FM_PPS_NIC_IN_S1_R", + "PWRGD_P12V_DIMM","FM_PPS_NIC_OUT_BUF_OE_R_N", + "PWRGD_CPU_DIMM0_AH","FM_PPS_NIC_OUT_CPU_OE_R_N", + "PWRGD_CPU_DIMM1_IP","FM_PPS_NIC_OUT_EN_R", + "PWRGD_NIC_CPLD","JTAG_CPLD_DBREQ_R_N", + "ALERT_INA230_DIMM_0_N","HDT_HDR_RESET_R_N", + "ALERT_INA230_DIMM_1_N","FM_SMB_AUTH_MUX_OE_R_N", + "ALERT_INA230_E1S_0_N","FM_SCM_LED_R_N", + /*bit32-bit39*/ + "ALERT_INA230_E1S_1_N","", + "ALERT_INA230_FAN0_N","", + "ALERT_INA230_FAN1_N","", + "ALERT_INA230_FAN2_N","", + "ALERT_INA230_FAN3_N","", + "ALERT_INA230_NIC_N","", + "ALERT_INA230_SCM_N","", + "ALERT_IRQ_PMBUS_PWR11_N","", + /*bit40-bit47*/ + "ALERT_MCIO2A_LEAK_DETECT_N","", + "ALERT_MCIO3A_LEAK_DETECT_N","", + "ALERT_MCIO4A_LEAK_DETECT_N","", + "ALERT_OC_PADDLE2_N","", + "ALERT_OC_PWR2_N","", + "ALERT_OC_PWR11_N","", + "ALERT_PADDLE2_SMB_N","", + "ALERT_PWR14_SB2_LEAK_DETECT_N","", + /*bit48-bit55*/ + "ALERT_PWR14_SB3_LEAK_DETECT_N","", + "ALERT_PWR15_SB2_LEAK_DETECT_N","", + "ALERT_PWR15_SB3_LEAK_DETECT_N","", + "ALERT_SMB_MCIO0A_N","", + "ALERT_SMB_MCIO1A_N","", + "ALERT_SMB_MCIO2A_N","", + "ALERT_SMB_MCIO2B_N","", + "ALERT_SMB_MCIO3A_N","", + /*bit56-bit63*/ + "ALERT_SMB_MCIO3B_N","", + "ALERT_SMB_MCIO4A_N","", + "ALERT_SMB_MCIO4B_N","", + "ALERT_THERMALTRIP_MCIO1A_N","", + "ALERT_THERMALTRIP_MCIO2A_N","", + "ALERT_THERMALTRIP_MCIO3A_N","", + "ALERT_THERMALTRIP_MCIO4A_N","", + "ALERT_UV_PADDLE2_N","", + /*bit64-bit71*/ + "ALERT_UV_PWR2_N","", + "ALERT_UV_PWR11_N","", + "ALERT_VR_SMB_N","", + "FAULT_FAN_0_N","", + "FAULT_FAN_1_N","", + "FAULT_FAN_2_N","", + "FAULT_FAN_3_N","", + "FAULT_P3V3_E1S_0_N","", + /*bit72-bit79*/ + "FAULT_P3V3_E1S_1_N","", + "FAULT_P3V3_NIC_N","", + "FAULT_P12V_NIC_N","", + "FAULT_P12V_SCM_N","", + "P0_I3C_APML_ALERT_L","", + "ALERT_INLET_TEMP_N","", + "FM_CPU_PROCHOT_R_N","", + "FM_CPU_THERMTRIP_N","", + /*bit80-bit87*/ + "ALERT_OUTLET_TEMP_N","", + "ALERT_RTC_N","", + "PVDDCR_CPU0_P0_OCP_N","", + "PVDDCR_CPU1_P0_OCP_N","", + "PVDDCR_SOC_P0_OCP_N","", + "MB_IOEXP_INT","", + "E1S_0_BD_IOEXP","", + "E1S_1_BD_IOEXP","", + /*bit88-bit95*/ + "PADDLE_BD_IOEXP_INT","", + "FM_BOARD_REV_ID0","", + "FM_BOARD_REV_ID1","", + "FM_BOARD_REV_ID2","", + "FM_VR_TYPE_ID0","", + "FM_VR_TYPE_ID1","", + "PRSNT_BOOT_N_IOEXP","", + "PRSNT_DATA_N_IOEXP","", + /*bit96-bit103*/ + "PRSNT_NIC_N_IOEXP","", + "PRSNT_BOOT_N_FF","", + "PRSNT_MCIO1A_N_FF","", + "NIC_PRSNT_N","", + "","", + "","", + "","", + "","", + /*bit104-bit111*/ + "","","","","","","","","","","","","","","","", + /*bit112-bit119*/ + "","","","","","","","","","","","","","","","", + /*bit120-bit127*/ + "","","","","","","","","","","","","","","",""; + status = "okay"; +}; + +/* BIOS Flash */ +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + status = "okay"; + + flash@0 { + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <12000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + status = "okay"; + }; +}; + +/* Host Console */ +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +/* SOL */ +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +/* BMC Console */ +&uart5 { + status = "okay"; +}; + +&wdt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-balcones.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-balcones.dts new file mode 100644 index 00000000000..63fcb7a7619 --- /dev/null +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-balcones.dts @@ -0,0 +1,609 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2025 IBM Corp. +/dts-v1/; + +#include +#include +#include +#include "aspeed-g6.dtsi" +#include "ibm-power11-dual.dtsi" + +/ { + model = "Balcones"; + compatible = "ibm,balcones-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + i2c16 = &i2c11mux0chn0; + i2c17 = &i2c11mux0chn1; + i2c18 = &i2c11mux0chn2; + i2c19 = &i2c11mux0chn3; + }; + + chosen { + stdout-path = &uart5; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + event-fan0-presence { + gpios = <&gpio0 ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; + label = "fan0-presence"; + linux,code = <6>; + }; + + event-fan1-presence { + gpios = <&gpio0 ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>; + label = "fan1-presence"; + linux,code = <7>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 7>; + }; + + leds { + compatible = "gpio-leds"; + + led-fan0 { + gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>; + }; + + led-fan1 { + gpios = <&gpio0 ASPEED_GPIO(G, 1) GPIO_ACTIVE_LOW>; + }; + + led-rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + led-rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + event_log: region@b3d00000 { + reg = <0xb3d00000 0x100000>; + no-map; + }; + + ramoops@b3e00000 { + compatible = "ramoops"; + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + reg = <0xb4000000 0x04000000>; /* 64M */ + no-map; + }; + + /* VGA region is dictated by hardware strapping */ + vga_memory: region@bf000000 { + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + no-map; + }; + }; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emmc { + clk-phase-mmc-hs200 = <180>, <180>; + status = "okay"; +}; + +&emmc_controller { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","checkstop","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","fan-ctlr-reset","rtc-battery-voltage-read-enable", + "reset-cause-pinhole","","","","", + /*G0-G7*/ "fan0","fan1","","","","","","", + /*H0-H7*/ "","","rear-enc-id0","rear-enc-fault0","","","","", + /*I0-I7*/ "","","","","","","bmc-secure-boot","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", + /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","", + "","","", + /*S0-S7*/ "presence-ps0","presence-ps1","","","power-ffs-sync-history","","", + "", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; + + usb-power-hog { + gpio-hog; + gpios = ; + output-high; + }; +}; + +&i2c0 { + status = "okay"; + + gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", + "RUSSEL_FW_I2C_ENABLE_N", + "RUSSEL_OPPANEL_PRESENCE_N", + "BLYTH_OPPANEL_PRESENCE_N", + "CPU_TPM_CARD_PRESENT_N", + "", + "", + "DASD_BP_PRESENT_N"; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + pmic@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c3 { + status = "okay"; + + power-supply@5a { + compatible = "acbel,fsg032"; + reg = <0x5a>; + }; + + power-supply@5b { + compatible = "acbel,fsg032"; + reg = <0x5b>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + led-controller@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + led@0 { + reg = <0>; + default-state = "keep"; + label = "cablecard2-cxp-top"; + retain-state-shutdown; + type = ; + }; + + led@1 { + reg = <1>; + default-state = "keep"; + label = "cablecard2-cxp-bot"; + retain-state-shutdown; + type = ; + }; + }; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + multi-master; + status = "okay"; + + temperature-sensor@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pwm@53 { + compatible = "maxim,max31785a"; + reg = <0x53>; + }; + + led-controller@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + led@0 { + reg = <0>; + default-state = "keep"; + label = "front-sys-id0"; + retain-state-shutdown; + type = ; + }; + + led@1 { + reg = <1>; + default-state = "keep"; + label = "front-check-log0"; + retain-state-shutdown; + type = ; + }; + + led@2 { + reg = <2>; + default-state = "keep"; + label = "front-enc-fault1"; + retain-state-shutdown; + type = ; + }; + + led@3 { + reg = <3>; + default-state = "keep"; + label = "front-sys-pwron0"; + retain-state-shutdown; + type = ; + }; + }; + + lcd-controller@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + pressure-sensor@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; +}; + +&i2c8 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + led-controller@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", + "APSS_RESET_N", + "", + "N_MODE_CPU_N", + "", + "", + "P10_DCM_PRESENT", + ""; + }; + + led-controller@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "", + "", + "SLOT2_PRSNT_EN_RSVD", + "", + "", + "", + "", + "SLOT2_EXPANDER_PRSNT_N", + "", + "", + "", + "", + "", + "", + "", + ""; + }; +}; + +&i2c9 { + status = "okay"; + + temperature-sensor@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "BOOT_RCVRY_TWI", + "BOOT_RCVRY_UART", + "", + "", + "", + "", + "", + "PE_SWITCH_RSTB_N"; + }; + + temperature-sensor@4c { + compatible = "ti,tmp435"; + reg = <0x4c>; + }; + + i2c-mux@75 { + compatible = "nxp,pca9849"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c11mux0chn0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0chn1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0chn2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0chn3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c12 { + status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + memory-region = <&event_log>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c13 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + led-controller@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + led@0 { + reg = <0>; + default-state = "keep"; + label = "nvme3"; + retain-state-shutdown; + type = ; + }; + + led@1 { + reg = <1>; + default-state = "keep"; + label = "nvme2"; + retain-state-shutdown; + type = ; + }; + + led@2 { + reg = <2>; + default-state = "keep"; + label = "nvme1"; + retain-state-shutdown; + type = ; + }; + + led@3 { + reg = <3>; + default-state = "keep"; + label = "nvme0"; + retain-state-shutdown; + type = ; + }; + }; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8 0xcac>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; +}; + +&lpc_ctrl { + memory-region = <&flash_memory>; + status = "okay"; +}; + +&mac2 { + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + use-ncsi; + status = "okay"; +}; + +&pinctrl_emmc_default { + bias-disable; +}; + +&uart2 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&vuart2 { + status = "okay"; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-bonnell.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-bonnell.dts index 2f5d4075a64..a37399ff3ce 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-bonnell.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-bonnell.dts @@ -277,15 +277,11 @@ #size-cells = <0>; fan0: fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; }; fan1: fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; }; }; diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts index 9f144f527f0..5a0975d5249 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts @@ -2066,27 +2066,19 @@ reg = <0x52>; fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; }; fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; }; fan@2 { - compatible = "pmbus-fan"; reg = <2>; - tach-pulses = <2>; }; fan@3 { - compatible = "pmbus-fan"; reg = <3>; - tach-pulses = <2>; }; }; diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts index c5fb5d41000..e90421bf7e3 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts @@ -1080,39 +1080,27 @@ #size-cells = <0>; fan0: fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; }; fan1: fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; }; fan2: fan@2 { - compatible = "pmbus-fan"; reg = <2>; - tach-pulses = <2>; }; fan3: fan@3 { - compatible = "pmbus-fan"; reg = <3>; - tach-pulses = <2>; }; fan4: fan@4 { - compatible = "pmbus-fan"; reg = <4>; - tach-pulses = <2>; }; fan5: fan@5 { - compatible = "pmbus-fan"; reg = <5>; - tach-pulses = <2>; }; }; diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts index b31eb8e58c6..6fe7023599e 100644 --- a/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts +++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts @@ -481,55 +481,19 @@ #size-cells = <0>; fan@0 { - compatible = "pmbus-fan"; reg = <0>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; fan@1 { - compatible = "pmbus-fan"; reg = <1>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; fan@2 { - compatible = "pmbus-fan"; reg = <2>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; fan@3 { - compatible = "pmbus-fan"; reg = <3>; - tach-pulses = <2>; - maxim,fan-rotor-input = "tach"; - maxim,fan-pwm-freq = <25000>; - maxim,fan-dual-tach; - maxim,fan-no-watchdog; - maxim,fan-no-fault-ramp; - maxim,fan-ramp = <2>; - maxim,fan-fault-pin-mon; }; }; diff --git a/dts/upstream/src/arm/aspeed/ibm-power11-dual.dtsi b/dts/upstream/src/arm/aspeed/ibm-power11-dual.dtsi new file mode 100644 index 00000000000..6db02d47538 --- /dev/null +++ b/dts/upstream/src/arm/aspeed/ibm-power11-dual.dtsi @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2025 IBM Corp. + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + + sbefifo100 = &sbefifo100; + sbefifo101 = &sbefifo101; + sbefifo110 = &sbefifo110; + sbefifo111 = &sbefifo111; + sbefifo112 = &sbefifo112; + sbefifo113 = &sbefifo113; + sbefifo114 = &sbefifo114; + sbefifo115 = &sbefifo115; + sbefifo202 = &sbefifo202; + sbefifo203 = &sbefifo203; + sbefifo210 = &sbefifo210; + sbefifo211 = &sbefifo211; + sbefifo214 = &sbefifo214; + sbefifo215 = &sbefifo215; + sbefifo216 = &sbefifo216; + sbefifo217 = &sbefifo217; + + scom100 = &scom100; + scom101 = &scom101; + scom110 = &scom110; + scom111 = &scom111; + scom112 = &scom112; + scom113 = &scom113; + scom114 = &scom114; + scom115 = &scom115; + scom202 = &scom202; + scom203 = &scom203; + scom210 = &scom210; + scom211 = &scom211; + scom214 = &scom214; + scom215 = &scom215; + scom216 = &scom216; + scom217 = &scom217; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + }; +}; + +&fsim0 { + bus-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <0>; + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + status = "okay"; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; /* OMI01 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom100: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo100: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; /* OMI23 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom101: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo101: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom110: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo110: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom111: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo111: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom112: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo112: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom113: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo113: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom114: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo114: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam0_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom115: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo115: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi1: spi@20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi2: spi@40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam0_spi3: spi@60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: fsi@3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,p9-scom"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,i2c-fsi"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; /* OMI45 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom202: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo202: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; /* OMI67 */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom203: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo203: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom210: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo210: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom211: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo211: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom214: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo214: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom215: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo215: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom216: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo216: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + + cfam1_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + #address-cells = <1>; + #size-cells = <0>; + + fsi@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom217: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo217: sbefifo@2400 { + compatible = "ibm,odyssey-sbefifo"; + reg = <0x2400 0x400>; + }; + }; + }; + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + compatible = "ibm,spi-fsi"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi1: spi@20 { + compatible = "ibm,spi-fsi"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi2: spi@40 { + compatible = "ibm,spi-fsi"; + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + + cfam1_spi3: spi@60 { + compatible = "ibm,spi-fsi"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "atmel,at25"; + reg = <0>; + address-width = <24>; + pagesize = <256>; + size = <0x80000>; + spi-max-frequency = <10000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + + occ { + compatible = "ibm,p10-occ"; + + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi@3400 { + compatible = "ibm,p9-fsi-controller"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + no-scan-on-init; + }; + }; +}; diff --git a/dts/upstream/src/arm/aspeed/ibm-power11-quad.dtsi b/dts/upstream/src/arm/aspeed/ibm-power11-quad.dtsi index 68c941a194b..7aa4113d302 100644 --- a/dts/upstream/src/arm/aspeed/ibm-power11-quad.dtsi +++ b/dts/upstream/src/arm/aspeed/ibm-power11-quad.dtsi @@ -1,24 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-or-later // Copyright 2024 IBM Corp. +#include "ibm-power11-dual.dtsi" + / { aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; i2c300 = &cfam2_i2c0; i2c301 = &cfam2_i2c1; i2c310 = &cfam2_i2c10; @@ -36,22 +22,6 @@ i2c416 = &cfam3_i2c16; i2c417 = &cfam3_i2c17; - sbefifo100 = &sbefifo100; - sbefifo101 = &sbefifo101; - sbefifo110 = &sbefifo110; - sbefifo111 = &sbefifo111; - sbefifo112 = &sbefifo112; - sbefifo113 = &sbefifo113; - sbefifo114 = &sbefifo114; - sbefifo115 = &sbefifo115; - sbefifo202 = &sbefifo202; - sbefifo203 = &sbefifo203; - sbefifo210 = &sbefifo210; - sbefifo211 = &sbefifo211; - sbefifo214 = &sbefifo214; - sbefifo215 = &sbefifo215; - sbefifo216 = &sbefifo216; - sbefifo217 = &sbefifo217; sbefifo300 = &sbefifo300; sbefifo301 = &sbefifo301; sbefifo310 = &sbefifo310; @@ -69,22 +39,6 @@ sbefifo416 = &sbefifo416; sbefifo417 = &sbefifo417; - scom100 = &scom100; - scom101 = &scom101; - scom110 = &scom110; - scom111 = &scom111; - scom112 = &scom112; - scom113 = &scom113; - scom114 = &scom114; - scom115 = &scom115; - scom202 = &scom202; - scom203 = &scom203; - scom210 = &scom210; - scom211 = &scom211; - scom214 = &scom214; - scom215 = &scom215; - scom216 = &scom216; - scom217 = &scom217; scom300 = &scom300; scom301 = &scom301; scom310 = &scom310; @@ -102,14 +56,6 @@ scom416 = &scom416; scom417 = &scom417; - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; spi30 = &cfam2_spi0; spi31 = &cfam2_spi1; spi32 = &cfam2_spi2; @@ -121,718 +67,7 @@ }; }; -&fsim0 { - #address-cells = <2>; - #size-cells = <0>; - status = "okay"; - bus-frequency = <100000000>; - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,p9-scom"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,i2c-fsi"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom100: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo100: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom101: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo101: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom110: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo110: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom111: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo111: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom112: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo112: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom113: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo113: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom114: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo114: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom115: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo115: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - compatible = "ibm,spi-fsi"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam0_spi1: spi@20 { - compatible = "ibm,spi-fsi"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam0_spi2: spi@40 { - compatible = "ibm,spi-fsi"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam0_spi3: spi@60 { - compatible = "ibm,spi-fsi"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - - occ { - compatible = "ibm,p10-occ"; - - hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub0: fsi@3400 { - compatible = "ibm,p9-fsi-controller"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; -}; - &fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,p9-scom"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,i2c-fsi"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom202: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo202: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom203: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo203: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom210: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo210: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom211: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo211: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom214: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo214: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom215: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo215: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom216: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo216: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - #address-cells = <1>; - #size-cells = <0>; - - fsi@20 { - compatible = "ibm,i2cr-fsi-master"; - reg = <0x20>; - #address-cells = <2>; - #size-cells = <0>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom217: scom@1000 { - compatible = "ibm,i2cr-scom"; - reg = <0x1000 0x400>; - }; - - sbefifo217: sbefifo@2400 { - compatible = "ibm,odyssey-sbefifo"; - reg = <0x2400 0x400>; - }; - }; - }; - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_spi0: spi@0 { - compatible = "ibm,spi-fsi"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam1_spi1: spi@20 { - compatible = "ibm,spi-fsi"; - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam1_spi2: spi@40 { - compatible = "ibm,spi-fsi"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - - cfam1_spi3: spi@60 { - compatible = "ibm,spi-fsi"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "atmel,at25"; - reg = <0>; - address-width = <24>; - pagesize = <256>; - size = <0x80000>; - spi-max-frequency = <10000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - - occ { - compatible = "ibm,p10-occ"; - - hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi@3400 { - compatible = "ibm,p9-fsi-controller"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - no-scan-on-init; - }; - }; - cfam@2,0 { reg = <2 0>; #address-cells = <1>; diff --git a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts index 413b9255f9e..19a8d7b0775 100644 --- a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts +++ b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts @@ -12,6 +12,17 @@ model = "Actiontec MI424WR rev A/C"; compatible = "actiontec,mi424wr-ac", "intel,ixp42x"; + /* Connect the switch to EthC */ + spi { + ethernet-switch@0 { + ethernet-ports { + ethernet-port@4 { + ethernet = <ðc>; + }; + }; + }; + }; + soc { /* EthB used for WAN */ ethernet@c8009000 { diff --git a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts index 3619c6411a5..244c6ea0973 100644 --- a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts +++ b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts @@ -12,6 +12,17 @@ model = "Actiontec MI424WR rev D"; compatible = "actiontec,mi424wr-d", "intel,ixp42x"; + /* Connect the switch to EthB */ + spi { + ethernet-switch@0 { + ethernet-ports { + ethernet-port@4 { + ethernet = <ðb>; + }; + }; + }; + }; + soc { /* EthB used for LAN */ ethernet@c8009000 { diff --git a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi index 76fd97c5beb..9b54e3c01a3 100644 --- a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi +++ b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi @@ -152,7 +152,6 @@ }; ethernet-port@4 { reg = <4>; - ethernet = <ðc>; phy-mode = "mii"; fixed-link { speed = <100>; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi index 41f865c8c09..c80201bce79 100644 --- a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -7,12 +7,14 @@ / { - model = "Enclustra Mercury AA1"; - compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; + model = "Enclustra Mercury+ AA1"; + compatible = "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; serial1 = &uart1; + spi0 = &qspi; }; memory@0 { @@ -24,52 +26,102 @@ chosen { stdout-path = "serial1:115200n8"; }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; +}; + +&i2c_encl { + status = "okay"; + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; }; &gmac0 { - phy-mode = "rgmii"; + status = "okay"; + phy-mode = "rgmii-id"; phy-addr = <0xffffffff>; /* probe for phy addr */ - max-frame-size = <3800>; - phy-handle = <&phy3>; + /delete-property/ mac-address; + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy3: ethernet-phy@3 { - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; /* 780ps */ rxd0-skew-ps = <420>; /* 0ps */ rxd1-skew-ps = <420>; /* 0ps */ rxd2-skew-ps = <420>; /* 0ps */ rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - reg = <3>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; /* 960ps */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + txen-skew-ps = <0>; /* -420ps */ }; }; }; -&i2c1 { - atsha204a: crypto@64 { - compatible = "atmel,atsha204a"; - reg = <0x64>; - }; +&gpio0 { + status = "okay"; +}; - isl12022: isl12022@6f { - compatible = "isil,isl12022"; - reg = <0x6f>; - }; +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; }; /* Following mappings are taken from arria10 socdk dts */ &mmc { + status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; @@ -79,3 +131,50 @@ &osc1 { clock-frequency = <33330000>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + status = "okay"; + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&watchdog1 { + status = "disabled"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts new file mode 100644 index 00000000000..b6cca0b5fd0 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts new file mode 100644 index 00000000000..6ad023477cd --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts new file mode 100644 index 00000000000..653c9a86516 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts new file mode 100644 index 00000000000..ae9c7c6a237 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts new file mode 100644 index 00000000000..c3a0c30a07a --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts new file mode 100644 index 00000000000..dc1e1ad2038 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts new file mode 100644 index 00000000000..61d5e4c85d9 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts new file mode 100644 index 00000000000..a3b99c9b16f --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts new file mode 100644 index 00000000000..5deb289e2b5 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_pe1.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a9f..00000000000 --- a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar - */ -/dts-v1/; -#include "socfpga_arria10_mercury_aa1.dtsi" - -/ { - model = "Enclustra Mercury+ PE1"; - compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1", - "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial0 = &uart0; - serial1 = &uart1; - }; -}; - -&gmac0 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&mmc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi new file mode 100644 index 00000000000..49944f9632f --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Enclustra Mercury SA1"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&osc1 { + clock-frequency = <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + status = "okay"; + + isl12020: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&mmc0 { + status = "okay"; + /delete-property/ cap-mmc-highspeed; + /delete-property/ cap-sd-highspeed; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii-id"; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts new file mode 100644 index 00000000000..85d6146da0d --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts new file mode 100644 index 00000000000..770ab680a18 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts new file mode 100644 index 00000000000..990ca0fec61 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts new file mode 100644 index 00000000000..6c8fd5b0d6e --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts new file mode 100644 index 00000000000..3292426078a --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts new file mode 100644 index 00000000000..1eb10b5244d --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts new file mode 100644 index 00000000000..8c97b5b3ade --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts new file mode 100644 index 00000000000..e6d14b22e41 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts new file mode 100644 index 00000000000..beaeca94d4d --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 00000000000..0b28964e037 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Enclustra Mercury+ SA2"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency = <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + status = "okay"; + + isl12020: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; + + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&mmc0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii-id"; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts new file mode 100644 index 00000000000..6f79d9ed1d3 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts new file mode 100644 index 00000000000..b94bd8bafc2 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts new file mode 100644 index 00000000000..51fc4a22937 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts new file mode 100644 index 00000000000..e4209209f4f --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts new file mode 100644 index 00000000000..ab4549a0d45 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts new file mode 100644 index 00000000000..ebe62879c3f --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi new file mode 100644 index 00000000000..d79cb64da0d --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status = "disabled"; +}; + +&mmc { + bus-width = <8>; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi new file mode 100644 index 00000000000..5ba21dd8f5b --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&mmc { + status = "disabled"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi new file mode 100644 index 00000000000..2b102e0b621 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status = "disabled"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 00000000000..abc4bfb7fcc --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status = "okay"; + + eeprom@57 { + status = "okay"; + compatible = "microchip,24c128"; + reg = <0x57>; + pagesize = <64>; + label = "user eeprom"; + address-width = <16>; + }; + + lm96080: temperature-sensor@2f { + status = "okay"; + compatible = "national,lm80"; + reg = <0x2f>; + }; + + si5338: clock-controller@70 { + compatible = "silabs,si5338"; + reg = <0x70>; + }; + +}; + +&i2c_encl_fpga { + status = "okay"; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 00000000000..bc57b068087 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status = "okay"; + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@56 { + status = "okay"; + compatible = "microchip,24c128"; + reg = <0x56>; + pagesize = <64>; + label = "user eeprom"; + address-width = <16>; + }; + + lm96080: temperature-sensor@2f { + status = "okay"; + compatible = "national,lm80"; + reg = <0x2f>; + }; + + pcal6416: gpio@20 { + status = "okay"; + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status = "okay"; + + i2c-mux@75 { + status = "okay"; + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + }; +}; diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 00000000000..4c00475f430 --- /dev/null +++ b/dts/upstream/src/arm/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338: clock-controller@70 { + compatible = "silabs,si5338"; + reg = <0x70>; + }; +}; + +&i2c_encl_fpga { + status = "okay"; +}; diff --git a/dts/upstream/src/arm/marvell/armada-38x.dtsi b/dts/upstream/src/arm/marvell/armada-38x.dtsi index 1181b13deab..1d616edda32 100644 --- a/dts/upstream/src/arm/marvell/armada-38x.dtsi +++ b/dts/upstream/src/arm/marvell/armada-38x.dtsi @@ -247,7 +247,7 @@ marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp41"; marvell,function = "nand"; }; diff --git a/dts/upstream/src/arm/marvell/armada-xp-98dx3236.dtsi b/dts/upstream/src/arm/marvell/armada-xp-98dx3236.dtsi index 7a7e2066c49..a9a71326aaf 100644 --- a/dts/upstream/src/arm/marvell/armada-xp-98dx3236.dtsi +++ b/dts/upstream/src/arm/marvell/armada-xp-98dx3236.dtsi @@ -322,7 +322,7 @@ marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp19"; marvell,function = "nand"; }; diff --git a/dts/upstream/src/arm/mediatek/mt2701.dtsi b/dts/upstream/src/arm/mediatek/mt2701.dtsi index ce6a4015fed..128b87229f3 100644 --- a/dts/upstream/src/arm/mediatek/mt2701.dtsi +++ b/dts/upstream/src/arm/mediatek/mt2701.dtsi @@ -597,7 +597,7 @@ }; hifsys: syscon@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; + compatible = "mediatek,mt2701-hifsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/dts/upstream/src/arm/mediatek/mt6582-alcatel-yarisxl.dts b/dts/upstream/src/arm/mediatek/mt6582-alcatel-yarisxl.dts new file mode 100644 index 00000000000..f55d8edad1a --- /dev/null +++ b/dts/upstream/src/arm/mediatek/mt6582-alcatel-yarisxl.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Cristian Cozzolino + */ + +/dts-v1/; +#include "mt6582.dtsi" + +/ { + model = "Alcatel One Touch Pop C7 (OT-7041D)"; + compatible = "alcatel,yarisxl", "mediatek,mt6582"; + + aliases { + serial0 = &uart0; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + stdout-path = "serial0:921600n8"; + + framebuffer: framebuffer@9fa00000 { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_reserved>; + width = <480>; + height = <854>; + stride = <(480 * 4)>; + format = "r5g6b5"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + connsys@9f900000 { + reg = <0x9f900000 0x100000>; + no-map; + }; + + modem@9e000000 { + reg = <0x9e000000 0x1800000>; + no-map; + }; + + framebuffer_reserved: framebuffer@9fa00000 { + reg = <0x9fa00000 0x600000>; + no-map; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm/mediatek/mt6582.dtsi b/dts/upstream/src/arm/mediatek/mt6582.dtsi index 4263371784c..f941ea44898 100644 --- a/dts/upstream/src/arm/mediatek/mt6582.dtsi +++ b/dts/upstream/src/arm/mediatek/mt6582.dtsi @@ -9,12 +9,12 @@ / { #address-cells = <1>; #size-cells = <1>; - compatible = "mediatek,mt6582"; interrupt-parent = <&sysirq>; cpus { - #address-cells = <1>; #size-cells = <0>; + #address-cells = <1>; + enable-method = "mediatek,mt6589-smp"; cpu@0 { device_type = "cpu"; @@ -38,91 +38,95 @@ }; }; + uart_clk: dummy26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + system_clk: dummy13m { compatible = "fixed-clock"; - clock-frequency = <13000000>; #clock-cells = <0>; + clock-frequency = <13000000>; }; rtc_clk: dummy32k { compatible = "fixed-clock"; + #clock-cells = <0>; clock-frequency = <32000>; - #clock-cells = <0>; }; - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; - timer: timer@11008000 { - compatible = "mediatek,mt6577-timer"; - reg = <0x10008000 0x80>; - interrupts = ; - clocks = <&system_clk>, <&rtc_clk>; - clock-names = "system-clk", "rtc-clk"; - }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6582-wdt", "mediatek,mt6589-wdt"; + reg = <0x10007000 0x100>; + }; - sysirq: interrupt-controller@10200100 { - compatible = "mediatek,mt6582-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10200100 0x1c>; - }; + timer: timer@10008000 { + compatible = "mediatek,mt6582-timer", "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + }; - gic: interrupt-controller@10211000 { - compatible = "arm,cortex-a7-gic"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, - <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq"; + reg = <0x10200100 0x1c>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + }; - uart0: serial@11002000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11002000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; - uart1: serial@11003000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11003000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart0: serial@11002000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; - uart2: serial@11004000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11004000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart1: serial@11003000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; - uart3: serial@11005000 { - compatible = "mediatek,mt6582-uart", - "mediatek,mt6577-uart"; - reg = <0x11005000 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; + uart2: serial@11004000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; - watchdog: watchdog@10007000 { - compatible = "mediatek,mt6582-wdt", - "mediatek,mt6589-wdt"; - reg = <0x10007000 0x100>; + uart3: serial@11005000 { + compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + clock-names = "baud"; + status = "disabled"; + }; }; }; diff --git a/dts/upstream/src/arm/mediatek/mt7623.dtsi b/dts/upstream/src/arm/mediatek/mt7623.dtsi index fd7a89cc337..4b1685b9398 100644 --- a/dts/upstream/src/arm/mediatek/mt7623.dtsi +++ b/dts/upstream/src/arm/mediatek/mt7623.dtsi @@ -744,8 +744,7 @@ hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", - "mediatek,mt2701-hifsys", - "syscon"; + "mediatek,mt2701-hifsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/dts/upstream/src/arm/microchip/lan966x-pcb8290.dts b/dts/upstream/src/arm/microchip/lan966x-pcb8290.dts index 3b7577e48b4..50bd29572f3 100644 --- a/dts/upstream/src/arm/microchip/lan966x-pcb8290.dts +++ b/dts/upstream/src/arm/microchip/lan966x-pcb8290.dts @@ -54,6 +54,7 @@ &mdio0 { pinctrl-0 = <&miim_a_pins>; pinctrl-names = "default"; + reset-gpios = <&gpio 53 GPIO_ACTIVE_LOW>; status = "okay"; ext_phy0: ethernet-phy@7 { diff --git a/dts/upstream/src/arm/microchip/sama5d2.dtsi b/dts/upstream/src/arm/microchip/sama5d2.dtsi index 17430d7f205..fde890f18d2 100644 --- a/dts/upstream/src/arm/microchip/sama5d2.dtsi +++ b/dts/upstream/src/arm/microchip/sama5d2.dtsi @@ -571,7 +571,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -642,7 +642,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -854,7 +854,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -925,7 +925,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -997,7 +997,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>; dma-names = "tx", "rx"; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; diff --git a/dts/upstream/src/arm/microchip/sama7d65.dtsi b/dts/upstream/src/arm/microchip/sama7d65.dtsi index e53e2dd6d53..868045c650a 100644 --- a/dts/upstream/src/arm/microchip/sama7d65.dtsi +++ b/dts/upstream/src/arm/microchip/sama7d65.dtsi @@ -527,7 +527,7 @@ interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, <&dma0 AT91_XDMAC_DT_PERID(11)>; dma-names = "tx", "rx"; @@ -557,7 +557,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; atmel,usart-mode = ; status = "disabled"; }; @@ -618,7 +618,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "usart"; atmel,usart-mode = ; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; }; @@ -643,7 +643,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; atmel,usart-mode = ; status = "disabled"; }; @@ -676,7 +676,7 @@ flx9: flexcom@e2820000 { compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2820000 0x200>; - ranges = <0x0 0xe281c000 0x800>; + ranges = <0x0 0xe2820000 0x800>; clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/upstream/src/arm/microchip/sama7g5.dtsi b/dts/upstream/src/arm/microchip/sama7g5.dtsi index 381cbcfcb34..03ef3d9aaee 100644 --- a/dts/upstream/src/arm/microchip/sama7g5.dtsi +++ b/dts/upstream/src/arm/microchip/sama7g5.dtsi @@ -824,7 +824,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; }; @@ -850,7 +850,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; - atmel,fifo-size = <16>; + atmel,fifo-size = <32>; status = "disabled"; }; }; diff --git a/dts/upstream/src/arm/nvidia/tegra114.dtsi b/dts/upstream/src/arm/nvidia/tegra114.dtsi index a2a50f95992..a98667641be 100644 --- a/dts/upstream/src/arm/nvidia/tegra114.dtsi +++ b/dts/upstream/src/arm/nvidia/tegra114.dtsi @@ -48,6 +48,45 @@ ranges = <0x54000000 0x54000000 0x01000000>; + vi@54080000 { + compatible = "nvidia,tegra114-vi"; + reg = <0x54080000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + + iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; + }; + + epp@540c0000 { + compatible = "nvidia,tegra114-epp"; + reg = <0x540c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_EPP>; + resets = <&tegra_car TEGRA114_CLK_EPP>; + reset-names = "epp"; + + iommus = <&mc TEGRA_SWGROUP_EPP>; + + status = "disabled"; + }; + + isp@54100000 { + compatible = "nvidia,tegra114-isp"; + reg = <0x54100000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_ISP>; + resets = <&tegra_car TEGRA114_CLK_ISP>; + reset-names = "isp"; + + iommus = <&mc TEGRA_SWGROUP_ISP>; + + status = "disabled"; + }; + gr2d@54140000 { compatible = "nvidia,tegra114-gr2d"; reg = <0x54140000 0x00040000>; @@ -150,6 +189,31 @@ #address-cells = <1>; #size-cells = <0>; }; + + msenc@544c0000 { + compatible = "nvidia,tegra114-msenc"; + reg = <0x544c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_MSENC>; + resets = <&tegra_car TEGRA114_CLK_MSENC>; + reset-names = "mpe"; + + iommus = <&mc TEGRA_SWGROUP_MSENC>; + + status = "disabled"; + }; + + tsec@54500000 { + compatible = "nvidia,tegra114-tsec"; + reg = <0x54500000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_TSEC>; + resets = <&tegra_car TEGRA114_CLK_TSEC>; + + iommus = <&mc TEGRA_SWGROUP_TSEC>; + + status = "disabled"; + }; }; gic: interrupt-controller@50041000 { diff --git a/dts/upstream/src/arm/nvidia/tegra124-xiaomi-mocha.dts b/dts/upstream/src/arm/nvidia/tegra124-xiaomi-mocha.dts new file mode 100644 index 00000000000..18c9cdf45ec --- /dev/null +++ b/dts/upstream/src/arm/nvidia/tegra124-xiaomi-mocha.dts @@ -0,0 +1,2790 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "tegra124.dtsi" + +/ { + model = "Xiaomi Mi Pad A0101"; + compatible = "xiaomi,mocha", "nvidia,tegra124"; + chassis-type = "tablet"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &palmas; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0 0x80000000 0 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + nvidia,ganged-mode = <&dsib>; + + panel@0 { + compatible = "sharp,lq079l1sx01"; + reg = <0>; + + reset-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_LOW>; + + avdd-supply = <&avdd_lcd>; + vddio-supply = <&vdd_lcd_io>; + + vsp-supply = <&vsp_5v5_lcd>; + vsn-supply = <&vsn_5v5_lcd>; + + backlight = <&lp8556>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_link0: endpoint { + remote-endpoint = <&dsia_out>; + }; + }; + + port@1 { + reg = <1>; + + panel_link1: endpoint { + remote-endpoint = <&dsib_out>; + }; + }; + }; + }; + + port { + dsia_out: endpoint { + remote-endpoint = <&panel_link0>; + }; + }; + }; + + dsib: dsi@54400000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + port { + dsib_out: endpoint { + remote-endpoint = <&panel_link1>; + }; + }; + }; + }; + + gpu@57000000 { + vdd-supply = <&vdd_gpu>; + }; + + clock@60006000 { + emc-timings-0 { + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + + timing-924000000 { + clock-frequency = <924000000>; + nvidia,parent-clock-frequency = <924000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Keys pinmux */ + keys { + nvidia,pins = "kb_col0_pq0", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hall-front { + nvidia,pins = "pi5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hall-back { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Leds pinmux */ + bl-en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + keys-led { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + rgb-led-en { + nvidia,pins = "pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Panel pinmux */ + lcd-rst { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd-vsp-en { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd-vsn-en { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd-id { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd-pwm { + nvidia,pins = "ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC1 pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3-cd { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + usd-pwr { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-B pinmux */ + uartb-cts { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartb-rts { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D pinmux */ + uartd-txd { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uartd-rxd { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + ts-irq { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ts-rst { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ts-en { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hapt-en { + nvidia,pins = "pg6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + charger-irq { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bat-irq { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + compass-rst { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + als-irq { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + therm-irq { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + wlan-reg-on { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + wlan-host-wake { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt-reg-on { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + bt-dev-wake { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + imu-irq { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + imu-sync { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cdc-mclk1 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cdc-din { + nvidia,pins = "dap1_din_pn1", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cdc-dout { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spkr-rl-rst { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spkr-rl-irq { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dvfs-pwm { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dvfs-clk { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam-mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam-mclk2 { + nvidia,pins = "pbb0"; + nvidia,function = "vimclk2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vbrtr-pwm { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + soc-pins { + nvidia,pins = "pj2", "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd-id-det0 { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cdc-rst { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cdc-det-irq { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hph-pa-sd { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hph-en { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam-rear-rst-n { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam-af-pwdn { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam-front-pwdn { + nvidia,pins = "pbb6"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam-front-rst-n { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gps-en { + nvidia,pins = "ph5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + boot-select { + nvidia,pins = "pg0", "pg1", "pg2", "pg3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ram-select { + nvidia,pins = "pg4", "pg5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + line-in-det { + nvidia,pins = "pk2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gpadc-sync { + nvidia,pins = "pi0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gpu-pwr-req { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ear-uart-sw { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dsi-b { + nvidia,pins = "mipi_pad_ctrl_dsi_b"; + nvidia,function = "dsi_b"; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <32>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <1>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + bluetooth { + compatible = "brcm,bcm43540-bt"; + max-speed = <4000000>; + + clocks = <&clk32k_pmic>; + clock-names = "lpo"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + uartd: serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + /* Console */ + }; + + pwm@7000a000 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + lp8556: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x83>; + init-brt = /bits/ 8 <0x1f>; + + power-supply = <&vdd_3v3_sys>; + enable-supply = <&vddio_1v8_bl>; + + rom-98h { + rom-addr = /bits/ 8 <0x98>; + rom-val = /bits/ 8 <0x80>; + }; + + rom-9eh { + rom-addr = /bits/ 8 <0x9e>; + rom-val = /bits/ 8 <0x21>; + }; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0xff>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x3f>; + }; + + rom-a2h { + rom-addr = /bits/ 8 <0xa2>; + rom-val = /bits/ 8 <0x20>; + }; + + rom-a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x00>; + }; + + rom-a4h { + rom-addr = /bits/ 8 <0xa4>; + rom-val = /bits/ 8 <0x72>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + + rom-a6h { + rom-addr = /bits/ 8 <0xa6>; + rom-val = /bits/ 8 <0x80>; + }; + + rom-a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xf5>; + }; + + rom-a8h { + rom-addr = /bits/ 8 <0xa8>; + rom-val = /bits/ 8 <0x24>; + }; + + rom-a9h { + rom-addr = /bits/ 8 <0xa9>; + rom-val = /bits/ 8 <0xb2>; + }; + + rom-aah { + rom-addr = /bits/ 8 <0xaa>; + rom-val = /bits/ 8 <0x8f>; + }; + + rom-aeh { + rom-addr = /bits/ 8 <0xae>; + rom-val = /bits/ 8 <0x0f>; + }; + }; + + led-controller@32 { + compatible = "national,lp5521"; + reg = <0x32>; + + enable-gpios = <&gpio TEGRA_GPIO(G, 7) GPIO_ACTIVE_HIGH>; + clock-mode = /bits/ 8 <2>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + + led-cur = /bits/ 8 <0x14>; + max-cur = /bits/ 8 <0xff>; + + color = ; + function = LED_FUNCTION_STATUS; + }; + + led@1 { + reg = <1>; + + led-cur = /bits/ 8 <0x14>; + max-cur = /bits/ 8 <0xff>; + + color = ; + function = LED_FUNCTION_STATUS; + }; + + led@2 { + reg = <2>; + + led-cur = /bits/ 8 <0x14>; + max-cur = /bits/ 8 <0xff>; + + color = ; + function = LED_FUNCTION_STATUS; + }; + }; + + audio-codec@34 { + compatible = "nxp,tfa9890"; + reg = <0x34>; + + sound-name-prefix = "Speaker Right"; + vddd-supply = <&vdd_1v8_vio>; + + #sound-dai-cells = <0>; + }; + + audio-codec@37 { + compatible = "nxp,tfa9890"; + reg = <0x37>; + + sound-name-prefix = "Speaker Left"; + vddd-supply = <&vdd_1v8_vio>; + + #sound-dai-cells = <0>; + }; + + light-sensor@44 { + compatible = "isil,isl29035"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + }; + + temp_sensor: temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_1v8_vio>; + #thermal-sensor-cells = <1>; + }; + + haptic-engine@5a { + compatible = "ti,drv2604"; + reg = <0x5a>; + + enable-gpios = <&gpio TEGRA_GPIO(G, 6) GPIO_ACTIVE_HIGH>; + + mode = ; + library-sel = ; + + vib-rated-mv = <3200>; + vib-overdrive-mv = <3400>; + + vbat-supply = <&vdd_3v3_sys>; + }; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + + vs-supply = <&vdd_hv_sdmmc>; + #io-channel-cells = <1>; + }; + + fuel-gauge@55 { + compatible = "ti,bq27520g4"; + reg = <0x55>; + + interrupt-parent = <&gpio>; + interrupts = ; + + monitored-battery = <&battery>; + power-supplies = <&bq24192>; + }; + + bq24192: charger@6b { + compatible = "ti,bq24192"; + reg = <0x6b>; + + interrupt-parent = <&gpio>; + interrupts = ; + + ce-gpios = <&palmas_gpio 7 GPIO_ACTIVE_LOW>; + + monitored-battery = <&battery>; + + omit-battery-class; + ti,system-minimum-microvolt = <3500000>; + + usb_otg_vbus: usb-otg-vbus { + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <400000>; + + /* Atmel mxT1664T/mxT1066T touchscreen */ + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>; + + linux,keycodes = ; + + vdda-supply = <&avdd_3v3_ts>; + vdd-supply = <&vdd_2v8_tp>; + }; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + palmas: pmic@58 { + compatible = "ti,tps65913", "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + adc { + compatible = "ti,palmas-gpadc"; + interrupts = <18 IRQ_TYPE_NONE>, + <16 IRQ_TYPE_NONE>, + <17 IRQ_TYPE_NONE>; + + ti,channel0-current-microamp = <20>; + #io-channel-cells = <1>; + }; + + palmas_extcon: extcon { + compatible = "ti,palmas-usb-vid"; + + ti,enable-vbus-detection; + ti,enable-id-detection; + + ti,wakeup; + }; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + clk32k_pmic: palmas-clk32k@0 { + compatible = "ti,palmas-clk32kg"; + #clock-cells = <0>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio0 { + pins = "gpio0"; + function = "id"; + bias-pull-up; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + /* GPIO3 is not used */ + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "clk32kgaudio"; + }; + + /* GPIO6 is not used */ + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldo1-in-supply = <&vdd_1v8_vio>; + ldo2-in-supply = <&vdd_3v3_sys>; + ldo3-in-supply = <&vdd_smps10_out2>; + ldo4-in-supply = <&vdd_3v3_sys>; + ldo5-in-supply = <&vdd_1v8_vio>; + ldo6-in-supply = <&vdd_3v3_sys>; + ldo7-in-supply = <&vdd_3v3_sys>; + ldo8-in-supply = <&vdd_3v3_sys>; + ldo9-in-supply = <&vdd_hv_sdmmc>; + ldousb-in-supply = <&vdd_smps10_out2>; + ldoln-in-supply = <&vdd_smps10_out2>; + + regulators { + vdd_cpu: smps123 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <1>; + ti,mode-sleep = <3>; + }; + + vdd_gpu: smps45 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + }; + + vddio_ddr: smps6 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_core: smps7 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_hv_sdmmc: smps9 { + regulator-name = "vdd_hv_sdmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out1 { + regulator-name = "vd_smps10_out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out2: smps10_out2 { + regulator-name = "vd_smps10_out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_pll: ldo1 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + ti,roof-floor = <3>; + }; + + avdd_lcd: ldo2 { + regulator-name = "avdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + avdd_3v3_ts: ldo3 { + regulator-name = "avdd_3v3_ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + avdd_2v7_cam: ldo4 { + regulator-name = "avdd_2v7_cam"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + avdd_dsi_csi: ldo5 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ldo6 { + regulator-name = "vdd_1v8_fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + avdd_2v7_vcm: ldo7 { + regulator-name = "avdd_2v7_vcm"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo8 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + ti,enable-ldo8-tracking; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln { + regulator-name = "vddio_hv"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 IRQ_TYPE_NONE>; + }; + }; + }; + + pmc@7000e400 { + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <2000>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + /* Clear DEV_ON bit in DEV_CTRL register of TPS65913 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x58>; + nvidia,reg-addr = <0xa0>; + nvidia,reg-data = <0x00>; + }; + }; + + memory-controller@70019000 { + emc-timings-0 { + /* Hynix H9CKNNNBKTMTDR DDR3 924MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x40040001 0x8000000a + 0x00000001 0x00000002 0x00000004 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000b0604 0x77230305 0x70000f03 + 0x001f0000 >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < 0x40020001 0x80000012 + 0x00000001 0x00000002 0x00000004 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000b0604 0x75a30305 0x70000f03 + 0x001f0000 >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < 0xa0000001 0x80000017 + 0x00000001 0x00000002 0x00000004 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000b0604 0x74030305 0x70000f03 + 0x001f0000 >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < 0x00000001 0x8000001e + 0x00000001 0x00000002 0x00000003 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000a0503 0x73830404 0x70000f03 + 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x08000001 0x80000026 + 0x00000001 0x00000002 0x00000004 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x05040102 0x000a0504 0x73430505 0x70000f03 + 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x01000003 0x80000040 + 0x00000001 0x00000002 0x00000007 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000007 + 0x00000003 0x00000001 0x00000005 0x00000005 + 0x05050103 0x000b0607 0x72e40a08 0x70000f03 + 0x001f0000 >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < 0x08000004 0x80000040 + 0x00000001 0x00000002 0x00000009 0x00000005 + 0x00000007 0x00000001 0x00000002 0x00000007 + 0x00000003 0x00000001 0x00000005 0x00000005 + 0x05050103 0x000c0709 0x72c50e0a 0x70000f03 + 0x001f0000 >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < 0x0f000005 0x80000040 + 0x00000002 0x00000003 0x0000000c 0x00000007 + 0x00000009 0x00000001 0x00000002 0x00000007 + 0x00000003 0x00000001 0x00000005 0x00000005 + 0x05050103 0x000e090c 0x72c6120d 0x70000f03 + 0x001f0000 >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < 0x0f000007 0x80000040 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000009 + 0x00000003 0x00000001 0x00000006 0x00000006 + 0x06060103 0x00120b10 0x72c81811 0x70000f03 + 0x001f0000 >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < 0x00000009 0x80000040 + 0x00000004 0x00000005 0x00000012 0x0000000b + 0x0000000e 0x00000002 0x00000003 0x0000000a + 0x00000003 0x00000001 0x00000006 0x00000007 + 0x07060103 0x00140d12 0x72c91b13 0x70000f03 + 0x001f0000 >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < 0x0e00000b 0x80000040 + 0x00000006 0x00000007 0x00000018 0x0000000f + 0x00000013 0x00000003 0x00000003 0x0000000c + 0x00000003 0x00000001 0x00000008 0x00000008 + 0x08080103 0x001a1118 0x72ac2419 0x70000f02 + 0x001f0000 >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emem-configuration = < 0x0e00000d 0x80000040 + 0x00000007 0x00000008 0x0000001b 0x00000012 + 0x00000017 0x00000004 0x00000004 0x0000000e + 0x00000004 0x00000001 0x00000009 0x00000009 + 0x09090104 0x001e141b 0x72ae2a1c 0x70000f02 + 0x001f0000 >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-0 { + /* Hynix H9CKNNNBKTMTDR DDR3 924MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x000d0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000000 0x00000002 0x00000000 0x00000002 + 0x00000005 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x00000030 + 0x00000000 0x0000000c 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000003 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000006 0x00000003 + 0x00000003 0x00000056 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000011 0x000d0011 0x00000000 0x00000003 + 0x0000f3f3 0x80000164 0x0000000a >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00150011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000001 0x00000004 0x00000000 0x00000002 + 0x00000005 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x0000004d + 0x00000000 0x00000013 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000005 0x00000005 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000006 0x00000003 + 0x00000003 0x0000008a 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000011 0x00150011 0x00000000 0x00000003 + 0x0000f3f3 0x8000019f 0x0000000a >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00290011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000002 0x00000008 0x00000000 0x00000002 + 0x00000005 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x0000009a + 0x00000000 0x00000026 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000009 0x00000009 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000007 0x00000003 + 0x00000003 0x00000113 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000011 0x00290011 0x00000000 0x00000003 + 0x0000f3f3 0x8000023a 0x0000000a >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00440011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000004 0x00000010 0x00000000 0x00000002 + 0x00000004 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x00000101 + 0x00000000 0x00000040 0x00000002 0x00000002 + 0x00000004 0x00000000 0x00000001 0x0000000c + 0x0000000f 0x0000000f 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000005 0x00000003 + 0x00000003 0x000001c9 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000019 0x00440011 0x00000000 0x00000003 + 0x0000f3f3 0x80000309 0x0000000a >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008c7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00660011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000015>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000006 0x00000015 0x00000000 0x00000004 + 0x00000004 0x00000006 0x00000008 0x00000003 + 0x0000000a 0x00000002 0x00000002 0x00000001 + 0x00000002 0x00000000 0x00000003 0x00000003 + 0x00000006 0x00000002 0x00000000 0x00000005 + 0x00000005 0x00010000 0x00000003 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x0000000c 0x0000000d 0x0000000f 0x00000182 + 0x00000000 0x00000060 0x00000002 0x00000002 + 0x00000004 0x00000000 0x00000001 0x0000000c + 0x00000017 0x00000017 0x00000003 0x00000003 + 0x00000003 0x00000006 0x00000005 0x00000003 + 0x00000003 0x000002ae 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00090000 0x00090000 0x00090000 0x00090000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x000fc000 0x000fc000 0x00000000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 + 0x0000fc00 0x0000fc00 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x00000025 0x00660011 0x00000000 0x00000003 + 0x0000f3f3 0x8000040b 0x0000000a >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0xd3200000>; + nvidia,emc-cfg-2 = <0x000008cf>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x00cc0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; + nvidia,emc-zcal-cnt-long = <0x00000017>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x0000000c 0x0000002a 0x00000000 0x00000008 + 0x00000005 0x00000007 0x00000008 0x00000003 + 0x0000000a 0x00000003 0x00000003 0x00000002 + 0x00000003 0x00000000 0x00000002 0x00000002 + 0x00000005 0x00000003 0x00000000 0x00000003 + 0x00000007 0x00010000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x0000000e 0x0000000f 0x00000011 0x00000304 + 0x00000000 0x000000c1 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x0000002d 0x0000002d 0x00000003 0x00000004 + 0x00000003 0x00000009 0x00000006 0x00000003 + 0x00000003 0x0000055b 0x00000000 0x00000000 + 0x00000000 0x1363a296 0x005800a0 0x00008000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00098000 0x00098000 0x00000000 0x00098000 + 0x00098000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x0008c000 0x00088000 + 0x00088000 0x00088000 0x00008800 0x00008800 + 0x00008800 0x00008800 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451400 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000004a 0x00cc0011 0x00000000 0x00000004 + 0x0000d3b3 0x80000713 0x0000000a >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x000008d7>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x012c0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004013c>; + nvidia,emc-xm2dqspadctrl2 = <0x01231239>; + nvidia,emc-zcal-cnt-long = <0x0000001f>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000011 0x0000003e 0x00000000 0x0000000c + 0x00000005 0x00000007 0x00000008 0x00000003 + 0x0000000a 0x00000005 0x00000005 0x00000002 + 0x00000003 0x00000000 0x00000002 0x00000002 + 0x00000006 0x00000003 0x00000000 0x00000003 + 0x00000008 0x00030000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x0000000f 0x00000012 0x00000014 0x0000046e + 0x00000000 0x0000011b 0x00000002 0x00000002 + 0x00000005 0x00000000 0x00000001 0x0000000c + 0x00000042 0x00000042 0x00000003 0x00000005 + 0x00000003 0x0000000d 0x00000007 0x00000003 + 0x00000003 0x000007e0 0x00000000 0x00000000 + 0x00000000 0x1363a096 0x005800a0 0x00008000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00060000 0x00060000 0x00000000 0x00060000 + 0x00060000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00048000 0x00048000 + 0x00048000 0x00048000 0x00004800 0x00004800 + 0x00004800 0x00004800 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000006c 0x012c0011 0x00000000 0x00000004 + 0x000052a3 0x800009ed 0x0000000b >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x00000897>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x80020004>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x018c0011>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x01231239>; + nvidia,emc-zcal-cnt-long = <0x00000028>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000017 0x00000053 0x00000000 0x00000010 + 0x00000007 0x00000008 0x00000008 0x00000003 + 0x0000000a 0x00000007 0x00000007 0x00000003 + 0x00000003 0x00000000 0x00000002 0x00000002 + 0x00000006 0x00000003 0x00000000 0x00000002 + 0x00000009 0x00030000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000001 + 0x00000010 0x00000012 0x00000014 0x000005d9 + 0x00000000 0x00000176 0x00000002 0x00000002 + 0x00000007 0x00000000 0x00000001 0x0000000e + 0x00000058 0x00000058 0x00000003 0x00000006 + 0x00000003 0x00000012 0x00000009 0x00000003 + 0x00000003 0x00000a66 0x00000000 0x00000000 + 0x00000000 0x1363a096 0x005800a0 0x00008000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00020000 0x00020000 0x00020000 0x00020000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00048000 0x00048000 0x00000000 0x00048000 + 0x00048000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00038000 0x00038000 + 0x00038000 0x00038000 0x00003800 0x00003800 + 0x00003800 0x00003800 0x00000200 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc000 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000008f 0x018c0011 0x00000000 0x00000004 + 0x000052a3 0x80000cc7 0x0000000b >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x800100c3>; + nvidia,emc-mode-2 = <0x80020006>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x02100013>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0123123d>; + nvidia,emc-zcal-cnt-long = <0x00000034>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x0000001f 0x0000006e 0x00000000 0x00000016 + 0x00000009 0x00000009 0x00000009 0x00000003 + 0x0000000d 0x00000009 0x00000009 0x00000005 + 0x00000004 0x00000000 0x00000002 0x00000002 + 0x00000008 0x00000003 0x00000000 0x00000003 + 0x0000000a 0x00050000 0x00000004 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x00000011 0x00000015 0x00000017 0x000007cd + 0x00000000 0x000001f3 0x00000003 0x00000003 + 0x00000009 0x00000000 0x00000001 0x00000011 + 0x00000075 0x00000075 0x00000004 0x00000008 + 0x00000004 0x00000019 0x0000000c 0x00000003 + 0x00000003 0x00000ddd 0x00000000 0x00000000 + 0x00000000 0x1363a096 0xe01200b9 0x00008000 + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00004010 0x00004010 0x00000000 0x00004010 + 0x00004010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x0000000c 0x0000000c + 0x0000000c 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000c 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x000000bf 0x02100013 0x00000000 0x00000004 + 0x000042a0 0x800010b3 0x0000000d >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x800100e3>; + nvidia,emc-mode-2 = <0x80020007>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x02580014>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0121103d>; + nvidia,emc-zcal-cnt-long = <0x0000003a>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000023 0x0000007d 0x00000000 0x00000019 + 0x0000000a 0x0000000a 0x0000000b 0x00000004 + 0x0000000f 0x0000000a 0x0000000a 0x00000005 + 0x00000004 0x00000000 0x00000004 0x00000004 + 0x0000000a 0x00000004 0x00000000 0x00000003 + 0x0000000d 0x00070000 0x00000005 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000002 + 0x00000014 0x00000018 0x0000001a 0x000008e4 + 0x00000000 0x00000239 0x00000004 0x00000004 + 0x0000000a 0x00000000 0x00000001 0x00000013 + 0x00000084 0x00000084 0x00000005 0x00000009 + 0x00000005 0x0000001c 0x0000000d 0x00000003 + 0x00000003 0x00000fc0 0x00000000 0x00000000 + 0x00000000 0x1363a096 0xe00e00b9 0x00008000 + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000010 0x00000010 0x00000000 0x00000010 + 0x00000010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000001 + 0x00000000 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000000 0x00000000 0x00000001 + 0x00000000 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000000 0x0000000c 0x0000000b + 0x0000000b 0x0000000b 0x0000000b 0x0000000b + 0x0000000b 0x0000000b 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000404 0x81f1f008 0x07070000 0x0000003f + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x000000d8 0x02580014 0x00000000 0x00000005 + 0x000040a0 0x800012d6 0x00000010 >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010043>; + nvidia,emc-mode-2 = <0x8002001a>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x03180017>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0120103d>; + nvidia,emc-zcal-cnt-long = <0x0000004c>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x0000002f 0x000000a6 0x00000000 0x00000021 + 0x0000000e 0x0000000d 0x0000000d 0x00000005 + 0x00000013 0x0000000e 0x0000000e 0x00000007 + 0x00000004 0x00000000 0x00000005 0x00000005 + 0x0000000e 0x00000004 0x00000000 0x00000005 + 0x0000000f 0x000b0000 0x00000006 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x00000016 0x0000001d 0x0000001f 0x00000bd1 + 0x00000000 0x000002f4 0x00000005 0x00000005 + 0x0000000e 0x00000000 0x00000001 0x00000017 + 0x000000af 0x000000af 0x00000006 0x0000000c + 0x00000006 0x00000026 0x00000011 0x00000003 + 0x00000003 0x000014cb 0x00000000 0x00000000 + 0x00000000 0x1363a096 0xe00700b9 0x00008000 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000006 0x00000006 0x00000006 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00008012 0x00008012 0x00000000 0x00008012 + 0x00008012 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000002 0x00000005 + 0x00000002 0x00000004 0x00000005 0x00000004 + 0x00000004 0x00000003 0x00000002 0x00000005 + 0x00000002 0x00000004 0x00000005 0x00000004 + 0x00000004 0x00000003 0x0000000b 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000808 0x81f1f008 0x07070000 0x00000000 + 0x015ddddd 0x61861820 0x00514514 0x00514514 + 0x61861800 0x0000003f 0x00000000 0x00000000 + 0x0000011e 0x03180017 0x00000000 0x00000006 + 0x00004080 0x8000188b 0x00000014 >; + }; + + timing-924000000 { + clock-frequency = <924000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0xd3300000>; + nvidia,emc-cfg-2 = <0x0000089f>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80010083>; + nvidia,emc-mode-2 = <0x8002001c>; + nvidia,emc-mode-4 = <0x800b0000>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-mrs-wait-cnt = <0x039c0019>; + nvidia,emc-sel-dpd-ctrl = <0x0004001c>; + nvidia,emc-xm2dqspadctrl2 = <0x0120103d>; + nvidia,emc-zcal-cnt-long = <0x00000058>; + nvidia,emc-zcal-interval = <0x00064000>; + + nvidia,emc-configuration = < + 0x00000037 0x000000c2 0x00000000 0x00000026 + 0x00000010 0x0000000f 0x00000010 0x00000006 + 0x00000017 0x00000010 0x00000010 0x00000009 + 0x00000005 0x00000000 0x00000007 0x00000007 + 0x00000010 0x00000005 0x00000000 0x00000005 + 0x00000012 0x000d0000 0x00000007 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000004 + 0x00000019 0x00000020 0x00000022 0x00000dd4 + 0x00000000 0x00000375 0x00000006 0x00000006 + 0x00000010 0x00000000 0x00000001 0x0000001b + 0x000000cc 0x000000cc 0x00000007 0x0000000e + 0x00000007 0x0000002d 0x00000014 0x00000003 + 0x00000003 0x00001842 0x00000000 0x00000000 + 0x00000000 0x1363a896 0xe00400b9 0x00008000 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x0000000f 0x0000000f 0x00000000 0x00000011 + 0x00000012 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000004 0x00000006 + 0x00000004 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000005 0x00000004 0x00000006 + 0x00000004 0x00000006 0x00000006 0x00000006 + 0x00000006 0x00000005 0x0000000a 0x00000009 + 0x00000009 0x0000000a 0x00000009 0x00000009 + 0x00000009 0x00000009 0x00000220 0x00000000 + 0x00100100 0x00000000 0x00000000 0x77ffc004 + 0x00000404 0x81f1f008 0x07070000 0x00000000 + 0x015ddddd 0x51451420 0x00514514 0x00514514 + 0x51451400 0x0000003f 0x00000000 0x00000000 + 0x0000014d 0x039c0019 0x00000000 0x00000007 + 0x00004080 0x80001c77 0x00000017 >; + }; + }; + }; + + padctl@7009f000 { + status = "disabled"; + }; + + /* WiFi */ + sdmmc1: mmc@700b0000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_P>; + assigned-clock-rates = <204000000>; + + max-frequency = <82000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + sd-uhs-sdr104; + mmc-ddr-1_8v; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* BCM4354XKUBG */ + wifi@1 { + compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + clocks = <&clk32k_pmic>; + clock-names = "lpo"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + /* MicroSD */ + sdmmc3: mmc@700b0400 { + status = "okay"; + bus-width = <4>; + + sd-uhs-sdr104; + mmc-ddr-1_8v; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_hv_sdmmc>; + vqmmc-supply = <&vddio_usd>; + }; + + /* eMMC */ + sdmmc4: mmc@700b0600 { + status = "okay"; + bus-width = <8>; + + mmc-hs200-1_8v; + non-removable; + + vmmc-supply = <&vdd_hv_sdmmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + + ahub@70300000 { + /* HIFI CODEC */ + i2s@70301000 { /* i2s0 */ + status = "okay"; + }; + + /* LEFT SPK */ + i2s@70301100 { /* i2s1 */ + status = "okay"; + }; + + /* RIGHT SPK */ + i2s@70301200 { /* i2s2 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70301300 { /* i2s3 */ + status = "okay"; + }; + }; + + usb1: usb@7d000000 { + compatible = "nvidia,tegra124-udc"; + status = "okay"; + dr_mode = "otg"; + + hnp-disable; + srp-disable; + adp-disable; + + usb-role-switch; + extcon = <&bq24192>, <&palmas_extcon>; /* vbus, id */ + vbus-supply = <&usb_otg_vbus>; + + port { + usb_in: endpoint { + remote-endpoint = <&connector_out>; + }; + }; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&avdd_usb>; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + + charge-full-design-microamp-hours = <6520000>; + energy-full-design-microwatt-hours = <2478000>; + + voltage-min-design-microvolt = <4300000>; + voltage-max-design-microvolt = <4350000>; + + precharge-current-microamp = <256000>; + charge-term-current-microamp = <400000>; + + operating-range-celsius = <0 45>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + connector { + compatible = "usb-b-connector"; + type = "micro"; + + port { + connector_out: endpoint { + remote-endpoint = <&usb_in>; + }; + }; + }; + + cpus { + cpu0: cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-back-hall-sensor { + label = "Hall sensor (back)"; + gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + + switch-front-hall-sensor { + label = "Hall sensor (front)"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + + led-controller { + compatible = "pwm-leds"; + + led-button { + color = ; + function = LED_FUNCTION_BACKLIGHT; + + pwms = <&pwm 1 10000>; + max-brightness = <100>; + }; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_3v3_sys: regulator-3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vddio_1v8_bl: regulator-bl-io { + compatible = "regulator-fixed"; + regulator-name = "vddio_1v8_bl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + vdd_lcd_io: regulator-lcd-vio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + vsp_5v5_lcd: regulator-vsp { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd_vsp"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vsn_5v5_lcd: regulator-vsn { + compatible = "regulator-fixed"; + regulator-name = "avdd_lcd_vsn"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_2v8_tp: regulator-vtp { + compatible = "regulator-fixed"; + regulator-name = "vdd_2v8_tp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_smps10_out2>; + }; + + iovdd_1v8_cam: regulator-iovdd-cam { + compatible = "regulator-fixed"; + regulator-name = "iovdd_1v8_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + dvdd_1v2_cam: regulator-dvdd-cam { + compatible = "regulator-fixed"; + regulator-name = "dvdd_1v2_cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&palmas_gpio 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8_vio>; + }; + + vdd_3v3_hph: regulator-hph { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_hph"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + thermal-zones { + /* + * TMP451 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * tablet from getting too hot from a user's tactile + * perspective. The CPU zone is intended to protect + * silicon from damage. + */ + + tmp451-skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <10000>; /* milliseconds */ + + thermal-sensors = <&temp_sensor 0>; + + trips { + skip_alert_trip: skin-alert { + /* throttle at 50C until temperature drops to 49.5C */ + temperature = <50000>; + hysteresis = <500>; + type = "passive"; + }; + + skin-crit { + /* shut down at 85C */ + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map-skip { + trip = <&skip_alert_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + tmp451-cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <10000>; /* milliseconds */ + + thermal-sensors = <&temp_sensor 1>; + + trips { + cpu_alert_trip: cpu-alert { + /* throttle at 85C until temperature drops to 84.5C */ + temperature = <85000>; + hysteresis = <500>; + type = "passive"; + }; + + cpu-crit { + /* shut down at 95C */ + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map-cpu { + trip = <&cpu_alert_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/dts/upstream/src/arm/nvidia/tegra124.dtsi b/dts/upstream/src/arm/nvidia/tegra124.dtsi index ec4f0e346b2..ce4efa1de50 100644 --- a/dts/upstream/src/arm/nvidia/tegra124.dtsi +++ b/dts/upstream/src/arm/nvidia/tegra124.dtsi @@ -103,6 +103,45 @@ ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; + vi@54080000 { + compatible = "nvidia,tegra124-vi"; + reg = <0x0 0x54080000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + + iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; + }; + + isp@54600000 { + compatible = "nvidia,tegra124-isp"; + reg = <0x0 0x54600000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ISP>; + resets = <&tegra_car TEGRA124_CLK_ISP>; + reset-names = "isp"; + + iommus = <&mc TEGRA_SWGROUP_ISP2>; + + status = "disabled"; + }; + + isp@54680000 { + compatible = "nvidia,tegra124-isp"; + reg = <0x0 0x54680000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ISPB>; + resets = <&tegra_car TEGRA124_CLK_ISPB>; + reset-names = "isp"; + + iommus = <&mc TEGRA_SWGROUP_ISP2B>; + + status = "disabled"; + }; + dc@54200000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; @@ -209,6 +248,31 @@ #size-cells = <0>; }; + msenc@544c0000 { + compatible = "nvidia,tegra124-msenc"; + reg = <0x0 0x544c0000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_MSENC>; + resets = <&tegra_car TEGRA124_CLK_MSENC>; + reset-names = "mpe"; + + iommus = <&mc TEGRA_SWGROUP_MSENC>; + + status = "disabled"; + }; + + tsec@54500000 { + compatible = "nvidia,tegra124-tsec"; + reg = <0x0 0x54500000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_TSEC>; + resets = <&tegra_car TEGRA124_CLK_TSEC>; + + iommus = <&mc TEGRA_SWGROUP_TSEC>; + + status = "disabled"; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; diff --git a/dts/upstream/src/arm/nvidia/tegra20.dtsi b/dts/upstream/src/arm/nvidia/tegra20.dtsi index 882adb7f2f2..c60fc197118 100644 --- a/dts/upstream/src/arm/nvidia/tegra20.dtsi +++ b/dts/upstream/src/arm/nvidia/tegra20.dtsi @@ -64,7 +64,7 @@ vi@54080000 { compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; + reg = <0x54080000 0x00000800>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 20>; @@ -72,6 +72,23 @@ power-domains = <&pd_venc>; operating-points-v2 = <&vi_dvfs_opp_table>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible = "nvidia,tegra20-csi"; + reg = <0x800 0x200>; + clocks = <&tegra_car TEGRA20_CLK_CSI>; + power-domains = <&pd_venc>; + #nvidia,mipi-calibrate-cells = <1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; epp@540c0000 { diff --git a/dts/upstream/src/arm/nvidia/tegra30.dtsi b/dts/upstream/src/arm/nvidia/tegra30.dtsi index 2a4d93db813..4c4e6097c91 100644 --- a/dts/upstream/src/arm/nvidia/tegra30.dtsi +++ b/dts/upstream/src/arm/nvidia/tegra30.dtsi @@ -150,8 +150,8 @@ }; vi@54080000 { - compatible = "nvidia,tegra30-vi"; - reg = <0x54080000 0x00040000>; + compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi"; + reg = <0x54080000 0x00000800>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_VI>; resets = <&tegra_car 20>; @@ -162,6 +162,26 @@ iommus = <&mc TEGRA_SWGROUP_VI>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x54080000 0x4000>; + + csi: csi@800 { + compatible = "nvidia,tegra30-csi"; + reg = <0x800 0x200>; + clocks = <&tegra_car TEGRA30_CLK_CSI>, + <&tegra_car TEGRA30_CLK_CSIA_PAD>, + <&tegra_car TEGRA30_CLK_CSIB_PAD>; + clock-names = "csi", "csia-pad", "csib-pad"; + power-domains = <&pd_venc>; + #nvidia,mipi-calibrate-cells = <1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; epp@540c0000 { diff --git a/dts/upstream/src/arm/nxp/imx/e70k02.dtsi b/dts/upstream/src/arm/nxp/imx/e70k02.dtsi index dcc3c9d488a..3bb11c5a635 100644 --- a/dts/upstream/src/arm/nxp/imx/e70k02.dtsi +++ b/dts/upstream/src/arm/nxp/imx/e70k02.dtsi @@ -69,6 +69,14 @@ reg = <0x80000000 0x20000000>; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; + reg_wifi: regulator-wifi { compatible = "regulator-fixed"; regulator-name = "SD3_SPWR"; @@ -133,7 +141,22 @@ vdd-supply = <&ldo5_reg>; }; - /* TODO: SY7636 PMIC for E Ink at 0x62 */ + sy7636: pmic@62 { + compatible = "silergy,sy7636a"; + reg = <0x62>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + vcom-en-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + epd-pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + vin-supply = <&epd_pmic_supply>; + + #thermal-sensor-cells = <0>; + + regulators { + reg_epdpmic: vcom { + regulator-name = "vcom"; + }; + }; + }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts index b8048e12e3d..5398e9067e6 100644 --- a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts +++ b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts @@ -248,14 +248,14 @@ linux,default-trigger = "nand-disk"; }; - ledg3: led@10 { - reg = <10>; + ledg3: led@a { + reg = <0xa>; label = "system:green3:live"; linux,default-trigger = "heartbeat"; }; - ledb3: led@11 { - reg = <11>; + ledb3: led@b { + reg = <0xb>; label = "system:blue3:cpu"; linux,default-trigger = "cpu0"; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts b/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts index 43ff5eafb2b..91c63d1f260 100644 --- a/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts +++ b/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts @@ -398,13 +398,13 @@ #size-cells = <0>; led-control = <0x0 0x0 0x3f83f8 0x0>; - sysled0@3 { + led@3 { reg = <3>; label = "system:green:status"; linux,default-trigger = "default-on"; }; - sysled1@4 { + led@4 { reg = <4>; label = "system:green:act"; linux,default-trigger = "heartbeat"; diff --git a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts index 26eb7a9506e..1598bf4f499 100644 --- a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts +++ b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts @@ -225,13 +225,13 @@ #size-cells = <0>; led-control = <0x0 0x0 0x3f83f8 0x0>; - sysled3: led3@3 { + sysled3: led@3 { reg = <3>; label = "system:red:power"; linux,default-trigger = "default-on"; }; - sysled4: led4@4 { + sysled4: led@4 { reg = <4>; label = "system:green:act"; linux,default-trigger = "heartbeat"; diff --git a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu3-esb.dts b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu3-esb.dts index 19a3b142c96..c2dcfd44c44 100644 --- a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu3-esb.dts +++ b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu3-esb.dts @@ -153,13 +153,13 @@ #size-cells = <0>; led-control = <0x0 0x0 0x3f83f8 0x0>; - sysled3: led3@3 { + sysled3: led@3 { reg = <3>; label = "system:red:power"; linux,default-trigger = "default-on"; }; - sysled4: led4@4 { + sysled4: led@4 { reg = <4>; label = "system:green:act"; linux,default-trigger = "heartbeat"; diff --git a/dts/upstream/src/arm/nxp/imx/imx53-ppd.dts b/dts/upstream/src/arm/nxp/imx/imx53-ppd.dts index 2892e457fea..e45a97d3f44 100644 --- a/dts/upstream/src/arm/nxp/imx/imx53-ppd.dts +++ b/dts/upstream/src/arm/nxp/imx/imx53-ppd.dts @@ -537,6 +537,8 @@ mpl3115: pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; }; eeprom: eeprom@50 { diff --git a/dts/upstream/src/arm/nxp/imx/imx53-qsrb.dts b/dts/upstream/src/arm/nxp/imx/imx53-qsrb.dts index 2f06ad61a76..6938ad6dbc2 100644 --- a/dts/upstream/src/arm/nxp/imx/imx53-qsrb.dts +++ b/dts/upstream/src/arm/nxp/imx/imx53-qsrb.dts @@ -28,6 +28,7 @@ reg = <0x08>; interrupt-parent = <&gpio5>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; regulators { sw1_reg: sw1a { regulator-name = "SW1"; diff --git a/dts/upstream/src/arm/nxp/imx/imx53-usbarmory.dts b/dts/upstream/src/arm/nxp/imx/imx53-usbarmory.dts index acc44010d51..3ad9db4b144 100644 --- a/dts/upstream/src/arm/nxp/imx/imx53-usbarmory.dts +++ b/dts/upstream/src/arm/nxp/imx/imx53-usbarmory.dts @@ -1,47 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * USB armory MkI device tree file * https://inversepath.com/usbarmory * * Copyright (C) 2015, Inverse Path * Andrej Rosano - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_7.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_7.dts index a7400d42475..bf8e07f9714 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_7.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_7.dts @@ -20,6 +20,7 @@ panel: panel { compatible = "lg,lb070wv8"; backlight = <&backlight>; + power-supply = <®_3p3v>; enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; port { diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-b1x5v2.dtsi b/dts/upstream/src/arm/nxp/imx/imx6dl-b1x5v2.dtsi index 590dcc0953c..5dc7f1f9ca1 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-b1x5v2.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-b1x5v2.dtsi @@ -47,7 +47,8 @@ mpl3115a2: pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; - + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; /* * The MPL3115 interrupts are connected to pin 22 and 23 * of &tca6424a, but the binding does not yet support diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-lanmcu.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-lanmcu.dts index 7c62db91173..47a6d63c8e0 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-lanmcu.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-lanmcu.dts @@ -72,6 +72,7 @@ panel { compatible = "edt,etm0700g0bdh6"; backlight = <&backlight>; + power-supply = <®_panel>; port { panel_in: endpoint { @@ -89,6 +90,13 @@ enable-active-high; }; + reg_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-plym2m.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-plym2m.dts index dfa8110b1d9..0ef24a07ded 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-plym2m.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-plym2m.dts @@ -123,7 +123,7 @@ }; }; - touch-thermal0 { + touch-0-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; @@ -137,7 +137,7 @@ }; }; - touch-thermal1 { + touch-1-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-prtvt7.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-prtvt7.dts index 29dc6875ab6..353f7097cb7 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-prtvt7.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-prtvt7.dts @@ -55,7 +55,7 @@ iio-hwmon { compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>; + io-channels = <&vdiv_vaccu 0>; }; keys { @@ -256,7 +256,7 @@ }; }; - touch-thermal0 { + touch-0-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; @@ -270,7 +270,7 @@ }; }; - touch-thermal1 { + touch-1-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; @@ -318,7 +318,7 @@ io-channels = <&adc_ts 2>; output-ohms = <2500>; full-ohms = <64000>; - #io-channel-cells = <0>; + #io-channel-cells = <1>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-qmx6.dtsi b/dts/upstream/src/arm/nxp/imx/imx6dl-qmx6.dtsi index 7a3b96315ea..d5baec5e7a7 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-qmx6.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-qmx6.dtsi @@ -14,6 +14,7 @@ / { memory@10000000 { reg = <0x10000000 0x40000000>; + device_type = "memory"; }; reg_3p3v: 3p3v { diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-victgo.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-victgo.dts index 4875afadb63..76b0007d20a 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-victgo.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-victgo.dts @@ -35,7 +35,7 @@ iio-hwmon { compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; + io-channels = <&vdiv_vaccu 0>, <&vdiv_hitch_pos 0>; }; panel { @@ -84,7 +84,7 @@ }; }; - touch-thermal0 { + touch-0-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; @@ -98,7 +98,7 @@ }; }; - touch-thermal1 { + touch-1-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; @@ -147,7 +147,7 @@ io-channels = <&adc_ts 2>; output-ohms = <2500>; full-ohms = <64000>; - #io-channel-cells = <0>; + #io-channel-cells = <1>; }; vdiv_hitch_pos: voltage-divider-hitch-pos { @@ -155,7 +155,7 @@ io-channels = <&adc_ts 6>; output-ohms = <3300>; full-ohms = <13300>; - #io-channel-cells = <0>; + #io-channel-cells = <1>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi index 8bc6376d0dc..4a573652692 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-common.dtsi @@ -279,28 +279,32 @@ #size-cells = <0>; status = "disabled"; - led@0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <0>; - color = ; - }; + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + color = ; + function = LED_FUNCTION_INDICATOR; - led@1 { - chan-name = "G"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <1>; - color = ; - }; + led@0 { + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <0>; + color = ; + }; - led@2 { - chan-name = "B"; - led-cur = /bits/ 8 <0x20>; - max-cur = /bits/ 8 <0x60>; - reg = <2>; - color = ; + led@1 { + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <1>; + color = ; + }; + + led@2 { + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <2>; + color = ; + }; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-lynx.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-lynx.dts index 5c2cd517589..0a6b668428a 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-lynx.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp4-lynx.dts @@ -21,6 +21,10 @@ status = "okay"; }; +&beeper { + status = "okay"; +}; + &lcd_display { status = "okay"; }; @@ -37,6 +41,10 @@ status = "okay"; }; +&pwm3 { + status = "okay"; +}; + ®_usb_h1_vbus { status = "okay"; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi index 2f42c56c21f..6e49e1ccf6f 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi @@ -26,6 +26,12 @@ status = "disabled"; }; + beeper: beeper { + compatible = "pwm-beeper"; + pwms = <&pwm3 0 500000 0>; + status = "disabled"; + }; + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -272,28 +278,32 @@ #size-cells = <0>; status = "disabled"; - led@0 { - chan-name = "R"; - led-cur = /bits/ 8 <0x6e>; - max-cur = /bits/ 8 <0xc8>; - reg = <0>; - color = ; - }; + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + color = ; + function = LED_FUNCTION_INDICATOR; - led@1 { - chan-name = "G"; - led-cur = /bits/ 8 <0xbe>; - max-cur = /bits/ 8 <0xc8>; - reg = <1>; - color = ; - }; + led@0 { + led-cur = /bits/ 8 <0x6e>; + max-cur = /bits/ 8 <0xc8>; + reg = <0>; + color = ; + }; - led@2 { - chan-name = "B"; - led-cur = /bits/ 8 <0xbe>; - max-cur = /bits/ 8 <0xc8>; - reg = <2>; - color = ; + led@1 { + led-cur = /bits/ 8 <0xbe>; + max-cur = /bits/ 8 <0xc8>; + reg = <1>; + color = ; + }; + + led@2 { + led-cur = /bits/ 8 <0xbe>; + max-cur = /bits/ 8 <0xc8>; + reg = <2>; + color = ; + }; }; }; @@ -466,6 +476,13 @@ >; }; + pinctrl_sound: soundgrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x8 + >; + }; + pinctrl_touch: touchgrp { fsl,pins = < MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 @@ -551,6 +568,12 @@ status = "disabled"; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sound>; + status = "disabled"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-ba16.dtsi b/dts/upstream/src/arm/nxp/imx/imx6q-ba16.dtsi index 53013b12c2e..02d66523668 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-ba16.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6q-ba16.dtsi @@ -337,7 +337,7 @@ pinctrl-0 = <&pinctrl_rtc>; reg = <0x32>; interrupt-parent = <&gpio4>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-bosch-acc.dts b/dts/upstream/src/arm/nxp/imx/imx6q-bosch-acc.dts index d3f14b4d3b5..929def2bb35 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-bosch-acc.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-bosch-acc.dts @@ -46,6 +46,7 @@ panel { compatible = "dataimage,fg1001l0dsswmg01"; backlight = <&backlight_lvds>; + power-supply = <®_lcd>; port { panel_in: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi index e1d0c6e123f..1e2266a2368 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi @@ -195,6 +195,8 @@ mma8453: mma8453@1c { compatible = "fsl,mma8453"; reg = <0x1c>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; @@ -211,6 +213,8 @@ mpl3115: mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-cm-fx6.dts b/dts/upstream/src/arm/nxp/imx/imx6q-cm-fx6.dts index 299106fbe51..13245af8f74 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-cm-fx6.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-cm-fx6.dts @@ -73,7 +73,7 @@ reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; }; - reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio { + reg_pcie_power_on_gpio: regulator-pcie-power-on { compatible = "regulator-fixed"; regulator-name = "regulator-pcie-power-on-gpio"; regulator-min-microvolt = <3300000>; @@ -99,6 +99,34 @@ enable-active-high; }; + avdd_reg: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "avdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hpvdd_reg: regulator-hpvdd { + compatible = "regulator-fixed"; + regulator-name = "hpvdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + dcvdd_reg: regulator-dcvdd { + compatible = "regulator-fixed"; + regulator-name = "dcvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + dbvdd_reg: regulator-dbvdd { + compatible = "regulator-fixed"; + regulator-name = "dbvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + sound-analog { compatible = "simple-audio-card"; simple-audio-card,name = "On-board analog audio"; @@ -307,6 +335,10 @@ #sound-dai-cells = <0>; compatible = "wlf,wm8731"; reg = <0x1a>; + AVDD-supply = <&avdd_reg>; + HPVDD-supply = <&hpvdd_reg>; + DCVDD-supply = <&dcvdd_reg>; + DBVDD-supply = <&dbvdd_reg>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-dmo-edmqmx6.dts b/dts/upstream/src/arm/nxp/imx/imx6q-dmo-edmqmx6.dts index 17fabff80e9..cbe580dec18 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-dmo-edmqmx6.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-dmo-edmqmx6.dts @@ -236,9 +236,12 @@ vcc-supply = <&sw2_reg>; vio-supply = <&sw2_reg>; - stmpe_gpio1: stmpe_gpio { + stmpe_gpio1: gpio { #gpio-cells = <2>; compatible = "st,stmpe-gpio"; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; }; @@ -250,9 +253,12 @@ vcc-supply = <&sw2_reg>; vio-supply = <&sw2_reg>; - stmpe_gpio2: stmpe_gpio { + stmpe_gpio2: gpio { #gpio-cells = <2>; compatible = "st,stmpe-gpio"; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-evi.dts b/dts/upstream/src/arm/nxp/imx/imx6q-evi.dts index 78d941fef5d..c936180ed32 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-evi.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-evi.dts @@ -55,6 +55,13 @@ reg = <0x10000000 0x40000000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usbh1_vbus: regulator-usbhubreset { compatible = "regulator-fixed"; regulator-name = "usbh1_vbus"; @@ -81,6 +88,7 @@ panel { compatible = "sharp,lq101k1ly04"; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -124,7 +132,7 @@ pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>; status = "okay"; - eeprom: m95m02@1 { + eeprom: eeprom@1 { compatible = "st,m95m02", "atmel,at25"; size = <262144>; pagesize = <256>; @@ -134,7 +142,7 @@ }; pb_rtc: rtc@3 { - compatible = "nxp,rtc-pcf2123"; + compatible = "nxp,pcf2123"; spi-max-frequency = <2450000>; spi-cs-high; reg = <3>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap10.dts b/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap10.dts index 02aca1e28ce..1ad3bdcea4a 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap10.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap10.dts @@ -16,6 +16,7 @@ panel { compatible = "ampire,am-1280800n3tzqw-t00h"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap12.dts b/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap12.dts index 241811c52b6..9e1c64da0b3 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap12.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-icore-ofcap12.dts @@ -16,6 +16,7 @@ panel { compatible = "koe,tx31d200vm0baa"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-pistachio.dts b/dts/upstream/src/arm/nxp/imx/imx6q-pistachio.dts index 56b77cc0af2..b8567167779 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-pistachio.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-pistachio.dts @@ -145,6 +145,7 @@ panel { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { @@ -324,8 +325,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /*pcie power*/ diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-prti6q.dts b/dts/upstream/src/arm/nxp/imx/imx6q-prti6q.dts index fb81bd8ba03..73ed40ae5a7 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-prti6q.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-prti6q.dts @@ -57,6 +57,7 @@ panel { compatible = "kyo,tcg121xglp"; backlight = <&backlight_lcd>; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -72,6 +73,13 @@ regulator-max-microvolt = <1800000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_wifi: regulator-wifi { compatible = "regulator-fixed"; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-tbs2910.dts b/dts/upstream/src/arm/nxp/imx/imx6q-tbs2910.dts index 5353a0c2442..3bd0e2c9e57 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-tbs2910.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-tbs2910.dts @@ -37,7 +37,7 @@ 3000 1>; }; - ir_recv { + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-utilite-pro.dts b/dts/upstream/src/arm/nxp/imx/imx6q-utilite-pro.dts index aae81feee00..c78f101c3cc 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-utilite-pro.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-utilite-pro.dts @@ -326,11 +326,14 @@ &pcie { pcie@0,0 { reg = <0x000000 0 0 0 0>; + device_type = "pci"; #address-cells = <3>; #size-cells = <2>; + bus-range = <0x00 0xff>; + ranges; /* non-removable i211 ethernet card */ - eth1: intel,i211@pcie0,0 { + eth1: ethernet@0,0 { reg = <0x010000 0 0 0 0>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts b/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts index 18a620832a2..a55644529c6 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "imx6q.dtsi" #include "imx6qdl-var-som.dtsi" #include diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-yapp4-pegasus.dts b/dts/upstream/src/arm/nxp/imx/imx6q-yapp4-pegasus.dts index ec6651ba4ba..7332f271898 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6q-yapp4-pegasus.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6q-yapp4-pegasus.dts @@ -17,6 +17,10 @@ }; }; +&beeper { + status = "okay"; +}; + &gpio_oled { status = "okay"; }; @@ -37,6 +41,10 @@ status = "okay"; }; +&pwm3 { + status = "okay"; +}; + ®_pu { regulator-always-on; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi index 419d85b5a66..8a0ce250e57 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi @@ -589,7 +589,7 @@ st,touch-det-delay = <5>; }; - stmpe_adc: stmpe_adc { + stmpe_adc: adc { compatible = "st,stmpe-adc"; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi index ea92b2b5c50..e9d5bbb4314 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi @@ -462,7 +462,6 @@ regulator-ramp-delay = <7000>; regulator-boot-on; regulator-always-on; - linux,phandle = <®_vdd_arm>; }; /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi index b518bcb6b7a..01f77142e15 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi @@ -360,7 +360,6 @@ regulator-ramp-delay = <7000>; regulator-boot-on; regulator-always-on; - linux,phandle = <®_vdd_arm>; }; /* VDD_SOC (1+R1/R2 = 1.635) */ @@ -372,7 +371,6 @@ regulator-ramp-delay = <7000>; regulator-boot-on; regulator-always-on; - linux,phandle = <®_vdd_soc>; }; /* VDD_1P0 (1+R1/R2 = 1.38): */ diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-nit6xlite.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-nit6xlite.dtsi index 8d471450d5c..610b2a72fe8 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-nit6xlite.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -127,6 +127,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; + power-supply = <®_3p3v>; port { panel_in_lvds0: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_max.dtsi index c727aac257f..ef0c2668844 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -135,13 +135,13 @@ i2c-parent = <&i2c2>; idle-state = <0>; - i2c2mux@1 { + i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; - i2c2mux@2 { + i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; @@ -158,7 +158,7 @@ i2c-parent = <&i2c3>; idle-state = <0>; - i2c3mux@1 { + i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -237,6 +237,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -248,6 +249,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; + power-supply = <®_3p3v>; port { panel_in_lvds0: endpoint { @@ -259,6 +261,7 @@ panel-lvds1 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds1>; + power-supply = <®_3p3v>; port { panel_in_lvds1: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_som2.dtsi index 806af7f6041..03fe053880c 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_som2.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -114,6 +114,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -125,6 +126,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds0>; + power-supply = <®_3p3v>; port { panel_in_lvds0: endpoint { @@ -136,6 +138,7 @@ panel-lvds1 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds1>; + power-supply = <®_3p3v>; port { panel_in_lvds1: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6x.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6x.dtsi index c71aa7498ac..6a353a99e13 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6x.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -179,6 +179,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -190,6 +191,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabrelite.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabrelite.dtsi index f7abc17c7c9..3b7d01065e8 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabrelite.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabrelite.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { chosen { @@ -207,6 +208,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3p3v>; port { lcd_panel_in: endpoint { @@ -218,6 +220,7 @@ panel-lvds0 { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3p3v>; port { panel_in: endpoint { @@ -360,7 +363,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ov5642>; clocks = <&clks IMX6QDL_CLK_CKO2>; - clock-names = "xclk"; reg = <0x42>; reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; @@ -370,6 +372,7 @@ port { ov5642_to_ipu1_csi0_mux: endpoint { remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-type = ; bus-width = <8>; hsync-active = <1>; vsync-active = <1>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi index e8368c6b27e..ba29720e3f7 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { chosen { @@ -17,6 +18,13 @@ reg = <0x10000000 0x40000000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -139,6 +147,7 @@ panel { compatible = "hannstar,hsd100pxn1"; backlight = <&backlight_lvds>; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -278,7 +287,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ov5642>; clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; reg = <0x3c>; DOVDD-supply = <&vgen4_reg>; /* 1.8v */ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 @@ -291,6 +299,7 @@ port { ov5642_to_ipu1_csi0_mux: endpoint { remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-type = ; bus-width = <8>; hsync-active = <1>; vsync-active = <1>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi index 6ab71a729fd..c93dbc595ef 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -69,7 +69,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_switch>; interrupt-parent = <&gpio3>; - interrupt = <30 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; reg = <0>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-ts4900.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-ts4900.dtsi index f88da757edd..948b612496a 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-ts4900.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-ts4900.dtsi @@ -140,7 +140,7 @@ reg = <0x28>; #gpio-cells = <2>; gpio-controller; - ngpio = <32>; + ngpios = <32>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-mb7.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-mb7.dtsi index dd4e5bce4a5..8232f4ea275 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-mb7.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-mb7.dtsi @@ -16,16 +16,19 @@ lcd-panel { compatible = "edt,et057090dhu"; + power-supply = <®_lcd1_pwr>; pixelclk-active = <0>; }; lvds0-panel { compatible = "edt,etml1010g0dka"; + power-supply = <®_lcd1_pwr>; pixelclk-active = <0>; }; lvds1-panel { compatible = "edt,etml1010g0dka"; + power-supply = <®_lcd1_pwr>; pixelclk-active = <0>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-var-som.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-var-som.dtsi index 2bff5f92242..fef34ce961d 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qdl-var-som.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-var-som.dtsi @@ -9,9 +9,6 @@ * Copyright 2022 Bootlin */ -/dts-v1/; - -#include "imx6q.dtsi" #include #include #include diff --git a/dts/upstream/src/arm/nxp/imx/imx6qp-yapp4-pegasus-plus.dts b/dts/upstream/src/arm/nxp/imx/imx6qp-yapp4-pegasus-plus.dts index 4a961a33bf2..770a85e0561 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6qp-yapp4-pegasus-plus.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6qp-yapp4-pegasus-plus.dts @@ -17,6 +17,10 @@ }; }; +&beeper { + status = "okay"; +}; + &gpio_oled { status = "okay"; }; @@ -37,6 +41,10 @@ status = "okay"; }; +&pwm3 { + status = "okay"; +}; + ®_pu { regulator-always-on; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision.dts b/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision.dts index 2694fe18a91..7cda1f21e41 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision.dts @@ -227,7 +227,6 @@ }; &usbotg1 { - pinctrl-names = "default"; disable-over-current; srp-disable; hnp-disable; diff --git a/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision5.dts b/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision5.dts index a2534c422a5..f8709a95240 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision5.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6sl-tolino-vision5.dts @@ -26,6 +26,11 @@ compatible = "kobo,tolino-vision5", "fsl,imx6sl"; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -59,6 +64,12 @@ >; }; + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */ @@ -159,6 +170,14 @@ >; }; + pinctrl_sy7636_gpio: sy7636-gpiogrp { + fsl,pins = < + MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* VCOM_CTRL */ + MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* PWR_GOOD */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 @@ -329,6 +348,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&sy7636 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sy7636_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6sll-kobo-librah2o.dts b/dts/upstream/src/arm/nxp/imx/imx6sll-kobo-librah2o.dts index 660620d226f..19bbe60331b 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6sll-kobo-librah2o.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6sll-kobo-librah2o.dts @@ -36,6 +36,11 @@ soc-supply = <&dcdc1_reg>; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -69,6 +74,12 @@ >; }; + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ @@ -169,6 +180,14 @@ >; }; + pinctrl_sy7636_gpio: sy7636-gpiogrp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* VCOM_CTRL */ + MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x17059 /* PWR_GOOD */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 @@ -319,6 +338,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&sy7636 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sy7636_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi index c7aeb99d8f0..3e238d8118f 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi @@ -119,7 +119,7 @@ regulator-always-on; }; - reg_pcie_gpio: regulator-pcie-gpio { + reg_pcie_gpio: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_reg>; diff --git a/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi index 73c9cfbdba6..3d147b160ec 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi @@ -43,6 +43,13 @@ regulator-max-microvolt = <2800000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -157,6 +164,7 @@ panel { compatible = "innolux,at043tn24"; backlight = <&backlight_display>; + power-supply = <®_3v3>; port { panel_in: endpoint { diff --git a/dts/upstream/src/arm/nxp/imx/imx6ul-isiot.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ul-isiot.dtsi index 4c09bb31269..e34c8cbe36a 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6ul-isiot.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6ul-isiot.dtsi @@ -122,15 +122,21 @@ VDDD-supply = <®_1p8v>; }; - stmpe811: gpio-expander@44 { + gpio-expander@44 { compatible = "st,stmpe811"; reg = <0x44>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_stmpe>; interrupt-parent = <&gpio1>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; + + gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; stmpe: touchscreen { compatible = "st,stmpe-ts"; diff --git a/dts/upstream/src/arm/nxp/imx/imx6ul-pico-dwarf.dts b/dts/upstream/src/arm/nxp/imx/imx6ul-pico-dwarf.dts index fb206c1d8ac..fbab126f95b 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6ul-pico-dwarf.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6ul-pico-dwarf.dts @@ -49,5 +49,7 @@ pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6ull-dhcom-pdk2.dts b/dts/upstream/src/arm/nxp/imx/imx6ull-dhcom-pdk2.dts index b29713831a7..04e570d76e4 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6ull-dhcom-pdk2.dts +++ b/dts/upstream/src/arm/nxp/imx/imx6ull-dhcom-pdk2.dts @@ -199,7 +199,7 @@ reg = <0x38>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - power-supply = <®_panel_3v3>; + vcc-supply = <®_panel_3v3>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi index 7ee25b14162..6fd68970c0b 100644 --- a/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi +++ b/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -126,7 +126,7 @@ s25fl064: flash@2 { #address-cells = <1>; #size-cells = <1>; - compatible = " jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <2>; spi-max-frequency = <40000000>; m25p,fast-read; diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-nitrogen7.dts b/dts/upstream/src/arm/nxp/imx/imx7d-nitrogen7.dts index 7acd28658e6..2192f105ec8 100644 --- a/dts/upstream/src/arm/nxp/imx/imx7d-nitrogen7.dts +++ b/dts/upstream/src/arm/nxp/imx/imx7d-nitrogen7.dts @@ -35,6 +35,7 @@ panel-lcd { compatible = "okaya,rs800480t-7x0gp"; backlight = <&backlight_lcd>; + power-supply = <®_3v3>; port { panel_in: endpoint { @@ -61,6 +62,13 @@ enable-active-high; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_can2_3v3: regulator-can2-3v3 { compatible = "regulator-fixed"; regulator-name = "can2-3v3"; diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts b/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts index 1b965652291..347dd0fe4f8 100644 --- a/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts +++ b/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts @@ -49,6 +49,8 @@ pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts b/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts index 17236f90ab3..a370e868caf 100644 --- a/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts +++ b/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts @@ -406,6 +406,8 @@ mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_audio_3v3>; + vddio-supply = <®_audio_3v3>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx7s-warp.dts b/dts/upstream/src/arm/nxp/imx/imx7s-warp.dts index 56dedd4fb8f..92b6258059e 100644 --- a/dts/upstream/src/arm/nxp/imx/imx7s-warp.dts +++ b/dts/upstream/src/arm/nxp/imx/imx7s-warp.dts @@ -31,6 +31,13 @@ }; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_peri_3p15v: regulator-peri-3p15v { compatible = "regulator-fixed"; regulator-name = "peri_3p15v_reg"; @@ -228,6 +235,8 @@ mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; }; }; diff --git a/dts/upstream/src/arm/nxp/imx/imx7ulp-evk.dts b/dts/upstream/src/arm/nxp/imx/imx7ulp-evk.dts index eff51e113db..88d7dc005fa 100644 --- a/dts/upstream/src/arm/nxp/imx/imx7ulp-evk.dts +++ b/dts/upstream/src/arm/nxp/imx/imx7ulp-evk.dts @@ -92,7 +92,6 @@ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 >; - bias-pull-up; }; pinctrl_pwm0: pwm0grp { diff --git a/dts/upstream/src/arm/nxp/mxs/imx28-amarula-rmm.dts b/dts/upstream/src/arm/nxp/mxs/imx28-amarula-rmm.dts index af59211842f..ddb64f3d047 100644 --- a/dts/upstream/src/arm/nxp/mxs/imx28-amarula-rmm.dts +++ b/dts/upstream/src/arm/nxp/mxs/imx28-amarula-rmm.dts @@ -112,6 +112,29 @@ enable-active-high; regulator-always-on; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx28-mrmmi-tlv320aic3x-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPROUT", + "Headphone Jack", "HPRCOM"; + simple-audio-card,mclk-fs = <512>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&saif0>; + clocks = <&saif0>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&tlv320aic3x>; + }; + }; }; &auart0 { @@ -154,6 +177,19 @@ pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + tlv320aic3x: audio-codec@18 { + compatible = "ti,tlv320aic3x"; + pinctrl-names = "default"; + pinctrl-0 = <&tlv320aic3x_pins>; + reg = <0x18>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + DVDD-supply = <®_1v8>; + IOVDD-supply = <®_3v3>; + AVDD-supply = <®_3v3>; + DRVDD-supply = <®_3v3>; + }; + touchscreen: touchscreen@38 { compatible = "edt,edt-ft5306"; reg = <0x38>; @@ -246,6 +282,14 @@ fsl,voltage = ; }; + tlv320aic3x_pins: tlv320aic3x-pins@0 { + reg = <0>; + fsl,pinmux-ids = ; + fsl,drive-strength = ; + fsl,pull-up = ; + fsl,voltage = ; + }; + usb0_vbus_enable_pin: usb0-vbus-enable@0 { reg = <0>; fsl,pinmux-ids = ; @@ -269,6 +313,12 @@ status = "okay"; }; +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + /* microSD */ &ssp0 { compatible = "fsl,imx28-mmc"; diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226-samsung-ms013g.dts b/dts/upstream/src/arm/qcom/qcom-msm8226-samsung-ms013g.dts index 08b50dc6392..80fe2916501 100644 --- a/dts/upstream/src/arm/qcom/qcom-msm8226-samsung-ms013g.dts +++ b/dts/upstream/src/arm/qcom/qcom-msm8226-samsung-ms013g.dts @@ -13,13 +13,37 @@ chassis-type = "handset"; aliases { + display0 = &framebuffer0; mmc0 = &sdhc_1; /* SDC1 eMMC slot */ mmc1 = &sdhc_2; /* SDC2 SD card slot */ serial0 = &blsp1_uart3; }; chosen { - stdout-path = "serial0:115200n8"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + memory-region = <&cont_splash_region>; + + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; + }; }; gpio-hall-sensor { @@ -93,6 +117,11 @@ }; reserved-memory { + cont_splash_region: cont-splash@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + smem_region: smem@fa00000 { reg = <0x0fa00000 0x100000>; no-map; diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts b/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts index 36f4c997b0b..1df078d7d89 100644 --- a/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts +++ b/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts @@ -19,7 +19,7 @@ ext_l2: gpio-regulator { compatible = "regulator-fixed"; regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; + gpio = <&tlmm 91 0>; startup-delay-us = <10000>; enable-active-high; }; @@ -38,12 +38,12 @@ ethernet@0 { compatible = "micrel,ks8851"; reg = <0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <90 IRQ_TYPE_LEVEL_LOW>; spi-max-frequency = <5400000>; vdd-supply = <&ext_l2>; vdd-io-supply = <&pm8921_lvs6>; - reset-gpios = <&msmgpio 89 0>; + reset-gpios = <&tlmm 89 0>; }; }; @@ -56,7 +56,7 @@ status = "okay"; }; -&msmgpio { +&tlmm { spi1_default: spi1-default-state { mosi-pins { pins = "gpio6"; @@ -90,7 +90,7 @@ }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &pm8921_keypad { diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960-pins.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8960-pins.dtsi deleted file mode 100644 index f18753e9f5e..00000000000 --- a/dts/upstream/src/arm/qcom/qcom-msm8960-pins.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&msmgpio { - i2c3_default_state: i2c3-default-state { - i2c3-pins { - pins = "gpio16", "gpio17"; - function = "gsbi3"; - drive-strength = <8>; - bias-disable; - }; - }; - - i2c3_sleep_state: i2c3-sleep-state { - i2c3-pins { - pins = "gpio16", "gpio17"; - function = "gpio"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - - sdcc3_default_state: sdcc3-default-state { - clk-pins { - pins = "sdc3_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "sdc3_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "sdc3_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; - - sdcc3_sleep_state: sdcc3-sleep-state { - clk-pins { - pins = "sdc3_clk"; - drive-strength = <2>; - bias-disable; - }; - - cmd-pins { - pins = "sdc3_cmd"; - drive-strength = <2>; - bias-pull-up; - }; - - data-pins { - pins = "sdc3_data"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts b/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts index 49d117ea033..5ee919dce75 100644 --- a/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts @@ -31,7 +31,7 @@ key-home { label = "Home"; - gpios = <&msmgpio 40 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 40 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = ; wakeup-event-action = ; @@ -40,14 +40,14 @@ key-volume-up { label = "Volume Up"; - gpios = <&msmgpio 50 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = ; }; key-volume-down { label = "Volume Down"; - gpios = <&msmgpio 81 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; debounce-interval = <5>; linux,code = ; }; @@ -102,7 +102,7 @@ touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; vdda-supply = <&pm8921_lvs6>; vdd-supply = <&pm8921_l17>; @@ -111,7 +111,7 @@ }; }; -&msmgpio { +&tlmm { spi1_default: spi1-default-state { mosi-pins { pins = "gpio6"; @@ -160,7 +160,7 @@ }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &rpm { diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960-sony-huashan.dts b/dts/upstream/src/arm/qcom/qcom-msm8960-sony-huashan.dts index f2f59fc8b9b..591dc837e60 100644 --- a/dts/upstream/src/arm/qcom/qcom-msm8960-sony-huashan.dts +++ b/dts/upstream/src/arm/qcom/qcom-msm8960-sony-huashan.dts @@ -54,7 +54,7 @@ }; &pm8921 { - interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; &pm8921_gpio { diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi index 6e272d5345a..38bd4fd8dda 100644 --- a/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi +++ b/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi @@ -15,6 +15,35 @@ compatible = "qcom,msm8960"; interrupt-parent = <&intc>; + clocks { + cxo_board: cxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "cxo_board"; + }; + + pxo_board: pxo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "pxo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "sleep_clk"; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = ; + qcom,no-pc-write; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -22,9 +51,9 @@ cpu@0 { compatible = "qcom,krait"; + reg = <0>; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; - reg = <0>; next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; @@ -32,9 +61,9 @@ cpu@1 { compatible = "qcom,krait"; + reg = <1>; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; - reg = <1>; next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; @@ -52,6 +81,635 @@ reg = <0x80000000 0>; }; + soc: soc { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + rpm: rpm@108000 { + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = , + , + ; + interrupt-names = "ack", + "err", + "wakeup"; + }; + + ssbi: ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + qfprom: efuse@700000 { + compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_calib: calib@404 { + reg = <0x404 0x10>; + }; + + tsens_backup: backup-calib@414 { + reg = <0x414 0x10>; + }; + }; + + tlmm: pinctrl@800000 { + compatible = "qcom,msm8960-pinctrl"; + reg = <0x800000 0x4000>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 152>; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + i2c1_default_state: i2c1-default-state { + i2c1-pins { + pins = "gpio8", "gpio9"; + function = "gsbi1"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c1_sleep_state: i2c1-sleep-state { + i2c1-pins { + pins = "gpio8", "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c3_default_state: i2c3-default-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c3_sleep_state: i2c3-sleep-state { + i2c3-pins { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c8_default_state: i2c8-default-state { + i2c8-pins { + pins = "gpio36", "gpio37"; + function = "gsbi8"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c8_sleep_state: i2c8-sleep-state { + i2c8-pins { + pins = "gpio36", "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c10_default_state: i2c10-default-state { + i2c10-pins { + pins = "gpio73", "gpio74"; + function = "gsbi10"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c10_sleep_state: i2c10-sleep-state { + i2c10-pins { + pins = "gpio73", "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + i2c12_default_state: i2c12-default-state { + i2c12-pins { + pins = "gpio44", "gpio45"; + function = "gsbi12"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c12_sleep_state: i2c12-sleep-state { + i2c12-pins { + pins = "gpio44", "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + sdcc3_default_state: sdcc3-default-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdcc3_sleep_state: sdcc3-sleep-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-msm8960", "syscon"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&cxo_board>, + <&pxo_board>, + <&lcc PLL4>; + clock-names = "cxo", + "pxo", + "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer@200a000 { + compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; + reg = <0x0200a000 0x100>; + interrupts = , + , + ; + clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; + cpu-offset = <0x80000>; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + + saw0: power-manager@2089000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; + }; + + saw1: power-manager@2099000 { + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; + + clock-controller@4000000 { + compatible = "qcom,mmcc-msm8960"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; + }; + + sdcc3: mmc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x12180000 0x2000>; + arm,primecell-periphid = <0x00051180>; + interrupts = ; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x4000>; + interrupts = ; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc1: mmc@12400000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x12400000 0x2000>; + arm,primecell-periphid = <0x00051180>; + interrupts = ; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x4000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + gsbi12: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12480000 0x100>; + ranges; + cell-index = <12>; + clocks = <&gcc GSBI12_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi12_i2c: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + pinctrl-0 = <&i2c12_default_state>; + pinctrl-1 = <&i2c12_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI12_QUP_CLK>, + <&gcc GSBI12_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + usb1: usb@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x200>, + <0x12500200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS1_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs1_phy>; + phy-names = "usb-phy"; + #reset-cells = <1>; + + status = "disabled"; + + ulpi { + usb_hs1_phy: phy { + compatible = "qcom,usb-hs-phy-msm8960", + "qcom,usb-hs-phy"; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb1 0>; + reset-names = "por"; + #phy-cells = <0>; + }; + }; + }; + + gsbi1: gsbi@16000000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16000000 0x100>; + ranges; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi1_i2c: i2c@16080000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + pinctrl-0 = <&i2c1_default_state>; + pinctrl-1 = <&i2c1_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + gsbi1_spi: spi@16080000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x16080000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + cs-gpios = <&tlmm 8 0>; + clocks = <&gcc GSBI1_QUP_CLK>, + <&gcc GSBI1_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16200000 0x100>; + ranges; + cell-index = <3>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi3_i2c: i2c@16280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16280000 0x1000>; + pinctrl-0 = <&i2c3_default_state>; + pinctrl-1 = <&i2c3_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI3_QUP_CLK>, + <&gcc GSBI3_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16400000 0x100>; + ranges; + cell-index = <5>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI5_UART_CLK>, + <&gcc GSBI5_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + + gsbi8: gsbi@1a000000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a000000 0x100>; + ranges; + cell-index = <8>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi8_serial: serial@1a040000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a040000 0x1000>, + <0x1a000000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI8_UART_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + + gsbi8_i2c: i2c@1a080000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a080000 0x1000>; + pinctrl-0 = <&i2c8_default_state>; + pinctrl-1 = <&i2c8_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI8_QUP_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gsbi10: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a200000 0x100>; + ranges; + cell-index = <10>; + clocks = <&gcc GSBI10_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi10_i2c: i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + pinctrl-0 = <&i2c10_default_state>; + pinctrl-1 = <&i2c10_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI10_QUP_CLK>, + <&gcc GSBI10_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-msm8960", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-msm8960"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; + }; + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; @@ -94,35 +752,6 @@ }; }; - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - qcom,no-pc-write; - }; - - clocks { - cxo_board: cxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "cxo_board"; - }; - - pxo_board: pxo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "pxo_board"; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; @@ -131,395 +760,4 @@ regulator-max-microvolt = <2700000>; regulator-always-on; }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts = , - , - ; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>; - clocks = <&sleep_clk>; - clock-names = "sleep"; - cpu-offset = <0x80000>; - }; - - qfprom: efuse@700000 { - compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - tsens_calib: calib@404 { - reg = <0x404 0x10>; - }; - - tsens_backup: backup-calib@414 { - reg = <0x414 0x10>; - }; - }; - - msmgpio: pinctrl@800000 { - compatible = "qcom,msm8960-pinctrl"; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 152>; - #gpio-cells = <2>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960", "syscon"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - clocks = <&cxo_board>, - <&pxo_board>, - <&lcc PLL4>; - clock-names = "cxo", "pxo", "pll4"; - - tsens: thermal-sensor { - compatible = "qcom,msm8960-tsens"; - - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - interrupts = ; - interrupt-names = "uplow"; - - #qcom,sensors = <5>; - #thermal-sensor-cells = <1>; - }; - }; - - lcc: clock-controller@28000000 { - compatible = "qcom,lcc-msm8960"; - reg = <0x28000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL4_VOTE>, - <0>, - <0>, <0>, - <0>, <0>, - <0>; - clock-names = "pxo", - "pll4_vote", - "mi2s_codec_clk", - "codec_i2s_mic_codec_clk", - "spare_i2s_mic_codec_clk", - "codec_i2s_spkr_codec_clk", - "spare_i2s_spkr_codec_clk", - "pcm_codec_clk"; - }; - - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - clocks = <&pxo_board>, - <&gcc PLL3>, - <&gcc PLL8_VOTE>, - <0>, - <0>, - <0>, - <0>, - <0>; - clock-names = "pxo", - "pll3", - "pll8_vote", - "dsi1pll", - "dsi1pllbyte", - "dsi2pll", - "dsi2pllbyte", - "hdmipll"; - }; - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - #clock-cells = <0>; - }; - - rpm: rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; - - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - #clock-cells = <0>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu1_aux"; - #clock-cells = <0>; - }; - - saw0: power-manager@2089000 { - compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - - saw0_vreg: regulator { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - }; - }; - - saw1: power-manager@2099000 { - compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - - saw1_vreg: regulator { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - }; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <5>; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi5_serial: serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - gsbi8: gsbi@1a000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <8>; - reg = <0x1a000000 0x100>; - clocks = <&gcc GSBI8_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon-tcsr = <&tcsr>; - - status = "disabled"; - - gsbi8_serial: serial@1a040000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a040000 0x1000>, - <0x1a000000 0x1000>; - interrupts = ; - clocks = <&gcc GSBI8_UART_CLK>, - <&gcc GSBI8_H_CLK>; - clock-names = "core", - "iface"; - - status = "disabled"; - }; - }; - - ssbi: ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3bam: dma-controller@12182000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x4000>; - interrupts = ; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc1bam: dma-controller@12402000 { - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x4000>; - interrupts = ; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,tcsr-msm8960", "syscon"; - reg = <0x1a400000 0x100>; - }; - - gsbi1: gsbi@16000000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <1>; - reg = <0x16000000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - status = "disabled"; - - gsbi1_spi: spi@16080000 { - compatible = "qcom,spi-qup-v1.1.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x16080000 0x1000>; - interrupts = ; - cs-gpios = <&msmgpio 8 0>; - - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - usb1: usb@12500000 { - compatible = "qcom,ci-hdrc"; - reg = <0x12500000 0x200>, - <0x12500200 0x200>; - interrupts = ; - clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; - clock-names = "core", "iface"; - assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; - assigned-clock-rates = <60000000>; - resets = <&gcc USB_HS1_RESET>; - reset-names = "core"; - phy_type = "ulpi"; - ahb-burst-config = <0>; - phys = <&usb_hs1_phy>; - phy-names = "usb-phy"; - #reset-cells = <1>; - status = "disabled"; - - ulpi { - usb_hs1_phy: phy { - compatible = "qcom,usb-hs-phy-msm8960", - "qcom,usb-hs-phy"; - clocks = <&sleep_clk>, <&cxo_board>; - clock-names = "sleep", "ref"; - resets = <&usb1 0>; - reset-names = "por"; - #phy-cells = <0>; - }; - }; - }; - - gsbi3: gsbi@16200000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x16200000 0x100>; - ranges; - cell-index = <3>; - clocks = <&gcc GSBI3_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - - gsbi3_i2c: i2c@16280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16280000 0x1000>; - pinctrl-0 = <&i2c3_default_state>; - pinctrl-1 = <&i2c3_sleep_state>; - pinctrl-names = "default", "sleep"; - interrupts = ; - clocks = <&gcc GSBI3_QUP_CLK>, - <&gcc GSBI3_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - }; }; -#include "qcom-msm8960-pins.dtsi" diff --git a/dts/upstream/src/arm/renesas/r7s72100.dtsi b/dts/upstream/src/arm/renesas/r7s72100.dtsi index a1e4e9ac8f6..245c26bb8e0 100644 --- a/dts/upstream/src/arm/renesas/r7s72100.dtsi +++ b/dts/upstream/src/arm/renesas/r7s72100.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r7s72100"; #address-cells = <1>; #size-cells = <1>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -84,7 +85,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; rtc_x1_clk: rtc_x1 { @@ -103,7 +104,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/upstream/src/arm/renesas/r7s9210.dtsi b/dts/upstream/src/arm/renesas/r7s9210.dtsi index fdeb0bc12cb..2b349b51003 100644 --- a/dts/upstream/src/arm/renesas/r7s9210.dtsi +++ b/dts/upstream/src/arm/renesas/r7s9210.dtsi @@ -52,7 +52,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/upstream/src/arm/renesas/r8a7742.dtsi b/dts/upstream/src/arm/renesas/r8a7742.dtsi index 9083d288cc3..4220b2349b4 100644 --- a/dts/upstream/src/arm/renesas/r8a7742.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7742.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7742"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -208,19 +209,19 @@ pmu-0 { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; pmu-1 { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; @@ -234,7 +235,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1932,10 +1932,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a7743.dtsi b/dts/upstream/src/arm/renesas/r8a7743.dtsi index 58a06cf3778..c697942387e 100644 --- a/dts/upstream/src/arm/renesas/r8a7743.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7743.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7743"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -115,8 +116,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -130,7 +131,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1841,10 +1841,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a7744.dtsi b/dts/upstream/src/arm/renesas/r8a7744.dtsi index 034244648d1..fed46345807 100644 --- a/dts/upstream/src/arm/renesas/r8a7744.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7744.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7744"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -115,8 +116,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -130,7 +131,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1827,10 +1827,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a7745.dtsi b/dts/upstream/src/arm/renesas/r8a7745.dtsi index 704fa6f3cbd..5424a73562d 100644 --- a/dts/upstream/src/arm/renesas/r8a7745.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7745.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7745"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -105,8 +106,8 @@ pmu { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -120,7 +121,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1631,10 +1631,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a77470.dtsi b/dts/upstream/src/arm/renesas/r8a77470.dtsi index a8a12275c98..c61790e7667 100644 --- a/dts/upstream/src/arm/renesas/r8a77470.dtsi +++ b/dts/upstream/src/arm/renesas/r8a77470.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a77470"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -66,8 +67,8 @@ pmu { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -81,7 +82,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -1057,10 +1057,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a7790.dtsi b/dts/upstream/src/arm/renesas/r8a7790.dtsi index 4f97c09dbc9..12cce9bdc44 100644 --- a/dts/upstream/src/arm/renesas/r8a7790.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7790.dtsi @@ -16,6 +16,7 @@ compatible = "renesas,r8a7790"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -239,19 +240,19 @@ pmu-0 { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; pmu-1 { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; @@ -265,7 +266,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -2012,10 +2012,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts b/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts index e9f90fa44d5..61ea438eb6a 100644 --- a/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts +++ b/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts @@ -301,6 +301,16 @@ clock-frequency = <12000000>; }; + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -383,13 +393,25 @@ }; composite-in@20 { - compatible = "adi,adv7180"; + compatible = "adi,adv7180cp"; reg = <0x20>; - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + adv7180_out: endpoint { + remote-endpoint = <&vin1ep>; + }; }; }; }; @@ -900,7 +922,7 @@ port { vin1ep: endpoint { - remote-endpoint = <&adv7180>; + remote-endpoint = <&adv7180_out>; bus-width = <8>; }; }; diff --git a/dts/upstream/src/arm/renesas/r8a7791.dtsi b/dts/upstream/src/arm/renesas/r8a7791.dtsi index 5023b41c28b..35313e8da42 100644 --- a/dts/upstream/src/arm/renesas/r8a7791.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7791.dtsi @@ -16,6 +16,7 @@ compatible = "renesas,r8a7791"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -137,8 +138,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -152,7 +153,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -1939,10 +1939,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a7792.dtsi b/dts/upstream/src/arm/renesas/r8a7792.dtsi index 7513afc1c95..9e0de69ac3a 100644 --- a/dts/upstream/src/arm/renesas/r8a7792.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7792.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7792"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -94,8 +95,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -109,7 +110,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -992,10 +992,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/dts/upstream/src/arm/renesas/r8a7793-gose.dts b/dts/upstream/src/arm/renesas/r8a7793-gose.dts index 45b267ec267..5c6928c941a 100644 --- a/dts/upstream/src/arm/renesas/r8a7793-gose.dts +++ b/dts/upstream/src/arm/renesas/r8a7793-gose.dts @@ -373,7 +373,6 @@ port@3 { reg = <3>; adv7180_out: endpoint { - bus-width = <8>; remote-endpoint = <&vin1ep>; }; }; diff --git a/dts/upstream/src/arm/renesas/r8a7793.dtsi b/dts/upstream/src/arm/renesas/r8a7793.dtsi index fc6d3bcca29..1ad50070a1a 100644 --- a/dts/upstream/src/arm/renesas/r8a7793.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7793.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a7793"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -122,8 +123,8 @@ pmu { compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -137,7 +138,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -1518,10 +1518,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r8a7794.dtsi b/dts/upstream/src/arm/renesas/r8a7794.dtsi index 92010d09f6c..7669a67377c 100644 --- a/dts/upstream/src/arm/renesas/r8a7794.dtsi +++ b/dts/upstream/src/arm/renesas/r8a7794.dtsi @@ -15,6 +15,7 @@ compatible = "renesas,r8a7794"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { i2c0 = &i2c0; @@ -104,8 +105,8 @@ pmu { compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&cpu0>, <&cpu1>; }; @@ -119,7 +120,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -1485,10 +1485,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm/renesas/r9a06g032-rzn1d400-db.dts b/dts/upstream/src/arm/renesas/r9a06g032-rzn1d400-db.dts index 3258b2e2743..4a72aa7663f 100644 --- a/dts/upstream/src/arm/renesas/r9a06g032-rzn1d400-db.dts +++ b/dts/upstream/src/arm/renesas/r9a06g032-rzn1d400-db.dts @@ -308,8 +308,6 @@ &switch { status = "okay"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; diff --git a/dts/upstream/src/arm/renesas/r9a06g032.dtsi b/dts/upstream/src/arm/renesas/r9a06g032.dtsi index 13a60656b04..8debb77803b 100644 --- a/dts/upstream/src/arm/renesas/r9a06g032.dtsi +++ b/dts/upstream/src/arm/renesas/r9a06g032.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r9a06g032"; #address-cells = <1>; #size-cells = <1>; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -63,7 +64,6 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&gic>; ranges; rtc0: rtc@40006000 { @@ -290,6 +290,16 @@ status = "disabled"; }; + adc: adc@40065000 { + compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc"; + reg = <0x40065000 0x200>; + clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; + clock-names = "pclk", "adc"; + power-domains = <&sysctrl>; + #io-channel-cells = <1>; + status = "disabled"; + }; + pinctrl: pinctrl@40067000 { compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; reg = <0x40067000 0x1000>, <0x51000000 0x480>; @@ -522,7 +532,6 @@ timer { compatible = "arm,armv7-timer"; - interrupt-parent = <&gic>; arm,cpu-registers-not-fw-configured; always-on; interrupts = diff --git a/dts/upstream/src/arm/renesas/sh73a0-kzm9g.dts b/dts/upstream/src/arm/renesas/sh73a0-kzm9g.dts index 1ce07d0878d..0a9cd61bcb5 100644 --- a/dts/upstream/src/arm/renesas/sh73a0-kzm9g.dts +++ b/dts/upstream/src/arm/renesas/sh73a0-kzm9g.dts @@ -209,6 +209,7 @@ reg = <0x1d>; interrupts-extended = <&irqpin3 2 IRQ_TYPE_LEVEL_HIGH>, <&irqpin3 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1", "INT2"; }; rtc@32 { diff --git a/dts/upstream/src/arm/rockchip/rk3066a-bqcurie2.dts b/dts/upstream/src/arm/rockchip/rk3066a-bqcurie2.dts index c227691013e..65f8bc804d2 100644 --- a/dts/upstream/src/arm/rockchip/rk3066a-bqcurie2.dts +++ b/dts/upstream/src/arm/rockchip/rk3066a-bqcurie2.dts @@ -80,26 +80,33 @@ clock-frequency = <400000>; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + vcc5-supply = <&vcc_io>; vcc6-supply = <&vcc_io>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -107,7 +114,7 @@ regulator-always-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -115,42 +122,42 @@ regulator-always-on; }; - vcc18_cif: regulator@5 { + vcc18_cif: vdig1 { regulator-name = "vcc18_cif"; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-always-on; }; - vcc_18: regulator@8 { + vcc_18: vdac { regulator-name = "vcc_18"; regulator-always-on; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-always-on; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-always-on; }; - vcc_tp: regulator@11 { + vcc_tp: vaux33 { regulator-name = "vcc_tp"; regulator-always-on; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-always-on; }; @@ -158,9 +165,6 @@ }; }; -/* must be included after &tps gets defined */ -#include "../tps65910.dtsi" - &mmc0 { /* sdmmc */ status = "okay"; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm/rockchip/rk3066a-marsboard.dts b/dts/upstream/src/arm/rockchip/rk3066a-marsboard.dts index de42d185512..15dbe1677e3 100644 --- a/dts/upstream/src/arm/rockchip/rk3066a-marsboard.dts +++ b/dts/upstream/src/arm/rockchip/rk3066a-marsboard.dts @@ -96,11 +96,18 @@ clock-frequency = <400000>; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + vcc1-supply = <&vsys>; vcc2-supply = <&vsys>; vcc3-supply = <&vsys>; @@ -111,17 +118,17 @@ vccio-supply = <&vsys>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -129,7 +136,7 @@ regulator-always-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -137,41 +144,41 @@ regulator-always-on; }; - vcc18_cif: regulator@5 { + vcc18_cif: vdig1 { regulator-name = "vcc18_cif"; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-always-on; }; - vcc_18: regulator@8 { + vcc_18: vdac { regulator-name = "vcc_18"; regulator-always-on; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-always-on; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-always-on; }; - vcc_rmii: regulator@11 { + vcc_rmii: vaux33 { regulator-name = "vcc_rmii"; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-always-on; }; @@ -179,9 +186,6 @@ }; }; -/* must be included after &tps gets defined */ -#include "../tps65910.dtsi" - &emac { phy = <&phy0>; phy-supply = <&vcc_rmii>; diff --git a/dts/upstream/src/arm/rockchip/rk3066a-rayeager.dts b/dts/upstream/src/arm/rockchip/rk3066a-rayeager.dts index b0b029f1464..07c03ed6fac 100644 --- a/dts/upstream/src/arm/rockchip/rk3066a-rayeager.dts +++ b/dts/upstream/src/arm/rockchip/rk3066a-rayeager.dts @@ -198,9 +198,18 @@ status = "okay"; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; pinctrl-0 = <&pmic_int>, <&pwr_hold>; @@ -214,19 +223,19 @@ vccio-supply = <&vsys>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -234,7 +243,7 @@ regulator-boot-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -242,52 +251,52 @@ regulator-boot-on; }; - vcc18: regulator@5 { + vcc18: vdig1 { regulator-name = "vcc18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - vccio_wl: regulator@8 { + vccio_wl: vdac { regulator-name = "vccio_wl"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_rmii: regulator@11 { + vcc_rmii: vaux33 { regulator-name = "vcc_rmii"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -296,8 +305,6 @@ }; }; -#include "../tps65910.dtsi" - &i2c2 { status = "okay"; }; diff --git a/dts/upstream/src/arm/rockchip/rk3288-veyron.dtsi b/dts/upstream/src/arm/rockchip/rk3288-veyron.dtsi index 260d6c92cfd..2d6cf08d00f 100644 --- a/dts/upstream/src/arm/rockchip/rk3288-veyron.dtsi +++ b/dts/upstream/src/arm/rockchip/rk3288-veyron.dtsi @@ -388,7 +388,7 @@ rx-sample-delay-ns = <12>; - flash@0 { + spi_flash: flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/dts/upstream/src/arm/rockchip/rk3288.dtsi b/dts/upstream/src/arm/rockchip/rk3288.dtsi index 42d705b544e..7477fc5da3e 100644 --- a/dts/upstream/src/arm/rockchip/rk3288.dtsi +++ b/dts/upstream/src/arm/rockchip/rk3288.dtsi @@ -34,10 +34,6 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -745,9 +741,6 @@ #address-cells = <1>; #size-cells = <0>; - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - /* * Note: Although SCLK_* are the working clocks * of device without including on the NOC, needed for @@ -1197,6 +1190,8 @@ compatible = "rockchip,rk3288-dp"; reg = <0x0 0xff970000 0x0 0x4000>; interrupts = ; + assigned-clocks = <&cru SCLK_EDP_24M>; + assigned-clock-parents = <&xin24m>; clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; phys = <&edp_phy>; diff --git a/dts/upstream/src/arm/samsung/exynos4210-i9100.dts b/dts/upstream/src/arm/samsung/exynos4210-i9100.dts index df229fb8a16..8a635bee59f 100644 --- a/dts/upstream/src/arm/samsung/exynos4210-i9100.dts +++ b/dts/upstream/src/arm/samsung/exynos4210-i9100.dts @@ -853,6 +853,7 @@ #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; vmmc-supply = <&vtf_reg>; diff --git a/dts/upstream/src/arm/samsung/exynos4210-trats.dts b/dts/upstream/src/arm/samsung/exynos4210-trats.dts index 95e0e01b6ff..6bd902cb8f4 100644 --- a/dts/upstream/src/arm/samsung/exynos4210-trats.dts +++ b/dts/upstream/src/arm/samsung/exynos4210-trats.dts @@ -518,6 +518,7 @@ #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; vmmc-supply = <&tflash_reg>; diff --git a/dts/upstream/src/arm/samsung/exynos4210-universal_c210.dts b/dts/upstream/src/arm/samsung/exynos4210-universal_c210.dts index bdc30f8cf74..91490693432 100644 --- a/dts/upstream/src/arm/samsung/exynos4210-universal_c210.dts +++ b/dts/upstream/src/arm/samsung/exynos4210-universal_c210.dts @@ -610,6 +610,7 @@ #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; vmmc-supply = <&ldo5_reg>; diff --git a/dts/upstream/src/arm/samsung/exynos4412-midas.dtsi b/dts/upstream/src/arm/samsung/exynos4412-midas.dtsi index 05ddddb565e..48245b1665a 100644 --- a/dts/upstream/src/arm/samsung/exynos4412-midas.dtsi +++ b/dts/upstream/src/arm/samsung/exynos4412-midas.dtsi @@ -1440,6 +1440,7 @@ #address-cells = <1>; #size-cells = <0>; non-removable; + cap-power-off-card; bus-width = <4>; mmc-pwrseq = <&wlan_pwrseq>; diff --git a/dts/upstream/src/arm/st/stih410.dtsi b/dts/upstream/src/arm/st/stih410.dtsi index d56343f44fd..07da9b48cca 100644 --- a/dts/upstream/src/arm/st/stih410.dtsi +++ b/dts/upstream/src/arm/st/stih410.dtsi @@ -34,6 +34,41 @@ status = "disabled"; }; + display-subsystem { + compatible = "st,sti-display-subsystem"; + ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>; + + assigned-clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>; + + assigned-clock-parents = <0>, + <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 0>; + + assigned-clock-rates = <297000000>, + <297000000>, + <0>, + <400000000>, + <400000000>; + }; + soc { ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; @@ -99,153 +134,176 @@ status = "disabled"; }; - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; + compositor: display-controller@9d11000 { + compatible = "st,stih407-compositor"; + reg = <0x9d11000 0x1000>; - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; + clock-names = "compo_main", + "compo_aux", + "pix_main", + "pix_aux", + "pix_gdp1", + "pix_gdp2", + "pix_gdp3", + "pix_gdp4", + "main_parent", + "aux_parent"; - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, + clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, + <&clk_s_d2_flexgen CLK_PIX_GDP1>, + <&clk_s_d2_flexgen CLK_PIX_GDP2>, + <&clk_s_d2_flexgen CLK_PIX_GDP3>, + <&clk_s_d2_flexgen CLK_PIX_GDP4>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; + + reset-names = "compo-main", "compo-aux"; + resets = <&softreset STIH407_COMPO_SOFTRESET>, + <&softreset STIH407_COMPO_SOFTRESET>; + st,vtg = <&vtg_main>, <&vtg_aux>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + compo_main_out: endpoint { + remote-endpoint = <&tvout_in0>; + }; + }; + + port@1 { + reg = <1>; + compo_aux_out: endpoint { + remote-endpoint = <&tvout_in1>; + }; + }; + }; + }; + + tvout: encoder@8d08000 { + compatible = "st,stih407-tvout"; + reg = <0x8d08000 0x1000>; + reg-names = "tvout-reg"; + reset-names = "tvout"; + resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; + assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>; + + assigned-clock-parents = <&clk_s_d2_quadfs 0>, + <&clk_tmdsout_hdmi>, <&clk_s_d2_quadfs 0>, + <&clk_s_d0_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, - <297000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; + ports { #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; + #size-cells = <0>; - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; + port@0 { + reg = <0>; + tvout_in0: endpoint { + remote-endpoint = <&compo_main_out>; + }; + }; + + port@1 { + reg = <1>; + tvout_in1: endpoint { + remote-endpoint = <&compo_aux_out>; + }; + }; + + port@2 { + reg = <2>; + tvout_out0: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + + port@3 { + reg = <3>; + tvout_out1: endpoint { + remote-endpoint = <&hda_in>; + }; + }; }; + }; - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; + sti_hdmi: hdmi@8d04000 { + compatible = "st,stih407-hdmi"; + reg = <0x8d04000 0x1000>; + reg-names = "hdmi-reg"; + #sound-dai-cells = <0>; + interrupts = ; + interrupt-names = "irq"; + clock-names = "pix", + "tmds", + "phy", + "audio", + "main_parent", + "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; + clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, + <&clk_s_d0_flexgen CLK_PCM_0>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; + reset-names = "hdmi"; + resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; + ddc = <&hdmiddc>; + + port { + hdmi_in: endpoint { + remote-endpoint = <&tvout_out0>; + }; }; + }; - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - status = "disabled"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; + analog@8d02000 { + compatible = "st,stih407-hda"; + status = "disabled"; + reg = <0x8d02000 0x400>, <0x92b0120 0x4>; + reg-names = "hda-reg", "video-dacs-ctrl"; + clock-names = "pix", + "hddac", + "main_parent", + "aux_parent"; + clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, + <&clk_s_d2_flexgen CLK_HDDAC>, + <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>; - sti-hqvdp@9c00000 { - compatible = "st,stih407-hqvdp"; - reg = <0x9C00000 0x100000>; - clock-names = "hqvdp", "pix_main"; - clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; - reset-names = "hqvdp"; - resets = <&softreset STIH407_HDQVDP_SOFTRESET>; - st,vtg = <&vtg_main>; + port { + hda_in: endpoint { + remote-endpoint = <&tvout_out1>; + }; }; }; + hqvdp: plane@9c00000 { + compatible = "st,stih407-hqvdp"; + reg = <0x9C00000 0x100000>; + clock-names = "hqvdp", "pix_main"; + clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; + reset-names = "hqvdp"; + resets = <&softreset STIH407_HDQVDP_SOFTRESET>; + st,vtg = <&vtg_main>; + }; + bdisp0:bdisp@9f10000 { compatible = "st,stih407-bdisp"; reg = <0x9f10000 0x1000>; diff --git a/dts/upstream/src/arm/st/stm32mp131.dtsi b/dts/upstream/src/arm/st/stm32mp131.dtsi index fd730aa37c2..b9657ff91c2 100644 --- a/dts/upstream/src/arm/st/stm32mp131.dtsi +++ b/dts/upstream/src/arm/st/stm32mp131.dtsi @@ -29,6 +29,12 @@ interrupt-parent = <&intc>; }; + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + firmware { optee { method = "smc"; @@ -1000,6 +1006,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; + interrupts = ; clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; @@ -1657,6 +1664,16 @@ reg = <1>; }; }; + + iwdg1: watchdog@5c003000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5c003000 0x400>; + interrupts = ; + clocks = <&rcc IWDG1>, <&scmi_clk CK_SCMI_LSI>; + clock-names = "pclk", "lsi"; + access-controllers = <&etzpc 12>; + status = "disabled"; + }; }; /* diff --git a/dts/upstream/src/arm/st/stm32mp135f-dk.dts b/dts/upstream/src/arm/st/stm32mp135f-dk.dts index 9764a6bfa5b..f894ee35b3d 100644 --- a/dts/upstream/src/arm/st/stm32mp135f-dk.dts +++ b/dts/upstream/src/arm/st/stm32mp135f-dk.dts @@ -161,6 +161,11 @@ }; }; +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + &crc1 { status = "okay"; }; diff --git a/dts/upstream/src/arm/st/stm32mp153c-lxa-fairytux2.dtsi b/dts/upstream/src/arm/st/stm32mp153c-lxa-fairytux2.dtsi index 9eeb9d6b5eb..7d3a6a3b5d0 100644 --- a/dts/upstream/src/arm/st/stm32mp153c-lxa-fairytux2.dtsi +++ b/dts/upstream/src/arm/st/stm32mp153c-lxa-fairytux2.dtsi @@ -374,9 +374,6 @@ baseboard_eeprom: &sip_eeprom { phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; - vusb_d-supply = <&vdd_usb>; - vusb_a-supply = <®18>; - status = "okay"; }; diff --git a/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi b/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi index bf0c32027ba..370b2afbf15 100644 --- a/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi +++ b/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi @@ -185,13 +185,13 @@ interrupt-parent = <&gpioi>; vio-supply = <&v3v3>; vcc-supply = <&v3v3>; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; touchscreen { compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; st,ave-ctrl = <1>; st,touch-det-delay = <2>; st,settling = <2>; diff --git a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi index 154698f87b0..ab13f0c3989 100644 --- a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi +++ b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi @@ -493,9 +493,6 @@ baseboard_eeprom: &sip_eeprom { phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; - vusb_d-supply = <&vdd_usb>; - vusb_a-supply = <®18>; - g-rx-fifo-size = <512>; g-np-tx-fifo-size = <32>; g-tx-fifo-size = <128 128 64 16 16 16 16 16>; diff --git a/dts/upstream/src/arm/ti/omap/am335x-baltos-leds.dtsi b/dts/upstream/src/arm/ti/omap/am335x-baltos-leds.dtsi index 049fd8e1b40..ed194469973 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-baltos-leds.dtsi +++ b/dts/upstream/src/arm/ti/omap/am335x-baltos-leds.dtsi @@ -17,18 +17,18 @@ compatible = "gpio-leds"; - led-power { + led_power: led-power { label = "onrisc:red:power"; linux,default-trigger = "default-on"; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; default-state = "on"; }; - led-wlan { + led_wlan: led-wlan { label = "onrisc:blue:wlan"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led-app { + led_app: led-app { label = "onrisc:green:app"; gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/dts/upstream/src/arm/ti/omap/am335x-baltos.dtsi b/dts/upstream/src/arm/ti/omap/am335x-baltos.dtsi index ea47f9960c3..afb38f023b8 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-baltos.dtsi +++ b/dts/upstream/src/arm/ti/omap/am335x-baltos.dtsi @@ -45,6 +45,23 @@ startup-delay-us = <70000>; enable-active-high; }; + + mpcie_regulator: mpcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "mpcie-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 4 0>; + enable-active-high; + regulator-boot-on; + }; + + mpcie_power_switch: mpcie-power-switch { + compatible = "regulator-output"; + regulator-name = "mpcie-power-switch"; + regulator-supplies = "vcc"; + vout-supply = <&mpcie_regulator>; + }; }; &am33xx_pinmux { diff --git a/dts/upstream/src/arm/ti/omap/am335x-bone-common.dtsi b/dts/upstream/src/arm/ti/omap/am335x-bone-common.dtsi index ad1e60a9b6f..1d83fc116b6 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-bone-common.dtsi +++ b/dts/upstream/src/arm/ti/omap/am335x-bone-common.dtsi @@ -16,7 +16,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { @@ -217,7 +217,7 @@ }; baseboard_eeprom: eeprom@50 { - compatible = "atmel,24c256"; + compatible = "atmel,24c32"; reg = <0x50>; vcc-supply = <&ldo4_reg>; diff --git a/dts/upstream/src/arm/ti/omap/am335x-boneblue.dts b/dts/upstream/src/arm/ti/omap/am335x-boneblue.dts index f579df4c2c5..d430f0bef16 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-boneblue.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-boneblue.dts @@ -13,7 +13,7 @@ compatible = "ti,am335x-bone-blue", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/dts/upstream/src/arm/ti/omap/am335x-chiliboard.dts b/dts/upstream/src/arm/ti/omap/am335x-chiliboard.dts index 648e97fe1df..ae5bc589849 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-chiliboard.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-chiliboard.dts @@ -12,7 +12,7 @@ "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/dts/upstream/src/arm/ti/omap/am335x-evm.dts b/dts/upstream/src/arm/ti/omap/am335x-evm.dts index 20222f82f21..856fa1191ed 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-evm.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-evm.dts @@ -23,7 +23,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; vbat: fixedregulator0 { diff --git a/dts/upstream/src/arm/ti/omap/am335x-evmsk.dts b/dts/upstream/src/arm/ti/omap/am335x-evmsk.dts index eba888dcd60..d8baccdf8bc 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-evmsk.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-evmsk.dts @@ -30,7 +30,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; vbat: fixedregulator0 { diff --git a/dts/upstream/src/arm/ti/omap/am335x-guardian.dts b/dts/upstream/src/arm/ti/omap/am335x-guardian.dts index 4b070e634b2..6ce3a2d029e 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-guardian.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-guardian.dts @@ -14,7 +14,7 @@ compatible = "bosch,am335x-guardian", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; tick-timer = &timer2; }; diff --git a/dts/upstream/src/arm/ti/omap/am335x-icev2.dts b/dts/upstream/src/arm/ti/omap/am335x-icev2.dts index 6f0f4fba043..ba488bba692 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-icev2.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-icev2.dts @@ -22,7 +22,7 @@ }; chosen { - stdout-path = &uart3; + stdout-path = "serial3:115200n8"; }; vbat: fixedregulator0 { diff --git a/dts/upstream/src/arm/ti/omap/am335x-mba335x.dts b/dts/upstream/src/arm/ti/omap/am335x-mba335x.dts new file mode 100644 index 00000000000..8c0b2a1c99b --- /dev/null +++ b/dts/upstream/src/arm/ti/omap/am335x-mba335x.dts @@ -0,0 +1,633 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2025 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Authors: Gregor Herburger, Matthias Schiffer + * + * Based on: + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include +#include +#include "am335x-tqma335x.dtsi" + +/ { + model = "TQ-Systems TQMa335x[L] SoM on MBa335x carrier board"; + compatible = "tq,tqma3359-mba335x", "tq,tqma3359", "ti,am33xx"; + chassis-type = "embedded"; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 58 61 66 75 90 125 170 255>; + default-brightness-level = <7>; + enable-gpios = <&expander1 4 GPIO_ACTIVE_HIGH>; + power-supply = <®_mba335x_12v>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-s5 { + label = "S5"; + linux,code = ; + gpios = <&expander2 0 GPIO_ACTIVE_LOW>; + }; + + button-s6 { + label = "S6"; + linux,code = ; + gpios = <&expander2 1 GPIO_ACTIVE_LOW>; + }; + + button-s7 { + label = "S7"; + linux,code = ; + gpios = <&expander2 2 GPIO_ACTIVE_LOW>; + }; + }; + + reg_mba335x_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "MBa335x-V12"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "tqm-tlv320aic32"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Line", "Line Out", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Line Out", "LOL", + "Line Out", "LOR", + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "Line In", "IN1_L", + "Line In", "IN1_R"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + #sound-dai-cells = <0>; + system-clock-direction-out; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic32x4>; + system-clock-frequency = <24000000>; + system-clock-direction-out; + }; + }; +}; + +&am33xx_pinmux { + codec_pins: codec-pins { + pinctrl-single,pins = < + /* xdma_event_intr0.clkout1 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) + >; + }; + + cpsw_default_pins: cpsw-default-pins { + pinctrl-single,pins = < + /* Port 1 */ + /* mii1_tx_en.rgmii1_tctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rx_dv.rgmii1_rctl */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd3.rgmii1_td3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd2.rgmii1_td2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd1.rgmii1_td1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_txd0.rgmii1_td0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_tx_clk.rgmii1_tclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* mii1_rx_clk.rgmii1_rclk */ + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd3.rgmii1_rd3 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd2.rgmii1_rd2 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd1.rgmii1_rd1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* mii1_rxd0.rgmii1_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) + + /* Port 2 */ + /* gpmc_a0.rgmii2_tctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a1.rgmii2_rctl */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a2.rgmii2_td3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a3.rgmii2_td2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a4.rgmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a5.rgmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a6.rgmii2_tclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a7.rgmii2_rclk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a8.rgmii2_rd3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a9.rgmii2_rd2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a10.rgmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) + /* gpmc_a11.rgmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) + >; + }; + + cpsw_sleep_pins: cpsw-sleep-pins { + pinctrl-single,pins = < + /* Port 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) + + /* Port 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) + >; + }; + + davinci_mdio_default_pins: davinci_mdio-default-pins { + pinctrl-single,pins = < + /* mdio.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + /* mdc.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + davinci_mdio_sleep_pins: davinci_mdio-sleep-pins { + pinctrl-single,pins = < + /* mdio.mdio_data */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP, MUX_MODE7) + /* mdc.mdio_clk */ + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + davinci_mdio_phy0_pins: davinci_mdio-phy0-pins { + pinctrl-single,pins = < + /* usb0_drvvbus.gpio0_18 - PHY interrupt */ + AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_INPUT, MUX_MODE7) + >; + }; + + davinci_mdio_phy1_pins: davinci_mdio-phy1-pins { + pinctrl-single,pins = < + /* gpmc_csn0.gpio1_29 - PHY interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7) + >; + }; + + dcan0_pins: dcan0-pins { + pinctrl-single,pins = < + /* uart1_ctsn.d_can0_tx */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* uart1_rtsn.d_can0_rx */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + dcan1_pins: dcan1-pins { + pinctrl-single,pins = < + /* uart0_ctsn.d_can1_tx */ + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + /* uart0_rtsn.d_can1_rx */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + ecap2_pins: ecap2-pins { + pinctrl-single,pins = < + /* mcasp0_ahclkr.ecap2_in_pwm2_out */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE4) + >; + }; + + expander1_pins: expander1-pins { + pinctrl-single,pins = < + /* gpmc_csn3.gpio2_0 - interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE7 ) + >; + }; + + expander2_pins: expander2-pins { + pinctrl-single,pins = < + /* gpmc_ben1.gpio1_28 - interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + i2c1_pins: i2c1-pins { + pinctrl-single,pins = < + /* uart1_rxd.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE3) + /* uart1_txd.i2c1_scl */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE3) + >; + }; + + lcd_pins: lcd-pins { + pinctrl-single,pins = < + /* gpmc_ad8.lcd_data23 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad9.lcd_data22 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad10.lcd_data21 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad11.lcd_data20 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad12.lcd_data19 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad13.lcd_data18 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad14.lcd_data17 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) + /* gpmc_ad15.lcd_data16 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) + /* lcd_data0.lcd_data0 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + /* lcd_data1.lcd_data1 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + /* lcd_data2.lcd_data2 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + /* lcd_data3.lcd_data3 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + /* lcd_data4.lcd_data4 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + /* lcd_data5.lcd_data5 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + /* lcd_data6.lcd_data6 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + /* lcd_data7.lcd_data7 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + /* lcd_data8.lcd_data8 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + /* lcd_data9.lcd_data9 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + /* lcd_data10.lcd_data10 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + /* lcd_data11.lcd_data11 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + /* lcd_data12.lcd_data12 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + /* lcd_data13.lcd_data13 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + /* lcd_data14.lcd_data14 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + /* lcd_data15.lcd_data15 */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + /* lcd_vsync.lcd_vsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + /* lcd_hsync.lcd_hsync */ + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + /* lcd_pclk.lcd_pclk */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + /* lcd_ac_bias_en.lcd_ac_bias_en */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_aclkx.mcasp0_aclkx*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_axr1.mcasp0_axr1 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_aclkr.mcasp0_aclkr */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* mcasp0_fsr.mcasp0_fsr */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT_PULLDOWN, MUX_MODE0) + >; + }; + + mmc1_pins: mmc1-pins { + pinctrl-single,pins = < + /* mmc0_dat3.mmc0_dat3 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat2.mmc0_dat2 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat1.mmc0_dat1 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_dat0.mmc0_dat0 */ + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_clk.mmc0_clk */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + /* mmc0_cmd.mmc0_cmd */ + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + polytouch_pins: polytouch-pins { + pinctrl-single,pins = < + /* gpmc_clk.gpio2_1 - touch interrupt */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + uart0_pins: uart0-pins { + pinctrl-single,pins = < + /* uart0_rxd.uart0_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + /* uart0_txd.uart0_txd */ + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart3_pins: uart3-pins { + pinctrl-single,pins = < + /* spi0_cs1.uart3_rxd */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) + /* ecap0_in_pwm0_out.uart3_txd */ + AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + >; + }; + + uart4_pins: uart4-pins { + pinctrl-single,pins = < + /* gpmc_wait0.uart4_rxd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) + /* gpmc_wpn.uart4_txd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) + >; + }; +}; + +&cpsw_port1 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + ti,dual-emac-pvid = <2>; +}; + +&davinci_mdio_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default_pins>; + pinctrl-1 = <&davinci_mdio_sleep_pins>; + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_phy0_pins>; + interrupt-parent = <&gpio0>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-ps = <1860>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_phy1_pins>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + rxc-skew-ps = <1860>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; +}; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +&ds1339 { + interrupt-parent = <&expander2>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; +}; + +&ecap2 { + pinctrl-names = "default"; + pinctrl-0 = <&ecap2_pins>; +}; + +&i2c0 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&codec_pins>; + clocks = <&clk_24mhz>; + clock-names = "mclk"; + iov-supply = <&vcc3v3>; + ldoin-supply = <&vcc3v3>; + #sound-dai-cells = <0>; + }; + + jc42_2: temperature-sensor@19 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander1: gpio@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&expander1_pins>; + vcc-supply = <&vcc3v3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + + expander2: gpio@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&expander2_pins>; + vcc-supply = <&vcc3v3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom3: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + vcc-supply = <&vcc3v3>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +&lcdc { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + blue-and-red-wiring = "crossed"; +}; + +&mac_sw { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default_pins>; + pinctrl-1 = <&cpsw_sleep_pins>; + status = "okay"; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + #sound-dai-cells = <0>; + op-mode = <0>; + tdm-slots = <2>; + /* 16 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 2 1 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&tps { + interrupt-parent = <&expander2>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1 { + /* Should be "otg", but role switching currently doesn't work */ + dr_mode = "peripheral"; +}; + +/* SOM supply */ +&vcc3v3in { + vin-supply = <&vcc3v3>; +}; diff --git a/dts/upstream/src/arm/ti/omap/am335x-myirtech-myd.dts b/dts/upstream/src/arm/ti/omap/am335x-myirtech-myd.dts index 06a352f98b2..476a6bdaf43 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-myirtech-myd.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-myirtech-myd.dts @@ -15,7 +15,7 @@ compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; clk12m: clk12m { diff --git a/dts/upstream/src/arm/ti/omap/am335x-netcom-plus-2xx.dts b/dts/upstream/src/arm/ti/omap/am335x-netcom-plus-2xx.dts index f66d57bb685..f0519ab3014 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-netcom-plus-2xx.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-netcom-plus-2xx.dts @@ -222,10 +222,10 @@ "ModeA1", "ModeA2", "ModeA3", - "NC", - "NC", - "NC", - "NC", + "ModeB0", + "ModeB1", + "ModeB2", + "ModeB3", "NC", "NC", "NC", diff --git a/dts/upstream/src/arm/ti/omap/am335x-osd3358-sm-red.dts b/dts/upstream/src/arm/ti/omap/am335x-osd3358-sm-red.dts index d28d3972884..23caaaabf35 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-osd3358-sm-red.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-osd3358-sm-red.dts @@ -147,7 +147,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts b/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts index c9ccb9de21a..9f611debc20 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts @@ -21,7 +21,7 @@ compatible = "ti,am33xx"; chosen { - stdout-path = &uart3; + stdout-path = "serial3:115200n8"; }; cpus { diff --git a/dts/upstream/src/arm/ti/omap/am335x-pepper.dts b/dts/upstream/src/arm/ti/omap/am335x-pepper.dts index e7d561a527f..10d54e0ad15 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-pepper.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-pepper.dts @@ -347,7 +347,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wireless_pins>; - vmmmc-supply = <&v3v3c_reg>; + vmmc-supply = <&v3v3c_reg>; bus-width = <4>; non-removable; dmas = <&edma_xbar 12 0 1 diff --git a/dts/upstream/src/arm/ti/omap/am335x-pocketbeagle.dts b/dts/upstream/src/arm/ti/omap/am335x-pocketbeagle.dts index 78ce860e59b..24d9f90fad0 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-pocketbeagle.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-pocketbeagle.dts @@ -15,7 +15,7 @@ compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/dts/upstream/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts b/dts/upstream/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts index 7c9f65126c6..8b47f45a995 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-sancloud-bbe-extended-wifi.dts @@ -87,7 +87,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins>; diff --git a/dts/upstream/src/arm/ti/omap/am335x-sl50.dts b/dts/upstream/src/arm/ti/omap/am335x-sl50.dts index f3524e5ee43..1dc4e344efd 100644 --- a/dts/upstream/src/arm/ti/omap/am335x-sl50.dts +++ b/dts/upstream/src/arm/ti/omap/am335x-sl50.dts @@ -25,7 +25,7 @@ }; chosen { - stdout-path = &uart0; + stdout-path = "serial0:115200n8"; }; leds { diff --git a/dts/upstream/src/arm/ti/omap/am335x-tqma335x.dtsi b/dts/upstream/src/arm/ti/omap/am335x-tqma335x.dtsi new file mode 100644 index 00000000000..b75949f0f02 --- /dev/null +++ b/dts/upstream/src/arm/ti/omap/am335x-tqma335x.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2025 TQ-Systems GmbH , D-82229 Seefeld, Germany. + * Authors: Gregor Herburger, Matthias Schiffer + * + * Based on: + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include "am33xx.dtsi" + +/ { + compatible = "tq,tqma3359", "ti,am33xx"; + + aliases { + mmc0 = &mmc2; + mmc1 = &mmc1; + /delete-property/ mmc2; + rtc0 = &tps; + rtc1 = &ds1339; + rtc2 = &rtc; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* SOM input voltage */ + vcc3v3in: regulator-vcc3v3in { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3IN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* + * Regulator is enabled by PMIC power sequence. The supplied voltage + * rail is also usable on baseboard. + */ + vddshv: regulator-vddshv { + compatible = "regulator-fixed"; + regulator-name = "VDDSHV"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc3v3in>; + }; +}; + +&am33xx_pinmux { + i2c0_pins: i2c0-pins { + pinctrl-single,pins = < + /* i2c0_sda.i2c0_sda */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + /* i2c0_scl.i2c0_scl */ + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc2_pins: mmc2-pins { + pinctrl-single,pins = < + /* gpmc_ad0.mmc1_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad1.mmc1_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad2.mmc1_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad3.mmc1_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad4.mmc1_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad5.mmc1_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad6.mmc1_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_ad7.mmc1_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE1) + /* gpmc_csn1.mmc1_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) + /* gpmc_csn2.mmc1_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, SLEWCTRL_SLOW | PIN_INPUT_PULLUP, MUX_MODE2) + >; + }; + + spi0_pins: spi0-pins { + pinctrl-single,pins = < + /* spi0_sclk.spi0_sclk */ + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) + /* spi0_d0.spi0_d0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) + /* spi0_d1.spi0_d1 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE0) + /* spi0_cs0.spi0_cs0 */ + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) + >; + }; +}; + +&cpu { + cpu0-supply = <&vdd1_reg>; +}; + +&elm { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + /* optional, not on TQMa335xL */ + jc42_1: temperature-sensor@1f { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1f>; + }; + + tps: pmic@2d { + reg = <0x2d>; + ti,en-ck32k-xtal; + /* Filled in by tps65910.dtsi */ + }; + + /* optional, not on TQMa335xL */ + eeprom: eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&vddshv>; + }; + + /* optional, not on TQMa335xL */ + se97btp: eeprom@57 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + vcc-supply = <&vddshv>; + }; + + /* optional, not on TQMa335xL */ + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +#include "../../tps65910.dtsi" + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + bus-width = <8>; + no-1-8-v; + no-sd; + no-sdio; + vmmc-supply = <&vddshv>; + non-removable; + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&tps { + vcc1-supply = <&vcc3v3in>; + vcc2-supply = <&vcc3v3in>; + vcc3-supply = <&vcc3v3in>; + vcc4-supply = <&vcc3v3in>; + vcc5-supply = <&vcc3v3in>; + vcc6-supply = <&vcc3v3in>; + vcc7-supply = <&vcc3v3in>; + vccio-supply = <&vcc3v3in>; +}; + +/* TPS outputs */ +&vrtc_reg { + regulator-always-on; +}; + +&vio_reg { + regulator-always-on; +}; + +&vdd1_reg { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; +}; + +&vdd2_reg { + regulator-name = "vdd_core"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; +}; + +&vdd3_reg { + regulator-always-on; +}; + +&vdig1_reg { + regulator-always-on; +}; + +&vdig2_reg { + regulator-always-on; +}; + +&vpll_reg { + regulator-always-on; +}; + +&vdac_reg { + regulator-always-on; +}; + +&vaux1_reg { + regulator-always-on; +}; + +&vaux2_reg { + regulator-always-on; +}; + +&vaux33_reg { + regulator-always-on; +}; + +&vmmc_reg { + regulator-always-on; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <24000000>; + vcc-supply = <&vddshv>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&usb0_phy { + vcc-supply = <&vaux1_reg>; +}; + +&usb1_phy { + vcc-supply = <&vaux1_reg>; +}; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/dts/upstream/src/arm/ti/omap/am33xx-l4.dtsi b/dts/upstream/src/arm/ti/omap/am33xx-l4.dtsi index 18ad52e9395..89d16fcc773 100644 --- a/dts/upstream/src/arm/ti/omap/am33xx-l4.dtsi +++ b/dts/upstream/src/arm/ti/omap/am33xx-l4.dtsi @@ -1501,7 +1501,6 @@ mmc1: mmc@0 { compatible = "ti,am335-sdhci"; - ti,needs-special-reset; dmas = <&edma 24 0>, <&edma 25 0>; dma-names = "tx", "rx"; interrupts = <64>; @@ -1987,7 +1986,6 @@ mmc2: mmc@0 { compatible = "ti,am335-sdhci"; - ti,needs-special-reset; dmas = <&edma 2 0 &edma 3 0>; dma-names = "tx", "rx"; diff --git a/dts/upstream/src/arm/ti/omap/am33xx.dtsi b/dts/upstream/src/arm/ti/omap/am33xx.dtsi index 43ec2a95f4b..ca3e7f5d7d0 100644 --- a/dts/upstream/src/arm/ti/omap/am33xx.dtsi +++ b/dts/upstream/src/arm/ti/omap/am33xx.dtsi @@ -45,7 +45,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu: cpu@0 { compatible = "arm,cortex-a8"; enable-method = "ti,am3352"; device_type = "cpu"; @@ -338,7 +338,6 @@ mmc3: mmc@0 { compatible = "ti,am335-sdhci"; - ti,needs-special-reset; interrupts = <29>; reg = <0x0 0x1000>; status = "disabled"; diff --git a/dts/upstream/src/arm/ti/omap/am4372.dtsi b/dts/upstream/src/arm/ti/omap/am4372.dtsi index 0a1df30f281..504fa6b57d3 100644 --- a/dts/upstream/src/arm/ti/omap/am4372.dtsi +++ b/dts/upstream/src/arm/ti/omap/am4372.dtsi @@ -321,7 +321,6 @@ mmc3: mmc@0 { compatible = "ti,am437-sdhci"; - ti,needs-special-reset; interrupts = ; reg = <0x0 0x1000>; status = "disabled"; diff --git a/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi b/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi index fd4634f8c62..e08f356e71c 100644 --- a/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi +++ b/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi @@ -1103,7 +1103,6 @@ mmc1: mmc@0 { compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; - ti,needs-special-reset; dmas = <&edma 24 0>, <&edma 25 0>; dma-names = "tx", "rx"; @@ -1620,7 +1619,6 @@ mmc2: mmc@0 { compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; - ti,needs-special-reset; dmas = <&edma 2 0>, <&edma 3 0>; dma-names = "tx", "rx"; diff --git a/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts b/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts index e6a18954e44..43cf4ade950 100644 --- a/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts +++ b/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts @@ -545,7 +545,6 @@ non-removable; mmc-pwrseq = <&emmc_pwrseq>; - ti,needs-special-reset; dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; dma-names = "tx", "rx"; @@ -561,7 +560,6 @@ /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ status = "okay"; - ti,needs-special-reset; vmmc-supply = <&vdd_3v3>; cap-power-off-card; keep-power-in-suspend; diff --git a/dts/upstream/src/arm/ti/omap/am57xx-cl-som-am57x.dts b/dts/upstream/src/arm/ti/omap/am57xx-cl-som-am57x.dts index 3dd898955e7..77c9fbb3bfb 100644 --- a/dts/upstream/src/arm/ti/omap/am57xx-cl-som-am57x.dts +++ b/dts/upstream/src/arm/ti/omap/am57xx-cl-som-am57x.dts @@ -481,7 +481,6 @@ vmmc-supply = <&vdd_3v3>; bus-width = <8>; ti,non-removable; - cap-mmc-dual-data-rate; }; &qspi { diff --git a/dts/upstream/src/arm/ti/omap/omap3-beagle-xm.dts b/dts/upstream/src/arm/ti/omap/omap3-beagle-xm.dts index 08ee0f8ea68..71b39a923d3 100644 --- a/dts/upstream/src/arm/ti/omap/omap3-beagle-xm.dts +++ b/dts/upstream/src/arm/ti/omap/omap3-beagle-xm.dts @@ -291,7 +291,7 @@ }; twl_power: power { - compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; + compatible = "ti,twl4030-power-idle-osc-off"; ti,use_poweroff; }; }; diff --git a/dts/upstream/src/arm/ti/omap/omap3-n900.dts b/dts/upstream/src/arm/ti/omap/omap3-n900.dts index c50ca572d1b..7db73d9bed9 100644 --- a/dts/upstream/src/arm/ti/omap/omap3-n900.dts +++ b/dts/upstream/src/arm/ti/omap/omap3-n900.dts @@ -508,7 +508,7 @@ }; twl_power: power { - compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off"; + compatible = "ti,twl4030-power-idle-osc-off"; ti,use_poweroff; }; }; diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi index ceedae9e399..8d1110c14ba 100644 --- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi @@ -304,6 +304,42 @@ bias-pull-up; }; + /omit-if-no-ref/ + nand_pins: nand-pins { + pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "nand0"; + }; + + /omit-if-no-ref/ + nand_cs0_pin: nand-cs0-pin { + pins = "PC4"; + function = "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_cs1_pin: nand-cs1-pin { + pins = "PC3"; + function = "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_rb0_pin: nand-rb0-pin { + pins = "PC6"; + function = "nand0"; + bias-pull-up; + }; + + /omit-if-no-ref/ + nand_rb1_pin: nand-rb1-pin { + pins = "PC7"; + function = "nand0"; + bias-pull-up; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins = "PC0", "PC2", "PC4"; @@ -377,6 +413,22 @@ #iommu-cells = <1>; }; + nfc: nand-controller@4011000 { + compatible = "allwinner,sun50i-h616-nand-controller"; + reg = <0x04011000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; + clock-names = "ahb", "mod", "ecc", "mbus"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + dmas = <&dma 10>; + dma-names = "rxtx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun50i-h616-mmc", "allwinner,sun50i-a100-mmc"; diff --git a/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi b/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi index 7b36c47a3a1..42dab01e3f5 100644 --- a/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi +++ b/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi @@ -145,6 +145,14 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + i2s2_pi_pins: i2s2-pi-pins { + pins = "PI2", "PI3", "PI4", "PI5"; + allwinner,pinmux = <5>; + function = "i2s2"; + bias-disable; + }; + mmc0_pins: mmc0-pins { pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,pinmux = <2>; @@ -182,6 +190,30 @@ bias-disable; }; + rgmii1_pins: rgmii1-pins { + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux = <5>; + function = "gmac1"; + drive-strength = <40>; + bias-disable; + }; + + /omit-if-no-ref/ + spdif_out_pb_pin: spdif-pb-pin { + pins = "PB8"; + function = "spdif"; + allwinner,pinmux = <2>; + }; + + /omit-if-no-ref/ + spdif_out_pi_pin: spdif-pi-pin { + pins = "PI10"; + function = "spdif"; + allwinner,pinmux = <2>; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; allwinner,pinmux = <2>; @@ -231,6 +263,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -242,6 +276,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -253,6 +289,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -264,6 +302,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -275,6 +315,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -286,6 +328,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART5>; resets = <&ccu RST_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -297,6 +341,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART6>; resets = <&ccu RST_BUS_UART6>; + dmas = <&dma 20>, <&dma 20>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -308,6 +354,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART7>; resets = <&ccu RST_BUS_UART7>; + dmas = <&dma 21>, <&dma 21>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -319,6 +367,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -332,6 +382,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -345,6 +397,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -358,6 +412,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -371,6 +427,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C4>; resets = <&ccu RST_BUS_I2C4>; + dmas = <&dma 47>, <&dma 47>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -384,6 +442,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C5>; resets = <&ccu RST_BUS_I2C5>; + dmas = <&dma 48>, <&dma 48>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -398,6 +458,19 @@ ranges; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun55i-a523-dma", + "allwinner,sun50i-a100-dma"; + reg = <0x03002000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <54>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun55i-a523-sid", "allwinner,sun50i-a64-sid"; @@ -603,6 +676,51 @@ }; }; + gmac1: ethernet@4510000 { + compatible = "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg = <0x04510000 0x10000>; + clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names = "stmmaceth", "mbus"; + resets = <&ccu RST_BUS_EMAC1>; + reset-names = "stmmaceth"; + interrupts = ; + interrupt-names = "macirq"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins>; + power-domains = <&pck600 PD_VO1>; + syscon = <&syscon>; + snps,fixed-burst; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible = "allwinner,sun55i-a523-ppu"; reg = <0x07001400 0x400>; @@ -674,6 +792,8 @@ reg = <0x07081400 0x400>; interrupts = ; clocks = <&r_ccu CLK_BUS_R_I2C0>; + dmas = <&dma 49>, <&dma 49>; + dma-names = "rx", "tx"; resets = <&r_ccu RST_BUS_R_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&r_i2c_pins>; @@ -720,6 +840,90 @@ #reset-cells = <1>; }; + i2s0: i2s@7112000 { + compatible = "allwinner,sun55i-a523-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x07112000 0x1000>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_I2S0>, <&mcu_ccu CLK_MCU_I2S0>; + clock-names = "apb", "mod"; + resets = <&mcu_ccu RST_BUS_MCU_I2S0>; + dmas = <&mcu_dma 3>, <&mcu_dma 3>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@7113000 { + compatible = "allwinner,sun55i-a523-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x07113000 0x1000>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_I2S1>, <&mcu_ccu CLK_MCU_I2S1>; + clock-names = "apb", "mod"; + resets = <&mcu_ccu RST_BUS_MCU_I2S1>; + dmas = <&mcu_dma 4>, <&mcu_dma 4>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2: i2s@7114000 { + compatible = "allwinner,sun55i-a523-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x07114000 0x1000>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_I2S2>, <&mcu_ccu CLK_MCU_I2S2>; + clock-names = "apb", "mod"; + resets = <&mcu_ccu RST_BUS_MCU_I2S2>; + dmas = <&mcu_dma 5>, <&mcu_dma 5>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3: i2s@7115000 { + compatible = "allwinner,sun55i-a523-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x07115000 0x1000>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_I2S3>, <&mcu_ccu CLK_MCU_I2S3>; + clock-names = "apb", "mod"; + resets = <&mcu_ccu RST_BUS_MCU_I2S3>; + dmas = <&mcu_dma 6>, <&mcu_dma 6>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif: spdif@7116000 { + compatible = "allwinner,sun55i-a523-spdif"; + reg = <0x07116000 0x400>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_SPDIF>, + <&mcu_ccu CLK_MCU_SPDIF_TX>, + <&mcu_ccu CLK_MCU_SPDIF_RX>; + clock-names = "apb", "tx", "rx"; + resets = <&mcu_ccu RST_BUS_MCU_SPDIF>; + dmas = <&mcu_dma 2>, <&mcu_dma 2>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + mcu_dma: dma-controller@7121000 { + compatible = "allwinner,sun55i-a523-mcu-dma", + "allwinner,sun50i-a100-dma"; + reg = <0x07121000 0x1000>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_DMA>, <&mcu_ccu CLK_MCU_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <15>; + resets = <&mcu_ccu RST_BUS_MCU_DMA>; + #dma-cells = <1>; + }; + npu: npu@7122000 { compatible = "vivante,gc"; reg = <0x07122000 0x1000>; diff --git a/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts b/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts index f82a8d12169..bfdf1728cd1 100644 --- a/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts +++ b/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ aliases { ethernet0 = &gmac0; + ethernet1 = &gmac1; serial0 = &uart0; }; @@ -75,7 +76,7 @@ &gmac0 { phy-mode = "rgmii-id"; - phy-handle = <&ext_rgmii_phy>; + phy-handle = <&ext_rgmii0_phy>; phy-supply = <®_cldo3>; allwinner,tx-delay-ps = <300>; @@ -84,13 +85,24 @@ status = "okay"; }; +&gmac1 { + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii1_phy>; + phy-supply = <®_cldo4>; + + tx-internal-delay-ps = <300>; + rx-internal-delay-ps = <400>; + + status = "okay"; +}; + &gpu { mali-supply = <®_dcdc2>; status = "okay"; }; &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -99,6 +111,16 @@ }; }; +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo3>; cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -250,6 +272,8 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay = <150000>; }; reg_cpusldo: cpusldo { diff --git a/dts/upstream/src/arm64/allwinner/sun55i-t527-avaota-a1.dts b/dts/upstream/src/arm64/allwinner/sun55i-t527-avaota-a1.dts index 1b054fa8ef7..054d0357c13 100644 --- a/dts/upstream/src/arm64/allwinner/sun55i-t527-avaota-a1.dts +++ b/dts/upstream/src/arm64/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gmac0; + ethernet1 = &gmac1; serial0 = &uart0; }; @@ -73,7 +74,7 @@ &gmac0 { phy-mode = "rgmii-id"; - phy-handle = <&ext_rgmii_phy>; + phy-handle = <&ext_rgmii0_phy>; phy-supply = <®_dcdc4>; allwinner,tx-delay-ps = <100>; @@ -82,13 +83,24 @@ status = "okay"; }; +&gmac1 { + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii1_phy>; + phy-supply = <®_dcdc4>; + + tx-internal-delay-ps = <100>; + rx-internal-delay-ps = <100>; + + status = "okay"; +}; + &gpu { mali-supply = <®_dcdc2>; status = "okay"; }; &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -97,6 +109,16 @@ }; }; +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo3>; cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ diff --git a/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts b/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts index 39a4e194712..9e6b21cf293 100644 --- a/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts +++ b/dts/upstream/src/arm64/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ compatible = "xunlong,orangepi-4a", "allwinner,sun55i-t527"; aliases { + ethernet0 = &gmac1; serial0 = &uart0; }; @@ -102,11 +103,33 @@ status = "okay"; }; +&gmac1 { + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_cldo4>; + + tx-internal-delay-ps = <0>; + rx-internal-delay-ps = <300>; + + status = "okay"; +}; + &gpu { mali-supply = <®_dcdc2>; status = "okay"; }; +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupts-extended = <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo3>; cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi b/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi index effd242f6bf..657e986e5db 100644 --- a/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi +++ b/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi @@ -630,6 +630,15 @@ interrupts = <5 4>; }; + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 4>, + <15 4>; + }; + }; qspi: spi@ff8d2000 { diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts index 4eee777ef1a..58f776e411f 100644 --- a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts +++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts @@ -50,19 +50,6 @@ regulator-min-microvolt = <330000>; regulator-max-microvolt = <330000>; }; - - soc@0 { - eccmgr { - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - }; }; &pinctrl0 { @@ -190,6 +177,8 @@ cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts index 7c53cb9621e..92954c5beb5 100644 --- a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts +++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts @@ -50,19 +50,6 @@ regulator-min-microvolt = <330000>; regulator-max-microvolt = <330000>; }; - - soc@0 { - eccmgr { - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - }; }; &gpio1 { diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts index ad52e8a0b9b..5ba6ca4ef19 100644 --- a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts +++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts @@ -62,7 +62,6 @@ &gmac0 { status = "okay"; phy-mode = "rgmii"; - phy-addr = <0xffffffff>; }; &gmac1 { @@ -73,7 +72,6 @@ &gmac2 { status = "okay"; phy-mode = "rgmii"; - phy-addr = <0xffffffff>; }; &mmc { @@ -104,5 +102,4 @@ &sysmgr { reg = <0xffd12000 0x1000>; - interrupts = <0x0 0x10 0x4>; }; diff --git a/dts/upstream/src/arm64/amlogic/amlogic-a5.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-a5.dtsi index b1da8cbaa25..2b12d828459 100644 --- a/dts/upstream/src/arm64/amlogic/amlogic-a5.dtsi +++ b/dts/upstream/src/arm64/amlogic/amlogic-a5.dtsi @@ -5,6 +5,7 @@ #include "amlogic-a4-common.dtsi" #include "amlogic-a5-reset.h" +#include #include / { cpus { @@ -58,6 +59,95 @@ #reset-cells = <1>; }; + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,pinctrl-a5", + "amlogic,pinctrl-a4"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x300>; + + gpioz: gpio@c0 { + reg = <0x0 0xc0 0x0 0x40>, + <0x0 0x18 0x0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; + }; + + gpiox: gpio@100 { + reg = <0x0 0x100 0x0 0x40>, + <0x0 0xc 0x0 0xc>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; + }; + + gpiot: gpio@140 { + reg = <0x0 0x140 0x0 0x40>, + <0x0 0x2c 0x0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 14>; + }; + + gpiod: gpio@180 { + reg = <0x0 0x180 0x0 0x40>, + <0x0 0x40 0x0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>; + }; + + gpioe: gpio@1c0 { + reg = <0x0 0x1c0 0x0 0x40>, + <0x0 0x48 0x0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; + }; + + gpioc: gpio@200 { + reg = <0x0 0x200 0x0 0x40>, + <0x0 0x24 0x0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 11>; + }; + + gpiob: gpio@240 { + reg = <0x0 0x240 0x0 0x40>, + <0x0 0x0 0x0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpioh: gpio@280 { + reg = <0x0 0x280 0x0 0x40>, + <0x0 0x4c 0x0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 5>; + }; + + gpio_test_n: gpio@2c0 { + reg = <0x0 0x2c0 0x0 0x40>, + <0x0 0x3c 0x0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + }; + gpio_intc: interrupt-controller@4080 { compatible = "amlogic,a5-gpio-intc", "amlogic,meson-gpio-intc"; diff --git a/dts/upstream/src/arm64/amlogic/amlogic-c3-c308l-aw419.dts b/dts/upstream/src/arm64/amlogic/amlogic-c3-c308l-aw419.dts index 45f8631f9fe..e026604c55e 100644 --- a/dts/upstream/src/arm64/amlogic/amlogic-c3-c308l-aw419.dts +++ b/dts/upstream/src/arm64/amlogic/amlogic-c3-c308l-aw419.dts @@ -17,6 +17,7 @@ aliases { serial0 = &uart_b; spi0 = &spifc; + i2c2 = &i2c2; }; memory@0 { @@ -146,6 +147,36 @@ regulator-boot-on; regulator-always-on; }; + + camera_vdddo_1v8: regulator-camera-1v8 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDDO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-boot-on; + regulator-always-on; + }; + + camera_vdda_2v9: regulator-camera-2v9 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDA"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + vin-supply = <&vcc_5v>; + regulator-boot-on; + regulator-always-on; + }; + + camera_vddd_1v2: regulator-camera-1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAMERA_VDDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3>; + regulator-boot-on; + regulator-always-on; + }; }; &uart_b { @@ -258,3 +289,56 @@ vmmc-supply = <&sdcard>; vqmmc-supply = <&sdcard>; }; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins1>; + clock-frequency = <100000>; /* default 100k */ + + imx290: sensor0@1a { + compatible = "sony,imx290"; + reg = <0x1a>; + clocks = <&clkc_pll CLKID_MCLK0>; + clock-names = "xclk"; + clock-frequency = <37125000>; + assigned-clocks = <&clkc_pll CLKID_MCLK_PLL>, + <&clkc_pll CLKID_MCLK0>; + assigned-clock-rates = <74250000>, <37125000>; + + vdddo-supply = <&camera_vdddo_1v8>; + vdda-supply = <&camera_vdda_2v9>; + vddd-supply = <&camera_vddd_1v2>; + + reset-gpios = <&gpio GPIOE_4 GPIO_ACTIVE_LOW>; + + port { + imx290_out: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <222750000 148500000>; + remote-endpoint = <&c3_mipi_csi_in>; + }; + }; + }; +}; + +&csi2 { + status = "okay"; + + ports { + port@0 { + c3_mipi_csi_in: endpoint { + remote-endpoint = <&imx290_out>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&adap { + status = "okay"; +}; + +&isp { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi index 07aaaf71ea9..13b7ac03f9b 100644 --- a/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi +++ b/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi @@ -1031,5 +1031,93 @@ #size-cells = <0>; }; }; + + csi2: csi2@ff018000 { + compatible = "amlogic,c3-mipi-csi2"; + reg = <0x0 0xff018000 0x0 0x100>, + <0x0 0xff019000 0x0 0x300>, + <0x0 0xff01a000 0x0 0x100>; + reg-names = "aphy", "dphy", "host"; + power-domains = <&pwrc PWRC_C3_MIPI_ISP_WRAP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + clock-names = "vapb", "phy0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_CSI_PHY0>; + assigned-clock-rates = <0>, <200000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + c3_mipi_csi_out: endpoint { + remote-endpoint = <&c3_adap_in>; + }; + }; + }; + }; + + adap: adap@ff010000 { + compatible = "amlogic,c3-mipi-adapter"; + reg = <0x0 0xff010000 0x0 0x100>, + <0x0 0xff01b000 0x0 0x100>, + <0x0 0xff01d000 0x0 0x200>; + reg-names = "top", "fd", "rd"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + c3_adap_in: endpoint { + remote-endpoint = <&c3_mipi_csi_out>; + }; + }; + + port@1 { + reg = <1>; + c3_adap_out: endpoint { + remote-endpoint = <&c3_isp_in>; + }; + }; + }; + }; + + isp: isp@ff000000 { + compatible = "amlogic,c3-isp"; + reg = <0x0 0xff000000 0x0 0xf000>; + reg-names = "isp"; + power-domains = <&pwrc PWRC_C3_ISP_TOP_ID>; + clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + clock-names = "vapb", "isp0"; + assigned-clocks = <&clkc_periphs CLKID_VAPB>, + <&clkc_periphs CLKID_ISP0>; + assigned-clock-rates = <0>, <400000000>; + interrupts = ; + status = "disabled"; + + port { + c3_isp_in: endpoint { + remote-endpoint = <&c3_adap_out>; + }; + }; + }; }; }; diff --git a/dts/upstream/src/arm64/amlogic/amlogic-s6.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-s6.dtsi index 5f602f1170c..8ef63193903 100644 --- a/dts/upstream/src/arm64/amlogic/amlogic-s6.dtsi +++ b/dts/upstream/src/arm64/amlogic/amlogic-s6.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { cpus { #address-cells = <2>; @@ -41,6 +42,15 @@ }; }; + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,s6-pwrc"; + #power-domain-cells = <1>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -189,6 +199,24 @@ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; }; }; + + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,s6-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + + ao-secure@10220 { + compatible = "amlogic,s6-ao-secure", + "amlogic,meson-gx-ao-secure", + "syscon"; + reg = <0x0 0x10220 0x0 0x140>; + amlogic,has-chip-id; + }; }; }; }; diff --git a/dts/upstream/src/arm64/amlogic/amlogic-s7.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-s7.dtsi index d262c0b66e4..a3faf4d188e 100644 --- a/dts/upstream/src/arm64/amlogic/amlogic-s7.dtsi +++ b/dts/upstream/src/arm64/amlogic/amlogic-s7.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { cpus { @@ -79,6 +80,15 @@ }; }; + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,s7-pwrc"; + #power-domain-cells = <1>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -211,6 +221,24 @@ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; }; }; + + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,s7-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + + ao-secure@10220 { + compatible = "amlogic,s7-ao-secure", + "amlogic,meson-gx-ao-secure", + "syscon"; + reg = <0x0 0x10220 0x0 0x140>; + amlogic,has-chip-id; + }; }; }; }; diff --git a/dts/upstream/src/arm64/amlogic/amlogic-s7d.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-s7d.dtsi index c4d260d5bb5..0c4417bcd68 100644 --- a/dts/upstream/src/arm64/amlogic/amlogic-s7d.dtsi +++ b/dts/upstream/src/arm64/amlogic/amlogic-s7d.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { cpus { @@ -43,6 +44,15 @@ }; + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,s7d-pwrc"; + #power-domain-cells = <1>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -184,6 +194,24 @@ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; }; }; + + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,s7d-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + + ao-secure@10220 { + compatible = "amlogic,s7d-ao-secure", + "amlogic,meson-gx-ao-secure", + "syscon"; + reg = <0x0 0x10220 0x0 0x140>; + amlogic,has-chip-id; + }; }; }; }; diff --git a/dts/upstream/src/arm64/amlogic/meson-axg.dtsi b/dts/upstream/src/arm64/amlogic/meson-axg.dtsi index 04fb130ac7c..e95c9189496 100644 --- a/dts/upstream/src/arm64/amlogic/meson-axg.dtsi +++ b/dts/upstream/src/arm64/amlogic/meson-axg.dtsi @@ -208,7 +208,7 @@ reg = <0x0 0xf9800000 0x0 0x400000>, <0x0 0xff646000 0x0 0x2000>, <0x0 0xf9f00000 0x0 0x100000>; - reg-names = "elbi", "cfg", "config"; + reg-names = "dbi", "cfg", "config"; interrupts = ; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; @@ -234,7 +234,7 @@ reg = <0x0 0xfa000000 0x0 0x400000>, <0x0 0xff648000 0x0 0x2000>, <0x0 0xfa400000 0x0 0x100000>; - reg-names = "elbi", "cfg", "config"; + reg-names = "dbi", "cfg", "config"; interrupts = ; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; diff --git a/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi index dcc927a9da8..ca455f63483 100644 --- a/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi +++ b/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi @@ -138,7 +138,7 @@ reg = <0x0 0xfc000000 0x0 0x400000>, <0x0 0xff648000 0x0 0x2000>, <0x0 0xfc400000 0x0 0x200000>; - reg-names = "elbi", "cfg", "config"; + reg-names = "dbi", "cfg", "config"; interrupts = ; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12b.dtsi index f04efa82825..23358d94844 100644 --- a/dts/upstream/src/arm64/amlogic/meson-g12b.dtsi +++ b/dts/upstream/src/arm64/amlogic/meson-g12b.dtsi @@ -87,7 +87,7 @@ i-cache-line-size = <32>; i-cache-size = <0x8000>; i-cache-sets = <32>; - next-level-cache = <&l2_cache_l>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; @@ -103,7 +103,7 @@ i-cache-line-size = <32>; i-cache-size = <0x8000>; i-cache-sets = <32>; - next-level-cache = <&l2_cache_l>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; diff --git a/dts/upstream/src/arm64/amlogic/meson-gxm-tx9-pro.dts b/dts/upstream/src/arm64/amlogic/meson-gxm-tx9-pro.dts new file mode 100644 index 00000000000..9a62176cfe5 --- /dev/null +++ b/dts/upstream/src/arm64/amlogic/meson-gxm-tx9-pro.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + */ + +/dts-v1/; + +#include "meson-gxm.dtsi" +#include "meson-gx-p23x-q20x.dtsi" +#include + +/ { + compatible = "oranth,tx9-pro", "amlogic,s912", "amlogic,meson-gxm"; + model = "Tanix TX9 Pro"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "Update"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + phy-mode = "rgmii"; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_15 */ + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ir { + linux,rc-map-name = "rc-tanix-tx3mini"; +}; + +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; diff --git a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b-base.dtsi similarity index 100% rename from dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts rename to dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b-base.dtsi diff --git a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts index 3e0319fdb93..28560828144 100644 --- a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts +++ b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts @@ -1,22 +1,16 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make - * the RP1 driver to load the RP1 dtb overlay at runtime, while - * bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it - * already contains RP1 node, so no overlay is loaded nor needed). - * This file is intended to host the override nodes for the RP1 peripherals, - * e.g. to declare the phy of the ethernet interface or the custom pin setup - * for several RP1 peripherals. - * This in turn is due to the fact that there's no current generic - * infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that - * are not yet defined in the DT since they are loaded at runtime via overlay. + * As a loose attempt to separate RP1 customizations from SoC peripherals + * definitioni, this file is intended to host the override nodes for the RP1 + * peripherals, e.g. to declare the phy of the ethernet interface or custom + * pin setup. * All other nodes that do not have anything to do with RP1 should be added - * to the included bcm2712-rpi-5-b-ovl-rp1.dts instead. + * to the included bcm2712-rpi-5-b-base.dtsi instead. */ /dts-v1/; -#include "bcm2712-rpi-5-b-ovl-rp1.dts" +#include "bcm2712-rpi-5-b-base.dtsi" / { aliases { @@ -25,7 +19,26 @@ }; &pcie2 { - #include "rp1-nexus.dtsi" + pci@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + bus-range = <0 1>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + dev@0,0 { + compatible = "pci1de4,1"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + ranges = <0x1 0x0 0x0 0x82010000 0x0 0x0 0x0 0x400000>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <3>; + #size-cells = <2>; + + #include "rp1-common.dtsi" + }; + }; }; &rp1_eth { diff --git a/dts/upstream/src/arm64/broadcom/rp1-nexus.dtsi b/dts/upstream/src/arm64/broadcom/rp1-nexus.dtsi deleted file mode 100644 index 0ef30d7f1c3..00000000000 --- a/dts/upstream/src/arm64/broadcom/rp1-nexus.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -rp1_nexus { - compatible = "pci1de4,1"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01 0x00 0x00000000 - 0x02000000 0x00 0x00000000 - 0x0 0x400000>; - interrupt-controller; - #interrupt-cells = <2>; - - #include "rp1-common.dtsi" -}; diff --git a/dts/upstream/src/arm64/broadcom/rp1.dtso b/dts/upstream/src/arm64/broadcom/rp1.dtso deleted file mode 100644 index ab4f146d22c..00000000000 --- a/dts/upstream/src/arm64/broadcom/rp1.dtso +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) - -/dts-v1/; -/plugin/; - -&pcie2 { - #address-cells = <3>; - #size-cells = <2>; - - #include "rp1-nexus.dtsi" -}; diff --git a/dts/upstream/src/arm64/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/dts/upstream/src/arm64/bst/bstc1200-cdcu1.0-adas_4c2g.dts new file mode 100644 index 00000000000..5eb9ef369d8 --- /dev/null +++ b/dts/upstream/src/arm64/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "bstc1200.dtsi" + +/ { + model = "BST C1200-96 CDCU1.0 4C2G"; + compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@810000000 { + device_type = "memory"; + reg = <0x8 0x10000000 0x0 0x30000000>, + <0x8 0xc0000000 0x1 0x0>, + <0xc 0x00000000 0x0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/bst/bstc1200.dtsi b/dts/upstream/src/arm64/bst/bstc1200.dtsi new file mode 100644 index 00000000000..dd13c6bfc3c --- /dev/null +++ b/dts/upstream/src/arm64/bst/bstc1200.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + compatible = "bst,c1200"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + uart0: serial@20008000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20008000 0x0 0x1000>; + clock-frequency = <25000000>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gic: interrupt-controller@32800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x32800000 0x0 0x10000>, + <0x0 0x32880000 0x0 0x100000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + always-on; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +}; diff --git a/dts/upstream/src/arm64/cix/sky1-orion-o6.dts b/dts/upstream/src/arm64/cix/sky1-orion-o6.dts index d74964d53c3..4dee8cd0b86 100644 --- a/dts/upstream/src/arm64/cix/sky1-orion-o6.dts +++ b/dts/upstream/src/arm64/cix/sky1-orion-o6.dts @@ -7,6 +7,8 @@ /dts-v1/; #include "sky1.dtsi" +#include "sky1-pinfunc.h" + / { model = "Radxa Orion O6"; compatible = "radxa,orion-o6", "cix,sky1"; @@ -34,6 +36,56 @@ }; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hog-cfg { + pins { + pinmux = , + , + , + ; + bias-pull-down; + drive-strength = <8>; + }; + }; +}; + +&iomuxc_s5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_s5>; + + pinctrl_hog_s5: hog-s5-cfg { + pins { + pinmux = ; + bias-pull-up; + drive-strength = <8>; + + }; + }; +}; + +&pcie_x8_rc { + status = "okay"; +}; + +&pcie_x4_rc { + status = "okay"; +}; + +&pcie_x2_rc { + status = "okay"; +}; + +&pcie_x1_0_rc { + status = "okay"; +}; + +&pcie_x1_1_rc { + status = "okay"; +}; + &uart2 { status = "okay"; }; diff --git a/dts/upstream/src/arm64/cix/sky1-pinfunc.h b/dts/upstream/src/arm64/cix/sky1-pinfunc.h new file mode 100644 index 00000000000..ebe9f6fef40 --- /dev/null +++ b/dts/upstream/src/arm64/cix/sky1-pinfunc.h @@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2024-2025 Cix Technology Group Co., Ltd. + */ + +#ifndef __CIX_SKY1_H +#define __CIX_SKY1_H + +/* s5 pads */ +#define CIX_PAD_GPIO001_FUNC_GPIO001 (0 << 8 | 0x0) +#define CIX_PAD_GPIO002_FUNC_GPIO002 (1 << 8 | 0x0) +#define CIX_PAD_GPIO003_FUNC_GPIO003 (2 << 8 | 0x0) +#define CIX_PAD_GPIO004_FUNC_GPIO004 (3 << 8 | 0x0) +#define CIX_PAD_GPIO005_FUNC_GPIO005 (4 << 8 | 0x0) +#define CIX_PAD_GPIO006_FUNC_GPIO006 (5 << 8 | 0x0) +#define CIX_PAD_GPIO007_FUNC_GPIO007 (6 << 8 | 0x0) +#define CIX_PAD_GPIO008_FUNC_GPIO008 (7 << 8 | 0x0) +#define CIX_PAD_GPIO009_FUNC_GPIO009 (8 << 8 | 0x0) +#define CIX_PAD_GPIO010_FUNC_GPIO010 (9 << 8 | 0x0) +#define CIX_PAD_GPIO011_FUNC_GPIO011 (10 << 8 | 0x0) +#define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0) +#define CIX_PAD_GPIO013_FUNC_GPIO013 (12 << 8 | 0x0) +#define CIX_PAD_GPIO014_FUNC_GPIO014 (13 << 8 | 0x0) +#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I2C0_SCL (28 << 8 | 0x0) +#define CIX_PAD_SFI_I2C0_SCL_FUNC_SFI_I3C0_SCL (28 << 8 | 0x1) +#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I2C0_SDA (29 << 8 | 0x0) +#define CIX_PAD_SFI_I2C0_SDA_FUNC_SFI_I3C0_SDA (29 << 8 | 0x1) +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I2C1_SCL (30 << 8 | 0x0) +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_I3C1_SCL (30 << 8 | 0x1) +#define CIX_PAD_SFI_I2C1_SCL_FUNC_SFI_SPI_CS0 (30 << 8 | 0x2) +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I2C1_SDA (31 << 8 | 0x0) +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_I3C1_SDA (31 << 8 | 0x1) +#define CIX_PAD_SFI_I2C1_SDA_FUNC_SFI_SPI_CS1 (31 << 8 | 0x2) +#define CIX_PAD_SFI_GPIO0_FUNC_GPIO015 (32 << 8 | 0x0) +#define CIX_PAD_SFI_GPIO0_FUNC_SFI_SPI_SCK (32 << 8 | 0x1) +#define CIX_PAD_SFI_GPIO0_FUNC_SFI_GPIO0 (32 << 8 | 0x2) +#define CIX_PAD_SFI_GPIO1_FUNC_GPIO016 (33 << 8 | 0x0) +#define CIX_PAD_SFI_GPIO1_FUNC_SFI_SPI_MOSI (33 << 8 | 0x1) +#define CIX_PAD_SFI_GPIO1_FUNC_SFI_GPIO1 (33 << 8 | 0x2) +#define CIX_PAD_SFI_GPIO2_FUNC_GPIO017 (34 << 8 | 0x0) +#define CIX_PAD_SFI_GPIO2_FUNC_SFI_SPI_MISO (34 << 8 | 0x1) +#define CIX_PAD_SFI_GPIO2_FUNC_SFI_GPIO2 (34 << 8 | 0x2) +#define CIX_PAD_GPIO018_FUNC_SFI_GPIO3 (35 << 8 | 0x0) +#define CIX_PAD_GPIO018_FUNC_GPIO018 (35 << 8 | 0x1) +#define CIX_PAD_GPIO019_FUNC_SFI_GPIO4 (36 << 8 | 0x0) +#define CIX_PAD_GPIO019_FUNC_GPIO019 (36 << 8 | 0x1) +#define CIX_PAD_GPIO020_FUNC_SFI_GPIO5 (37 << 8 | 0x0) +#define CIX_PAD_GPIO020_FUNC_GPIO020 (37 << 8 | 0x1) +#define CIX_PAD_GPIO021_FUNC_SFI_GPIO6 (38 << 8 | 0x0) +#define CIX_PAD_GPIO021_FUNC_GPIO021 (38 << 8 | 0x1) +#define CIX_PAD_GPIO022_FUNC_SFI_GPIO7 (39 << 8 | 0x0) +#define CIX_PAD_GPIO022_FUNC_GPIO022 (39 << 8 | 0x1) +#define CIX_PAD_GPIO023_FUNC_SFI_GPIO8 (40 << 8 | 0x0) +#define CIX_PAD_GPIO023_FUNC_GPIO023 (40 << 8 | 0x1) +#define CIX_PAD_GPIO023_FUNC_SFI_I3C0_PUR_EN_L (40 << 8 | 0x2) +#define CIX_PAD_GPIO024_FUNC_SFI_GPIO9 (41 << 8 | 0x0) +#define CIX_PAD_GPIO024_FUNC_GPIO024 (41 << 8 | 0x1) +#define CIX_PAD_GPIO024_FUNC_SFI_I3C1_PUR_EN_L (41 << 8 | 0x2) +#define CIX_PAD_SPI1_MISO_FUNC_SPI1_MISO (42 << 8 | 0x0) +#define CIX_PAD_SPI1_MISO_FUNC_GPIO025 (42 << 8 | 0x1) +#define CIX_PAD_SPI1_CS0_FUNC_SPI1_CS0 (43 << 8 | 0x0) +#define CIX_PAD_SPI1_CS0_FUNC_GPIO026 (43 << 8 | 0x1) +#define CIX_PAD_SPI1_CS1_FUNC_SPI1_CS1 (44 << 8 | 0x0) +#define CIX_PAD_SPI1_CS1_FUNC_GPIO027 (44 << 8 | 0x1) +#define CIX_PAD_SPI1_MOSI_FUNC_SPI1_MOSI (45 << 8 | 0x0) +#define CIX_PAD_SPI1_MOSI_FUNC_GPIO028 (45 << 8 | 0x1) +#define CIX_PAD_SPI1_CLK_FUNC_SPI1_CLK (46 << 8 | 0x0) +#define CIX_PAD_SPI1_CLK_FUNC_GPIO029 (46 << 8 | 0x1) +#define CIX_PAD_GPIO030_FUNC_GPIO030 (47 << 8 | 0x0) +#define CIX_PAD_GPIO030_FUNC_USB_OC0_L (47 << 8 | 0x1) +#define CIX_PAD_GPIO031_FUNC_GPIO031 (48 << 8 | 0x0) +#define CIX_PAD_GPIO031_FUNC_USB_OC1_L (48 << 8 | 0x1) +#define CIX_PAD_GPIO032_FUNC_GPIO032 (49 << 8 | 0x0) +#define CIX_PAD_GPIO032_FUNC_USB_OC2_L (49 << 8 | 0x1) +#define CIX_PAD_GPIO033_FUNC_GPIO033 (50 << 8 | 0x0) +#define CIX_PAD_GPIO033_FUNC_USB_OC3_L (50 << 8 | 0x1) +#define CIX_PAD_GPIO034_FUNC_GPIO034 (51 << 8 | 0x0) +#define CIX_PAD_GPIO034_FUNC_USB_OC4_L (51 << 8 | 0x1) +#define CIX_PAD_GPIO035_FUNC_GPIO035 (52 << 8 | 0x0) +#define CIX_PAD_GPIO035_FUNC_USB_OC5_L (52 << 8 | 0x1) +#define CIX_PAD_GPIO036_FUNC_GPIO036 (53 << 8 | 0x0) +#define CIX_PAD_GPIO036_FUNC_USB_OC6_L (53 << 8 | 0x1) +#define CIX_PAD_GPIO037_FUNC_GPIO037 (54 << 8 | 0x0) +#define CIX_PAD_GPIO037_FUNC_USB_OC7_L (54 << 8 | 0x1) +#define CIX_PAD_GPIO038_FUNC_GPIO038 (55 << 8 | 0x0) +#define CIX_PAD_GPIO038_FUNC_USB_OC8_L (55 << 8 | 0x1) +#define CIX_PAD_GPIO039_FUNC_GPIO039 (56 << 8 | 0x0) +#define CIX_PAD_GPIO039_FUNC_USB_OC9_L (56 << 8 | 0x1) +#define CIX_PAD_GPIO040_FUNC_GPIO040 (57 << 8 | 0x0) +#define CIX_PAD_GPIO040_FUNC_USB_DRIVE_VBUS0 (57 << 8 | 0x1) +#define CIX_PAD_GPIO041_FUNC_GPIO041 (58 << 8 | 0x0) +#define CIX_PAD_GPIO041_FUNC_USB_DRIVE_VBUS4 (58 << 8 | 0x1) +#define CIX_PAD_GPIO042_FUNC_GPIO042 (59 << 8 | 0x0) +#define CIX_PAD_GPIO042_FUNC_USB_DRIVE_VBUS5 (59 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_CLK_FUNC_SE_QSPI_CLK (60 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_CLK_FUNC_QSPI_CLK (60 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_CS_L_FUNC_SE_QSPI_CS_L (61 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_CS_L_FUNC_QSPI_CS_L (61 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA0_FUNC_SE_QSPI_DATA0 (62 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA0_FUNC_QSPI_DATA0 (62 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA1_FUNC_SE_QSPI_DATA1 (63 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA1_FUNC_QSPI_DATA1 (63 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA2_FUNC_SE_QSPI_DATA2 (64 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA2_FUNC_QSPI_DATA2 (64 << 8 | 0x1) +#define CIX_PAD_SE_QSPI_DATA3_FUNC_SE_QSPI_DATA3 (65 << 8 | 0x0) +#define CIX_PAD_SE_QSPI_DATA3_FUNC_QSPI_DATA3 (65 << 8 | 0x1) +/* s0 pads */ +#define CIX_PAD_GPIO043_FUNC_GPIO043 (0 << 8 | 0x0) +#define CIX_PAD_GPIO044_FUNC_GPIO044 (1 << 8 | 0x0) +#define CIX_PAD_GPIO045_FUNC_GPIO045 (2 << 8 | 0x0) +#define CIX_PAD_GPIO046_FUNC_GPIO046 (3 << 8 | 0x0) +#define CIX_PAD_DP2_DIGON_FUNC_DP2_DIGON (18 << 8 | 0x0) +#define CIX_PAD_DP2_BLON_FUNC_DP2_BLON (19 << 8 | 0x0) +#define CIX_PAD_DP2_VARY_BL_FUNC_DP2_VARY_BL (20 << 8 | 0x0) +#define CIX_PAD_I2C7_SCL_FUNC_I2C7_SCL (21 << 8 | 0x0) +#define CIX_PAD_I2C7_SDA_FUNC_I2C7_SDA (22 << 8 | 0x0) +#define CIX_PAD_I2C5_SCL_FUNC_I2C5_SCL (26 << 8 | 0x0) +#define CIX_PAD_I2C5_SCL_FUNC_GPIO047 (26 << 8 | 0x1) +#define CIX_PAD_I2C5_SDA_FUNC_I2C5_SDA (27 << 8 | 0x0) +#define CIX_PAD_I2C5_SDA_FUNC_GPIO048 (27 << 8 | 0x1) +#define CIX_PAD_I2C6_SCL_FUNC_I2C6_SCL (28 << 8 | 0x0) +#define CIX_PAD_I2C6_SCL_FUNC_GPIO049 (28 << 8 | 0x1) +#define CIX_PAD_I2C6_SDA_FUNC_I2C6_SDA (29 << 8 | 0x0) +#define CIX_PAD_I2C6_SDA_FUNC_GPIO050 (29 << 8 | 0x1) +#define CIX_PAD_I2C0_CLK_FUNC_I2C0_CLK (30 << 8 | 0x0) +#define CIX_PAD_I2C0_CLK_FUNC_GPIO051 (30 << 8 | 0x1) +#define CIX_PAD_I2C0_SDA_FUNC_I2C0_SDA (31 << 8 | 0x0) +#define CIX_PAD_I2C0_SDA_FUNC_GPIO052 (31 << 8 | 0x1) +#define CIX_PAD_I2C1_CLK_FUNC_I2C1_CLK (32 << 8 | 0x0) +#define CIX_PAD_I2C1_CLK_FUNC_GPIO053 (32 << 8 | 0x1) +#define CIX_PAD_I2C1_SDA_FUNC_I2C1_SDA (33 << 8 | 0x0) +#define CIX_PAD_I2C1_SDA_FUNC_GPIO054 (33 << 8 | 0x1) +#define CIX_PAD_I2C2_SCL_FUNC_I2C2_SCL (34 << 8 | 0x0) +#define CIX_PAD_I2C2_SCL_FUNC_I3C0_SCL (34 << 8 | 0x1) +#define CIX_PAD_I2C2_SCL_FUNC_GPIO055 (34 << 8 | 0x2) +#define CIX_PAD_I2C2_SDA_FUNC_I2C2_SDA (35 << 8 | 0x0) +#define CIX_PAD_I2C2_SDA_FUNC_I3C0_SDA (35 << 8 | 0x1) +#define CIX_PAD_I2C2_SDA_FUNC_GPIO056 (35 << 8 | 0x2) +#define CIX_PAD_GPIO057_FUNC_GPIO057 (36 << 8 | 0x0) +#define CIX_PAD_GPIO057_FUNC_I3C0_PUR_EN_L (36 << 8 | 0x1) +#define CIX_PAD_I2C3_CLK_FUNC_I2C3_CLK (37 << 8 | 0x0) +#define CIX_PAD_I2C3_CLK_FUNC_I3C1_CLK (37 << 8 | 0x1) +#define CIX_PAD_I2C3_CLK_FUNC_GPIO058 (37 << 8 | 0x2) +#define CIX_PAD_I2C3_SDA_FUNC_I2C3_SDA (38 << 8 | 0x0) +#define CIX_PAD_I2C3_SDA_FUNC_I3C1_SDA (38 << 8 | 0x1) +#define CIX_PAD_I2C3_SDA_FUNC_GPIO059 (38 << 8 | 0x2) +#define CIX_PAD_GPIO060_FUNC_GPIO060 (39 << 8 | 0x0) +#define CIX_PAD_GPIO060_FUNC_I3C1_PUR_EN_L (39 << 8 | 0x1) +#define CIX_PAD_I2C4_CLK_FUNC_I2C4_CLK (40 << 8 | 0x0) +#define CIX_PAD_I2C4_CLK_FUNC_GPIO061 (40 << 8 | 0x1) +#define CIX_PAD_I2C4_SDA_FUNC_I2C4_SDA (41 << 8 | 0x0) +#define CIX_PAD_I2C4_SDA_FUNC_GPIO062 (41 << 8 | 0x1) +#define CIX_PAD_HDA_BITCLK_FUNC_HDA_BITCLK (42 << 8 | 0x0) +#define CIX_PAD_HDA_BITCLK_FUNC_I2S0_SCK (42 << 8 | 0x1) +#define CIX_PAD_HDA_BITCLK_FUNC_I2S9_RSCK_DBG (42 << 8 | 0x2) +#define CIX_PAD_HDA_RST_L_FUNC_HDA_RST_L (43 << 8 | 0x0) +#define CIX_PAD_HDA_RST_L_FUNC_I2S0_DATA_IN (43 << 8 | 0x1) +#define CIX_PAD_HDA_RST_L_FUNC_I2S9_DATA_IN0_DBG (43 << 8 | 0x2) +#define CIX_PAD_HDA_SDIN0_FUNC_HDA_SDIN0 (44 << 8 | 0x0) +#define CIX_PAD_HDA_SDIN0_FUNC_I2S0_MCLK (44 << 8 | 0x1) +#define CIX_PAD_HDA_SDIN0_FUNC_I2S9_TSCK_DBG (44 << 8 | 0x2) +#define CIX_PAD_HDA_SDOUT0_FUNC_HDA_SDOUT0 (45 << 8 | 0x0) +#define CIX_PAD_HDA_SDOUT0_FUNC_I2S0_DATA_OUT (45 << 8 | 0x1) +#define CIX_PAD_HDA_SDOUT0_FUNC_I2S9_TWS_DBG (45 << 8 | 0x2) +#define CIX_PAD_HDA_SYNC_FUNC_HDA_SYNC (46 << 8 | 0x0) +#define CIX_PAD_HDA_SYNC_FUNC_I2S0_WS (46 << 8 | 0x1) +#define CIX_PAD_HDA_SYNC_FUNC_I2S9_RWS_DBG (46 << 8 | 0x2) +#define CIX_PAD_HDA_SDIN1_FUNC_HDA_SDIN1 (47 << 8 | 0x0) +#define CIX_PAD_HDA_SDIN1_FUNC_GPIO063 (47 << 8 | 0x1) +#define CIX_PAD_HDA_SDIN1_FUNC_I2S9_DATA_IN1_DBG (47 << 8 | 0x2) +#define CIX_PAD_HDA_SDOUT1_FUNC_HDA_SDOUT1 (48 << 8 | 0x0) +#define CIX_PAD_HDA_SDOUT1_FUNC_GPIO064 (48 << 8 | 0x1) +#define CIX_PAD_HDA_SDOUT1_FUNC_I2S9_DATA_OUT0_DBG (48 << 8 | 0x2) +#define CIX_PAD_I2S1_MCLK_FUNC_I2S1_MCLK (49 << 8 | 0x0) +#define CIX_PAD_I2S1_MCLK_FUNC_GPIO065 (49 << 8 | 0x1) +#define CIX_PAD_I2S1_SCK_FUNC_I2S1_SCK (50 << 8 | 0x0) +#define CIX_PAD_I2S1_SCK_FUNC_GPIO066 (50 << 8 | 0x1) +#define CIX_PAD_I2S1_WS_FUNC_I2S1_WS (51 << 8 | 0x0) +#define CIX_PAD_I2S1_WS_FUNC_GPIO067 (51 << 8 | 0x1) +#define CIX_PAD_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (52 << 8 | 0x0) +#define CIX_PAD_I2S1_DATA_IN_FUNC_GPIO068 (52 << 8 | 0x1) +#define CIX_PAD_I2S1_DATA_OUT_FUNC_I2S1_DATA_OUT (53 << 8 | 0x0) +#define CIX_PAD_I2S1_DATA_OUT_FUNC_GPIO069 (53 << 8 | 0x1) +#define CIX_PAD_I2S2_MCLK_FUNC_I2S2_MCLK (54 << 8 | 0x0) +#define CIX_PAD_I2S2_MCLK_FUNC_GPIO070 (54 << 8 | 0x1) +#define CIX_PAD_I2S2_RSCK_FUNC_I2S2_RSCK (55 << 8 | 0x0) +#define CIX_PAD_I2S2_RSCK_FUNC_GPIO071 (55 << 8 | 0x1) +#define CIX_PAD_I2S2_RSCK_FUNC_I2S5_RSCK_DBG (55 << 8 | 0x2) +#define CIX_PAD_I2S2_RSCK_FUNC_I2S6_RSCK_DBG (55 << 8 | 0x3) +#define CIX_PAD_I2S2_RWS_FUNC_I2S2_RWS (56 << 8 | 0x0) +#define CIX_PAD_I2S2_RWS_FUNC_GPIO072 (56 << 8 | 0x1) +#define CIX_PAD_I2S2_RWS_FUNC_I2S5_RWS_DBG (56 << 8 | 0x2) +#define CIX_PAD_I2S2_RWS_FUNC_I2S6_RWS_DBG (56 << 8 | 0x3) +#define CIX_PAD_I2S2_TSCK_FUNC_I2S2_TSCK (57 << 8 | 0x0) +#define CIX_PAD_I2S2_TSCK_FUNC_GPIO073 (57 << 8 | 0x1) +#define CIX_PAD_I2S2_TSCK_FUNC_I2S5_TSCK_DBG (57 << 8 | 0x2) +#define CIX_PAD_I2S2_TSCK_FUNC_I2S6_TSCK_DBG (57 << 8 | 0x3) +#define CIX_PAD_I2S2_TWS_FUNC_I2S2_TWS (58 << 8 | 0x0) +#define CIX_PAD_I2S2_TWS_FUNC_GPIO074 (58 << 8 | 0x1) +#define CIX_PAD_I2S2_TWS_FUNC_I2S5_TWS_DBG (58 << 8 | 0x2) +#define CIX_PAD_I2S2_TWS_FUNC_I2S6_TWS_DBG (58 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S2_DATA_IN0 (59 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_GPIO075 (59 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S5_DATA_IN0_DBG (59 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_IN0_FUNC_I2S6_DATA_IN0_DBG (59 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S2_DATA_IN1 (60 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_GPIO076 (60 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S5_DATA_IN1_DBG (60 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_IN1_FUNC_I2S6_DATA_IN1_DBG (60 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S2_DATA_OUT0 (61 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_GPIO077 (61 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S5_DATA_OUT0_DBG (61 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_OUT0_FUNC_I2S6_DATA_OUT0_DBG (61 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S2_DATA_OUT1 (62 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_GPIO078 (62 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S5_DATA_OUT1_DBG (62 << 8 | 0x2) +#define CIX_PAD_I2S2_DATA_OUT1_FUNC_I2S6_DATA_OUT1_DBG (62 << 8 | 0x3) +#define CIX_PAD_I2S2_DATA_OUT2_FUNC_I2S2_DATA_OUT2 (63 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT2_FUNC_GPIO079 (63 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S2_DATA_OUT3 (64 << 8 | 0x0) +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_GPIO080 (64 << 8 | 0x1) +#define CIX_PAD_I2S2_DATA_OUT3_FUNC_I2S9_DATA_OUT1_DBG (64 << 8 | 0x2) +#define CIX_PAD_I2S3_MCLK_FUNC_I2S3_MCLK (65 << 8 | 0x0) +#define CIX_PAD_I2S3_MCLK_FUNC_GPIO081 (65 << 8 | 0x1) +#define CIX_PAD_I2S3_RSCK_FUNC_I2S3_RSCK (66 << 8 | 0x0) +#define CIX_PAD_I2S3_RSCK_FUNC_GPIO082 (66 << 8 | 0x1) +#define CIX_PAD_I2S3_RSCK_FUNC_I2S7_RSCK_DBG (66 << 8 | 0x2) +#define CIX_PAD_I2S3_RSCK_FUNC_I2S8_RSCK_DBG (66 << 8 | 0x3) +#define CIX_PAD_I2S3_RWS_FUNC_I2S3_RWS (67 << 8 | 0x0) +#define CIX_PAD_I2S3_RWS_FUNC_GPIO083 (67 << 8 | 0x1) +#define CIX_PAD_I2S3_RWS_FUNC_I2S7_RWS_DBG (67 << 8 | 0x2) +#define CIX_PAD_I2S3_RWS_FUNC_I2S8_RWS_DBG (67 << 8 | 0x3) +#define CIX_PAD_I2S3_TSCK_FUNC_I2S3_TSCK (68 << 8 | 0x0) +#define CIX_PAD_I2S3_TSCK_FUNC_GPIO084 (68 << 8 | 0x1) +#define CIX_PAD_I2S3_TSCK_FUNC_I2S7_TSCK_DBG (68 << 8 | 0x2) +#define CIX_PAD_I2S3_TSCK_FUNC_I2S8_TSCK_DBG (68 << 8 | 0x3) +#define CIX_PAD_I2S3_TWS_FUNC_I2S3_TWS (69 << 8 | 0x0) +#define CIX_PAD_I2S3_TWS_FUNC_GPIO085 (69 << 8 | 0x1) +#define CIX_PAD_I2S3_TWS_FUNC_I2S7_TWS_DBG (69 << 8 | 0x2) +#define CIX_PAD_I2S3_TWS_FUNC_I2S8_TWS_DBG (69 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S3_DATA_IN0 (70 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_GPIO086 (70 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S7_DATA_IN0_DBG (70 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_IN0_FUNC_I2S8_DATA_IN0_DBG (70 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S3_DATA_IN1 (71 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_GPIO087 (71 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S7_DATA_IN1_DBG (71 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_IN1_FUNC_I2S8_DATA_IN1_DBG (71 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S3_DATA_OUT0 (72 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_GPIO088 (72 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S7_DATA_OUT0_DBG (72 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_OUT0_FUNC_I2S8_DATA_OUT0_DBG (72 << 8 | 0x3) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S3_DATA_OUT1 (73 << 8 | 0x0) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_GPIO089 (73 << 8 | 0x1) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S7_DATA_OUT1_DBG (73 << 8 | 0x2) +#define CIX_PAD_I2S3_DATA_OUT1_FUNC_I2S8_DATA_OUT1_DBG (73 << 8 | 0x3) +#define CIX_PAD_GPIO090_FUNC_GPIO090 (74 << 8 | 0x0) +#define CIX_PAD_GPIO090_FUNC_I2S4_MCLK_LB (74 << 8 | 0x1) +#define CIX_PAD_GPIO091_FUNC_GPIO091 (75 << 8 | 0x0) +#define CIX_PAD_GPIO091_FUNC_I2S4_SCK_LB (75 << 8 | 0x1) +#define CIX_PAD_GPIO092_FUNC_GPIO092 (76 << 8 | 0x0) +#define CIX_PAD_GPIO092_FUNC_I2S4_WS_LB (76 << 8 | 0x1) +#define CIX_PAD_GPIO093_FUNC_GPIO093 (77 << 8 | 0x0) +#define CIX_PAD_GPIO093_FUNC_I2S4_DATA_IN_LB (77 << 8 | 0x1) +#define CIX_PAD_GPIO094_FUNC_GPIO094 (78 << 8 | 0x0) +#define CIX_PAD_GPIO094_FUNC_I2S4_DATA_OUT_LB (78 << 8 | 0x1) +#define CIX_PAD_UART0_TXD_FUNC_UART0_TXD (79 << 8 | 0x0) +#define CIX_PAD_UART0_TXD_FUNC_PWM0 (79 << 8 | 0x1) +#define CIX_PAD_UART0_TXD_FUNC_GPIO095 (79 << 8 | 0x2) +#define CIX_PAD_UART0_RXD_FUNC_UART0_RXD (80 << 8 | 0x0) +#define CIX_PAD_UART0_RXD_FUNC_PWM1 (80 << 8 | 0x1) +#define CIX_PAD_UART0_RXD_FUNC_GPIO096 (80 << 8 | 0x2) +#define CIX_PAD_UART0_CTS_FUNC_UART0_CTS (81 << 8 | 0x0) +#define CIX_PAD_UART0_CTS_FUNC_FAN_OUT2 (81 << 8 | 0x1) +#define CIX_PAD_UART0_CTS_FUNC_GPIO097 (81 << 8 | 0x2) +#define CIX_PAD_UART0_RTS_FUNC_UART0_RTS (82 << 8 | 0x0) +#define CIX_PAD_UART0_RTS_FUNC_FAN_TACH2 (82 << 8 | 0x1) +#define CIX_PAD_UART0_RTS_FUNC_GPIO098 (82 << 8 | 0x2) +#define CIX_PAD_UART1_TXD_FUNC_UART1_TXD (83 << 8 | 0x0) +#define CIX_PAD_UART1_TXD_FUNC_FAN_OUT0 (83 << 8 | 0x1) +#define CIX_PAD_UART1_TXD_FUNC_GPIO099 (83 << 8 | 0x2) +#define CIX_PAD_UART1_RXD_FUNC_UART1_RXD (84 << 8 | 0x0) +#define CIX_PAD_UART1_RXD_FUNC_FAN_TACH0 (84 << 8 | 0x1) +#define CIX_PAD_UART1_RXD_FUNC_GPIO100 (84 << 8 | 0x2) +#define CIX_PAD_UART1_CTS_FUNC_UART1_CTS (85 << 8 | 0x0) +#define CIX_PAD_UART1_CTS_FUNC_FAN_OUT1 (85 << 8 | 0x1) +#define CIX_PAD_UART1_CTS_FUNC_GPIO101 (85 << 8 | 0x2) +#define CIX_PAD_UART1_RTS_FUNC_UART1_RTS (86 << 8 | 0x0) +#define CIX_PAD_UART1_RTS_FUNC_FAN_TACH1 (86 << 8 | 0x1) +#define CIX_PAD_UART1_RTS_FUNC_GPIO102 (86 << 8 | 0x2) +#define CIX_PAD_UART2_TXD_FUNC_UART2_TXD (87 << 8 | 0x0) +#define CIX_PAD_UART2_TXD_FUNC_GPIO103 (87 << 8 | 0x1) +#define CIX_PAD_UART2_RXD_FUNC_UART2_RXD (88 << 8 | 0x0) +#define CIX_PAD_UART2_RXD_FUNC_GPIO104 (88 << 8 | 0x1) +#define CIX_PAD_UART3_TXD_FUNC_UART3_TXD (89 << 8 | 0x0) +#define CIX_PAD_UART3_TXD_FUNC_GPIO105 (89 << 8 | 0x1) +#define CIX_PAD_UART3_RXD_FUNC_UART3_RXD (90 << 8 | 0x0) +#define CIX_PAD_UART3_RXD_FUNC_GPIO106 (90 << 8 | 0x1) +#define CIX_PAD_UART3_CTS_FUNC_UART3_CTS (91 << 8 | 0x0) +#define CIX_PAD_UART3_CTS_FUNC_GPIO107 (91 << 8 | 0x1) +#define CIX_PAD_UART3_CTS_FUNC_TRIGIN0 (91 << 8 | 0x2) +#define CIX_PAD_UART3_RTS_FUNC_UART3_RTS (92 << 8 | 0x0) +#define CIX_PAD_UART3_RTS_FUNC_GPIO108 (92 << 8 | 0x1) +#define CIX_PAD_UART3_RTS_FUNC_TRIGIN1 (92 << 8 | 0x2) +#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_UART4_CSU_PM_TXD (93 << 8 | 0x0) +#define CIX_PAD_UART4_CSU_PM_TXD_FUNC_GPIO109 (93 << 8 | 0x1) +#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_UART4_CSU_PM_RXD (94 << 8 | 0x0) +#define CIX_PAD_UART4_CSU_PM_RXD_FUNC_GPIO110 (94 << 8 | 0x1) +#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_UART5_CSU_SE_TXD (95 << 8 | 0x0) +#define CIX_PAD_UART5_CSU_SE_TXD_FUNC_GPIO111 (95 << 8 | 0x1) +#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_UART5_CSU_SE_RXD (96 << 8 | 0x0) +#define CIX_PAD_UART5_CSU_SE_RXD_FUNC_GPIO112 (96 << 8 | 0x1) +#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_UART6_CSU_SE_RXD (97 << 8 | 0x0) +#define CIX_PAD_UART6_CSU_SE_RXD_FUNC_GPIO113 (97 << 8 | 0x1) +#define CIX_PAD_CLK_REQ0_L_FUNC_CLK_REQ0_L (98 << 8 | 0x0) +#define CIX_PAD_CLK_REQ0_L_FUNC_GPIO114 (98 << 8 | 0x1) +#define CIX_PAD_CLK_REQ2_L_FUNC_CLK_REQ2_L (99 << 8 | 0x0) +#define CIX_PAD_CLK_REQ2_L_FUNC_GPIO115 (99 << 8 | 0x1) +#define CIX_PAD_CLK_REQ4_L_FUNC_CLK_REQ4_L (100 << 8 | 0x0) +#define CIX_PAD_CLK_REQ4_L_FUNC_GPIO116 (100 << 8 | 0x1) +#define CIX_PAD_CSI0_MCLK0_FUNC_CSI0_MCLK0 (101 << 8 | 0x0) +#define CIX_PAD_CSI0_MCLK0_FUNC_GPIO117 (101 << 8 | 0x1) +#define CIX_PAD_CSI0_MCLK1_FUNC_CSI0_MCLK1 (102 << 8 | 0x0) +#define CIX_PAD_CSI0_MCLK1_FUNC_GPIO118 (102 << 8 | 0x1) +#define CIX_PAD_CSI1_MCLK0_FUNC_CSI1_MCLK0 (103 << 8 | 0x0) +#define CIX_PAD_CSI1_MCLK0_FUNC_GPIO119 (103 << 8 | 0x1) +#define CIX_PAD_CSI1_MCLK1_FUNC_CSI1_MCLK1 (104 << 8 | 0x0) +#define CIX_PAD_CSI1_MCLK1_FUNC_GPIO120 (104 << 8 | 0x1) +#define CIX_PAD_GPIO121_FUNC_GPIO121 (105 << 8 | 0x0) +#define CIX_PAD_GPIO121_FUNC_GMAC0_REFCLK_25M (105 << 8 | 0x1) +#define CIX_PAD_GPIO122_FUNC_GPIO122 (106 << 8 | 0x0) +#define CIX_PAD_GPIO122_FUNC_GMAC0_TX_CTL (106 << 8 | 0x1) +#define CIX_PAD_GPIO123_FUNC_GPIO123 (107 << 8 | 0x0) +#define CIX_PAD_GPIO123_FUNC_GMAC0_TXD0 (107 << 8 | 0x1) +#define CIX_PAD_GPIO124_FUNC_GPIO124 (108 << 8 | 0x0) +#define CIX_PAD_GPIO124_FUNC_GMAC0_TXD1 (108 << 8 | 0x1) +#define CIX_PAD_GPIO125_FUNC_GPIO125 (109 << 8 | 0x0) +#define CIX_PAD_GPIO125_FUNC_GMAC0_TXD2 (109 << 8 | 0x1) +#define CIX_PAD_GPIO126_FUNC_GPIO126 (110 << 8 | 0x0) +#define CIX_PAD_GPIO126_FUNC_GMAC0_TXD3 (110 << 8 | 0x1) +#define CIX_PAD_GPIO127_FUNC_GPIO127 (111 << 8 | 0x0) +#define CIX_PAD_GPIO127_FUNC_GMAC0_TX_CLK (111 << 8 | 0x1) +#define CIX_PAD_GPIO128_FUNC_GPIO128 (112 << 8 | 0x0) +#define CIX_PAD_GPIO128_FUNC_GMAC0_RX_CTL (112 << 8 | 0x1) +#define CIX_PAD_GPIO129_FUNC_GPIO129 (113 << 8 | 0x0) +#define CIX_PAD_GPIO129_FUNC_GMAC0_RXD0 (113 << 8 | 0x1) +#define CIX_PAD_GPIO130_FUNC_GPIO130 (114 << 8 | 0x0) +#define CIX_PAD_GPIO130_FUNC_GMAC0_RXD1 (114 << 8 | 0x1) +#define CIX_PAD_GPIO131_FUNC_GPIO131 (115 << 8 | 0x0) +#define CIX_PAD_GPIO131_FUNC_GMAC0_RXD2 (115 << 8 | 0x1) +#define CIX_PAD_GPIO132_FUNC_GPIO132 (116 << 8 | 0x0) +#define CIX_PAD_GPIO132_FUNC_GMAC0_RXD3 (116 << 8 | 0x1) +#define CIX_PAD_GPIO133_FUNC_GPIO133 (117 << 8 | 0x0) +#define CIX_PAD_GPIO133_FUNC_GMAC0_RX_CLK (117 << 8 | 0x1) +#define CIX_PAD_GPIO134_FUNC_GPIO134 (118 << 8 | 0x0) +#define CIX_PAD_GPIO134_FUNC_GMAC0_MDC (118 << 8 | 0x1) +#define CIX_PAD_GPIO135_FUNC_GPIO135 (119 << 8 | 0x0) +#define CIX_PAD_GPIO135_FUNC_GMAC0_MDIO (119 << 8 | 0x1) +#define CIX_PAD_GPIO136_FUNC_GPIO136 (120 << 8 | 0x0) +#define CIX_PAD_GPIO136_FUNC_GMAC1_REFCLK_25M (120 << 8 | 0x1) +#define CIX_PAD_GPIO137_FUNC_GPIO137 (121 << 8 | 0x0) +#define CIX_PAD_GPIO137_FUNC_GMAC1_TX_CTL (121 << 8 | 0x1) +#define CIX_PAD_GPIO138_FUNC_GPIO138 (122 << 8 | 0x0) +#define CIX_PAD_GPIO138_FUNC_GMAC1_TXD0 (122 << 8 | 0x1) +#define CIX_PAD_GPIO138_FUNC_SPI2_MISO (122 << 8 | 0x2) +#define CIX_PAD_GPIO139_FUNC_GPIO139 (123 << 8 | 0x0) +#define CIX_PAD_GPIO139_FUNC_GMAC1_TXD1 (123 << 8 | 0x1) +#define CIX_PAD_GPIO139_FUNC_SPI2_CS0 (123 << 8 | 0x2) +#define CIX_PAD_GPIO140_FUNC_GPIO140 (124 << 8 | 0x0) +#define CIX_PAD_GPIO140_FUNC_GMAC1_TXD2 (124 << 8 | 0x1) +#define CIX_PAD_GPIO140_FUNC_SPI2_CS1 (124 << 8 | 0x2) +#define CIX_PAD_GPIO141_FUNC_GPIO141 (125 << 8 | 0x0) +#define CIX_PAD_GPIO141_FUNC_GMAC1_TXD3 (125 << 8 | 0x1) +#define CIX_PAD_GPIO141_FUNC_SPI2_MOSI (125 << 8 | 0x2) +#define CIX_PAD_GPIO142_FUNC_GPIO142 (126 << 8 | 0x0) +#define CIX_PAD_GPIO142_FUNC_GMAC1_TX_CLK (126 << 8 | 0x1) +#define CIX_PAD_GPIO142_FUNC_SPI2_CLK (126 << 8 | 0x2) +#define CIX_PAD_GPIO143_FUNC_GPIO143 (127 << 8 | 0x0) +#define CIX_PAD_GPIO143_FUNC_GMAC1_RX_CTL (127 << 8 | 0x1) +#define CIX_PAD_GPIO144_FUNC_GPIO144 (128 << 8 | 0x0) +#define CIX_PAD_GPIO144_FUNC_GMAC1_RXD0 (128 << 8 | 0x1) +#define CIX_PAD_GPIO145_FUNC_GPIO145 (129 << 8 | 0x0) +#define CIX_PAD_GPIO145_FUNC_GMAC1_RXD1 (129 << 8 | 0x1) +#define CIX_PAD_GPIO146_FUNC_GPIO146 (130 << 8 | 0x0) +#define CIX_PAD_GPIO146_FUNC_GMAC1_RXD2 (130 << 8 | 0x1) +#define CIX_PAD_GPIO147_FUNC_GPIO147 (131 << 8 | 0x0) +#define CIX_PAD_GPIO147_FUNC_GMAC1_RXD3 (131 << 8 | 0x1) +#define CIX_PAD_GPIO148_FUNC_GPIO148 (132 << 8 | 0x0) +#define CIX_PAD_GPIO148_FUNC_GMAC1_RX_CLK (132 << 8 | 0x1) +#define CIX_PAD_GPIO149_FUNC_GPIO149 (133 << 8 | 0x0) +#define CIX_PAD_GPIO149_FUNC_GMAC1_MDC (133 << 8 | 0x1) +#define CIX_PAD_GPIO150_FUNC_GPIO150 (134 << 8 | 0x0) +#define CIX_PAD_GPIO150_FUNC_GMAC1_MDIO (134 << 8 | 0x1) +#define CIX_PAD_GPIO151_FUNC_GPIO151 (135 << 8 | 0x0) +#define CIX_PAD_GPIO151_FUNC_PM_GPIO0 (135 << 8 | 0x1) +#define CIX_PAD_GPIO152_FUNC_GPIO152 (136 << 8 | 0x0) +#define CIX_PAD_GPIO152_FUNC_PM_GPIO1 (136 << 8 | 0x1) +#define CIX_PAD_GPIO153_FUNC_GPIO153 (137 << 8 | 0x0) +#define CIX_PAD_GPIO153_FUNC_PM_GPIO2 (137 << 8 | 0x1) + +#endif diff --git a/dts/upstream/src/arm64/cix/sky1.dtsi b/dts/upstream/src/arm64/cix/sky1.dtsi index 2fb2c99c079..64b76905cbf 100644 --- a/dts/upstream/src/arm64/cix/sky1.dtsi +++ b/dts/upstream/src/arm64/cix/sky1.dtsi @@ -264,6 +264,26 @@ status = "disabled"; }; + spi0: spi@4090000 { + compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; + reg = <0x0 0x04090000 0x0 0x10000>; + clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>, + <&scmi_clk CLK_TREE_FCH_SPI0_APB>; + clock-names = "ref_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + spi1: spi@40a0000 { + compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; + reg = <0x0 0x040a0000 0x0 0x10000>; + clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>, + <&scmi_clk CLK_TREE_FCH_SPI1_APB>; + clock-names = "ref_clk", "pclk"; + interrupts = ; + status = "disabled"; + }; + uart0: serial@40b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x040b0000 0x0 0x1000>; @@ -328,6 +348,11 @@ status = "disabled"; }; + iomuxc: pinctrl@4170000 { + compatible = "cix,sky1-pinctrl"; + reg = <0x0 0x04170000 0x0 0x1000>; + }; + mbox_ap2se: mailbox@5060000 { compatible = "cix,sky1-mbox"; reg = <0x0 0x05060000 0x0 0x10000>; @@ -388,6 +413,132 @@ cix,mbox-dir = "tx"; }; + pcie_x8_rc: pcie@a010000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000300 0x00 0x100>, + <0x00 0x0a000400 0x00 0x100>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0xc0 0xff>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0xc000 &gic_its 0xc000 0x4000>; + status = "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x0a060300 0x00 0x40>, + <0x00 0x0a060400 0x00 0x40>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x90 0xbf>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x9000 &gic_its 0x9000 0x3000>; + status = "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x0a0600340 0x00 0x20>, + <0x00 0x0a0600440 0x00 0x20>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x60 0x8f>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x6000 &gic_its 0x6000 0x3000>; + status = "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x0a060360 0x00 0x20>, + <0x00 0x0a060460 0x00 0x20>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x2f>; + device_type = "pci"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x0000 &gic_its 0x0000 0x3000>; + status = "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { + compatible = "cix,sky1-pcie-host"; + reg = <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x0a060380 0x00 0x20>, + <0x00 0x0a060480 0x00 0x20>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x30 0x5f>; + device_type = "pci"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map = <0x3000 &gic_its 0x3000 0x3000>; + status = "disabled"; + }; + gic: interrupt-controller@e010000 { compatible = "arm,gic-v3"; reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ @@ -416,6 +567,11 @@ }; }; }; + + iomuxc_s5: pinctrl@16007000 { + compatible = "cix,sky1-pinctrl-s5"; + reg = <0x0 0x16007000 0x0 0x1000>; + }; }; timer { diff --git a/dts/upstream/src/arm64/exynos/exynos7870-a2corelte.dts b/dts/upstream/src/arm64/exynos/exynos7870-a2corelte.dts index eb7b4859318..6f40ca4350e 100644 --- a/dts/upstream/src/arm64/exynos/exynos7870-a2corelte.dts +++ b/dts/upstream/src/arm64/exynos/exynos7870-a2corelte.dts @@ -27,20 +27,7 @@ }; chosen { - #address-cells = <2>; - #size-cells = <1>; - ranges; - stdout-path = &serial2; - - framebuffer@67000000 { - compatible = "simple-framebuffer"; - reg = <0x0 0x67000000 (540 * 960 * 4)>; - width = <540>; - height = <960>; - stride = <(540 * 4)>; - format = "a8r8g8b8"; - }; }; gpio-keys { @@ -110,8 +97,9 @@ pmsg-size = <0x4000>; }; - framebuffer@67000000 { + cont_splash_mem: framebuffer@67000000 { reg = <0x0 0x67000000 (540 * 960 * 4)>; + iommu-addresses = <&decon 0x67000000 (540 * 960 * 4)>; no-map; }; }; @@ -124,6 +112,47 @@ }; }; +&decon { + memory-region = <&cont_splash_mem>; + + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + samsung,burst-clock-frequency = <836000000>; + samsung,esc-clock-frequency = <16000000>; + samsung,pll-clock-frequency = <26000000>; + + status = "okay"; + + panel@0 { + compatible = "syna,td4101-panel"; + reg = <0>; + + backlight-gpios = <&gpd3 7 GPIO_ACTIVE_LOW>; + + width-mm = <62>; + height-mm = <110>; + + panel-timing { + clock-frequency = <69336720>; + + hactive = <540>; + hsync-len = <4>; + hfront-porch = <364>; + hback-porch = <40>; + + vactive = <960>; + vsync-len = <2>; + vfront-porch = <244>; + vback-porch = <13>; + }; + }; +}; + &gpu { status = "okay"; }; @@ -447,6 +476,7 @@ vmmc-supply = <&vdd_ldo26>; vqmmc-supply = <&vdd_ldo27>; + bus-width = <8>; fifo-depth = <64>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; diff --git a/dts/upstream/src/arm64/exynos/exynos7870-j6lte.dts b/dts/upstream/src/arm64/exynos/exynos7870-j6lte.dts index b8ce433b93b..09f2367cfec 100644 --- a/dts/upstream/src/arm64/exynos/exynos7870-j6lte.dts +++ b/dts/upstream/src/arm64/exynos/exynos7870-j6lte.dts @@ -27,20 +27,7 @@ }; chosen { - #address-cells = <2>; - #size-cells = <1>; - ranges; - stdout-path = &serial2; - - framebuffer@67000000 { - compatible = "simple-framebuffer"; - reg = <0x0 0x67000000 (720 * 1480 * 4)>; - width = <720>; - height = <1480>; - stride = <(720 * 4)>; - format = "a8r8g8b8"; - }; }; gpio-hall-effect-sensor { @@ -119,8 +106,9 @@ pmsg-size = <0x4000>; }; - framebuffer@67000000 { + cont_splash_mem: framebuffer@67000000 { reg = <0x0 0x67000000 (720 * 1480 * 4)>; + iommu-addresses = <&decon 0x67000000 (720 * 1480 * 4)>; no-map; }; }; @@ -133,6 +121,28 @@ }; }; +&decon { + memory-region = <&cont_splash_mem>; + + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <16000000>; + samsung,pll-clock-frequency = <26000000>; + + status = "okay"; + + panel@0 { + compatible = "samsung,s6e8aa5x01-ams561ra01"; + reg = <0>; + }; +}; + &gpu { status = "okay"; }; @@ -430,6 +440,7 @@ vmmc-supply = <&vdd_ldo26>; vqmmc-supply = <&vdd_ldo27>; + bus-width = <8>; fifo-depth = <64>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; diff --git a/dts/upstream/src/arm64/exynos/exynos7870-on7xelte.dts b/dts/upstream/src/arm64/exynos/exynos7870-on7xelte.dts index b1d9eff5a82..29e124c72e9 100644 --- a/dts/upstream/src/arm64/exynos/exynos7870-on7xelte.dts +++ b/dts/upstream/src/arm64/exynos/exynos7870-on7xelte.dts @@ -27,20 +27,7 @@ }; chosen { - #address-cells = <2>; - #size-cells = <1>; - ranges; - stdout-path = &serial2; - - framebuffer@67000000 { - compatible = "simple-framebuffer"; - reg = <0x0 0x67000000 (1080 * 1920 * 4)>; - width = <1080>; - height = <1920>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - }; }; gpio-keys { @@ -108,8 +95,9 @@ pmsg-size = <0x4000>; }; - framebuffer@67000000 { + cont_splash_mem: framebuffer@67000000 { reg = <0x0 0x67000000 (1080 * 1920 * 4)>; + iommu-addresses = <&decon 0x67000000 (1080 * 1920 * 4)>; no-map; }; }; @@ -122,6 +110,47 @@ }; }; +&decon { + memory-region = <&cont_splash_mem>; + + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + samsung,burst-clock-frequency = <1001000000>; + samsung,esc-clock-frequency = <16000000>; + samsung,pll-clock-frequency = <26000000>; + + status = "okay"; + + panel@0 { + compatible = "syna,td4300-panel"; + reg = <0>; + + backlight-gpios = <&gpd3 5 GPIO_ACTIVE_LOW>; + + width-mm = <68>; + height-mm = <121>; + + panel-timing { + clock-frequency = <144389520>; + + hactive = <1080>; + hsync-len = <4>; + hfront-porch = <120>; + hback-porch = <32>; + + vactive = <1920>; + vsync-len = <2>; + vfront-porch = <21>; + vback-porch = <4>; + }; + }; +}; + &gpu { status = "okay"; }; @@ -463,6 +492,7 @@ vmmc-supply = <&vdd_ldo26>; vqmmc-supply = <&vdd_ldo27>; + bus-width = <8>; fifo-depth = <64>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; diff --git a/dts/upstream/src/arm64/exynos/exynos7870.dtsi b/dts/upstream/src/arm64/exynos/exynos7870.dtsi index d5d347623b9..2827e10d696 100644 --- a/dts/upstream/src/arm64/exynos/exynos7870.dtsi +++ b/dts/upstream/src/arm64/exynos/exynos7870.dtsi @@ -178,6 +178,14 @@ "samsung,exynos7-pmu", "syscon"; reg = <0x10480000 0x10000>; + mipi_phy: mipi-phy { + compatible = "samsung,exynos7870-mipi-video-phy"; + #phy-cells = <1>; + + samsung,cam0-sysreg = <&syscon_cam0>; + samsung,disp-sysreg = <&syscon_disp>; + }; + reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x080c>; @@ -675,6 +683,77 @@ <&cmu_mif CLK_GOUT_MIF_CMU_ISP_VRA>; }; + syscon_cam0: system-controller@144f1040 { + compatible = "samsung,exynos7870-cam0-sysreg", "syscon"; + reg = <0x144f1040 0x04>; + }; + + dsi: dsi@14800000 { + compatible = "samsung,exynos7870-mipi-dsi"; + reg = <0x14800000 0x100>; + interrupts = ; + + clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_BUS_DISP>, + <&cmu_dispaud CLK_GOUT_DISPAUD_APB_DISP>, + <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER>, + <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER>; + clock-names = "bus", "pll", "byte", "esc"; + + phys = <&mipi_phy 1>; + phy-names = "dsim"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_to_decon: endpoint { + remote-endpoint = <&decon_to_dsi>; + }; + }; + }; + }; + + decon: display-controller@14830000 { + compatible = "samsung,exynos7870-decon"; + reg = <0x14830000 0x8000>; + interrupts = , + , + ; + interrupt-names = "fifo", "vsync", "lcd_sys"; + + clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_PLL>, + <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_BUS_USER>, + <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_DECON_ECLK>, + <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_DECON_VCLK>; + clock-names = "pclk_decon0", "aclk_decon0", + "decon0_eclk", "decon0_vclk"; + + iommus = <&sysmmu_decon>; + + status = "disabled"; + + port { + decon_to_dsi: endpoint { + remote-endpoint = <&dsi_to_decon>; + }; + }; + }; + + sysmmu_decon: iommu@14860000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14860000 0x1000>; + interrupts = ; + #iommu-cells = <0>; + + clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_MUX_BUS_USER>; + clock-names = "sysmmu"; + }; + pinctrl_dispaud: pinctrl@148c0000 { compatible = "samsung,exynos7870-pinctrl"; reg = <0x148c0000 0x1000>; @@ -692,6 +771,11 @@ <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK>, <&cmu_mif CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK>; }; + + syscon_disp: system-controller@148f100c { + compatible = "samsung,exynos7870-disp-sysreg", "syscon"; + reg = <0x148f100c 0x04>; + }; }; timer { diff --git a/dts/upstream/src/arm64/exynos/exynos990.dtsi b/dts/upstream/src/arm64/exynos/exynos990.dtsi index 7179109c49d..f8e2a31b4b7 100644 --- a/dts/upstream/src/arm64/exynos/exynos990.dtsi +++ b/dts/upstream/src/arm64/exynos/exynos990.dtsi @@ -260,6 +260,12 @@ clock-names = "oscclk", "bus", "ip"; }; + sysreg_peric0: syscon@10420000 { + compatible = "samsung,exynos990-peric0-sysreg", "syscon"; + reg = <0x10420000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PCLK>; + }; + pinctrl_peric0: pinctrl@10430000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10430000 0x1000>; @@ -277,6 +283,12 @@ clock-names = "oscclk", "bus", "ip"; }; + sysreg_peric1: syscon@10720000 { + compatible = "samsung,exynos990-peric1-sysreg", "syscon"; + reg = <0x10720000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PCLK>; + }; + pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10730000 0x1000>; diff --git a/dts/upstream/src/arm64/exynos/exynosautov920.dtsi b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi index 0fdf2062930..6ee74d26077 100644 --- a/dts/upstream/src/arm64/exynos/exynosautov920.dtsi +++ b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi @@ -1449,11 +1449,37 @@ status = "disabled"; }; + cmu_mfc: clock-controller@19c00000 { + compatible = "samsung,exynosautov920-cmu-mfc"; + reg = <0x19c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_MFC_MFC>, + <&cmu_top DOUT_CLKCMU_MFC_WFD>; + clock-names = "oscclk", + "mfc", + "wfd"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; }; + cmu_m2m: clock-controller@1a800000 { + compatible = "samsung,exynosautov920-cmu-m2m"; + reg = <0x1a800000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_M2M_NOC>, + <&cmu_top DOUT_CLKCMU_M2M_JPEG>; + clock-names = "oscclk", + "noc", + "jpeg"; + }; + cmu_cpucl0: clock-controller@1ec00000 { compatible = "samsung,exynosautov920-cmu-cpucl0"; reg = <0x1ec00000 0x8000>; diff --git a/dts/upstream/src/arm64/exynos/google/gs101-pixel-common.dtsi b/dts/upstream/src/arm64/exynos/google/gs101-pixel-common.dtsi index 84ff3e047d3..93892adaa67 100644 --- a/dts/upstream/src/arm64/exynos/google/gs101-pixel-common.dtsi +++ b/dts/upstream/src/arm64/exynos/google/gs101-pixel-common.dtsi @@ -109,6 +109,13 @@ system-power-controller; wakeup-source; + clocks { + compatible = "samsung,s2mpg10-clk"; + #clock-cells = <1>; + clock-output-names = "rtc32k_ap", "peri32k1", + "peri32k2"; + }; + regulators { }; }; diff --git a/dts/upstream/src/arm64/exynos/google/gs101.dtsi b/dts/upstream/src/arm64/exynos/google/gs101.dtsi index 31c99526470..d06d1d05f36 100644 --- a/dts/upstream/src/arm64/exynos/google/gs101.dtsi +++ b/dts/upstream/src/arm64/exynos/google/gs101.dtsi @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -72,80 +73,96 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0000>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; + operating-points-v2 = <&cpucl0_opp_table>; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0100>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; + operating-points-v2 = <&cpucl0_opp_table>; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0200>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; + operating-points-v2 = <&cpucl0_opp_table>; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0300>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; enable-method = "psci"; cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; + operating-points-v2 = <&cpucl0_opp_table>; }; cpu4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0400>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; + operating-points-v2 = <&cpucl1_opp_table>; }; cpu5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0500>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; enable-method = "psci"; cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; + operating-points-v2 = <&cpucl1_opp_table>; }; cpu6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-x1"; reg = <0x0600>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; + operating-points-v2 = <&cpucl2_opp_table>; }; cpu7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-x1"; reg = <0x0700>; + clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; enable-method = "psci"; cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; + operating-points-v2 = <&cpucl2_opp_table>; }; idle-states { @@ -183,6 +200,273 @@ }; }; + cpucl0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <537500>; + clock-latency-ns = <500000>; + }; + + opp-574000000 { + opp-hz = /bits/ 64 <574000000>; + opp-microvolt = <600000>; + clock-latency-ns = <500000>; + }; + + opp-738000000 { + opp-hz = /bits/ 64 <738000000>; + opp-microvolt = <618750>; + clock-latency-ns = <500000>; + }; + + opp-930000000 { + opp-hz = /bits/ 64 <930000000>; + opp-microvolt = <668750>; + clock-latency-ns = <500000>; + }; + + opp-1098000000 { + opp-hz = /bits/ 64 <1098000000>; + opp-microvolt = <712500>; + clock-latency-ns = <500000>; + }; + + opp-1197000000 { + opp-hz = /bits/ 64 <1197000000>; + opp-microvolt = <731250>; + clock-latency-ns = <500000>; + }; + + opp-1328000000 { + opp-hz = /bits/ 64 <1328000000>; + opp-microvolt = <762500>; + clock-latency-ns = <500000>; + }; + + opp-1401000000 { + opp-hz = /bits/ 64 <1401000000>; + opp-microvolt = <781250>; + clock-latency-ns = <500000>; + }; + + opp-1598000000 { + opp-hz = /bits/ 64 <1598000000>; + opp-microvolt = <831250>; + clock-latency-ns = <500000>; + }; + + opp-1704000000 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <862500>; + clock-latency-ns = <500000>; + }; + + opp-1803000000 { + opp-hz = /bits/ 64 <1803000000>; + opp-microvolt = <906250>; + clock-latency-ns = <500000>; + }; + }; + + cpucl1_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <506250>; + clock-latency-ns = <500000>; + }; + + opp-553000000 { + opp-hz = /bits/ 64 <553000000>; + opp-microvolt = <537500>; + clock-latency-ns = <500000>; + }; + + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <562500>; + clock-latency-ns = <500000>; + }; + + opp-799000000 { + opp-hz = /bits/ 64 <799000000>; + opp-microvolt = <581250>; + clock-latency-ns = <500000>; + }; + + opp-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <606250>; + clock-latency-ns = <500000>; + }; + + opp-1024000000 { + opp-hz = /bits/ 64 <1024000000>; + opp-microvolt = <625000>; + clock-latency-ns = <500000>; + }; + + opp-1197000000 { + opp-hz = /bits/ 64 <1197000000>; + opp-microvolt = <662500>; + clock-latency-ns = <500000>; + }; + + opp-1328000000 { + opp-hz = /bits/ 64 <1328000000>; + opp-microvolt = <687500>; + clock-latency-ns = <500000>; + }; + + opp-1491000000 { + opp-hz = /bits/ 64 <1491000000>; + opp-microvolt = <731250>; + clock-latency-ns = <500000>; + }; + + opp-1663000000 { + opp-hz = /bits/ 64 <1663000000>; + opp-microvolt = <775000>; + clock-latency-ns = <500000>; + }; + + opp-1836000000 { + opp-hz = /bits/ 64 <1836000000>; + opp-microvolt = <818750>; + clock-latency-ns = <500000>; + }; + + opp-1999000000 { + opp-hz = /bits/ 64 <1999000000>; + opp-microvolt = <868750>; + clock-latency-ns = <500000>; + }; + + opp-2130000000 { + opp-hz = /bits/ 64 <2130000000>; + opp-microvolt = <918750>; + clock-latency-ns = <500000>; + }; + + opp-2253000000 { + opp-hz = /bits/ 64 <2253000000>; + opp-microvolt = <968750>; + clock-latency-ns = <500000>; + }; + }; + + cpucl2_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <500000>; + clock-latency-ns = <500000>; + }; + + opp-851000000 { + opp-hz = /bits/ 64 <851000000>; + opp-microvolt = <556250>; + clock-latency-ns = <500000>; + }; + + opp-984000000 { + opp-hz = /bits/ 64 <984000000>; + opp-microvolt = <575000>; + clock-latency-ns = <500000>; + }; + + opp-1106000000 { + opp-hz = /bits/ 64 <1106000000>; + opp-microvolt = <606250>; + clock-latency-ns = <500000>; + }; + + opp-1277000000 { + opp-hz = /bits/ 64 <1277000000>; + opp-microvolt = <631250>; + clock-latency-ns = <500000>; + }; + + opp-1426000000 { + opp-hz = /bits/ 64 <1426000000>; + opp-microvolt = <662500>; + clock-latency-ns = <500000>; + }; + + opp-1582000000 { + opp-hz = /bits/ 64 <1582000000>; + opp-microvolt = <693750>; + clock-latency-ns = <500000>; + }; + + opp-1745000000 { + opp-hz = /bits/ 64 <1745000000>; + opp-microvolt = <731250>; + clock-latency-ns = <500000>; + }; + + opp-1826000000 { + opp-hz = /bits/ 64 <1826000000>; + opp-microvolt = <750000>; + clock-latency-ns = <500000>; + }; + + opp-2048000000 { + opp-hz = /bits/ 64 <2048000000>; + opp-microvolt = <793750>; + clock-latency-ns = <500000>; + }; + + opp-2188000000 { + opp-hz = /bits/ 64 <2188000000>; + opp-microvolt = <831250>; + clock-latency-ns = <500000>; + }; + + opp-2252000000 { + opp-hz = /bits/ 64 <2252000000>; + opp-microvolt = <850000>; + clock-latency-ns = <500000>; + }; + + opp-2401000000 { + opp-hz = /bits/ 64 <2401000000>; + opp-microvolt = <887500>; + clock-latency-ns = <500000>; + }; + + opp-2507000000 { + opp-hz = /bits/ 64 <2507000000>; + opp-microvolt = <925000>; + clock-latency-ns = <500000>; + }; + + opp-2630000000 { + opp-hz = /bits/ 64 <2630000000>; + opp-microvolt = <968750>; + clock-latency-ns = <500000>; + }; + + opp-2704000000 { + opp-hz = /bits/ 64 <2704000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + + opp-2802000000 { + opp-hz = /bits/ 64 <2802000000>; + opp-microvolt = <1056250>; + clock-latency-ns = <500000>; + }; + }; + /* ect node is required to be present by bootloader */ ect { }; @@ -202,6 +486,7 @@ firmware { acpm_ipc: power-management { compatible = "google,gs101-acpm-ipc"; + #clock-cells = <1>; mboxes = <&ap2apm_mailbox>; shmem = <&apm_sram>; }; @@ -288,13 +573,19 @@ cmu_misc: clock-controller@10010000 { compatible = "google,gs101-cmu-misc"; - reg = <0x10010000 0x8000>; + reg = <0x10010000 0x10000>; #clock-cells = <1>; clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, <&cmu_top CLK_DOUT_CMU_MISC_SSS>; clock-names = "bus", "sss"; }; + sysreg_misc: syscon@10030000 { + compatible = "google,gs101-misc-sysreg", "syscon"; + reg = <0x10030000 0x10000>; + clocks = <&cmu_misc CLK_GOUT_MISC_SYSREG_MISC_PCLK>; + }; + timer@10050000 { compatible = "google,gs101-mct", "samsung,exynos4210-mct"; @@ -365,7 +656,7 @@ cmu_peric0: clock-controller@10800000 { compatible = "google,gs101-cmu-peric0"; - reg = <0x10800000 0x4000>; + reg = <0x10800000 0x10000>; #clock-cells = <1>; clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, @@ -911,7 +1202,7 @@ cmu_peric1: clock-controller@10c00000 { compatible = "google,gs101-cmu-peric1"; - reg = <0x10c00000 0x4000>; + reg = <0x10c00000 0x10000>; #clock-cells = <1>; clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, @@ -1265,7 +1556,7 @@ cmu_hsi0: clock-controller@11000000 { compatible = "google,gs101-cmu-hsi0"; - reg = <0x11000000 0x4000>; + reg = <0x11000000 0x10000>; #clock-cells = <1>; clocks = <&ext_24_5m>, @@ -1277,6 +1568,12 @@ "usbdpdbg"; }; + sysreg_hsi0: syscon@11020000 { + compatible = "google,gs101-hsi0-sysreg", "syscon"; + reg = <0x11020000 0x10000>; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_SYSREG_HSI0_PCLK>; + }; + usbdrd31_phy: phy@11100000 { compatible = "google,gs101-usb31drd-phy"; reg = <0x11100000 0x0200>, @@ -1332,7 +1629,7 @@ cmu_hsi2: clock-controller@14400000 { compatible = "google,gs101-cmu-hsi2"; - reg = <0x14400000 0x4000>; + reg = <0x14400000 0x10000>; #clock-cells = <1>; clocks = <&ext_24_5m>, <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, @@ -1395,16 +1692,16 @@ cmu_apm: clock-controller@17400000 { compatible = "google,gs101-cmu-apm"; - reg = <0x17400000 0x8000>; + reg = <0x17400000 0x10000>; #clock-cells = <1>; clocks = <&ext_24_5m>; clock-names = "oscclk"; }; - sysreg_apm: syscon@174204e0 { + sysreg_apm: syscon@17420000 { compatible = "google,gs101-apm-sysreg", "syscon"; - reg = <0x174204e0 0x1000>; + reg = <0x17420000 0x10000>; }; pmu_system_controller: system-controller@17460000 { @@ -1497,7 +1794,7 @@ cmu_top: clock-controller@1e080000 { compatible = "google,gs101-cmu-top"; - reg = <0x1e080000 0x8000>; + reg = <0x1e080000 0x10000>; #clock-cells = <1>; clocks = <&ext_24_5m>; diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi index fc3e138077b..ef80bf6a604 100644 --- a/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi +++ b/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi @@ -493,10 +493,11 @@ }; usb0: usb@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1012a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi index 7d172d7e573..e7f9c931931 100644 --- a/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi +++ b/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi @@ -613,9 +613,11 @@ }; usb0: usb@3100000 { - compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; + compatible = "fsl,ls1028a-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; + iommus = <&smmu 1>; + dma-coherent; snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; @@ -623,9 +625,11 @@ }; usb1: usb@3110000 { - compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; + compatible = "fsl,ls1028a-dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; + iommus = <&smmu 2>; + dma-coherent; snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi index 73315c51703..50d9b03a284 100644 --- a/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi +++ b/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi @@ -833,10 +833,11 @@ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; usb0: usb@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; usb3-lpm-capable; @@ -845,10 +846,11 @@ }; usb1: usb@3000000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; usb3-lpm-capable; @@ -857,10 +859,11 @@ }; usb2: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1043a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; usb3-lpm-capable; diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts b/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts index 736722b58e7..48a6c08fcea 100644 --- a/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts +++ b/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts @@ -42,6 +42,21 @@ chosen { stdout-path = "serial0:115200n8"; }; + + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&sfp1_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&stat_pres2 6 GPIO_ACTIVE_LOW>; + }; + + sfp2: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&sfp2_i2c>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&stat_pres2 7 GPIO_ACTIVE_LOW>; + }; + }; &dspi { @@ -139,6 +154,31 @@ reg = <0x4c>; }; }; + + i2c@7 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@76 { + compatible = "nxp,pca9547"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + + sfp1_i2c: i2c@6 { + reg = <0x6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp2_i2c: i2c@7 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; }; @@ -166,8 +206,20 @@ fpga: board-control@2,0 { compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x2 0x0 0x0000100>; ranges = <0 2 0 0x100>; + + stat_pres2: gpio@c { + compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2"; + reg = <0xc 1>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SLOT1", "SLOT2", "SLOT3", "SLOT4", "SLOT5", "SLOT6", + "SFP1_MOD_DEF", "SFP2_MOD_DEF"; + }; }; }; diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi index 770d91ef031..22173d69713 100644 --- a/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi +++ b/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi @@ -749,10 +749,11 @@ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; usb0: usb@2f00000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; @@ -760,10 +761,11 @@ }; usb1: usb@3000000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; @@ -771,10 +773,11 @@ }; usb2: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1046a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1088a-ten64.dts b/dts/upstream/src/arm64/freescale/fsl-ls1088a-ten64.dts index 3a11068f221..71765ec9174 100644 --- a/dts/upstream/src/arm64/freescale/fsl-ls1088a-ten64.dts +++ b/dts/upstream/src/arm64/freescale/fsl-ls1088a-ten64.dts @@ -253,6 +253,10 @@ reg = <0x2d>; }; + uc: board-controller@7e { + compatible = "traverse,ten64-controller"; + reg = <0x7e>; + }; }; &i2c2 { diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi index 9d5726378aa..b2f6cd237be 100644 --- a/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi +++ b/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi @@ -489,10 +489,12 @@ }; usb0: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + iommus = <&smmu 1>; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; @@ -500,10 +502,12 @@ }; usb1: usb@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,ls1088a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; dr_mode = "host"; + iommus = <&smmu 2>; + dma-coherent; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-qds.dts b/dts/upstream/src/arm64/freescale/fsl-lx2160a-qds.dts index 2d01e20b47e..d8ef68ad3bc 100644 --- a/dts/upstream/src/arm64/freescale/fsl-lx2160a-qds.dts +++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-qds.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev2.dtsi" / { model = "NXP Layerscape LX2160AQDS"; diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-rdb.dts b/dts/upstream/src/arm64/freescale/fsl-lx2160a-rdb.dts index 0c44b3cbef7..935f421475a 100644 --- a/dts/upstream/src/arm64/freescale/fsl-lx2160a-rdb.dts +++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-rdb.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev2.dtsi" / { model = "NXP Layerscape LX2160ARDB"; @@ -31,6 +31,28 @@ regulator-boot-on; regulator-always-on; }; + + sfp2: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&sfp2_i2c>; + maximum-power-milliwatt = <2000>; + /* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */ + /* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */ + los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>; + }; + + sfp3: sfp-3 { + compatible = "sff,sfp"; + i2c-bus = <&sfp3_i2c>; + maximum-power-milliwatt = <2000>; + /* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */ + /* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */ + los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>; + }; }; &crypto { @@ -170,6 +192,37 @@ &i2c0 { status = "okay"; + cpld@66 { + compatible = "fsl,lx2160ardb-fpga"; + reg = <0x66>; + #address-cells = <1>; + #size-cells = <0>; + + sfp2_csr: gpio@19 { + compatible = "fsl,lx2160ardb-fpga-gpio-sfp"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SFP2_TX_EN", "", + "", "", + "SFP2_RX_LOS", "SFP2_TX_FAULT", + "", "SFP2_MOD_ABS"; + }; + + sfp3_csr: gpio@1a { + compatible = "fsl,lx2160ardb-fpga-gpio-sfp"; + reg = <0x1a>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SFP3_TX_EN", "", + "", "", + "SFP3_RX_LOS", "SFP3_TX_FAULT", + "", "SFP3_MOD_ABS"; + }; + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; @@ -205,6 +258,31 @@ vcc-supply = <&sb_3v3>; }; }; + + i2c@7 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + + i2c-mux@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + + sfp2_i2c: i2c@4 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp3_i2c: i2c@5 { + reg = <0x5>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; }; diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi index c9541403bcd..d899c0355e5 100644 --- a/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi +++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi @@ -1094,24 +1094,28 @@ }; usb0: usb@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; usb3-lpm-capable; + iommus = <&smmu 1>; + dma-coherent; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; }; usb1: usb@3110000 { - compatible = "snps,dwc3"; + compatible = "fsl,lx2160a-dwc3", "fsl,ls1028a-dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; usb3-lpm-capable; + iommus = <&smmu 2>; + dma-coherent; snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; status = "disabled"; diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2162a-qds.dts b/dts/upstream/src/arm64/freescale/fsl-lx2162a-qds.dts index 9f5ff1ffe7d..7a595fddc02 100644 --- a/dts/upstream/src/arm64/freescale/fsl-lx2162a-qds.dts +++ b/dts/upstream/src/arm64/freescale/fsl-lx2162a-qds.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev2.dtsi" / { model = "NXP Layerscape LX2162AQDS"; diff --git a/dts/upstream/src/arm64/freescale/imx8-apalis-eval.dtsi b/dts/upstream/src/arm64/freescale/imx8-apalis-eval.dtsi index 311d4950793..06790255a76 100644 --- a/dts/upstream/src/arm64/freescale/imx8-apalis-eval.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-apalis-eval.dtsi @@ -109,7 +109,10 @@ status = "okay"; }; -/* TODO: Apalis BKL1_PWM */ +/* Apalis BKL1_PWM */ +&pwm_lvds1 { + status = "okay"; +}; /* Apalis DAP1 */ &sai1 { diff --git a/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.1.dtsi b/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.1.dtsi index 3d8731504ce..7022de46b8b 100644 --- a/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -196,7 +196,10 @@ status = "okay"; }; -/* TODO: Apalis BKL1_PWM */ +/* Apalis BKL1_PWM */ +&pwm_lvds1 { + status = "okay"; +}; /* Apalis DAP1 */ &sai1 { diff --git a/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi b/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi index 106e802a68b..12732ed7f81 100644 --- a/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -245,7 +245,10 @@ status = "okay"; }; -/* TODO: Apalis BKL1_PWM */ +/* Apalis BKL1_PWM */ +&pwm_lvds1 { + status = "okay"; +}; /* Apalis DAP1 */ &sai1 { diff --git a/dts/upstream/src/arm64/freescale/imx8-apalis-v1.1.dtsi b/dts/upstream/src/arm64/freescale/imx8-apalis-v1.1.dtsi index 86d018f470c..9153dddfd3b 100644 --- a/dts/upstream/src/arm64/freescale/imx8-apalis-v1.1.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-apalis-v1.1.dtsi @@ -18,7 +18,7 @@ brightness-levels = <0 45 63 88 119 158 203 255>; default-brightness-level = <4>; enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ - /* TODO: hook-up to Apalis BKL1_PWM */ + pwms = <&pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED>; status = "disabled"; }; @@ -31,12 +31,6 @@ 3000 1>; }; - /* TODO: LVDS Panel */ - - /* TODO: Shared PCIe/SATA Reference Clock */ - - /* TODO: PCIe Wi-Fi Reference Clock */ - /* * Power management bus used to control LDO1OUT of the * second PMIC PF8100. This is used for controlling voltage levels of @@ -83,8 +77,8 @@ gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; - regulator-name = "wifi_pwrdn_fake_regulator"; - regulator-settling-time-us = <100>; + regulator-name = "Wi-Fi_POWER_DOWN"; /* Wi-Fi module PDn */ + startup-delay-us = <100>; }; reg_pcie_switch: regulator-pcie-switch { @@ -232,6 +226,34 @@ spdif-out; }; + thermal-zones { + pmic-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + cooling-maps { + cooling_maps_map0: map0 { + trip = <&pmic_alert0>; + }; + }; + + trips { + pmic_alert0: trip0 { + hysteresis = <2000>; + temperature = <110000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + hysteresis = <2000>; + temperature = <125000>; + type = "critical"; + }; + }; + }; + }; + touchscreen: touchscreen { compatible = "toradex,vf50-touchscreen"; interrupt-parent = <&lsio_gpio3>; @@ -262,15 +284,15 @@ &adc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; }; &adc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_vref_1v8>; }; -/* TODO: Asynchronous Sample Rate Converter (ASRC) */ - &cpu_alert0 { temperature = <95000>; }; @@ -799,7 +821,10 @@ <&hsio_refa_clk>, <&hsio_per_clk>; }; -/* TODO: Apalis BKL1_PWM */ +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_bkl>; +}; /* Apalis DAP1 */ &sai1 { @@ -841,8 +866,6 @@ status = "okay"; }; -/* TODO: Thermal Zones */ - /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ /* Apalis USBH4 */ diff --git a/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi b/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi index c32a6947ae9..5e4233ccfde 100644 --- a/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi @@ -296,7 +296,8 @@ audio_subsys: bus@59000000 { , /* 20 unused */ , /* 21 */ , /* 22 unused */ - ; /* 23 unused */ + , /* 23 unused */ + ; power-domains = <&pd IMX_SC_R_DMA_0_CH0>, <&pd IMX_SC_R_DMA_0_CH1>, <&pd IMX_SC_R_DMA_0_CH2>, @@ -558,7 +559,8 @@ audio_subsys: bus@59000000 { , /* 7 unused */ , /* sai4 */ , - ; /* sai5 */ + , /* sai5 */ + ; power-domains = <&pd IMX_SC_R_DMA_1_CH0>, <&pd IMX_SC_R_DMA_1_CH1>, <&pd IMX_SC_R_DMA_1_CH2>, diff --git a/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi b/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi index ce6ef160fd5..176e2e332f8 100644 --- a/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi @@ -77,7 +77,11 @@ conn_subsys: bus@5b000000 { <&sdhc0_lpcg IMX_LPCG_CLK_5>, <&sdhc0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -88,6 +92,8 @@ conn_subsys: bus@5b000000 { <&sdhc1_lpcg IMX_LPCG_CLK_5>, <&sdhc1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; @@ -101,7 +107,11 @@ conn_subsys: bus@5b000000 { <&sdhc2_lpcg IMX_LPCG_CLK_5>, <&sdhc2_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -114,8 +124,9 @@ conn_subsys: bus@5b000000 { clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, <&enet0_lpcg IMX_LPCG_CLK_2>, <&enet0_lpcg IMX_LPCG_CLK_3>, - <&enet0_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + <&enet0_lpcg IMX_LPCG_CLK_0>, + <&enet0_lpcg IMX_LPCG_CLK_1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; @@ -134,8 +145,9 @@ conn_subsys: bus@5b000000 { clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, <&enet1_lpcg IMX_LPCG_CLK_2>, <&enet1_lpcg IMX_LPCG_CLK_3>, - <&enet1_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + <&enet1_lpcg IMX_LPCG_CLK_0>, + <&enet0_lpcg IMX_LPCG_CLK_1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; diff --git a/dts/upstream/src/arm64/freescale/imx8-ss-dma.dtsi b/dts/upstream/src/arm64/freescale/imx8-ss-dma.dtsi index 575be8115e4..4de78f870c0 100644 --- a/dts/upstream/src/arm64/freescale/imx8-ss-dma.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8-ss-dma.dtsi @@ -182,7 +182,8 @@ dma_subsys: bus@5a000000 { , , , - ; + , + ; power-domains = <&pd IMX_SC_R_DMA_2_CH0>, <&pd IMX_SC_R_DMA_2_CH1>, <&pd IMX_SC_R_DMA_2_CH2>, @@ -466,7 +467,8 @@ dma_subsys: bus@5a000000 { , , , - ; + , + ; power-domains = <&pd IMX_SC_R_DMA_3_CH0>, <&pd IMX_SC_R_DMA_3_CH1>, <&pd IMX_SC_R_DMA_3_CH2>, diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts b/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts index 25a77cac6f0..5c68d33e19f 100644 --- a/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts +++ b/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts @@ -598,6 +598,10 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart1>; status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; }; &lsio_mu5 { @@ -649,6 +653,7 @@ pinctrl-names = "default"; reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; + vpcie3v3aux-supply = <®_pcieb>; status = "okay"; }; @@ -775,8 +780,10 @@ }; &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; no-sd; no-sdio; @@ -785,12 +792,15 @@ }; &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + max-frequency = <100000000>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi b/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi index 72434529f78..7a191195dbd 100644 --- a/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi @@ -101,7 +101,8 @@ , /* gpt0 */ , /* gpt1 */ , /* gpt2 */ - ; /* gpt3 */ + , /* gpt3 */ + ; power-domains = <&pd IMX_SC_R_DMA_0_CH0>, <&pd IMX_SC_R_DMA_0_CH1>, <&pd IMX_SC_R_DMA_0_CH2>, @@ -145,7 +146,8 @@ , , , - ; + , + ; }; &edma3 { @@ -156,7 +158,8 @@ , , , - ; + , + ; }; &flexcan1 { diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi b/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi index da33a35c6d4..74f9ce49324 100644 --- a/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi @@ -7,6 +7,7 @@ /delete-node/ &fec2; /delete-node/ &usbotg3; /delete-node/ &usb3_phy; +/delete-node/ &usb3_lpcg; / { conn_enet0_root_clk: clock-conn-enet0-root { diff --git a/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi index ff7ca207523..6eab8a6001d 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi @@ -542,6 +542,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; vpcie-supply = <®_pcie0>; + supports-clkreq; status = "okay"; }; diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso new file mode 100644 index 00000000000..193fa9dc34d --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx8mm-phyboard-polis-peb-av-10.dtsi" + +&backlight { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + pwms = <&pwm4 0 50000 0>; + status = "okay"; +}; + +&bridge_out { + ti,lvds-vod-swing-clock-microvolt = <200000 600000>; + ti,lvds-vod-swing-data-microvolt = <200000 600000>; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel { + compatible = "edt,etml1010g3dra"; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&sn65dsi83 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso new file mode 100644 index 00000000000..fd819bd563b --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10-ph128800t006.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx8mm-phyboard-polis-peb-av-10.dtsi" + +&backlight { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + pwms = <&pwm4 0 50000 0>; + status = "okay"; +}; + +&bridge_out { + ti,lvds-vod-swing-clock-microvolt = <200000 600000>; + ti,lvds-vod-swing-data-microvolt = <200000 600000>; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel { + compatible = "powertip,ph128800t006-zhc01"; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&sn65dsi83 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi new file mode 100644 index 00000000000..bd1f255e15e --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include "imx8mm-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + power-supply = <®_vdd_3v3_s>; + status = "disabled"; + }; + + panel: panel { + backlight = <&backlight>; + power-supply = <®_vcc_3v3>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8_Audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_Analog"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-peb-av-10 { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clk IMX8MM_CLK_SAI5>; + }; + }; +}; + +&bridge_out { + remote-endpoint = <&panel_in>; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: codec@18 { + compatible = "ti,tlv320aic3007"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tlv320>; + #sound-dai-cells = <0>; + reg = <0x18>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x57>; + vcc-supply = <®_vdd_3v3_s>; + }; + + eeprom@5f { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x5f>; + size = <32>; + vcc-supply = <®_vdd_3v3_s>; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +&sai5 { + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <11289600>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + fsl,sai-mclk-direction-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iomuxc { + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2 + >; + }; + pinctrl_lcd: lcd0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x116 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso index 79e4c3710ac..28e8589f9f9 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso +++ b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso @@ -1,239 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright (C) 2025 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet */ /dts-v1/; /plugin/; -#include -#include -#include "imx8mm-pinfunc.h" - -&{/} { - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; - default-brightness-level = <6>; - pwms = <&pwm4 0 50000 0>; - power-supply = <®_vdd_3v3_s>; - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - brightness-levels = <0 4 8 16 32 64 128 255>; - }; - - panel { - compatible = "edt,etml1010g3dra"; - backlight = <&backlight>; - power-supply = <®_vcc_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&bridge_out>; - }; - }; - }; - - reg_sound_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8_Audio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_sound_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3_Analog"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound-peb-av-10 { - compatible = "simple-audio-card"; - simple-audio-card,name = "snd-peb-av-10"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,mclk-fs = <32>; - simple-audio-card,widgets = - "Line", "Line In", - "Speaker", "Speaker", - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Speaker", "SPOP", - "Speaker", "SPOM", - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In", - "MIC3R", "Microphone Jack", - "Microphone Jack", "Mic Bias"; - - simple-audio-card,cpu { - sound-dai = <&sai5>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clk IMX8MM_CLK_SAI5>; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - codec: codec@18 { - compatible = "ti,tlv320aic3007"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tlv320>; - #sound-dai-cells = <0>; - reg = <0x18>; - reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - ai3x-gpio-func = <0xd 0x0>; - ai3x-micbias-vg = <2>; - AVDD-supply = <®_sound_3v3>; - IOVDD-supply = <®_sound_3v3>; - DRVDD-supply = <®_sound_3v3>; - DVDD-supply = <®_sound_1v8>; - }; - - eeprom@57 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x57>; - vcc-supply = <®_vdd_3v3_s>; - }; - - eeprom@5f { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x5f>; - size = <32>; - vcc-supply = <®_vdd_3v3_s>; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_dsi { - samsung,esc-clock-frequency = <10000000>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&sai5 { - assigned-clocks = <&clk IMX8MM_CLK_SAI5>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; - assigned-clock-rates = <11289600>; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, - <&clk IMX8MM_AUDIO_PLL2_OUT>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", - "pll11k"; - fsl,sai-mclk-direction-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai5>; - #sound-dai-cells = <0>; - status = "okay"; -}; - -&sn65dsi83 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - bridge_in: endpoint { - remote-endpoint = <&dsi_out>; - data-lanes = <1 2 3 4>; - }; - }; - - port@2 { - reg = <2>; - bridge_out: endpoint { - remote-endpoint = <&panel_in>; - ti,lvds-vod-swing-clock-microvolt = <200000 600000>; - ti,lvds-vod-swing-data-microvolt = <200000 600000>; - }; - }; - }; -}; - -&iomuxc { - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2 - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2 - >; - }; - pinctrl_lcd: lcd0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12 - >; - }; - - pinctrl_sai5: sai5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 - MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 - >; - }; - - pinctrl_tlv320: tlv320grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 - >; - }; -}; +#include "imx8mm-phyboard-polis-peb-av-10.dtsi" diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso index a28f51ece93..1059c26990f 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso +++ b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso @@ -1,7 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright (C) 2025 PHYTEC Messtechnik GmbH - * Author: Janine Hagemann */ /dts-v1/; diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts index be470cfb03d..6043e7d1630 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/dts/upstream/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts @@ -1,7 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet */ /dts-v1/; @@ -285,6 +284,8 @@ over-current-active-low; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; + pinctrl-0 = <&pinctrl_usbotg1>; + pinctrl-names = "default"; srp-disable; vbus-supply = <®_usb_otg1_vbus>; status = "okay"; @@ -458,6 +459,12 @@ >; }; + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x00 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phycore-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-phycore-som.dtsi index 921a7f58fd4..3d66c670134 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-phycore-som.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mm-phycore-som.dtsi @@ -1,7 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright (C) 2022 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet */ #include "imx8mm.dtsi" @@ -288,6 +287,23 @@ reg = <0x2d>; vcc-supply = <®_vdd_1v8>; status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint {}; + }; + }; }; /* EEPROM */ @@ -305,6 +321,14 @@ }; }; +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; +}; + +&mipi_dsi_out { + remote-endpoint = <&bridge_in>; +}; + /* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts index 755cf9cacd2..2ecc8b3c67d 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts +++ b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts @@ -452,7 +452,7 @@ pinctrl_usbotg1: usbotg1grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x00 >; }; diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi index 37db4f0dd50..dca213c85cc 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi @@ -115,6 +115,7 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,tx-internal-delay = ; tx-fifo-depth = ; @@ -445,7 +446,7 @@ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x0 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi index 752caa38eb0..266038fbbef 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi @@ -351,17 +351,6 @@ >; }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts index c09b40fc6de..468c7e993c5 100644 --- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts +++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts @@ -253,6 +253,7 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,tx-internal-delay = ; tx-fifo-depth = ; diff --git a/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts b/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts index a5f52f60169..5aa0e2cd155 100644 --- a/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts +++ b/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts @@ -248,6 +248,7 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,tx-internal-delay = ; tx-fifo-depth = ; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aipstz.h b/dts/upstream/src/arm64/freescale/imx8mp-aipstz.h new file mode 100644 index 00000000000..6481c484ca3 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-aipstz.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX8MP_AIPSTZ_H +#define __IMX8MP_AIPSTZ_H + +/* consumer type - master or peripheral */ +#define IMX8MP_AIPSTZ_MASTER 0x0 +#define IMX8MP_AIPSTZ_PERIPH 0x1 + +/* master configuration options */ +#define IMX8MP_AIPSTZ_MPL (1 << 0) +#define IMX8MP_AIPSTZ_MTW (1 << 1) +#define IMX8MP_AIPSTZ_MTR (1 << 2) +#define IMX8MP_AIPSTZ_MBW (1 << 3) + +/* peripheral configuration options */ +#define IMX8MP_AIPSTZ_TP (1 << 0) +#define IMX8MP_AIPSTZ_WP (1 << 1) +#define IMX8MP_AIPSTZ_SP (1 << 2) +#define IMX8MP_AIPSTZ_BW (1 << 3) + +/* master ID definitions */ +#define IMX8MP_AIPSTZ_EDMA 0 /* AUDIOMIX EDMA */ +#define IMX8MP_AIPSTZ_CA53 1 /* Cortex-A53 cluster */ +#define IMX8MP_AIPSTZ_SDMA2 3 /* AUDIOMIX SDMA2 */ +#define IMX8MP_AIPSTZ_SDMA3 3 /* AUDIOMIX SDMA3 */ +#define IMX8MP_AIPSTZ_HIFI4 5 /* HIFI4 DSP */ +#define IMX8MP_AIPSTZ_CM7 6 /* Cortex-M7 */ + +#endif /* __IMX8MP_AIPSTZ_H */ diff --git a/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts b/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts index af02af9e533..9422beee30b 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts @@ -96,9 +96,9 @@ #address-cells = <1>; #size-cells = <0>; - ethphy0: ethernet-phy@0 { /* RTL8211E */ + ethphy0: ethernet-phy@1 { /* RTL8211E */ compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; + reg = <1>; reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; reset-assert-us = <20>; reset-deassert-us = <200000>; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts b/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts index d241db3743a..04619a72290 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts @@ -22,6 +22,18 @@ stdout-path = &uart2; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -222,6 +234,28 @@ }; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c4 { expander0: gpio@20 { compatible = "nxp,pca9535"; @@ -276,6 +310,10 @@ }; }; +&lcdif3 { + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -430,6 +468,15 @@ >; }; + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 diff --git a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts index ebdf13e97b4..3d18c964a22 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts @@ -88,6 +88,7 @@ color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */ pinctrl-0 = <&pinctrl_dhcom_e>; pinctrl-names = "default"; @@ -97,6 +98,7 @@ color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ pinctrl-0 = <&pinctrl_dhcom_f>; pinctrl-names = "default"; @@ -106,6 +108,7 @@ color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */ pinctrl-0 = <&pinctrl_dhcom_h>; pinctrl-names = "default"; @@ -115,6 +118,7 @@ color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ pinctrl-0 = <&pinctrl_dhcom_i>; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi index 68c2e0156a5..f8303b7e2bd 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi @@ -113,6 +113,7 @@ ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ compatible = "ethernet-phy-id0007.c110", "ethernet-phy-ieee802.3-c22"; + clocks = <&clk IMX8MP_CLK_ENET_QOS>; interrupt-parent = <&gpio3>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy0>; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts index 3730792daf5..c6facb2ad9a 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts @@ -442,6 +442,10 @@ status = "disabled";/* can2 pin conflict with pdm */ }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; @@ -710,6 +714,8 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie0>; + vpcie3v3aux-supply = <®_pcie0>; + supports-clkreq; status = "okay"; }; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso new file mode 100644 index 00000000000..7a7f27d6bb1 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-etml1010g3dra.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds1 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + pwms = <&pwm3 0 50000 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates = <0>, <506800000>; + status = "okay"; +}; + +&panel_lvds1 { + compatible = "edt,etml1010g3dra"; + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso new file mode 100644 index 00000000000..aceb5b6056e --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <2>; + pwms = <&pwm4 0 50000 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates = <0>, <506800000>; + status = "okay"; +}; + +&panel_lvds0 { + compatible = "edt,etml1010g3dra"; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso new file mode 100644 index 00000000000..559286f384b --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <2>; + pwms = <&pwm4 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates = <0>, <465500000>; + status = "okay"; +}; + +&panel_lvds0 { + compatible = "powertip,ph128800t006-zhc01"; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi new file mode 100644 index 00000000000..bb740f84585 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include "imx8mp-pinfunc.h" + +&{/} { + backlight_lvds0: backlight0 { + compatible = "pwm-backlight"; + pinctrl-0 = <&pinctrl_lvds0>; + pinctrl-names = "default"; + power-supply = <®_vcc_12v>; + status = "disabled"; + }; + + panel_lvds0: panel-lvds0 { + backlight = <&backlight_lvds0>; + power-supply = <®_vcc_3v3_sw>; + status = "disabled"; + + port { + panel0_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + + reg_vcc_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VCC_12V"; + }; + + reg_vcc_1v8_audio: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC_1V8_Audio"; + }; + + reg_vcc_3v3_analog: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3_Analog"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clk IMX8MP_CLK_SAI2>; + }; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + pinctrl-0 = <&pinctrl_tlv320>; + pinctrl-names = "default"; + #sound-dai-cells = <0>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_vcc_3v3_analog>; + DRVDD-supply = <®_vcc_3v3_analog>; + DVDD-supply = <®_vcc_1v8_audio>; + IOVDD-supply = <®_vcc_3v3_sw>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vcc_3v3_sw>; + }; +}; + +&ldb_lvds_ch0 { + remote-endpoint = <&panel0_in>; +}; + +&pwm4 { + pinctrl-0 = <&pinctrl_pwm4>; + pinctrl-names = "default"; +}; + +&sai2 { + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-names = "default"; + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1e2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1e2 + >; + }; + + pinctrl_lvds0: lvds0grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x12 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x12 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 + MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x16 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x16 + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso new file mode 100644 index 00000000000..95078618ee0 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-peb-av-10.dtso @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso new file mode 100644 index 00000000000..a39f83bf820 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-ph128800t006.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds1 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + pwms = <&pwm3 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates = <0>, <465500000>; + status = "okay"; +}; + + +&panel_lvds1 { + compatible = "powertip,ph128800t006-zhc01"; + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts index 43615230864..9687b4ded8f 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -1,14 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet */ /dts-v1/; #include #include -#include #include #include "imx8mp-phycore-som.dtsi" @@ -21,16 +19,12 @@ stdout-path = &uart1; }; - backlight_lvds: backlight { + backlight_lvds1: backlight1 { compatible = "pwm-backlight"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lvds1>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <11>; - enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; - num-interpolated-steps = <2>; + pinctrl-names = "default"; power-supply = <®_lvds1_reg_en>; - pwms = <&pwm3 0 50000 0>; + status = "disabled"; }; fan0: fan { @@ -43,10 +37,11 @@ #cooling-cells = <2>; }; - panel1_lvds: panel-lvds { - compatible = "edt,etml1010g3dra"; - backlight = <&backlight_lvds>; + panel_lvds1: panel-lvds1 { + /* compatible panel in overlay */ + backlight = <&backlight_lvds1>; power-supply = <®_vcc_3v3_sw>; + status = "disabled"; port { panel1_in: endpoint { @@ -232,32 +227,8 @@ }; }; -&lcdif2 { - status = "okay"; -}; - -&lvds_bridge { - status = "okay"; - - ports { - port@2 { - ldb_lvds_ch1: endpoint { - remote-endpoint = <&panel1_in>; - }; - }; - }; -}; - -&media_blk_ctrl { - /* - * The LVDS panel on this device uses 72.4 MHz pixel clock, - * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB - * serializer and LCDIFv3 scanout engine can reach accurate - * pixel clock of exactly 72.4 MHz. - */ - assigned-clock-rates = <500000000>, <200000000>, - <0>, <0>, <500000000>, - <506800000>; +&ldb_lvds_ch1 { + remote-endpoint = <&panel1_in>; }; &snvs_pwrkey { @@ -282,9 +253,8 @@ }; &pwm3 { - status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; + pinctrl-names = "default"; }; &rv3028 { diff --git a/dts/upstream/src/arm64/freescale/imx8mp-phycore-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-phycore-som.dtsi index 04f724c6ec2..88831c0fbb7 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-phycore-som.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mp-phycore-som.dtsi @@ -1,7 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (C) 2020 PHYTEC Messtechnik GmbH - * Author: Teresa Remmet */ #include diff --git a/dts/upstream/src/arm64/freescale/imx8mp-prt8ml.dts b/dts/upstream/src/arm64/freescale/imx8mp-prt8ml.dts new file mode 100644 index 00000000000..30616218017 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-prt8ml.dts @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Protonic Holland + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "Protonic PRT8ML"; + compatible = "prt,prt8ml", "fsl,imx8mp"; + + chosen { + stdout-path = &uart4; + }; + + pcie_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_refclk_oe: pcie0-refclk-oe { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_refclk>; + clocks = <&pcie_refclk>; + #clock-cells = <0>; + enable-gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&A53_0 { + cpu-supply = <&fan53555>; +}; + +&A53_1 { + cpu-supply = <&fan53555>; +}; + +&A53_2 { + cpu-supply = <&fan53555>; +}; + +&A53_3 { + cpu-supply = <&fan53555>; +}; + +&a53_opp_table { + opp-1200000000 { + opp-microvolt = <900000>; + }; + + opp-1600000000 { + opp-microvolt = <980000>; + }; + + /* Power supply insuffient for 1.8 GHz */ + /delete-node/ opp-1800000000; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + + /* Disable DMA to meet performance requirements */ + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + reset-gpios = <&gpio_exp_1 4 GPIO_ACTIVE_LOW>; + spi-cpha; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rj45_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + ethernet = <&fec>; + label = "cpu"; + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + + /* Unreliable at 1000Mbps, limit RGMII to 100Mbps */ + fixed-link { + full-duplex; + speed = <100>; + }; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii"; /* switch inserts delay */ + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + status = "okay"; + + fixed-link { + full-duplex; + speed = <100>; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + rj45_phy: ethernet-phy@2 { + reg = <2>; + reset-gpios = <&gpio_exp_1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + ak5558: codec@10 { + compatible = "asahi-kasei,ak5558"; + reg = <0x10>; + reset-gpios = <&gpio_exp_1 2 GPIO_ACTIVE_LOW>; + }; + + gpio_exp_1: gpio@25 { + compatible = "nxp,pca9571"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tps65987ddh_0: usb-pd@20 { + compatible = "ti,tps6598x"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65987ddh_0>; + interrupts-extended = <&gpio1 12 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio_exp_2: gpio@25 { + compatible = "nxp,pca9571"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + + c0-hreset-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + line-name = "c0-hreset"; + output-low; + }; + + c1-hreset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + line-name = "c1-hreset"; + output-low; + }; + }; + + fan53555: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan53555>; + regulator-name = "fan53555"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <980000>; + regulator-always-on; + regulator-boot-on; + fcs,suspend-voltage-selector = <1>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ak4458: codec@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + #sound-dai-cells = <0>; + reset-gpios = <&gpio_exp_2 5 GPIO_ACTIVE_LOW>; + }; + + tps65987ddh_1: usb-pd@20 { + compatible = "ti,tps6598x"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65987ddh_1>; + interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lcdif1 { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <100000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + no-1-8-v; + sd-uhs-sdr12; + sd-uhs-sdr25; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x154 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x154 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x154 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x154 + >; + }; + + pinctrl_fan53555: fan53555grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x114 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x400000c3 + MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x400000c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400000c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400000c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400000c3 + >; + }; + + pinctrl_pcie_refclk: pcierefclkgrp { + fsl,pins = < + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0xc6 + >; + }; + + pinctrl_tps65987ddh_0: tps65987ddh-0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x1d0 + >; + }; + + pinctrl_tps65987ddh_1: tps65987ddh-1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1d0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x040 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0d4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-revc-hdmi.dts b/dts/upstream/src/arm64/freescale/imx8mp-skov-revc-hdmi.dts new file mode 100644 index 00000000000..c263e8fd048 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-revc-hdmi.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "imx8mp-skov-revb-hdmi.dts" + +/ { + model = "SKOV IMX8MP CPU revC - HDMI"; + compatible = "skov,imx8mp-skov-revc-hdmi", "fsl,imx8mp"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts b/dts/upstream/src/arm64/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts new file mode 100644 index 00000000000..3e320d6dea3 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-revc-jutouch-jt101tm023.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revC - JuTouch JT101TM023"; + compatible = "skov,imx8mp-skov-revc-jutouch-jt101tm023", "fsl,imx8mp"; + + panel { + compatible = "jutouch,jt101tm023"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@2a { + compatible = "eeti,exc81w32", "eeti,exc80h84"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + vdd-supply = <®_vdd_3v3>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ + assigned-clock-rates = <0>, <506800000>; + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&in_lvds0>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 4eedd00d83b..59642a8a2c4 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -238,6 +238,13 @@ audio-asrc = <&easrc>; audio-cpu = <&sai3>; audio-codec = <&tlv320aic3x04>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; }; thermal-zones { diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts b/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts index 88ad422c276..399230144ce 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts @@ -9,7 +9,7 @@ #include "imx8mp-tx8p-ml81.dtsi" / { - compatible = "gocontroll,moduline-display", "fsl,imx8mp"; + compatible = "gocontroll,moduline-display-106", "karo,tx8p-ml81", "fsl,imx8mp"; chassis-type = "embedded"; hardware = "Moduline Display V1.06"; model = "GOcontroll Moduline Display baseboard"; diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81.dtsi index fe8ba16eb40..761ee046eb7 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mp-tx8p-ml81.dtsi @@ -47,6 +47,7 @@ <&clk IMX8MP_SYS_PLL2_100M>, <&clk IMX8MP_SYS_PLL2_50M>; assigned-clock-rates = <266000000>, <100000000>, <50000000>; + nvmem-cells = <ð_mac1>; phy-handle = <ðphy0>; phy-mode = "rmii"; pinctrl-0 = <&pinctrl_eqos>; @@ -75,6 +76,10 @@ }; }; +&fec { + nvmem-cells = <ð_mac2>; +}; + &gpio1 { gpio-line-names = "SODIMM_152", "SODIMM_42", diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi index cbf0c9a740f..de852ebff57 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi @@ -101,6 +101,7 @@ reg = <0x0>; interrupt-parent = <&gpio3>; interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,tx-internal-delay = ; tx-fifo-depth = ; @@ -395,13 +396,6 @@ status = "okay"; }; -/* off-board header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - /* console */ &uart2 { pinctrl-names = "default"; @@ -409,25 +403,6 @@ status = "okay"; }; -/* off-board header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -/* off-board */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - status = "okay"; - bus-width = <4>; - non-removable; - status = "okay"; -}; - /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -464,7 +439,7 @@ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x0 >; }; @@ -523,13 +498,6 @@ >; }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - >; - }; - pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 @@ -537,24 +505,6 @@ >; }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi index cf747ec6fa1..76020ef89bf 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi @@ -365,17 +365,6 @@ >; }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts index 12de7cf1e85..7662663ff5d 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts +++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts @@ -228,6 +228,7 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; + ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,tx-internal-delay = ; tx-fifo-depth = ; diff --git a/dts/upstream/src/arm64/freescale/imx8mp.dtsi b/dts/upstream/src/arm64/freescale/imx8mp.dtsi index a3de6604e29..9b2b3a9bf9e 100644 --- a/dts/upstream/src/arm64/freescale/imx8mp.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8mp.dtsi @@ -13,6 +13,7 @@ #include #include +#include "imx8mp-aipstz.h" #include "imx8mp-pinfunc.h" / { @@ -80,6 +81,12 @@ operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; cpu-idle-states = <&cpu_pd_wait>; + + cpu0_therm: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <700>; + }; }; A53_1: cpu@1 { @@ -98,6 +105,12 @@ operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; cpu-idle-states = <&cpu_pd_wait>; + + cpu1_therm: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <700>; + }; }; A53_2: cpu@2 { @@ -116,6 +129,12 @@ operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; cpu-idle-states = <&cpu_pd_wait>; + + cpu2_therm: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <700>; + }; }; A53_3: cpu@3 { @@ -134,6 +153,12 @@ operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; cpu-idle-states = <&cpu_pd_wait>; + + cpu3_therm: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <700>; + }; }; A53_L2: l2-cache0 { @@ -323,7 +348,11 @@ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu0_therm 0 50>, + <&cpu1_therm 0 50>, + <&cpu2_therm 0 50>, + <&cpu3_therm 0 50>; }; }; }; @@ -356,7 +385,11 @@ <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu0_therm 0 50>, + <&cpu1_therm 0 50>, + <&cpu2_therm 0 50>, + <&cpu3_therm 0 50>; }; }; }; @@ -1396,12 +1429,14 @@ }; }; - aips5: bus@30c00000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30c00000 0x400000>; + aips5: bus@30df0000 { + compatible = "fsl,imx8mp-aipstz"; + reg = <0x30df0000 0x10000>; + power-domains = <&pgc_audio>; #address-cells = <1>; #size-cells = <1>; - ranges; + #access-controller-cells = <3>; + ranges = <0x30c00000 0x30c00000 0x400000>; spba-bus@30c00000 { compatible = "fsl,spba-bus", "simple-bus"; @@ -1770,6 +1805,7 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, <&clk IMX8MP_CLK_24M>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + fsl,num-channels = <3>; status = "disabled"; ports { @@ -1805,6 +1841,7 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, <&clk IMX8MP_CLK_24M>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + fsl,num-channels = <3>; status = "disabled"; ports { @@ -2073,7 +2110,7 @@ hdmi_pvi: display-bridge@32fc4000 { compatible = "fsl,imx8mp-hdmi-pvi"; - reg = <0x32fc4000 0x1000>; + reg = <0x32fc4000 0x800>; interrupt-parent = <&irqsteer_hdmi>; interrupts = <12>; power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; @@ -2099,6 +2136,23 @@ }; }; + hdmi_pai: audio-bridge@32fc4800 { + compatible = "fsl,imx8mp-hdmi-pai"; + reg = <0x32fc4800 0x800>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <14>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "apb"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI>; + status = "disabled"; + + port { + pai_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pai>; + }; + }; + }; + lcdif3: display-controller@32fc6000 { compatible = "fsl,imx8mp-lcdif"; reg = <0x32fc6000 0x1000>; @@ -2150,6 +2204,14 @@ reg = <1>; /* Point endpoint to the HDMI connector */ }; + + port@2 { + reg = <2>; + + hdmi_tx_from_pai: endpoint { + remote-endpoint = <&pai_to_hdmi_tx>; + }; + }; }; }; @@ -2445,6 +2507,11 @@ firmware-name = "imx/dsp/hifi4.bin"; resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; reset-names = "runstall"; + access-controllers = <&aips5 + IMX8MP_AIPSTZ_HIFI4 + IMX8MP_AIPSTZ_MASTER + (IMX8MP_AIPSTZ_MPL | IMX8MP_AIPSTZ_MTW | IMX8MP_AIPSTZ_MTR) + >; status = "disabled"; }; }; diff --git a/dts/upstream/src/arm64/freescale/imx8mq-evk.dts b/dts/upstream/src/arm64/freescale/imx8mq-evk.dts index a88bc903466..d48f901487d 100644 --- a/dts/upstream/src/arm64/freescale/imx8mq-evk.dts +++ b/dts/upstream/src/arm64/freescale/imx8mq-evk.dts @@ -375,6 +375,7 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&clk IMX8MQ_CLK_PCIE1_AUX>; vph-supply = <&vgen5_reg>; + supports-clkreq; status = "okay"; }; @@ -397,7 +398,9 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; vpcie-supply = <®_pcie1>; + vpcie3v3aux-supply = <®_pcie1>; vph-supply = <&vgen5_reg>; + supports-clkreq; status = "okay"; }; diff --git a/dts/upstream/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi b/dts/upstream/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi index b1c3f331c4e..8a37cbe922a 100644 --- a/dts/upstream/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi @@ -11,4 +11,12 @@ model = "Toradex Apalis iMX8QM V1.1"; }; -/* TODO: Cooling Maps */ +&cooling_maps_map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; diff --git a/dts/upstream/src/arm64/freescale/imx8qm-apalis.dtsi b/dts/upstream/src/arm64/freescale/imx8qm-apalis.dtsi index f97feee52c8..7594ac61fe5 100644 --- a/dts/upstream/src/arm64/freescale/imx8qm-apalis.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qm-apalis.dtsi @@ -314,8 +314,6 @@ ; }; -/* TODO: On-module Wi-Fi */ - /* Apalis MMC1 */ &usdhc2 { /* diff --git a/dts/upstream/src/arm64/freescale/imx8qm-mek.dts b/dts/upstream/src/arm64/freescale/imx8qm-mek.dts index 9c0b6b8d645..f1b0563d3a0 100644 --- a/dts/upstream/src/arm64/freescale/imx8qm-mek.dts +++ b/dts/upstream/src/arm64/freescale/imx8qm-mek.dts @@ -249,6 +249,13 @@ regulator-max-microvolt = <2800000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -256,6 +263,7 @@ regulator-max-microvolt = <3000000>; gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; enable-active-high; + off-on-delay-us = <4800>; }; reg_audio: regulator-audio { @@ -323,6 +331,15 @@ enable-active-high; }; + reg_usb_otg1_vbus: regulator-usbotg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; @@ -560,12 +577,14 @@ compatible = "isil,isl29023"; reg = <0x44>; interrupt-parent = <&lsio_gpio4>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; }; max7322: gpio@68 { @@ -686,6 +705,16 @@ status = "okay"; }; +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &lpuart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart2>; @@ -775,6 +804,8 @@ pinctrl-names = "default"; reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pciea>; + vpcie3v3aux-supply = <®_pciea>; + supports-clkreq; status = "okay"; }; @@ -800,8 +831,12 @@ }; &usdhc1 { - pinctrl-names = "default"; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; no-sd; no-sdio; @@ -810,8 +845,10 @@ }; &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; @@ -819,10 +856,25 @@ status = "okay"; }; +&usbphy1 { + status = "okay"; +}; + &usb3_phy { status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + &usbotg3 { status = "okay"; }; @@ -896,6 +948,38 @@ status = "okay"; }; +&thermal_zones { + pmic-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -1011,38 +1095,38 @@ pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp { fsl,pins = < - IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 - IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 - IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 + IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 0x00000020 >; }; pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp { fsl,pins = < - IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 - IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 - IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 + IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 0x00000020 >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < - IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 - IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 - IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 - IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 - IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 - IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 - IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 - IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 - IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 - IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 - IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 - IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 - IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 - IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 - IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 - IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 >; }; @@ -1092,6 +1176,15 @@ >; }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + pinctrl_lpuart2: lpuart2grp { fsl,pins = < IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 @@ -1201,6 +1294,12 @@ >; }; + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 @@ -1228,4 +1327,12 @@ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; }; diff --git a/dts/upstream/src/arm64/freescale/imx8qm-ss-audio.dtsi b/dts/upstream/src/arm64/freescale/imx8qm-ss-audio.dtsi index c9b55f02497..7c5386d4ab2 100644 --- a/dts/upstream/src/arm64/freescale/imx8qm-ss-audio.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qm-ss-audio.dtsi @@ -327,7 +327,8 @@ , /* sai2 */ , /* sai3 */ , /* sai4 */ - ; /* sai5 */ + , /* sai5 */ + ; power-domains = <&pd IMX_SC_R_DMA_2_CH0>, <&pd IMX_SC_R_DMA_2_CH1>, <&pd IMX_SC_R_DMA_2_CH2>, @@ -365,7 +366,8 @@ , /* no used */ , /* sai6 */ , - ; /* sai7 */ + , /* sai7 */ + ; power-domains = <&pd IMX_SC_R_DMA_3_CH0>, <&pd IMX_SC_R_DMA_3_CH1>, <&pd IMX_SC_R_DMA_3_CH2>, diff --git a/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi b/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi index d4856b8590e..974e193f8dc 100644 --- a/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi @@ -99,7 +99,8 @@ , , , - ; + , + ; power-domains = <&pd IMX_SC_R_DMA_0_CH0>, <&pd IMX_SC_R_DMA_0_CH1>, <&pd IMX_SC_R_DMA_0_CH2>, @@ -171,25 +172,25 @@ &lpuart0 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; - dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>; dma-names = "rx","tx"; }; &lpuart1 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; - dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; + dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>; dma-names = "rx","tx"; }; &lpuart2 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; - dmas = <&edma2 17 0 0>, <&edma2 16 0 1>; + dmas = <&edma2 16 0 FSL_EDMA_RX>, <&edma2 17 0 0>; dma-names = "rx","tx"; }; &lpuart3 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; - dmas = <&edma2 19 0 0>, <&edma2 18 0 1>; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 19 0 0>; dma-names = "rx","tx"; }; diff --git a/dts/upstream/src/arm64/freescale/imx8qm.dtsi b/dts/upstream/src/arm64/freescale/imx8qm.dtsi index 5206ca82eaf..cb66853b1cd 100644 --- a/dts/upstream/src/arm64/freescale/imx8qm.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qm.dtsi @@ -369,7 +369,7 @@ }; }; - thermal-zones { + thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <2000>; diff --git a/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts b/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts index 7b033744554..523f48896b6 100644 --- a/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts +++ b/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts @@ -150,6 +150,13 @@ regulator-max-microvolt = <2800000>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_pcieb: regulator-pcie { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; @@ -212,6 +219,15 @@ vin-supply = <®_can_en>; }; + reg_fec2_supply: regulator-fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usb_otg1_vbus: regulator-usbotg1-vbus { compatible = "regulator-fixed"; regulator-max-microvolt = <5000000>; @@ -397,6 +413,8 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + nvmem-cells = <&fec_mac0>; + nvmem-cell-names = "mac-address"; fsl,magic-packet; status = "okay"; @@ -408,9 +426,26 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; }; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + status = "disabled"; +}; + &i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -453,6 +488,8 @@ pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; }; }; @@ -586,6 +623,20 @@ status = "okay"; }; +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &jpegdec { status = "okay"; }; @@ -600,6 +651,16 @@ status = "okay"; }; +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &lpuart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart2>; @@ -631,6 +692,8 @@ pinctrl-names = "default"; reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; + vpcie3v3aux-supply = <®_pcieb>; + supports-clkreq; status = "okay"; }; @@ -729,9 +792,11 @@ &usdhc1 { assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; no-sd; no-sdio; @@ -742,8 +807,10 @@ &usdhc2 { assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; vmmc-supply = <®_usdhc2_vmmc>; cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; @@ -807,8 +874,8 @@ pinctrl_cm40_i2c: cm40i2cgrp { fsl,pins = < - IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c - IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c >; }; @@ -821,16 +888,16 @@ pinctrl_esai0: esai0grp { fsl,pins = < - IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 - IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 - IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 - IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 - IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 - IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 - IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 - IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 - IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 - IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 >; }; @@ -853,6 +920,23 @@ >; }; + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + pinctrl_flexcan1: flexcan0grp { fsl,pins = < IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 @@ -874,6 +958,27 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + pinctrl_ioexp_rst: ioexprstgrp { fsl,pins = < IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 @@ -900,17 +1005,26 @@ >; }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + pinctrl_lpuart2: lpuart2grp { fsl,pins = < - IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 - IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 >; }; pinctrl_lpuart3: lpuart3grp { fsl,pins = < - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 >; }; @@ -932,13 +1046,13 @@ pinctrl_typec: typecgrp { fsl,pins = < - IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 + IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 >; }; pinctrl_typec_mux: typecmuxgrp { fsl,pins = < - IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 >; }; @@ -953,11 +1067,11 @@ pinctrl_sai1: sai1grp { fsl,pins = < - IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 - IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 - IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 - IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 - IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 >; }; @@ -977,6 +1091,14 @@ >; }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 diff --git a/dts/upstream/src/arm64/freescale/imx8qxp.dtsi b/dts/upstream/src/arm64/freescale/imx8qxp.dtsi index 95edab05827..7c4a50e0ec9 100644 --- a/dts/upstream/src/arm64/freescale/imx8qxp.dtsi +++ b/dts/upstream/src/arm64/freescale/imx8qxp.dtsi @@ -234,11 +234,20 @@ compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; }; scu_key: keys { compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; linux,keycodes = ; + wakeup-source; status = "disabled"; }; diff --git a/dts/upstream/src/arm64/freescale/imx91-phyboard-segin.dts b/dts/upstream/src/arm64/freescale/imx91-phyboard-segin.dts new file mode 100644 index 00000000000..7b18a58024f --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx91-phyboard-segin.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner + * + * Product homepage: + * phyBOARD-Segin carrier board is reused for the i.MX91 design. + * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ + */ +/dts-v1/; + +#include "imx91-phycore-som.dtsi" + +/{ + model = "PHYTEC phyBOARD-Segin-i.MX91"; + compatible = "phytec,imx91-phyboard-segin", "phytec,imx91-phycore-som", + "fsl,imx91"; + + aliases { + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &i2c_rtc; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan1_tc: can-phy0 { + /* TI SN65HVD234D CAN-CC 1MBit/s */ + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_tc>; + enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + }; + + reg_sound_1v8: regulator-sound-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC1V8_AUDIO"; + }; + + reg_sound_3v3: regulator-sound-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC3V3_ANALOG"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_OTG1_VBUS"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_OTG2_VBUS"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_SD"; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + clocks = <&clk IMX93_CLK_SAI1>; + }; + }; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1561"; + reg = <2>; + clocks = <&clk IMX91_CLK_ENET2_REGULAR>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + }; +}; + +/* CAN */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + phys = <&flexcan1_tc>; + status = "okay"; +}; + +/* I2C2 */ +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Codec */ + audio_codec: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + }; + + /* RTC */ + i2c_rtc: rtc@68 { + compatible = "microcrystal,rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Audio */ +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <19200000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* USB */ +&usbphynop1 { + vbus-supply = <®_usb_otg1_vbus>; +}; + +&usbphynop2 { + vbus-supply = <®_usb_otg2_vbus>; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x4000050e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x50e + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e + MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + >; + }; + + pinctrl_flexcan1_tc: flexcan1tcgrp { + fsl,pins = < + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x31e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = < + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e + MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_UART2_RXD__SAI1_MCLK 0x1202 + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x1402 + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x1402 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x30e + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_default: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1386 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x159e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx91-phycore-som.dtsi b/dts/upstream/src/arm64/freescale/imx91-phycore-som.dtsi new file mode 100644 index 00000000000..29a428a052b --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx91-phycore-som.dtsi @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner + * + * Product homepage: + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ + */ + +#include + +#include "imx91.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX91"; + compatible = "phytec,imx91-phycore-som", "fsl,imx91"; + + aliases { + ethernet0 = &fec; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vdda_1v8: regulator-vdda-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDA_1V8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + vin-supply = <&buck5>; + }; +}; + +/* ADC */ +&adc1 { + vref-supply = <®_vdda_1v8>; +}; + +/* Ethernet */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <50000000>; + status = "okay"; + + mdio: mdio { + clock-frequency = <5000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + reset-assert-us = <30>; + }; + }; +}; + +/* I2C3 */ +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <610000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "VDDQ_0V6"; + regulator-max-microvolt = <600000>; + regulator-min-microvolt = <600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3_BUCK"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "VDD_1V1"; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "PMIC_SNVS_1V8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_0V8"; + regulator-max-microvolt = <800000>; + regulator-min-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + /* EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +/* Watchdog */ +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x50e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x502 + /* the three pins below are connected to PHYs straps, + * that is what the pull-up/down setting is for. + */ + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x37e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x37e + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x50e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x50e + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x50e + MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x4000050e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX91_PAD_I2C1_SDA__GPIO1_IO1 0x11e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x179e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1386 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x139e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13be + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x139e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x139e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x139e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x139e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x139e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x139e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13be + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13be + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13be + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13be + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13be + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13be + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13be + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx91_93_common.dtsi b/dts/upstream/src/arm64/freescale/imx91_93_common.dtsi index 52da571f26c..7958cef3537 100644 --- a/dts/upstream/src/arm64/freescale/imx91_93_common.dtsi +++ b/dts/upstream/src/arm64/freescale/imx91_93_common.dtsi @@ -706,7 +706,7 @@ }; flexspi1: spi@425e0000 { - compatible = "nxp,imx8mm-fspi"; + compatible = "nxp,imx93-fspi", "nxp,imx8mm-fspi"; reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; #address-cells = <1>; diff --git a/dts/upstream/src/arm64/freescale/imx93-phyboard-nash-jtag.dtso b/dts/upstream/src/arm64/freescale/imx93-phyboard-nash-jtag.dtso new file mode 100644 index 00000000000..89f93dca320 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx93-phyboard-nash-jtag.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +/* + * NOTE: Bind pinctrl_jtag to gpio2 so that the pinctrl settings are applied. + * JTAG itself has no dedicated driver, so without attaching it to an active + * device node (like gpio2), the pinmux configuration would not take effect. + */ +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_jtag>; +}; + +&iomuxc { + pinctrl_jtag: jtaggrp { + fsl,pins = < + MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x31e + MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x31e + MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x31e + MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x31e + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx93-phyboard-nash-pwm-fan.dtso b/dts/upstream/src/arm64/freescale/imx93-phyboard-nash-pwm-fan.dtso new file mode 100644 index 00000000000..d1adf04d56d --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx93-phyboard-nash-pwm-fan.dtso @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan>; + cooling-levels = <1 90 150 200 255>; + pwms = <&tpm6 1 40000 PWM_POLARITY_INVERTED>; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu_low: cpu-low { + hysteresis = <3000>; + temperature = <50000>; + type = "active"; + }; + + cpu_med: cpu-med { + hysteresis = <3000>; + temperature = <58000>; + type = "active"; + }; + + cpu_high: cpu-high { + hysteresis = <3000>; + temperature = <65000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + cooling-device = <&fan0 1 1>; + trip = <&cpu_low>; + }; + + map2 { + cooling-device = <&fan0 2 2>; + trip = <&cpu_med>; + }; + + map3 { + cooling-device = <&fan0 4 4>; + trip = <&cpu_high>; + }; + }; + }; + }; +}; + +&tpm6 { + status = "okay"; +}; + +&iomuxc { + pinctrl_fan: fangrp { + fsl,pins = < + MX93_PAD_GPIO_IO23__TPM6_CH1 0x31e + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx93-phyboard-nash.dts b/dts/upstream/src/arm64/freescale/imx93-phyboard-nash.dts index 5599e296919..9e875e082ee 100644 --- a/dts/upstream/src/arm64/freescale/imx93-phyboard-nash.dts +++ b/dts/upstream/src/arm64/freescale/imx93-phyboard-nash.dts @@ -71,6 +71,22 @@ io-channels = <&curr_sens 0>; }; + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB1_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB2_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; @@ -187,6 +203,14 @@ }; /* USB */ +&usbphynop1 { + vbus-supply = <®_usb1_vbus>; +}; + +&usbphynop2 { + vbus-supply = <®_usb2_vbus>; +}; + &usbotg1 { disable-over-current; dr_mode = "otg"; diff --git a/dts/upstream/src/arm64/freescale/imx93-phyboard-segin.dts b/dts/upstream/src/arm64/freescale/imx93-phyboard-segin.dts index 802d96b19e4..ac64abacc4a 100644 --- a/dts/upstream/src/arm64/freescale/imx93-phyboard-segin.dts +++ b/dts/upstream/src/arm64/freescale/imx93-phyboard-segin.dts @@ -59,6 +59,22 @@ regulator-name = "VCC3V3_ANALOG"; }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_OTG1_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_OTG2_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; enable-active-high; @@ -177,6 +193,14 @@ }; /* USB */ +&usbphynop1 { + vbus-supply = <®_usb_otg1_vbus>; +}; + +&usbphynop2 { + vbus-supply = <®_usb_otg2_vbus>; +}; + &usbotg1 { disable-over-current; dr_mode = "otg"; diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi b/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi index 82914ca148d..3a23e2eb9fe 100644 --- a/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi +++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi @@ -67,6 +67,7 @@ spi-max-frequency = <62000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5>; partitions { compatible = "fixed-partitions"; diff --git a/dts/upstream/src/arm64/freescale/imx93-var-som.dtsi b/dts/upstream/src/arm64/freescale/imx93-var-som.dtsi index a5f09487d80..2dc8b18ae91 100644 --- a/dts/upstream/src/arm64/freescale/imx93-var-som.dtsi +++ b/dts/upstream/src/arm64/freescale/imx93-var-som.dtsi @@ -12,7 +12,35 @@ model = "Variscite VAR-SOM-MX93 module"; compatible = "variscite,var-som-mx93", "fsl,imx93"; - mmc_pwrseq: mmc-pwrseq { + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + simple-audio-card,mclk-fs = <256>; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; + + usdhc3_pwrseq: mmc-pwrseq { compatible = "mmc-pwrseq-simple"; post-power-on-delay-ms = <100>; power-off-delay-us = <10000>; @@ -70,6 +98,175 @@ }; }; +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + pinctrl-2 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_GATE>; + clock-names = "mclk"; + AVDD-supply = <&buck5>; + CPVDD-supply = <&buck5>; + DBVDD-supply = <&buck4>; + DCVDD-supply = <&buck5>; + MICVDD-supply = <&buck5>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&lpspi8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi8>; + cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1000000>; + pendown-gpio = <&gpio4 29 0>; + vcc-supply = <&buck5>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + +/* BT module */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + /* eMMC */ &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -81,7 +278,27 @@ status = "okay"; }; +/* WiFi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + bus-width = <4>; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + wakeup-source; + status = "okay"; +}; + &iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e @@ -108,6 +325,68 @@ >; }; + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e + MX93_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e + >; + }; + + pinctrl_lpspi8: lpspi8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__GPIO2_IO12 0x31e + MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x31e + MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e + MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x31e + >; + }; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e + MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e + MX93_PAD_UART2_RXD__SAI1_MCLK 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1-sleepgrp { + fsl,pins = < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x31e + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x31e + MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x31e + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x31e + MX93_PAD_UART2_RXD__GPIO1_IO06 0x31e + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe @@ -123,4 +402,55 @@ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe >; }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 /* SDIO_B_CLK */ + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 /* SDIO_B_CMD */ + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 /* SDIO_B_D0 */ + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 /* SDIO_B_D1 */ + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 /* SDIO_B_D2 */ + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 /* SDIO_B_D3 */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e /* SDIO_B_CLK */ + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e /* SDIO_B_CMD */ + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e /* SDIO_B_D0 */ + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e /* SDIO_B_D1 */ + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e /* SDIO_B_D2 */ + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e /* SDIO_B_D3 */ + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe /* SDIO_B_CLK */ + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe /* SDIO_B_CMD */ + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe /* SDIO_B_D0 */ + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe /* SDIO_B_D1 */ + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe /* SDIO_B_D2 */ + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe /* SDIO_B_D3 */ + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x400 + MX93_PAD_SD3_CMD__GPIO3_IO21 0x400 + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x400 + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x400 + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x400 + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x400 + >; + }; + + pinctrl_usdhc3_wlan: usdhc3-wlangrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e /* WIFI_REG_ON */ + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x51e /* WIFI_PWR_EN */ + >; + }; }; diff --git a/dts/upstream/src/arm64/freescale/imx94.dtsi b/dts/upstream/src/arm64/freescale/imx94.dtsi index d4a880496b0..73184f03f8a 100644 --- a/dts/upstream/src/arm64/freescale/imx94.dtsi +++ b/dts/upstream/src/arm64/freescale/imx94.dtsi @@ -1190,5 +1190,11 @@ status = "disabled"; }; }; + + ddr-pmu@4e090dc0 { + compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu"; + reg = <0x0 0x4e090dc0 0x0 0x200>; + interrupts = ; + }; }; }; diff --git a/dts/upstream/src/arm64/freescale/imx95-15x15-evk.dts b/dts/upstream/src/arm64/freescale/imx95-15x15-evk.dts index 148243470dd..c1e245ecea9 100644 --- a/dts/upstream/src/arm64/freescale/imx95-15x15-evk.dts +++ b/dts/upstream/src/arm64/freescale/imx95-15x15-evk.dts @@ -61,6 +61,7 @@ fan0: pwm-fan { compatible = "pwm-fan"; + fan-supply = <®_vcc_12v>; #cooling-cells = <2>; cooling-levels = <64 128 192 255>; pwms = <&tpm6 0 4000000 PWM_POLARITY_INVERTED>; @@ -556,6 +557,8 @@ pinctrl-names = "default"; reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; vpcie-supply = <®_m2_pwr>; + vpcie3v3aux-supply = <®_m2_pwr>; + supports-clkreq; status = "okay"; }; diff --git a/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts index 9f968feccef..aaa0da55a22 100644 --- a/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts +++ b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts @@ -542,6 +542,8 @@ pinctrl-names = "default"; reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie0>; + vpcie3v3aux-supply = <®_pcie0>; + supports-clkreq; status = "okay"; }; @@ -557,6 +559,7 @@ pinctrl-names = "default"; reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; vpcie-supply = <®_slot_pwr>; + vpcie3v3aux-supply = <®_slot_pwr>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/freescale/imx95-19x19-verdin-evk.dts b/dts/upstream/src/arm64/freescale/imx95-19x19-verdin-evk.dts new file mode 100644 index 00000000000..2b0ff232f68 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx95-19x19-verdin-evk.dts @@ -0,0 +1,695 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 NXP + * Copyright 2025 Marek Vasut + */ + +/dts-v1/; + +#include +#include "imx95.dtsi" + +#define FALLING_EDGE 1 +#define RISING_EDGE 2 + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ + +/ { + model = "i.MX 95 Verdin Evaluation Kit (EVK)"; + compatible = "toradex,verdin-imx95-19x19-evk", "fsl,imx95"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + ethernet2 = &enetc_port2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 4 GPIO_ACTIVE_LOW>; + }; + + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "PCIE_WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&i2c7_pcal6524 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&i2c7_pcal6524 11 GPIO_ACTIVE_HIGH>; + }; + + sound-wm8904 { + compatible = "fsl,imx-audio-wm8904"; + model = "wm8904-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8904>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "AMIC", "MICBIAS", + "IN2L", "AMIC"; + }; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1_reset>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c4>; + status = "okay"; + + wm8904: codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + AVDD-supply = <®_1p8v>; + CPVDD-supply = <®_1p8v>; + DBVDD-supply = <®_1p8v>; + DCVDD-supply = <®_1p8v>; + MICVDD-supply = <®_1p8v>; + }; +}; + +&lpi2c5 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c5>; + status = "okay"; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c6>; + status = "okay"; +}; + +&lpi2c7 { + clock-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; + status = "okay"; + + i2c7_pcal6524: i2c7-gpio@23 { + compatible = "nxp,pcal6524"; + reg = <0x23>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; + + /* Current measurement at SoM 5V power output */ + hwmon@41 { + compatible = "ti,ina219"; + reg = <0x41>; + shunt-resistor = <10000>; + }; + + /* Current measurement at Board power input */ + hwmon@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <10000>; + }; + + eeprom@50 { + compatible = "st,24c02"; + reg = <0x50>; + }; + + ptn5110: tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + realtek,clkout-disable; + }; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&i2c7_pcal6524 17 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + orientation-switch; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_pcie0>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&scmi_misc { + nxp,ctrl-ids = ; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = + ; + }; + + pinctrl_emdio: emdiogrp { + fsl,pins = + , + ; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi1: flexspi1grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi1_reset: flexspi1-reset-grp { + fsl,pins = + ; + }; + + pinctrl_hp: hpgrp { + fsl,pins = + ; + }; + + pinctrl_i2c4_pcal6408: i2c4pcal6498grp { + fsl,pins = + ; + }; + + pinctrl_i2c7_pcal6524: i2c7pcal6524grp { + fsl,pins = + ; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = + , + ; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = + , + ; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = + , + ; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = + , + ; + }; + + pinctrl_pcal6416: pcal6416grp { + fsl,pins = + ; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = + ; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = + ; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = + , + ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = + ; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = + , + , + , + ; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = + , + , + , + , + ; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = + ; + }; + + pinctrl_typec: typecgrp { + fsl,pins = + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , + ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + , + , + , + , + , + ; + }; +}; diff --git a/arch/arm/dts/imx95-toradex-smarc-dev.dts b/dts/upstream/src/arm64/freescale/imx95-toradex-smarc-dev.dts similarity index 100% rename from arch/arm/dts/imx95-toradex-smarc-dev.dts rename to dts/upstream/src/arm64/freescale/imx95-toradex-smarc-dev.dts diff --git a/arch/arm/dts/imx95-toradex-smarc.dtsi b/dts/upstream/src/arm64/freescale/imx95-toradex-smarc.dtsi similarity index 99% rename from arch/arm/dts/imx95-toradex-smarc.dtsi rename to dts/upstream/src/arm64/freescale/imx95-toradex-smarc.dtsi index e99f1a57af8..115a16e44a9 100644 --- a/arch/arm/dts/imx95-toradex-smarc.dtsi +++ b/dts/upstream/src/arm64/freescale/imx95-toradex-smarc.dtsi @@ -112,8 +112,8 @@ compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - enable-active-high; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; off-on-delay-us = <100000>; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; @@ -406,8 +406,6 @@ "", "", "", - "", - "", "SMARC_SDIO_WP"; }; @@ -453,12 +451,14 @@ port@0 { reg = <0>; + sn65dsi86_in: endpoint { }; }; port@1 { reg = <1>; + sn65dsi86_out: endpoint { data-lanes = <3 2 1 0>; }; @@ -580,7 +580,7 @@ ethphy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&som_gpio_expander_1>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; }; diff --git a/dts/upstream/src/arm64/freescale/imx95-tqma9596sa-mb-smarc-2.dts b/dts/upstream/src/arm64/freescale/imx95-tqma9596sa-mb-smarc-2.dts index 5b6b2bb80b2..97726eded0f 100644 --- a/dts/upstream/src/arm64/freescale/imx95-tqma9596sa-mb-smarc-2.dts +++ b/dts/upstream/src/arm64/freescale/imx95-tqma9596sa-mb-smarc-2.dts @@ -39,6 +39,8 @@ serial5 = &lpuart6; serial6 = &lpuart7; serial7 = &lpuart8; + spi0 = &flexspi1; + spi1 = &lpspi3; }; chosen { @@ -144,6 +146,13 @@ model = "tqm-tlv320aic32"; audio-codec = <&tlv320aic3x04>; audio-cpu = <&sai3>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; }; }; @@ -172,15 +181,11 @@ }; &flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <®_3v3>; status = "okay"; }; &flexcan3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan3>; xceiver-supply = <®_3v3>; status = "okay"; }; @@ -204,15 +209,12 @@ }; &lpspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi3>; - cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; status = "okay"; }; /* SER0 */ &lpuart1 { - status = "disabled"; + status = "reserved"; }; /* SER3 */ @@ -232,27 +234,11 @@ /* X44 mPCIe */ &pcie0 { - pinctrl-0 = <&pinctrl_pcie0>; - pinctrl-names = "default"; - clocks = <&scmi_clk IMX95_CLK_HSIO>, - <&pcieclk 1>, - <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; - reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>; status = "okay"; }; /* X22 PCIe x1 socket */ &pcie1 { - pinctrl-0 = <&pinctrl_pcie1>; - pinctrl-names = "default"; - clocks = <&scmi_clk IMX95_CLK_HSIO>, - <&pcieclk 0>, - <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; - reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -261,39 +247,9 @@ }; &sai3 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>, - <&scmi_clk IMX95_CLK_AUDIOPLL2>, - <&scmi_clk IMX95_CLK_SAI3>; - assigned-clock-parents = <0>, <0>, <0>, <0>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>; - assigned-clock-rates = <3932160000>, - <3612672000>, <393216000>, - <361267200>, <12288000>; - fsl,sai-mclk-direction-output; status = "okay"; }; -&sai5 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai5>; - assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>, - <&scmi_clk IMX95_CLK_AUDIOPLL2>, - <&scmi_clk IMX95_CLK_SAI5>; - assigned-clock-parents = <0>, <0>, <0>, <0>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>; - assigned-clock-rates = <3932160000>, - <3612672000>, <393216000>, - <361267200>, <12288000>; -}; - /* X4 */ &usb2 { srp-disable; @@ -305,20 +261,9 @@ status = "okay"; }; - /* X16 */ &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pinctrl-3 = <&pinctrl_usdhc2>; - vmmc-supply = <®_sdvmmc>; - cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - no-1-8-v; no-mmc; no-sdio; - disable-wp; - bus-width = <4>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/freescale/imx95-tqma9596sa.dtsi b/dts/upstream/src/arm64/freescale/imx95-tqma9596sa.dtsi index 180124cc5bc..43418844701 100644 --- a/dts/upstream/src/arm64/freescale/imx95-tqma9596sa.dtsi +++ b/dts/upstream/src/arm64/freescale/imx95-tqma9596sa.dtsi @@ -106,16 +106,25 @@ status = "okay"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + &flexspi1 { - pinctrl-names = "default", "sleep"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi1>; - pinctrl-1 = <&pinctrl_flexspi1>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <66000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; vcc-supply = <®_1v8>; @@ -156,9 +165,8 @@ &lpi2c1 { clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpi2c1>; - pinctrl-1 = <&pinctrl_lpi2c1>; status = "okay"; tmp1075: temperature-sensor@4a { @@ -195,6 +203,7 @@ eeprom@58 { compatible = "atmel,24c64d-wl"; reg = <0x58>; + pagesize = <32>; vcc-supply = <®_1v8>; }; @@ -202,6 +211,7 @@ eeprom@5c { compatible = "atmel,24c64d-wl"; reg = <0x5c>; + pagesize = <32>; vcc-supply = <®_1v8>; }; @@ -255,9 +265,11 @@ /* I2C_CAM0 */ &lpi2c3 { clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-1 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; dp_bridge: dp-bridge@f { @@ -292,21 +304,31 @@ /* I2C_CAM1 */ &lpi2c4 { clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c4>; - pinctrl-1 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* I2C_LCD */ &lpi2c6 { clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c6>; - pinctrl-1 = <&pinctrl_lpi2c6>; + pinctrl-1 = <&pinctrl_lpi2c6_gpio>; + sda-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; +&lpspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; +}; + /* SER0 */ &lpuart1 { pinctrl-names = "default"; @@ -375,6 +397,63 @@ }; }; +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&pcieclk 1>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; + reset-gpios = <&expander2 9 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&pcieclk 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; + reset-gpios = <&expander2 10 GPIO_ACTIVE_LOW>; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; +}; + +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI5>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; +}; + &scmi_bbm { linux,code = ; }; @@ -425,11 +504,10 @@ }; &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - pinctrl-3 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; no-sdio; @@ -437,6 +515,18 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_sdvmmc>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + bus-width = <4>; +}; + &wdog3 { status = "okay"; }; @@ -497,12 +587,12 @@ }; pinctrl_flexspi1: flexspi1grp { - fsl,pins = , - , - , - , - , - ; + fsl,pins = , + , + , + , + , + ; }; pinctrl_gpio1: gpio1grp { @@ -527,14 +617,29 @@ ; }; + pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { + fsl,pins = , + ; + }; + pinctrl_lpi2c4: lpi2c4grp { - fsl,pins = , - ; + fsl,pins = , + ; + }; + + pinctrl_lpi2c4_gpio: lpi2c4-gpiogrp { + fsl,pins = , + ; }; pinctrl_lpi2c6: lpi2c6grp { - fsl,pins = , - ; + fsl,pins = , + ; + }; + + pinctrl_lpi2c6_gpio: lpi2c6-gpiogrp { + fsl,pins = , + ; }; pinctrl_lpspi3: lpspi3grp { @@ -617,7 +722,7 @@ fsl,pins = ; }; - pinctrl_tpm5: tpm4grp { + pinctrl_tpm5: tpm5grp { fsl,pins = ; }; diff --git a/dts/upstream/src/arm64/freescale/imx95.dtsi b/dts/upstream/src/arm64/freescale/imx95.dtsi index 6da961eb3fe..a4d85481755 100644 --- a/dts/upstream/src/arm64/freescale/imx95.dtsi +++ b/dts/upstream/src/arm64/freescale/imx95.dtsi @@ -250,6 +250,28 @@ clock-output-names = "dummy"; }; + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-hz-real = /bits/ 64 <500000000>; + opp-microvolt = <920000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-hz-real = /bits/ 64 <800000000>; + opp-microvolt = <920000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-hz-real = /bits/ 64 <1000000000>; + opp-microvolt = <920000>; + }; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -806,7 +828,7 @@ interrupts = ; #address-cells = <3>; #size-cells = <0>; - clocks = <&scmi_clk IMX95_CLK_BUSAON>, + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&scmi_clk IMX95_CLK_I3C2SLOW>; clock-names = "pclk", "fast_clk"; status = "disabled"; @@ -945,7 +967,7 @@ }; flexspi1: spi@425e0000 { - compatible = "nxp,imx8mm-fspi"; + compatible = "nxp,imx95-fspi", "nxp,imx8mm-fspi"; reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; reg-names = "fspi_base", "fspi_mmap"; #address-cells = <1>; @@ -2139,6 +2161,21 @@ }; }; + gpu: gpu@4d900000 { + compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; + reg = <0 0x4d900000 0 0x480000>; + clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; + clock-names = "core", "coregroup"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&scmi_devpd IMX95_PD_GPU>; + #cooling-cells = <2>; + dynamic-power-coefficient = <1013>; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>; diff --git a/dts/upstream/src/arm64/freescale/imx952-clock.h b/dts/upstream/src/arm64/freescale/imx952-clock.h new file mode 100644 index 00000000000..7d6f6635dc0 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx952-clock.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2025 NXP + */ + +#ifndef __CLOCK_IMX952_H__ +#define __CLOCK_IMX952_H__ + +/* Clock Source */ +#define IMX952_CLK_EXT 0 +#define IMX952_CLK_OSC32K 1 +#define IMX952_CLK_OSC24M 2 +#define IMX952_CLK_FRO 3 +#define IMX952_CLK_SYSPLL1_VCO 4 +#define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX952_CLK_SYSPLL1_PFD0 6 +#define IMX952_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX952_CLK_SYSPLL1_PFD1 9 +#define IMX952_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX952_CLK_SYSPLL1_PFD2 12 +#define IMX952_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX952_CLK_AUDIOPLL1_VCO 14 +#define IMX952_CLK_AUDIOPLL1 15 +#define IMX952_CLK_AUDIOPLL2_VCO 16 +#define IMX952_CLK_AUDIOPLL2 17 +#define IMX952_CLK_VIDEOPLL1_VCO 18 +#define IMX952_CLK_VIDEOPLL1 19 +#define IMX952_CLK_SRC_RESERVED20 20 +#define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21 +#define IMX952_CLK_SYSPLL1_PFD3 22 +#define IMX952_CLK_SYSPLL1_PFD3_DIV2 23 +#define IMX952_CLK_ARMPLL_VCO 24 +#define IMX952_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX952_CLK_ARMPLL_PFD0 26 +#define IMX952_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX952_CLK_ARMPLL_PFD1 28 +#define IMX952_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX952_CLK_ARMPLL_PFD2 30 +#define IMX952_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX952_CLK_ARMPLL_PFD3 32 +#define IMX952_CLK_DRAMPLL_VCO 33 +#define IMX952_CLK_DRAMPLL 34 +#define IMX952_CLK_HSIOPLL_VCO 35 +#define IMX952_CLK_HSIOPLL 36 +#define IMX952_CLK_LDBPLL_VCO 37 +#define IMX952_CLK_LDBPLL 38 +#define IMX952_CLK_EXT1 39 +#define IMX952_CLK_EXT2 40 + +/* Clock ROOT */ +#define IMX952_CLK_ADC 41 +#define IMX952_CLK_RESERVED1 42 +#define IMX952_CLK_BUSAON 43 +#define IMX952_CLK_CAN1 44 +#define IMX952_CLK_RESERVED4 45 +#define IMX952_CLK_I3C1SLOW 46 +#define IMX952_CLK_LPI2C1 47 +#define IMX952_CLK_LPI2C2 48 +#define IMX952_CLK_LPSPI1 49 +#define IMX952_CLK_LPSPI2 50 +#define IMX952_CLK_LPTMR1 51 +#define IMX952_CLK_LPUART1 52 +#define IMX952_CLK_LPUART2 53 +#define IMX952_CLK_M33 54 +#define IMX952_CLK_M33SYSTICK 55 +#define IMX952_CLK_RESERVED15 56 +#define IMX952_CLK_PDM 57 +#define IMX952_CLK_SAI1 58 +#define IMX952_CLK_RESERVED18 59 +#define IMX952_CLK_TPM2 60 +#define IMX952_CLK_RESERVED20 61 +#define IMX952_CLK_CAMAPB 62 +#define IMX952_CLK_CAMAXI 63 +#define IMX952_CLK_CAMCM0 64 +#define IMX952_CLK_CAMISI 65 +#define IMX952_CLK_CAMPHYCFG 66 +#define IMX952_CLK_MIPIPHYPLLBYPASS 67 +#define IMX952_CLK_RESERVED27 68 +#define IMX952_CLK_MIPITESTBYTE 69 +#define IMX952_CLK_A55 70 +#define IMX952_CLK_A55MTRBUS 71 +#define IMX952_CLK_A55PERIPH 72 +#define IMX952_CLK_DRAMALT 73 +#define IMX952_CLK_DRAMAPB 74 +#define IMX952_CLK_DISPAPB 75 +#define IMX952_CLK_DISPAXI 76 +#define IMX952_CLK_DISPLPSPI 77 +#define IMX952_CLK_DISPOCRAM 78 +#define IMX952_CLK_DISPPHYCFG 79 +#define IMX952_CLK_DISP1PIX 80 +#define IMX952_CLK_DISPCDPHYAPB 81 +#define IMX952_CLK_RESERVED41 82 +#define IMX952_CLK_GPUAPB 83 +#define IMX952_CLK_GPU 84 +#define IMX952_CLK_HSIOACSCAN480M 85 +#define IMX952_CLK_HSIOACSCAN80M 86 +#define IMX952_CLK_HSIO 87 +#define IMX952_CLK_HSIOPCIEAUX 88 +#define IMX952_CLK_HSIOPCIETEST160M 89 +#define IMX952_CLK_HSIOPCIETEST400M 90 +#define IMX952_CLK_HSIOPCIETEST500M 91 +#define IMX952_CLK_HSIOUSBTEST50M 92 +#define IMX952_CLK_HSIOUSBTEST60M 93 +#define IMX952_CLK_BUSM7 94 +#define IMX952_CLK_M7 95 +#define IMX952_CLK_M7SYSTICK 96 +#define IMX952_CLK_BUSNETCMIX 97 +#define IMX952_CLK_ENET 98 +#define IMX952_CLK_ENETPHYTEST200M 99 +#define IMX952_CLK_ENETPHYTEST500M 100 +#define IMX952_CLK_ENETPHYTEST667M 101 +#define IMX952_CLK_ENETREF 102 +#define IMX952_CLK_ENETTIMER1 103 +#define IMX952_CLK_RESERVED63 104 +#define IMX952_CLK_SAI2 105 +#define IMX952_CLK_NOCAPB 106 +#define IMX952_CLK_NOC 107 +#define IMX952_CLK_NPUAPB 108 +#define IMX952_CLK_NPU 109 +#define IMX952_CLK_CCMCKO1 110 +#define IMX952_CLK_CCMCKO2 111 +#define IMX952_CLK_CCMCKO3 112 +#define IMX952_CLK_CCMCKO4 113 +#define IMX952_CLK_VPUAPB 114 +#define IMX952_CLK_VPU 115 +#define IMX952_CLK_RESERVED75 116 +#define IMX952_CLK_RESERVED76 117 +#define IMX952_CLK_AUDIOXCVR 118 +#define IMX952_CLK_BUSWAKEUP 119 +#define IMX952_CLK_CAN2 120 +#define IMX952_CLK_CAN3 121 +#define IMX952_CLK_CAN4 122 +#define IMX952_CLK_CAN5 123 +#define IMX952_CLK_FLEXIO1 124 +#define IMX952_CLK_FLEXIO2 125 +#define IMX952_CLK_XSPI1 126 +#define IMX952_CLK_RESERVED86 127 +#define IMX952_CLK_I3C2SLOW 128 +#define IMX952_CLK_LPI2C3 129 +#define IMX952_CLK_LPI2C4 130 +#define IMX952_CLK_LPI2C5 131 +#define IMX952_CLK_LPI2C6 132 +#define IMX952_CLK_LPI2C7 133 +#define IMX952_CLK_LPI2C8 134 +#define IMX952_CLK_LPSPI3 135 +#define IMX952_CLK_LPSPI4 136 +#define IMX952_CLK_LPSPI5 137 +#define IMX952_CLK_LPSPI6 138 +#define IMX952_CLK_LPSPI7 139 +#define IMX952_CLK_LPSPI8 140 +#define IMX952_CLK_LPTMR2 141 +#define IMX952_CLK_LPUART3 142 +#define IMX952_CLK_LPUART4 143 +#define IMX952_CLK_LPUART5 144 +#define IMX952_CLK_LPUART6 145 +#define IMX952_CLK_LPUART7 146 +#define IMX952_CLK_LPUART8 147 +#define IMX952_CLK_SAI3 148 +#define IMX952_CLK_SAI4 149 +#define IMX952_CLK_SAI5 150 +#define IMX952_CLK_SPDIF 151 +#define IMX952_CLK_SWOTRACE 152 +#define IMX952_CLK_TPM4 153 +#define IMX952_CLK_TPM5 154 +#define IMX952_CLK_TPM6 155 +#define IMX952_CLK_MIPIPHYDFT400 156 +#define IMX952_CLK_MIPIPHYDFT540 157 +#define IMX952_CLK_USDHC1 158 +#define IMX952_CLK_USDHC2 159 +#define IMX952_CLK_USDHC3 160 +#define IMX952_CLK_V2XPK 161 +#define IMX952_CLK_WAKEUPAXI 162 +#define IMX952_CLK_XSPISLVROOT 163 +#define IMX952_CLK_AUDMIX1 164 +#define IMX952_CLK_ASRC1 165 +#define IMX952_CLK_ASRC2 166 +#define IMX952_CLK_GPT1 167 +#define IMX952_CLK_GPT2 168 +#define IMX952_CLK_GPT3 169 +#define IMX952_CLK_GPT4 170 + +/* Clock GPR SEL */ +#define IMX952_CLK_GPR_SEL_EXT 171 +#define IMX952_CLK_GPR_SEL_A55C0 172 +#define IMX952_CLK_GPR_SEL_A55C1 173 +#define IMX952_CLK_GPR_SEL_A55C2 174 +#define IMX952_CLK_GPR_SEL_A55C3 175 +#define IMX952_CLK_GPR_SEL_A55P 176 +#define IMX952_CLK_GPR_SEL_DRAM 177 +#define IMX952_CLK_GPR_SEL_TEMPSENSE 178 + +/* Clock CGC */ +#define IMX952_CLK_CGC_NPU 179 +#define IMX952_CLK_CGC_GPU 180 +#define IMX952_CLK_CGC_CAMISI 181 +#define IMX952_CLK_CGC_CAMISP 182 +#define IMX952_CLK_CGC_CAMCSI0 183 +#define IMX952_CLK_CGC_CAMCSI1 184 +#define IMX952_CLK_CGC_CAMOCRAM 185 +#define IMX952_CLK_CGC_HSIOUSB 186 +#define IMX952_CLK_CGC_HSIOPCIE 187 +#define IMX952_CLK_CGC_DISPOCRAM 188 +#define IMX952_CLK_CGC_DISPSEERIS 189 +#define IMX952_CLK_CGC_DISPDSI 190 +#define IMX952_CLK_CGC_NOCGIC 191 +#define IMX952_CLK_CGC_NOCOCRAM 192 +#define IMX952_CLK_CGC_NETC 193 +#define IMX952_CLK_CGC_VPUENC 194 +#define IMX952_CLK_CGC_VPUJPEGENC 195 +#define IMX952_CLK_CGC_VPUJPEGDEC 196 +#define IMX952_CLK_CGC_VPUDEC 197 + +#endif diff --git a/dts/upstream/src/arm64/freescale/imx952-evk.dts b/dts/upstream/src/arm64/freescale/imx952-evk.dts new file mode 100644 index 00000000000..2c753fcbae3 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx952-evk.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include "imx952.dtsi" + +/ { + model = "NXP i.MX952 EVK board"; + compatible = "fsl,imx952-evk", "fsl,imx952"; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x15fe + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x13fe + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x13fe + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x13fe + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x13fe + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x13fe + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x13fe + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x13fe + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x13fe + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x13fe + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e + >; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/imx952-pinfunc.h b/dts/upstream/src/arm64/freescale/imx952-pinfunc.h new file mode 100644 index 00000000000..debe6ede2d7 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx952-pinfunc.h @@ -0,0 +1,867 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DTS_IMX952_PINFUNC_H__ +#define __DTS_IMX952_PINFUNC_H__ + +/* + * The pin function ID is a tuple of + * + */ +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_TDI 0x0000 0x0230 0x05FC 0x00 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0230 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0230 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_CAN2_TX 0x0000 0x0230 0x0000 0x03 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_30 0x0000 0x0230 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_GPIO3_IO_28 0x0000 0x0230 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x0000 0x0230 0x059C 0x06 0x00 + +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_TMS 0x0004 0x0234 0x0600 0x00 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_31 0x0004 0x0234 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_GPIO3_IO_29 0x0004 0x0234 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x0004 0x0234 0x0000 0x06 0x00 + +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_TCK 0x0008 0x0238 0x05F8 0x00 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0008 0x0238 0x04B4 0x04 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_GPIO3_IO_30 0x0008 0x0238 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0008 0x0238 0x0598 0x06 0x00 + +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_TDO 0x000C 0x023C 0x0000 0x00 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x023C 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM2 0x000C 0x023C 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_CAN2_RX 0x000C 0x023C 0x04A4 0x03 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x000C 0x023C 0x04B8 0x04 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_GPIO3_IO_31 0x000C 0x023C 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x000C 0x023C 0x05A0 0x06 0x00 + +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPIO2_IO_0 0x0010 0x0240 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x0010 0x0240 0x0530 0x01 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPTMUX_INOUT0 0x0010 0x0240 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPSPI6_PCS0 0x0010 0x0240 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPUART5_TX 0x0010 0x0240 0x05A0 0x05 0x01 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C5_SDA 0x0010 0x0240 0x0540 0x06 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x0010 0x0240 0x04BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPIO2_IO_1 0x0014 0x0244 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x0014 0x0244 0x052C 0x01 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPTMUX_INOUT1 0x0014 0x0244 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPSPI6_SIN 0x0014 0x0244 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPUART5_RX 0x0014 0x0244 0x059C 0x05 0x01 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C5_SCL 0x0014 0x0244 0x053C 0x06 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x0014 0x0244 0x04C0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPIO2_IO_2 0x0018 0x0248 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C4_SDA 0x0018 0x0248 0x0538 0x01 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPTMUX_INOUT2 0x0018 0x0248 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPSPI6_SOUT 0x0018 0x0248 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0018 0x0248 0x0598 0x05 0x01 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x0018 0x0248 0x0548 0x06 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x0018 0x0248 0x04C4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPIO2_IO_3 0x001C 0x024C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C4_SCL 0x001C 0x024C 0x0534 0x01 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPTMUX_INOUT3 0x001C 0x024C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPSPI6_SCK 0x001C 0x024C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPUART5_RTS_B 0x001C 0x024C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x001C 0x024C 0x0544 0x06 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x001C 0x024C 0x04C8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x0020 0x0250 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_TPM3_CH0 0x0020 0x0250 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0250 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPTMUX_INOUT4 0x0020 0x0250 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPSPI7_PCS0 0x0020 0x0250 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPUART6_TX 0x0020 0x0250 0x05AC 0x05 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPI2C6_SDA 0x0020 0x0250 0x0548 0x06 0x01 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x0020 0x0250 0x04CC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPIO2_IO_5 0x0024 0x0254 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_TPM4_CH0 0x0024 0x0254 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_0 0x0024 0x0254 0x0464 0x02 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPTMUX_INOUT5 0x0024 0x0254 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x0024 0x0254 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPUART6_RX 0x0024 0x0254 0x05A8 0x05 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPI2C6_SCL 0x0024 0x0254 0x0544 0x06 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x0024 0x0254 0x04D0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPIO2_IO_6 0x0028 0x0258 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_TPM5_CH0 0x0028 0x0258 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_1 0x0028 0x0258 0x0468 0x02 0x01 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPTMUX_INOUT6 0x0028 0x0258 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x0028 0x0258 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0028 0x0258 0x05A4 0x05 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPI2C7_SDA 0x0028 0x0258 0x0550 0x06 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x0028 0x0258 0x04D4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPIO2_IO_7 0x002C 0x025C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI3_PCS1 0x002C 0x025C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPTMUX_INOUT7 0x002C 0x025C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x002C 0x025C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPUART6_RTS_B 0x002C 0x025C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPI2C7_SCL 0x002C 0x025C 0x054C 0x06 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x002C 0x025C 0x04D8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPIO2_IO_8 0x0030 0x0260 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPSPI3_PCS0 0x0030 0x0260 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPTMUX_INOUT8 0x0030 0x0260 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_TPM6_CH0 0x0030 0x0260 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPUART7_TX 0x0030 0x0260 0x05B4 0x05 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x0030 0x0260 0x0550 0x06 0x01 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0030 0x0260 0x04DC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPIO2_IO_9 0x0034 0x0264 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPSPI3_SIN 0x0034 0x0264 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPTMUX_INOUT9 0x0034 0x0264 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_TPM3_EXTCLK 0x0034 0x0264 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPUART7_RX 0x0034 0x0264 0x05B0 0x05 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x0034 0x0264 0x054C 0x06 0x01 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0034 0x0264 0x04E0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x0038 0x0268 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPSPI3_SOUT 0x0038 0x0268 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPTMUX_INOUT10 0x0038 0x0268 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_TPM4_EXTCLK 0x0038 0x0268 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPUART7_CTS_B 0x0038 0x0268 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPI2C8_SDA 0x0038 0x0268 0x0558 0x06 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x0038 0x0268 0x04E4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x003C 0x026C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPSPI3_SCK 0x003C 0x026C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPTMUX_INOUT11 0x003C 0x026C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_TPM5_EXTCLK 0x003C 0x026C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPUART7_RTS_B 0x003C 0x026C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPI2C8_SCL 0x003C 0x026C 0x0554 0x06 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x003C 0x026C 0x04E8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_GPIO2_IO_12 0x0040 0x0270 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x0040 0x0270 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_2 0x0040 0x0270 0x046C 0x02 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0040 0x0270 0x04EC 0x03 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPSPI8_PCS0 0x0040 0x0270 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPUART8_TX 0x0040 0x0270 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPI2C8_SDA 0x0040 0x0270 0x0558 0x06 0x01 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x0040 0x0270 0x05BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_GPIO2_IO_13 0x0044 0x0274 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_TPM4_CH2 0x0044 0x0274 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_3 0x0044 0x0274 0x0470 0x02 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPSPI8_SIN 0x0044 0x0274 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPUART8_RX 0x0044 0x0274 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPI2C8_SCL 0x0044 0x0274 0x0554 0x06 0x01 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0044 0x0274 0x04F0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_GPIO2_IO_14 0x0048 0x0278 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART3_TX 0x0048 0x0278 0x0588 0x01 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPSPI8_SOUT 0x0048 0x0278 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART8_CTS_B 0x0048 0x0278 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART4_TX 0x0048 0x0278 0x0594 0x06 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x0048 0x0278 0x04F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_GPIO2_IO_15 0x004C 0x027C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART3_RX 0x004C 0x027C 0x0584 0x01 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x004C 0x027C 0x0624 0x03 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPSPI8_SCK 0x004C 0x027C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART8_RTS_B 0x004C 0x027C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART4_RX 0x004C 0x027C 0x0590 0x06 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x004C 0x027C 0x04F8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x0050 0x0280 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x0050 0x0280 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_2 0x0050 0x0280 0x046C 0x02 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0050 0x0280 0x0580 0x04 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0050 0x0280 0x0564 0x05 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART4_CTS_B 0x0050 0x0280 0x058C 0x06 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0050 0x0280 0x04FC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x0054 0x0284 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x0054 0x0284 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART3_RTS_B 0x0054 0x0284 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0054 0x0284 0x0560 0x05 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART4_RTS_B 0x0054 0x0284 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0054 0x0284 0x0500 0x07 0x00 + +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x0058 0x0288 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0058 0x0288 0x05B8 0x01 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI5_PCS0 0x0058 0x0288 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0058 0x0288 0x055C 0x05 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_TPM5_CH2 0x0058 0x0288 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x0058 0x0288 0x0504 0x07 0x00 + +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_GPIO2_IO_19 0x005C 0x028C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x005C 0x028C 0x05BC 0x01 0x01 +#define IMX952_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_3 0x005C 0x028C 0x0470 0x02 0x01 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x005C 0x028C 0x0508 0x03 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI5_SIN 0x005C 0x028C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI4_SIN 0x005C 0x028C 0x056C 0x05 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x005C 0x028C 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x005C 0x028C 0x05F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x0060 0x0290 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x0060 0x0290 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_0 0x0060 0x0290 0x0464 0x02 0x02 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI5_SOUT 0x0060 0x0290 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI4_SOUT 0x0060 0x0290 0x0570 0x05 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_TPM3_CH1 0x0060 0x0290 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0060 0x0290 0x050C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x0064 0x0294 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x0064 0x0294 0x05F4 0x01 0x01 +#define IMX952_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0294 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0064 0x0294 0x0510 0x03 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI5_SCK 0x0064 0x0294 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI4_SCK 0x0064 0x0294 0x0568 0x05 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_TPM4_CH1 0x0064 0x0294 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0064 0x0294 0x05B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_GPIO2_IO_22 0x0068 0x0298 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_USDHC3_CLK 0x0068 0x0298 0x0604 0x01 0x00 +#define IMX952_PAD_GPIO_IO22__HSIOMIX_TOP_USB1_OTG_OC 0x0068 0x0298 0x047C 0x03 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM5_CH1 0x0068 0x0298 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM6_EXTCLK 0x0068 0x0298 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_LPI2C5_SDA 0x0068 0x0298 0x0540 0x06 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x0068 0x0298 0x0514 0x07 0x00 + +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_GPIO2_IO_23 0x006C 0x029C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_USDHC3_CMD 0x006C 0x029C 0x0608 0x01 0x00 +#define IMX952_PAD_GPIO_IO23__HSIOMIX_TOP_USB2_OTG_OC 0x006C 0x029C 0x0480 0x03 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_TPM6_CH1 0x006C 0x029C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_LPI2C5_SCL 0x006C 0x029C 0x053C 0x06 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x006C 0x029C 0x0518 0x07 0x00 + +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_GPIO2_IO_24 0x0070 0x02A0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_USDHC3_DATA0 0x0070 0x02A0 0x060C 0x01 0x00 +#define IMX952_PAD_GPIO_IO24__HSIOMIX_TOP_USB1_OTG_PWR 0x0070 0x02A0 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TPM3_CH3 0x0070 0x02A0 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TDO 0x0070 0x02A0 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_LPSPI6_PCS1 0x0070 0x02A0 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0070 0x02A0 0x051C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_GPIO2_IO_25 0x0074 0x02A4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_USDHC3_DATA1 0x0074 0x02A4 0x0610 0x01 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x0074 0x02A4 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO25__HSIOMIX_TOP_USB2_OTG_PWR 0x0074 0x02A4 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TPM4_CH3 0x0074 0x02A4 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TCK 0x0074 0x02A4 0x05F8 0x05 0x01 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_LPSPI7_PCS1 0x0074 0x02A4 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0074 0x02A4 0x0520 0x07 0x00 + +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x0078 0x02A8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_USDHC3_DATA2 0x0078 0x02A8 0x0614 0x01 0x00 +#define IMX952_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_1 0x0078 0x02A8 0x0468 0x02 0x02 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x0078 0x02A8 0x04AC 0x03 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TPM5_CH3 0x0078 0x02A8 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TDI 0x0078 0x02A8 0x05FC 0x05 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_LPSPI8_PCS1 0x0078 0x02A8 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x0078 0x02A8 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_GPIO2_IO_27 0x007C 0x02AC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_USDHC3_DATA3 0x007C 0x02AC 0x0618 0x01 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x007C 0x02AC 0x04A4 0x02 0x02 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TPM6_CH3 0x007C 0x02AC 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TMS 0x007C 0x02AC 0x0600 0x05 0x01 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_LPSPI5_PCS1 0x007C 0x02AC 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x007C 0x02AC 0x04B0 0x07 0x01 + +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_GPIO2_IO_28 0x0080 0x02B0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_LPI2C3_SDA 0x0080 0x02B0 0x0530 0x01 0x01 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_CAN3_TX 0x0080 0x02B0 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_28 0x0080 0x02B0 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_GPIO2_IO_29 0x0084 0x02B4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_LPI2C3_SCL 0x0084 0x02B4 0x052C 0x01 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_CAN3_RX 0x0084 0x02B4 0x04A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_29 0x0084 0x02B4 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_GPIO2_IO_30 0x0088 0x02B8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x0088 0x02B8 0x0538 0x01 0x01 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0088 0x02B8 0x04B4 0x07 0x01 + +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_GPIO2_IO_31 0x008C 0x02BC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x008C 0x02BC 0x0534 0x01 0x01 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x008C 0x02BC 0x04B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_GPIO5_IO_12 0x0090 0x02C0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x02C0 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPUART6_TX 0x0090 0x02C0 0x05AC 0x02 0x01 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0090 0x02C0 0x0564 0x04 0x01 + +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_GPIO5_IO_13 0x0094 0x02C4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPUART6_RX 0x0094 0x02C4 0x05A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0094 0x02C4 0x0560 0x04 0x01 + +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x0098 0x02C8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0098 0x02C8 0x05A4 0x02 0x01 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0098 0x02C8 0x055C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_GPIO5_IO_15 0x009C 0x02CC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPUART6_RTS_B 0x009C 0x02CC 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPSPI4_SIN 0x009C 0x02CC 0x056C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPSPI4_SOUT 0x00A0 0x02D0 0x0570 0x04 0x01 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x00A0 0x02D0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPUART7_TX 0x00A0 0x02D0 0x05B4 0x02 0x01 + +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_GPIO5_IO_17 0x00A4 0x02D4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPUART7_RX 0x00A4 0x02D4 0x05B0 0x02 0x01 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPSPI4_SCK 0x00A4 0x02D4 0x0568 0x04 0x01 + +#define IMX952_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00D4 0x0304 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00D4 0x0304 0x0494 0x01 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x00D4 0x0304 0x04AC 0x04 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x00D4 0x0304 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x00D8 0x0308 0x0000 0x05 0x00 +#define IMX952_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00D8 0x0308 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00D8 0x0308 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x00D8 0x0308 0x04B0 0x04 0x00 + +#define IMX952_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00DC 0x030C 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00DC 0x030C 0x0498 0x01 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_CAN3_TX 0x00DC 0x030C 0x0000 0x02 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_28 0x00DC 0x030C 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_GPIO4_IO_28 0x00DC 0x030C 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00E0 0x0310 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00E0 0x0310 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_CAN3_RX 0x00E0 0x0310 0x04A8 0x02 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_29 0x00E0 0x0310 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_GPIO4_IO_29 0x00E0 0x0310 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00E4 0x0314 0x0484 0x00 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_LPUART3_DCD_B 0x00E4 0x0314 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_I3C2_SCL 0x00E4 0x0314 0x0524 0x02 0x00 +#define IMX952_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00E4 0x0314 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_0 0x00E4 0x0314 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_GPIO4_IO_0 0x00E4 0x0314 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00E8 0x0318 0x0488 0x00 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_LPUART3_RIN_B 0x00E8 0x0318 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_I3C2_SDA 0x00E8 0x0318 0x0528 0x02 0x00 +#define IMX952_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00E8 0x0318 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_1 0x00E8 0x0318 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_GPIO4_IO_1 0x00E8 0x0318 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00EC 0x031C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_CAN2_TX 0x00EC 0x031C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00EC 0x031C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_2 0x00EC 0x031C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_GPIO4_IO_2 0x00EC 0x031C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00F0 0x0320 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00F0 0x0320 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_CAN2_RX 0x00F0 0x0320 0x04A4 0x02 0x01 +#define IMX952_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00F0 0x0320 0x0480 0x03 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_3 0x00F0 0x0320 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_GPIO4_IO_3 0x00F0 0x0320 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00F4 0x0324 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_LPUART3_RTS_B 0x00F4 0x0324 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR 0x00F4 0x0324 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00F4 0x0324 0x047C 0x03 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_4 0x00F4 0x0324 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_GPIO4_IO_4 0x00F4 0x0324 0x0000 0x05 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR_B 0x00F4 0x0324 0x0000 0x06 0x00 +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00F4 0x0324 0x0000 0x07 0x00 + +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00F8 0x0328 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_LPUART3_TX 0x00F8 0x0328 0x0588 0x01 0x00 +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00F8 0x0328 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_5 0x00F8 0x0328 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_GPIO4_IO_5 0x00F8 0x0328 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00FC 0x032C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_LPUART3_DTR_B 0x00FC 0x032C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00FC 0x032C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_6 0x00FC 0x032C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_6 0x00FC 0x032C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x0100 0x0330 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RMII_REF50_CLK_OUT 0x0100 0x0330 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_7 0x0100 0x0330 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_GPIO4_IO_7 0x0100 0x0330 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x0104 0x0334 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_LPUART3_DSR_B 0x0104 0x0334 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x0104 0x0334 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x0104 0x0334 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_8 0x0104 0x0334 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_8 0x0104 0x0334 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x0108 0x0338 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0108 0x0338 0x048C 0x01 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_9 0x0108 0x0338 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_GPIO4_IO_9 0x0108 0x0338 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x010C 0x033C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_LPUART3_RX 0x010C 0x033C 0x0584 0x01 0x00 +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x010C 0x033C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_10 0x010C 0x033C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_GPIO4_IO_10 0x010C 0x033C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x0110 0x0340 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0110 0x0340 0x0580 0x01 0x00 +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x0110 0x0340 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPTMR2_ALT0 0x0110 0x0340 0x0574 0x03 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_11 0x0110 0x0340 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_GPIO4_IO_11 0x0110 0x0340 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x0114 0x0344 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0114 0x0344 0x048C 0x02 0x01 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_LPTMR2_ALT1 0x0114 0x0344 0x0578 0x03 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_12 0x0114 0x0344 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_GPIO4_IO_12 0x0114 0x0344 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x0118 0x0348 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0118 0x0348 0x057C 0x03 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_13 0x0118 0x0348 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_GPIO4_IO_13 0x0118 0x0348 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x011C 0x034C 0x0484 0x00 0x01 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_LPUART4_DCD_B 0x011C 0x034C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x011C 0x034C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_14 0x011C 0x034C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_GPIO4_IO_14 0x011C 0x034C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x0120 0x0350 0x0488 0x00 0x01 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_LPUART4_RIN_B 0x0120 0x0350 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x0120 0x0350 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_15 0x0120 0x0350 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_GPIO4_IO_15 0x0120 0x0350 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_0 0x0124 0x0354 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_16 0x0124 0x0354 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_GPIO4_IO_16 0x0124 0x0354 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x0124 0x0354 0x0000 0x00 0x00 + +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x0128 0x0358 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x0128 0x0358 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_1 0x0128 0x0358 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x0128 0x0358 0x05D0 0x03 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_17 0x0128 0x0358 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_GPIO4_IO_17 0x0128 0x0358 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x012C 0x035C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_LPUART4_RTS_B 0x012C 0x035C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_2 0x012C 0x035C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x012C 0x035C 0x05CC 0x03 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_18 0x012C 0x035C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_GPIO4_IO_18 0x012C 0x035C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x012C 0x035C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0130 0x0360 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_LPUART4_TX 0x0130 0x0360 0x0594 0x01 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_3 0x0130 0x0360 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x0130 0x0360 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_19 0x0130 0x0360 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_GPIO4_IO_19 0x0130 0x0360 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0130 0x0360 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0134 0x0364 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_LPUART4_DTR_B 0x0134 0x0364 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0134 0x0364 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0134 0x0364 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_20 0x0134 0x0364 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_20 0x0134 0x0364 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x0138 0x0368 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RMII_REF50_CLK_OUT 0x0138 0x0368 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x0138 0x0368 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_21 0x0138 0x0368 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_GPIO4_IO_21 0x0138 0x0368 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x013C 0x036C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_LPUART4_DSR_B 0x013C 0x036C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_0 0x013C 0x036C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_22 0x013C 0x036C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_22 0x013C 0x036C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x013C 0x036C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0140 0x0370 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0140 0x0370 0x0490 0x01 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_1 0x0140 0x0370 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x0140 0x0370 0x05C8 0x03 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_23 0x0140 0x0370 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_GPIO4_IO_23 0x0140 0x0370 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0144 0x0374 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_LPUART4_RX 0x0144 0x0374 0x0590 0x01 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_2 0x0144 0x0374 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x0144 0x0374 0x05C0 0x03 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_24 0x0144 0x0374 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_GPIO4_IO_24 0x0144 0x0374 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0144 0x0374 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x0148 0x0378 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_3 0x0148 0x0378 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x0148 0x0378 0x05C4 0x03 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_25 0x0148 0x0378 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_GPIO4_IO_25 0x0148 0x0378 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x0148 0x0378 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x014C 0x037C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_LPUART4_CTS_B 0x014C 0x037C 0x058C 0x01 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x014C 0x037C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x014C 0x037C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_26 0x014C 0x037C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_GPIO4_IO_26 0x014C 0x037C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x014C 0x037C 0x0490 0x06 0x01 + +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0150 0x0380 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0150 0x0380 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_27 0x0150 0x0380 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_GPIO4_IO_27 0x0150 0x0380 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0154 0x0384 0x04DC 0x04 0x01 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_GPIO3_IO_8 0x0154 0x0384 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x0154 0x0384 0x0000 0x00 0x00 + +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x0158 0x0388 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0158 0x0388 0x04E0 0x04 0x01 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_GPIO3_IO_9 0x0158 0x0388 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x015C 0x038C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x015C 0x038C 0x04E4 0x04 0x01 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_GPIO3_IO_10 0x015C 0x038C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x0160 0x0390 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x0160 0x0390 0x04E8 0x04 0x01 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_GPIO3_IO_11 0x0160 0x0390 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x0164 0x0394 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x0164 0x0394 0x0624 0x01 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0164 0x0394 0x04EC 0x04 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_GPIO3_IO_12 0x0164 0x0394 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0164 0x0394 0x0000 0x06 0x00 + +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x0168 0x0398 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x0168 0x0398 0x064C 0x01 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0168 0x0398 0x04F0 0x04 0x01 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_GPIO3_IO_13 0x0168 0x0398 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x016C 0x039C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x016C 0x039C 0x0638 0x01 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x016C 0x039C 0x04F4 0x04 0x01 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_GPIO3_IO_14 0x016C 0x039C 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x016C 0x039C 0x066C 0x06 0x00 + +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x0170 0x03A0 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x0170 0x03A0 0x063C 0x01 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_RESET_B 0x0170 0x03A0 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x0170 0x03A0 0x04F8 0x04 0x01 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_GPIO3_IO_15 0x0170 0x03A0 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x0170 0x03A0 0x0670 0x06 0x00 + +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x0174 0x03A4 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x0174 0x03A4 0x0640 0x01 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_CD_B 0x0174 0x03A4 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0174 0x03A4 0x04FC 0x04 0x01 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_GPIO3_IO_16 0x0174 0x03A4 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x0174 0x03A4 0x0674 0x06 0x00 + +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x0178 0x03A8 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x0178 0x03A8 0x0644 0x01 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_WP 0x0178 0x03A8 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0178 0x03A8 0x0500 0x04 0x01 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_GPIO3_IO_17 0x0178 0x03A8 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x0178 0x03A8 0x0678 0x06 0x00 + +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x017C 0x03AC 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI1_A_DQS 0x017C 0x03AC 0x0620 0x01 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x017C 0x03AC 0x0504 0x04 0x01 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_GPIO3_IO_18 0x017C 0x03AC 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x017C 0x03AC 0x0654 0x06 0x00 + +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x0180 0x03B0 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_WP 0x0180 0x03B0 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0180 0x03B0 0x057C 0x02 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x0180 0x03B0 0x0508 0x04 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_GPIO3_IO_19 0x0180 0x03B0 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0180 0x03B0 0x0478 0x06 0x01 + +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x0184 0x03B4 0x0604 0x00 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x0184 0x03B4 0x061C 0x01 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x0184 0x03B4 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x0184 0x03B4 0x05D8 0x03 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0184 0x03B4 0x050C 0x04 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_GPIO3_IO_20 0x0184 0x03B4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x0184 0x03B4 0x0658 0x06 0x00 + +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x0188 0x03B8 0x0608 0x00 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x0188 0x03B8 0x0648 0x01 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x0188 0x03B8 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x0188 0x03B8 0x05E8 0x03 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0188 0x03B8 0x0510 0x04 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_GPIO3_IO_21 0x0188 0x03B8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI_SLV_CS 0x0188 0x03B8 0x0650 0x06 0x00 + +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x018C 0x03BC 0x060C 0x00 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x018C 0x03BC 0x0628 0x01 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x018C 0x03BC 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x018C 0x03BC 0x05D4 0x03 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x018C 0x03BC 0x0514 0x04 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_GPIO3_IO_22 0x018C 0x03BC 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x018C 0x03BC 0x065C 0x06 0x00 + +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x0190 0x03C0 0x0610 0x00 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x0190 0x03C0 0x062C 0x01 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x0190 0x03C0 0x05DC 0x02 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x0190 0x03C0 0x0000 0x03 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x0190 0x03C0 0x0518 0x04 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_GPIO3_IO_23 0x0190 0x03C0 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x0190 0x03C0 0x0660 0x06 0x00 + +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x0194 0x03C4 0x0614 0x00 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x0194 0x03C4 0x0630 0x01 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x0194 0x03C4 0x05E0 0x02 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x0194 0x03C4 0x05F0 0x03 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0194 0x03C4 0x051C 0x04 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_GPIO3_IO_24 0x0194 0x03C4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x0194 0x03C4 0x0664 0x06 0x00 + +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x0198 0x03C8 0x0618 0x00 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x0198 0x03C8 0x0634 0x01 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x0198 0x03C8 0x05E4 0x02 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x0198 0x03C8 0x05EC 0x03 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0198 0x03C8 0x0520 0x04 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_GPIO3_IO_25 0x0198 0x03C8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x0198 0x03C8 0x0668 0x06 0x00 + +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x019C 0x03CC 0x0628 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_4 0x019C 0x03CC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x019C 0x03CC 0x05CC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_RX_DATA_1 0x019C 0x03CC 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x019C 0x03CC 0x065C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_GPIO5_IO_0 0x019C 0x03CC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x01A0 0x03D0 0x062C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_5 0x01A0 0x03D0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x01A0 0x03D0 0x05D0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_DATA_1 0x01A0 0x03D0 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x01A0 0x03D0 0x0660 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_GPIO5_IO_1 0x01A0 0x03D0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x01A4 0x03D4 0x0630 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_6 0x01A4 0x03D4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x01A4 0x03D4 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x01A4 0x03D4 0x0664 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_GPIO5_IO_2 0x01A4 0x03D4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x01A8 0x03D8 0x0634 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_7 0x01A8 0x03D8 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x01A8 0x03D8 0x05C4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x01A8 0x03D8 0x0668 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_GPIO5_IO_3 0x01A8 0x03D8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x01AC 0x03DC 0x0638 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x01AC 0x03DC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x01AC 0x03DC 0x05DC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x01AC 0x03DC 0x066C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_GPIO5_IO_4 0x01AC 0x03DC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x01B0 0x03E0 0x063C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x01B0 0x03E0 0x05F0 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x01B0 0x03E0 0x05E0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_6 0x01B0 0x03E0 0x049C 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x01B0 0x03E0 0x0670 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_GPIO5_IO_5 0x01B0 0x03E0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x01B4 0x03E4 0x0640 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x01B4 0x03E4 0x05EC 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x01B4 0x03E4 0x05E4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_7 0x01B4 0x03E4 0x04A0 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x01B4 0x03E4 0x0674 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_GPIO5_IO_6 0x01B4 0x03E4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x01B8 0x03E8 0x0644 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x01B8 0x03E8 0x05D8 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x01B8 0x03E8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x01B8 0x03E8 0x0678 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_GPIO5_IO_7 0x01B8 0x03E8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x01BC 0x03EC 0x0620 0x00 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x01BC 0x03EC 0x05E8 0x01 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x01BC 0x03EC 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_6 0x01BC 0x03EC 0x049C 0x03 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x01BC 0x03EC 0x0654 0x04 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_GPIO5_IO_8 0x01BC 0x03EC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x01C0 0x03F0 0x061C 0x00 0x01 +#define IMX952_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_4 0x01C0 0x03F0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x01C0 0x03F0 0x05C8 0x02 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x01C0 0x03F0 0x0658 0x04 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_GPIO5_IO_9 0x01C0 0x03F0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x01C4 0x03F4 0x0648 0x00 0x01 +#define IMX952_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_5 0x01C4 0x03F4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x01C4 0x03F4 0x05C0 0x02 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI_SLV_CS 0x01C4 0x03F4 0x0650 0x04 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_GPIO5_IO_10 0x01C4 0x03F4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x01C8 0x03F8 0x064C 0x00 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x01C8 0x03F8 0x05D4 0x01 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x01C8 0x03F8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_7 0x01C8 0x03F8 0x04A0 0x03 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x01C8 0x03F8 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_USDHC2_CD_B 0x01CC 0x03FC 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01CC 0x03FC 0x0494 0x01 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_I3C2_SCL 0x01CC 0x03FC 0x0524 0x02 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x01CC 0x03FC 0x04BC 0x04 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x01CC 0x03FC 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x01D0 0x0400 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01D0 0x0400 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_I3C2_SDA 0x01D0 0x0400 0x0528 0x02 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x01D0 0x0400 0x04C0 0x04 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_GPIO3_IO_1 0x01D0 0x0400 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01D0 0x0400 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x01D4 0x0404 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01D4 0x0404 0x0498 0x01 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR 0x01D4 0x0404 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR_B 0x01D4 0x0404 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x01D4 0x0404 0x04C4 0x04 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_GPIO3_IO_2 0x01D4 0x0404 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01D4 0x0404 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x01D8 0x0408 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01D8 0x0408 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_CAN2_TX 0x01D8 0x0408 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x01D8 0x0408 0x04C8 0x04 0x01 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_GPIO3_IO_3 0x01D8 0x0408 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01D8 0x0408 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x01DC 0x040C 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01DC 0x040C 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_CAN2_RX 0x01DC 0x040C 0x04A4 0x02 0x03 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x01DC 0x040C 0x04CC 0x04 0x01 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_GPIO3_IO_4 0x01DC 0x040C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x01E0 0x0410 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01E0 0x0410 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01E0 0x0410 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x01E0 0x0410 0x04D0 0x04 0x01 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_GPIO3_IO_5 0x01E0 0x0410 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x01E4 0x0414 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_LPTMR2_ALT0 0x01E4 0x0414 0x0574 0x01 0x01 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01E4 0x0414 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01E4 0x0414 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x01E4 0x0414 0x04D4 0x04 0x01 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_GPIO3_IO_6 0x01E4 0x0414 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_USDHC2_RESET_B 0x01E8 0x0418 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_LPTMR2_ALT1 0x01E8 0x0418 0x0578 0x01 0x01 +#define IMX952_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01E8 0x0418 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x01E8 0x0418 0x04D8 0x04 0x01 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x01E8 0x0418 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01EC 0x041C 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01EC 0x041C 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01EC 0x041C 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01EC 0x041C 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01EC 0x041C 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_0 0x01EC 0x041C 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01F0 0x0420 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01F0 0x0420 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01F0 0x0420 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01F0 0x0420 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01F0 0x0420 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_1 0x01F0 0x0420 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01F4 0x0424 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01F4 0x0424 0x0000 0x01 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01F4 0x0424 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01F4 0x0424 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01F4 0x0424 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_2 0x01F4 0x0424 0x0000 0x05 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01F4 0x0424 0x0000 0x06 0x00 + +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01F8 0x0428 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01F8 0x0428 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01F8 0x0428 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01F8 0x0428 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_3 0x01F8 0x0428 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01FC 0x042C 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_UART_CSSI_RX 0x01FC 0x042C 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01FC 0x042C 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01FC 0x042C 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_4 0x01FC 0x042C 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x0200 0x0430 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_UART_CSSI_TX 0x0200 0x0430 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x0200 0x0430 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x0200 0x0430 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_5 0x0200 0x0430 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x0204 0x0434 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x0204 0x0434 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x0204 0x0434 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x0204 0x0434 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x0204 0x0434 0x0474 0x04 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_6 0x0204 0x0434 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x0208 0x0438 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x0208 0x0438 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x0208 0x0438 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x0208 0x0438 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_7 0x0208 0x0438 0x0000 0x05 0x00 + +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x020C 0x043C 0x0000 0x00 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x020C 0x043C 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT0 0x020C 0x043C 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x020C 0x043C 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x020C 0x043C 0x0000 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x0210 0x0440 0x0464 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x0210 0x0440 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x0210 0x0440 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x0210 0x0440 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT1 0x0210 0x0440 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x0210 0x0440 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x0210 0x0440 0x0460 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_1 0x0214 0x0444 0x0468 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_NMI 0x0214 0x0444 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x0214 0x0444 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x0214 0x0444 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT2 0x0214 0x0444 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_10 0x0214 0x0444 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0214 0x0444 0x0478 0x06 0x00 + +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x0218 0x0448 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_1 0x0218 0x0448 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x0218 0x0448 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x0218 0x0448 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x0218 0x0448 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x0218 0x0448 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x021C 0x044C 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x021C 0x044C 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x021C 0x044C 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x021C 0x044C 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x021C 0x044C 0x0460 0x04 0x01 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x021C 0x044C 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x0220 0x0450 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x0220 0x0450 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x0220 0x0450 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x0220 0x0450 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x0220 0x0450 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x0220 0x0450 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x0224 0x0454 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x0224 0x0454 0x0474 0x01 0x01 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x0224 0x0454 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x0224 0x0454 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x0224 0x0454 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x0224 0x0454 0x0000 0x05 0x00 + +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x0228 0x0458 0x0000 0x00 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x0228 0x0458 0x0000 0x01 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_15 0x0228 0x0458 0x0000 0x05 0x00 +#endif /* __DTS_IMX952_PINFUNC_H__ */ diff --git a/dts/upstream/src/arm64/freescale/imx952-power.h b/dts/upstream/src/arm64/freescale/imx952-power.h new file mode 100644 index 00000000000..1d0fb8c93e2 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx952-power.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX952_POWER_H__ +#define __IMX952_POWER_H__ + +#define IMX952_PD_ANA 0 +#define IMX952_PD_AON 1 +#define IMX952_PD_BBSM 2 +#define IMX952_PD_CAMERA 3 +#define IMX952_PD_CCMSRCGPC 4 +#define IMX952_PD_A55C0 5 +#define IMX952_PD_A55C1 6 +#define IMX952_PD_A55C2 7 +#define IMX952_PD_A55C3 8 +#define IMX952_PD_A55P 9 +#define IMX952_PD_DDR 10 +#define IMX952_PD_DISPLAY 11 +#define IMX952_PD_GPU 12 +#define IMX952_PD_HSIO_TOP 13 +#define IMX952_PD_HSIO_WAON 14 +#define IMX952_PD_M7 15 +#define IMX952_PD_NETC 16 +#define IMX952_PD_NOC 17 +#define IMX952_PD_NPU 18 +#define IMX952_PD_VPU 19 +#define IMX952_PD_WAKEUP 20 + +#define IMX952_PERF_M33 0 +#define IMX952_PERF_WAKEUP 1 +#define IMX952_PERF_M7 2 +#define IMX952_PERF_DRAM 3 +#define IMX952_PERF_HSIO 4 +#define IMX952_PERF_NPU 5 +#define IMX952_PERF_NOC 6 +#define IMX952_PERF_A55 7 +#define IMX952_PERF_GPU 8 +#define IMX952_PERF_VPU 9 +#define IMX952_PERF_CAM 10 +#define IMX952_PERF_DISP 11 + +#endif diff --git a/dts/upstream/src/arm64/freescale/imx952.dtsi b/dts/upstream/src/arm64/freescale/imx952.dtsi new file mode 100644 index 00000000000..33bde271d39 --- /dev/null +++ b/dts/upstream/src/arm64/freescale/imx952.dtsi @@ -0,0 +1,1248 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2025 NXP + */ + +#include +#include +#include + +#include "imx952-clock.h" +#include "imx952-pinfunc.h" +#include "imx952-power.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + + clk_ldb_pll_pixel: clock-ldb-pll-div7 { + compatible = "fixed-factor-clock"; + clocks = <&scmi_clk IMX952_CLK_LDBPLL>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + clock-output-names = "ldb_pll_div7"; + }; + + clk_osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&A55_0>; + }; + + core1 { + cpu = <&A55_1>; + }; + + core2 { + cpu = <&A55_2>; + }; + + core3 { + cpu = <&A55_3>; + }; + }; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; + shmem = <&scmi_buf0>, <&scmi_buf1>; + #address-cells = <1>; + #size-cells = <0>; + arm,max-rx-timeout-ms = <5000>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sys_power: protocol@12 { + reg = <0x12>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_iomuxc: protocol@19 { + reg = <0x19>; + }; + + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + + scmi_bbm: protocol@81 { + reg = <0x81>; + }; + + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + + scmi_misc: protocol@84 { + reg = <0x84>; + }; + }; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + dma-noncoherent; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>, + <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x42000000 0x0 0x800000>; + ranges = <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + mu7: mailbox@42050000 { + compatible = "fsl,imx95-mu"; + reg = <0x42050000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: watchdog@420b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x420b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@42100000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42100000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@42110000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42110000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42120000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42120000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42130000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42130000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c@42140000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42140000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_I3C2SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42150000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42150000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42160000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42160000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi3: spi@42170000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42170000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi4: spi@42180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42180000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart3: serial@42190000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42190000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART3>; + clock-names = "ipg"; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart4: serial@421a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART4>; + clock-names = "ipg"; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart5: serial@421b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421b0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART5>; + clock-names = "ipg"; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart6: serial@421c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421c0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART6>; + clock-names = "ipg"; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan2: can@421d0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x421d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN2>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan3: can@42220000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x42220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN3>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + lpuart7: serial@422b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422b0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART7>; + clock-names = "ipg"; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart8: serial@422c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422c0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART8>; + clock-names = "ipg"; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpi2c5: i2c@422d0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c6: i2c@422e0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c7: i2c@422f0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c8: i2c@42300000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42300000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi5: spi@42310000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42310000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi6: spi@42320000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42320000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi7: spi@42330000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42330000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi8: spi@42340000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42340000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mu8: mailbox@42350000 { + compatible = "fsl,imx95-mu"; + reg = <0x42350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x42800000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x42800000 0x0 0x42800000 0x800000>; + + edma2: dma-controller@42800000 { + compatible = "fsl,imx95-edma5"; + reg = <0x42800000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <64>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; //error irq + }; + + usdhc1: mmc@42c20000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c20000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42c30000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c30000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@42c40000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c40000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 4 32>; + ngpios = <32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>, + <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>; + ngpios = <32>; + }; + + gpio4: gpio@43840000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>; + ngpios = <30>; + }; + + gpio5: gpio@43850000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>; + ngpios = <18>; + }; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x44000000 0x0 0x800000>; + ranges = <0x44000000 0x0 0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + edma1: dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; //error irq + }; + + mu1: mailbox@44220000 { + compatible = "fsl,imx95-mu"; + reg = <0x44220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@44290000 { + compatible = "nxp,imx95-sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = ; + clocks = <&clk_osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_I3C1SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART1>; + clock-names = "ipg"; + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART2>; + clock-names = "ipg"; + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_CAN1>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + ; + clocks = <&scmi_clk IMX952_CLK_ADC>; + clock-names = "ipg"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x1000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram0: sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu5: mailbox@44610000 { + compatible = "fsl,imx95-mu"; + reg = <0x44610000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu6: mailbox@44630000 { + compatible = "fsl,imx95-mu"; + reg = <0x44630000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + v2x_mu0: mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu2: mailbox@47320000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47320000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu3: mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu4: mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu: mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_M33>, + <&scmi_clk IMX952_CLK_M33>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 123 16>; + ngpios = <16>; + status = "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47520000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47530000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47540000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + elemu4: mailbox@47560000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47560000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47570000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + usb1: usb@4c100000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c100000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c100200 0x0 0x200>, + <0x0 0x4c010010 0x0 0x4>; + }; + + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x4>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/mba8mx.dtsi b/dts/upstream/src/arm64/freescale/mba8mx.dtsi index 79daba930ad..10d5c211b1c 100644 --- a/dts/upstream/src/arm64/freescale/mba8mx.dtsi +++ b/dts/upstream/src/arm64/freescale/mba8mx.dtsi @@ -141,6 +141,13 @@ model = "tqm-tlv320aic32"; ssi-controller = <&sai3>; audio-codec = <&tlv320aic3x04>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; }; }; @@ -185,7 +192,7 @@ reset-assert-us = <500000>; reset-deassert-us = <500>; interrupt-parent = <&expander2>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/dts/upstream/src/arm64/freescale/mba8xx.dtsi b/dts/upstream/src/arm64/freescale/mba8xx.dtsi index c4b5663949a..f534dab44e8 100644 --- a/dts/upstream/src/arm64/freescale/mba8xx.dtsi +++ b/dts/upstream/src/arm64/freescale/mba8xx.dtsi @@ -128,6 +128,13 @@ model = "tqm-tlv320aic32"; audio-codec = <&tlv320aic3x04>; ssi-controller = <&sai1>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; }; }; diff --git a/dts/upstream/src/arm64/freescale/s32g2.dtsi b/dts/upstream/src/arm64/freescale/s32g2.dtsi index d167624d1f0..51d00dac12d 100644 --- a/dts/upstream/src/arm64/freescale/s32g2.dtsi +++ b/dts/upstream/src/arm64/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024 NXP + * Copyright 2017-2021, 2024-2025 NXP */ #include @@ -727,6 +727,62 @@ status = "disabled"; }; + gmac0: ethernet@4033c000 { + compatible = "nxp,s32g2-dwmac"; + reg = <0x4033c000 0x2000>, /* gmac IP */ + <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + + queue0 { + }; + + queue1 { + }; + + queue2 { + }; + + queue3 { + }; + + queue4 { + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + }; + + queue1 { + }; + + queue2 { + }; + + queue3 { + }; + + queue4 { + }; + }; + + gmac0mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; reg = <0x50800000 0x10000>, diff --git a/dts/upstream/src/arm64/freescale/s32g274a-evb.dts b/dts/upstream/src/arm64/freescale/s32g274a-evb.dts index c4a195dd67b..aa40a52f8e5 100644 --- a/dts/upstream/src/arm64/freescale/s32g274a-evb.dts +++ b/dts/upstream/src/arm64/freescale/s32g274a-evb.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC - * Copyright 2019-2021, 2024 NXP + * Copyright 2019-2021, 2024-2025 NXP */ /dts-v1/; @@ -14,6 +14,7 @@ compatible = "nxp,s32g274a-evb", "nxp,s32g2"; aliases { + ethernet0 = &gmac0; serial0 = &uart0; }; @@ -43,3 +44,18 @@ no-1-8-v; status = "okay"; }; + +&gmac0 { + clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>; + clock-names = "stmmaceth", "tx", "rx", "ptp_ref"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmiiaphy4>; + status = "okay"; +}; + +&gmac0mdio { + /* KSZ 9031 on RGMII */ + rgmiiaphy4: ethernet-phy@4 { + reg = <4>; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/s32g274a-rdb2.dts b/dts/upstream/src/arm64/freescale/s32g274a-rdb2.dts index 4f58be68c81..ee3121b192e 100644 --- a/dts/upstream/src/arm64/freescale/s32g274a-rdb2.dts +++ b/dts/upstream/src/arm64/freescale/s32g274a-rdb2.dts @@ -14,6 +14,7 @@ compatible = "nxp,s32g274a-rdb2", "nxp,s32g2"; aliases { + ethernet0 = &gmac0; serial0 = &uart0; serial1 = &uart1; }; @@ -77,3 +78,18 @@ no-1-8-v; status = "okay"; }; + +&gmac0 { + clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>; + clock-names = "stmmaceth", "tx", "rx", "ptp_ref"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmiiaphy1>; + status = "okay"; +}; + +&gmac0mdio { + /* KSZ 9031 on RGMII */ + rgmiiaphy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/s32g3.dtsi b/dts/upstream/src/arm64/freescale/s32g3.dtsi index be3a582ebc1..eff7673e7f3 100644 --- a/dts/upstream/src/arm64/freescale/s32g3.dtsi +++ b/dts/upstream/src/arm64/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -804,6 +804,62 @@ status = "disabled"; }; + gmac0: ethernet@4033c000 { + compatible = "nxp,s32g2-dwmac"; + reg = <0x4033c000 0x2000>, /* gmac IP */ + <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-names = "macirq"; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + + queue0 { + }; + + queue1 { + }; + + queue2 { + }; + + queue3 { + }; + + queue4 { + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + }; + + queue1 { + }; + + queue2 { + }; + + queue3 { + }; + + queue4 { + }; + }; + + gmac0mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + swt8: watchdog@40500000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; reg = <40500000 0x1000>; diff --git a/dts/upstream/src/arm64/freescale/s32g399a-rdb3.dts b/dts/upstream/src/arm64/freescale/s32g399a-rdb3.dts index e94f70ad82d..326322b6219 100644 --- a/dts/upstream/src/arm64/freescale/s32g399a-rdb3.dts +++ b/dts/upstream/src/arm64/freescale/s32g399a-rdb3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) */ @@ -15,6 +15,7 @@ compatible = "nxp,s32g399a-rdb3", "nxp,s32g3"; aliases { + ethernet0 = &gmac0; mmc0 = &usdhc0; serial0 = &uart0; serial1 = &uart1; @@ -93,3 +94,18 @@ disable-wp; status = "okay"; }; + +&gmac0 { + clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>; + clock-names = "stmmaceth", "tx", "rx", "ptp_ref"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmiiaphy1>; + status = "okay"; +}; + +&gmac0mdio { + /* KSZ 9031 on RGMII */ + rgmiiaphy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/dts/upstream/src/arm64/freescale/tqma8xxs-mb-smarc-2.dtsi b/dts/upstream/src/arm64/freescale/tqma8xxs-mb-smarc-2.dtsi index 478cc8ede05..3d20e3bf32c 100644 --- a/dts/upstream/src/arm64/freescale/tqma8xxs-mb-smarc-2.dtsi +++ b/dts/upstream/src/arm64/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -98,6 +98,13 @@ model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic3x04>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; }; }; diff --git a/dts/upstream/src/arm64/hisilicon/hi3660-hikey960.dts b/dts/upstream/src/arm64/hisilicon/hi3660-hikey960.dts index 3f13a960f34..ed84ab92fb1 100644 --- a/dts/upstream/src/arm64/hisilicon/hi3660-hikey960.dts +++ b/dts/upstream/src/arm64/hisilicon/hi3660-hikey960.dts @@ -675,10 +675,7 @@ snps,lfps_filter_quirk; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; - snps,tx_de_emphasis_quirk; - snps,tx_de_emphasis = <1>; snps,dis_enblslpm_quirk; - snps,gctl-reset-quirk; usb-role-switch; role-switch-default-mode = "host"; port { diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi index c1e66db0f4c..0dfbafde882 100644 --- a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi +++ b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi @@ -167,6 +167,7 @@ compatible = "intel,agilex-clkmgr"; reg = <0xffd10000 0x1000>; #clock-cells = <1>; + clocks = <&osc1>; }; gmac0: ethernet@ff800000 { diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex3_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_agilex3_socdk.dts new file mode 100644 index 00000000000..14b299f19f3 --- /dev/null +++ b/dts/upstream/src/arm64/intel/socfpga_agilex3_socdk.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex3 SoCDK"; + compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3", + "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + /delete-node/ cpu@2; + /delete-node/ cpu@3; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "hps_led0"; + gpios = <&porta 1 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&porta 12 GPIO_ACTIVE_HIGH>; + }; + + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + rxc-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <0>; + txen-skew-ps = <60>; + txd0-skew-ps = <60>; + txd1-skew-ps = <60>; + txd2-skew-ps = <60>; + txd3-skew-ps = <60>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x00c00000>; + }; + + root: partition@c00000 { + label = "root"; + reg = <0x00c00000 0x03400000>; + }; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi index 04e99cd7e74..a5c2025a616 100644 --- a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi +++ b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi @@ -37,6 +37,7 @@ reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -44,6 +45,7 @@ reg = <0x100>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ reg = <0x200>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -58,6 +61,30 @@ reg = <0x300>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3>; + cache-unified; + }; + + L3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + + }; + + firmware { + svc { + compatible = "intel,agilex5-svc"; + method = "smc"; + memory-region = <&service_reserved>; + iommus = <&smmu 10>; }; }; @@ -75,8 +102,11 @@ #address-cells = <2>; #size-cells = <2>; interrupt-controller; + interrupt-parent = <&intc>; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; + /* VGIC maintenance interrupt */ + interrupts = ; its: msi-controller@1d040000 { compatible = "arm,gic-v3-its"; @@ -133,6 +163,12 @@ compatible = "usb-nop-xceiv"; }; + pmu0: pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&intc>; + interrupts = ; + }; + soc: soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0xffffffff>; @@ -203,7 +239,8 @@ }; i3c0: i3c@10da0000 { - compatible = "snps,dw-i3c-master-1.00a"; + compatible = "altr,agilex5-dw-i3c-master", + "snps,dw-i3c-master-1.00a"; reg = <0x10da0000 0x1000>; #address-cells = <3>; #size-cells = <0>; @@ -213,7 +250,8 @@ }; i3c1: i3c@10da1000 { - compatible = "snps,dw-i3c-master-1.00a"; + compatible = "altr,agilex5-dw-i3c-master", + "snps,dw-i3c-master-1.00a"; reg = <0x10da1000 0x1000>; #address-cells = <3>; #size-cells = <0>; @@ -271,7 +309,9 @@ #size-cells = <0>; interrupts = ; clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; + clock-names = "nf_clk"; cdns,board-delay-ps = <4830>; + iommus = <&smmu 4>; status = "disabled"; }; @@ -298,6 +338,7 @@ snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; + iommus = <&smmu 8>; }; dmac1: dma-controller@10dc0000 { @@ -315,6 +356,7 @@ snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; + iommus = <&smmu 9>; }; rst: rstmgr@10d11000 { @@ -323,6 +365,18 @@ #reset-cells = <1>; }; + smmu: iommu@16000000 { + compatible = "arm,smmu-v3"; + reg = <0x16000000 0x30000>; + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "priq"; + dma-coherent; + #iommu-cells = <1>; + status = "disabled"; + }; + spi0: spi@10da4000 { compatible = "snps,dw-apb-ssi"; reg = <0x10da4000 0x1000>; @@ -423,6 +477,7 @@ phy-names = "usb2-phy"; resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; + iommus = <&smmu 6>; clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; clock-names = "otg"; status = "disabled"; @@ -822,5 +877,61 @@ }; }; }; + + pmu0_tcu: pmu@16002000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16002000 0x1000>, + <0x16022000 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + }; + + pmu0_tbu0: pmu@16042000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16042000 0x1000>, + <0x16052000 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + }; + + pmu0_tbu1: pmu@16062000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16062000 0x1000>, + <0x16072000 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + }; + + pmu0_tbu2: pmu@16082000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16082000 0x1000>, + <0x16092000 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + }; + + pmu0_tbu3: pmu@160a2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160A2000 0x1000>, + <0x160B2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + }; + + pmu0_tbu4: pmu@160c2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160C2000 0x1000>, + <0x160D2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + }; + + pmu0_tbu5: pmu@160e2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160E2000 0x1000>, + <0x160F2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + }; }; }; diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk.dts index e9776e1cdc9..262bb3e8e5c 100644 --- a/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk.dts +++ b/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk.dts @@ -77,6 +77,8 @@ cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk_013b.dts b/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk_013b.dts new file mode 100644 index 00000000000..f71e1280c77 --- /dev/null +++ b/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk_013b.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 013B SoCDK"; + compatible = "intel,socfpga-agilex5-socdk-013b", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "hps_led0"; + gpios = <&porta 1 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&porta 12 GPIO_ACTIVE_HIGH>; + }; + + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + rxc-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <0>; + txen-skew-ps = <60>; + txd0-skew-ps = <60>; + txd1-skew-ps = <60>; + txd2-skew-ps = <60>; + txd3-skew-ps = <60>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x00c00000>; + }; + + root: partition@c00000 { + label = "root"; + reg = <0x00c00000 0x03400000>; + }; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk_nand.dts b/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk_nand.dts index 38a582ef86b..ec4541d44c9 100644 --- a/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk_nand.dts +++ b/dts/upstream/src/arm64/intel/socfpga_agilex5_socdk_nand.dts @@ -10,6 +10,7 @@ aliases { serial0 = &uart0; + ethernet0 = &gmac0; }; chosen { @@ -36,6 +37,23 @@ }; }; +&gmac0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac0_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts index b31cfa6b802..9ee312bae8d 100644 --- a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts +++ b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts @@ -116,6 +116,8 @@ cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk_nand.dts b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk_nand.dts index 0f9020bd0c5..98900cb410d 100644 --- a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk_nand.dts +++ b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk_nand.dts @@ -81,7 +81,7 @@ &nand { status = "okay"; - flash@0 { + nand@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; diff --git a/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts index 7952c7f47cc..0034a489722 100644 --- a/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts +++ b/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts @@ -93,6 +93,8 @@ cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; partitions { compatible = "fixed-partitions"; diff --git a/dts/upstream/src/arm64/marvell/armada-70x0.dtsi b/dts/upstream/src/arm64/marvell/armada-70x0.dtsi index 293403a1a33..df939426d25 100644 --- a/dts/upstream/src/arm64/marvell/armada-70x0.dtsi +++ b/dts/upstream/src/arm64/marvell/armada-70x0.dtsi @@ -56,7 +56,7 @@ marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp13"; marvell,function = "nf"; }; diff --git a/dts/upstream/src/arm64/marvell/armada-80x0.dtsi b/dts/upstream/src/arm64/marvell/armada-80x0.dtsi index ee67c70bf02..fb361d657a7 100644 --- a/dts/upstream/src/arm64/marvell/armada-80x0.dtsi +++ b/dts/upstream/src/arm64/marvell/armada-80x0.dtsi @@ -89,7 +89,7 @@ marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp13", "mpp12"; marvell,function = "nf"; }; diff --git a/dts/upstream/src/arm64/marvell/cn9130-db.dtsi b/dts/upstream/src/arm64/marvell/cn9130-db.dtsi index 50e9e072482..3cc320f569a 100644 --- a/dts/upstream/src/arm64/marvell/cn9130-db.dtsi +++ b/dts/upstream/src/arm64/marvell/cn9130-db.dtsi @@ -379,7 +379,7 @@ "mpp27"; marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp13"; marvell,function = "nf"; }; diff --git a/dts/upstream/src/arm64/marvell/cn9132-clearfog.dts b/dts/upstream/src/arm64/marvell/cn9132-clearfog.dts index 5cf83d8ca1f..2507896d58f 100644 --- a/dts/upstream/src/arm64/marvell/cn9132-clearfog.dts +++ b/dts/upstream/src/arm64/marvell/cn9132-clearfog.dts @@ -413,13 +413,7 @@ /* SRDS #0,#1,#2,#3 - PCIe */ &cp0_pcie0 { num-lanes = <4>; - /* - * The mvebu-comphy driver does not currently know how to pass correct - * lane-count to ATF while configuring the serdes lanes. - * Rely on bootloader configuration only. - * - * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; - */ + phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; status = "okay"; }; @@ -481,13 +475,7 @@ /* SRDS #0,#1 - PCIe */ &cp1_pcie0 { num-lanes = <2>; - /* - * The mvebu-comphy driver does not currently know how to pass correct - * lane-count to ATF while configuring the serdes lanes. - * Rely on bootloader configuration only. - * - * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; - */ + phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/marvell/mmp/pxa1908-samsung-coreprimevelte.dts b/dts/upstream/src/arm64/marvell/mmp/pxa1908-samsung-coreprimevelte.dts index 47a4f01a707..b2ce5edd9c6 100644 --- a/dts/upstream/src/arm64/marvell/mmp/pxa1908-samsung-coreprimevelte.dts +++ b/dts/upstream/src/arm64/marvell/mmp/pxa1908-samsung-coreprimevelte.dts @@ -10,6 +10,7 @@ aliases { mmc0 = &sdh2; /* eMMC */ mmc1 = &sdh0; /* SD card */ + mmc2 = &sdh1; /* SDIO */ serial0 = &uart0; }; @@ -23,6 +24,7 @@ fb0: framebuffer@17177000 { compatible = "simple-framebuffer"; reg = <0 0x17177000 0 (480 * 800 * 4)>; + power-domains = <&apmu PXA1908_POWER_DOMAIN_DSI>; width = <480>; height = <800>; stride = <(480 * 4)>; @@ -30,46 +32,26 @@ }; }; - /* Bootloader fills this in */ memory@0 { device_type = "memory"; - reg = <0 0 0 0>; + reg = <0 0 0 0x40000000>; }; reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; + /* + * Reserved by the vendor bootloader as a "secure region". + * + * TODO: See if the responsible stage of the bootloader can be + * replaced + */ + secure-region@0 { + reg = <0 0 0 0x1000000>; + }; framebuffer@17000000 { reg = <0 0x17000000 0 0x1800000>; no-map; }; - - gpu@9000000 { - reg = <0 0x9000000 0 0x1000000>; - }; - - /* Communications processor, aka modem */ - cp@5000000 { - reg = <0 0x5000000 0 0x3000000>; - }; - - cm3@a000000 { - reg = <0 0xa000000 0 0x80000>; - }; - - seclog@8000000 { - reg = <0 0x8000000 0 0x100000>; - }; - - ramoops@8100000 { - compatible = "ramoops"; - reg = <0 0x8100000 0 0x40000>; - record-size = <0x8000>; - console-size = <0x20000>; - max-reason = <5>; - }; }; i2c-muic { @@ -88,6 +70,12 @@ reg = <0x14>; interrupt-parent = <&gpio>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; @@ -115,6 +103,21 @@ gpios = <&gpio 17 GPIO_ACTIVE_LOW>; }; }; + + backlight { + compatible = "kinetic,ktd2801"; + ctrl-gpios = <&gpio 97 GPIO_ACTIVE_HIGH>; + max-brightness = <210>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwm-names = "enable"; + pwms = <&pwm3 100000>; + enable-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_pin>; + }; }; &smmu { @@ -286,6 +289,151 @@ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; pinctrl-single,low-power-mode = <0x208 0x388>; }; + + sdh1_pins_0: sdh1-pins-0 { + pinctrl-single,pins = < + 0x170 1 + 0x174 1 + 0x178 1 + 0x17c 1 + 0x180 1 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + sdh1_pins_1: sdh1-pins-1 { + pinctrl-single,pins = <0x184 1>; + pinctrl-single,drive-strength = <0 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0x208 0x388>; + }; + + sdh1_pins_2: sdh1-pins-2 { + pinctrl-single,pins = <0xec 0>; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + sdh1_fast_pins_0: sdh1-fast-pins-0 { + pinctrl-single,pins = < + 0x170 1 + 0x174 1 + 0x178 1 + 0x17c 1 + 0x180 1 + >; + pinctrl-single,drive-strength = <0x1800 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + sdh1_fast_pins_1: sdh1-fast-pins-1 { + pinctrl-single,pins = <0x184 1>; + pinctrl-single,drive-strength = <0x1800 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0x208 0x388>; + }; + + sdh2_pins_0: sdh2-pins-0 { + pinctrl-single,pins = < + 0x24 1 + 0x28 1 + 0x2c 1 + 0x30 1 + 0x34 1 + 0x38 1 + 0x3c 1 + 0x40 1 + >; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + sdh2_pins_1: sdh2-pins-1 { + pinctrl-single,pins = <0x64 1>; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0x208 0x388>; + }; + + sdh2_pins_2: sdh2-pins-2 { + pinctrl-single,pins = <0x5c 1>; + pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,low-power-mode = <0x288 0x388>; + }; + + sdh2_fast_pins_0: sdh2-fast-pins-0 { + pinctrl-single,pins = < + 0x24 1 + 0x28 1 + 0x2c 1 + 0x30 1 + 0x34 1 + 0x38 1 + 0x3c 1 + 0x40 1 + >; + pinctrl-single,drive-strength = <0x1800 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; + + sdh2_fast_pins_1: sdh2-fast-pins-1 { + pinctrl-single,pins = <0x64 1>; + pinctrl-single,drive-strength = <0x1800 0x1800>; + pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0x208 0x388>; + }; + + sdh2_fast_pins_2: sdh2-fast-pins-2 { + pinctrl-single,pins = <0x5c 1>; + pinctrl-single,drive-strength = <0x1800 0x1800>; + pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,low-power-mode = <0x288 0x388>; + }; + + vibrator_pin: vibrator-pin { + pinctrl-single,pins = <0x12c 0>; + pinctrl-single,drive-strength = <0x1000 0x1800>; + pinctrl-single,bias-pullup = <0x8000 0xc000 0x8000 0xc000>; + pinctrl-single,bias-pulldown = <0xa000 0xa000 0 0xa000>; + pinctrl-single,input-schmitt = <0 0x30>; + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode = <0 0x388>; + }; }; &uart0 { @@ -303,10 +451,46 @@ &twsi2 { status = "okay"; + + pmic@30 { + compatible = "marvell,88pm886-a1"; + reg = <0x30>; + interrupts = ; + wakeup-source; + + regulators { + ldo2: ldo2 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <3100000>; + }; + + ldo6: ldo6 { + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + + ldo14: ldo14 { + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; }; &twsi3 { status = "okay"; + + touchscreen@50 { + compatible = "imagis,ist3032c"; + reg = <0x50>; + interrupt-parent = <&gpio>; + interrupts = <72 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ldo2>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + }; }; &usb { @@ -314,18 +498,33 @@ }; &sdh2 { - /* Disabled for now because initialization fails with -ETIMEDOUT. */ - status = "disabled"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sdh2_pins_0 &sdh2_pins_1 &sdh2_pins_2>; + pinctrl-1 = <&sdh2_fast_pins_0 &sdh2_fast_pins_1 &sdh2_fast_pins_2>; bus-width = <8>; non-removable; mmc-ddr-1_8v; + mmc-hs200-1_8v; }; &sdh0 { pinctrl-names = "default"; pinctrl-0 = <&sdh0_pins_0 &sdh0_pins_1 &sdh0_pins_2>; - cd-gpios = <&gpio 11 0>; - cd-inverted; + cd-gpios = <&gpio 11 GPIO_ACTIVE_LOW>; bus-width = <4>; wp-inverted; + vmmc-supply = <&ldo14>; + vqmmc-supply = <&ldo6>; +}; + +&sdh1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sdh1_pins_0 &sdh1_pins_1 &sdh1_pins_2>; + pinctrl-1 = <&sdh1_fast_pins_0 &sdh1_fast_pins_1 &sdh1_pins_2>; + bus-width = <4>; + non-removable; +}; + +&pwm3 { + status = "okay"; }; diff --git a/dts/upstream/src/arm64/marvell/mmp/pxa1908.dtsi b/dts/upstream/src/arm64/marvell/mmp/pxa1908.dtsi index cf2b9109688..5778bfdb856 100644 --- a/dts/upstream/src/arm64/marvell/mmp/pxa1908.dtsi +++ b/dts/upstream/src/arm64/marvell/mmp/pxa1908.dtsi @@ -3,6 +3,7 @@ #include #include +#include / { model = "Marvell Armada PXA1908"; @@ -58,6 +59,20 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@8100000 { + compatible = "ramoops"; + reg = <0 0x8100000 0 0x40000>; + record-size = <0x8000>; + console-size = <0x20000>; + max-reason = <5>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -79,6 +94,7 @@ #iommu-cells = <1>; interrupts = , ; + power-domains = <&apmu PXA1908_POWER_DOMAIN_VPU>; status = "disabled"; }; @@ -195,6 +211,38 @@ }; }; + pwm0: pwm@1a000 { + compatible = "marvell,pxa250-pwm"; + reg = <0x1a000 0x10>; + clocks = <&apbc PXA1908_CLK_PWM0>; + #pwm-cells = <1>; + status = "disabled"; + }; + + pwm1: pwm@1a400 { + compatible = "marvell,pxa250-pwm"; + reg = <0x1a400 0x10>; + clocks = <&apbc PXA1908_CLK_PWM1>; + #pwm-cells = <1>; + status = "disabled"; + }; + + pwm2: pwm@1a800 { + compatible = "marvell,pxa250-pwm"; + reg = <0x1a800 0x10>; + clocks = <&apbc PXA1908_CLK_PWM2>; + #pwm-cells = <1>; + status = "disabled"; + }; + + pwm3: pwm@1ac00 { + compatible = "marvell,pxa250-pwm"; + reg = <0x1ac00 0x10>; + clocks = <&apbc PXA1908_CLK_PWM3>; + #pwm-cells = <1>; + status = "disabled"; + }; + pmx: pinmux@1e000 { compatible = "marvell,pxa1908-padconf", "pinconf-single"; reg = <0x1e000 0x330>; @@ -291,9 +339,10 @@ }; apmu: clock-controller@82800 { - compatible = "marvell,pxa1908-apmu"; + compatible = "marvell,pxa1908-apmu", "syscon"; reg = <0x82800 0x400>; #clock-cells = <1>; + #power-domain-cells = <1>; }; }; }; diff --git a/dts/upstream/src/arm64/mediatek/mt6878-pinfunc.h b/dts/upstream/src/arm64/mediatek/mt6878-pinfunc.h new file mode 100644 index 00000000000..4e8e475a745 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt6878-pinfunc.h @@ -0,0 +1,1201 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Light Hsieh + * + * Copyright (C) 2025 Igor Belwon + */ + +#ifndef __MT6878_PINFUNC_H +#define __MT6878_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_SRCLKENA1 (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_DBG_MON_A3 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SRCLKENA1 (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_SRCLKENA2 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_IDDIG (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_DBG_MON_A4 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_SRCLKENAI0 (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_DMIC_CLK (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_DBG_MON_A5 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_DMIC_DAT (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_DBG_MON_A6 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI7_CLK (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_ANT_SEL0 (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_MD_INT4 (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_DBG_MON_A7 (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_MD_INT0 (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_DBG_MON_A8 (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_ANT_SEL2 (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_MD_INT3 (MTK_PIN_NO(6) | 6) +#define PINMUX_GPIO6__FUNC_DBG_MON_B0 (MTK_PIN_NO(6) | 7) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_MI (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_ANT_SEL3 (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(7) | 4) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_IO_JTAG_TCK (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_IO_JTAG_TMS (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_IO_JTAG_TDI (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_IO_JTAG_TDO (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(13) | 6) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(16) | 6) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(17) | 6) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_CONN_BT_TXD (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 6) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_PWM_0 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SDA10 (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_DBG_MON_A9 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_PWM_1 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A10 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_PWM_2 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_SPI4_CSB (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A11 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_PWM_3 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_SPI4_MO (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_VBUSVALID (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 6) +#define PINMUX_GPIO22__FUNC_DBG_MON_A12 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_SPI4_MI (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_USB_DRVVBUS (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DAP_MD32_SWD (MTK_PIN_NO(23) | 6) +#define PINMUX_GPIO23__FUNC_DBG_MON_A13 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_SCL12 (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_SCL10 (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_CMVREF0 (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_CMFLASH0 (MTK_PIN_NO(24) | 6) +#define PINMUX_GPIO24__FUNC_DBG_MON_A14 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_SPI6_CLK (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_SCL11 (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_CMVREF1 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_CMFLASH1 (MTK_PIN_NO(25) | 6) +#define PINMUX_GPIO25__FUNC_DBG_MON_A15 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_SPI6_CSB (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_SDA11 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_CMVREF2 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_CMFLASH2 (MTK_PIN_NO(26) | 6) +#define PINMUX_GPIO26__FUNC_DBG_MON_A16 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_SPI6_MO (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_VBUSVALID (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_CMVREF3 (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_DMIC1_CLK (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_CMFLASH3 (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_A17 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_SPI6_MI (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_IDDIG (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_DMIC1_DAT (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_CMFLASH0 (MTK_PIN_NO(28) | 6) +#define PINMUX_GPIO28__FUNC_DBG_MON_A18 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_I2SIN2_BCK (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_MD_UTXD0 (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_MD32_1_TXD (MTK_PIN_NO(29) | 5) +#define PINMUX_GPIO29__FUNC_CONN_BT_TXD (MTK_PIN_NO(29) | 6) +#define PINMUX_GPIO29__FUNC_PTA_TXD (MTK_PIN_NO(29) | 7) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_I2SIN2_LRCK (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_MD_URXD0 (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_MD32_1_RXD (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_PTA_RXD (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_I2SOUT2_DO (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_MD_UTXD1 (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_HFRP_UTXD1 (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_MD32_0_TXD (MTK_PIN_NO(31) | 5) +#define PINMUX_GPIO31__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(31) | 6) +#define PINMUX_GPIO31__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(31) | 7) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_I2SIN2_DI (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_MD_URXD1 (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_HFRP_URXD1 (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_MD32_0_RXD (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(32) | 7) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_ANT_SEL0 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_SCL1 (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_MD_UCTS0 (MTK_PIN_NO(33) | 6) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_ANT_SEL1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_SDA1 (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_MD_URTS0 (MTK_PIN_NO(34) | 6) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_ANT_SEL2 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_UDI_TCK (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_MD_UCTS1 (MTK_PIN_NO(35) | 6) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_ANT_SEL3 (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_UDI_NTRST (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_MD_URTS1 (MTK_PIN_NO(36) | 6) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_ANT_SEL4 (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_UDI_TDI (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(37) | 6) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_ANT_SEL5 (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_UDI_TMS (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(38) | 6) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_ANT_SEL6 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_UDI_TDO (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 5) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_ANT_SEL7 (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_PMSR_SMAP (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_GPS_PPS (MTK_PIN_NO(40) | 5) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_I2SIN1_MCK (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_GPS_PPS (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_HFRP_UCTS1 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_TP_UCTS2_VCORE (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_ANT_SEL8 (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_DBG_MON_B1 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_I2SIN1_BCK (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_I2SIN4_BCK (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_HFRP_URTS1 (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_TP_URTS2_VCORE (MTK_PIN_NO(42) | 5) +#define PINMUX_GPIO42__FUNC_ANT_SEL9 (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_DBG_MON_B2 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_I2SIN1_LRCK (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_I2SIN4_LRCK (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_ANT_SEL10 (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_B3 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_I2SOUT1_DO (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_ANT_SEL11 (MTK_PIN_NO(44) | 6) +#define PINMUX_GPIO44__FUNC_DBG_MON_B4 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_I2SIN1_DI (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_AGPS_SYNC (MTK_PIN_NO(45) | 5) +#define PINMUX_GPIO45__FUNC_ANT_SEL12 (MTK_PIN_NO(45) | 6) +#define PINMUX_GPIO45__FUNC_DBG_MON_B5 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_SRCLKENAI0 (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_DBG_MON_B6 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_SRCLKENAI1 (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_DBG_MON_B7 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_UTXD0 (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_MD_UTXD1 (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_HFRP_UTXD1 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_MD32_0_TXD (MTK_PIN_NO(48) | 5) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_URXD0 (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_HFRP_URXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_MD32_0_RXD (MTK_PIN_NO(49) | 5) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_MD_UTXD0 (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(50) | 6) +#define PINMUX_GPIO50__FUNC_UTXD1 (MTK_PIN_NO(50) | 7) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_MD_URXD0 (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_TP_URXD1_VLP (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_TP_URXD2_VLP (MTK_PIN_NO(51) | 6) +#define PINMUX_GPIO51__FUNC_URXD1 (MTK_PIN_NO(51) | 7) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_KPROW0 (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_CMFLASH0 (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_SDA12 (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_DSI_TE1 (MTK_PIN_NO(52) | 4) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_KPROW1 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_CMFLASH1 (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_SCL12 (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_LCM_RST1 (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_EXTIF0_ACT (MTK_PIN_NO(53) | 6) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_KPCOL0_VLP (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_KPCOL0_VLP_A (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_KPCOL1 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_SDA12 (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_DISP_PWM1 (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_JTRSTN_SEL1_VCORE (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_SPI0_CLK (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_JTCK_SEL1_VCORE (MTK_PIN_NO(56) | 7) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_SPI0_CSB (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_JTMS_SEL1_VCORE (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_JTDO_SEL1_VCORE (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_JTDI_SEL1_VCORE (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_SCP_SPI1_CK (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_SPI1_CLK (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_SCP_SCL3 (MTK_PIN_NO(60) | 4) +#define PINMUX_GPIO60__FUNC_TP_GPIO0_AO (MTK_PIN_NO(60) | 5) +#define PINMUX_GPIO60__FUNC_UTXD0 (MTK_PIN_NO(60) | 6) +#define PINMUX_GPIO60__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(60) | 7) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_SCP_SPI1_CS (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_SPI1_CSB (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_TP_GPIO1_AO (MTK_PIN_NO(61) | 5) +#define PINMUX_GPIO61__FUNC_URXD0 (MTK_PIN_NO(61) | 6) +#define PINMUX_GPIO61__FUNC_TP_URXD2_VLP (MTK_PIN_NO(61) | 7) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_SCP_SPI1_MO (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_SPI1_MO (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SCP_SCL3 (MTK_PIN_NO(62) | 3) +#define PINMUX_GPIO62__FUNC_SCP_SDA3 (MTK_PIN_NO(62) | 4) +#define PINMUX_GPIO62__FUNC_TP_GPIO2_AO (MTK_PIN_NO(62) | 5) +#define PINMUX_GPIO62__FUNC_DBG_MON_B29 (MTK_PIN_NO(62) | 7) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_SCP_SPI1_MI (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_SPI1_MI (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_SCP_SDA3 (MTK_PIN_NO(63) | 3) +#define PINMUX_GPIO63__FUNC_TP_GPIO3_AO (MTK_PIN_NO(63) | 5) +#define PINMUX_GPIO63__FUNC_DBG_MON_B30 (MTK_PIN_NO(63) | 7) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_SCP_SPI2_CK (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_SPI2_CLK (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_SCP_SCL2 (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_TP_GPIO4_AO (MTK_PIN_NO(64) | 5) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_SCP_SPI2_CS (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_SPI2_CSB (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_TP_GPIO5_AO (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_DBG_MON_B31 (MTK_PIN_NO(65) | 7) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_SCP_SPI2_MO (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_SPI2_MO (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_SCP_SCL2 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_SCP_SDA2 (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_TP_GPIO6_AO (MTK_PIN_NO(66) | 5) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_SCP_SPI2_MI (MTK_PIN_NO(67) | 1) +#define PINMUX_GPIO67__FUNC_SPI2_MI (MTK_PIN_NO(67) | 2) +#define PINMUX_GPIO67__FUNC_SCP_SDA2 (MTK_PIN_NO(67) | 3) +#define PINMUX_GPIO67__FUNC_TP_GPIO7_AO (MTK_PIN_NO(67) | 5) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_SCP_SPI3_CK (MTK_PIN_NO(68) | 1) +#define PINMUX_GPIO68__FUNC_SPI3_CLK (MTK_PIN_NO(68) | 2) +#define PINMUX_GPIO68__FUNC_MD_INT4 (MTK_PIN_NO(68) | 3) +#define PINMUX_GPIO68__FUNC_SCP_SCL4 (MTK_PIN_NO(68) | 4) +#define PINMUX_GPIO68__FUNC_TP_GPIO8_AO (MTK_PIN_NO(68) | 5) +#define PINMUX_GPIO68__FUNC_DBG_MON_A19 (MTK_PIN_NO(68) | 7) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_SCP_SPI3_CS (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_SPI3_CSB (MTK_PIN_NO(69) | 2) +#define PINMUX_GPIO69__FUNC_MD_INT3 (MTK_PIN_NO(69) | 3) +#define PINMUX_GPIO69__FUNC_TP_GPIO9_AO (MTK_PIN_NO(69) | 5) +#define PINMUX_GPIO69__FUNC_DBG_MON_A20 (MTK_PIN_NO(69) | 7) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_SCP_SPI3_MO (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_SPI3_MO (MTK_PIN_NO(70) | 2) +#define PINMUX_GPIO70__FUNC_SCP_SCL4 (MTK_PIN_NO(70) | 3) +#define PINMUX_GPIO70__FUNC_SCP_SDA4 (MTK_PIN_NO(70) | 4) +#define PINMUX_GPIO70__FUNC_TP_GPIO10_AO (MTK_PIN_NO(70) | 5) +#define PINMUX_GPIO70__FUNC_DBG_MON_A21 (MTK_PIN_NO(70) | 7) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_SCP_SPI3_MI (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_SPI3_MI (MTK_PIN_NO(71) | 2) +#define PINMUX_GPIO71__FUNC_SCP_SDA4 (MTK_PIN_NO(71) | 3) +#define PINMUX_GPIO71__FUNC_MD_INT0 (MTK_PIN_NO(71) | 4) +#define PINMUX_GPIO71__FUNC_TP_GPIO11_AO (MTK_PIN_NO(71) | 5) +#define PINMUX_GPIO71__FUNC_DBG_MON_A22 (MTK_PIN_NO(71) | 7) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_SPI5_CLK (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_SCP_SPI0_CK (MTK_PIN_NO(72) | 2) +#define PINMUX_GPIO72__FUNC_UCTS2 (MTK_PIN_NO(72) | 3) +#define PINMUX_GPIO72__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(72) | 4) +#define PINMUX_GPIO72__FUNC_TP_GPIO12_AO (MTK_PIN_NO(72) | 5) +#define PINMUX_GPIO72__FUNC_EXTIF0_ACT (MTK_PIN_NO(72) | 6) +#define PINMUX_GPIO72__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(72) | 7) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_SPI5_CSB (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_SCP_SPI0_CS (MTK_PIN_NO(73) | 2) +#define PINMUX_GPIO73__FUNC_URTS2 (MTK_PIN_NO(73) | 3) +#define PINMUX_GPIO73__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(73) | 4) +#define PINMUX_GPIO73__FUNC_TP_GPIO13_AO (MTK_PIN_NO(73) | 5) +#define PINMUX_GPIO73__FUNC_EXTIF0_PRI (MTK_PIN_NO(73) | 6) +#define PINMUX_GPIO73__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(73) | 7) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_SPI5_MO (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_SCP_SPI0_MO (MTK_PIN_NO(74) | 2) +#define PINMUX_GPIO74__FUNC_UTXD2 (MTK_PIN_NO(74) | 3) +#define PINMUX_GPIO74__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(74) | 4) +#define PINMUX_GPIO74__FUNC_TP_GPIO14_AO (MTK_PIN_NO(74) | 5) +#define PINMUX_GPIO74__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(74) | 6) +#define PINMUX_GPIO74__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(74) | 7) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_SPI5_MI (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_SCP_SPI0_MI (MTK_PIN_NO(75) | 2) +#define PINMUX_GPIO75__FUNC_URXD2 (MTK_PIN_NO(75) | 3) +#define PINMUX_GPIO75__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(75) | 4) +#define PINMUX_GPIO75__FUNC_TP_GPIO15_AO (MTK_PIN_NO(75) | 5) +#define PINMUX_GPIO75__FUNC_DAP_MD32_SWD (MTK_PIN_NO(75) | 7) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_AP_GOOD (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(76) | 3) +#define PINMUX_GPIO76__FUNC_GPS_PPS (MTK_PIN_NO(76) | 4) +#define PINMUX_GPIO76__FUNC_PMSR_SMAP (MTK_PIN_NO(76) | 5) +#define PINMUX_GPIO76__FUNC_AGPS_SYNC (MTK_PIN_NO(76) | 6) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(77) | 2) +#define PINMUX_GPIO77__FUNC_UDI_TCK (MTK_PIN_NO(77) | 3) +#define PINMUX_GPIO77__FUNC_CONN_DSP_JCK (MTK_PIN_NO(77) | 4) +#define PINMUX_GPIO77__FUNC_TSFDC_EN (MTK_PIN_NO(77) | 6) +#define PINMUX_GPIO77__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(77) | 7) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(78) | 2) +#define PINMUX_GPIO78__FUNC_UDI_TMS (MTK_PIN_NO(78) | 3) +#define PINMUX_GPIO78__FUNC_CONN_DSP_JMS (MTK_PIN_NO(78) | 4) +#define PINMUX_GPIO78__FUNC_TSFDC_VCO_RST (MTK_PIN_NO(78) | 6) +#define PINMUX_GPIO78__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(78) | 7) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_MSDC1_DAT0 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(79) | 2) +#define PINMUX_GPIO79__FUNC_UDI_TDI (MTK_PIN_NO(79) | 3) +#define PINMUX_GPIO79__FUNC_CONN_DSP_JDI (MTK_PIN_NO(79) | 4) +#define PINMUX_GPIO79__FUNC_TSFDC_TSSEL2 (MTK_PIN_NO(79) | 6) +#define PINMUX_GPIO79__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(79) | 7) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_MSDC1_DAT1 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_UDI_TDO (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_CONN_DSP_JDO (MTK_PIN_NO(80) | 4) +#define PINMUX_GPIO80__FUNC_TSFDC_TSSEL1 (MTK_PIN_NO(80) | 6) +#define PINMUX_GPIO80__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(80) | 7) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_MSDC1_DAT2 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(81) | 2) +#define PINMUX_GPIO81__FUNC_UDI_NTRST (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(81) | 4) +#define PINMUX_GPIO81__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(81) | 5) +#define PINMUX_GPIO81__FUNC_TSFDC_TSSEL0 (MTK_PIN_NO(81) | 6) +#define PINMUX_GPIO81__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(81) | 7) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_MSDC1_DAT3 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(82) | 5) +#define PINMUX_GPIO82__FUNC_TSFDC_RCK_SELB (MTK_PIN_NO(82) | 6) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_TSFDC_26M (MTK_PIN_NO(83) | 6) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(84) | 3) +#define PINMUX_GPIO84__FUNC_APU_JTAG_TCK (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_TSFDC_SDO (MTK_PIN_NO(84) | 6) +#define PINMUX_GPIO84__FUNC_CONN_DSP_L5_JCK (MTK_PIN_NO(84) | 7) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_APU_JTAG_TRST (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_TSFDC_FOUT (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_CONN_DSP_L5_JINTP (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(86) | 3) +#define PINMUX_GPIO86__FUNC_APU_JTAG_TDI (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_TSFDC_SCK (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_CONN_DSP_L5_JDI (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(87) | 3) +#define PINMUX_GPIO87__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_TSFDC_SDI (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_CONN_DSP_L5_JMS (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_APU_JTAG_TDO (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_TSFDC_SCF (MTK_PIN_NO(88) | 6) +#define PINMUX_GPIO88__FUNC_CONN_DSP_L5_JDO (MTK_PIN_NO(88) | 7) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_DSI_TE (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_DBG_MON_B8 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_LCM_RST (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_DBG_MON_B9 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_DISP_PWM (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_DBG_MON_B10 (MTK_PIN_NO(91) | 7) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_CMMCLK0 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_DBG_MON_A23 (MTK_PIN_NO(92) | 7) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_CMMCLK1 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_DBG_MON_A24 (MTK_PIN_NO(93) | 7) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_DBG_MON_A25 (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_CMMCLK3 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_MD32_1_TXD (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_PTA_TXD (MTK_PIN_NO(95) | 6) +#define PINMUX_GPIO95__FUNC_DBG_MON_A26 (MTK_PIN_NO(95) | 7) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_CMMCLK4 (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_MD32_1_RXD (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_PTA_RXD (MTK_PIN_NO(96) | 6) +#define PINMUX_GPIO96__FUNC_DBG_MON_A27 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(97) | 1) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_DIGRF_IRQ (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_BPI_BUS0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_MFG_TSFDC_EN (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 6) +#define PINMUX_GPIO99__FUNC_DBG_MON_B11 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_BPI_BUS1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_MFG_TSFDC_VCO_RST (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 6) +#define PINMUX_GPIO100__FUNC_DBG_MON_B12 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_BPI_BUS2 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_MFG_TSFDC_TSSEL2 (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 6) +#define PINMUX_GPIO101__FUNC_DBG_MON_B13 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_BPI_BUS3 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_MFG_TSFDC_TSSEL1 (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_DBG_MON_B14 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_BPI_BUS4 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_MFG_TSFDC_TSSEL0 (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_DBG_MON_B15 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_BPI_BUS5 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_MFG_TSFDC_RCK_SELB (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_DBG_MON_B16 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_BPI_BUS6 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_DBG_MON_B17 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_BPI_BUS7 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_MFG_TSFDC_SDO (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_DBG_MON_B18 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_BPI_BUS8 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_MFG_TSFDC_FOUT (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_ANT_SEL8 (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_DBG_MON_B19 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_BPI_BUS9 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_ANT_SEL9 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_DBG_MON_B20 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_BPI_BUS10 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_ANT_SEL10 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_DBG_MON_B21 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_BPI_BUS11 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_ANT_SEL11 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_DBG_MON_B22 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_BPI_BUS12 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_CLKM0 (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_I2SIN4_BCK (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_ANT_SEL12 (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_DBG_MON_B23 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_BPI_BUS13 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_CLKM1 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_ANT_SEL13 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_DBG_MON_B24 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_BPI_BUS14 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_CLKM2 (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_ANT_SEL14 (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_DBG_MON_B25 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_BPI_BUS15 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_CLKM3 (MTK_PIN_NO(114) | 3) +#define PINMUX_GPIO114__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(114) | 5) +#define PINMUX_GPIO114__FUNC_ANT_SEL15 (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_DBG_MON_B26 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_BPI_BUS16 (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(115) | 5) +#define PINMUX_GPIO115__FUNC_ANT_SEL16 (MTK_PIN_NO(115) | 6) +#define PINMUX_GPIO115__FUNC_DBG_MON_B27 (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_BPI_BUS17 (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_I2SIN4_LRCK (MTK_PIN_NO(116) | 5) +#define PINMUX_GPIO116__FUNC_ANT_SEL17 (MTK_PIN_NO(116) | 6) +#define PINMUX_GPIO116__FUNC_DBG_MON_B28 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_BPI_BUS18 (MTK_PIN_NO(117) | 3) +#define PINMUX_GPIO117__FUNC_ANT_SEL18 (MTK_PIN_NO(117) | 6) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_BPI_BUS19 (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_ANT_SEL19 (MTK_PIN_NO(118) | 6) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_BPI_BUS20 (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_ANT_SEL20 (MTK_PIN_NO(119) | 6) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_BPI_BUS21 (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_ANT_SEL21 (MTK_PIN_NO(120) | 6) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_MIPI4_D_SCLK (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_BPI_BUS22 (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(121) | 6) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_MIPI4_D_SDATA (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_BPI_BUS23 (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(122) | 6) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_MIPI_M_SCLK (MTK_PIN_NO(123) | 1) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_MIPI_M_SDATA (MTK_PIN_NO(124) | 1) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_SCL0 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_SCP_SCL4 (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(125) | 4) +#define PINMUX_GPIO125__FUNC_TP_GPIO4_AO (MTK_PIN_NO(125) | 5) +#define PINMUX_GPIO125__FUNC_UTXD2 (MTK_PIN_NO(125) | 6) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_SDA0 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_SCP_SDA4 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_TP_URXD2_VLP (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_TP_URTS1_VLP (MTK_PIN_NO(126) | 4) +#define PINMUX_GPIO126__FUNC_TP_GPIO5_AO (MTK_PIN_NO(126) | 5) +#define PINMUX_GPIO126__FUNC_URXD2 (MTK_PIN_NO(126) | 6) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_SCL1 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_SCP_SCL5 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_TP_UCTS2_VLP (MTK_PIN_NO(127) | 3) +#define PINMUX_GPIO127__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_TP_GPIO6_AO (MTK_PIN_NO(127) | 5) +#define PINMUX_GPIO127__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(127) | 6) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_SDA1 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_SCP_SDA5 (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_TP_URTS2_VLP (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_TP_URXD1_VLP (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_TP_GPIO7_AO (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(128) | 6) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_SCL2 (MTK_PIN_NO(129) | 1) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_SDA2 (MTK_PIN_NO(130) | 1) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_SCL3 (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(131) | 6) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_SDA3 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(132) | 6) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_SCL4 (MTK_PIN_NO(133) | 1) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_SDA4 (MTK_PIN_NO(134) | 1) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_SCL5 (MTK_PIN_NO(135) | 1) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SDA5 (MTK_PIN_NO(136) | 1) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_SCL6 (MTK_PIN_NO(137) | 1) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_SDA6 (MTK_PIN_NO(138) | 1) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL7 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_MD_UTXD0 (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 6) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA7 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_MD_URXD0 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 6) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL8 (MTK_PIN_NO(141) | 1) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA8 (MTK_PIN_NO(142) | 1) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_SCL9 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_HFRP_UTXD1 (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(143) | 5) +#define PINMUX_GPIO143__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_SDA9 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_HFRP_URXD1 (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_SCL10 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_TP_GPIO8_AO (MTK_PIN_NO(145) | 5) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_SDA10 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_TP_GPIO9_AO (MTK_PIN_NO(146) | 5) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_SCL11 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_SCP_SCL1 (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_DMIC_CLK (MTK_PIN_NO(147) | 4) +#define PINMUX_GPIO147__FUNC_TP_GPIO10_AO (MTK_PIN_NO(147) | 5) +#define PINMUX_GPIO147__FUNC_EXTIF0_PRI (MTK_PIN_NO(147) | 6) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_SDA11 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_SCP_SDA1 (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_DMIC_DAT (MTK_PIN_NO(148) | 4) +#define PINMUX_GPIO148__FUNC_TP_GPIO11_AO (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(148) | 6) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_KPROW2 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_PWM_VLP (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_MD_INT0 (MTK_PIN_NO(149) | 4) +#define PINMUX_GPIO149__FUNC_TP_GPIO12_AO (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_SCL0 (MTK_PIN_NO(149) | 6) +#define PINMUX_GPIO149__FUNC_DBG_MON_A28 (MTK_PIN_NO(149) | 7) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_KPCOL2 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_PWM_VLP (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_CMMCLK5 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_MD_INT3 (MTK_PIN_NO(150) | 4) +#define PINMUX_GPIO150__FUNC_TP_GPIO13_AO (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_SDA0 (MTK_PIN_NO(150) | 6) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_SRCLKENAI0 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_MD_INT4 (MTK_PIN_NO(151) | 4) +#define PINMUX_GPIO151__FUNC_TP_GPIO14_AO (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_DBG_MON_A29 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_SRCLKENAI1 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(152) | 4) +#define PINMUX_GPIO152__FUNC_TP_GPIO15_AO (MTK_PIN_NO(152) | 5) +#define PINMUX_GPIO152__FUNC_DBG_MON_A30 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DISP_PWM1 (MTK_PIN_NO(153) | 2) +#define PINMUX_GPIO153__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_DBG_MON_A0 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_LCM_RST1 (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_CMFLASH2 (MTK_PIN_NO(154) | 4) +#define PINMUX_GPIO154__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(154) | 5) +#define PINMUX_GPIO154__FUNC_DBG_MON_A1 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_DSI_TE1 (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_CMFLASH3 (MTK_PIN_NO(155) | 4) +#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 5) +#define PINMUX_GPIO155__FUNC_DBG_MON_A2 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_SPMI_M_SCL (MTK_PIN_NO(156) | 1) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_SPMI_M_SDA (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_SPMI_P_SCL (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_SPMI_P_SDA (MTK_PIN_NO(159) | 1) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_SRCLKENA0 (MTK_PIN_NO(160) | 1) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(161) | 1) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_RTC32K_CK (MTK_PIN_NO(162) | 1) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_WATCHDOG (MTK_PIN_NO(163) | 1) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_AUD_CLK_MOSI_A (MTK_PIN_NO(164) | 3) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(165) | 1) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_AUD_DAT_MOSI0_A (MTK_PIN_NO(166) | 3) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_AUD_DAT_MOSI1_A (MTK_PIN_NO(167) | 3) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(168) | 2) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_AUD_CLK_MISO (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_AUD_CLK_MISO_A (MTK_PIN_NO(169) | 3) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_VOW_DAT_MISO (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_AUD_DAT_MISO0_A (MTK_PIN_NO(170) | 3) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_VOW_CLK_MISO (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_AUD_DAT_MISO1_A (MTK_PIN_NO(171) | 3) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_DBG_MON_A31 (MTK_PIN_NO(172) | 7) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_CONN_BT_CLK (MTK_PIN_NO(174) | 1) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_CONN_BT_DATA (MTK_PIN_NO(175) | 1) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_CONN_HRST_B (MTK_PIN_NO(176) | 1) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_CONN_WB_PTA (MTK_PIN_NO(177) | 1) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_CONN_TOP_CLK_2 (MTK_PIN_NO(181) | 2) +#define PINMUX_GPIO181__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(181) | 3) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_CONN_TOP_DATA_2 (MTK_PIN_NO(182) | 2) +#define PINMUX_GPIO182__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(182) | 3) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_CONN_HRST_B_2 (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_MSDC0_DSL (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_ANT_SEL13 (MTK_PIN_NO(184) | 3) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_MSDC0_CLK (MTK_PIN_NO(185) | 1) +#define PINMUX_GPIO185__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(185) | 2) +#define PINMUX_GPIO185__FUNC_ANT_SEL14 (MTK_PIN_NO(185) | 3) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_MSDC0_CMD (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(186) | 2) +#define PINMUX_GPIO186__FUNC_ANT_SEL15 (MTK_PIN_NO(186) | 3) +#define PINMUX_GPIO186__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(186) | 5) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_MSDC0_RSTB (MTK_PIN_NO(187) | 1) +#define PINMUX_GPIO187__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(187) | 2) +#define PINMUX_GPIO187__FUNC_ANT_SEL16 (MTK_PIN_NO(187) | 3) +#define PINMUX_GPIO187__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(187) | 5) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_MSDC0_DAT0 (MTK_PIN_NO(188) | 1) +#define PINMUX_GPIO188__FUNC_ANT_SEL17 (MTK_PIN_NO(188) | 3) +#define PINMUX_GPIO188__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(188) | 5) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_MSDC0_DAT1 (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_ANT_SEL18 (MTK_PIN_NO(189) | 3) +#define PINMUX_GPIO189__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(189) | 5) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_MSDC0_DAT2 (MTK_PIN_NO(190) | 1) +#define PINMUX_GPIO190__FUNC_DMIC1_CLK (MTK_PIN_NO(190) | 2) +#define PINMUX_GPIO190__FUNC_ANT_SEL19 (MTK_PIN_NO(190) | 3) +#define PINMUX_GPIO190__FUNC_I2SIN4_BCK (MTK_PIN_NO(190) | 5) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_MSDC0_DAT3 (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_DMIC1_DAT (MTK_PIN_NO(191) | 2) +#define PINMUX_GPIO191__FUNC_ANT_SEL20 (MTK_PIN_NO(191) | 3) +#define PINMUX_GPIO191__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(191) | 5) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_MSDC0_DAT4 (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_IDDIG (MTK_PIN_NO(192) | 2) +#define PINMUX_GPIO192__FUNC_ANT_SEL21 (MTK_PIN_NO(192) | 3) +#define PINMUX_GPIO192__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(192) | 4) +#define PINMUX_GPIO192__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(192) | 5) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_MSDC0_DAT5 (MTK_PIN_NO(193) | 1) +#define PINMUX_GPIO193__FUNC_USB_DRVVBUS (MTK_PIN_NO(193) | 2) +#define PINMUX_GPIO193__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(193) | 4) +#define PINMUX_GPIO193__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(193) | 5) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_MSDC0_DAT6 (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_VBUSVALID (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(194) | 5) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_MSDC0_DAT7 (MTK_PIN_NO(195) | 1) +#define PINMUX_GPIO195__FUNC_I2SIN4_LRCK (MTK_PIN_NO(195) | 5) + +#endif /* __MT6878_PINFUNC_H */ diff --git a/dts/upstream/src/arm64/mediatek/mt7622.dtsi b/dts/upstream/src/arm64/mediatek/mt7622.dtsi index 917fa39a74f..158bd9a305d 100644 --- a/dts/upstream/src/arm64/mediatek/mt7622.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt7622.dtsi @@ -278,6 +278,10 @@ #address-cells = <1>; #size-cells = <1>; + soc-uuid@140 { + reg = <0x140 0x8>; + }; + thermal_calibration: calib@198 { reg = <0x198 0xc>; }; diff --git a/dts/upstream/src/arm64/mediatek/mt7981b-openwrt-one.dts b/dts/upstream/src/arm64/mediatek/mt7981b-openwrt-one.dts index 4f6cbb49128..2e39e728773 100644 --- a/dts/upstream/src/arm64/mediatek/mt7981b-openwrt-one.dts +++ b/dts/upstream/src/arm64/mediatek/mt7981b-openwrt-one.dts @@ -3,13 +3,163 @@ /dts-v1/; #include "mt7981b.dtsi" +#include +#include +#include "dt-bindings/pinctrl/mt65xx.h" / { compatible = "openwrt,one", "mediatek,mt7981b"; model = "OpenWrt One"; + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + memory@40000000 { reg = <0 0x40000000 0 0x40000000>; device_type = "memory"; }; + + pwm-leds { + compatible = "pwm-leds"; + + led-0 { + color = ; + default-brightness = <0>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + pwms = <&pwm 0 10000>; + }; + + led-1 { + color = ; + default-brightness = <0>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + pwms = <&pwm 1 10000>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + }; +}; + +&pio { + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0_0", "pwm1_1"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2"; + }; + + conf-pu { + bias-pull-up = ; + drive-strength = <8>; + pins = "SPI2_CS", "SPI2_WP"; + }; + + conf-pd { + bias-pull-down = ; + drive-strength = <8>; + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x00000 0x40000>; + label = "bl2-nor"; + }; + + partition@40000 { + reg = <0x40000 0xc0000>; + label = "factory"; + read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + wifi_factory_calibration: eeprom@0 { + reg = <0x0 0x1000>; + }; + + wan_factory_mac: macaddr@24 { + reg = <0x24 0x6>; + compatible = "mac-base"; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@100000 { + reg = <0x100000 0x80000>; + label = "fip-nor"; + }; + + partition@180000 { + reg = <0x180000 0xc80000>; + label = "recovery"; + }; + }; + }; +}; + +&uart0 { + status = "okay"; }; diff --git a/dts/upstream/src/arm64/mediatek/mt7981b.dtsi b/dts/upstream/src/arm64/mediatek/mt7981b.dtsi index 277c11247c1..416096b8077 100644 --- a/dts/upstream/src/arm64/mediatek/mt7981b.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt7981b.dtsi @@ -41,6 +41,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + soc { compatible = "simple-bus"; ranges; @@ -82,7 +94,7 @@ #clock-cells = <1>; }; - pwm@10048000 { + pwm: pwm@10048000 { compatible = "mediatek,mt7981-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_PWM_STA>, @@ -94,7 +106,7 @@ #pwm-cells = <2>; }; - serial@11002000 { + uart0: serial@11002000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x100>; interrupts = ; @@ -102,10 +114,12 @@ clocks = <&infracfg CLK_INFRA_UART0_SEL>, <&infracfg CLK_INFRA_UART0_CK>; clock-names = "baud", "bus"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "disabled"; }; - serial@11003000 { + uart1: serial@11003000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x100>; interrupts = ; @@ -116,7 +130,7 @@ status = "disabled"; }; - serial@11004000 { + uart2: serial@11004000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x100>; interrupts = ; @@ -142,7 +156,7 @@ status = "disabled"; }; - spi@11009000 { + spi2: spi@11009000 { compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; reg = <0 0x11009000 0 0x1000>; interrupts = ; @@ -229,6 +243,13 @@ gpio-controller; #gpio-cells = <2>; #interrupt-cells = <2>; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; }; efuse@11f20000 { @@ -237,6 +258,10 @@ #address-cells = <1>; #size-cells = <1>; + soc-uuid@140 { + reg = <0x140 0x10>; + }; + thermal_calibration: thermal-calib@274 { reg = <0x274 0xc>; }; diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts index e7654dc9a1c..19f538d160a 100644 --- a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -42,7 +42,7 @@ compatible = "pwm-fan"; #cooling-cells = <2>; /* cooling level (0, 1, 2) - pwm inverted */ - cooling-levels = <255 96 0>; + cooling-levels = <255 40 0>; pwms = <&pwm 0 10000>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/mediatek/mt7986a.dtsi b/dts/upstream/src/arm64/mediatek/mt7986a.dtsi index a8972330a7b..7790601586c 100644 --- a/dts/upstream/src/arm64/mediatek/mt7986a.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt7986a.dtsi @@ -450,6 +450,10 @@ #address-cells = <1>; #size-cells = <1>; + soc-uuid@140 { + reg = <0x140 0x8>; + }; + thermal_calibration: calib@274 { reg = <0x274 0xc>; }; diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts index 6f0c81e3fd9..0e41c07d3a5 100644 --- a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts @@ -19,4 +19,5 @@ &int_2p5g_phy { pinctrl-0 = <&i2p5gbe_led0_pins>; pinctrl-names = "i2p5gbe-led"; + status = "okay"; }; diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts new file mode 100644 index 00000000000..c7ea6e88c4f --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; + +#include "mt7988a-bananapi-bpi-r4-pro.dtsi" + +/ { + model = "Bananapi BPI-R4"; + compatible = "bananapi,bpi-r4-pro-4e", + "bananapi,bpi-r4-pro", + "mediatek,mt7988a"; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts new file mode 100644 index 00000000000..c9a0e69e9dd --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; + +#include "mt7988a-bananapi-bpi-r4-pro.dtsi" + +/ { + model = "Bananapi BPI-R4"; + compatible = "bananapi,bpi-r4-pro-8x", + "bananapi,bpi-r4-pro", + "mediatek,mt7988a"; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso new file mode 100644 index 00000000000..9750916042d --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/* This enables key-b slot CN15 on pcie2(11280000 1L0) on BPI-R4-Pro */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/pinctrl@1001f000/pcie-2-hog} { + output-low; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso new file mode 100644 index 00000000000..9830fb0fd97 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/* This enables key-b slot CN18 on pcie3(11290000 1L1) on BPI-R4-Pro */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/pinctrl@1001f000/pcie-3-hog} { + output-low; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso new file mode 100644 index 00000000000..5ed2f0a6bd6 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/mmc@11230000} { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_emmc_51>; + pinctrl-1 = <&mmc0_pins_emmc_51>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x12814>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_3p3v>; + non-removable; + no-sd; + no-sdio; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso new file mode 100644 index 00000000000..1ec1a9fbd8b --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a"; +}; + +&{/soc/mmc@11230000} { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_sdcard>; + pinctrl-1 = <&mmc0_pins_sdcard>; + cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-mmc; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi new file mode 100644 index 00000000000..a48132f0941 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam.Shih + * Author: Frank Wunderlich + */ + +/dts-v1/; + +#include "mt7988a.dtsi" +#include +#include +#include +#include + +/ { + aliases { + ethernet0 = &gmac0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + /* PCA9548 (0-0070) provides 4 i2c channels */ + i2c3 = &imux0; + i2c4 = &imux1_sfp1; + i2c5 = &imux2_sfp2; + i2c6 = &imux3_wifi; + }; + + chosen { + stdout-path = &serial0; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */ + cooling-levels = <0 80 128 255>; + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + pwms = <&pwm 0 50000>; + #cooling-cells = <2>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "reset"; + gpios = <&pio 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-wps { + label = "WPS"; + gpios = <&pio 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_red: sys-led-red { + color = ; + gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_blue: sys-led-blue { + color = ; + gpios = <&pca9555 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_1p8v: regulator-dvdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "DVDD1V8_SOC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3v3vd { + compatible = "regulator-fixed"; + regulator-name = "3V3VD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* SFP1 cage (LAN) */ + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&imux1_sfp1>; + los-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 21 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + /* SFP2 cage (WAN) */ + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&imux2_sfp2>; + los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 1 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; +}; + +&cci { + proc-supply = <&rt5190_buck3>; +}; + +&cpu0 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu1 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu2 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu3 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu_thermal { + trips { + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map-cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + map-cpu-active-med { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_med>; + }; + + map-cpu-active-low { + /* active: set fan to cooling level 0 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + }; +}; + +ð { + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fan { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + pwms = <&pwm 0 50000>; + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&gsw_phy0 { + pinctrl-0 = <&gbe0_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy0_led0 { + color = ; + status = "okay"; +}; + +&gsw_port0 { + label = "mgmt"; +}; + +/* R4Pro has only port 0 connected, so disable the others */ +&gsw_phy1 { + status = "disabled"; +}; + +&gsw_port1 { + status = "disabled"; +}; + +&gsw_phy2 { + status = "disabled"; +}; + +&gsw_port2 { + status = "disabled"; +}; + +&gsw_phy3 { + status = "disabled"; +}; + +&gsw_port3 { + status = "disabled"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; + + rt5190a_64: rt5190a@64 { + compatible = "richtek,rt5190a"; + reg = <0x64>; + vin2-supply = <&rt5190_buck1>; + vin3-supply = <&rt5190_buck1>; + vin4-supply = <&rt5190_buck1>; + + regulators { + rt5190_buck1: buck1 { + regulator-name = "rt5190a-buck1"; + regulator-min-microvolt = <5090000>; + regulator-max-microvolt = <5090000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + + buck2 { + regulator-name = "vcore"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + rt5190_buck3: buck3 { + regulator-name = "vproc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4 { + regulator-name = "rt5190a-buck4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + + ldo { + regulator-name = "rt5190a-ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_1_pins>; + pinctrl-names = "default"; + status = "okay"; + + pca9545: i2c-mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + imux0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555: i2c-gpio-expander@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + address-width = <8>; + pagesize = <8>; + size = <256>; + }; + }; + + imux1_sfp1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux2_sfp2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + imux3_wifi: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* mPCIe SIM2 (11300000) */ +&pcie0 { + status = "okay"; +}; + +/* mPCIe (11310000 near leds) SIM3 */ +&pcie1 { + status = "okay"; +}; + +/* M.2 (11280000) 1L0 key-m SSD1 CN13 / key-b SIM1 CN15 */ +&pcie2 { + status = "okay"; +}; + +/* M.2 (11290000) 1L1 key-m SSD2 CN14 / key-b SIM2 CN18 */ +&pcie3 { + status = "okay"; +}; + +&pio { + gbe0_led0_pins: gbe0-led0-pins { + mux { + function = "led"; + groups = "gbe0_led0"; + }; + }; + + i2c0_pins: i2c0-g0-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-g0-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c2_1_pins: i2c2-g1-pins { + mux { + function = "i2c"; + groups = "i2c2_1"; + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + pins = "SMI_0_MDC", "SMI_0_MDIO"; + drive-strength = <8>; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-sdcard-pins { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + /* 1L0 0=key-b (CN15), 1=key-m (CN13) */ + pcie-2-hog { + gpio-hog; + gpios = <79 GPIO_ACTIVE_HIGH>; + output-high; + }; + + /* 1L1 0=key-b (CN18), 1=key-m (CN14) */ + pcie-3-hog { + gpio-hog; + gpios = <63 GPIO_ACTIVE_HIGH>; + output-high; + }; + + pwm0_pins: pwm0-pins { + mux { + groups = "pwm0"; + function = "pwm"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; +}; + +&pwm { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_flash_pins>; + pinctrl-names = "default"; + status = "okay"; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&spi_nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x200000>; + label = "bl2"; + }; + + partition@200000 { + compatible = "linux,ubi"; + reg = <0x200000 0xfe00000>; + label = "ubi"; + }; + }; +}; + +/* back USB */ +&ssusb0 { + /* Use U2P only instead of both U3P/U2P due to U3P serdes shared with pcie2 */ + phys = <&xphyu2port0 PHY_TYPE_USB2>; + mediatek,u3p-dis-msk = <1>; + status = "okay"; +}; + +/* front USB */ +&ssusb1 { + status = "okay"; +}; + +&switch { + dsa,member = <1 0>; + status = "okay"; +}; + +&tphy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&xsphy { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi index 366203a72d6..bec590d2665 100644 --- a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi @@ -418,7 +418,7 @@ nvmem-cell-names = "lvts-calib-data-1"; }; - usb@11190000 { + ssusb0: usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, <0 0x11193e00 0 0x0100>; @@ -714,6 +714,10 @@ #address-cells = <1>; #size-cells = <1>; + soc-uuid@140 { + reg = <0x140 0x10>; + }; + lvts_calibration: calib@918 { reg = <0x918 0x28>; }; @@ -995,6 +999,7 @@ int_2p5g_phy: ethernet-phy@15 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <15>; + status = "disabled"; }; }; }; diff --git a/dts/upstream/src/arm64/mediatek/mt8183.dtsi b/dts/upstream/src/arm64/mediatek/mt8183.dtsi index 960d8955d01..4e20a8f2eb2 100644 --- a/dts/upstream/src/arm64/mediatek/mt8183.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt8183.dtsi @@ -1445,11 +1445,11 @@ }; }; - audiosys: audio-controller@11220000 { + audiosys: clock-controller@11220000 { compatible = "mediatek,mt8183-audiosys", "syscon"; reg = <0 0x11220000 0 0x1000>; #clock-cells = <1>; - afe: mt8183-afe-pcm { + afe: audio-controller { compatible = "mediatek,mt8183-audio"; interrupts = ; resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; diff --git a/dts/upstream/src/arm64/mediatek/mt8195.dtsi b/dts/upstream/src/arm64/mediatek/mt8195.dtsi index ec452d65703..c7adafaa832 100644 --- a/dts/upstream/src/arm64/mediatek/mt8195.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt8195.dtsi @@ -3067,7 +3067,7 @@ jpgdec@0,10000 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0 0x10000 0x10000>;/* JPGDEC_C1 */ + reg = <0 0x10000 0 0x10000>;/* JPGDEC_C1 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, diff --git a/dts/upstream/src/arm64/mediatek/mt8196-gce.h b/dts/upstream/src/arm64/mediatek/mt8196-gce.h new file mode 100644 index 00000000000..aa909e4f496 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt8196-gce.h @@ -0,0 +1,612 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2025 MediaTek Inc. + * + */ + +#ifndef __DTS_GCE_MT8196_H +#define __DTS_GCE_MT8196_H + +/* GCE Thread Priority + * The GCE core has multiple GCE threads, each of which can independently + * execute its own sequence of instructions. + * However, the GCE threads on the same core cannot run in parallel. + * Different GCE threads can determine thread priority based on the scenario, + * thereby serving different user needs. + * + * Low priority thread is executed when no high priority thread is active. + * Same priority thread is scheduled by round robin. + */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_1 1 +#define CMDQ_THR_PRIO_2 2 +#define CMDQ_THR_PRIO_3 3 +#define CMDQ_THR_PRIO_4 4 +#define CMDQ_THR_PRIO_5 5 +#define CMDQ_THR_PRIO_6 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +/* + * GCE0 Hardware Event IDs + * Different SoCs will have varying numbers of hardware event signals, + * which are sent from the corresponding hardware to the GCE. + * Each hardware event signal corresponds to an event ID in the GCE. + * The CMDQ driver can use the following event ID definitions to allow + * the client driver to use wait and clear APIs provided by CMDQ, enabling + * the GCE to execute operations in the instructions for that event ID. + * + * The event IDs of GCE0 are mainly used by display hardware. + */ +/* CMDQ_EVENT_DISP0_STREAM_SOF0 ~ 15: 0 ~ 15 */ +#define CMDQ_EVENT_DISP0_STREAM_SOF(n) (0 + (n)) +/* CMDQ_EVENT_DISP0_FRAME_DONE_SEL0 ~ 15: 16 ~ 31 */ +#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL(n) (16 + (n)) +#define CMDQ_EVENT_DISP0_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 32 +#define CMDQ_EVENT_DISP0_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 33 +#define CMDQ_EVENT_DISP0_DISP_POSTMASK1_RST_DONE_ENG_EVENT 34 +#define CMDQ_EVENT_DISP0_DISP_POSTMASK0_RST_DONE_ENG_EVENT 35 +#define CMDQ_EVENT_DISP0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 36 +/* CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT0 ~ 15: 37 ~ 52 */ +#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT(n) (37 + (n)) +#define CMDQ_EVENT_DISP0_DISP_MUTEX0_GET_RELEASE_ENG_EVENT 53 +#define CMDQ_EVENT_DISP0_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 54 +/* CMDQ_EVENT_DISP1_STREAM_SOF0 ~ 15: 55 ~ 70 */ +#define CMDQ_EVENT_DISP1_STREAM_SOF(n) (55 + (n)) +/* CMDQ_EVENT_DISP1_FRAME_DONE_SEL0 ~ 15: 71 ~ 86 */ +#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL(n) (71 + (n)) +/* CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT0 ~ 15: 87 ~ 102 */ +#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT(n) (87 + (n)) +/* CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 103 ~ 118 */ +#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT(n) (103 + (n)) +#define CMDQ_EVENT_DISP1_OCIP_SUBSYS_SRAM_ISOINT_ENG_EVENT 119 +#define CMDQ_EVENT_DISP1_DISP_WDMA4_TARGET_LINE_END_ENG_EVENT 120 +#define CMDQ_EVENT_DISP1_DISP_WDMA4_SW_RST_DONE_ENG_EVENT 121 +#define CMDQ_EVENT_DISP1_DISP_WDMA3_TARGET_LINE_END_ENG_EVENT 122 +#define CMDQ_EVENT_DISP1_DISP_WDMA3_SW_RST_DONE_ENG_EVENT 123 +#define CMDQ_EVENT_DISP1_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT 124 +#define CMDQ_EVENT_DISP1_DISP_WDMA2_SW_RST_DONE_ENG_EVENT 125 +#define CMDQ_EVENT_DISP1_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 126 +#define CMDQ_EVENT_DISP1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 127 +#define CMDQ_EVENT_DISP1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 128 +#define CMDQ_EVENT_DISP1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 129 +#define CMDQ_EVENT_DISP1_DISP_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 130 +#define CMDQ_EVENT_DISP1_DISP_GDMA0_SW_RST_DONE_ENG_EVENT 131 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_START_ENG_EVENT 132 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_END_ENG_EVENT 133 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VRR_VFP_LAST_SAFE_BLANK_ENG_EVENT 134 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_START_ENG_EVENT 135 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_LAST_LINE_ENG_EVENT 136 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VDE_END_ENG_EVENT 137 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TRIGGER_LOOP_CLR_ENG_EVENT 138 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE1_ENG_EVENT 139 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE0_ENG_EVENT 140 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_START_ENG_EVENT 141 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_END_ENG_EVENT 142 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_START_ENG_EVENT 143 +#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_END_ENG_EVENT 144 +/* CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT0 ~ 10: 145 ~ 155 */ +#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT(n) (145 + (n)) +/* CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT0 ~ 21: 156 ~ 177 */ +#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT(n) (156 + (n)) +/* CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT0 ~ 10: 178 ~ 188 */ +#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT(n) (178 + (n)) +#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_START_ENG_EVENT 189 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_END_ENG_EVENT 190 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_START_ENG_EVENT 191 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_END_ENG_EVENT 192 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_TARGET_LINE_ENG_EVENT 193 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_START_ENG_EVENT 194 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_END_ENG_EVENT 195 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_START_ENG_EVENT 196 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_END_ENG_EVENT 197 +#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT 198 +/* CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT0 ~ 10: 199 ~ 209 */ +#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT(n) (199 + (n)) +/* CMDQ_EVENT_MML0_STREAM_SOF0 ~ 15: 210 ~ 225 */ +#define CMDQ_EVENT_MML0_STREAM_SOF(n) (210 + (n)) +/* CMDQ_EVENT_MML0_FRAME_DONE_SEL0 ~ 15: 226 ~ 241 */ +#define CMDQ_EVENT_MML0_FRAME_DONE_SEL(n) (226 + (n)) +/* CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 242 ~ 257 */ +#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT(n) (242 + (n)) +#define CMDQ_EVENT_MML0_MDP_WROT2_SW_RST_DONE_ENG_EVENT 258 +#define CMDQ_EVENT_MML0_MDP_WROT1_SW_RST_DONE_ENG_EVENT 259 +#define CMDQ_EVENT_MML0_MDP_WROT0_SW_RST_DONE_ENG_EVENT 260 +#define CMDQ_EVENT_MML0_MDP_RROT0_SW_RST_DONE_ENG_EVENT 261 +#define CMDQ_EVENT_MML0_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 262 +#define CMDQ_EVENT_MML0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 263 +#define CMDQ_EVENT_MML0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 264 +#define CMDQ_EVENT_MML0_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 265 +#define CMDQ_EVENT_MML0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 266 +#define CMDQ_EVENT_MML0_DISP_MUTEX0_GET_RLZ_ENG_EVENT 267 +/* CMDQ_EVENT_MML1_STREAM_SOF0 ~ 15: 268 ~ 283 */ +#define CMDQ_EVENT_MML1_STREAM_SOF(n) (268 + (n)) +/* CMDQ_EVENT_MML1_FRAME_DONE_SEL0 ~ 15: 284 ~ 299 */ +#define CMDQ_EVENT_MML1_FRAME_DONE_SEL(n) (284 + (n)) +/* CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 300 ~ 315 */ +#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT(n) (300 + (n)) +#define CMDQ_EVENT_MML1_MDP_WROT2_SW_RST_DONE_ENG_EVENT 316 +#define CMDQ_EVENT_MML1_MDP_WROT1_SW_RST_DONE_ENG_EVENT 317 +#define CMDQ_EVENT_MML1_MDP_WROT0_SW_RST_DONE_ENG_EVENT 318 +#define CMDQ_EVENT_MML1_MDP_RROT0_SW_RST_DONE_ENG_EVENT 319 +#define CMDQ_EVENT_MML1_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 320 +#define CMDQ_EVENT_MML1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 321 +#define CMDQ_EVENT_MML1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 322 +#define CMDQ_EVENT_MML1_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 323 +#define CMDQ_EVENT_MML1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 324 +#define CMDQ_EVENT_MML1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 325 +/* CMDQ_EVENT_OVL0_STREAM_SOF0 ~ 15: 326 ~ 341 */ +#define CMDQ_EVENT_OVL0_STREAM_SOF(n) (326 + (n)) +/* CMDQ_EVENT_OVL0_FRAME_DONE_SEL0 ~ 15: 342 ~ 357 */ +#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL(n) (342 + (n)) +#define CMDQ_EVENT_OVL0_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 358 +#define CMDQ_EVENT_OVL0_OVL_MUTEX0_TIMEOUT_ENG_EVENT 359 +/* CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 360 ~ 375 */ +#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n) (360 + (n)) +#define CMDQ_EVENT_OVL0_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 376 +#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 377 +#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 378 +#define CMDQ_EVENT_OVL0_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 379 +#define CMDQ_EVENT_OVL0_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 380 +#define CMDQ_EVENT_OVL0_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 381 +#define CMDQ_EVENT_OVL0_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 382 +#define CMDQ_EVENT_OVL0_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 383 +#define CMDQ_EVENT_OVL0_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 384 +#define CMDQ_EVENT_OVL0_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 385 +#define CMDQ_EVENT_OVL0_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 386 +#define CMDQ_EVENT_OVL0_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 387 +#define CMDQ_EVENT_OVL0_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 388 +#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 389 +#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 390 +#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 391 +#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 392 +#define CMDQ_EVENT_OVL0_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 393 +/* CMDQ_EVENT_OVL1_STREAM_SOF0 ~ 15: 394 ~ 409 */ +#define CMDQ_EVENT_OVL1_STREAM_SOF(n) (394 + (n)) +/* CMDQ_EVENT_OVL1_FRAME_DONE_SEL0 ~ 15: 410 ~ 425 */ +#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL(n) (410 + (n)) +#define CMDQ_EVENT_OVL1_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 426 +#define CMDQ_EVENT_OVL1_OVL_MUTEX0_TIMEOUT_ENG_EVENT 427 +/* CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 428 ~ 443 */ +#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n) (428 + (n)) +#define CMDQ_EVENT_OVL1_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 444 +#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 445 +#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 446 +#define CMDQ_EVENT_OVL1_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 447 +#define CMDQ_EVENT_OVL1_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 448 +#define CMDQ_EVENT_OVL1_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 449 +#define CMDQ_EVENT_OVL1_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 450 +#define CMDQ_EVENT_OVL1_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 451 +#define CMDQ_EVENT_OVL1_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 452 +#define CMDQ_EVENT_OVL1_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 453 +#define CMDQ_EVENT_OVL1_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 454 +#define CMDQ_EVENT_OVL1_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 455 +#define CMDQ_EVENT_OVL1_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 456 +#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 457 +#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 458 +#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 459 +#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 460 +#define CMDQ_EVENT_OVL1_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 461 +#define CMDQ_EVENT_DPC_DT_DONE0 462 +#define CMDQ_EVENT_DPC_DT_DONE1 463 +#define CMDQ_EVENT_DPC_DT_DONE2_0_MERGE 464 +#define CMDQ_EVENT_DPC_DT_DONE2_1_MERGE 465 +#define CMDQ_EVENT_DPC_DT_DONE2_2_MERGE 466 +#define CMDQ_EVENT_DPC_DT_DONE2_3_MERGE 467 +#define CMDQ_EVENT_DPC_DT_DONE3 468 +#define CMDQ_EVENT_DPC_DT_DONE4_MERGE 469 +#define CMDQ_EVENT_DPC_DT_DONE5 470 +#define CMDQ_EVENT_DPC_DT_DONE6_0_MERGE 471 +#define CMDQ_EVENT_DPC_DT_DONE6_1_MERGE 472 +#define CMDQ_EVENT_DPC_DT_DONE6_2_MERGE 473 +#define CMDQ_EVENT_DPC_DT_DONE6_3_MERGE 474 +#define CMDQ_EVENT_DPC_DT_DONE7 475 +#define CMDQ_EVENT_DPC_DT_DONE32_MERGE 476 +#define CMDQ_EVENT_DPC_DT_DONE33 477 +#define CMDQ_EVENT_DPC_DT_DONE34_0 478 +#define CMDQ_EVENT_DPC_DT_DONE35 479 +#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_ON_BEFORE_OFF 480 +#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_PRETE_BEFORE_ON 481 +#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_ON_BEFORE_OFF 482 +#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_PRETE_BEFORE_ON 483 +#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_ON_BEFORE_OFF 484 +#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_PRETE_BEFORE_ON 485 +#define CMDQ_EVENT_DPC_DISP_SW_CONFIG_WHEN_MTCMOS_OFF 486 +#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_ON_BEFORE_OFF 487 +#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_PRETE_BEFORE_ON 488 +#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_ON_BEFORE_OFF 489 +#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_PRETE_BEFORE_ON 490 +#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_ON_BEFORE_OFF 491 +#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_PRETE_BEFORE_ON 492 +#define CMDQ_EVENT_DPC_MML_SW_CONFIG_WHEN_MTCMOS_OFF 493 +/* CMDQ_EVENT_DPTX_DPTX_EVENT0 ~ 3: 494 ~ 497 */ +#define CMDQ_EVENT_DPTX_DPTX_EVENT(n) (494 + (n)) +/* CMDQ_EVENT_EDPTX_EDPTX_EVENT0 ~ 1: 498 ~ 499 */ +#define CMDQ_EVENT_EDPTX_EDPTX_EVENT(n) (498 + (n)) + +#define CMDQ_EVENT_DSI0_TE_I_DSI0_TE_I 898 +#define CMDQ_EVENT_DSI1_TE_I_DSI1_TE_I 899 +#define CMDQ_EVENT_DSI2_TE_I_DSI2_TE_I 900 +/* CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK0 ~ 23: 901 ~ 924 */ +#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK(n) (901 + (n)) +/* CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX0 ~ 1: 925 ~ 926 */ +#define CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX(n) (925 + (n)) +/* CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P10 ~ 1: 927 ~ 928 */ +#define CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P1(n) (927 + (n)) +/* CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX0 ~ 1: 929 ~ 930 */ +#define CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX(n) (929 + (n)) +#define CMDQ_EVENT_DSI3_TE_I_DSI3_TE_I 931 +#define CMDQ_EVENT_SPI0_FINISH_EVENT_DSI4_TE_I 932 +#define CMDQ_EVENT_SPI0_EVENT_EVENT_DSI5_TE_I 933 + +/* + * GCE1 Hardware Event IDs + * Different SoCs will have varying numbers of hardware event signals, + * which are sent from the corresponding hardware to the GCE. + * Each hardware event signal corresponds to an event ID in the GCE. + * The CMDQ driver can use the following event ID definitions to allow + * the client driver to use wait and clear APIs provided by CMDQ, enabling + * the GCE to execute operations in the instructions for that event ID. + * + * The event IDs of GCE1 are mainly used by non-display hardware. + */ +#define CMDQ_EVENT_VENC3_VENC_RESERVED 0 +#define CMDQ_EVENT_VENC3_VENC_FRAME_DONE 1 +#define CMDQ_EVENT_VENC3_VENC_PAUSE_DONE 2 +#define CMDQ_EVENT_VENC3_JPGENC_DONE 3 +#define CMDQ_EVENT_VENC3_VENC_MB_DONE 4 +#define CMDQ_EVENT_VENC3_VENC_128BYTE_DONE 5 +#define CMDQ_EVENT_VENC3_JPGDEC_DONE 6 +#define CMDQ_EVENT_VENC3_JPGDEC_C1_DONE 7 +#define CMDQ_EVENT_VENC3_JPGDEC_INSUFF_DONE 8 +#define CMDQ_EVENT_VENC3_JPGDEC_C1_INSUFF_DONE 9 +#define CMDQ_EVENT_VENC3_WP_2ND_STAGE_DONE 10 +#define CMDQ_EVENT_VENC3_WP_3RD_STAGE_DONE 11 +#define CMDQ_EVENT_VENC3_PPS_HEADER_DONE 12 +#define CMDQ_EVENT_VENC3_SPS_HEADER_DONE 13 +#define CMDQ_EVENT_VENC3_VPS_HEADER_DONE 14 +#define CMDQ_EVENT_VENC3_VENC_SLICE_DONE 15 +#define CMDQ_EVENT_VENC3_VENC_SOC_SLICE_DONE 16 +#define CMDQ_EVENT_VENC3_VENC_SOC_FRAME_DONE 17 + +#define CMDQ_EVENT_VENC2_VENC_FRAME_DONE 33 +#define CMDQ_EVENT_VENC2_VENC_PAUSE_DONE 34 +#define CMDQ_EVENT_VENC2_JPGENC_DONE 35 +#define CMDQ_EVENT_VENC2_VENC_MB_DONE 36 +#define CMDQ_EVENT_VENC2_VENC_128BYTE_DONE 37 +#define CMDQ_EVENT_VENC2_JPGDEC_DONE 38 +#define CMDQ_EVENT_VENC2_JPGDEC_C1_DONE 39 +#define CMDQ_EVENT_VENC2_JPGDEC_INSUFF_DONE 40 +#define CMDQ_EVENT_VENC2_JPGDEC_C1_INSUFF_DONE 41 +#define CMDQ_EVENT_VENC2_WP_2ND_STAGE_DONE 42 +#define CMDQ_EVENT_VENC2_WP_3RD_STAGE_DONE 43 +#define CMDQ_EVENT_VENC2_PPS_HEADER_DONE 44 +#define CMDQ_EVENT_VENC2_SPS_HEADER_DONE 45 +#define CMDQ_EVENT_VENC2_VPS_HEADER_DONE 46 +#define CMDQ_EVENT_VENC2_VENC_SLICE_DONE 47 +#define CMDQ_EVENT_VENC2_VENC_SOC_SLICE_DONE 48 +#define CMDQ_EVENT_VENC2_VENC_SOC_FRAME_DONE 49 + +#define CMDQ_EVENT_VENC1_VENC_FRAME_DONE 65 +#define CMDQ_EVENT_VENC1_VENC_PAUSE_DONE 66 +#define CMDQ_EVENT_VENC1_JPGENC_DONE 67 +#define CMDQ_EVENT_VENC1_VENC_MB_DONE 68 +#define CMDQ_EVENT_VENC1_VENC_128BYTE_DONE 69 +#define CMDQ_EVENT_VENC1_JPGDEC_DONE 70 +#define CMDQ_EVENT_VENC1_JPGDEC_C1_DONE 71 +#define CMDQ_EVENT_VENC1_JPGDEC_INSUFF_DONE 72 +#define CMDQ_EVENT_VENC1_JPGDEC_C1_INSUFF_DONE 73 +#define CMDQ_EVENT_VENC1_WP_2ND_STAGE_DONE 74 +#define CMDQ_EVENT_VENC1_WP_3RD_STAGE_DONE 75 +#define CMDQ_EVENT_VENC1_PPS_HEADER_DONE 76 +#define CMDQ_EVENT_VENC1_SPS_HEADER_DONE 77 +#define CMDQ_EVENT_VENC1_VPS_HEADER_DONE 78 +#define CMDQ_EVENT_VENC1_VENC_SLICE_DONE 79 +#define CMDQ_EVENT_VENC1_VENC_SOC_SLICE_DONE 80 +#define CMDQ_EVENT_VENC1_VENC_SOC_FRAME_DONE 81 + +#define CMDQ_EVENT_VDEC1_VDEC_LINE_CNT_INT 192 +#define CMDQ_EVENT_VDEC1_VDEC_INT 193 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_2 194 +#define CMDQ_EVENT_VDEC1_VDEC_DEC_ERR 195 +#define CMDQ_EVENT_VDEC1_VDEC_BUSY_OVERFLOW 196 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_5 197 +#define CMDQ_EVENT_VDEC1_VDEC_INI_FETCH_RDY 198 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_7 199 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_8 200 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_9 201 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_10 202 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_11 203 + +#define CMDQ_EVENT_VDEC1_VDEC_GCE_CNT_OP_THR 207 + +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_32 224 +#define CMDQ_EVENT_VDEC1_VDEC_LAT_INT 225 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_34 226 +#define CMDQ_EVENT_VDEC1_VDEC_LAT_DEC_ERR 227 +#define CMDQ_EVENT_VDEC1_VDEC_LAT_BUSY_OVERFLOW 228 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_37 229 +#define CMDQ_EVENT_VDEC1_VDEC_LAT_INI_FETCH_RDY 230 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_39 231 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_40 232 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_41 233 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_42 234 +#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_43 235 + +#define CMDQ_EVENT_VDEC1_VDEC_LAT_GCE_CNT_OP_THR 239 + +#define CMDQ_EVENT_IMG_IMG_EVENT_0 256 +/* CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 ~ 5: 257 ~ 262 */ +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0(n) (257 + (n)) +#define CMDQ_EVENT_IMG_TRAW0_DMA_ERR_EVENT 263 +#define CMDQ_EVENT_IMG_TRAW0_DUMMY_0 264 +/* CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 ~ 5: 265 ~ 270 */ +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0(n) (265 + (n)) +#define CMDQ_EVENT_IMG_TRAW1_DMA_ERR_EVENT 271 +#define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT 272 +#define CMDQ_EVENT_IMG_ADLWR0_TILE_DONE_EVENT 273 +#define CMDQ_EVENT_IMG_ADLWR1_TILE_DONE_EVENT 274 +#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 275 +#define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE 276 +/* CMDQ_EVENT_IMG_QOF_ACK_EVENT0 ~ 19: 277 ~ 296 */ +#define CMDQ_EVENT_IMG_QOF_ACK_EVENT(n) (277 + (n)) +/* CMDQ_EVENT_IMG_QOF_ON_EVENT0 ~ 4: 297 ~ 301 */ +#define CMDQ_EVENT_IMG_QOF_ON_EVENT(n) (297 + (n)) +/* CMDQ_EVENT_IMG_QOF_OFF_EVENT0 ~ 4: 302 ~ 306 */ +#define CMDQ_EVENT_IMG_QOF_OFF_EVENT(n) (302 + (n)) +/* CMDQ_EVENT_IMG_QOF_SAVE_EVENT0 ~ 4: 307 ~ 311 */ +#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT(n) (307 + (n)) +/* CMDQ_EVENT_IMG_QOF_RESTORE_EVENT0 ~ 4: 312 ~ 316 */ +#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT(n) (312 + (n)) +/* CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P20~5: 317 ~ 322 */ +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2(n) (317 + (n)) +#define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT 323 +#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT 324 +#define CMDQ_EVENT_IMG_DIP_DUMMY_0 325 +#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 326 +#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 327 +/* CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P20 ~ 5: 328 ~ 333 */ +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2(n) (328 + (n)) +/* CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P20 ~ 5: 334 ~ 339 */ +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2(n) (334 + (n)) +#define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT 340 +/* CMDQ_EVENT_IMG_WPE0_DUMMY0~2: 341 ~ 343 */ +#define CMDQ_EVENT_IMG_WPE0_DUMMY(n) (341 + (n)) +#define CMDQ_EVENT_IMG_OMC_TNR_GCE_FRAME_DONE 344 +#define CMDQ_EVENT_IMG_OMC_TNR_DONE_SYNC_OUT 345 +/* CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P20 ~ 5: 346 ~ 351 */ +#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2(n) (346 + (n)) +/* CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P20 ~ 5: 352 ~ 357 */ +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2(n) (352 + (n)) +#define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT 358 +/* CMDQ_EVENT_IMG_WPE1_DUMMY0 ~ 2: 359 ~ 361 */ +#define CMDQ_EVENT_IMG_WPE1_DUMMY(n) (359 + (n)) +#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 362 +#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 363 +/* CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P20 ~ 5: 364 ~ 369 */ +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2(n) (364 + (n)) +#define CMDQ_EVENT_IMG_OMC_LITE_GCE_FRAME_DONE 370 +#define CMDQ_EVENT_IMG_OMC_LITE_DONE_SYNC_OUT 371 +/* CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P20 ~ 5: 372 ~ 377 */ +#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2(n) (372 + (n)) +/* CMDQ_EVENT_IMG_WPE2_DUMMY0 ~ 2: 378 ~ 380 */ +#define CMDQ_EVENT_IMG_WPE2_DUMMY(n) (378 + (n)) +#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE 381 +#define CMDQ_EVENT_IMG_IMG_EVENT_126 382 +#define CMDQ_EVENT_IMG_IMG_EVENT_127 383 +#define CMDQ_EVENT_CAM_CAM_EVENT_0 384 +#define CMDQ_EVENT_CAM_CAM_SUBA_SW_PASS1_DONE 385 +#define CMDQ_EVENT_CAM_CAM_SUBB_SW_PASS1_DONE 386 +#define CMDQ_EVENT_CAM_CAM_SUBC_SW_PASS1_DONE 387 +#define CMDQ_EVENT_CAM_CAM_SUBA_TFMR_PASS1_DONE 388 +#define CMDQ_EVENT_CAM_CAM_SUBB_TFMR_PASS1_DONE 389 +#define CMDQ_EVENT_CAM_CAM_SUBC_TFMR_PASS1_DONE 390 +/* CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE0 ~ 3: 391 ~ 394 */ +#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE(n) (391 + (n)) +/* CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE0 ~ 3: 395 ~ 398 */ +#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE(n) (395 + (n)) +/* CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE0 ~ 3: 399 + 402 */ +#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE(n) (399 + (n)) +/* CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE0 ~ 3: 403 ~ 406 */ +#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE(n) (403 + (n)) +/* CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE0 ~ 3: 407 ~ 409 */ +#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE(n) (407 + (n)) +/* CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE0 ~ 3: 411 ~ 413 */ +#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE(n) (411 + (n)) +#define CMDQ_EVENT_CAM_MRAW0_SW_PASS1_DONE 415 +#define CMDQ_EVENT_CAM_MRAW1_SW_PASS1_DONE 416 +#define CMDQ_EVENT_CAM_MRAW2_SW_PASS1_DONE 417 +#define CMDQ_EVENT_CAM_MRAW3_SW_PASS1_DONE 418 +#define CMDQ_EVENT_CAM_UISP_SW_PASS1_DONE 419 +#define CMDQ_EVENT_CAM_TG_MRAW0_OUT_SOF 420 +#define CMDQ_EVENT_CAM_TG_MRAW1_OUT_SOF 421 +#define CMDQ_EVENT_CAM_TG_MRAW2_OUT_SOF 422 +#define CMDQ_EVENT_CAM_TG_MRAW3_OUT_SOF 423 +#define CMDQ_EVENT_CAM_PDA0_IRQO_EVENT_DONE_D1 424 +#define CMDQ_EVENT_CAM_PDA1_IRQO_EVENT_DONE_D1 425 +#define CMDQ_EVENT_CAM_DPE_DVP_CMQ_EVENT 426 +#define CMDQ_EVENT_CAM_DPE_DVS_CMQ_EVENT 427 +#define CMDQ_EVENT_CAM_DPE_DVFG_CMQ_EVENT 428 +#define CMDQ_EVENT_CAM_CAM_EVENT_45 429 +#define CMDQ_EVENT_CAM_CAM_EVENT_46 430 +#define CMDQ_EVENT_CAM_CAM_EVENT_47 431 +#define CMDQ_EVENT_CAM_CAM_EVENT_48 432 +/* CMDQ_EVENT_CAM_CAM_SUBA_TG_INT1 ~ 4: 433 ~ 436 */ +#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT(n) (433 + (n) - 1) +/* CMDQ_EVENT_CAM_CAM_SUBB_TG_INT1 ~ 4: 437 ~ 440 */ +#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT(n) (437 + (n) - 1) +/* CMDQ_EVENT_CAM_CAM_SUBC_TG_INT1 ~ 4: 441 ~ 444 */ +#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT(n) (441 + (n) - 1) +#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBA 445 +#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBB 446 +#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBC 447 +#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBA 448 +#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBB 449 +#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBC 450 +#define CMDQ_EVENT_CAM_RAW_SEL_SOF_UISP 451 +#define CMDQ_EVENT_CAM_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 452 +#define CMDQ_EVENT_CAM_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 453 +#define CMDQ_EVENT_CAM_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 454 +#define CMDQ_EVENT_CAM_CAM_EVENT_71 455 +#define CMDQ_EVENT_CAM_ADL_WR_FRAME_DONE 456 +#define CMDQ_EVENT_CAM_ADL_RD_FRAME_DONE 457 +#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_ON_EVENT 458 +#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_ON_EVENT 459 +#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_ON_EVENT 460 +#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_OFF_EVENT 461 +#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_OFF_EVENT 462 +#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_OFF_EVENT 463 +#define CMDQ_EVENT_CAM_QOF_RAWA_SAVE_EVENT 464 +#define CMDQ_EVENT_CAM_QOF_RAWB_SAVE_EVENT 465 +#define CMDQ_EVENT_CAM_QOF_RAWC_SAVE_EVENT 466 +#define CMDQ_EVENT_CAM_QOF_RAWA_RESTORE_EVENT 467 +#define CMDQ_EVENT_CAM_QOF_RAWB_RESTORE_EVENT 468 +#define CMDQ_EVENT_CAM_QOF_RAWC_RESTORE_EVENT 469 +/* CMDQ_EVENT_CAM_QOF_CAM_EVENT0 ~ 11: 470 ~ 481 */ +#define CMDQ_EVENT_CAM_QOF_CAM_EVENT(n) (470 + (n)) +/* CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT0 ~ 11: 482 ~ 495 */ +#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT(n) (482 + (n)) +#define CMDQ_EVENT_CAM_CCU0_TO_GCE_NON_SEC_IRQ 496 +#define CMDQ_EVENT_CAM_CCU0_TO_GCE_SEC_IRQ 497 +#define CMDQ_EVENT_CAM_CCU0_TO_GCE_VM_IRQ 498 +#define CMDQ_EVENT_CAM_CCU0_TO_GCE_EXCH_VM_IRQ 499 +#define CMDQ_EVENT_CAM_CCU1_TO_GCE_NON_SEC_IRQ 500 +#define CMDQ_EVENT_CAM_CCU1_TO_GCE_SEC_IRQ 501 +#define CMDQ_EVENT_CAM_CCU1_TO_GCE_VM_IRQ 502 +#define CMDQ_EVENT_CAM_CCU1_TO_GCE_EXCH_VM_IRQ 503 +/* CMDQ_EVENT_CAM_I2C_CH2_EVENT0 ~ 4: 504 ~ 509 */ +#define CMDQ_EVENT_CAM_I2C_CH2_EVENT(n) (504 + (n)) +#define CMDQ_EVENT_CAM_CAM_EVENT_125 509 +#define CMDQ_EVENT_CAM_CAM_EVENT_126 510 +#define CMDQ_EVENT_CAM_CAM_EVENT_127 511 + +#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MMSRAM_COMM_SMIASSER 898 +#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MDP_COMM_SMIASSER 899 +#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_DISP_COMM_SMIASSER 900 + +/* + * GCE Software Tokens + * Apart from the event IDs that are already bound to hardware event signals, + * the remaining event IDs can be used as software tokens. + * This allows the client driver to name and operate them independently, + * and their usage is the same as that of hardware events. + */ +/* Begin of GCE0 software token */ +/* Config thread notify trigger thread */ +#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 +/* Trigger thread notify config thread */ +#define CMDQ_SYNC_TOKEN_STREAM_EOF 641 +/* Block Trigger thread until the ESD check finishes */ +#define CMDQ_SYNC_TOKEN_ESD_EOF 642 +#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 +/* Check CABC setup finish */ +#define CMDQ_SYNC_TOKEN_CABC_EOF 644 +/* VFP period token for Msync */ +#define CMDQ_SYNC_TOKEN_VFP_PERIOD 645 +/* Software sync token for dual display */ +#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1 694 +#define CMDQ_SYNC_TOKEN_STREAM_EOF_1 695 +#define CMDQ_SYNC_TOKEN_ESD_EOF_1 696 +#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1 697 +#define CMDQ_SYNC_TOKEN_CABC_EOF_1 698 + +/* + * GPR access tokens (for HW register backup) + * There are 15 32-bit GPR, form 3 GPR as a set + * (64-bit for address, 32-bit for value) + * + * CMDQ_SYNC_TOKEN_GPR_SET0 ~ 4: 700 ~ 704 + */ +#define CMDQ_SYNC_TOKEN_GPR_SET(n) (700 + (n)) +#define CMDQ_SYNC_TOKEN_TE_0 705 +#define CMDQ_SYNC_TOKEN_PREFETCH_TE_0 706 +#define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON 707 +#define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE 708 + +/* Resource lock event to control resource in GCE thread */ +#define CMDQ_SYNC_RESOURCE_WROT0 710 +#define CMDQ_SYNC_RESOURCE_WROT1 711 +/* Hardware TRACE software token */ +#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT 712 +#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK 713 +/* Software sync token for dual display */ +#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3 714 +#define CMDQ_SYNC_TOKEN_STREAM_EOF_3 715 +#define CMDQ_SYNC_TOKEN_ESD_EOF_3 716 +#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3 717 +#define CMDQ_SYNC_TOKEN_CABC_EOF_3 718 +/* End of GCE0 software token */ + +/* Begin of GCE1 software token */ +/* CMDQ_SYNC_TOKEN_IMGSYS_POOL0 ~ 300: 512 ~ 812 */ +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL(n) (512 + (n)) +/* ISP software token */ +#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 813 +#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_TNR 814 +#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 815 +#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 816 +#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 817 +#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 818 +#define CMDQ_SYNC_TOKEN_IMGSYS_DIP 819 +#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 820 +#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 821 +#define CMDQ_SYNC_TOKEN_IPESYS_ME 822 +#define CMDQ_SYNC_TOKEN_APUSYS_APU 823 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 824 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 825 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 826 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 827 +#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_LITE 828 +/* IMG software token for QoS */ +#define CMDQ_SYNC_TOKEN_IMGSYS_QOS_LOCK 829 +/* IMG software token for Qof */ +#define CMDQ_SYNC_TOKEN_DIP_POWER_CTRL 830 +#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_ON 831 +#define CMDQ_SYNC_TOKEN_DIP_PWR_ON 832 +#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_OFF 833 +#define CMDQ_SYNC_TOKEN_DIP_PWR_OFF 834 +#define CMDQ_SYNC_TOKEN_DIP_PWR_HAND_SHAKE 835 +#define CMDQ_SYNC_TOKEN_TRAW_POWER_CTRL 836 +#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_ON 837 +#define CMDQ_SYNC_TOKEN_TRAW_PWR_ON 838 +#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_OFF 839 +#define CMDQ_SYNC_TOKEN_TRAW_PWR_OFF 840 +#define CMDQ_SYNC_TOKEN_TRAW_PWR_HAND_SHAKE 841 +/* End of GCE1 software token */ + +/* Begin of common software token */ +/* + * Notify normal CMDQ there are some secure task done + * MUST NOT CHANGE, this token sync with secure world + */ +#define CMDQ_SYNC_SECURE_THR_EOF 940 +/* CMDQ use software token */ +#define CMDQ_SYNC_TOKEN_USER_0 941 +#define CMDQ_SYNC_TOKEN_USER_1 942 +#define CMDQ_SYNC_TOKEN_POLL_MONITOR 943 +#define CMDQ_SYNC_TOKEN_TPR_LOCK 942 +/* TZMP software token */ +#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 943 +#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 944 +#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 945 +#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 946 +#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 947 +#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 948 +#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT 949 +#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET 950 +/* PREBUILT software token */ +#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 951 +#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 952 +#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 953 +#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 954 +#define CMDQ_SYNC_TOKEN_DISP_VA_START 955 +#define CMDQ_SYNC_TOKEN_DISP_VA_END 956 + +/* + * Event for GPR timer, used in sleep and poll with timeout + * + * CMDQ_TOKEN_GPR_TIMER_R0~15: 994 ~ 1009 + */ +#define CMDQ_TOKEN_GPR_TIMER_R(n) (994 + (n)) +/* End of common software token */ + +#endif diff --git a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts index c8418888268..b5dd5ef9fa1 100644 --- a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts +++ b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts @@ -284,6 +284,11 @@ }; }; +&gpu { + mali-supply = <&mt6357_vcore_reg>; + status = "okay"; +}; + &i2c0 { clock-frequency = <100000>; pinctrl-0 = <&i2c0_pins>; @@ -353,6 +358,10 @@ }; }; +&mfg { + domain-supply = <&mt6357_vsram_others_reg>; +}; + &mmc0 { assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; diff --git a/dts/upstream/src/arm64/mediatek/mt8365.dtsi b/dts/upstream/src/arm64/mediatek/mt8365.dtsi index e6d2b3221a3..a5ca3cda6ef 100644 --- a/dts/upstream/src/arm64/mediatek/mt8365.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt8365.dtsi @@ -267,6 +267,26 @@ clock-output-names = "clk26m"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <650000>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-microvolt = <700000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <800000>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -292,6 +312,27 @@ interrupts = ; }; + mfgcfg: syscon@13000000 { + compatible = "mediatek,mt8365-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + gpu: gpu@13040000 { + compatible = "mediatek,mt8365-mali", "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + + clocks = <&mfgcfg CLK_MFG_BG3D>; + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&spm MT8365_POWER_DOMAIN_MFG>; + status = "disabled"; + }; + topckgen: syscon@10000000 { compatible = "mediatek,mt8365-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; @@ -398,7 +439,7 @@ mediatek,infracfg = <&infracfg>; }; - power-domain@MT8365_POWER_DOMAIN_MFG { + mfg: power-domain@MT8365_POWER_DOMAIN_MFG { reg = ; clocks = <&topckgen CLK_TOP_MFG_SEL>; clock-names = "mfg"; diff --git a/dts/upstream/src/arm64/mediatek/mt8370-grinn-genio-510-sbc.dts b/dts/upstream/src/arm64/mediatek/mt8370-grinn-genio-510-sbc.dts new file mode 100644 index 00000000000..92ff80e6097 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt8370-grinn-genio-510-sbc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Bartosz Bilas + */ +/dts-v1/; + +#include "mt8370.dtsi" +#include "mt8390-grinn-genio-som.dtsi" +#include "mt8390-grinn-genio-sbc.dtsi" + +/ { + model = "Grinn GenioSBC-510"; + compatible = "grinn,genio-510-sbc", "mediatek,mt8370", "mediatek,mt8188"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 1 0x00000000>; + }; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-700-sbc.dts b/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-700-sbc.dts new file mode 100644 index 00000000000..4931d761bd1 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-700-sbc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ +/dts-v1/; + +#include "mt8188.dtsi" +#include "mt8390-grinn-genio-som.dtsi" +#include "mt8390-grinn-genio-sbc.dtsi" + +/ { + model = "Grinn GenioSBC-700"; + compatible = "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 1 0x00000000>; + }; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-sbc.dtsi b/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-sbc.dtsi new file mode 100644 index 00000000000..888248a75e9 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-sbc.dtsi @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +#include + +/ { + chassis-type = "embedded"; + + aliases { + ethernet0 = ð + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + reg_sbc_vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + reg_fixed_5v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + vin-supply = <®_sbc_vsys>; + }; + + reg_fixed_4v2: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-4v2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + enable-active-high; + regulator-always-on; + vin-supply = <®_sbc_vsys>; + }; + + reg_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + vin-supply = <®_sbc_vsys>; + }; +}; + +&pio { + gpio-line-names = + /* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4", + /* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9", + /* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "", + /* 15 - 19 */ "", "", "", "", "", + /* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "", + /* 25 - 29 */ "", "", "", "", "", + /* 30 - 34 */ "RPI_GPIO30", "", "", "", "", + /* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "", + /* 40 - 44 */ "", "", "", "", "", + /* 45 - 49 */ "", "", "", "", "", + /* 50 - 54 */ "", "", "", "", "", + /* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59", + /* 60 - 64 */ "RPI_GPIO60", "", "", "", "", + /* 65 - 69 */ "", "", "", "", "RPI_GPIO69", + /* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74", + /* 75 - 79 */ "", "", "", "", "RPI_GPIO79", + /* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "", + /* 85 - 89 */ "", "", "", "", "", + /* 90 - 94 */ "", "", "", "", "", + /* 95 - 99 */ "", "", "", "", "", + /*100 - 104 */ "", "", "", "", "", + /*105 - 109 */ "", "", "", "", "", + /*110 - 114 */ "", "", "", "", "", + /*115 - 119 */ "", "", "", "", "", + /*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124"; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + pcie_pins_default: pcie-default { + mux { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = , + ; + drive-strength = <8>; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-rxd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = , + , + , + ; + }; + }; + + usb_default_pins: usb-default-pins { + pins-valid { + pinmux = ; + input-enable; + }; + }; +}; + +ð { + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; + mediatek,tx-delay-ps = <30>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 200000>; + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; + eee-broken-1000t; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci1 { + #address-cells = <1>; + #size-cells = <0>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8027"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <®_fixed_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8025"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <®_fixed_3v3>; + }; +}; + +&xhci2 { + #address-cells = <1>; + #size-cells = <0>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; + + hub@1 { + compatible = "microchip,usb2513bi"; + reg = <1>; + vdd-supply = <®_fixed_3v3>; + }; +}; + +&ssusb0 { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_default_pins>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&sound { + compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; + model = "mt8390-evk"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_default_pins>; + audio-routing = + "Headphone", "Headphone L", + "Headphone", "Headphone R", + "AP DMIC", "AUDGLB", + "AP DMIC", "MIC_BIAS_0", + "AP DMIC", "MIC_BIAS_2", + "DMIC_INPUT", "AP DMIC"; + + mediatek,adsp = <&adsp>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-som.dtsi b/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-som.dtsi new file mode 100644 index 00000000000..8da47c91631 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt8390-grinn-genio-som.dtsi @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +#include "mt6359.dtsi" +#include + +/ { + aliases { + i2c1 = &i2c1; + mmc0 = &mmc0; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x1481b>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name = "vcn18_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name = "vcn33_2_pmu"; + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name = "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name = "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name = "vpa_pmu"; + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name = "vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-name = "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name = "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name = "vsim1_pmu"; + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name = "vufs18_pmu"; + regulator-always-on; +}; + +&pio { + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = ; + wakeup-source; + }; + }; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk-ufs.dts b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk-ufs.dts new file mode 100644 index 00000000000..e09a3ecd877 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk-ufs.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Ramax Lo + * Macpaul Lin + */ +/dts-v1/; + +#include "mt8395-genio-common.dtsi" + +/ { + model = "MediaTek Genio 1200 EVK-P1V2-UFS"; + compatible = "mediatek,mt8395-evk-ufs", "mediatek,mt8395", + "mediatek,mt8195"; +}; + +&ufshci { + status = "okay"; + vcc-supply = <&mt6359_vemc_1_ldo_reg>; + vccq2-supply = <&mt6359_vufs_ldo_reg>; +}; + +&ufsphy { + status = "okay"; +}; + +&mmc0 { + status = "disabled"; +}; diff --git a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts index cf8cd37f570..68455f28c24 100644 --- a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts +++ b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts @@ -6,1197 +6,10 @@ */ /dts-v1/; -#include "mt8195.dtsi" -#include "mt6359.dtsi" -#include -#include -#include -#include -#include -#include -#include +#include "mt8395-genio-common.dtsi" / { model = "MediaTek Genio 1200 EVK-P1V2-EMMC"; compatible = "mediatek,mt8395-evk", "mediatek,mt8395", "mediatek,mt8195"; - - aliases { - serial0 = &uart0; - ethernet0 = ð - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0x2 0x00000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 12 MiB reserved for OP-TEE (BL32) - * +-----------------------+ 0x43e0_0000 - * | SHMEM 2MiB | - * +-----------------------+ 0x43c0_0000 - * | | TA_RAM 8MiB | - * + TZDRAM +--------------+ 0x4340_0000 - * | | TEE_RAM 2MiB | - * +-----------------------+ 0x4320_0000 - */ - optee_reserved: optee@43200000 { - no-map; - reg = <0 0x43200000 0 0x00c00000>; - }; - - scp_mem: memory@50000000 { - compatible = "shared-dma-pool"; - reg = <0 0x50000000 0 0x2900000>; - no-map; - }; - - vpu_mem: memory@53000000 { - compatible = "shared-dma-pool"; - reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ - }; - - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - bl31_secmon_mem: memory@54600000 { - no-map; - reg = <0 0x54600000 0x0 0x200000>; - }; - - adsp_mem: memory@60000000 { - compatible = "shared-dma-pool"; - reg = <0 0x60000000 0 0xf00000>; - no-map; - }; - - afe_dma_mem: memory@60f00000 { - compatible = "shared-dma-pool"; - reg = <0 0x60f00000 0 0x100000>; - no-map; - }; - - adsp_dma_mem: memory@61000000 { - compatible = "shared-dma-pool"; - reg = <0 0x61000000 0 0x100000>; - no-map; - }; - - apu_mem: memory@62000000 { - compatible = "shared-dma-pool"; - reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ - }; - }; - - backlight_lcm0: backlight-lcm0 { - compatible = "pwm-backlight"; - brightness-levels = <0 1023>; - default-brightness-level = <576>; - num-interpolated-steps = <1023>; - pwms = <&disp_pwm0 0 500000>; - }; - - backlight_lcd1: backlight-lcd1 { - compatible = "pwm-backlight"; - pwms = <&disp_pwm1 0 500000>; - enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; - brightness-levels = <0 1023>; - num-interpolated-steps = <1023>; - default-brightness-level = <576>; - status = "disabled"; - }; - - can_clk: can-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <20000000>; - clock-output-names = "can-clk"; - }; - - edp_panel_fixed_3v3: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "edp_panel_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_panel_3v3_en_pins>; - }; - - edp_panel_fixed_12v: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "edp_backlight_12v"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - gpio = <&pio 96 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_panel_12v_en_pins>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - button-volume-up { - wakeup-source; - debounce-interval = <100>; - gpios = <&pio 106 GPIO_ACTIVE_LOW>; - label = "volume_up"; - linux,code = ; - }; - }; - - lcm0_iovcc: regulator-vio18-lcm0 { - compatible = "regulator-fixed"; - regulator-name = "vio18_lcm0"; - enable-active-high; - gpio = <&pio 47 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&dsi0_vreg_en_pins>; - vin-supply = <&mt6360_ldo2>; - }; - - lcm0_vddp: regulator-vsys-lcm0 { - compatible = "regulator-fixed"; - regulator-name = "vsys_lcm0"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&mt6360_ldo1>; - }; - - wifi_fixed_3v3: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "wifi_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 135 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; -}; - -&adsp { - memory-region = <&adsp_dma_mem>, <&adsp_mem>; - status = "okay"; -}; - -&afe { - memory-region = <&afe_dma_mem>; - status = "okay"; -}; - -&disp_pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - status = "okay"; -}; - -&dither0_in { - remote-endpoint = <&gamma0_out>; -}; - -&dither0_out { - remote-endpoint = <&dsi0_in>; -}; - -&dmic_codec { - wakeup-delay-ms = <200>; -}; - -&dsi0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - panel@0 { - compatible = "startek,kd070fhfid078", "himax,hx8279"; - reg = <0>; - backlight = <&backlight_lcm0>; - enable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; - reset-gpios = <&pio 108 GPIO_ACTIVE_HIGH>; - iovcc-supply = <&lcm0_iovcc>; - vdd-supply = <&lcm0_vddp>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_default_pins>; - - port { - dsi_panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&dither0_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; -}; - -ð { - phy-mode ="rgmii-rxid"; - phy-handle = <ð_phy0>; - snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; - snps,reset-delays-us = <0 10000 10000>; - mediatek,tx-delay-ps = <2030>; - mediatek,mac-wol; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <ð_default_pins>; - pinctrl-1 = <ð_sleep_pins>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - eth_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - }; - }; -}; - -&gamma0_out { - remote-endpoint = <&dither0_in>; -}; - -&gpu { - mali-supply = <&mt6315_7_vbuck1>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt9271"; - reg = <0x5d>; - interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; - irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; - reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; - AVDD28-supply = <&mt6360_ldo1>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_pins>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - status = "okay"; - - typec-mux@48 { - compatible = "ite,it5205"; - reg = <0x48>; - vcc-supply = <&mt6359_vibr_ldo_reg>; - mode-switch; - orientation-switch; - status = "okay"; - - port { - it5205_sbu_ep: endpoint { - remote-endpoint = <&mt6360_ssusb_sbu_ep>; - }; - }; - }; -}; - -&i2c6 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c6_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - mt6360: pmic@34 { - compatible = "mediatek,mt6360"; - reg = <0x34>; - interrupt-parent = <&pio>; - interrupts = <128 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "IRQB"; - interrupt-controller; - #interrupt-cells = <1>; - pinctrl-0 = <&mt6360_pins>; - - charger { - compatible = "mediatek,mt6360-chg"; - richtek,vinovp-microvolt = <14500000>; - - otg_vbus_regulator: usb-otg-vbus-regulator { - regulator-name = "usb-otg-vbus"; - regulator-min-microvolt = <4425000>; - regulator-max-microvolt = <5825000>; - }; - }; - - regulator { - compatible = "mediatek,mt6360-regulator"; - LDO_VIN3-supply = <&mt6360_buck2>; - - mt6360_buck1: buck1 { - regulator-name = "emi_vdd2"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1300000>; - regulator-allowed-modes = ; - regulator-always-on; - }; - - mt6360_buck2: buck2 { - regulator-name = "emi_vddq"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1300000>; - regulator-allowed-modes = ; - regulator-always-on; - }; - - mt6360_ldo1: ldo1 { - regulator-name = "tp1_p3v0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-allowed-modes = ; - regulator-always-on; - }; - - mt6360_ldo2: ldo2 { - regulator-name = "panel1_p1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo3: ldo3 { - regulator-name = "vmc_pmu"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo5: ldo5 { - regulator-name = "vmch_pmu"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3600000>; - regulator-allowed-modes = ; - }; - - /* This is a measure point, which name is mt6360_ldo1 on schematic */ - mt6360_ldo6: ldo6 { - regulator-name = "mt6360_ldo1"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2100000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo7: ldo7 { - regulator-name = "emi_vmddr_en"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2100000>; - regulator-allowed-modes = ; - regulator-always-on; - }; - }; - - tcpc { - compatible = "mediatek,mt6360-tcpc"; - interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "PD_IRQB"; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - op-sink-microwatt = <10000000>; - power-role = "dual"; - try-power-role = "sink"; - - source-pdos = ; - sink-pdos = ; - - pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>; - - altmodes { - displayport { - svid = /bits/ 16 <0xff01>; - vdo = <0x00001c46>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - typec_con_hs: endpoint { - remote-endpoint = <&mtu3_hs0_role_sw>; - }; - }; - - port@1 { - reg = <1>; - typec_con_ss: endpoint { - remote-endpoint = <&mtu3_ss0_role_sw>; - }; - }; - - port@2 { - reg = <2>; - mt6360_ssusb_sbu_ep: endpoint { - remote-endpoint = <&it5205_sbu_ep>; - }; - }; - }; - }; - }; - }; -}; - -&mfg0 { - domain-supply = <&mt6315_7_vbuck1>; -}; - -&mfg1 { - domain-supply = <&mt6359_vsram_others_ldo_reg>; -}; - -&mipi_tx0 { - status = "okay"; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_default_pins>; - pinctrl-1 = <&mmc0_uhs_pins>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-hw-reset; - no-sdio; - no-sd; - hs400-ds-delay = <0x14c11>; - vmmc-supply = <&mt6359_vemc_1_ldo_reg>; - vqmmc-supply = <&mt6359_vufs_ldo_reg>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_default_pins>; - pinctrl-1 = <&mmc1_uhs_pins>; - bus-width = <4>; - max-frequency = <200000000>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - no-mmc; - no-sdio; - vmmc-supply = <&mt6360_ldo5>; - vqmmc-supply = <&mt6360_ldo3>; - status = "okay"; - non-removable; -}; - -&mt6359_vaud18_ldo_reg { - regulator-always-on; -}; - -&mt6359_vbbck_ldo_reg { - regulator-always-on; -}; - -/* For USB Hub */ -&mt6359_vcamio_ldo_reg { - regulator-always-on; -}; - -&mt6359_vcn33_2_bt_ldo_reg { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&mt6359_vcore_buck_reg { - regulator-always-on; -}; - -&mt6359_vgpu11_buck_reg { - regulator-always-on; -}; - -&mt6359_vpu_buck_reg { - regulator-always-on; -}; - -&mt6359_vrf12_ldo_reg { - regulator-always-on; -}; - -/* for GPU SRAM */ -&mt6359_vsram_others_ldo_reg { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; -}; - -&mt6359codec { - mediatek,mic-type-0 = <1>; /* ACC */ - mediatek,mic-type-1 = <3>; /* DCC */ - mediatek,mic-type-2 = <1>; /* ACC */ -}; - -&ovl0_in { - remote-endpoint = <&vdosys0_ep_main>; -}; - -&pcie0 { - pinctrl-names = "default", "idle"; - pinctrl-0 = <&pcie0_default_pins>; - pinctrl-1 = <&pcie0_idle_pins>; - status = "okay"; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_pins>; - status = "disabled"; -}; - -&pciephy { - status = "okay"; -}; - -&pio { - audio_default_pins: audio-default-pins { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - disp_pwm1_default_pins: disp-pwm1-default-pins { - pins1 { - pinmux = ; - }; - }; - - edp_panel_12v_en_pins: edp-panel-12v-en-pins { - pins1 { - pinmux = ; - output-high; - }; - }; - - edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { - pins1 { - pinmux = ; - output-high; - }; - }; - - eth_default_pins: eth-default-pins { - pins-cc { - pinmux = , - , - , - ; - drive-strength = <8>; - }; - - pins-mdio { - pinmux = , - ; - input-enable; - }; - - pins-power { - pinmux = , - ; - output-high; - }; - - pins-rxd { - pinmux = , - , - , - ; - }; - - pins-txd { - pinmux = , - , - , - ; - drive-strength = <8>; - }; - }; - - eth_sleep_pins: eth-sleep-pins { - pins-cc { - pinmux = , - , - , - ; - }; - - pins-mdio { - pinmux = , - ; - input-disable; - bias-disable; - }; - - pins-rxd { - pinmux = , - , - , - ; - }; - - pins-txd { - pinmux = , - , - , - ; - }; - }; - - gpio_key_pins: gpio-keys-pins { - pins { - pinmux = ; - bias-pull-up; - input-enable; - }; - }; - - i2c0_pins: i2c0-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c1_pins: i2c1-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c2_pins: i2c2-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength = <6>; - }; - }; - - i2c6_pins: i2c6-pins { - pins { - pinmux = , - ; - bias-pull-up; - }; - }; - - mmc0_default_pins: mmc0-default-pins { - pins-clk { - pinmux = ; - drive-strength = <6>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = <6>; - bias-pull-up = ; - }; - - pins-rst { - pinmux = ; - drive-strength = <6>; - bias-pull-up = ; - }; - }; - - mmc0_uhs_pins: mmc0-uhs-pins { - pins-clk { - pinmux = ; - drive-strength = <8>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = <8>; - bias-pull-up = ; - }; - - pins-ds { - pinmux = ; - drive-strength = <8>; - bias-pull-down = ; - }; - - pins-rst { - pinmux = ; - drive-strength = <8>; - bias-pull-up = ; - }; - }; - - mmc1_default_pins: mmc1-default-pins { - pins-clk { - pinmux = ; - drive-strength = <8>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = <8>; - bias-pull-up = ; - }; - }; - - mmc1_uhs_pins: mmc1-uhs-pins { - pins-clk { - pinmux = ; - drive-strength = <8>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = <8>; - bias-pull-up = ; - }; - }; - - mt6360_pins: mt6360-pins { - pins { - pinmux = , - ; - input-enable; - bias-pull-up; - }; - }; - - dsi0_vreg_en_pins: dsi0-vreg-en-pins { - pins-pwr-en { - pinmux = ; - output-low; - }; - }; - - panel_default_pins: panel-default-pins { - pins-rst { - pinmux = ; - output-high; - }; - - pins-en { - pinmux = ; - output-low; - }; - }; - - pcie0_default_pins: pcie0-default-pins { - pins { - pinmux = , - , - ; - bias-pull-up; - }; - }; - - pcie0_idle_pins: pcie0-idle-pins { - pins { - pinmux = ; - bias-disable; - output-low; - }; - }; - - pcie1_default_pins: pcie1-default-pins { - pins { - pinmux = , - , - ; - bias-pull-up; - }; - }; - - disp_pwm0_pins: disp-pwm0-pins { - pins-disp-pwm { - pinmux = ; - }; - }; - - spi1_pins: spi1-pins { - pins { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi2_pins: spi-pins { - pins { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - touch_pins: touch-pins { - pins-irq { - pinmux = ; - input-enable; - bias-disable; - }; - - pins-reset { - pinmux = ; - output-high; - }; - }; - - u3_p0_vbus: u3-p0-vbus-default-pins { - pins-vbus { - pinmux = ; - input-enable; - }; - }; - - uart0_pins: uart0-pins { - pins { - pinmux = , - ; - }; - }; - - uart1_pins: uart1-pins { - pins { - pinmux = , - , - , - ; - }; - }; -}; - -&pmic { - interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; - - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; - mediatek,long-press-mode = <1>; - power-off-time-sec = <0>; - - power-key { - linux,keycodes = ; - wakeup-source; - }; - - home { - linux,keycodes = ; - }; - }; -}; - -&scp { - memory-region = <&scp_mem>; - firmware-name = "mediatek/mt8195/scp.img"; - status = "okay"; -}; - -&sound { - compatible = "mediatek,mt8195_mt6359"; - model = "mt8395-evk"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_default_pins>; - audio-routing = - "Headphone", "Headphone L", - "Headphone", "Headphone R"; - mediatek,adsp = <&adsp>; - status = "okay"; - - headphone-dai-link { - link-name = "DL_SRC_BE"; - - codec { - sound-dai = <&pmic 0>; - }; - }; -}; - -&spi1 { - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - mediatek,pad-select = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>; - - can0: can@0 { - compatible = "microchip,mcp2518fd"; - reg = <0>; - clocks = <&can_clk>; - spi-max-frequency = <20000000>; - interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; - xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; - }; -}; - -&spi2 { - pinctrl-0 = <&spi2_pins>; - pinctrl-names = "default"; - mediatek,pad-select = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; -}; - -&spmi { - #address-cells = <2>; - #size-cells = <0>; - - mt6315_6: pmic@6 { - compatible = "mediatek,mt6315-regulator"; - reg = <0x6 SPMI_USID>; - - regulators { - mt6315_6_vbuck1: vbuck1 { - regulator-name = "Vbcpu"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1193750>; - regulator-enable-ramp-delay = <256>; - regulator-allowed-modes = <0 1 2>; - regulator-always-on; - }; - }; - }; - - mt6315_7: pmic@7 { - compatible = "mediatek,mt6315-regulator"; - reg = <0x7 SPMI_USID>; - - regulators { - mt6315_7_vbuck1: vbuck1 { - regulator-name = "Vgpu"; - regulator-min-microvolt = <546000>; - regulator-max-microvolt = <787000>; - regulator-enable-ramp-delay = <256>; - regulator-allowed-modes = <0 1 2>; - }; - }; - }; -}; - -&u3phy0 { - status = "okay"; -}; - -&u3phy1 { - status = "okay"; - - u3port1: usb-phy@700 { - mediatek,force-mode; - }; -}; - -&u3phy2 { - status = "okay"; -}; - -&u3phy3 { - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&ufsphy { - status = "disabled"; -}; - -&ssusb0 { - dr_mode = "otg"; - pinctrl-names = "default"; - pinctrl-0 = <&u3_p0_vbus>; - usb-role-switch; - vusb33-supply = <&mt6359_vusb_ldo_reg>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mtu3_hs0_role_sw: endpoint { - remote-endpoint = <&typec_con_hs>; - }; - }; - - port@1 { - reg = <1>; - mtu3_ss0_role_sw: endpoint { - remote-endpoint = <&typec_con_ss>; - }; - }; - }; -}; - -&ssusb2 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; - status = "okay"; -}; - -&ssusb3 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; - status = "okay"; -}; - -&vdosys0 { - port { - #address-cells = <1>; - #size-cells = <0>; - - vdosys0_ep_main: endpoint@0 { - reg = <0>; - remote-endpoint = <&ovl0_in>; - }; - }; -}; - -&xhci0 { - status = "okay"; -}; - -&xhci1 { - vusb33-supply = <&mt6359_vusb_ldo_reg>; - status = "okay"; -}; - -&xhci2 { - status = "okay"; -}; - -&xhci3 { - status = "okay"; }; diff --git a/dts/upstream/src/arm64/mediatek/mt8395-genio-common.dtsi b/dts/upstream/src/arm64/mediatek/mt8395-genio-common.dtsi new file mode 100644 index 00000000000..2b7167804e7 --- /dev/null +++ b/dts/upstream/src/arm64/mediatek/mt8395-genio-common.dtsi @@ -0,0 +1,1230 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Ben Lok + * Macpaul Lin + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include +#include + +/ { + aliases { + serial0 = &uart0; + ethernet0 = ð + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; + + backlight_lcm0: backlight-lcm0 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <576>; + num-interpolated-steps = <1023>; + pwms = <&disp_pwm0 0 500000>; + }; + + backlight_lcd1: backlight-lcd1 { + compatible = "pwm-backlight"; + pwms = <&disp_pwm1 0 500000>; + enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + status = "disabled"; + }; + + can_clk: can-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "can-clk"; + }; + + edp_panel_fixed_3v3: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "edp_panel_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_3v3_en_pins>; + }; + + edp_panel_fixed_12v: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "edp_backlight_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&pio 96 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_12v_en_pins>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + + button-volume-up { + wakeup-source; + debounce-interval = <100>; + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + }; + }; + + lcm0_iovcc: regulator-vio18-lcm0 { + compatible = "regulator-fixed"; + regulator-name = "vio18_lcm0"; + enable-active-high; + gpio = <&pio 47 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_vreg_en_pins>; + vin-supply = <&mt6360_ldo2>; + }; + + lcm0_vddp: regulator-vsys-lcm0 { + compatible = "regulator-fixed"; + regulator-name = "vsys_lcm0"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&mt6360_ldo1>; + }; + + wifi_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "wifi_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 135 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu4 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu5 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + +&dither0_in { + remote-endpoint = <&gamma0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dmic_codec { + wakeup-delay-ms = <200>; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "startek,kd070fhfid078", "himax,hx8279"; + reg = <0>; + backlight = <&backlight_lcm0>; + enable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 108 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&lcm0_iovcc>; + vdd-supply = <&lcm0_vddp>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_pins>; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; +}; + +ð { + phy-mode ="rgmii-rxid"; + phy-handle = <ð_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + mediatek,tx-delay-ps = <2030>; + mediatek,mac-wol; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + eth_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + +&gamma0_out { + remote-endpoint = <&dither0_in>; +}; + +&gpu { + mali-supply = <&mt6315_7_vbuck1>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&mt6360_ldo1>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + status = "okay"; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + vcc-supply = <&mt6359_vibr_ldo_reg>; + mode-switch; + orientation-switch; + status = "okay"; + + port { + it5205_sbu_ep: endpoint { + remote-endpoint = <&mt6360_ssusb_sbu_ep>; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <128 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + interrupt-controller; + #interrupt-cells = <1>; + pinctrl-0 = <&mt6360_pins>; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-name = "tp1_p3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo2: ldo2 { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: ldo3 { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: ldo5 { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + /* This is a measure point, which name is mt6360_ldo1 on schematic */ + mt6360_ldo6: ldo6 { + regulator-name = "mt6360_ldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: ldo7 { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + + tcpc { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + + source-pdos = ; + sink-pdos = ; + + pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0x00001c46>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs0_role_sw>; + }; + }; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&mtu3_ss0_role_sw>; + }; + }; + + port@2 { + reg = <2>; + mt6360_ssusb_sbu_ep: endpoint { + remote-endpoint = <&it5205_sbu_ep>; + }; + }; + }; + }; + }; + }; +}; + +&mfg0 { + domain-supply = <&mt6315_7_vbuck1>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x14c11>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; + non-removable; +}; + +&mt6359_vaud18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +/* For USB Hub */ +&mt6359_vcamio_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; /* ACC */ + mediatek,mic-type-1 = <3>; /* DCC */ + mediatek,mic-type-2 = <1>; /* ACC */ +}; + +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + +&pcie0 { + pinctrl-names = "default", "idle"; + pinctrl-0 = <&pcie0_default_pins>; + pinctrl-1 = <&pcie0_idle_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_pins>; + status = "disabled"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + disp_pwm1_default_pins: disp-pwm1-default-pins { + pins1 { + pinmux = ; + }; + }; + + edp_panel_12v_en_pins: edp-panel-12v-en-pins { + pins1 { + pinmux = ; + output-high; + }; + }; + + edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { + pins1 { + pinmux = ; + output-high; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = , + ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + }; + }; + + gpio_key_pins: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength = <6>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mt6360_pins: mt6360-pins { + pins { + pinmux = , + ; + input-enable; + bias-pull-up; + }; + }; + + dsi0_vreg_en_pins: dsi0-vreg-en-pins { + pins-pwr-en { + pinmux = ; + output-low; + }; + }; + + panel_default_pins: panel-default-pins { + pins-rst { + pinmux = ; + output-high; + }; + + pins-en { + pinmux = ; + output-low; + }; + }; + + pcie0_default_pins: pcie0-default-pins { + pins { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pcie0_idle_pins: pcie0-idle-pins { + pins { + pinmux = ; + bias-disable; + output-low; + }; + }; + + pcie1_default_pins: pcie1-default-pins { + pins { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + disp_pwm0_pins: disp-pwm0-pins { + pins-disp-pwm { + pinmux = ; + }; + }; + + spi1_pins: spi1-pins { + pins { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi-pins { + pins { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = ; + output-high; + }; + }; + + u3_p0_vbus: u3-p0-vbus-default-pins { + pins-vbus { + pinmux = ; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + , + , + ; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = ; + wakeup-source; + }; + + home { + linux,keycodes = ; + }; + }; +}; + +&scp { + memory-region = <&scp_mem>; + firmware-name = "mediatek/mt8195/scp.img"; + status = "okay"; +}; + +&sound { + compatible = "mediatek,mt8195_mt6359"; + model = "mt8395-evk"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_default_pins>; + audio-routing = + "Headphone", "Headphone L", + "Headphone", "Headphone R"; + mediatek,adsp = <&adsp>; + status = "okay"; + + headphone-dai-link { + link-name = "DL_SRC_BE"; + + codec { + sound-dai = <&pmic 0>; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + clocks = <&can_clk>; + spi-max-frequency = <20000000>; + interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + }; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-name = "Vgpu"; + regulator-min-microvolt = <546000>; + regulator-max-microvolt = <787000>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; + + u3port1: usb-phy@700 { + mediatek,force-mode; + }; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ufsphy { + status = "disabled"; +}; + +&ssusb0 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&u3_p0_vbus>; + usb-role-switch; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mtu3_hs0_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; + + port@1 { + reg = <1>; + mtu3_ss0_role_sw: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; +}; + +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + status = "okay"; +}; + +&xhci3 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/nvidia/tegra132.dtsi b/dts/upstream/src/arm64/nvidia/tegra132.dtsi index 5bcccfef3f7..26cd11a8a4a 100644 --- a/dts/upstream/src/arm64/nvidia/tegra132.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra132.dtsi @@ -175,6 +175,7 @@ gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x50041000 0x0 0x1000>, @@ -271,7 +272,7 @@ interrupt-controller; }; - apbdma: dma@60020000 { + apbdma: dma-controller@60020000 { compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; reg = <0x0 0x60020000 0x0 0x1400>; interrupts = , diff --git a/dts/upstream/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts b/dts/upstream/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts index 5f3f572ecea..d9aafe05311 100644 --- a/dts/upstream/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/dts/upstream/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -671,7 +671,6 @@ vbus-gpios = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_LOW>; - id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; }; }; diff --git a/dts/upstream/src/arm64/nvidia/tegra186.dtsi b/dts/upstream/src/arm64/nvidia/tegra186.dtsi index 5778c93af3e..b0063045190 100644 --- a/dts/upstream/src/arm64/nvidia/tegra186.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra186.dtsi @@ -36,6 +36,12 @@ interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux 0 0 140>; + }; + + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra186-pinmux"; + reg = <0x0 0x2430000 0x0 0x15000>; }; ethernet@2490000 { @@ -1173,6 +1179,7 @@ gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x03881000 0x0 0x1000>, @@ -1274,10 +1281,16 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pinmux_aon 0 0 47>; interrupt-controller; #interrupt-cells = <2>; }; + pinmux_aon: pinmux@c300000 { + compatible = "nvidia,tegra186-pinmux-aon"; + reg = <0x0 0xc300000 0x0 0x4000>; + }; + pwm4: pwm@c340000 { compatible = "nvidia,tegra186-pwm"; reg = <0x0 0xc340000 0x0 0x10000>; diff --git a/dts/upstream/src/arm64/nvidia/tegra194.dtsi b/dts/upstream/src/arm64/nvidia/tegra194.dtsi index 1399342f23e..b782f8db128 100644 --- a/dts/upstream/src/arm64/nvidia/tegra194.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra194.dtsi @@ -1331,6 +1331,7 @@ gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x03881000 0x0 0x1000>, diff --git a/dts/upstream/src/arm64/nvidia/tegra210-p2180.dtsi b/dts/upstream/src/arm64/nvidia/tegra210-p2180.dtsi index e07aeeee358..9ee7952af79 100644 --- a/dts/upstream/src/arm64/nvidia/tegra210-p2180.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra210-p2180.dtsi @@ -18,6 +18,12 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; diff --git a/dts/upstream/src/arm64/nvidia/tegra210-p2597.dtsi b/dts/upstream/src/arm64/nvidia/tegra210-p2597.dtsi index 584461f3a61..4a64fe510f0 100644 --- a/dts/upstream/src/arm64/nvidia/tegra210-p2597.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra210-p2597.dtsi @@ -20,10 +20,10 @@ vi@54080000 { status = "okay"; - avdd-dsi-csi-supply = <&vdd_dsi_csi>; - csi@838 { status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; }; }; diff --git a/dts/upstream/src/arm64/nvidia/tegra210-p3450-0000.dts b/dts/upstream/src/arm64/nvidia/tegra210-p3450-0000.dts index ec0e84cb83e..d78b9bd45df 100644 --- a/dts/upstream/src/arm64/nvidia/tegra210-p3450-0000.dts +++ b/dts/upstream/src/arm64/nvidia/tegra210-p3450-0000.dts @@ -22,6 +22,12 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; @@ -64,10 +70,10 @@ vi@54080000 { status = "okay"; - avdd-dsi-csi-supply = <&vdd_sys_1v2>; - csi@838 { status = "okay"; + + avdd-dsi-csi-supply = <&vdd_sys_1v2>; }; }; @@ -520,7 +526,7 @@ ports { usb2-0 { status = "okay"; - mode = "peripheral"; + mode = "otg"; usb-role-switch; vbus-supply = <&vdd_5v0_usb>; diff --git a/dts/upstream/src/arm64/nvidia/tegra210-p3541-0000.dts b/dts/upstream/src/arm64/nvidia/tegra210-p3541-0000.dts new file mode 100644 index 00000000000..b86e271dde0 --- /dev/null +++ b/dts/upstream/src/arm64/nvidia/tegra210-p3541-0000.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra210-p3450-0000.dts" + +/ { + model = "NVIDIA Jetson Nano 2GB Developer Kit"; + compatible = "nvidia,p3541-0000", "nvidia,p3450-0000", "nvidia,tegra210"; + + memory@80000000 { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@50000000 { + sor@54540000 { + status = "disabled"; + }; + + dpaux@545c0000 { + status = "disabled"; + }; + }; + + padctl@7009f000 { + ports { + usb2-1 { + vbus-supply = <&vdd_hub_5v0>; + }; + + usb2-2 { + vbus-supply = <&vdd_hub_5v0>; + }; + + usb3-0 { + /delete-property/ vbus-supply; + }; + }; + }; + + regulator-vdd-hdmi-5v0 { + gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /delete-node/ regulator-vdd-hub-3v3; + + vdd_hub_5v0: regulator-vdd-hub-5v0 { + compatible = "regulator-fixed"; + + regulator-name = "VDD_HUB_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vdd_5v0_sys>; + }; +}; diff --git a/dts/upstream/src/arm64/nvidia/tegra210-peripherals-opp.dtsi b/dts/upstream/src/arm64/nvidia/tegra210-peripherals-opp.dtsi new file mode 100644 index 00000000000..bf2527d7379 --- /dev/null +++ b/dts/upstream/src/arm64/nvidia/tegra210-peripherals-opp.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* EMC DVFS OPP table */ + emc_icc_dvfs_opp_table: opp-table-dvfs0 { + compatible = "operating-points-v2"; + + opp-40800000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp-68000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0007>; + opp-suspend; + }; + + opp-408000000-812 { + opp-microvolt = <812000 812000 1150000>; + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0003>; + }; + + opp-665600000-825 { + opp-microvolt = <825000 825000 1150000>; + opp-hz = /bits/ 64 <665600000>; + opp-supported-hw = <0x0003>; + }; + + opp-800000000-825 { + opp-microvolt = <825000 825000 1150000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0003>; + }; + + opp-1065600000-837 { + opp-microvolt = <837000 837000 1150000>; + opp-hz = /bits/ 64 <1065600000>; + opp-supported-hw = <0x0003>; + }; + + opp-1331200000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <1331200000>; + opp-supported-hw = <0x0003>; + }; + + opp-1600000000-887 { + opp-microvolt = <887000 887000 1150000>; + opp-hz = /bits/ 64 <1600000000>; + opp-supported-hw = <0x0007>; + }; + }; + + /* EMC bandwidth OPP table */ + emc_bw_dfs_opp_table: opp-table-dvfs1 { + compatible = "operating-points-v2"; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0007>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <6528000>; + }; + + opp-665600000 { + opp-hz = /bits/ 64 <665600000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <10649600>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12800000>; + }; + + opp-1065600000 { + opp-hz = /bits/ 64 <1065600000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <17049600>; + }; + + opp-1331200000 { + opp-hz = /bits/ 64 <1331200000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <21299200>; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-supported-hw = <0x0007>; + opp-peak-kBps = <25600000>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/nvidia/tegra210.dtsi b/dts/upstream/src/arm64/nvidia/tegra210.dtsi index 402b0ede147..137aa837525 100644 --- a/dts/upstream/src/arm64/nvidia/tegra210.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra210.dtsi @@ -9,6 +9,8 @@ #include #include +#include "tegra210-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra210"; interrupt-parent = <&lic>; @@ -183,9 +185,7 @@ reg = <0x0 0x54100000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_TSEC>; - clock-names = "tsec"; resets = <&tegra_car 83>; - reset-names = "tsec"; status = "disabled"; }; @@ -253,7 +253,13 @@ nvjpg@54380000 { compatible = "nvidia,tegra210-nvjpg"; reg = <0x0 0x54380000 0x0 0x00040000>; - status = "disabled"; + clocks = <&tegra_car TEGRA210_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&tegra_car 195>; + reset-names = "nvjpg"; + + iommus = <&mc TEGRA_SWGROUP_NVJPG>; + power-domains = <&pd_nvjpg>; }; dsib: dsi@54400000 { @@ -277,13 +283,25 @@ nvdec@54480000 { compatible = "nvidia,tegra210-nvdec"; reg = <0x0 0x54480000 0x0 0x00040000>; - status = "disabled"; + clocks = <&tegra_car TEGRA210_CLK_NVDEC>; + clock-names = "nvdec"; + resets = <&tegra_car 194>; + reset-names = "nvdec"; + + iommus = <&mc TEGRA_SWGROUP_NVDEC>; + power-domains = <&pd_nvdec>; }; nvenc@544c0000 { compatible = "nvidia,tegra210-nvenc"; reg = <0x0 0x544c0000 0x0 0x00040000>; - status = "disabled"; + clocks = <&tegra_car TEGRA210_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&tegra_car 219>; + reset-names = "nvenc"; + + iommus = <&mc TEGRA_SWGROUP_NVENC>; + power-domains = <&pd_nvenc>; }; tsec@54500000 { @@ -409,6 +427,7 @@ gic: interrupt-controller@50041000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x50041000 0x0 0x1000>, @@ -485,6 +504,21 @@ reg = <0x0 0x60007000 0x0 0x1000>; }; + actmon@6000c800 { + compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon"; + reg = <0x0 0x6000c800 0x0 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_ACTMON>, + <&tegra_car TEGRA210_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car 119>; + reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA210_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; + #cooling-cells = <2>; + }; + gpio: gpio@6000d000 { compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; @@ -502,7 +536,7 @@ interrupt-controller; }; - apbdma: dma@60020000 { + apbdma: dma-controller@60020000 { compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; reg = <0x0 0x60020000 0x0 0x1400>; interrupts = , @@ -894,6 +928,18 @@ #power-domain-cells = <0>; }; + pd_nvenc: mpe { + clocks = <&tegra_car TEGRA210_CLK_NVENC>; + resets = <&tegra_car 219>; + #power-domain-cells = <0>; + }; + + pd_nvdec: nvdec { + clocks = <&tegra_car TEGRA210_CLK_NVDEC>; + resets = <&tegra_car 194>; + #power-domain-cells = <0>; + }; + pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, @@ -947,6 +993,12 @@ resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; #power-domain-cells = <0>; }; + + pd_nvjpg: nvjpg { + clocks = <&tegra_car TEGRA210_CLK_NVJPG>; + resets = <&tegra_car 195>; + #power-domain-cells = <0>; + }; }; }; @@ -989,6 +1041,8 @@ clock-names = "emc"; interrupts = ; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + #cooling-cells = <2>; }; diff --git a/dts/upstream/src/arm64/nvidia/tegra234-p3701.dtsi b/dts/upstream/src/arm64/nvidia/tegra234-p3701.dtsi index 9086a0d010e..58bf55c0e41 100644 --- a/dts/upstream/src/arm64/nvidia/tegra234-p3701.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra234-p3701.dtsi @@ -8,6 +8,7 @@ aliases { mmc0 = "/bus@0/mmc@3460000"; mmc1 = "/bus@0/mmc@3400000"; + rtc0 = "/bpmp/i2c/pmic@3c"; }; bus@0 { @@ -170,6 +171,16 @@ i2c { status = "okay"; + pmic@3c { + compatible = "nvidia,vrs-10"; + reg = <0x3c>; + interrupt-parent = <&pmc>; + /* VRS Wake ID is 24 */ + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + }; + thermal-sensor@4c { compatible = "ti,tmp451"; status = "okay"; diff --git a/dts/upstream/src/arm64/nvidia/tegra234-p3767.dtsi b/dts/upstream/src/arm64/nvidia/tegra234-p3767.dtsi index 84db7132e8f..ab391a71c3d 100644 --- a/dts/upstream/src/arm64/nvidia/tegra234-p3767.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra234-p3767.dtsi @@ -7,6 +7,7 @@ aliases { mmc0 = "/bus@0/mmc@3400000"; + rtc0 = "/bpmp/i2c/pmic@3c"; }; bus@0 { @@ -121,6 +122,20 @@ }; }; + bpmp { + i2c { + pmic@3c { + compatible = "nvidia,vrs-10"; + reg = <0x3c>; + interrupt-parent = <&pmc>; + /* VRS Wake ID is 24 */ + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; diff --git a/dts/upstream/src/arm64/nvidia/tegra234.dtsi b/dts/upstream/src/arm64/nvidia/tegra234.dtsi index df034dbb828..827dbb42082 100644 --- a/dts/upstream/src/arm64/nvidia/tegra234.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra234.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra234"; @@ -127,6 +128,56 @@ pinmux: pinmux@2430000 { compatible = "nvidia,tegra234-pinmux"; reg = <0x0 0x2430000 0x0 0x19100>; + + pex_rst_c4_in_state: pinmux-pex-rst-c4-in { + pex_rst { + nvidia,pins = "pex_l4_rst_n_pl1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c5_in_state: pinmux-pex-rst-c5-in { + pex_rst { + nvidia,pins = "pex_l5_rst_n_paf1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c6_in_state: pinmux-pex-rst-c6-in { + pex_rst { + nvidia,pins = "pex_l6_rst_n_paf3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c7_in_state: pinmux-pex-rst-c7-in { + pex_rst { + nvidia,pins = "pex_l7_rst_n_pag1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + + pex_rst_c10_in_state: pinmux-pex-rst-c10-in { + pex_rst { + nvidia,pins = "pex_l10_rst_n_pag7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; }; gpcdma: dma-controller@2600000 { @@ -3276,8 +3327,15 @@ <0x0 0x03650000 0x0 0x10000>; reg-names = "hcd", "fpci", "bar2"; - interrupts = , - ; + interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 77 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 79 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 80 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 81 IRQ_TYPE_LEVEL_HIGH>, + <&pmc 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, <&bpmp TEGRA234_CLK_XUSB_FALCON>, @@ -4630,6 +4688,8 @@ <&bpmp TEGRA234_RESET_PEX2_CORE_10>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c10_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; @@ -4881,6 +4941,8 @@ <&bpmp TEGRA234_RESET_PEX0_CORE_4>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c4_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; nvidia,bpmp = <&bpmp 4>; @@ -5023,6 +5085,8 @@ <&bpmp TEGRA234_RESET_PEX1_CORE_5>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; @@ -5115,6 +5179,8 @@ <&bpmp TEGRA234_RESET_PEX1_CORE_6>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c6_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; @@ -5207,6 +5273,8 @@ <&bpmp TEGRA234_RESET_PEX2_CORE_7>; reset-names = "apb", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c7_in_state>; interrupts = ; /* controller interrupt */ interrupt-names = "intr"; diff --git a/dts/upstream/src/arm64/nvidia/tegra264-p3971.dtsi b/dts/upstream/src/arm64/nvidia/tegra264-p3971.dtsi index 6b6259b7310..b1bd4ee7aee 100644 --- a/dts/upstream/src/arm64/nvidia/tegra264-p3971.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra264-p3971.dtsi @@ -1,4 +1,112 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause / { + bus@0 { + aconnect@9000000 { + status = "okay"; + + dma-controller@9440000 { + status = "okay"; + }; + + ahub@9630000 { + status = "okay"; + + i2s@9280000 { + status = "okay"; + }; + + i2s@9290000 { + status = "okay"; + }; + + i2s@92b0000 { + status = "okay"; + }; + }; + + interrupt-controller@9960000 { + status = "okay"; + }; + }; + }; + + bus@8800000000 { + hda@90b0000 { + nvidia,model = "NVIDIA Jetson Thor AGX HDA"; + status = "okay"; + }; + }; + + sound { + status = "okay"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + <&admaif20_port>, <&admaif21_port>, <&admaif22_port>, <&admaif23_port>, + <&admaif24_port>, <&admaif25_port>, <&admaif26_port>, <&admaif27_port>, + <&admaif28_port>, <&admaif29_port>, <&admaif30_port>, <&admaif31_port>, + /* XBAR Ports */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_amx5_in1_port>, <&xbar_amx5_in2_port>, + <&xbar_amx5_in3_port>, <&xbar_amx5_in4_port>, + <&xbar_amx6_in1_port>, <&xbar_amx6_in2_port>, + <&xbar_amx6_in3_port>, <&xbar_amx6_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_adx5_in_port>, <&xbar_adx6_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&amx5_out_port>, <&amx6_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&adx5_out1_port>, <&adx5_out2_port>, + <&adx5_out3_port>, <&adx5_out4_port>, + <&adx6_out1_port>, <&adx6_out2_port>, + <&adx6_out3_port>, <&adx6_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, + /* BE I/O Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s4_port>; + + label = "NVIDIA Jetson Thor AGX APE"; + }; }; diff --git a/dts/upstream/src/arm64/nvidia/tegra264.dtsi b/dts/upstream/src/arm64/nvidia/tegra264.dtsi index 872a69553e3..f137565da80 100644 --- a/dts/upstream/src/arm64/nvidia/tegra264.dtsi +++ b/dts/upstream/src/arm64/nvidia/tegra264.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include / { @@ -49,6 +50,3163 @@ status = "disabled"; }; + aconnect@9000000 { + compatible = "nvidia,tegra264-aconnect", + "nvidia,tegra210-aconnect"; + clocks = <&bpmp TEGRA264_CLK_APE>, + <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "ape", "apb2ape"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>; + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>; + + adma: dma-controller@9440000 { + compatible = "nvidia,tegra264-adma"; + reg = <0x0 0x9440000 0x0 0xb0000>; + interrupt-parent = <&agic_page0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + clocks = <&bpmp TEGRA264_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + tegra_ahub: ahub@9630000 { + compatible = "nvidia,tegra264-ahub"; + reg = <0x0 0x9630000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>; + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + /* ADMA is under AHUB range, its excluded in the defined range */ + ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>, + <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>; + + tegra_i2s1: i2s@9280000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x9280000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S1>, + <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif: endpoint { + remote-endpoint = <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s2: i2s@9290000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x9290000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S2>, + <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif: endpoint { + remote-endpoint = <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s3: i2s@92a0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92a0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S3>, + <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif: endpoint { + remote-endpoint = <&xbar_i2s3>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s4: i2s@92b0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92b0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S4>, + <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif: endpoint { + remote-endpoint = <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s5: i2s@92c0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92c0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S5>, + <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif: endpoint { + remote-endpoint = <&xbar_i2s5>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s6: i2s@92d0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92d0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S6>, + <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif: endpoint { + remote-endpoint = <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s7: i2s@92e0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92e0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S7>, + <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S7"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s7_cif: endpoint { + remote-endpoint = <&xbar_i2s7>; + }; + }; + + i2s7_port: port@1 { + reg = <1>; + + i2s7_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s8: i2s@92f0000 { + compatible = "nvidia,tegra264-i2s"; + reg = <0x0 0x92f0000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_I2S8>, + <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S8"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s8_cif: endpoint { + remote-endpoint = <&xbar_i2s8>; + }; + }; + + i2s8_port: port@1 { + reg = <1>; + + i2s8_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dmic1: dmic@9300000 { + compatible = "nvidia,tegra264-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x9300000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif: endpoint { + remote-endpoint = <&xbar_dmic1>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dmic2: dmic@9310000 { + compatible = "nvidia,tegra264-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x9310000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif: endpoint { + remote-endpoint = <&xbar_dmic2>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dspk1: dspk@9380000 { + compatible = "nvidia,tegra264-dspk", + "nvidia,tegra186-dspk"; + reg = <0x0 0x9380000 0x0 0x10000>; + clocks = <&bpmp TEGRA264_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif: endpoint { + remote-endpoint = <&xbar_dspk1>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_amx1: amx@9510000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9510000 0x0 0x10000>; + sound-name-prefix = "AMX1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1: endpoint { + remote-endpoint = <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2: endpoint { + remote-endpoint = <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3: endpoint { + remote-endpoint = <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4: endpoint { + remote-endpoint = <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out: endpoint { + remote-endpoint = <&xbar_amx1_out>; + }; + }; + }; + }; + + tegra_amx2: amx@9520000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9520000 0x0 0x10000>; + sound-name-prefix = "AMX2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1: endpoint { + remote-endpoint = <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2: endpoint { + remote-endpoint = <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx2_in3: endpoint { + remote-endpoint = <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx2_in4: endpoint { + remote-endpoint = <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out: endpoint { + remote-endpoint = <&xbar_amx2_out>; + }; + }; + }; + }; + + tegra_amx3: amx@9530000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9530000 0x0 0x10000>; + sound-name-prefix = "AMX3"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1: endpoint { + remote-endpoint = <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2: endpoint { + remote-endpoint = <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3: endpoint { + remote-endpoint = <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4: endpoint { + remote-endpoint = <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out: endpoint { + remote-endpoint = <&xbar_amx3_out>; + }; + }; + }; + }; + + tegra_amx4: amx@9540000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9540000 0x0 0x10000>; + sound-name-prefix = "AMX4"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1: endpoint { + remote-endpoint = <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2: endpoint { + remote-endpoint = <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3: endpoint { + remote-endpoint = <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4: endpoint { + remote-endpoint = <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out: endpoint { + remote-endpoint = <&xbar_amx4_out>; + }; + }; + }; + }; + + tegra_amx5: amx@9550000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9550000 0x0 0x10000>; + sound-name-prefix = "AMX5"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx5_in1: endpoint { + remote-endpoint = <&xbar_amx5_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx5_in2: endpoint { + remote-endpoint = <&xbar_amx5_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx5_in3: endpoint { + remote-endpoint = <&xbar_amx5_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx5_in4: endpoint { + remote-endpoint = <&xbar_amx5_in4>; + }; + }; + + amx5_out_port: port@4 { + reg = <4>; + + amx5_out: endpoint { + remote-endpoint = <&xbar_amx5_out>; + }; + }; + }; + }; + + tegra_amx6: amx@9560000 { + compatible = "nvidia,tegra264-amx"; + reg = <0x0 0x9560000 0x0 0x10000>; + sound-name-prefix = "AMX6"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx6_in1: endpoint { + remote-endpoint = <&xbar_amx6_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx6_in2: endpoint { + remote-endpoint = <&xbar_amx6_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx6_in3: endpoint { + remote-endpoint = <&xbar_amx6_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx6_in4: endpoint { + remote-endpoint = <&xbar_amx6_in4>; + }; + }; + + amx6_out_port: port@4 { + reg = <4>; + + amx6_out: endpoint { + remote-endpoint = <&xbar_amx6_out>; + }; + }; + }; + }; + + tegra_adx1: adx@9590000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x9590000 0x0 0x10000>; + sound-name-prefix = "ADX1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in: endpoint { + remote-endpoint = <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1: endpoint { + remote-endpoint = <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2: endpoint { + remote-endpoint = <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3: endpoint { + remote-endpoint = <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4: endpoint { + remote-endpoint = <&xbar_adx1_out4>; + }; + }; + }; + }; + + tegra_adx2: adx@95a0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95a0000 0x0 0x10000>; + sound-name-prefix = "ADX2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in: endpoint { + remote-endpoint = <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1: endpoint { + remote-endpoint = <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2: endpoint { + remote-endpoint = <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3: endpoint { + remote-endpoint = <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4: endpoint { + remote-endpoint = <&xbar_adx2_out4>; + }; + }; + }; + }; + + tegra_adx3: adx@95b0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95b0000 0x0 0x10000>; + sound-name-prefix = "ADX3"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in: endpoint { + remote-endpoint = <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1: endpoint { + remote-endpoint = <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2: endpoint { + remote-endpoint = <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3: endpoint { + remote-endpoint = <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4: endpoint { + remote-endpoint = <&xbar_adx3_out4>; + }; + }; + }; + }; + + tegra_adx4: adx@95c0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95c0000 0x0 0x10000>; + sound-name-prefix = "ADX4"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in: endpoint { + remote-endpoint = <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1: endpoint { + remote-endpoint = <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2: endpoint { + remote-endpoint = <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3: endpoint { + remote-endpoint = <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4: endpoint { + remote-endpoint = <&xbar_adx4_out4>; + }; + }; + }; + }; + + tegra_adx5: adx@95d0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95d0000 0x0 0x10000>; + sound-name-prefix = "ADX5"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx5_in: endpoint { + remote-endpoint = <&xbar_adx5_in>; + }; + }; + + adx5_out1_port: port@1 { + reg = <1>; + + adx5_out1: endpoint { + remote-endpoint = <&xbar_adx5_out1>; + }; + }; + + adx5_out2_port: port@2 { + reg = <2>; + + adx5_out2: endpoint { + remote-endpoint = <&xbar_adx5_out2>; + }; + }; + + adx5_out3_port: port@3 { + reg = <3>; + + adx5_out3: endpoint { + remote-endpoint = <&xbar_adx5_out3>; + }; + }; + + adx5_out4_port: port@4 { + reg = <4>; + + adx5_out4: endpoint { + remote-endpoint = <&xbar_adx5_out4>; + }; + }; + }; + }; + + tegra_adx6: adx@95e0000 { + compatible = "nvidia,tegra264-adx"; + reg = <0x0 0x95e0000 0x0 0x10000>; + sound-name-prefix = "ADX6"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx6_in: endpoint { + remote-endpoint = <&xbar_adx6_in>; + }; + }; + + adx6_out1_port: port@1 { + reg = <1>; + + adx6_out1: endpoint { + remote-endpoint = <&xbar_adx6_out1>; + }; + }; + + adx6_out2_port: port@2 { + reg = <2>; + + adx6_out2: endpoint { + remote-endpoint = <&xbar_adx6_out2>; + }; + }; + + adx6_out3_port: port@3 { + reg = <3>; + + adx6_out3: endpoint { + remote-endpoint = <&xbar_adx6_out3>; + }; + }; + + adx6_out4_port: port@4 { + reg = <4>; + + adx6_out4: endpoint { + remote-endpoint = <&xbar_adx6_out4>; + }; + }; + }; + }; + + tegra_admaif: admaif@9610000 { + compatible = "nvidia,tegra264-admaif"; + reg = <0x0 0x9610000 0x0 0x10000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>, + <&adma 21>, <&adma 21>, + <&adma 22>, <&adma 22>, + <&adma 23>, <&adma 23>, + <&adma 24>, <&adma 24>, + <&adma 25>, <&adma 25>, + <&adma 26>, <&adma 26>, + <&adma 27>, <&adma 27>, + <&adma 28>, <&adma 28>, + <&adma 29>, <&adma 29>, + <&adma 30>, <&adma 30>, + <&adma 31>, <&adma 31>, + <&adma 32>, <&adma 32>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20", + "rx21", "tx21", + "rx22", "tx22", + "rx23", "tx23", + "rx24", "tx24", + "rx25", "tx25", + "rx26", "tx26", + "rx27", "tx27", + "rx28", "tx28", + "rx29", "tx29", + "rx30", "tx30", + "rx31", "tx31", + "rx32", "tx32"; + + interconnects = + <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + + iommus = <&smmu1 TEGRA264_SID_APE>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0: endpoint { + remote-endpoint = <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1: endpoint { + remote-endpoint = <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2: endpoint { + remote-endpoint = <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3: endpoint { + remote-endpoint = <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4: endpoint { + remote-endpoint = <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5: endpoint { + remote-endpoint = <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6: endpoint { + remote-endpoint = <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7: endpoint { + remote-endpoint = <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8: endpoint { + remote-endpoint = <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9: endpoint { + remote-endpoint = <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10: endpoint { + remote-endpoint = <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11: endpoint { + remote-endpoint = <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12: endpoint { + remote-endpoint = <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13: endpoint { + remote-endpoint = <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14: endpoint { + remote-endpoint = <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15: endpoint { + remote-endpoint = <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16: endpoint { + remote-endpoint = <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17: endpoint { + remote-endpoint = <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18: endpoint { + remote-endpoint = <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19: endpoint { + remote-endpoint = <&xbar_admaif19>; + }; + }; + + admaif20_port: port@14 { + reg = <0x14>; + + admaif20: endpoint { + remote-endpoint = <&xbar_admaif20>; + }; + }; + + admaif21_port: port@15 { + reg = <0x15>; + + admaif21: endpoint { + remote-endpoint = <&xbar_admaif21>; + }; + }; + + admaif22_port: port@16 { + reg = <0x16>; + + admaif22: endpoint { + remote-endpoint = <&xbar_admaif22>; + }; + }; + + admaif23_port: port@17 { + reg = <0x17>; + + admaif23: endpoint { + remote-endpoint = <&xbar_admaif23>; + }; + }; + + admaif24_port: port@18 { + reg = <0x18>; + + admaif24: endpoint { + remote-endpoint = <&xbar_admaif24>; + }; + }; + + admaif25_port: port@19 { + reg = <0x19>; + + admaif25: endpoint { + remote-endpoint = <&xbar_admaif25>; + }; + }; + + admaif26_port: port@1a { + reg = <0x1a>; + + admaif26: endpoint { + remote-endpoint = <&xbar_admaif26>; + }; + }; + + admaif27_port: port@1b { + reg = <0x1b>; + + admaif27: endpoint { + remote-endpoint = <&xbar_admaif27>; + }; + }; + + admaif28_port: port@1c { + reg = <0x1c>; + + admaif28: endpoint { + remote-endpoint = <&xbar_admaif28>; + }; + }; + + admaif29_port: port@1d { + reg = <0x1d>; + + admaif29: endpoint { + remote-endpoint = <&xbar_admaif29>; + }; + }; + + admaif30_port: port@1e { + reg = <0x1e>; + + admaif30: endpoint { + remote-endpoint = <&xbar_admaif30>; + }; + }; + + admaif31_port: port@1f { + reg = <0x1f>; + + admaif31: endpoint { + remote-endpoint = <&xbar_admaif31>; + }; + }; + }; + }; + + tegra_sfc1: sfc@9700000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9700000 0x0 0x10000>; + sound-name-prefix = "SFC1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in: endpoint { + remote-endpoint = <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out: endpoint { + remote-endpoint = <&xbar_sfc1_out>; + }; + }; + }; + }; + + tegra_sfc2: sfc@9710000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9710000 0x0 0x10000>; + sound-name-prefix = "SFC2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in: endpoint { + remote-endpoint = <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out: endpoint { + remote-endpoint = <&xbar_sfc2_out>; + }; + }; + }; + }; + + tegra_sfc3: sfc@9720000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9720000 0x0 0x10000>; + sound-name-prefix = "SFC3"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in: endpoint { + remote-endpoint = <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out: endpoint { + remote-endpoint = <&xbar_sfc3_out>; + }; + }; + }; + }; + + tegra_sfc4: sfc@9730000 { + compatible = "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg = <0x0 0x9730000 0x0 0x10000>; + sound-name-prefix = "SFC4"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in: endpoint { + remote-endpoint = <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out: endpoint { + remote-endpoint = <&xbar_sfc4_out>; + }; + }; + }; + }; + + tegra_ope1: processing-engine@9780000 { + compatible = "nvidia,tegra264-ope", + "nvidia,tegra210-ope"; + reg = <0x0 0x9780000 0x0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>; + sound-name-prefix = "OPE1"; + + equalizer@9790000 { + compatible = "nvidia,tegra264-peq", + "nvidia,tegra210-peq"; + reg = <0x0 0x9790000 0x0 0x10000>; + }; + + dynamic-range-compressor@97a0000 { + compatible = "nvidia,tegra264-mbdrc", + "nvidia,tegra210-mbdrc"; + reg = <0x0 0x97a0000 0x0 0x10000>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = + <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = + <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + tegra_mvc1: mvc@9800000 { + compatible = "nvidia,tegra264-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x9800000 0x0 0x10000>; + sound-name-prefix = "MVC1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in: endpoint { + remote-endpoint = <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out: endpoint { + remote-endpoint = <&xbar_mvc1_out>; + }; + }; + }; + }; + + tegra_mvc2: mvc@9810000 { + compatible = "nvidia,tegra264-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x9810000 0x0 0x10000>; + sound-name-prefix = "MVC2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in: endpoint { + remote-endpoint = <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out: endpoint { + remote-endpoint = <&xbar_mvc2_out>; + }; + }; + }; + }; + + tegra_amixer: amixer@9820000 { + compatible = "nvidia,tegra264-amixer", + "nvidia,tegra210-amixer"; + reg = <0x0 0x9820000 0x0 0x10000>; + sound-name-prefix = "MIXER1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mix_in1: endpoint { + remote-endpoint = <&xbar_mix_in1>; + }; + }; + + port@1 { + reg = <0x1>; + + mix_in2: endpoint { + remote-endpoint = <&xbar_mix_in2>; + }; + }; + + port@2 { + reg = <0x2>; + + mix_in3: endpoint { + remote-endpoint = <&xbar_mix_in3>; + }; + }; + + port@3 { + reg = <0x3>; + + mix_in4: endpoint { + remote-endpoint = <&xbar_mix_in4>; + }; + }; + + port@4 { + reg = <0x4>; + + mix_in5: endpoint { + remote-endpoint = <&xbar_mix_in5>; + }; + }; + + port@5 { + reg = <0x5>; + + mix_in6: endpoint { + remote-endpoint = <&xbar_mix_in6>; + }; + }; + + port@6 { + reg = <0x6>; + + mix_in7: endpoint { + remote-endpoint = <&xbar_mix_in7>; + }; + }; + + port@7 { + reg = <0x7>; + + mix_in8: endpoint { + remote-endpoint = <&xbar_mix_in8>; + }; + }; + + port@8 { + reg = <0x8>; + + mix_in9: endpoint { + remote-endpoint = <&xbar_mix_in9>; + }; + }; + + port@9 { + reg = <0x9>; + + mix_in10: endpoint { + remote-endpoint = <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg = <0xa>; + + mix_out1: endpoint { + remote-endpoint = <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg = <0xb>; + + mix_out2: endpoint { + remote-endpoint = <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg = <0xc>; + + mix_out3: endpoint { + remote-endpoint = <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg = <0xd>; + + mix_out4: endpoint { + remote-endpoint = <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg = <0xe>; + + mix_out5: endpoint { + remote-endpoint = <&xbar_mix_out5>; + }; + }; + }; + }; + + tegra_asrc: asrc@9850000 { + compatible = "nvidia,tegra264-asrc"; + reg = <0x0 0x9850000 0x0 0x10000>; + sound-name-prefix = "ASRC1"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = + <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = + <&xbar_asrc_out6_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + port@14 { + reg = <0x14>; + + xbar_admaif20: endpoint { + remote-endpoint = <&admaif20>; + }; + }; + + port@15 { + reg = <0x15>; + + xbar_admaif21: endpoint { + remote-endpoint = <&admaif21>; + }; + }; + + port@16 { + reg = <0x16>; + + xbar_admaif22: endpoint { + remote-endpoint = <&admaif22>; + }; + }; + + port@17 { + reg = <0x17>; + + xbar_admaif23: endpoint { + remote-endpoint = <&admaif23>; + }; + }; + + port@18 { + reg = <0x18>; + + xbar_admaif24: endpoint { + remote-endpoint = <&admaif24>; + }; + }; + + port@19 { + reg = <0x19>; + + xbar_admaif25: endpoint { + remote-endpoint = <&admaif25>; + }; + }; + + port@1a { + reg = <0x1a>; + + xbar_admaif26: endpoint { + remote-endpoint = <&admaif26>; + }; + }; + + port@1b { + reg = <0x1b>; + + xbar_admaif27: endpoint { + remote-endpoint = <&admaif27>; + }; + }; + + port@1c { + reg = <0x1c>; + + xbar_admaif28: endpoint { + remote-endpoint = <&admaif28>; + }; + }; + + port@1d { + reg = <0x1d>; + + xbar_admaif29: endpoint { + remote-endpoint = <&admaif29>; + }; + }; + + port@1e { + reg = <0x1e>; + + xbar_admaif30: endpoint { + remote-endpoint = <&admaif30>; + }; + }; + + port@1f { + reg = <0x1f>; + + xbar_admaif31: endpoint { + remote-endpoint = <&admaif31>; + }; + }; + + xbar_i2s1_port: port@20 { + reg = <0x20>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@21 { + reg = <0x21>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s3_port: port@22 { + reg = <0x22>; + + xbar_i2s3: endpoint { + remote-endpoint = <&i2s3_cif>; + }; + }; + + xbar_i2s4_port: port@23 { + reg = <0x23>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s5_port: port@24 { + reg = <0x24>; + + xbar_i2s5: endpoint { + remote-endpoint = <&i2s5_cif>; + }; + }; + + xbar_i2s6_port: port@25 { + reg = <0x25>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_i2s7_port: port@26 { + reg = <0x26>; + + xbar_i2s7: endpoint { + remote-endpoint = <&i2s7_cif>; + }; + }; + + xbar_i2s8_port: port@27 { + reg = <0x27>; + + xbar_i2s8: endpoint { + remote-endpoint = <&i2s8_cif>; + }; + }; + + xbar_dmic1_port: port@28 { + reg = <0x28>; + + xbar_dmic1: endpoint { + remote-endpoint = <&dmic1_cif>; + }; + }; + + xbar_dmic2_port: port@29 { + reg = <0x29>; + + xbar_dmic2: endpoint { + remote-endpoint = <&dmic2_cif>; + }; + }; + + xbar_dspk1_port: port@2a { + reg = <0x2a>; + + xbar_dspk1: endpoint { + remote-endpoint = <&dspk1_cif>; + }; + }; + + xbar_sfc1_in_port: port@2b { + reg = <0x2b>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@2c { + reg = <0x2c>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@2d { + reg = <0x2d>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@2e { + reg = <0x2e>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@2f { + reg = <0x2f>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@31 { + reg = <0x31>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@32 { + reg = <0x32>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@33 { + reg = <0x33>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@34 { + reg = <0x34>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@35 { + reg = <0x35>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@36 { + reg = <0x36>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@37 { + reg = <0x37>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@38 { + reg = <0x38>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@39 { + reg = <0x39>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@3a { + reg = <0x3a>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@3b { + reg = <0x3b>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@3c { + reg = <0x3c>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@3d { + reg = <0x3d>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@3e { + reg = <0x3e>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@3f { + reg = <0x3f>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@40 { + reg = <0x40>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@41 { + reg = <0x41>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@42 { + reg = <0x42>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@43 { + reg = <0x43>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@44 { + reg = <0x44>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@45 { + reg = <0x45>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@46 { + reg = <0x46>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@47 { + reg = <0x47>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@48 { + reg = <0x48>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@49 { + reg = <0x49>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@4a { + reg = <0x4a>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_amx5_in1_port: port@4b { + reg = <0x4b>; + + xbar_amx5_in1: endpoint { + remote-endpoint = <&amx5_in1>; + }; + }; + + xbar_amx5_in2_port: port@4c { + reg = <0x4c>; + + xbar_amx5_in2: endpoint { + remote-endpoint = <&amx5_in2>; + }; + }; + + xbar_amx5_in3_port: port@4d { + reg = <0x4d>; + + xbar_amx5_in3: endpoint { + remote-endpoint = <&amx5_in3>; + }; + }; + + xbar_amx5_in4_port: port@4e { + reg = <0x4e>; + + xbar_amx5_in4: endpoint { + remote-endpoint = <&amx5_in4>; + }; + }; + + port@4f { + reg = <0x4f>; + + xbar_amx5_out: endpoint { + remote-endpoint = <&amx5_out>; + }; + }; + + xbar_amx6_in1_port: port@50 { + reg = <0x50>; + + xbar_amx6_in1: endpoint { + remote-endpoint = <&amx6_in1>; + }; + }; + + xbar_amx6_in2_port: port@51 { + reg = <0x51>; + + xbar_amx6_in2: endpoint { + remote-endpoint = <&amx6_in2>; + }; + }; + + xbar_amx6_in3_port: port@52 { + reg = <0x52>; + + xbar_amx6_in3: endpoint { + remote-endpoint = <&amx6_in3>; + }; + }; + + xbar_amx6_in4_port: port@53 { + reg = <0x53>; + + xbar_amx6_in4: endpoint { + remote-endpoint = <&amx6_in4>; + }; + }; + + port@54 { + reg = <0x54>; + + xbar_amx6_out: endpoint { + remote-endpoint = <&amx6_out>; + }; + }; + + xbar_adx1_in_port: port@55 { + reg = <0x55>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@56 { + reg = <0x56>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@57 { + reg = <0x57>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@58 { + reg = <0x58>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@59 { + reg = <0x59>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@5a { + reg = <0x5a>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@5b { + reg = <0x5b>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@5c { + reg = <0x5c>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@5d { + reg = <0x5d>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@5f { + reg = <0x5f>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@63 { + reg = <0x63>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@64 { + reg = <0x64>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@65 { + reg = <0x65>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@67 { + reg = <0x67>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_adx5_in_port: port@69 { + reg = <0x69>; + + xbar_adx5_in: endpoint { + remote-endpoint = <&adx5_in>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_adx5_out1: endpoint { + remote-endpoint = <&adx5_out1>; + }; + }; + + port@6b { + reg = <0x6b>; + + xbar_adx5_out2: endpoint { + remote-endpoint = <&adx5_out2>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_adx5_out3: endpoint { + remote-endpoint = <&adx5_out3>; + }; + }; + + port@6d { + reg = <0x6d>; + + xbar_adx5_out4: endpoint { + remote-endpoint = <&adx5_out4>; + }; + }; + + xbar_adx6_in_port: port@6e { + reg = <0x6e>; + + xbar_adx6_in: endpoint { + remote-endpoint = <&adx6_in>; + }; + }; + + port@6f { + reg = <0x6f>; + + xbar_adx6_out1: endpoint { + remote-endpoint = <&adx6_out1>; + }; + }; + + port@70 { + reg = <0x70>; + + xbar_adx6_out2: endpoint { + remote-endpoint = <&adx6_out2>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_adx6_out3: endpoint { + remote-endpoint = <&adx6_out3>; + }; + }; + + port@72 { + reg = <0x72>; + + xbar_adx6_out4: endpoint { + remote-endpoint = <&adx6_out4>; + }; + }; + + xbar_mix_in1_port: port@73 { + reg = <0x73>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@74 { + reg = <0x74>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@75 { + reg = <0x75>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@76 { + reg = <0x76>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@77 { + reg = <0x77>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@78 { + reg = <0x78>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@79 { + reg = <0x79>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@7a { + reg = <0x7a>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@7b { + reg = <0x7b>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@7c { + reg = <0x7c>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@7d { + reg = <0x7d>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@7e { + reg = <0x7e>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@7f { + reg = <0x7f>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@80 { + reg = <0x80>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@81 { + reg = <0x81>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@82 { + reg = <0x82>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@83 { + reg = <0x83>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@84 { + reg = <0x84>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@85 { + reg = <0x85>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@86 { + reg = <0x86>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@87 { + reg = <0x87>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@88 { + reg = <0x88>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@89 { + reg = <0x89>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@8a { + reg = <0x8a>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@8b { + reg = <0x8b>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@8c { + reg = <0x8c>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@8d { + reg = <0x8d>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@8e { + reg = <0x8e>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@8f { + reg = <0x8f>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@90 { + reg = <0x90>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + }; + }; + + agic_page0: interrupt-controller@9960000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9961000 0x0 0x1000>, + <0x0 0x9962000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page1: interrupt-controller@9970000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9971000 0x0 0x1000>, + <0x0 0x9972000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page2: interrupt-controller@9980000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9981000 0x0 0x1000>, + <0x0 0x9982000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page3: interrupt-controller@9990000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x9991000 0x0 0x1000>, + <0x0 0x9992000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page4: interrupt-controller@99a0000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x99a1000 0x0 0x1000>, + <0x0 0x99a2000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + + agic_page5: interrupt-controller@99b0000 { + compatible = "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x99b1000 0x0 0x1000>, + <0x0 0x99b2000 0x0 0x1000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_ADSP>; + clock-names = "clk"; + status = "disabled"; + }; + }; + gpcdma: dma-controller@8400000 { compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; reg = <0x0 0x08400000 0x0 0x210000>; @@ -542,6 +3700,22 @@ #iommu-cells = <1>; dma-coherent; }; + + hda@90b0000 { + compatible = "nvidia,tegra264-hda"; + reg = <0x0 0x90b0000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; + clock-names = "hda"; + resets = <&bpmp TEGRA264_RESET_HDA>, + <&bpmp TEGRA264_RESET_HDACODEC>; + reset-names = "hda", "hda2codec_2x"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu3 TEGRA264_SID_HDA>; + status = "disabled"; + }; }; /* UPHY MMIO */ @@ -625,6 +3799,22 @@ method = "smc"; }; + sound { + compatible = "nvidia,tegra264-audio-graph-card"; + + clocks = <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>, + <&bpmp TEGRA264_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + + status = "disabled"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , diff --git a/dts/upstream/src/arm64/qcom/qcm2290.dtsi b/dts/upstream/src/arm64/qcom/agatti.dtsi similarity index 93% rename from dts/upstream/src/arm64/qcom/qcm2290.dtsi rename to dts/upstream/src/arm64/qcom/agatti.dtsi index 08141b41de2..8bf5c5583fc 100644 --- a/dts/upstream/src/arm64/qcom/qcm2290.dtsi +++ b/dts/upstream/src/arm64/qcom/agatti.dtsi @@ -17,6 +17,9 @@ #include #include #include +#include +#include +#include / { interrupt-parent = <&intc>; @@ -552,6 +555,13 @@ bias-disable; }; + qup_uart1_default: qup-uart1-default-state { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-disable; + }; + qup_uart3_default: qup-uart3-default-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "qup3"; @@ -566,6 +576,13 @@ bias-disable; }; + qup_uart5_default: qup-uart5-default-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-disable; + }; + cci0_default: cci0-default-state { pins = "gpio22", "gpio23"; function = "cci_i2c"; @@ -671,6 +688,43 @@ }; }; + lpass_tlmm: pinctrl@a7c0000 { + compatible = "qcom,qcm2290-lpass-lpi-pinctrl", + "qcom,sm6115-lpass-lpi-pinctrl"; + reg = <0x0 0x0a7c0000 0x0 0x20000>, + <0x0 0x0a950000 0x0 0x10000>; + + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 19>; + + lpi_i2s2_active: lpi-i2s2-active-state { + sck-pins { + pins = "gpio10"; + function = "i2s2_clk"; + bias-disable; + drive-strength = <8>; + }; + + ws-pins { + pins = "gpio11"; + function = "i2s2_ws"; + bias-disable; + drive-strength = <8>; + }; + + data-pins { + pins = "gpio12"; + function = "i2s2_data"; + bias-disable; + drive-strength = <8>; + }; + }; + }; + gcc: clock-controller@1400000 { compatible = "qcom,gcc-qcm2290"; reg = <0x0 0x01400000 0x0 0x1f0000>; @@ -1197,6 +1251,23 @@ status = "disabled"; }; + uart1: serial@4a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + status = "disabled"; + }; + i2c2: i2c@4a88000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x04a88000 0x0 0x4000>; @@ -1302,7 +1373,7 @@ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG - &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; @@ -1418,6 +1489,23 @@ #size-cells = <0>; status = "disabled"; }; + + uart5: serial@4a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart5_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + status = "disabled"; + }; }; usb: usb@4ef8800 { @@ -1537,7 +1625,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; @@ -1685,25 +1773,25 @@ }; }; - camss: camss@5c6e000 { + camss: camss@5c11000 { compatible = "qcom,qcm2290-camss"; - reg = <0x0 0x5c6e000 0x0 0x1000>, + reg = <0x0 0x5c11000 0x0 0x1000>, + <0x0 0x5c6e000 0x0 0x1000>, <0x0 0x5c75000 0x0 0x1000>, <0x0 0x5c52000 0x0 0x1000>, <0x0 0x5c53000 0x0 0x1000>, <0x0 0x5c66000 0x0 0x400>, <0x0 0x5c68000 0x0 0x400>, - <0x0 0x5c11000 0x0 0x1000>, <0x0 0x5c6f000 0x0 0x4000>, <0x0 0x5c76000 0x0 0x4000>; - reg-names = "csid0", + reg-names = "top", + "csid0", "csid1", "csiphy0", "csiphy1", "csitpg0", "csitpg1", - "top", "vfe0", "vfe1"; @@ -2077,6 +2165,76 @@ label = "lpass"; qcom,remote-pid = <2>; mboxes = <&apcs_glb 8>; + + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + reg = ; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1c1 0x0>; + + dai@0 { + reg = ; + }; + + dai@1 { + reg = ; + }; + + dai@2 { + reg = ; + }; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; }; }; diff --git a/dts/upstream/src/arm64/qcom/apq8096-db820c.dts b/dts/upstream/src/arm64/qcom/apq8096-db820c.dts index 5b2e88915c2..9fa70ff6887 100644 --- a/dts/upstream/src/arm64/qcom/apq8096-db820c.dts +++ b/dts/upstream/src/arm64/qcom/apq8096-db820c.dts @@ -203,6 +203,10 @@ status = "okay"; }; +&gpu_zap_shader { + firmware-name = "qcom/apq8096/a530_zap.mbn"; +}; + &hsusb_phy1 { status = "okay"; diff --git a/dts/upstream/src/arm64/qcom/hamoa-iot-evk.dts b/dts/upstream/src/arm64/qcom/hamoa-iot-evk.dts index df8d6e5c1f4..36dd6599402 100644 --- a/dts/upstream/src/arm64/qcom/hamoa-iot-evk.dts +++ b/dts/upstream/src/arm64/qcom/hamoa-iot-evk.dts @@ -743,20 +743,32 @@ }; &lpass_tlmm { - spkr_01_sd_n_active: spkr-01-sd-n-active-state { + spkr_0_sd_n_active: spkr-0-sd-n-active-state { pins = "gpio12"; function = "gpio"; drive-strength = <16>; bias-disable; - output-low; }; - spkr_23_sd_n_active: spkr-23-sd-n-active-state { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio13"; function = "gpio"; drive-strength = <16>; bias-disable; - output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_3_sd_n_active: spkr-3-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; }; }; @@ -908,12 +920,14 @@ &swr0 { status = "okay"; - pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-0 = <&wsa_swr_active>; pinctrl-names = "default"; /* WSA8845, Left Woofer */ left_woofer: speaker@0,0 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_0_sd_n_active>; + pinctrl-names = "default"; reg = <0 0>; reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; @@ -926,8 +940,10 @@ /* WSA8845, Left Tweeter */ left_tweeter: speaker@0,1 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; reg = <0 1>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TweeterLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -961,14 +977,16 @@ &swr3 { status = "okay"; - pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-0 = <&wsa2_swr_active>; pinctrl-names = "default"; /* WSA8845, Right Woofer */ right_woofer: speaker@0,0 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; reg = <0 0>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -979,8 +997,10 @@ /* WSA8845, Right Tweeter */ right_tweeter: speaker@0,1 { compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_3_sd_n_active>; + pinctrl-names = "default"; reg = <0 1>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TweeterRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; diff --git a/dts/upstream/src/arm64/qcom/hamoa-iot-som.dtsi b/dts/upstream/src/arm64/qcom/hamoa-iot-som.dtsi index 1aead50b892..4a69852e917 100644 --- a/dts/upstream/src/arm64/qcom/hamoa-iot-som.dtsi +++ b/dts/upstream/src/arm64/qcom/hamoa-iot-som.dtsi @@ -3,8 +3,8 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" #include #include @@ -451,8 +451,7 @@ }; &tlmm { - gpio-reserved-ranges = <34 2>, /* TPM LP & INT */ - <44 4>; /* SPI (TPM) */ + gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ pcie4_default: pcie4-default-state { clkreq-n-pins { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi b/dts/upstream/src/arm64/qcom/hamoa-pmics.dtsi similarity index 96% rename from dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi rename to dts/upstream/src/arm64/qcom/hamoa-pmics.dtsi index 621890ada15..6a31a0adf8b 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi +++ b/dts/upstream/src/arm64/qcom/hamoa-pmics.dtsi @@ -240,6 +240,26 @@ }; }; + pmk8550_sdam_15: nvram@7e00 { + compatible = "qcom,spmi-sdam"; + reg = <0x7e00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7e00 0x100>; + + charge_limit_en: charge-limit-en@73 { + reg = <0x73 0x1>; + }; + + charge_limit_end: charge-limit-end@75 { + reg = <0x75 0x1>; + }; + + charge_limit_delta: charge-limit-delta@76 { + reg = <0x76 0x1>; + }; + }; + pmk8550_gpios: gpio@8800 { compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg = <0xb800>; diff --git a/dts/upstream/src/arm64/qcom/x1e80100.dtsi b/dts/upstream/src/arm64/qcom/hamoa.dtsi similarity index 98% rename from dts/upstream/src/arm64/qcom/x1e80100.dtsi rename to dts/upstream/src/arm64/qcom/hamoa.dtsi index 51576d9c935..a17900eacb2 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100.dtsi +++ b/dts/upstream/src/arm64/qcom/hamoa.dtsi @@ -75,7 +75,6 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; l2_0: l2-cache { compatible = "cache"; @@ -92,7 +91,6 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu2: cpu@200 { @@ -103,7 +101,6 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu3: cpu@300 { @@ -114,7 +111,6 @@ next-level-cache = <&l2_0>; power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu4: cpu@10000 { @@ -125,7 +121,6 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; l2_1: l2-cache { compatible = "cache"; @@ -142,7 +137,6 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu6: cpu@10200 { @@ -153,7 +147,6 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu7: cpu@10300 { @@ -164,7 +157,6 @@ next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu8: cpu@20000 { @@ -175,7 +167,6 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; l2_2: l2-cache { compatible = "cache"; @@ -192,7 +183,6 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu10: cpu@20200 { @@ -203,7 +193,6 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu11: cpu@20300 { @@ -214,7 +203,6 @@ next-level-cache = <&l2_2>; power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; - cpu-idle-states = <&cluster_c4>; }; cpu-map { @@ -371,61 +359,73 @@ cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; + domain-idle-states = <&cluster_c4>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; + domain-idle-states = <&cluster_c4>; }; cpu_pd8: power-domain-cpu8 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cpu_pd9: power-domain-cpu9 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cpu_pd10: power-domain-cpu10 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cpu_pd11: power-domain-cpu11 { #power-domain-cells = <0>; power-domains = <&cluster_pd2>; + domain-idle-states = <&cluster_c4>; }; cluster_pd0: power-domain-cpu-cluster0 { @@ -807,7 +807,34 @@ <0>, <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, - <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; @@ -3240,74 +3267,132 @@ pcie3_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 1 x4 and GEN 2 x2 */ - opp-10000000 { + /* 2.5 GT/s x4 */ + opp-10000000-1 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <1>; }; - /* GEN 1 x8 and GEN 2 x4 */ - opp-20000000 { + /* 2.5 GT/s x8 */ + opp-20000000-1 { opp-hz = /bits/ 64 <20000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <2000000 1>; + opp-level = <1>; }; - /* GEN 2 x8 */ - opp-40000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x8 */ + opp-40000000-2 { opp-hz = /bits/ 64 <40000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <4000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 3 x4 and GEN 4 x2 */ - opp-32000000 { + /* 8 GT/s x4 */ + opp-32000000-3 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <3938000 1>; + opp-level = <3>; }; - /* GEN 3 x8 and GEN 4 x4 */ - opp-64000000 { + /* 8 GT/s x8 */ + opp-64000000-3 { opp-hz = /bits/ 64 <64000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <7876000 1>; + opp-level = <3>; }; - /* GEN 4 x8 */ - opp-128000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x8 */ + opp-128000000-4 { opp-hz = /bits/ 64 <128000000>; required-opps = <&rpmhpd_opp_svs>; opp-peak-kBps = <15753000 1>; + opp-level = <4>; }; }; @@ -4922,6 +5007,7 @@ interconnect-names = "usb-ddr", "apps-usb"; + qcom,select-utmi-as-pipe-clk; wakeup-source; status = "disabled"; @@ -4939,15 +5025,8 @@ dma-coherent; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_2_dwc3_hs: endpoint { - }; + port { + usb_2_dwc3_hs: endpoint { }; }; }; @@ -5466,7 +5545,7 @@ compatible = "qcom,x1e80100-dp"; reg = <0 0x0ae90000 0 0x200>, <0 0x0ae90200 0 0x200>, - <0 0x0ae90400 0 0x600>, + <0 0x0ae90400 0 0xc00>, <0 0x0ae91000 0 0x400>, <0 0x0ae91400 0 0x400>; @@ -5554,7 +5633,7 @@ compatible = "qcom,x1e80100-dp"; reg = <0 0x0ae98000 0 0x200>, <0 0x0ae98200 0 0x200>, - <0 0x0ae98400 0 0x600>, + <0 0x0ae98400 0 0xc00>, <0 0x0ae99000 0 0x400>, <0 0x0ae99400 0 0x400>; @@ -5642,7 +5721,7 @@ compatible = "qcom,x1e80100-dp"; reg = <0 0x0ae9a000 0 0x200>, <0 0x0ae9a200 0 0x200>, - <0 0x0ae9a400 0 0x600>, + <0 0x0ae9a400 0 0xc00>, <0 0x0ae9b000 0 0x400>, <0 0x0ae9b400 0 0x400>; @@ -5729,7 +5808,7 @@ compatible = "qcom,x1e80100-dp"; reg = <0 0x0aea0000 0 0x200>, <0 0x0aea0200 0 0x200>, - <0 0x0aea0400 0 0x600>, + <0 0x0aea0400 0 0xc00>, <0 0x0aea1000 0 0x400>, <0 0x0aea1400 0 0x400>; diff --git a/dts/upstream/src/arm64/qcom/ipq5424.dtsi b/dts/upstream/src/arm64/qcom/ipq5424.dtsi index ef2b52f3597..eb393f3fd72 100644 --- a/dts/upstream/src/arm64/qcom/ipq5424.dtsi +++ b/dts/upstream/src/arm64/qcom/ipq5424.dtsi @@ -3,7 +3,7 @@ * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -13,6 +13,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -57,6 +58,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -82,6 +84,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_100: l2-cache { compatible = "cache"; @@ -101,6 +104,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_200: l2-cache { compatible = "cache"; @@ -120,6 +124,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + #cooling-cells = <2>; l2_300: l2-cache { compatible = "cache"; @@ -213,7 +218,7 @@ }; tfa@8a832000 { - reg = <0x0 0x8a832000 0x0 0x7d000>; + reg = <0x0 0x8a832000 0x0 0x80000>; no-map; status = "disabled"; }; @@ -815,6 +820,36 @@ #interconnect-cells = <1>; }; + clock-controller@39b00000 { + compatible = "qcom,ipq5424-nsscc"; + reg = <0 0x39b00000 0 0x100000>; + clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>, + <&cmn_pll IPQ5424_NSS_300MHZ_CLK>, + <&cmn_pll IPQ5424_PPE_375MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss", + "ppe", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus"; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; + pcie3: pcie@40000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x40000000 0x0 0xf1c>, @@ -1235,18 +1270,28 @@ thermal-sensors = <&tsens 14>; trips { - cpu-critical { + cpu0_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu0_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -1254,18 +1299,28 @@ thermal-sensors = <&tsens 12>; trips { - cpu-critical { + cpu1_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu1_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -1273,18 +1328,28 @@ thermal-sensors = <&tsens 11>; trips { - cpu-critical { + cpu2_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu2_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -1292,18 +1357,28 @@ thermal-sensors = <&tsens 13>; trips { - cpu-critical { + cpu3_crit: cpu-critical { temperature = <120000>; hysteresis = <9000>; type = "critical"; }; - cpu-passive { + cpu3_alert: cpu-passive { temperature = <110000>; hysteresis = <9000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; wcss-tile2-thermal { diff --git a/dts/upstream/src/arm64/qcom/sc7280.dtsi b/dts/upstream/src/arm64/qcom/kodiak.dtsi similarity index 97% rename from dts/upstream/src/arm64/qcom/sc7280.dtsi rename to dts/upstream/src/arm64/qcom/kodiak.dtsi index 4b04dea57ec..c2ccbb67f80 100644 --- a/dts/upstream/src/arm64/qcom/sc7280.dtsi +++ b/dts/upstream/src/arm64/qcom/kodiak.dtsi @@ -3338,6 +3338,86 @@ }; }; + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x06004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1c { + reg = <0x1c>; + + qdss_tpda_in28: endpoint { + remote-endpoint = <&spdm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = <&qdss_dl_funnel_in0>; + }; + }; + }; + }; + + funnel@6005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x06005000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_dl_funnel_in0: endpoint { + remote-endpoint = <&qdss_tpda_out>; + }; + }; + }; + + out-ports { + port { + qdss_dl_funnel_out: endpoint { + remote-endpoint = <&funnel0_in6>; + }; + }; + }; + }; + + tpdm@600f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x0600f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + spdm_tpdm_out: endpoint { + remote-endpoint = <&qdss_tpda_in28>; + }; + }; + }; + }; + + cti@6010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06010000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; @@ -3357,6 +3437,14 @@ #address-cells = <1>; #size-cells = <0>; + port@6 { + reg = <6>; + + funnel0_in6: endpoint { + remote-endpoint = <&qdss_dl_funnel_out>; + }; + }; + port@7 { reg = <7>; funnel0_in7: endpoint { @@ -3471,6 +3559,38 @@ }; }; + cti@6b00000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b00000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@6b01000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b01000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@6b02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b02000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + cti@6b03000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b03000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + funnel@6b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06b04000 0 0x1000>; @@ -3490,6 +3610,14 @@ #address-cells = <1>; #size-cells = <0>; + port@6 { + reg = <6>; + + swao_funnel_in6: endpoint { + remote-endpoint = <&aoss_tpda_out>; + }; + }; + port@7 { reg = <7>; swao_funnel_in: endpoint { @@ -3548,6 +3676,170 @@ }; }; + tpda@6b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x06b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint = <&swao_prio0_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint = <&swao_prio1_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint = <&swao_prio2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint = <&swao_prio3_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint = <&swao_tpdm_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = <&swao_funnel_in6>; + }; + }; + }; + }; + + tpdm@6b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio0_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@6b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio1_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@6b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio2_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@6b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + swao_prio3_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@6b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x06b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + swao_tpdm_out: endpoint { + remote-endpoint = <&aoss_tpda_in4>; + }; + }; + }; + }; + + cti@6b11000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x06b11000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; @@ -3885,6 +4177,12 @@ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sc7280-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x84>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sc7280-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -5074,6 +5372,8 @@ phys = <&mdss_dsi_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/qcom/lemans-evk-camera.dtso b/dts/upstream/src/arm64/qcom/lemans-evk-camera.dtso new file mode 100644 index 00000000000..4600d5441cc --- /dev/null +++ b/dts/upstream/src/arm64/qcom/lemans-evk-camera.dtso @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * Camera Sensor overlay on top of leman evk core kit. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vreg_cam1_1p8: vreg_cam1_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1_1p8"; + startup-delay-us = <10000>; + enable-active-high; + gpio = <&pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&camcc { + status = "okay"; +}; + +&camss { + vdda-pll-supply = <&vreg_l1c>; + vdda-phy-supply = <&vreg_l4a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 = <&cci1_0_default>; + pinctrl-1 = <&cci1_0_sleep>; + + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam1_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vreg_s4a>; + avdd-supply = <&vreg_cam1_1p8>; + + port { + imx577_ep1: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio73"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + rst-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/dts/upstream/src/arm64/qcom/lemans-evk.dts b/dts/upstream/src/arm64/qcom/lemans-evk.dts index c7dc9b8f445..b40fa203e4a 100644 --- a/dts/upstream/src/arm64/qcom/lemans-evk.dts +++ b/dts/upstream/src/arm64/qcom/lemans-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include @@ -501,6 +502,20 @@ }; }; +&i2c19 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; +}; + &iris { firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn"; @@ -587,15 +602,28 @@ status = "okay"; }; +&pmm8654au_0_pon_resin { + linux,code = ; + status = "okay"; +}; + +&qup_i2c19_default { + drive-strength = <2>; + bias-pull-up; +}; + &qupv3_id_0 { + firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; }; &qupv3_id_1 { + firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; }; &qupv3_id_2 { + firmware-name = "qcom/sa8775p/qupv3fw.elf"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/qcom/lemans-pmics.dtsi b/dts/upstream/src/arm64/qcom/lemans-pmics.dtsi index 1369c3d43f8..341119fc824 100644 --- a/dts/upstream/src/arm64/qcom/lemans-pmics.dtsi +++ b/dts/upstream/src/arm64/qcom/lemans-pmics.dtsi @@ -132,6 +132,15 @@ }; }; + pmm8654au_0_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, + <0x6200>; + reg-names = "rtc", + "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + pmm8654au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; diff --git a/dts/upstream/src/arm64/qcom/lemans.dtsi b/dts/upstream/src/arm64/qcom/lemans.dtsi index cf685cb186e..0b154d57ba2 100644 --- a/dts/upstream/src/arm64/qcom/lemans.dtsi +++ b/dts/upstream/src/arm64/qcom/lemans.dtsi @@ -3901,6 +3901,32 @@ status = "disabled"; }; + usb_1_hsphy: phy@88e6000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e6000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2_hsphy: phy@88e7000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e7000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB3_PHY_TERT_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + usb_0_qmpphy: phy@88e8000 { compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; reg = <0 0x088e8000 0 0x2000>; @@ -3925,6 +3951,36 @@ status = "disabled"; }; + usb_1_qmpphy: phy@88ea000 { + compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; + reg = <0 0x088ea000 0 0x2000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "pipe"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy", "phy_phy"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb3_sec_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + refgen: regulator@891c000 { + compatible = "qcom,sa8775p-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0891c000 0x0 0x84>; + }; + usb_0: usb@a600000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a600000 0 0xfc100>; @@ -3973,43 +4029,6 @@ status = "disabled"; }; - usb_1_hsphy: phy@88e6000 { - compatible = "qcom,sa8775p-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg = <0 0x088e6000 0 0x120>; - clocks = <&gcc GCC_USB_CLKREF_EN>; - clock-names = "ref"; - resets = <&gcc GCC_USB2_PHY_SEC_BCR>; - - #phy-cells = <0>; - - status = "disabled"; - }; - - usb_1_qmpphy: phy@88ea000 { - compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; - reg = <0 0x088ea000 0 0x2000>; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&gcc GCC_USB_CLKREF_EN>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "aux", "ref", "com_aux", "pipe"; - - resets = <&gcc GCC_USB3_PHY_SEC_BCR>, - <&gcc GCC_USB3PHY_PHY_SEC_BCR>; - reset-names = "phy", "phy_phy"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - #clock-cells = <0>; - clock-output-names = "usb3_sec_phy_pipe_clk_src"; - - #phy-cells = <0>; - - status = "disabled"; - }; - usb_1: usb@a800000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a800000 0 0xfc100>; @@ -4058,19 +4077,6 @@ status = "disabled"; }; - usb_2_hsphy: phy@88e7000 { - compatible = "qcom,sa8775p-usb-hs-phy", - "qcom,usb-snps-hs-5nm-phy"; - reg = <0 0x088e7000 0 0x120>; - clocks = <&gcc GCC_USB_CLKREF_EN>; - clock-names = "ref"; - resets = <&gcc GCC_USB3_PHY_TERT_BCR>; - - #phy-cells = <0>; - - status = "disabled"; - }; - usb_2: usb@a400000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a400000 0 0xfc100>; @@ -4106,6 +4112,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; interconnect-names = "usb-ddr", "apps-usb"; + qcom,select-utmi-as-pipe-clk; wakeup-source; iommus = <&apps_smmu 0x020 0x0>; @@ -4899,6 +4906,8 @@ operating-points-v2 = <&mdss_dsi_opp_table>; power-domains = <&rpmhpd SA8775P_MMCX>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; @@ -4981,6 +4990,8 @@ operating-points-v2 = <&mdss_dsi_opp_table>; power-domains = <&rpmhpd SA8775P_MMCX>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; @@ -6812,11 +6823,12 @@ "ptp_ref", "phyaux"; - interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "mac-mem", "cpu-mac"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", + "mac-mem"; power-domains = <&gcc EMAC1_GDSC>; @@ -6853,11 +6865,12 @@ "ptp_ref", "phyaux"; - interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "mac-mem", "cpu-mac"; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", + "mac-mem"; power-domains = <&gcc EMAC0_GDSC>; diff --git a/dts/upstream/src/arm64/qcom/monaco-evk.dts b/dts/upstream/src/arm64/qcom/monaco-evk.dts index e72cf6725a5..bb35893da73 100644 --- a/dts/upstream/src/arm64/qcom/monaco-evk.dts +++ b/dts/upstream/src/arm64/qcom/monaco-evk.dts @@ -9,8 +9,8 @@ #include #include -#include "qcs8300.dtsi" -#include "qcs8300-pmics.dtsi" +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. Monaco EVK"; @@ -401,10 +401,12 @@ }; &qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; }; &qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/qcom/qcs8300-pmics.dtsi b/dts/upstream/src/arm64/qcom/monaco-pmics.dtsi similarity index 98% rename from dts/upstream/src/arm64/qcom/qcs8300-pmics.dtsi rename to dts/upstream/src/arm64/qcom/monaco-pmics.dtsi index a94b0bfa98d..e990d736771 100644 --- a/dts/upstream/src/arm64/qcom/qcs8300-pmics.dtsi +++ b/dts/upstream/src/arm64/qcom/monaco-pmics.dtsi @@ -18,7 +18,6 @@ reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; - allow-set-time; }; pmm8620au_0_gpios: gpio@8800 { diff --git a/dts/upstream/src/arm64/qcom/qcs8300.dtsi b/dts/upstream/src/arm64/qcom/monaco.dtsi similarity index 99% rename from dts/upstream/src/arm64/qcom/qcs8300.dtsi rename to dts/upstream/src/arm64/qcom/monaco.dtsi index 8d78ccac411..816fa2af8a9 100644 --- a/dts/upstream/src/arm64/qcom/qcs8300.dtsi +++ b/dts/upstream/src/arm64/qcom/monaco.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -4294,6 +4295,12 @@ status = "disabled"; }; + refgen: regulator@891c000 { + compatible = "qcom,qcs8300-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0891c000 0x0 0x84>; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-623.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, diff --git a/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts b/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts index 887764dc55b..93d5ea279cf 100644 --- a/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts +++ b/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts @@ -79,6 +79,19 @@ }; }; + reg_ts_vcca: regulator-vcca-ts { + compatible = "regulator-fixed"; + regulator-name = "regulator-vcca-ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 78 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&ts_vcca_default>; + pinctrl-names = "default"; + }; + usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; @@ -176,6 +189,25 @@ }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "himax,hx8527e", "himax,hx852es"; + reg = <0x48>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + vcca-supply = <®_ts_vcca>; + vccd-supply = <&pm8916_l6>; + + pinctrl-0 = <&ts_int_reset_default>; + pinctrl-names = "default"; + + linux,keycodes = ; + }; +}; + &blsp_uart2 { status = "okay"; pinctrl-0 = <&blsp_uart2_console_default>; @@ -338,6 +370,20 @@ bias-disable; }; + ts_int_reset_default: ts-int-reset-default-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_vcca_default: ts-vcca-default-state { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi index e7f265e3c2a..e33453c3e51 100644 --- a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi +++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi @@ -5,7 +5,7 @@ /* SM5504 MUIC instead of SM5502 */ /delete-node/ &muic; -/* Touchscreen varies depending on model variant */ +/* IST3038 instead of Zinitix BT541 */ /delete-node/ &touchscreen; &blsp_i2c1 { @@ -24,6 +24,26 @@ }; }; +&blsp_i2c5 { + touchscreen: touchscreen@50 { + compatible = "imagis,ist3038"; + reg = <0x50>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + + vdd-supply = <®_vdd_tsp_a>; + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + + linux,keycodes = ; + }; +}; + /* On rossa backlight is controlled with MIPI DCS commands */ &clk_pwm { status = "disabled"; diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts index 3413b0970c4..1981bb71f6a 100644 --- a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts +++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts @@ -16,26 +16,6 @@ constant-charge-voltage-max-microvolt = <4400000>; }; -&blsp_i2c5 { - touchscreen@50 { - compatible = "imagis,ist3038"; - reg = <0x50>; - - interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; - - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - - vdd-supply = <®_vdd_tsp_a>; - vddio-supply = <&pm8916_l6>; - - pinctrl-0 = <&tsp_int_default>; - pinctrl-names = "default"; - - linux,keycodes = ; - }; -}; - &mpss_mem { /* Firmware for rossa needs more space */ reg = <0x0 0x86800000 0x0 0x5800000>; diff --git a/dts/upstream/src/arm64/qcom/msm8937-xiaomi-land.dts b/dts/upstream/src/arm64/qcom/msm8937-xiaomi-land.dts new file mode 100644 index 00000000000..91837ff940f --- /dev/null +++ b/dts/upstream/src/arm64/qcom/msm8937-xiaomi-land.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Barnabas Czeman + */ +/dts-v1/; + +#include +#include +#include + +#include "msm8937.dtsi" +#include "pm8937.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model = "Xiaomi Redmi 3S (land)"; + compatible = "xiaomi,land", "qcom,msm8937"; + chassis-type = "handset"; + + qcom,msm-id = ; + qcom,board-id = <0x1000b 1>, <0x2000b 1>; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <4100000>; + constant-charge-current-max-microamp = <1000000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@8dd01000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains = <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + key-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + irled { + compatible = "gpio-ir-tx"; + gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; + + reserved-memory { + reserved@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer: memory@8dd01000 { + reg = <0x0 0x8dd01000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + #address-cells = <1>; + #size-cells = <0>; + + vcc-supply = <&pm8937_l10>; + vio-supply = <&pm8937_l5>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_STATUS; + led-max-microamp = <5000>; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + led-max-microamp = <5000>; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + led-max-microamp = <5000>; + color = ; + }; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + touchscreen@3e { + compatible = "edt,edt-ft5306"; + reg = <0x3e>; + + interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + vcc-supply = <&pm8937_l10>; + iovcc-supply = <&pm8937_l5>; + + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; + +&pm8937_resin { + linux,code = ; + + status = "okay"; +}; + +&pm8937_spmi_regulators { + /* APC */ + pm8937_s5: s5 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&pmi8950_wled { + qcom,num-strings = <2>; + qcom,external-pfet; + qcom,current-limit-microamp = <20000>; + qcom,ovp-millivolt = <29600>; + + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + + vdd_l1_l19-supply = <&pm8937_s3>; + vdd_l2_l23-supply = <&pm8937_s3>; + vdd_l3-supply = <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; +}; + +&sdc2_cmd_default { + drive-strength = <12>; +}; + +&sdc2_data_default { + drive-strength = <12>; +}; + +&sdhc_1 { + vmmc-supply = <&pm8937_l8>; + vqmmc-supply = <&pm8937_l5>; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply = <&pm8937_l11>; + vqmmc-supply = <&pm8937_l12>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32768>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <20 4>; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins = "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&wcnss { + vddpx-supply = <&pm8937_l5>; + + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; + vddxo-supply = <&pm8937_l7>; + vddrfa-supply = <&pm8937_l19>; + vddpa-supply = <&pm8937_l9>; + vdddig-supply = <&pm8937_l5>; +}; + +&wcnss_mem { + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; diff --git a/dts/upstream/src/arm64/qcom/msm8937.dtsi b/dts/upstream/src/arm64/qcom/msm8937.dtsi new file mode 100644 index 00000000000..b9362108098 --- /dev/null +++ b/dts/upstream/src/arm64/qcom/msm8937.dtsi @@ -0,0 +1,2133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Dang Huynh + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; + }; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c0>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-unified; + }; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x101>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x102>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x103>; + device_type = "cpu"; + next-level-cache = <&l2_1>; + enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table_c1>; + #cooling-cells = <2>; + }; + + cpu-map { + /* Little Cores */ + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + /* Big Cores */ + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8937", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", + "bus", + "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + device_type = "memory"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + qseecom_mem: reserved@85b00000 { + reg = <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg = <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + rmtfs@92100000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x92100000 0x0 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + + adsp_mem: adsp { + size = <0x0 0x1100000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + mba_mem: mba { + size = <0x0 0x100000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + wcnss_mem: wcnss { + size = <0x0 0x700000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + + venus_mem: venus { + size = <0x0 0x400000>; + alignment = <0x0 0x100000>; + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; + no-map; + status = "disabled"; + }; + }; + + cpu_opp_table_c0: opp-table-c0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + }; + + cpu_opp_table_c1: opp-table-c1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm: remoteproc { + compatible = "qcom,msm8937-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs1 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8937", "qcom,smd-rpm"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8937", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8937-rpmpd", "qcom,msm8917-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apcs1 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs1 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = ; + + mboxes = <&apcs1 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + mboxes = <0>, <&apcs1 13>, <0>, <&apcs1 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + + qfprom: qfprom@a4000 { + compatible = "qcom,msm8937-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@1d8 { + reg = <0x1d8 0x1>; + bits = <0 8>; + }; + + tsens_s5_p1: s5-p1@1d9 { + reg = <0x1d9 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@1d9 { + reg = <0x1d9 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@1da { + reg = <0x1da 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@1db { + reg = <0x1db 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@1dc { + reg = <0x1dc 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@1dc { + reg = <0x1dc 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@1dd { + reg = <0x1dd 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@1de { + reg = <0x1de 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@1df { + reg = <0x1df 0x1>; + bits = <0 8>; + }; + + tsens_mode: mode@210 { + reg = <0x210 0x1>; + bits = <0 3>; + }; + + tsens_s0_p1: s0-p1@210 { + reg = <0x210 0x2>; + bits = <3 6>; + }; + + tsens_s0_p2: s0-p2@211 { + reg = <0x211 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@211 { + reg = <0x211 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@212 { + reg = <0x212 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@213 { + reg = <0x213 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@214 { + reg = <0x214 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@214 { + reg = <0x214 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@215 { + reg = <0x215 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@216 { + reg = <0x216 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@217 { + reg = <0x217 0x1>; + bits = <1 6>; + }; + + tsens_s9_p1: s9-p1@230 { + reg = <0x230 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@230 { + reg = <0x230 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1: s10-p1@231 { + reg = <0x231 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10-p2@232 { + reg = <0x232 0x1>; + bits = <2 6>; + }; + + gpu_speed_bin: gpu-speed-bin@201b { + reg = <0x201b 0x1>; + bits = <7 1>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0006c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", + "ahb", + "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", + "por"; + status = "disabled"; + }; + + rng@e3000 { + compatible = "qcom,prng"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8937-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts = ; + interrupt-names = "uplow"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8917-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1_i2c2_default: blsp1-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_default: blsp1-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_default: blsp1-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c1_default: blsp2-i2c1-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + cs-pins { + pins = "gpio10"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + }; + + blsp1_spi3_sleep: blsp1-spi3-sleep-state { + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + cs0-pins { + pins = "gpio47"; + function = "blsp_spi6"; + drive-strength = <16>; + bias-disable; + }; + + cs1-pins { + pins = "gpio22"; + function = "blsp_spi6"; + drive-strength = <16>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_spi2_sleep: blsp2-spi2-sleep-state { + cs0-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cs1-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + sdc2_cmd_default: cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + sdc2_data_default: data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan-pins { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + + }; + + wcss-wlan0-pins { + pins = "gpio78"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + + }; + + wcss-wlan1-pins { + pins = "gpio77"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + + }; + + wcss-wlan2-pins { + pins = "gpio76"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8937"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; + clock-names = "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8937", "syscon"; + reg = <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names = "mdss_phys", + "vbif_phys"; + ranges; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + mdp: display-controller@1a01000 { + compatible = "qcom,msm8937-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 0x15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x01a94000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&mdss_dsi0_opp_table>; + power-domains = <&rpmpd MSM8937_VDDCX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94400 { + compatible = "qcom,dsi-phy-28nm-8937"; + reg = <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@1a96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x01a96000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc MSM8937_BYTE1_CLK_SRC>, + <&gcc MSM8937_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc MSM8937_GCC_MDSS_BYTE1_CLK>, + <&gcc MSM8937_GCC_MDSS_PCLK1_CLK>, + <&gcc MSM8937_GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys = <&mdss_dsi1_phy>; + + operating-points-v2 = <&mdss_dsi1_opp_table>; + power-domains = <&rpmpd MSM8937_VDDCX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + + mdss_dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible = "qcom,dsi-phy-28nm-8937"; + reg = <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + }; + + gpu: gpu@1c00000 { + compatible = "qcom,adreno-505.0", "qcom,adreno"; + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + #cooling-cells = <2>; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc MSM8937_GCC_OXILI_TIMER_CLK>, + <&gcc MSM8937_GCC_OXILI_AON_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "rbbmtimer", + "alwayson"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&gcc OXILI_GX_GDSC>; + + iommus = <&adreno_smmu 0>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_nom_plus>; + }; + + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + adreno_smmu: iommu@1c40000 { + compatible = "qcom,msm8996-smmu-v2", + "qcom,adreno-smmu", + "qcom,smmu-v2"; + reg = <0x01c40000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + , + , + ; + #iommu-cells = <1>; + + clocks = <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_OXILI_AHB_CLK>; + clock-names = "bus", + "iface"; + + power-domains = <&gcc MSM8937_OXILI_CX_GDSC>; + }; + + apps_iommu: iommu@1e20000 { + compatible = "qcom,msm8937-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x01e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", + "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #iommu-cells = <1>; + #size-cells = <1>; + + /* VFE */ + iommu-ctx@14000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x14000 0x1000>; + interrupts = ; + }; + + /* MDP_0 */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x15000 0x1000>; + interrupts = ; + }; + + /* VENUS_NS */ + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x16000 0x1000>; + interrupts = ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x04044000 0x19000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + + status = "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x500>, + <0x07824000 0x800>; + reg-names = "hc", + "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", + "sleep"; + power-domains = <&rpmpd MSM8937_VDDCX>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x500>, + <0x07864000 0x800>; + reg-names = "hc", + "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", + "sleep"; + power-domains = <&rpmpd MSM8937_VDDCX>; + bus-width = <4>; + status = "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + num-channels = <12>; + qcom,num-ees = <4>; + qcom,ee = <0>; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 2>, + <&blsp1_dma 3>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-names = "default", + "sleep"; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, + <&blsp1_dma 7>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 8>, + <&blsp1_dma 9>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_spi3_default>; + pinctrl-1 = <&blsp1_spi3_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp1_dma 10>, + <&blsp1_dma 11>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp1_i2c4_default>; + pinctrl-1 = <&blsp1_i2c4_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x1d000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + num-channels = <10>; + qcom,num-ees = <4>; + qcom,ee = <0>; + }; + + blsp2_i2c1: i2c@7af5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp2_dma 4>, + <&blsp2_dma 5>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi2: spi@7af6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp2_dma 6>, + <&blsp2_dma 7>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&blsp2_spi2_default>; + pinctrl-1 = <&blsp2_spi2_sleep>; + pinctrl-names = "default", + "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@78db000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", + "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + }; + + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", + "dxe", + "pmu"; + + memory-region = <&wcnss_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + power-domains = <&rpmpd MSM8937_VDDCX>, + <&rpmpd MSM8937_VDDMX>; + power-domain-names = "cx", + "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-0 = <&wcnss_pin_a>; + pinctrl-names = "default"; + + status = "disabled"; + + wcnss_iris: iris { + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + mboxes = <&apcs1 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", + "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs1: mailbox@b011000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + }; + + watchdog@b017000 { + compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg = <0x0b017000 0x1000>; + clocks = <&sleep_clk>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + frame@b121000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + }; + + thermal_zones: thermal-zones { + aoss-thermal { + thermal-sensors = <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + mdm-core-thermal { + thermal-sensors = <&tsens 1>; + + trips { + mdm_core_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + q6-thermal { + thermal-sensors = <&tsens 2>; + + trips { + q6_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors = <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens 4>; + + cooling-maps { + map0 { + trip = <&cpuss1_alert0>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss1_crit: cpuss1-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + thermal-sensors = <&tsens 5>; + + cooling-maps { + map0 { + trip = <&cpu4_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu4_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu4_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + thermal-sensors = <&tsens 6>; + + cooling-maps { + map0 { + trip = <&cpu5_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu5_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu5_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + thermal-sensors = <&tsens 7>; + + cooling-maps { + map0 { + trip = <&cpu6_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu6_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu6_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + thermal-sensors = <&tsens 8>; + + cooling-maps { + map0 { + trip = <&cpu7_alert1>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu7_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu7_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens 9>; + + cooling-maps { + map0 { + trip = <&cpuss0_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss0_crit: cpuss0-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens 10>; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + diff --git a/dts/upstream/src/arm64/qcom/msm8939-asus-z00t.dts b/dts/upstream/src/arm64/qcom/msm8939-asus-z00t.dts new file mode 100644 index 00000000000..ebb548e62e0 --- /dev/null +++ b/dts/upstream/src/arm64/qcom/msm8939-asus-z00t.dts @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8939-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include +#include +#include + +/ { + model = "Asus ZenFone 2 Laser/Selfie (1080p)"; + compatible = "asus,z00t", "qcom,msm8939"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + button-volume-down { + label = "Volume Down"; + gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + reg_sd_vmmc: regulator-sdcard-vmmc { + compatible = "regulator-fixed"; + regulator-name = "sdcard-vmmc"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + + startup-delay-us = <200>; + + pinctrl-0 = <&sd_vmmc_en_default>; + pinctrl-names = "default"; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + + vdd-supply = <&pm8916_l8>; + vid-supply = <&pm8916_l6>; + + reset-gpios = <&tlmm 112 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&mag_reset_default>; + pinctrl-names = "default"; + }; + + imu@68 { + compatible = "invensense,mpu6515"; + reg = <0x68>; + + interrupts-extended = <&tlmm 36 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l8>; + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&imu_default>; + pinctrl-names = "default"; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8916_l8>; + iovcc-supply = <&pm8916_l6>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5500000>; +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,micbias1-ext-cap; + qcom,hphl-jack-type-normally-open; + + status = "okay"; +}; + +&pm8916_vib { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <®_sd_vmmc>; + + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + +&wcnss_mem { + status = "okay"; +}; + +&tlmm { + touchscreen_default: touchscreen-default-state { + reset-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touch-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + imu_default: imu-default-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sd_vmmc_en_default: sd-vmmc-en-default-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + mag_reset_default: mag-reset-default-state { + pins = "gpio112"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/dts/upstream/src/arm64/qcom/msm8996-oneplus3.dts b/dts/upstream/src/arm64/qcom/msm8996-oneplus3.dts index 220eeb31fdc..0bb9e3d8f71 100644 --- a/dts/upstream/src/arm64/qcom/msm8996-oneplus3.dts +++ b/dts/upstream/src/arm64/qcom/msm8996-oneplus3.dts @@ -27,10 +27,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn"; }; &mss_pil { diff --git a/dts/upstream/src/arm64/qcom/msm8996-oneplus3t.dts b/dts/upstream/src/arm64/qcom/msm8996-oneplus3t.dts index f772618e80c..1d7b27c5aff 100644 --- a/dts/upstream/src/arm64/qcom/msm8996-oneplus3t.dts +++ b/dts/upstream/src/arm64/qcom/msm8996-oneplus3t.dts @@ -28,10 +28,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn"; }; &mss_pil { diff --git a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts index bd3f39e1b98..3c6a40212a8 100644 --- a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts +++ b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts @@ -91,10 +91,8 @@ }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; }; &mdss_dsi0 { diff --git a/dts/upstream/src/arm64/qcom/msm8996.dtsi b/dts/upstream/src/arm64/qcom/msm8996.dtsi index c75b522f6eb..9d4ce47578f 100644 --- a/dts/upstream/src/arm64/qcom/msm8996.dtsi +++ b/dts/upstream/src/arm64/qcom/msm8996.dtsi @@ -1333,7 +1333,7 @@ }; }; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; }; @@ -3496,6 +3496,9 @@ <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <60000000>; + interconnects = <&pnoc MASTER_USB_HS &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &pnoc SLAVE_USB_HS>; + interconnect-names = "usb-ddr", "apps-usb"; power-domains = <&gcc USB30_GDSC>; qcom,select-utmi-as-pipe-clk; status = "disabled"; diff --git a/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-natrium.dts b/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-natrium.dts index 443599a5a5d..f8ab03f106a 100644 --- a/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-natrium.dts +++ b/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-natrium.dts @@ -39,10 +39,8 @@ }; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; }; &mdss_dsi0 { diff --git a/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-scorpio.dts b/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-scorpio.dts index 33d84ac541e..1cc33c3123a 100644 --- a/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-scorpio.dts +++ b/dts/upstream/src/arm64/qcom/msm8996pro-xiaomi-scorpio.dts @@ -91,10 +91,8 @@ }; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/scorpio/a530_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/msm8996/scorpio/a530_zap.mbn"; }; &mdp_smmu { diff --git a/dts/upstream/src/arm64/qcom/pmi8950.dtsi b/dts/upstream/src/arm64/qcom/pmi8950.dtsi index 3d3b1cd97cc..5bd91a5cd12 100644 --- a/dts/upstream/src/arm64/qcom/pmi8950.dtsi +++ b/dts/upstream/src/arm64/qcom/pmi8950.dtsi @@ -22,19 +22,19 @@ channel@0 { reg = ; - qcom,pre-scaling = <1 4>; + qcom,pre-scaling = <1 20>; label = "usbin"; }; channel@1 { reg = ; - qcom,pre-scaling = <1 4>; + qcom,pre-scaling = <1 20>; label = "dcin"; }; channel@2 { reg = ; - qcom,pre-scaling = <1 1>; + qcom,pre-scaling = <1 3>; label = "vchg_sns"; }; @@ -55,6 +55,14 @@ qcom,pre-scaling = <1 1>; label = "chg_temp"; }; + + channel@e { + reg = ; + }; + + channel@f { + reg = ; + }; }; pmi8950_mpps: mpps@a000 { diff --git a/dts/upstream/src/arm64/qcom/x1p42100.dtsi b/dts/upstream/src/arm64/qcom/purwa.dtsi similarity index 99% rename from dts/upstream/src/arm64/qcom/x1p42100.dtsi rename to dts/upstream/src/arm64/qcom/purwa.dtsi index 10d26958d3c..2cecd2dd0de 100644 --- a/dts/upstream/src/arm64/qcom/x1p42100.dtsi +++ b/dts/upstream/src/arm64/qcom/purwa.dtsi @@ -3,8 +3,8 @@ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. */ -/* X1P42100 is heavily based on X1E80100, with some meaningful differences */ -#include "x1e80100.dtsi" +/* X1P42100 is heavily based on hamoa, with some meaningful differences */ +#include "hamoa.dtsi" /delete-node/ &bwmon_cluster0; /delete-node/ &cluster_pd2; diff --git a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts index 519e458e1a8..455e5c9bb07 100644 --- a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts +++ b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts @@ -16,7 +16,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" /* PM7350C */ @@ -47,6 +47,8 @@ stride = <(1224 * 4)>; format = "a8r8g8b8"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + vci-supply = <&vreg_oled_vci>; + dvdd-supply = <&vreg_oled_dvdd>; }; }; @@ -193,6 +195,19 @@ pinctrl-names = "default"; }; + vreg_vtof_ldo_2p8: regulator-vtof-ldo-2p8 { + compatible = "regulator-fixed"; + regulator-name = "VTOF_LDO_2P8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <233>; + + gpio = <&tlmm 141 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + reserved-memory { cont_splash_mem: cont-splash@e1000000 { reg = <0x0 0xe1000000 0x0 0x2300000>; @@ -627,6 +642,15 @@ }; &cci0_i2c1 { + camera_imx858_dw9800k: actuator@e { + compatible = "dongwoon,dw9800k"; + reg = <0x0e>; + vdd-supply = <&vreg_afvdd_2p8>; + + dongwoon,sac-mode = <1>; + dongwoon,vcm-prescale = <16>; + }; + /* IMX858 @ 29 */ eeprom@54 { @@ -749,6 +773,8 @@ regulator-name = "vreg_l6p"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1904000>; + /* Pull-up for CCI I2C busses */ + regulator-always-on; }; vreg_l7p: ldo7 { @@ -780,7 +806,16 @@ }; }; - /* AW86927FCR haptics @ 5a */ + vibrator@5a { + compatible = "awinic,aw86927"; + reg = <0x5a>; + + interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&aw86927_int_default>; + pinctrl-names = "default"; + }; }; &i2c2 { @@ -839,6 +874,11 @@ status = "okay"; }; +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &mdss { status = "okay"; }; @@ -1318,6 +1358,13 @@ bias-disable; output-high; }; + + aw86927_int_default: aw86927-int-default-state { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart5 { diff --git a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts index 73fce639370..089a027c57d 100644 --- a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts +++ b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts @@ -13,7 +13,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" diff --git a/dts/upstream/src/arm64/qcom/qcm6490-particle-tachyon.dts b/dts/upstream/src/arm64/qcom/qcm6490-particle-tachyon.dts index 251e72f1142..bf18c485208 100644 --- a/dts/upstream/src/arm64/qcom/qcm6490-particle-tachyon.dts +++ b/dts/upstream/src/arm64/qcom/qcm6490-particle-tachyon.dts @@ -11,7 +11,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" diff --git a/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts index eb8efba1b9d..797f37596bf 100644 --- a/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts +++ b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts @@ -14,7 +14,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" /* PM7350C */ @@ -118,6 +118,11 @@ no-map; }; + removed_mem: removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x5100000>; + no-map; + }; + rmtfs_mem: rmtfs@f8500000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0xf8500000 0x0 0x600000>; @@ -130,8 +135,6 @@ thermal-zones { camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 2>; trips { @@ -144,8 +147,6 @@ }; chg-skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 0>; trips { @@ -158,8 +159,6 @@ }; conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 1>; trips { @@ -172,8 +171,6 @@ }; quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 1>; trips { @@ -186,8 +183,6 @@ }; rear-cam-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 4>; trips { @@ -200,8 +195,6 @@ }; sdm-skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 3>; trips { @@ -214,8 +207,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 0>; trips { @@ -568,6 +559,11 @@ status = "okay"; }; +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &pm7250b_adc { channel@4d { reg = ; @@ -614,6 +610,46 @@ }; }; +&pm8350c_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <2>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm8350c_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &pmk8350_adc_tm { status = "okay"; @@ -857,7 +893,7 @@ &uart7 { /delete-property/interrupts; interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; pinctrl-names = "default", "sleep"; @@ -920,10 +956,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_dp_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c>; vdda18-supply = <&vreg_l1c>; @@ -950,6 +982,16 @@ status = "okay"; }; +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&venus { + firmware-name = "qcom/qcm6490/SHIFT/otter/venus.mbn"; + + status = "okay"; +}; + &wifi { qcom,calibration-variant = "SHIFTphone_8"; diff --git a/dts/upstream/src/arm64/qcom/qcs615-ride.dts b/dts/upstream/src/arm64/qcom/qcs615-ride.dts index 705ea71b07a..be67eb17304 100644 --- a/dts/upstream/src/arm64/qcom/qcs615-ride.dts +++ b/dts/upstream/src/arm64/qcom/qcs615-ride.dts @@ -7,10 +7,10 @@ #include #include #include -#include "sm6150.dtsi" +#include "talos.dtsi" #include "pm8150.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS615 Ride"; + model = "Qualcomm Technologies, Inc. QCS615 Ride (IQ-615 Beta EVK)"; compatible = "qcom,qcs615-ride", "qcom,qcs615", "qcom,sm6150"; chassis-type = "embedded"; @@ -39,6 +39,18 @@ }; }; + dp-dsi0-connector { + compatible = "dp-connector"; + label = "DSI0"; + type = "mini"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint = <&dsi2dp_bridge_out>; + }; + }; + }; + vreg_conn_1p8: regulator-conn-1p8 { compatible = "regulator-fixed"; regulator-name = "vreg_conn_1p8"; @@ -65,6 +77,64 @@ regulator-always-on; }; + vreg_12p0: regulator-vreg-12p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_12P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vreg_1p0: regulator-vreg-1p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + vin-supply = <&vreg_1p8>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_5p0>; + }; + + vreg_3p0: regulator-vreg-3p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_3P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&vreg_12p0>; + }; + + vreg_5p0: regulator-vreg-5p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_5P0"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vreg_12p0>; + }; + wcn6855-pmu { compatible = "qcom,wcn6855-pmu"; @@ -288,6 +358,86 @@ }; }; +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + io_expander: pinctrl@3e { + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupts-extended = <&tlmm 58 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + semtech,probe-reset; + }; + + i2c-mux@77 { + compatible = "nxp,pca9542"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&io_expander 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&vreg_1p0>; + vdd18-supply = <&vreg_1p8>; + vdd33-supply = <&vreg_3p0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_bridge_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_bridge_out: endpoint { + remote-endpoint = <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l11a>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&dsi2dp_bridge_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vcca-supply = <&vreg_l5a>; + status = "okay"; +}; + &pcie { perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; @@ -398,6 +548,7 @@ pins = "gpio98"; function = "gpio"; bias-pull-down; + drive-strength = <16>; output-low; }; }; diff --git a/dts/upstream/src/arm64/qcom/qcs6490-radxa-dragon-q6a.dts b/dts/upstream/src/arm64/qcom/qcs6490-radxa-dragon-q6a.dts new file mode 100644 index 00000000000..bb5a42b038f --- /dev/null +++ b/dts/upstream/src/arm64/qcom/qcs6490-radxa-dragon-q6a.dts @@ -0,0 +1,1095 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include "kodiak.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ +#include "qcs6490-audioreach.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Radxa Dragon Q6A"; + compatible = "radxa,dragon-q6a", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &uart5; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; + + vdd-rxtx-supply = <&vreg_l18b_1p8>; + vdd-io-supply = <&vreg_l18b_1p8>; + vdd-buck-supply = <&vreg_l17b_1p8>; + vdd-mic-bias-supply = <&vreg_bob_3p296>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + qcom,hphl-jack-type-normally-closed; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb2_1_con: connector-0 { + compatible = "usb-a-connector"; + vbus-supply = <&vcc_5v_peri>; + + port { + usb2_1_connector: endpoint { + remote-endpoint = <&usb_hub_2_1>; + }; + }; + }; + + usb2_2_con: connector-1 { + compatible = "usb-a-connector"; + vbus-supply = <&vcc_5v_peri>; + + port { + usb2_2_connector: endpoint { + remote-endpoint = <&usb_hub_2_2>; + }; + }; + }; + + usb2_3_con: connector-2 { + compatible = "usb-a-connector"; + vbus-supply = <&vcc_5v_peri>; + + port { + usb2_3_connector: endpoint { + remote-endpoint = <&usb_hub_2_3>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&user_led>; + pinctrl-names = "default"; + + user-led { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@84800000 { + reg = <0x0 0x84800000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@87000000 { + reg = <0x0 0x87000000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@88e00000 { + reg = <0x0 0x88e00000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@89500000 { + reg = <0x0 0x89500000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@89a00000 { + reg = <0x0 0x89a00000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + thermal-zones { + msm-skin-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + }; + + quiet-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + }; + + ufs-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + }; + + xo-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_5v_peri: regulator-vcc-5v-peri { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v_peri"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vph_pwr>; + + regulator-boot-on; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>; + + vreg_s1b_1p84: smps1 { + regulator-name = "vreg_s1b_1p84"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p536: smps7 { + regulator-name = "vreg_s7b_0p536"; + regulator-min-microvolt = <536000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p2: smps8 { + regulator-name = "vreg_s8b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1496000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name = "vreg_l17b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p84>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p536>; + vdd-bob-supply = <&vph_pwr>; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1976000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3032000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +/* Pin 13, 15 in GPIO header */ +&i2c0 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 27, 28 in GPIO header */ +&i2c2 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 3, 5 in GPIO header */ +&i2c6 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +&i2c10 { + qcom,enable-gsi-dma; + status = "okay"; + + rtc: rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +/* External touchscreen */ +&i2c13 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + +&lpass_va_macro { + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; + pinctrl-names = "default"; + + /* Support for QPS615 PCIe switch */ + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x400 &apps_smmu 0x1c88 0x1>, + <0x500 &apps_smmu 0x1c89 0x1>, + <0x501 &apps_smmu 0x1c90 0x1>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pm7325_gpios { + pm7325_adc_default: adc-default-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + msm-skin-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + ufs-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_vadc { + pinctrl-0 = <&pm7325_adc_default>; + pinctrl-names = "default"; + + channel@3 { + reg = ; + label = "pmk7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = ; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "quiet_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "msm_skin_therm"; + }; + + channel@14a { + /* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */ + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "ufs_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qspi { + /* It's not possible to use QSPI with iommu */ + /* due to an error in qcom_smmu_write_s2cr */ + /delete-property/ iommus; + + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, + <&qspi_data1>, <&qspi_data23>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + spi_flash: flash@0 { + compatible = "winbond,w25q256", "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + status = "okay"; +}; + +&sdhc_1 { + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p96>; + vqmmc-supply = <&vreg_l19b_1p8>; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; + + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sound { + compatible = "qcom,qcs6490-rb3gen2-sndcard"; + model = "QCS6490-Radxa-Dragon-Q6A"; + + audio-routing = "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + +/* Pin 11, 29, 31, 32 in GPIO header */ +&spi7 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 19, 21, 23, 24, 26 in GPIO header */ +&spi12 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 22, 33, 36, 37 in GPIO header */ +&spi14 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +&swr0 { + status = "okay"; + + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr1 { + status = "okay"; + + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&tlmm { + gpio-line-names = + /* GPIO_0 ~ GPIO_3 */ + "PIN_13", "PIN_15", "", "", + /* GPIO_4 ~ GPIO_7 */ + "", "", "", "", + /* GPIO_8 ~ GPIO_11 */ + "PIN_27", "PIN_28", "", "", + /* GPIO_12 ~ GPIO_15 */ + "", "", "", "", + /* GPIO_16 ~ GPIO_19 */ + "", "", "", "", + /* GPIO_20 ~ GPIO_23 */ + "", "", "PIN_8", "PIN_10", + /* GPIO_24 ~ GPIO_27 */ + "PIN_3", "PIN_5", "PIN_16", "PIN_27", + /* GPIO_28 ~ GPIO_31 */ + "PIN_31", "PIN_11", "PIN_32", "PIN_29", + /* GPIO_32 ~ GPIO_35 */ + "", "", "", "", + /* GPIO_36 ~ GPIO_39 */ + "", "", "", "", + /* GPIO_40 ~ GPIO_43 */ + "", "", "", "", + /* GPIO_44 ~ GPIO_47 */ + "", "", "", "", + /* GPIO_48 ~ GPIO_51 */ + "PIN_21", "PIN_19", "PIN_23", "PIN_24", + /* GPIO_52 ~ GPIO_55 */ + "", "", "", "PIN_26", + /* GPIO_56 ~ GPIO_59 */ + "PIN_33", "PIN_22", "PIN_37", "PIN_36", + /* GPIO_60 ~ GPIO_63 */ + "", "", "", "", + /* GPIO_64 ~ GPIO_67 */ + "", "", "", "", + /* GPIO_68 ~ GPIO_71 */ + "", "", "", "", + /* GPIO_72 ~ GPIO_75 */ + "", "", "", "", + /* GPIO_76 ~ GPIO_79 */ + "", "", "", "", + /* GPIO_80 ~ GPIO_83 */ + "", "", "", "", + /* GPIO_84 ~ GPIO_87 */ + "", "", "", "", + /* GPIO_88 ~ GPIO_91 */ + "", "", "", "", + /* GPIO_92 ~ GPIO_95 */ + "", "", "", "", + /* GPIO_96 ~ GPIO_99 */ + "PIN_7", "PIN_12", "PIN_38", "PIN_40", + /* GPIO_100 ~ GPIO_103 */ + "PIN_35", "", "", "", + /* GPIO_104 ~ GPIO_107 */ + "", "", "", "", + /* GPIO_108 ~ GPIO_111 */ + "", "", "", "", + /* GPIO_112 ~ GPIO_115 */ + "", "", "", "", + /* GPIO_116 ~ GPIO_119 */ + "", "", "", "", + /* GPIO_120 ~ GPIO_123 */ + "", "", "", "", + /* GPIO_124 ~ GPIO_127 */ + "", "", "", "", + /* GPIO_128 ~ GPIO_131 */ + "", "", "", "", + /* GPIO_132 ~ GPIO_135 */ + "", "", "", "", + /* GPIO_136 ~ GPIO_139 */ + "", "", "", "", + /* GPIO_140 ~ GPIO_143 */ + "", "", "", "", + /* GPIO_144 ~ GPIO_147 */ + "", "", "", "", + /* GPIO_148 ~ GPIO_151 */ + "", "", "", "", + /* GPIO_152 ~ GPIO_155 */ + "", "", "", "", + /* GPIO_156 ~ GPIO_159 */ + "", "", "", "", + /* GPIO_160 ~ GPIO_163 */ + "", "", "", "", + /* GPIO_164 ~ GPIO_167 */ + "", "", "", "", + /* GPIO_168 ~ GPIO_171 */ + "", "", "", "", + /* GPIO_172 ~ GPIO_174 */ + "", "", ""; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qspi_sleep: qspi-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17"; + function = "gpio"; + output-disable; + }; + + sd_cd: sd-cd-state { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; + + user_led: user-led-state { + pins = "gpio42"; + function = "gpio"; + bias-pull-up; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart5 { + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + /* Onboard USB 2.0 hub */ + usb_hub_2_x: hub@1 { + compatible = "usb1a40,0101"; + reg = <1>; + vdd-supply = <&vcc_5v_peri>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&usb2_1_connector>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_2_2: endpoint { + remote-endpoint = <&usb2_2_connector>; + }; + }; + + port@3 { + reg = <3>; + + usb_hub_2_3: endpoint { + remote-endpoint = <&usb2_3_connector>; + }; + }; + }; + + /* FCU760K Wi-Fi & Bluetooth module */ + wifi@4 { + compatible = "usba69c,8d80"; + reg = <4>; + }; + }; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&pcie0_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&qspi_clk { + bias-disable; + drive-strength = <16>; +}; + +&qspi_cs0 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data0 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data1 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data23 { + bias-disable; + drive-strength = <8>; +}; + +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; diff --git a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts index 18cea881200..f29a352b028 100644 --- a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts +++ b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts @@ -14,7 +14,7 @@ #include #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" @@ -217,6 +217,13 @@ }; }; + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + thermal-zones { sdm-skin-thermal { thermal-sensors = <&pmk8350_adc_tm 3>; @@ -255,13 +262,6 @@ }; }; - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - wcn6750-pmu { compatible = "qcom,wcn6750-pmu"; pinctrl-0 = <&bt_en>; @@ -335,8 +335,6 @@ vdd-s8-supply = <&vph_pwr>; vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; vdd-l2-l7-supply = <&vreg_bob_3p296>; - vdd-l3-supply = <&vreg_s2b_0p876>; - vdd-l5-supply = <&vreg_s2b_0p876>; vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; vdd-l8-supply = <&vreg_s7b_0p972>; vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; @@ -349,12 +347,6 @@ regulator-max-microvolt = <2040000>; }; - vreg_s2b_0p876: smps2 { - regulator-name = "vreg_s2b_0p876"; - regulator-min-microvolt = <570070>; - regulator-max-microvolt = <1050000>; - }; - vreg_s7b_0p972: smps7 { regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; @@ -385,27 +377,13 @@ vreg_l3b_0p504: ldo3 { regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; - regulator-max-microvolt = <910000>; - regulator-initial-mode = ; - }; - - vreg_l4b_0p752: ldo4 { - regulator-name = "vreg_l4b_0p752"; - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <820000>; - regulator-initial-mode = ; - }; - - reg_l5b_0p752: ldo5 { - regulator-name = "reg_l5b_0p752"; - regulator-min-microvolt = <552000>; - regulator-max-microvolt = <832000>; + regulator-max-microvolt = <650000>; regulator-initial-mode = ; }; vreg_l6b_1p2: ldo6 { regulator-name = "vreg_l6b_1p2"; - regulator-min-microvolt = <1140000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; @@ -436,7 +414,7 @@ vreg_l11b_1p504: ldo11 { regulator-name = "vreg_l11b_1p504"; - regulator-min-microvolt = <1504000>; + regulator-min-microvolt = <1776000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; @@ -457,7 +435,7 @@ vreg_l14b_1p08: ldo14 { regulator-name = "vreg_l14b_1p08"; - regulator-min-microvolt = <1080000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; @@ -521,26 +499,8 @@ vreg_s1c_2p19: smps1 { regulator-name = "vreg_s1c_2p19"; - regulator-min-microvolt = <2190000>; - regulator-max-microvolt = <2210000>; - }; - - vreg_s2c_0p752: smps2 { - regulator-name = "vreg_s2c_0p752"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <800000>; - }; - - vreg_s5c_0p752: smps5 { - regulator-name = "vreg_s5c_0p752"; - regulator-min-microvolt = <465000>; - regulator-max-microvolt = <1050000>; - }; - - vreg_s7c_0p752: smps7 { - regulator-name = "vreg_s7c_0p752"; - regulator-min-microvolt = <465000>; - regulator-max-microvolt = <800000>; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2208000>; }; vreg_s9c_1p084: smps9 { @@ -600,7 +560,7 @@ vreg_l8c_1p62: ldo8 { regulator-name = "vreg_l8c_1p62"; - regulator-min-microvolt = <1620000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; @@ -608,7 +568,7 @@ vreg_l9c_2p96: ldo9 { regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <35440000>; + regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; @@ -628,7 +588,7 @@ vreg_l12c_1p65: ldo12 { regulator-name = "vreg_l12c_1p65"; - regulator-min-microvolt = <1650000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; @@ -1009,10 +969,12 @@ }; &qupv3_id_0 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; status = "okay"; }; &qupv3_id_1 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/qcom/qcs8300-ride.dts b/dts/upstream/src/arm64/qcom/qcs8300-ride.dts index cabb3f50870..9bcb869dd27 100644 --- a/dts/upstream/src/arm64/qcom/qcs8300-ride.dts +++ b/dts/upstream/src/arm64/qcom/qcs8300-ride.dts @@ -8,8 +8,8 @@ #include #include -#include "qcs8300.dtsi" -#include "qcs8300-pmics.dtsi" +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. QCS8300 Ride"; compatible = "qcom,qcs8300-ride", "qcom,qcs8300"; diff --git a/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts b/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts index 67ba508e92b..1b9ca957a94 100644 --- a/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts +++ b/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts @@ -7,7 +7,7 @@ #include #include -#include "qcm2290.dtsi" +#include "agatti.dtsi" #include "pm4125.dtsi" / { @@ -188,6 +188,53 @@ regulator-always-on; regulator-boot-on; }; + + sound { + compatible = "qcom,qrb2210-sndcard"; + pinctrl-0 = <&lpi_i2s2_active>; + pinctrl-names = "default"; + model = "Qualcomm-RB1-WSA8815-Speaker-DMIC0"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + hdmi-i2s-dai-link { + link-name = "HDMI/I2S Playback"; + + codec { + sound-dai = <<9611_codec 0>; + }; + + cpu { + sound-dai = <&q6afedai SECONDARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + }; }; &cpu_pd0 { @@ -214,10 +261,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/qcm2290/a702_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/qcm2290/a702_zap.mbn"; }; &i2c2_gpio { @@ -323,6 +370,14 @@ status = "okay"; }; +/* SECONDARY I2S uses 1 I2S SD Line for audio on LT9611UXC HDMI Bridge */ +&q6afedai { + dai@18 { + reg = ; + qcom,sd-lines = <0>; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -649,7 +704,7 @@ &uart3 { /delete-property/ interrupts; interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + <&tlmm 11 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&uart3_default>; pinctrl-1 = <&uart3_sleep>; pinctrl-names = "default", "sleep"; diff --git a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts index bdf2d66e40c..0cd36c54632 100644 --- a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts +++ b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts @@ -245,10 +245,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/qrb4210/a610_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/qrb4210/a610_zap.mbn"; }; &i2c2_gpio { diff --git a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts index d99448a0732..71b42e76f03 100644 --- a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts +++ b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts @@ -594,11 +594,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sm8250/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/a650_zap.mbn"; }; /* LS-I2C0 */ diff --git a/dts/upstream/src/arm64/qcom/sa8295p-adp.dts b/dts/upstream/src/arm64/qcom/sa8295p-adp.dts index 64e59299672..d28d6916242 100644 --- a/dts/upstream/src/arm64/qcom/sa8295p-adp.dts +++ b/dts/upstream/src/arm64/qcom/sa8295p-adp.dts @@ -149,13 +149,6 @@ enable-active-high; regulator-always-on; }; - - reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - }; }; &apps_rsc { @@ -345,11 +338,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sa8295p/a690_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sa8295p/a690_zap.mbn"; }; &gpu_smmu { diff --git a/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts b/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts index ad342d8b750..1514da63626 100644 --- a/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts +++ b/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts @@ -31,7 +31,7 @@ }; reserved-memory { - zap_mem: zap-shader@80840000 { + gpu_mem: zap-shader@80840000 { reg = <0x0 0x80840000 0 0x2000>; no-map; }; @@ -426,11 +426,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&zap_mem>; - firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn"; }; &mdss { diff --git a/dts/upstream/src/arm64/qcom/sc7180-el2.dtso b/dts/upstream/src/arm64/qcom/sc7180-el2.dtso index 49a98676ca4..6e8da59597b 100644 --- a/dts/upstream/src/arm64/qcom/sc7180-el2.dtso +++ b/dts/upstream/src/arm64/qcom/sc7180-el2.dtso @@ -8,10 +8,8 @@ /plugin/; /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ -&gpu { - zap-shader { - status = "disabled"; - }; +&gpu_zap_shader { + status = "disabled"; }; /* Venus can be used in EL2 if booted similarly to ChromeOS devices. */ diff --git a/dts/upstream/src/arm64/qcom/sc7180-idp.dts b/dts/upstream/src/arm64/qcom/sc7180-idp.dts index 19cf419cf53..0bce3eefca2 100644 --- a/dts/upstream/src/arm64/qcom/sc7180-idp.dts +++ b/dts/upstream/src/arm64/qcom/sc7180-idp.dts @@ -39,6 +39,7 @@ * */ +/delete-node/ &gpu_zap_shader; /delete-node/ &hyp_mem; /delete-node/ &xbl_mem; /delete-node/ &aop_mem; diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi index 74ab321d333..b398f69917f 100644 --- a/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi +++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi @@ -41,6 +41,7 @@ * required by the board dts. */ +/delete-node/ &gpu_zap_shader; /delete-node/ &hyp_mem; /delete-node/ &ipa_fw_mem; /delete-node/ &xbl_mem; diff --git a/dts/upstream/src/arm64/qcom/sc7180.dtsi b/dts/upstream/src/arm64/qcom/sc7180.dtsi index a0df10a97c7..45b9864e330 100644 --- a/dts/upstream/src/arm64/qcom/sc7180.dtsi +++ b/dts/upstream/src/arm64/qcom/sc7180.dtsi @@ -1474,6 +1474,12 @@ }; }; + refgen: regulator@ff1000 { + compatible = "qcom,sc7180-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x00ff1000 0x0 0x60>; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sc7180-config-noc"; reg = <0 0x01500000 0 0x28000>; @@ -2179,6 +2185,10 @@ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; + gpu_zap_shader: zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -3332,6 +3342,8 @@ phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi b/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi index ccd39a1baed..8cac4ce9c85 100644 --- a/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi +++ b/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi @@ -7,7 +7,7 @@ #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" @@ -573,7 +573,7 @@ }; }; -/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +/* PINCTRL - additions to nodes defined in kodiak.dtsi */ &dp_hot_plug_det { bias-disable; diff --git a/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi b/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi index 7d1d5bbbbbd..469a5d103e3 100644 --- a/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi +++ b/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi @@ -16,7 +16,7 @@ #include #include -#include "sc7280.dtsi" +#include "kodiak.dtsi" /* PMICs depend on spmi_bus label and so must come after SoC */ #include "pm7325.dtsi" diff --git a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts index 08d0784d0cb..d86a31ddede 100644 --- a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts +++ b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts @@ -151,11 +151,6 @@ no-map; }; - gpu_mem: gpu-region@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - cdsp_mem: cdsp-region@98900000 { reg = <0x0 0x98900000 0x0 0x1400000>; no-map; @@ -355,11 +350,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; }; &i2c1 { diff --git a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts index 93de9fe918e..aff398390eb 100644 --- a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts +++ b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts @@ -14,6 +14,8 @@ #include "sc8180x.dtsi" #include "sc8180x-pmics.dtsi" +/delete-node/ &gpu_mem; + / { model = "Qualcomm SC8180x Primus"; compatible = "qcom,sc8180x-primus", "qcom,sc8180x"; @@ -442,11 +444,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; }; &i2c1 { diff --git a/dts/upstream/src/arm64/qcom/sc8180x.dtsi b/dts/upstream/src/arm64/qcom/sc8180x.dtsi index 85c2afcb417..8319d892c6e 100644 --- a/dts/upstream/src/arm64/qcom/sc8180x.dtsi +++ b/dts/upstream/src/arm64/qcom/sc8180x.dtsi @@ -646,6 +646,11 @@ no-map; }; + gpu_mem: memory@98715000 { + reg = <0x0 0x98715000 0x0 0x2000>; + no-map; + }; + reserved@9d400000 { reg = <0x0 0x9d400000 0x0 0x1000000>; no-map; @@ -2274,6 +2279,10 @@ status = "disabled"; + gpu_zap_shader: zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2530,6 +2539,12 @@ status = "disabled"; }; + refgen: regulator@88e7000 { + compatible = "qcom,sc8180x-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x60>; + }; + usb_prim_qmpphy: phy@88e8000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -3116,6 +3131,8 @@ phys = <&mdss_dsi0_phy>; phy-names = "dsi"; + refgen-supply = <&refgen>; + status = "disabled"; ports { @@ -3203,6 +3220,8 @@ phys = <&mdss_dsi1_phy>; phy-names = "dsi"; + refgen-supply = <&refgen>; + status = "disabled"; ports { diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts b/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts index 490e970c54a..c53e00cae46 100644 --- a/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts +++ b/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts @@ -225,11 +225,6 @@ }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -509,11 +504,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-el2.dtso b/dts/upstream/src/arm64/qcom/sc8280xp-el2.dtso index 25d1fa4bc20..cff3735a12d 100644 --- a/dts/upstream/src/arm64/qcom/sc8280xp-el2.dtso +++ b/dts/upstream/src/arm64/qcom/sc8280xp-el2.dtso @@ -8,10 +8,8 @@ /plugin/; /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ -&gpu { - zap-shader { - status = "disabled"; - }; +&gpu_zap_shader { + status = "disabled"; }; /* diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts b/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts index 0374251d332..9819454abe1 100644 --- a/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts +++ b/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts @@ -158,11 +158,6 @@ }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -600,11 +595,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcdxkmsuc8280.mbn"; }; &i2c4 { diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 637430719e6..d84ca010ab9 100644 --- a/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -83,14 +83,11 @@ pinctrl-names = "default"; pinctrl-0 = <&cam_indicator_en>; - led-camera-indicator { - label = "white:camera-indicator"; + privacy_led: privacy-led { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; - /* Reuse as a panic indicator until we get a "camera on" trigger */ panic-indicator; }; }; @@ -283,11 +280,6 @@ }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -685,6 +677,9 @@ pinctrl-names = "default"; pinctrl-0 = <&cam_rgb_default>; + leds = <&privacy_led>; + led-names = "privacy"; + clocks = <&camcc CAMCC_MCLK3_CLK>; orientation = <0>; /* Front facing */ @@ -722,11 +717,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-arcata.dts b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-arcata.dts index aeed3ef152e..f2b4470d440 100644 --- a/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-arcata.dts +++ b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-arcata.dts @@ -186,11 +186,6 @@ }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -462,11 +457,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8280xp/MICROSOFT/SurfacePro9/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/MICROSOFT/SurfacePro9/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts index a40dccd70df..00bbeeef6f1 100644 --- a/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts +++ b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts @@ -227,11 +227,6 @@ }; reserved-memory { - gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -579,11 +574,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcdxkmsuc8280.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcdxkmsuc8280.mbn"; }; &mdss0 { diff --git a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi index 279e5e6beae..b9e0d9c7c06 100644 --- a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi +++ b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi @@ -691,6 +691,11 @@ no-map; }; + pil_gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + pil_adsp_mem: adsp-region@86c00000 { reg = <0 0x86c00000 0 0x2000000>; no-map; @@ -967,8 +972,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, - <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -989,8 +994,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, - <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1011,8 +1016,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, - <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1033,8 +1038,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, - <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1069,8 +1074,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, - <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1091,8 +1096,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, - <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1131,8 +1136,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, - <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1153,8 +1158,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1175,8 +1180,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, - <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1197,8 +1202,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1241,8 +1246,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, - <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1285,8 +1290,8 @@ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, - <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1338,7 +1343,7 @@ }; }; - gpi_dma0: dma-controller@900000 { + gpi_dma0: dma-controller@900000 { compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00900000 0 0x60000>; @@ -1393,8 +1398,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, - <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1415,8 +1420,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1437,8 +1442,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1459,8 +1464,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1481,8 +1486,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1503,8 +1508,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1539,8 +1544,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1561,8 +1566,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1583,8 +1588,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1605,8 +1610,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1627,8 +1632,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1649,8 +1654,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1671,8 +1676,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1693,8 +1698,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, - <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1715,8 +1720,8 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, - <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1800,8 +1805,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, - <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1822,8 +1827,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1844,8 +1849,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1866,8 +1871,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1888,8 +1893,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1910,8 +1915,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1932,8 +1937,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1954,8 +1959,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -1976,8 +1981,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1998,8 +2003,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -2020,8 +2025,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -2042,8 +2047,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -2064,8 +2069,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -2086,8 +2091,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; @@ -2108,8 +2113,8 @@ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -3366,6 +3371,10 @@ status = "disabled"; + gpu_zap_shader: zap-shader { + memory-region = <&pil_gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -3723,6 +3732,12 @@ status = "disabled"; }; + refgen: regulator@8900000 { + compatible = "qcom,sc8280xp-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x08900000 0x0 0x96>; + }; + usb_1_hsphy: phy@8902000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -5773,8 +5788,12 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SC8280XP_NSP>; - power-domain-names = "nsp"; + power-domains = <&rpmhpd SC8280XP_NSP>, + <&rpmhpd SC8280XP_CX>, + <&rpmhpd SC8280XP_MXC>; + power-domain-names = "nsp", + "cx", + "mxc"; memory-region = <&pil_nsp0_mem>; @@ -5904,8 +5923,12 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SC8280XP_NSP>; - power-domain-names = "nsp"; + power-domains = <&rpmhpd SC8280XP_NSP>, + <&rpmhpd SC8280XP_CX>, + <&rpmhpd SC8280XP_MXC>; + power-domain-names = "nsp", + "cx", + "mxc"; memory-region = <&pil_nsp1_mem>; diff --git a/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts b/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts index d01422844fb..ed55646ca41 100644 --- a/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts +++ b/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts @@ -404,11 +404,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm670/sargo/a615_zap.mbn"; }; &i2c9 { diff --git a/dts/upstream/src/arm64/qcom/sdm670.dtsi b/dts/upstream/src/arm64/qcom/sdm670.dtsi index c33f3de779f..b8a8dcbdfbe 100644 --- a/dts/upstream/src/arm64/qcom/sdm670.dtsi +++ b/dts/upstream/src/arm64/qcom/sdm670.dtsi @@ -1124,6 +1124,12 @@ }; }; + refgen: regulator@ff1000 { + compatible = "qcom,sdm670-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x00ff1000 0x0 0x60>; + }; + mem_noc: interconnect@1380000 { compatible = "qcom,sdm670-mem-noc"; reg = <0 0x01380000 0 0x27200>; @@ -1376,6 +1382,10 @@ status = "disabled"; + gpu_zap_shader: zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -1926,6 +1936,8 @@ phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; @@ -2000,6 +2012,8 @@ phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/qcom/sdm845-db845c.dts b/dts/upstream/src/arm64/qcom/sdm845-db845c.dts index 8abf3e90950..ce23f87e031 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-db845c.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-db845c.dts @@ -455,10 +455,10 @@ &gpu { status = "okay"; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm845/a630_zap.mbn"; }; &i2c10 { diff --git a/dts/upstream/src/arm64/qcom/sdm845-lg-common.dtsi b/dts/upstream/src/arm64/qcom/sdm845-lg-common.dtsi index 99dafc6716e..0ee2f4b99fb 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-lg-common.dtsi +++ b/dts/upstream/src/arm64/qcom/sdm845-lg-common.dtsi @@ -99,26 +99,15 @@ no-map; }; - /* rmtfs lower guard */ - memory@f0800000 { - reg = <0 0xf0800000 0 0x1000>; - no-map; - }; - - rmtfs_mem: memory@f0801000 { + rmtfs_mem: rmtfs-region@f0800000 { compatible = "qcom,rmtfs-mem"; - reg = <0 0xf0801000 0 0x200000>; + reg = <0 0xf0800000 0 0x202000>; + qcom,use-guard-pages; no-map; qcom,client-id = <1>; qcom,vmid = ; }; - - /* rmtfs upper guard */ - memory@f0a01000 { - reg = <0 0xf0a01000 0 0x1000>; - no-map; - }; }; gpio-keys { @@ -467,10 +456,6 @@ &gpu { status = "okay"; - - zap-shader { - memory-region = <&gpu_mem>; - }; }; &ipa { diff --git a/dts/upstream/src/arm64/qcom/sdm845-lg-judyln.dts b/dts/upstream/src/arm64/qcom/sdm845-lg-judyln.dts index a12723310c8..09bfcef4240 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-lg-judyln.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-lg-judyln.dts @@ -47,10 +47,8 @@ firmware-name = "qcom/sdm845/judyln/cdsp.mbn"; }; -&gpu { - zap-shader { - firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; }; &mss_pil { diff --git a/dts/upstream/src/arm64/qcom/sdm845-lg-judyp.dts b/dts/upstream/src/arm64/qcom/sdm845-lg-judyp.dts index d17d4d4d560..ffe1da2227f 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-lg-judyp.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-lg-judyp.dts @@ -33,10 +33,8 @@ firmware-name = "qcom/sdm845/judyp/cdsp.mbn"; }; -&gpu { - zap-shader { - firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; }; &mss_pil { diff --git a/dts/upstream/src/arm64/qcom/sdm845-mtp.dts b/dts/upstream/src/arm64/qcom/sdm845-mtp.dts index 63d2993536a..091568642fa 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-mtp.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-mtp.dts @@ -416,11 +416,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/a630_zap.mbn"; }; &i2c10 { diff --git a/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi b/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi index dcfffb271fc..db6dd04c51b 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi +++ b/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi @@ -75,32 +75,20 @@ }; reserved-memory { - /* - * The rmtfs_mem needs to be guarded due to "XPU limitations" - * it is otherwise possible for an allocation adjacent to the - * rmtfs_mem region to trigger an XPU violation, causing a crash. - */ - rmtfs_lower_guard: rmtfs-lower-guard@f5b00000 { - no-map; - reg = <0 0xf5b00000 0 0x1000>; - }; /* * The rmtfs memory region in downstream is 'dynamically allocated' * but given the same address every time. Hard code it as this address is * where the modem firmware expects it to be. */ - rmtfs_mem: rmtfs-mem@f5b01000 { + rmtfs_mem: rmtfs-region@f5b00000 { compatible = "qcom,rmtfs-mem"; - reg = <0 0xf5b01000 0 0x200000>; + reg = <0 0xf5b00000 0 0x202000>; + qcom,use-guard-pages; no-map; qcom,client-id = <1>; qcom,vmid = ; }; - rmtfs_upper_guard: rmtfs-upper-guard@f5d01000 { - no-map; - reg = <0 0xf5d01000 0 0x1000>; - }; /* * It seems like reserving the old rmtfs_mem region is also needed to prevent @@ -162,6 +150,34 @@ enable-active-high; regulator-boot-on; }; + + panel_vci_3v3: panel-vci-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LCD_VCI_3V"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&panel_vci_default>; + pinctrl-names = "default"; + regulator-boot-on; + }; + + panel_vddi_poc_1p8: panel-vddi-poc-regulator { + compatible = "regulator-fixed"; + regulator-name = "VDDI_POC"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&panel_poc_default>; + pinctrl-names = "default"; + regulator-boot-on; + }; }; &adsp_pas { @@ -351,11 +367,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; }; &i2c10 { @@ -429,11 +444,15 @@ reg = <0>; vddio-supply = <&vreg_l14a_1p88>; + vci-supply = <&panel_vci_3v3>; + poc-supply = <&panel_vddi_poc_1p8>; + te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; + pinctrl-0 = <&panel_default>; + pinctrl-1 = <&panel_sleep>; + pinctrl-names = "default", "sleep"; port { panel_in: endpoint { @@ -803,13 +822,73 @@ bias-disable; }; - tri_state_key_default: tri-state-key-default-state { - pins = "gpio40", "gpio42", "gpio26"; + panel_vci_default: vci-state { + pins = "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + panel_poc_default: poc-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + alert_slider_default: alert-slider-default-state { + pins = "gpio126", "gpio52", "gpio24"; function = "gpio"; drive-strength = <2>; bias-disable; }; + panel_default: panel-default-state { + esd-pins { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; + }; + + panel_sleep: panel-sleep-state { + esd-pins { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; + }; + ts_default_pins: ts-int-state { pins = "gpio99", "gpio125"; function = "gpio"; @@ -817,27 +896,6 @@ bias-pull-up; }; - panel_reset_pins: panel-reset-state { - pins = "gpio6", "gpio25", "gpio26"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - panel_te_pin: panel-te-state { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-disable; - }; - - panel_esd_pin: panel-esd-state { - pins = "gpio30"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - speaker_default: speaker-default-state { pins = "gpio69"; function = "gpio"; diff --git a/dts/upstream/src/arm64/qcom/sdm845-oneplus-enchilada.dts b/dts/upstream/src/arm64/qcom/sdm845-oneplus-enchilada.dts index a259eb9d45a..8aead6dc25e 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-oneplus-enchilada.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-oneplus-enchilada.dts @@ -31,9 +31,9 @@ }; &display_panel { - status = "okay"; + compatible = "samsung,sofef00-ams628nw01", "samsung,sofef00"; - compatible = "samsung,sofef00"; + status = "okay"; }; &bq27441_fg { diff --git a/dts/upstream/src/arm64/qcom/sdm845-oneplus-fajita.dts b/dts/upstream/src/arm64/qcom/sdm845-oneplus-fajita.dts index 7e75decfda0..d6cd873aef0 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-oneplus-fajita.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-oneplus-fajita.dts @@ -32,7 +32,7 @@ &display_panel { status = "okay"; - compatible = "samsung,s6e3fc2x01"; + compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01"; }; &i2c4 { diff --git a/dts/upstream/src/arm64/qcom/sdm845-samsung-starqltechn.dts b/dts/upstream/src/arm64/qcom/sdm845-samsung-starqltechn.dts index 75a53f0bbeb..5d41a92cfeb 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-samsung-starqltechn.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-samsung-starqltechn.dts @@ -158,7 +158,7 @@ }; }; - i2c21 { + i2c-21 { compatible = "i2c-gpio"; sda-gpios = <&tlmm 127 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&tlmm 128 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -251,11 +251,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn"; }; &mdss { @@ -599,15 +598,15 @@ &i2c14 { status = "okay"; - pmic@66 { + max77705: pmic@66 { compatible = "maxim,max77705"; reg = <0x66>; + #interrupt-cells = <1>; interrupt-parent = <&pm8998_gpios>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; pinctrl-0 = <&pmic_int_default>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; leds { compatible = "maxim,max77705-rgb"; @@ -646,8 +645,8 @@ reg = <0x69>; compatible = "maxim,max77705-charger"; monitored-battery = <&battery>; - interrupt-parent = <&pm8998_gpios>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&max77705>; + interrupts = <0>; }; fuel-gauge@36 { @@ -655,8 +654,8 @@ compatible = "maxim,max77705-battery"; power-supplies = <&max77705_charger>; maxim,rsns-microohm = <5000>; - interrupt-parent = <&pm8998_gpios>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&max77705>; + interrupts = <2>; }; }; diff --git a/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts b/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts index 89260fce651..ddc2b3ca3bc 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts @@ -423,31 +423,29 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; }; &i2c5 { status = "okay"; touchscreen@38 { - compatible = "focaltech,fts8719"; + compatible = "focaltech,ft5452"; reg = <0x38>; - wakeup-source; - interrupt-parent = <&tlmm>; - interrupts = <125 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&vreg_l28a_3p0>; - vcc-i2c-supply = <&vreg_l14a_1p88>; - pinctrl-names = "default", "suspend"; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l28a_3p0>; + iovcc-supply = <&vreg_l14a_1p88>; + pinctrl-0 = <&ts_int_active &ts_reset_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default", "suspend"; - reset-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; - irq-gpio = <&tlmm 125 GPIO_TRANSITORY>; touchscreen-size-x = <1080>; touchscreen-size-y = <2160>; }; @@ -479,9 +477,6 @@ vdda-supply = <&vreg_l14a_1p88>; vdd3p3-supply = <&vreg_l28a_3p0>; - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; diff --git a/dts/upstream/src/arm64/qcom/sdm845-sony-xperia-tama.dtsi b/dts/upstream/src/arm64/qcom/sdm845-sony-xperia-tama.dtsi index f3f4c090057..7dc9349eedf 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-sony-xperia-tama.dtsi +++ b/dts/upstream/src/arm64/qcom/sdm845-sony-xperia-tama.dtsi @@ -426,11 +426,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn"; }; &i2c5 { diff --git a/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi b/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi index 7480c8d7ac5..785006a15e9 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -246,11 +246,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; }; &ibb { diff --git a/dts/upstream/src/arm64/qcom/sdm845-xiaomi-polaris.dts b/dts/upstream/src/arm64/qcom/sdm845-xiaomi-polaris.dts index 1c50a0563bc..30e88ff010a 100644 --- a/dts/upstream/src/arm64/qcom/sdm845-xiaomi-polaris.dts +++ b/dts/upstream/src/arm64/qcom/sdm845-xiaomi-polaris.dts @@ -392,11 +392,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; }; &ibb { diff --git a/dts/upstream/src/arm64/qcom/sdm845.dtsi b/dts/upstream/src/arm64/qcom/sdm845.dtsi index 13c9515260e..bf2f9c04adb 100644 --- a/dts/upstream/src/arm64/qcom/sdm845.dtsi +++ b/dts/upstream/src/arm64/qcom/sdm845.dtsi @@ -2218,6 +2218,11 @@ }; }; + refgen: regulator@ff1000 { + compatible = "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x00ff1000 0x0 0x60>; + }; + llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, @@ -4750,6 +4755,8 @@ phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; @@ -4824,6 +4831,8 @@ phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; @@ -4893,6 +4902,10 @@ status = "disabled"; + gpu_zap_shader: zap-shader { + memory-region = <&gpu_mem>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/dts/upstream/src/arm64/qcom/sdm850-huawei-matebook-e-2019.dts b/dts/upstream/src/arm64/qcom/sdm850-huawei-matebook-e-2019.dts new file mode 100644 index 00000000000..0ef9ea38a42 --- /dev/null +++ b/dts/upstream/src/arm64/qcom/sdm850-huawei-matebook-e-2019.dts @@ -0,0 +1,971 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Huawei MateBook E 2019 + * + * Copyright (c) 2025, Jingzhou Zhu + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sdm850.dtsi" +#include "sdm845-wcd9340.dtsi" +#include "pm8998.dtsi" + +/* + * Update following upstream (sdm845.dtsi) reserved + * memory mappings for firmware loading to succeed + * and enable the IPA device. + */ +/delete-node/ &tz_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; +/delete-node/ &adsp_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &slpi_mem; + +/ { + model = "Huawei MateBook E 2019"; + compatible = "huawei,planck", "qcom,sdm845"; + chassis-type = "convertible"; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_gpio &mode_pin_active>; + pinctrl-names = "default"; + + key-vol-up { + label = "Volume up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + wakeup-source; + }; + + switch-mode { + label = "Tablet mode switch"; + gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + led: led-camera-indicator { + label = "white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + /* Reuse as a panic indicator until we get a "camera on" trigger */ + panic-indicator; + }; + }; + + sw_edp_1p2: regulator-edp-1p2 { + compatible = "regulator-fixed"; + regulator-name = "sw_edp_1p2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + pinctrl-0 = <&sw_edp_1p2_en>; + pinctrl-names = "default"; + + gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l2a_1p2>; + }; + + vlcm_3v3: regulator-vlcm-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vlcm_3v3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + }; + + reserved-memory { + cont_splash_mem: framebuffer@80100000 { + reg = <0 0x80100000 0 0xd00000>; + no-map; + }; + + tz_mem: tz@86d00000 { + reg = <0 0x86d00000 0 0x4600000>; + no-map; + }; + + qseecom_mem: qseecom@8b500000 { + reg = <0 0x8b500000 0 0xa00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@8c400000 { + reg = <0 0x8c400000 0 0x100000>; + no-map; + }; + + adsp_mem: adsp@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8df00000 { + reg = <0 0x8df00000 0 0x100000>; + no-map; + }; + + slpi_mem: slpi@96700000 { + reg = <0 0x96700000 0 0x1200000>; + }; + + gpu_mem: gpu@97900000 { + reg = <0 0x97900000 0 0x5000>; + no-map; + }; + + rmtfs_mem: rmtfs@97c00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x97c00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + + }; + }; + + sn65dsi86_refclk: sn65dsi86-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <19200000>; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcadsp850.mbn"; + + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s4a_1p8: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p8: smps6 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <1028000>; + regulator-max-microvolt = <1028000>; + regulator-initial-mode = ; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + }; + + vreg_l9a_1p8: ldo9 { + }; + + vreg_l10a_1p8: ldo10 { + }; + + vreg_l11a_1p0: ldo11 { + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l15a_1p8: ldo15 { + }; + + vreg_l16a_2p7: ldo16 { + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p7: ldo18 { + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + + regulator-always-on; + }; + + vreg_l23a_3p3: ldo23 { + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + /* 3075000 uV causes -ENOTRECOVERABLE error */ + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + /* 3300000 uV causes -ENOTRECOVERABLE error */ + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s2c_0p752: smps2 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + }; + }; +}; + +&cci_i2c0 { + /* chipnext,cn3927e vcm@0xc */ + /* samsung,s5k3l6 camera@0x10 */ + /* eeprom@0x50 */ +}; + +&cci_i2c1 { + /* galaxycore,gc5025 camera@0x36 */ + /* eeprom@0x50 */ +}; + +&cdsp_pas { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qccdsp850.mbn"; + + status = "okay"; +}; + +&crypto { + /* FIXME: qce_start triggers an SError */ + status = "disabled"; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcdxkmsuc850.mbn"; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen: hid@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&i2c5_hid_active>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c7 { + /* ec@0x76 */ +}; + +&i2c10 { + clock-frequency = <400000>; + + status = "okay"; + + sn65dsi86: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + pinctrl-0 = <&sn65dsi86_pin_active>; + pinctrl-names = "default"; + + enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + vcca-supply = <&sw_edp_1p2>; + vcc-supply = <&sw_edp_1p2>; + vpll-supply = <&vreg_l14a_1p88>; + vccio-supply = <&vreg_l14a_1p88>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + no-hpd; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "innolux,p120zdg-bf1"; + power-supply = <&vlcm_3v3>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + }; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm850/HUAWEI/AL09/ipa_fws.elf"; + + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + + status = "okay"; +}; + +&mss_pil { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcdsp1v2850.mbn", + "qcom/sdm850/HUAWEI/AL09/qcdsp2850.mbn"; + + status = "okay"; +}; + +&pm8998_gpios { + sw_edp_1p2_en: sw-edp-1p2-en-state { + pins = "gpio9"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + }; + + volume_up_gpio: volume-up-gpio-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + }; +}; + +&pm8998_pwrkey { + status = "okay"; +}; + +&pm8998_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&q6asmdai { + dai@0 { + reg = ; + }; + + dai@1 { + reg = ; + }; + + dai@2 { + reg = ; + }; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-names = "default"; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; + + bus-width = <4>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&slpi_pas { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcslpi850.mbn"; + + status = "okay"; +}; + +&sound { + compatible = "lenovo,yoga-c630-sndcard", "qcom,sdm845-sndcard"; + model = "HUAWEI-PAK_AL09-M1040"; + + audio-routing = "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "DMIC0", "MCLK", + "DMIC0", "MIC BIAS1", + "DMIC2", "MCLK", + "DMIC2", "MIC BIAS3", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 AIF1_PB>; + }; + + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + + codec { + sound-dai = <&wcd9340 AIF1_CAP>; + }; + + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + + slim-wcd-dai-link { + link-name = "SLIM WCD Playback"; + + codec { + sound-dai = <&wcd9340 AIF2_PB>; + }; + + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, /* Unused */ + <81 4>; /* SPI (fingerprint reader) */ + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c5_hid_active: i2c5-hid-active-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + mode_pin_active: mode-pin-state { + pins = "gpio79"; + function = "gpio"; + bias-disable; + }; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; + }; + + sn65dsi86_pin_active: sn65dsi86-enable-state { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 = <&qup_uart6_4pin>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + + status = "okay"; +}; + +&usb_2_qmpphy { + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sdm850/HUAWEI/AL09/qcvss850.mbn"; + + status = "okay"; +}; + +&wcd9340 { + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <2700000>; + qcom,micbias3-microvolt = <1800000>; + + swm: soundwire@c85 { + left_spkr: speaker@0,3 { + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: speaker@0,4 { + compatible = "sdw10217211000"; + reg = <0 4>; + powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; + }; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + qcom,calibration-variant = "Huawei_Planck"; + + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts index 90efbb7e379..e41200839db 100644 --- a/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts +++ b/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts @@ -356,11 +356,10 @@ }; &gpu { - status = "okay"; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn"; - }; + status = "okay";}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn"; }; &i2c1 { diff --git a/dts/upstream/src/arm64/qcom/sdx75-idp.dts b/dts/upstream/src/arm64/qcom/sdx75-idp.dts index 06cacec3461..6696e1aee24 100644 --- a/dts/upstream/src/arm64/qcom/sdx75-idp.dts +++ b/dts/upstream/src/arm64/qcom/sdx75-idp.dts @@ -337,11 +337,9 @@ }; &usb { - status = "okay"; -}; - -&usb_dwc3 { dr_mode = "peripheral"; + + status = "okay"; }; &usb_hsphy { diff --git a/dts/upstream/src/arm64/qcom/sdx75.dtsi b/dts/upstream/src/arm64/qcom/sdx75.dtsi index 75bfc19f412..eff4c9055d6 100644 --- a/dts/upstream/src/arm64/qcom/sdx75.dtsi +++ b/dts/upstream/src/arm64/qcom/sdx75.dtsi @@ -1019,12 +1019,9 @@ }; }; - usb: usb@a6f8800 { - compatible = "qcom,sdx75-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb: usb@a600000 { + compatible = "qcom,sdx75-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, @@ -1041,21 +1038,35 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&pdc 10 IRQ_TYPE_EDGE_RISING>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + iommus = <&apps_smmu 0x80 0x0>; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + power-domains = <&gcc GCC_USB30_GDSC>; resets = <&gcc GCC_USB30_BCR>; + phys = <&usb_hsphy>, + <&usb_qmpphy>; + phy-names = "usb2-phy", + "usb3-phy"; + interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1063,38 +1074,25 @@ interconnect-names = "usb-ddr", "apps-usb"; + usb-role-switch; + status = "disabled"; - usb_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x80 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_hsphy>, - <&usb_qmpphy>; - phy-names = "usb2-phy", - "usb3-phy"; + ports { + #address-cells = <1>; + #size-cells = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; + port@0 { + reg = <0>; - port@0 { - reg = <0>; - - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - }; + usb_1_dwc3_ss: endpoint { }; }; }; diff --git a/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts b/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts index ad347ccd197..466ad409e92 100644 --- a/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts +++ b/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts @@ -121,10 +121,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm6115/Fxtec/QX1050/a610_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm6115/Fxtec/QX1050/a610_zap.mbn"; }; &i2c1 { diff --git a/dts/upstream/src/arm64/qcom/sm6115.dtsi b/dts/upstream/src/arm64/qcom/sm6115.dtsi index 91fc36b59ab..5e2032c26ea 100644 --- a/dts/upstream/src/arm64/qcom/sm6115.dtsi +++ b/dts/upstream/src/arm64/qcom/sm6115.dtsi @@ -1745,7 +1745,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; diff --git a/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts b/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts index c17545111f4..be1f550fd7b 100644 --- a/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts +++ b/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts @@ -67,10 +67,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn"; }; &mdss { diff --git a/dts/upstream/src/arm64/qcom/sm6350.dtsi b/dts/upstream/src/arm64/qcom/sm6350.dtsi index 8459b27cacc..f34dc6e278b 100644 --- a/dts/upstream/src/arm64/qcom/sm6350.dtsi +++ b/dts/upstream/src/arm64/qcom/sm6350.dtsi @@ -1175,18 +1175,47 @@ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; + + operating-points-v2 = <&ufs_opp_table>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 { @@ -1768,6 +1797,12 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sm6350-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x84>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm6350-qmp-usb3-dp-phy"; reg = <0x0 0x088e8000 0x0 0x3000>; @@ -2158,6 +2193,8 @@ power-domains = <&dispcc MDSS_GDSC>; iommus = <&apps_smmu 0x800 0x2>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -2360,6 +2397,8 @@ phys = <&mdss_dsi0_phy>; phy-names = "dsi"; + refgen-supply = <&refgen>; + #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/qcom/sm6375.dtsi b/dts/upstream/src/arm64/qcom/sm6375.dtsi index 0faa3a40ff8..87d6600ccbd 100644 --- a/dts/upstream/src/arm64/qcom/sm6375.dtsi +++ b/dts/upstream/src/arm64/qcom/sm6375.dtsi @@ -971,6 +971,12 @@ status = "disabled"; }; + refgen: regulator@162f000 { + compatible = "qcom,sm6375-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0162f000 0x0 0x84>; + }; + spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x01c40000 0 0x1100>, diff --git a/dts/upstream/src/arm64/qcom/sm7325-nothing-spacewar.dts b/dts/upstream/src/arm64/qcom/sm7325-nothing-spacewar.dts index f16b47b6a74..cb59c122f6f 100644 --- a/dts/upstream/src/arm64/qcom/sm7325-nothing-spacewar.dts +++ b/dts/upstream/src/arm64/qcom/sm7325-nothing-spacewar.dts @@ -978,6 +978,11 @@ status = "okay"; }; +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &mdss { status = "okay"; }; diff --git a/dts/upstream/src/arm64/qcom/sm7325.dtsi b/dts/upstream/src/arm64/qcom/sm7325.dtsi index 85d34b53e5e..beb279956df 100644 --- a/dts/upstream/src/arm64/qcom/sm7325.dtsi +++ b/dts/upstream/src/arm64/qcom/sm7325.dtsi @@ -4,7 +4,7 @@ * Copyright (c) 2024, Danila Tikhonov */ -#include "sc7280.dtsi" +#include "kodiak.dtsi" /* SM7325 uses Kryo 670 */ &cpu0 { compatible = "qcom,kryo670"; }; diff --git a/dts/upstream/src/arm64/qcom/sm8150.dtsi b/dts/upstream/src/arm64/qcom/sm8150.dtsi index acdba79612a..e3ec99972a2 100644 --- a/dts/upstream/src/arm64/qcom/sm8150.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8150.dtsi @@ -2255,7 +2255,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; @@ -3469,6 +3469,12 @@ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sm8150-refgen-regulator", + "qcom,sdm845-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x60>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm8150-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -3992,6 +3998,8 @@ phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; @@ -4085,6 +4093,8 @@ phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; diff --git a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts index 7f592bd3024..51779b99176 100644 --- a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts +++ b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts @@ -484,11 +484,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sm8250/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/a650_zap.mbn"; }; &i2c1 { diff --git a/dts/upstream/src/arm64/qcom/sm8250-samsung-common.dtsi b/dts/upstream/src/arm64/qcom/sm8250-samsung-common.dtsi index cf3d917addd..ef7ea4f72bf 100644 --- a/dts/upstream/src/arm64/qcom/sm8250-samsung-common.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8250-samsung-common.dtsi @@ -159,7 +159,8 @@ }; &tlmm { - gpio-reserved-ranges = <40 4>; /* I2C (Unused) */ + gpio-reserved-ranges = <20 4>, /* SPI (fingerprint scanner) */ + <40 4>; /* Unused */ }; &usb_1 { diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi index 465fd6e954a..c017399297b 100644 --- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi @@ -554,11 +554,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sm8250/xiaomi/elish/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/xiaomi/elish/a650_zap.mbn"; }; &i2c0 { diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts index 4ad24974c09..078ba13f876 100644 --- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts +++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts @@ -424,11 +424,10 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sm8250/xiaomi/pipa/a650_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/xiaomi/pipa/a650_zap.mbn"; }; &i2c11 { diff --git a/dts/upstream/src/arm64/qcom/sm8250.dtsi b/dts/upstream/src/arm64/qcom/sm8250.dtsi index 50dd11432bb..c7dffa44007 100644 --- a/dts/upstream/src/arm64/qcom/sm8250.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8250.dtsi @@ -2944,7 +2944,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_mem>; }; @@ -3901,6 +3901,11 @@ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; + refgen: regulator@88e7000 { + compatible = "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x088e7000 0x0 0x84>; + }; + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm8250-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; @@ -4679,6 +4684,8 @@ iommus = <&apps_smmu 0x820 0x402>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + status = "disabled"; #address-cells = <2>; @@ -4873,6 +4880,8 @@ phys = <&mdss_dsi0_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; @@ -4967,6 +4976,8 @@ phys = <&mdss_dsi1_phy>; + refgen-supply = <&refgen>; + status = "disabled"; #address-cells = <1>; diff --git a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts index 24a8c91e9f7..5f975d00946 100644 --- a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts +++ b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts @@ -403,10 +403,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8350/a660_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8350/a660_zap.mbn"; }; &i2c13 { diff --git a/dts/upstream/src/arm64/qcom/sm8350.dtsi b/dts/upstream/src/arm64/qcom/sm8350.dtsi index fc4ce9d4977..5c8fe213f5e 100644 --- a/dts/upstream/src/arm64/qcom/sm8350.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8350.dtsi @@ -2051,7 +2051,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&pil_gpu_mem>; }; diff --git a/dts/upstream/src/arm64/qcom/sm8450-hdk.dts b/dts/upstream/src/arm64/qcom/sm8450-hdk.dts index 0c6aa7ddf43..268ae0cd642 100644 --- a/dts/upstream/src/arm64/qcom/sm8450-hdk.dts +++ b/dts/upstream/src/arm64/qcom/sm8450-hdk.dts @@ -643,10 +643,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8450/a730_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8450/a730_zap.mbn"; }; &i2c9 { diff --git a/dts/upstream/src/arm64/qcom/sm8450.dtsi b/dts/upstream/src/arm64/qcom/sm8450.dtsi index 23420e69247..920a2d1c04d 100644 --- a/dts/upstream/src/arm64/qcom/sm8450.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8450.dtsi @@ -2047,25 +2047,28 @@ pcie0_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ + /* 2.5 GT/s x1 */ opp-2500000 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 2 x1 */ + /* 5 GT/s x1 */ opp-5000000 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ + /* 8 GT/s x1 */ opp-8000000 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; }; @@ -2209,46 +2212,68 @@ pcie1_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 4 x2 */ - opp-32000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; + opp-level = <4>; }; }; @@ -2434,7 +2459,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_micro_code_mem>; }; diff --git a/dts/upstream/src/arm64/qcom/sm8550-hdk-rear-camera-card.dtso b/dts/upstream/src/arm64/qcom/sm8550-hdk-rear-camera-card.dtso new file mode 100644 index 00000000000..66bec0fef76 --- /dev/null +++ b/dts/upstream/src/arm64/qcom/sm8550-hdk-rear-camera-card.dtso @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SM8550-HDK Rear Camera Card overlay + * + * Copyright (c) 2025, Linaro Limited + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + + csiphy3_ep: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + sensor@10 { + compatible = "samsung,s5k3m5"; + reg = <0x10>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7n_2p96>; + avdd-supply = <&vreg_l4m_2p8>; + dovdd-supply = <&vreg_l5n_1p8>; + dvdd-supply = <&vreg_l2m_1p056>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <602500000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; diff --git a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts index b5d7f0cd443..599850c4849 100644 --- a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts +++ b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts @@ -955,10 +955,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8550/a740_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; }; &lpass_tlmm { diff --git a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts index 38f2928f23c..f430038bd40 100644 --- a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts +++ b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts @@ -642,10 +642,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8550/a740_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; }; &i2c_master_hub_0 { diff --git a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts index a3f4200a114..05c98fe2c25 100644 --- a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts +++ b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts @@ -716,6 +716,52 @@ }; }; +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + port@3 { + csiphy3_ep: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + sensor@10 { + compatible = "samsung,s5k3m5"; + reg = <0x10>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7n_2p96>; + avdd-supply = <&vreg_l4m_2p8>; + dovdd-supply = <&vreg_l5n_1p8>; + dvdd-supply = <&vreg_l2m_1p056>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <602500000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + &i2c_master_hub_0 { status = "okay"; }; @@ -789,10 +835,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8550/a740_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; }; &lpass_tlmm { diff --git a/dts/upstream/src/arm64/qcom/sm8550.dtsi b/dts/upstream/src/arm64/qcom/sm8550.dtsi index 7724dba75db..e3f93f4f412 100644 --- a/dts/upstream/src/arm64/qcom/sm8550.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8550.dtsi @@ -2027,39 +2027,52 @@ pcie0_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; }; @@ -2194,46 +2207,68 @@ pcie1_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 4 x2 */ - opp-32000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; + opp-level = <4>; }; }; @@ -2456,7 +2491,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_micro_code_mem>; }; @@ -3189,6 +3224,7 @@ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; + max-sd-hs-hz = <37500000>; dma-coherent; /* Forbid SDR104/SDR50 - broken hw! */ @@ -4097,8 +4133,6 @@ usb_1: usb@a600000 { compatible = "qcom,sm8550-dwc3", "qcom,snps-dwc3"; reg = <0x0 0x0a600000 0x0 0xfc100>; - #address-cells = <1>; - #size-cells = <0>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4277,6 +4311,150 @@ gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + cam0_default: cam0-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam0_sleep: cam0-sleep-state { + mclk-pins { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam1_sleep: cam1-sleep-state { + mclk-pins { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam2_default: cam2-default-state { + mclk-pins { + pins = "gpio102"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam2_sleep: cam2-sleep-state { + mclk-pins { + pins = "gpio102"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam3_default: cam3-default-state { + mclk-pins { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam3_sleep: cam3-sleep-state { + mclk-pins { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam4_default: cam4-default-state { + mclk-pins { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam4_sleep: cam4-sleep-state { + mclk-pins { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam5_default: cam5-default-state { + mclk-pins { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam5_sleep: cam5-sleep-state { + mclk-pins { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam6_default: cam6-default-state { + mclk-pins { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam6_sleep: cam6-sleep-state { + mclk-pins { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cam7_default: cam7-default-state { + mclk-pins { + pins = "gpio107"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam7_sleep: cam7-sleep-state { + mclk-pins { + pins = "gpio107"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins = "gpio110"; diff --git a/dts/upstream/src/arm64/qcom/sm8650-hdk.dts b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts index 87d7190dc99..5bf1af3308c 100644 --- a/dts/upstream/src/arm64/qcom/sm8650-hdk.dts +++ b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts @@ -900,10 +900,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8650/gen70900_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; }; &lpass_tlmm { diff --git a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts index 9e790cf4480..b2feac61a89 100644 --- a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts +++ b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts @@ -830,10 +830,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/sm8650/gen70900_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; }; &lpass_tlmm { diff --git a/dts/upstream/src/arm64/qcom/sm8650.dtsi b/dts/upstream/src/arm64/qcom/sm8650.dtsi index ebf1971b1bf..f8e1950a74a 100644 --- a/dts/upstream/src/arm64/qcom/sm8650.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8650.dtsi @@ -3659,39 +3659,52 @@ pcie0_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; }; @@ -3839,46 +3852,68 @@ pcie1_opp_table: opp-table { compatible = "operating-points-v2"; - /* GEN 1 x1 */ - opp-2500000 { + /* 2.5 GT/s x1 */ + opp-2500000-1 { opp-hz = /bits/ 64 <2500000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <250000 1>; + opp-level = <1>; }; - /* GEN 1 x2 and GEN 2 x1 */ - opp-5000000 { + /* 2.5 GT/s x2 */ + opp-5000000-1 { opp-hz = /bits/ 64 <5000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <500000 1>; + opp-level = <1>; }; - /* GEN 2 x2 */ - opp-10000000 { + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { opp-hz = /bits/ 64 <10000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1000000 1>; + opp-level = <2>; }; - /* GEN 3 x1 */ - opp-8000000 { + /* 8 GT/s x1 */ + opp-8000000-3 { opp-hz = /bits/ 64 <8000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <984500 1>; + opp-level = <3>; }; - /* GEN 3 x2 and GEN 4 x1 */ - opp-16000000 { + /* 8 GT/s x2 */ + opp-16000000-3 { opp-hz = /bits/ 64 <16000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <1969000 1>; + opp-level = <3>; }; - /* GEN 4 x2 */ - opp-32000000 { + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { opp-hz = /bits/ 64 <32000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <3938000 1>; + opp-level = <4>; }; }; @@ -3988,6 +4023,8 @@ iommus = <&apps_smmu 0x60 0>; + dma-coherent; + lanes-per-direction = <2>; qcom,ice = <&ice>; @@ -4121,7 +4158,7 @@ status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_micro_code_mem>; }; @@ -5113,9 +5150,6 @@ dma-coherent; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; ports { diff --git a/dts/upstream/src/arm64/qcom/sm8750-mtp.dts b/dts/upstream/src/arm64/qcom/sm8750-mtp.dts index 3bbb53b7c71..c8cb521b4c2 100644 --- a/dts/upstream/src/arm64/qcom/sm8750-mtp.dts +++ b/dts/upstream/src/arm64/qcom/sm8750-mtp.dts @@ -191,6 +191,51 @@ }; }; + pmic-glink { + compatible = "qcom,sm8750-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -960,9 +1005,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -977,6 +1019,9 @@ }; &pcieport0 { + wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1200,3 +1245,31 @@ status = "okay"; }; + +&usb { + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3g_1p2>; + vdda-pll-supply = <&vreg_l2d_0p88>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l2d_0p88>; + vdda12-supply = <&vreg_l3g_1p2>; + + phys = <&pmih0108_eusb2_repeater>; + + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/qcom/sm8750-qrd.dts b/dts/upstream/src/arm64/qcom/sm8750-qrd.dts index 13c7b9664c8..b0cb61c5a60 100644 --- a/dts/upstream/src/arm64/qcom/sm8750-qrd.dts +++ b/dts/upstream/src/arm64/qcom/sm8750-qrd.dts @@ -193,6 +193,51 @@ }; }; + pmic-glink { + compatible = "qcom,sm8750-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -1054,3 +1099,31 @@ status = "okay"; }; + +&usb { + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3g_1p2>; + vdda-pll-supply = <&vreg_l2d_0p88>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l2d_0p88>; + vdda12-supply = <&vreg_l3g_1p2>; + + phys = <&pmih0108_eusb2_repeater>; + + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/qcom/sm8750.dtsi b/dts/upstream/src/arm64/qcom/sm8750.dtsi index a82d9867c7c..3f0b57f428b 100644 --- a/dts/upstream/src/arm64/qcom/sm8750.dtsi +++ b/dts/upstream/src/arm64/qcom/sm8750.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -635,7 +636,7 @@ <0>, <0>, <0>, - <0>; + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; #clock-cells = <1>; #reset-cells = <1>; @@ -2581,6 +2582,164 @@ }; }; + usb_hsphy: phy@88e3000 { + compatible = "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x88e3000 0x0 0x29c>; + + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8750-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb: usb@a600000 { + compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; diff --git a/dts/upstream/src/arm64/qcom/sm6150.dtsi b/dts/upstream/src/arm64/qcom/talos.dtsi similarity index 92% rename from dts/upstream/src/arm64/qcom/sm6150.dtsi rename to dts/upstream/src/arm64/qcom/talos.dtsi index 3d2a1cb02b6..95d26e31362 100644 --- a/dts/upstream/src/arm64/qcom/sm6150.dtsi +++ b/dts/upstream/src/arm64/qcom/talos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -11,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +41,10 @@ clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_0: l2-cache { compatible = "cache"; @@ -60,6 +66,10 @@ next-level-cache = <&l2_100>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_100: l2-cache { compatible = "cache"; @@ -81,6 +91,10 @@ next-level-cache = <&l2_200>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_200: l2-cache { compatible = "cache"; @@ -102,6 +116,10 @@ next-level-cache = <&l2_300>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_300: l2-cache { compatible = "cache"; @@ -123,6 +141,10 @@ next-level-cache = <&l2_400>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_400: l2-cache { compatible = "cache"; @@ -144,6 +166,10 @@ next-level-cache = <&l2_500>; clocks = <&cpufreq_hw 0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_500: l2-cache { compatible = "cache"; @@ -166,6 +192,10 @@ clocks = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_600: l2-cache { compatible = "cache"; @@ -187,6 +217,10 @@ next-level-cache = <&l2_700>; clocks = <&cpufreq_hw 1>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_700: l2-cache { compatible = "cache"; @@ -239,6 +273,111 @@ }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 4) (300000 * 16)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 4) (576000 * 16)>; + }; + + opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-peak-kBps = <(300000 * 4) (576000 * 16)>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <(451000 * 4) (806400 * 16)>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; + }; + + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(451000 * 4) (300000 * 16)>; + }; + + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <(451000 * 4) (576000 * 16)>; + }; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <(451000 * 4) (576000 * 16)>; + }; + + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <(547000 * 4) (806400 * 16)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(547000 * 4) (806400 * 16)>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <109440000>; + opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; + }; + }; + dummy_eud: dummy-sink { compatible = "arm,coresight-dummy-sink"; @@ -1260,10 +1399,10 @@ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", @@ -3657,14 +3796,191 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm6150-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_CORE_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm6150-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names = "mdp", + "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + interrupts-extended = <&mdss 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sm6150-dsi-phy-14nm"; + reg = <0x0 0x0ae94400 0x0 0x100>, + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x124>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,qcs615-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>, <0>; @@ -3978,6 +4294,16 @@ }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; + reg = <0x0 0x18321000 0x0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + usb_1_hsphy: phy@88e2000 { compatible = "qcom,qcs615-qusb2-phy"; reg = <0x0 0x88e2000 0x0 0x180>; diff --git a/dts/upstream/src/arm64/qcom/x1-asus-zenbook-a14.dtsi b/dts/upstream/src/arm64/qcom/x1-asus-zenbook-a14.dtsi index ee3c8c5e2c5..8e5c5575a53 100644 --- a/dts/upstream/src/arm64/qcom/x1-asus-zenbook-a14.dtsi +++ b/dts/upstream/src/arm64/qcom/x1-asus-zenbook-a14.dtsi @@ -11,10 +11,9 @@ #include #include -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" / { - model = "ASUS Zenbook A14"; chassis-type = "laptop"; aliases { @@ -1005,14 +1004,10 @@ status = "okay"; aux-bus { - panel { + panel: panel { compatible = "edp-panel"; - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; power-supply = <&vreg_edp_3p3>; - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - port { edp_panel_in: endpoint { remote-endpoint = <&mdss_dp3_out>; diff --git a/dts/upstream/src/arm64/qcom/x1-crd.dtsi b/dts/upstream/src/arm64/qcom/x1-crd.dtsi index 3c9455fede5..ded96fb4348 100644 --- a/dts/upstream/src/arm64/qcom/x1-crd.dtsi +++ b/dts/upstream/src/arm64/qcom/x1-crd.dtsi @@ -9,7 +9,7 @@ #include #include -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 CRD"; @@ -82,6 +82,13 @@ <&tlmm 123 GPIO_ACTIVE_HIGH>, <&tlmm 125 GPIO_ACTIVE_HIGH>; + nvmem-cells = <&charge_limit_en>, + <&charge_limit_end>, + <&charge_limit_delta>; + nvmem-cell-names = "charge_limit_en", + "charge_limit_end", + "charge_limit_delta"; + /* Left-side rear port */ connector@0 { compatible = "usb-c-connector"; diff --git a/dts/upstream/src/arm64/qcom/x1-dell-thena.dtsi b/dts/upstream/src/arm64/qcom/x1-dell-thena.dtsi index cc64558ed5e..bf04a12b16b 100644 --- a/dts/upstream/src/arm64/qcom/x1-dell-thena.dtsi +++ b/dts/upstream/src/arm64/qcom/x1-dell-thena.dtsi @@ -12,7 +12,7 @@ #include #include -#include "x1e80100-pmics.dtsi" +#include "hamoa-pmics.dtsi" / { chassis-type = "laptop"; @@ -1023,7 +1023,6 @@ }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1032,13 +1031,15 @@ }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { diff --git a/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts b/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts index bfc649d4b64..a9643cd746d 100644 --- a/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts +++ b/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts @@ -8,8 +8,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit for Windows"; @@ -763,10 +763,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn"; }; &i2c1 { diff --git a/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 654cbce9d6e..80ece9db875 100644 --- a/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -12,8 +12,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Lenovo ThinkPad T14s Gen 6"; @@ -722,10 +722,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/LENOVO/21N1/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/LENOVO/21N1/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts index 0113d856b3a..d4df21de0d9 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts @@ -11,8 +11,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "ASUS Vivobook S 15"; @@ -479,10 +479,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-asus-zenbook-a14.dts b/dts/upstream/src/arm64/qcom/x1e80100-asus-zenbook-a14.dts index 0d0bcc50207..0408ade7150 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-asus-zenbook-a14.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-asus-zenbook-a14.dts @@ -6,12 +6,71 @@ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-asus-zenbook-a14.dtsi" / { model = "ASUS Zenbook A14 (UX3407RA)"; compatible = "asus,zenbook-a14-ux3407ra", "qcom,x1e80100"; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &gpu { @@ -22,6 +81,31 @@ firmware-name = "qcom/x1e80100/ASUSTeK/zenbook-a14/qcdxkmsuc8380.mbn"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + }; +}; + +&panel { + compatible = "samsung,atna40cu11", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; +}; + &remoteproc_adsp { firmware-name = "qcom/x1e80100/ASUSTeK/zenbook-a14/qcadsp8380.mbn", "qcom/x1e80100/ASUSTeK/zenbook-a14/adsp_dtbs.elf"; @@ -35,3 +119,21 @@ status = "okay"; }; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + + max-speed = <3000000>; + }; +}; diff --git a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts index dfc378e1a05..429deffcf3e 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-crd.dtsi" / { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-dell-inspiron-14-plus-7441.dts b/dts/upstream/src/arm64/qcom/x1e80100-dell-inspiron-14-plus-7441.dts index cf2a7c26288..75e10d97c38 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-dell-inspiron-14-plus-7441.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-dell-inspiron-14-plus-7441.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-dell-thena.dtsi" / { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-dell-latitude-7455.dts b/dts/upstream/src/arm64/qcom/x1e80100-dell-latitude-7455.dts index 32ad9679550..a8ff7ef258a 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-dell-latitude-7455.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-dell-latitude-7455.dts @@ -4,7 +4,7 @@ */ /dts-v1/; -#include "x1e80100.dtsi" +#include "hamoa.dtsi" #include "x1-dell-thena.dtsi" / { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts b/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts index 58f8caaa725..2f533e56c8c 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts @@ -12,8 +12,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Dell XPS 13 9345"; @@ -676,10 +676,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/dell/xps13-9345/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/dell/xps13-9345/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-hp-elitebook-ultra-g1q.dts b/dts/upstream/src/arm64/qcom/x1e80100-hp-elitebook-ultra-g1q.dts index 4ea00d82369..0b3b6cb23e1 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-hp-elitebook-ultra-g1q.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-hp-elitebook-ultra-g1q.dts @@ -9,10 +9,8 @@ compatible = "hp,elitebook-ultra-g1q", "qcom,x1e80100"; }; -&gpu { - zap-shader { - firmware-name = "qcom/x1e80100/hp/elitebook-ultra-g1q/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/hp/elitebook-ultra-g1q/qcdxkmsuc8380.mbn"; }; &remoteproc_adsp { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts b/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts index e5a839d4584..b79e59e1c41 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts @@ -6,8 +6,8 @@ /dts-v1/; -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" #include "x1-hp-omnibook-x14.dtsi" / { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts index e0642fe8343..4c31d14a07b 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -9,8 +9,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Lenovo Yoga Slim 7x"; @@ -799,10 +799,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi index ed468b93ba5..7e1e808ea98 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi +++ b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi @@ -9,8 +9,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { aliases { @@ -861,11 +861,11 @@ &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_microcode_mem>; - firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; }; &i2c0 { diff --git a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts index 4a9b6d791e7..b742aabd9c0 100644 --- a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts +++ b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts @@ -8,8 +8,8 @@ #include #include -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 QCP"; @@ -831,10 +831,10 @@ &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; }; &i2c5 { diff --git a/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14-lcd.dts b/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14-lcd.dts new file mode 100644 index 00000000000..be756069131 --- /dev/null +++ b/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14-lcd.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Aleksandrs Vinarskis + */ + +/dts-v1/; + +#include "x1p42100-asus-zenbook-a14.dtsi" + +/ { + model = "ASUS Zenbook A14 (UX3407QA, LCD)"; + compatible = "asus,zenbook-a14-ux3407qa-lcd", "asus,zenbook-a14-ux3407qa", "qcom,x1p42100"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 416667>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; +}; + +&panel { + backlight = <&backlight>; +}; + +&pmc8380_3_gpios { + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14.dts b/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14.dts index bd75ff89860..68cd318d690 100644 --- a/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14.dts +++ b/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14.dts @@ -6,136 +6,17 @@ /dts-v1/; -#include "x1p42100.dtsi" -#include "x1-asus-zenbook-a14.dtsi" - -/delete-node/ &pmc8380_6; -/delete-node/ &pmc8380_6_thermal; +#include "x1p42100-asus-zenbook-a14.dtsi" / { model = "ASUS Zenbook A14 (UX3407QA)"; - compatible = "asus,zenbook-a14-ux3407qa", "qcom,x1p42100"; - - wcn6855-pmu { - compatible = "qcom,wcn6855-pmu"; - - vddaon-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_wcn_1p9>; - vddpcie1p3-supply = <&vreg_wcn_1p9>; - vddpcie1p9-supply = <&vreg_wcn_1p9>; - vddpmu-supply = <&vreg_wcn_0p95>; - vddpmucx-supply = <&vreg_wcn_0p95>; - vddpmumx-supply = <&vreg_wcn_0p95>; - vddrfa0p95-supply = <&vreg_wcn_0p95>; - vddrfa1p3-supply = <&vreg_wcn_1p9>; - vddrfa1p9-supply = <&vreg_wcn_1p9>; - - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; - pinctrl-names = "default"; - - regulators { - vreg_pmu_rfa_cmn_0p8: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn_0p8"; - }; - - vreg_pmu_aon_0p8: ldo1 { - regulator-name = "vreg_pmu_aon_0p8"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p8: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p8"; - }; - - vreg_pmu_btcmx_0p8: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p8"; - }; - - vreg_pmu_pcie_1p8: ldo5 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo6 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_rfa_0p8: ldo7 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo8 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p7: ldo9 { - regulator-name = "vreg_pmu_rfa_1p7"; - }; - }; - }; + compatible = "asus,zenbook-a14-ux3407qa-oled", "asus,zenbook-a14-ux3407qa", "qcom,x1p42100"; }; -&gpu { - status = "okay"; -}; - -&gpu_zap_shader { - firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcdxkmsucpurwa.mbn"; -}; - -&pcie4_port0 { - wifi@0 { - compatible = "pci17cb,1103"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - - qcom,calibration-variant = "UX3407Q"; - }; -}; - -&remoteproc_adsp { - firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcadsp8380.mbn", - "qcom/x1p42100/ASUSTeK/zenbook-a14/adsp_dtbs.elf"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qccdsp8380.mbn", - "qcom/x1p42100/ASUSTeK/zenbook-a14/cdsp_dtbs.elf"; - - status = "okay"; -}; - -&uart14 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn6855-bt"; - - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - - max-speed = <3000000>; - }; +&panel { + compatible = "samsung,atna40ct06", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; }; diff --git a/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14.dtsi b/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14.dtsi new file mode 100644 index 00000000000..22470a97e1e --- /dev/null +++ b/dts/upstream/src/arm64/qcom/x1p42100-asus-zenbook-a14.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Aleksandrs Vinarskis + */ + +/dts-v1/; + +#include "purwa.dtsi" +#include "x1-asus-zenbook-a14.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + vddaon-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_wcn_1p9>; + vddpcie1p3-supply = <&vreg_wcn_1p9>; + vddpcie1p9-supply = <&vreg_wcn_1p9>; + vddpmu-supply = <&vreg_wcn_0p95>; + vddpmucx-supply = <&vreg_wcn_0p95>; + vddpmumx-supply = <&vreg_wcn_0p95>; + vddrfa0p95-supply = <&vreg_wcn_0p95>; + vddrfa1p3-supply = <&vreg_wcn_1p9>; + vddrfa1p9-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name = "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcdxkmsucpurwa.mbn"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + + qcom,calibration-variant = "UX3407Q"; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qcadsp8380.mbn", + "qcom/x1p42100/ASUSTeK/zenbook-a14/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/ASUSTeK/zenbook-a14/qccdsp8380.mbn", + "qcom/x1p42100/ASUSTeK/zenbook-a14/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + + max-speed = <3000000>; + }; +}; diff --git a/dts/upstream/src/arm64/qcom/x1p42100-crd.dts b/dts/upstream/src/arm64/qcom/x1p42100-crd.dts index cf999c2cf8d..7ed4116b959 100644 --- a/dts/upstream/src/arm64/qcom/x1p42100-crd.dts +++ b/dts/upstream/src/arm64/qcom/x1p42100-crd.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "x1p42100.dtsi" +#include "purwa.dtsi" #include "x1-crd.dtsi" /delete-node/ &pmc8380_6; diff --git a/dts/upstream/src/arm64/qcom/x1p42100-hp-omnibook-x14.dts b/dts/upstream/src/arm64/qcom/x1p42100-hp-omnibook-x14.dts index 6696cab2de3..0f338e457ab 100644 --- a/dts/upstream/src/arm64/qcom/x1p42100-hp-omnibook-x14.dts +++ b/dts/upstream/src/arm64/qcom/x1p42100-hp-omnibook-x14.dts @@ -2,8 +2,8 @@ /dts-v1/; -#include "x1p42100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" #include "x1-hp-omnibook-x14.dtsi" /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; diff --git a/dts/upstream/src/arm64/qcom/x1p42100-lenovo-thinkbook-16.dts b/dts/upstream/src/arm64/qcom/x1p42100-lenovo-thinkbook-16.dts index 1ac46cdc438..3186e79e862 100644 --- a/dts/upstream/src/arm64/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/dts/upstream/src/arm64/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -13,8 +13,8 @@ #include #include -#include "x1p42100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; diff --git a/dts/upstream/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi b/dts/upstream/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi index 7cb5c958aec..529388f6bf2 100644 --- a/dts/upstream/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi +++ b/dts/upstream/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi @@ -66,7 +66,6 @@ compatible = "ovti,ov5645"; reg = <0x3c>; clocks = <&osc25250_clk>; - clock-frequency = <24000000>; vdddo-supply = <&ov5645_vdddo_1v8>; vdda-supply = <&ov5645_vdda_2v8>; vddd-supply = <&ov5645_vddd_1v5>; diff --git a/dts/upstream/src/arm64/renesas/draak.dtsi b/dts/upstream/src/arm64/renesas/draak.dtsi index 71d9f277c96..733a55f77cf 100644 --- a/dts/upstream/src/arm64/renesas/draak.dtsi +++ b/dts/upstream/src/arm64/renesas/draak.dtsi @@ -722,6 +722,11 @@ shared-pin; }; +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm64/renesas/ebisu.dtsi b/dts/upstream/src/arm64/renesas/ebisu.dtsi index c4c86344fb9..adc4449b809 100644 --- a/dts/upstream/src/arm64/renesas/ebisu.dtsi +++ b/dts/upstream/src/arm64/renesas/ebisu.dtsi @@ -858,6 +858,11 @@ shared-pin; }; +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm64/renesas/r8a774a1.dtsi b/dts/upstream/src/arm64/renesas/r8a774a1.dtsi index 6b737d91b32..f0729a482ce 100644 --- a/dts/upstream/src/arm64/renesas/r8a774a1.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a774a1.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a774a1"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -235,17 +236,17 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; pmu_a57 { compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts= , + ; interrupt-affinity = <&a57_0>, <&a57_1>; }; @@ -263,7 +264,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -2863,10 +2863,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a774b1.dtsi b/dts/upstream/src/arm64/renesas/r8a774b1.dtsi index 3f15d656215..c9857ea944e 100644 --- a/dts/upstream/src/arm64/renesas/r8a774b1.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a774b1.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a774b1"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -128,8 +129,8 @@ pmu_a57 { compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&a57_0>, <&a57_1>; }; @@ -147,7 +148,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -2734,10 +2734,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a774c0.dtsi b/dts/upstream/src/arm64/renesas/r8a774c0.dtsi index 55df063cb32..3858f4328e9 100644 --- a/dts/upstream/src/arm64/renesas/r8a774c0.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a774c0.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a774c0"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -119,8 +120,8 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts= , + ; interrupt-affinity = <&a53_0>, <&a53_1>; }; @@ -138,7 +139,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -2000,10 +2000,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a774e1.dtsi b/dts/upstream/src/arm64/renesas/r8a774e1.dtsi index 5d730b488d4..52920a6bf59 100644 --- a/dts/upstream/src/arm64/renesas/r8a774e1.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a774e1.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a774e1"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -297,19 +298,19 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; pmu_a57 { compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; }; @@ -327,7 +328,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -2997,10 +2997,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77951.dtsi b/dts/upstream/src/arm64/renesas/r8a77951.dtsi index c389ebc7e6c..9ad700bde4b 100644 --- a/dts/upstream/src/arm64/renesas/r8a77951.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77951.dtsi @@ -18,6 +18,7 @@ compatible = "renesas,r8a7795"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -312,10 +313,10 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, @@ -324,10 +325,10 @@ pmu_a57 { compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, @@ -348,7 +349,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -365,6 +365,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A7795_CLK_OSC>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7795", "renesas,rcar-gen3-gpio"; @@ -3476,10 +3486,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77960.dtsi b/dts/upstream/src/arm64/renesas/r8a77960.dtsi index 6d039019905..e03b1f7cbfd 100644 --- a/dts/upstream/src/arm64/renesas/r8a77960.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77960.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a7796"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -284,17 +285,17 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; pmu_a57 { compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&a57_0>, <&a57_1>; }; @@ -312,7 +313,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -330,6 +330,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A7796_CLK_OSC>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7796", "renesas,rcar-gen3-gpio"; @@ -2565,6 +2575,23 @@ resets = <&cpg 408>; }; + gpu: gpu@fd000000 { + compatible = "renesas,r8a7796-gpu", + "img,img-gx6250", + "img,img-rogue"; + reg = <0 0xfd000000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A7796_CLK_ZG>, + <&cpg CPG_CORE R8A7796_CLK_S2D1>, + <&cpg CPG_MOD 112>; + clock-names = "core", "mem", "sys"; + power-domains = <&sysc R8A7796_PD_3DG_A>, + <&sysc R8A7796_PD_3DG_B>; + power-domain-names = "a", "b"; + resets = <&cpg 112>; + status = "disabled"; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a7796", "renesas,pcie-rcar-gen3"; @@ -3074,10 +3101,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77961.dtsi b/dts/upstream/src/arm64/renesas/r8a77961.dtsi index 1637b534fc6..31b11bdab69 100644 --- a/dts/upstream/src/arm64/renesas/r8a77961.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77961.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a77961"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -284,17 +285,17 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; pmu_a57 { compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&a57_0>, <&a57_1>; }; @@ -312,7 +313,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -330,6 +330,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77961-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77961_CLK_OSC>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77961", "renesas,rcar-gen3-gpio"; @@ -2445,6 +2455,23 @@ resets = <&cpg 408>; }; + gpu: gpu@fd000000 { + compatible = "renesas,r8a77961-gpu", + "img,img-gx6250", + "img,img-rogue"; + reg = <0 0xfd000000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77961_CLK_ZG>, + <&cpg CPG_CORE R8A77961_CLK_S2D1>, + <&cpg CPG_MOD 112>; + clock-names = "core", "mem", "sys"; + power-domains = <&sysc R8A77961_PD_3DG_A>, + <&sysc R8A77961_PD_3DG_B>; + power-domain-names = "a", "b"; + resets = <&cpg 112>; + status = "disabled"; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a77961", "renesas,pcie-rcar-gen3"; @@ -2895,10 +2922,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77965.dtsi b/dts/upstream/src/arm64/renesas/r8a77965.dtsi index 353a7718708..4e730144e5f 100644 --- a/dts/upstream/src/arm64/renesas/r8a77965.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77965.dtsi @@ -18,6 +18,7 @@ compatible = "renesas,r8a77965"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -163,8 +164,8 @@ pmu_a57 { compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&a57_0>, <&a57_1>; }; @@ -183,7 +184,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -201,6 +201,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77965-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77965_CLK_OSC>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; @@ -2440,6 +2450,23 @@ resets = <&cpg 408>; }; + gpu: gpu@fd000000 { + compatible = "renesas,r8a77965-gpu", + "img,img-ge7800", + "img,img-rogue"; + reg = <0 0xfd000000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77965_CLK_ZG>, + <&cpg CPG_CORE R8A77965_CLK_S2D1>, + <&cpg CPG_MOD 112>; + clock-names = "core", "mem", "sys"; + power-domains = <&sysc R8A77965_PD_3DG_A>, + <&sysc R8A77965_PD_3DG_B>; + power-domain-names = "a", "b"; + resets = <&cpg 112>; + status = "disabled"; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a77965", "renesas,pcie-rcar-gen3"; @@ -2903,10 +2930,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso b/dts/upstream/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso index 0c005660d8d..ecb35257b9a 100644 --- a/dts/upstream/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso +++ b/dts/upstream/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso @@ -170,7 +170,24 @@ }; }; +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&d3p3>; + vqmmc-supply = <&d1p8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &pfc { + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; + vin0_pins_parallel: vin0 { groups = "vin0_data12", "vin0_sync", "vin0_clk", "vin0_clkenb"; function = "vin0"; diff --git a/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts b/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts index 8b594e9e9dc..b7328f9f7d4 100644 --- a/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts +++ b/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts @@ -417,3 +417,8 @@ &scif_clk { clock-frequency = <14745600>; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; diff --git a/dts/upstream/src/arm64/renesas/r8a77970-v3msk.dts b/dts/upstream/src/arm64/renesas/r8a77970-v3msk.dts index 445f5dd7c98..f18d2636061 100644 --- a/dts/upstream/src/arm64/renesas/r8a77970-v3msk.dts +++ b/dts/upstream/src/arm64/renesas/r8a77970-v3msk.dts @@ -146,7 +146,6 @@ hdmi@39 { compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; reg = <0x39>; interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; avdd-supply = <&vcc_d1_8v>; @@ -293,6 +292,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; @@ -300,3 +304,8 @@ status = "okay"; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; diff --git a/dts/upstream/src/arm64/renesas/r8a77970.dtsi b/dts/upstream/src/arm64/renesas/r8a77970.dtsi index e7a5800bf74..1007ee48adc 100644 --- a/dts/upstream/src/arm64/renesas/r8a77970.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77970.dtsi @@ -15,6 +15,7 @@ compatible = "renesas,r8a77970"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { @@ -73,8 +74,8 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&a53_0>, <&a53_1>; }; @@ -92,7 +93,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -110,6 +110,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77970_CLK_OSC>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77970", "renesas,rcar-gen3-gpio"; @@ -1227,10 +1237,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77980-v3hsk.dts b/dts/upstream/src/arm64/renesas/r8a77980-v3hsk.dts index c2692d6fd00..2da63b4daa0 100644 --- a/dts/upstream/src/arm64/renesas/r8a77980-v3hsk.dts +++ b/dts/upstream/src/arm64/renesas/r8a77980-v3hsk.dts @@ -138,7 +138,6 @@ hdmi@39 { compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; reg = <0x39>; interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; avdd-supply = <&vcc1v8_d4>; diff --git a/dts/upstream/src/arm64/renesas/r8a77980.dtsi b/dts/upstream/src/arm64/renesas/r8a77980.dtsi index 964aa14f3e6..8cd7f68d026 100644 --- a/dts/upstream/src/arm64/renesas/r8a77980.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77980.dtsi @@ -15,6 +15,7 @@ compatible = "renesas,r8a77980"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { @@ -100,10 +101,10 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + , + , + ; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; @@ -121,7 +122,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -1631,14 +1631,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77990.dtsi b/dts/upstream/src/arm64/renesas/r8a77990.dtsi index e16ede6eb37..d3698f7e494 100644 --- a/dts/upstream/src/arm64/renesas/r8a77990.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77990.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a77990"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -134,8 +135,8 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-affinity = <&a53_0>, <&a53_1>; }; @@ -153,7 +154,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -171,6 +171,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77990-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77990_CLK_OSC>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77990", "renesas,rcar-gen3-gpio"; @@ -2164,10 +2174,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r8a77995.dtsi b/dts/upstream/src/arm64/renesas/r8a77995.dtsi index b66cd7c90d5..5f3fcef7560 100644 --- a/dts/upstream/src/arm64/renesas/r8a77995.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a77995.dtsi @@ -14,6 +14,7 @@ compatible = "renesas,r8a77995"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* * The external audio clocks are configured as 0 Hz fixed frequency @@ -70,7 +71,7 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; }; psci { @@ -86,7 +87,6 @@ soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -104,6 +104,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77995_CLK_OSC>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77995", "renesas,rcar-gen3-gpio"; @@ -1479,10 +1489,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi index 2c3fb34abb2..4b101a6dc49 100644 --- a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a779a0"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { @@ -60,7 +61,7 @@ pmu_a76 { compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; /* External SCIF clock - to be overridden by boards that provide it */ @@ -72,7 +73,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -90,6 +90,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a779a0-wdt", "renesas,rcar-gen4-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A779A0_CLK_OSC>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1128>; + status = "disabled"; + }; + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779a0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, @@ -2327,6 +2337,23 @@ interrupts = ; }; + gpu: gpu@fd000000 { + compatible = "renesas,r8a779a0-gpu", + "img,img-ge7800", + "img,img-rogue"; + reg = <0 0xfd000000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>, + <&cpg CPG_CORE R8A779A0_CLK_S3D1>, + <&cpg CPG_MOD 0>; + clock-names = "core", "mem", "sys"; + power-domains = <&sysc R8A779A0_PD_3DG_A>, + <&sysc R8A779A0_PD_3DG_B>; + power-domain-names = "a", "b"; + resets = <&cpg 0>; + status = "disabled"; + }; + fcpvd0: fcp@fea10000 { compatible = "renesas,fcpv"; reg = <0 0xfea10000 0 0x200>; @@ -3086,11 +3113,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a779f0.dtsi b/dts/upstream/src/arm64/renesas/r8a779f0.dtsi index b496495c59a..0ebf8e5dd2f 100644 --- a/dts/upstream/src/arm64/renesas/r8a779f0.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a779f0.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a779f0"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; cluster01_opp: opp-table-0 { compatible = "operating-points-v2"; @@ -280,7 +281,7 @@ pmu_a55 { compatible = "arm,cortex-a55-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; psci { @@ -297,7 +298,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -315,6 +315,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A779F0_CLK_OSC>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1128>; + status = "disabled"; + }; + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779f0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, @@ -1340,11 +1350,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi index 4fae063bf91..ff2bd1908a4 100644 --- a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a779g0"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* External Audio clock - to be overridden by boards that provide it */ audio_clkin: audio_clkin { @@ -193,7 +194,7 @@ pmu_a76 { compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; psci { @@ -216,7 +217,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -234,6 +234,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a779g0-wdt", "renesas,rcar-gen4-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A779G0_CLK_OSC>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1128>; + status = "disabled"; + }; + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779g0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, @@ -2601,11 +2611,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-fan-argon40.dtso b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-fan-argon40.dtso new file mode 100644 index 00000000000..c730ef39c7d --- /dev/null +++ b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-fan-argon40.dtso @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for the Argon40 HAT blower fan on connector CN7 + * on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + * + * Example usage: + * + * # Localize hwmon sysfs directory that matches the PWM fan, + * # enable the PWM fan, and configure the fan speed manually. + * r8a779g3-sparrow-hawk$ ls -1 /sys/devices/platform/pwm-fan-ext/hwmon/hwmon?/pwm?_enable + * /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1_enable + * + * # Select mode 2 , enable fan PWM and regulator and keep them enabled. + * # For details, see Linux Documentation/hwmon/pwm-fan.rst + * r8a779g3-sparrow-hawk$ echo 2 > /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1_enable + * + * # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed . + * # Fan speed 101 is about 2/5 of the PWM fan speed: + * r8a779g3-sparrow-hawk$ echo 101 > /sys/devices/platform/pwm-fan-ext/hwmon/hwmon0/pwm1 + */ + +/dts-v1/; +/plugin/; + +&{/} { + pwm-fan-ext { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* PWM period: 33us ~= 30 kHz */ + pwms = <&pwmhat 0 33334 0>; + /* Available cooling levels */ + cooling-levels = <0 50 100 150 200 255>; + fan-shutdown-percent = <100>; + }; +}; + +/* Page 31 / IO_CN */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + status = "okay"; + + pwmhat: pwm@1a { + compatible = "argon40,fan-hat"; + reg = <0x1a>; + #pwm-cells = <3>; + }; +}; diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2-5in.dtso b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2-5in.dtso new file mode 100644 index 00000000000..bf7b531ae9d --- /dev/null +++ b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2-5in.dtso @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for the RPi Display 2 5" MIPI DSI panel connected + * to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + */ + +#include "r8a779g3-sparrow-hawk-rpi-display-2.dtsi" + +&panel { + compatible = "raspberrypi,dsi-5inch", "ilitek,ili9881c"; +}; diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2-7in.dtso b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2-7in.dtso new file mode 100644 index 00000000000..6ec47f213c0 --- /dev/null +++ b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2-7in.dtso @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for the RPi Display 2 7" MIPI DSI panel connected + * to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + */ + +#include "r8a779g3-sparrow-hawk-rpi-display-2.dtsi" + +&panel { + compatible = "raspberrypi,dsi-7inch", "ilitek,ili9881c"; +}; diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2.dtsi b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2.dtsi new file mode 100644 index 00000000000..733333b85a9 --- /dev/null +++ b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk-rpi-display-2.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for the RPi Display 2 MIPI DSI panel connected + * to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025 Marek Vasut + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + display_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&mcu 0 255 0>; + }; + + reg_display: regulator-display { + compatible = "regulator-fixed"; + regulator-name = "rpi-display"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_dsi_touch: regulator-dsi-touch { + compatible = "regulator-fixed"; + gpio = <&mcu 1 GPIO_ACTIVE_HIGH>; + regulator-name = "rpi-touch"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + enable-active-high; + }; +}; + +&i2c0_mux3 { + #address-cells = <1>; + #size-cells = <0>; + + mcu: gpio@45 { + compatible = "raspberrypi,touchscreen-panel-regulator-v2"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <3>; + }; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + AVDD28-supply = <®_dsi_touch>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <1 2>; + }; + }; + }; + + panel: panel@0 { + reg = <0>; + backlight = <&display_bl>; + power-supply = <®_display>; + reset-gpios = <&mcu 0 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts index 1da8e476b21..ff07d984cbf 100644 --- a/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts +++ b/dts/upstream/src/arm64/renesas/r8a779g3-sparrow-hawk.dts @@ -119,13 +119,13 @@ }; /* Page 27 / DSI to Display */ - mini-dp-con { + dp-con { compatible = "dp-connector"; label = "CN6"; type = "full-size"; port { - mini_dp_con_in: endpoint { + dp_con_in: endpoint { remote-endpoint = <&sn65dsi86_out>; }; }; @@ -407,7 +407,7 @@ port@1 { reg = <1>; sn65dsi86_out: endpoint { - remote-endpoint = <&mini_dp_con_in>; + remote-endpoint = <&dp_con_in>; }; }; }; diff --git a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi index 0f20a2d2398..4dc0e5304f7 100644 --- a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi +++ b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r8a779h0"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* External Audio clock - to be overridden by boards that provide it */ audio_clkin: audio_clkin { @@ -158,7 +159,7 @@ pmu-a76 { compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; psci { @@ -181,7 +182,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; bootph-all; #address-cells = <2>; @@ -199,6 +199,16 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a779h0-wdt", "renesas,rcar-gen4-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A779H0_CLK_OSC>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1128>; + status = "disabled"; + }; + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a779h0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, @@ -2212,11 +2222,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; diff --git a/dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts b/dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts new file mode 100644 index 00000000000..a721734fbd5 --- /dev/null +++ b/dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a78000.dtsi" + +/ { + model = "Renesas Ironhide board based on r8a78000"; + compatible = "renesas,ironhide", "renesas,r8a78000"; + + aliases { + serial0 = &hscif0; + }; + + chosen { + stdout-path = "serial0:1843200n8"; + }; + + memory@60600000 { + device_type = "memory"; + /* first 518MiB is reserved for other purposes. */ + reg = <0x0 0x60600000 0x0 0x5fa00000>; + }; + + memory@1080000000 { + device_type = "memory"; + reg = <0x10 0x80000000 0x0 0x80000000>; + }; + + memory@1200000000 { + device_type = "memory"; + reg = <0x12 0x00000000 0x1 0x00000000>; + }; + + memory@1400000000 { + device_type = "memory"; + reg = <0x14 0x00000000 0x1 0x00000000>; + }; + + memory@1600000000 { + device_type = "memory"; + reg = <0x16 0x00000000 0x1 0x00000000>; + }; + + memory@1800000000 { + device_type = "memory"; + reg = <0x18 0x00000000 0x1 0x00000000>; + }; + + memory@1a00000000 { + device_type = "memory"; + reg = <0x1a 0x00000000 0x1 0x00000000>; + }; + + memory@1c00000000 { + device_type = "memory"; + reg = <0x1c 0x00000000 0x1 0x00000000>; + }; + + memory@1e00000000 { + device_type = "memory"; + reg = <0x1e 0x00000000 0x1 0x00000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666600>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <26000000>; +}; diff --git a/dts/upstream/src/arm64/renesas/r8a78000.dtsi b/dts/upstream/src/arm64/renesas/r8a78000.dtsi new file mode 100644 index 00000000000..4c97298fa76 --- /dev/null +++ b/dts/upstream/src/arm64/renesas/r8a78000.dtsi @@ -0,0 +1,787 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car X5H (R8A78000) SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include + +/ { + compatible = "renesas,r8a78000"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a720_0>; + }; + core1 { + cpu = <&a720_1>; + }; + core2 { + cpu = <&a720_2>; + }; + core3 { + cpu = <&a720_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a720_4>; + }; + core1 { + cpu = <&a720_5>; + }; + core2 { + cpu = <&a720_6>; + }; + core3 { + cpu = <&a720_7>; + }; + }; + + cluster2 { + core0 { + cpu = <&a720_8>; + }; + core1 { + cpu = <&a720_9>; + }; + core2 { + cpu = <&a720_10>; + }; + core3 { + cpu = <&a720_11>; + }; + }; + + cluster3 { + core0 { + cpu = <&a720_12>; + }; + core1 { + cpu = <&a720_13>; + }; + core2 { + cpu = <&a720_14>; + }; + core3 { + cpu = <&a720_15>; + }; + }; + + cluster4 { + core0 { + cpu = <&a720_16>; + }; + core1 { + cpu = <&a720_17>; + }; + core2 { + cpu = <&a720_18>; + }; + core3 { + cpu = <&a720_19>; + }; + }; + + cluster5 { + core0 { + cpu = <&a720_20>; + }; + core1 { + cpu = <&a720_21>; + }; + core2 { + cpu = <&a720_22>; + }; + core3 { + cpu = <&a720_23>; + }; + }; + + cluster6 { + core0 { + cpu = <&a720_24>; + }; + core1 { + cpu = <&a720_25>; + }; + core2 { + cpu = <&a720_26>; + }; + core3 { + cpu = <&a720_27>; + }; + }; + + cluster7 { + core0 { + cpu = <&a720_28>; + }; + core1 { + cpu = <&a720_29>; + }; + core2 { + cpu = <&a720_30>; + }; + core3 { + cpu = <&a720_31>; + }; + }; + }; + + a720_0: cpu@0 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x0>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_0>; + }; + + a720_1: cpu@100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_1>; + }; + + a720_2: cpu@200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_2>; + }; + + a720_3: cpu@300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_3>; + }; + + a720_4: cpu@10000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_4>; + }; + + a720_5: cpu@10100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_5>; + }; + + a720_6: cpu@10200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_6>; + }; + + a720_7: cpu@10300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_7>; + }; + + a720_8: cpu@20000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_8>; + }; + + a720_9: cpu@20100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_9>; + }; + + a720_10: cpu@20200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_10>; + }; + + a720_11: cpu@20300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_11>; + }; + + a720_12: cpu@30000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_12>; + }; + + a720_13: cpu@30100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_13>; + }; + + a720_14: cpu@30200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_14>; + }; + + a720_15: cpu@30300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_15>; + }; + + a720_16: cpu@40000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_16>; + }; + + a720_17: cpu@40100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_17>; + }; + + a720_18: cpu@40200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_18>; + }; + + a720_19: cpu@40300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_19>; + }; + + a720_20: cpu@50000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_20>; + }; + + a720_21: cpu@50100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_21>; + }; + + a720_22: cpu@50200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_22>; + }; + + a720_23: cpu@50300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_23>; + }; + + a720_24: cpu@60000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_24>; + }; + + a720_25: cpu@60100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_25>; + }; + + a720_26: cpu@60200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_26>; + }; + + a720_27: cpu@60300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_27>; + }; + + a720_28: cpu@70000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_28>; + }; + + a720_29: cpu@70100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_29>; + }; + + a720_30: cpu@70200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_30>; + }; + + a720_31: cpu@70300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_31>; + }; + + L2_CA720_0: cache-controller-200 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_1: cache-controller-201 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_2: cache-controller-202 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_3: cache-controller-203 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_4: cache-controller-204 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_5: cache-controller-205 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_6: cache-controller-206 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_7: cache-controller-207 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_8: cache-controller-208 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_9: cache-controller-209 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_10: cache-controller-210 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_11: cache-controller-211 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_12: cache-controller-212 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_13: cache-controller-213 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_14: cache-controller-214 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_15: cache-controller-215 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_16: cache-controller-216 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_17: cache-controller-217 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_18: cache-controller-218 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_19: cache-controller-219 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_20: cache-controller-220 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_21: cache-controller-221 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_22: cache-controller-222 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_23: cache-controller-223 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_24: cache-controller-224 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_25: cache-controller-225 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_26: cache-controller-226 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_27: cache-controller-227 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_28: cache-controller-228 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_29: cache-controller-229 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_30: cache-controller-230 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_31: cache-controller-231 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L3_CA720_0: cache-controller-30 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_1: cache-controller-31 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_2: cache-controller-32 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_3: cache-controller-33 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_4: cache-controller-34 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_5: cache-controller-35 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_6: cache-controller-36 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_7: cache-controller-37 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + }; + + /* + * In the early phase, there is no clock control support, + * so assume that the clocks are enabled by default. + * Therefore, dummy clocks are used. + */ + dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <66666000>; + }; + + dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266660000>; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* clock-frequency must be set on board */ + }; + + extalr_clk: extalr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* clock-frequency must be set on board */ + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; /* optional */ + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + prr: chipid@189e0044 { + compatible = "renesas,prr"; + reg = <0 0x189e0044 0 4>; + }; + + /* Application Processors manage View-1 of a GIC-720AE */ + gic: interrupt-controller@39000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x39000000 0 0x10000>, + <0 0x39080000 0 0x800000>; + interrupts = ; + }; + + scif0: serial@c0700000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0700000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + scif1: serial@c0704000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0704000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + scif3: serial@c0708000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0708000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + scif4: serial@c070c000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc070c000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif0: serial@c0710000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0710000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif1: serial@c0714000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0714000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif2: serial@c0718000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0718000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif3: serial@c071c000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc071c000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi b/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi index a3998e5928f..5f5d1b0c31c 100644 --- a/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi @@ -12,6 +12,8 @@ #include "r9a07g043.dtsi" / { + interrupt-parent = <&gic>; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -37,7 +39,7 @@ pmu { compatible = "arm,cortex-a55-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; psci { @@ -47,19 +49,17 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; }; &soc { - interrupt-parent = <&gic>; - cru: video@10830000 { compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru"; reg = <0 0x10830000 0 0x400>; diff --git a/dts/upstream/src/arm64/renesas/r9a07g044.dtsi b/dts/upstream/src/arm64/renesas/r9a07g044.dtsi index ecaa9c4f305..bd52d60bafb 100644 --- a/dts/upstream/src/arm64/renesas/r9a07g044.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a07g044.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a07g044"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; audio_clk1: audio1-clk { compatible = "fixed-clock"; @@ -159,7 +160,7 @@ pmu { compatible = "arm,cortex-a55-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; psci { @@ -169,7 +170,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -1450,11 +1450,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; diff --git a/dts/upstream/src/arm64/renesas/r9a07g054.dtsi b/dts/upstream/src/arm64/renesas/r9a07g054.dtsi index 669eca74da0..4e0256d3201 100644 --- a/dts/upstream/src/arm64/renesas/r9a07g054.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a07g054.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a07g054"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; audio_clk1: audio1-clk { compatible = "fixed-clock"; @@ -159,7 +160,7 @@ pmu { compatible = "arm,cortex-a55-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupts = ; }; psci { @@ -169,7 +170,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -1458,11 +1458,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; diff --git a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi index 16e6ac61441..876de634908 100644 --- a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi @@ -13,6 +13,7 @@ compatible = "renesas,r9a08g045"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; audio_clk1: audio1-clk { compatible = "fixed-clock"; @@ -92,7 +93,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -233,7 +233,6 @@ #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - status = "disabled"; channel@0 { reg = <0>; @@ -272,6 +271,17 @@ }; }; + tsu: thermal@10059000 { + compatible = "renesas,r9a08g045-tsu"; + reg = <0 0x10059000 0 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets = <&cpg R9A08G045_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + io-channels = <&adc 8>; + io-channel-names = "tsu"; + }; + i3c: i3c@1005b000 { compatible = "renesas,r9a08g045-i3c"; reg = <0 0x1005b000 0 0x1000>; @@ -717,6 +727,124 @@ status = "disabled"; }; + phyrst: usbphy-ctrl@11e00000 { + compatible = "renesas,r9a08g045-usbphy-ctrl"; + reg = <0 0x11e00000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets = <&cpg R9A08G045_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + renesas,sysc-pwrrdy = <&sysc 0xd70 0x1>; + status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible = "generic-ohci"; + reg = <0 0x11e10000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11e30000 { + compatible = "generic-ohci"; + reg = <0 0x11e30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11e10100 { + compatible = "generic-ehci"; + reg = <0 0x11e10100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11e30100 { + compatible = "generic-ehci"; + reg = <0 0x11e30100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e10200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e30200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + hsusb: usb@11e20000 { + compatible = "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg = <0 0x11e20000 0 0x10000>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -744,15 +872,52 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu>; + sustainable-power = <423>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + cpu_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_alert1: trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vbattb_xtal: vbattb-xtal { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/dts/upstream/src/arm64/renesas/r9a09g011.dtsi b/dts/upstream/src/arm64/renesas/r9a09g011.dtsi index 9a4cbef704c..42462c138dd 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g011.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a09g011.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a09g011"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ extal_clk: extal { @@ -50,7 +51,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -368,10 +368,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r9a09g047.dtsi b/dts/upstream/src/arm64/renesas/r9a09g047.dtsi index 47d843c7902..7a469de3bb6 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g047.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a09g047.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a09g047"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; audio_extal_clk: audio-clk { compatible = "fixed-clock"; @@ -64,6 +65,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -74,6 +76,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -84,6 +87,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -94,6 +98,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -155,7 +160,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -617,6 +621,19 @@ status = "disabled"; }; + tsu: thermal@14002000 { + compatible = "renesas,r9a09g047-tsu"; + reg = <0 0x14002000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; @@ -1173,13 +1190,44 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r9a09g056.dtsi b/dts/upstream/src/arm64/renesas/r9a09g056.dtsi index 88711087890..8781c2fa731 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g056.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a09g056.dtsi @@ -30,6 +30,7 @@ compatible = "renesas,r9a09g056"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; audio_extal_clk: audio-clk { compatible = "fixed-clock"; @@ -152,6 +153,11 @@ }; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -173,7 +179,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -961,11 +966,11 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r9a09g057.dtsi b/dts/upstream/src/arm64/renesas/r9a09g057.dtsi index 630f7a98df3..4df32d7e999 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g057.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a09g057.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a09g057"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; audio_extal_clk: audio-clk { compatible = "fixed-clock"; @@ -64,6 +65,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -74,6 +76,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -84,6 +87,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -94,6 +98,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -134,6 +139,11 @@ }; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -155,7 +165,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -280,6 +289,32 @@ resets = <&cpg 0x30>; }; + tsu0: thermal@11000000 { + compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x11000000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x109>; + resets = <&cpg 0xf7>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x320>; + }; + + tsu1: thermal@14002000 { + compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x14002000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; + xspi: spi@11030000 { compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; reg = <0 0x11030000 0 0x10000>, @@ -586,6 +621,21 @@ status = "disabled"; }; + rtc: rtc@11c00800 { + compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3"; + reg = <0 0x11c00800 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg 0x79>, <&cpg 0x7a>; + reset-names = "rtc", "rtest"; + status = "disabled"; + }; + scif: serial@11c01400 { compatible = "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; @@ -1307,13 +1357,58 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + sensor1_thermal: sensor1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor2_thermal: sensor2-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu1>; + + cooling-maps { + map0 { + trip = <&sensor2_target>; + cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution = <1024>; + }; + }; + + trips { + sensor2_target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts b/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts index 5c06bce3d5b..445fce156f7 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts @@ -9,6 +9,7 @@ #include #include +#include #include "r9a09g057.dtsi" / { @@ -34,6 +35,18 @@ stdout-path = "serial0:115200n8"; }; + keys: keys { + compatible = "gpio-keys"; + + key-wakeup { + interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "NMI_SW"; + debounce-interval = <20>; + wakeup-source; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -388,6 +401,10 @@ clock-frequency = <24000000>; }; +&rtc { + status = "okay"; +}; + &rtxin_clk { clock-frequency = <32768>; }; diff --git a/dts/upstream/src/arm64/renesas/r9a09g077.dtsi b/dts/upstream/src/arm64/renesas/r9a09g077.dtsi index 7f1aca218c9..f5fa6ca0640 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g077.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a09g077.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a09g077"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -64,6 +65,11 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -71,7 +77,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -265,6 +270,481 @@ status = "disabled"; }; + gmac0: ethernet@80100000 { + compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; + reg = <0 0x80100000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks = <&cpg CPG_MOD 400>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G077_ETCLKB>; + clock-names = "stmmaceth", "pclk", "tx"; + resets = <&cpg 400>, <&cpg 401>; + reset-names = "stmmaceth", "ahb"; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <32>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup0>; + snps,mtl-tx-config = <&mtl_tx_setup0>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0x10>; + snps,map-to-dma-channel = <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority = <0x20>; + snps,map-to-dma-channel = <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority = <0x40>; + snps,map-to-dma-channel = <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority = <0x80>; + snps,map-to-dma-channel = <7>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@92000000 { + compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; + reg = <0 0x92000000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G077_ETCLKB>; + clock-names = "stmmaceth", "pclk", "tx"; + resets = <&cpg 416>, <&cpg 417>; + reset-names = "stmmaceth", "ahb"; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <32>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0x10>; + snps,map-to-dma-channel = <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority = <0x20>; + snps,map-to-dma-channel = <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority = <0x40>; + snps,map-to-dma-channel = <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority = <0x80>; + snps,map-to-dma-channel = <7>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@92010000 { + compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; + reg = <0 0x92010000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks = <&cpg CPG_MOD 417>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G077_ETCLKB>; + clock-names = "stmmaceth", "pclk", "tx"; + resets = <&cpg 418>, <&cpg 419>; + reset-names = "stmmaceth", "ahb"; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <32>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup2>; + snps,mtl-tx-config = <&mtl_tx_setup2>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + + mdio2: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup2: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0x10>; + snps,map-to-dma-channel = <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority = <0x20>; + snps,map-to-dma-channel = <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority = <0x40>; + snps,map-to-dma-channel = <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority = <0x80>; + snps,map-to-dma-channel = <7>; + }; + }; + + mtl_tx_setup2: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + ethss: ethss@80110000 { + compatible = "renesas,r9a09g077-miic"; + reg = <0 0x80110000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G077_ETCLKE>, + <&cpg CPG_CORE R9A09G077_ETCLKB>, + <&cpg CPG_CORE R9A09G077_ETCLKD>, + <&cpg CPG_MOD 403>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + resets = <&cpg 405>, <&cpg 406>; + reset-names = "rst", "crst"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + mii_conv0: mii-conv@0 { + reg = <0>; + status = "disabled"; + }; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g077-cpg-mssr"; reg = <0 0x80280000 0 0x1000>, @@ -299,6 +779,72 @@ interrupts = ; }; + adc0: adc@90014000 { + compatible = "renesas,r9a09g077-adc"; + reg = <0 0x90014000 0 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 206>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc1: adc@90014400 { + compatible = "renesas,r9a09g077-adc"; + reg = <0 0x90014400 0 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 207>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc2: adc@80008000 { + compatible = "renesas,r9a09g077-adc"; + reg = <0 0x80008000 0 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + ohci: usb@92040000 { compatible = "generic-ohci"; reg = <0 0x92040000 0 0x100>; @@ -387,13 +933,20 @@ }; }; + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <16 8 4 0 0 0 0>; + }; + timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r9a09g077m44-rzt2h-evk.dts b/dts/upstream/src/arm64/renesas/r9a09g077m44-rzt2h-evk.dts index 2bf867273ad..b7706d0bc3a 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/dts/upstream/src/arm64/renesas/r9a09g077m44-rzt2h-evk.dts @@ -149,7 +149,77 @@ status = "okay"; }; +&mdio1_phy { + reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>; +}; + +&mdio2_phy { + /* + * PHY2 Reset Configuration: + * + * SW6[1] OFF; SW6[2] ON; SW6[3] OFF - use pin P17_5 for GMAC_RESETOUT2# + */ + reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>; +}; + &pinctrl { + /* + * GMAC2 Pin Configuration: + * + * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 + * SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 + * for Ethernet port 2 + */ + gmac2_pins: gmac2-pins { + pinmux = , /* ETH2_TXCLK */ + , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + , /* ETH2_TXEN */ + , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + , /* ETH2_RXDV */ + , /* ETH2_TXER */ + , /* ETH2_RXER */ + , /* ETH2_CRS */ + , /* ETH2_COL */ + , /* GMAC2_MDC */ + , /* GMAC2_MDIO */ + ; /* ETH2_REFCLK */ + }; + + /* + * GMAC1 Pin Configuration: + * + * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and + * P35_0-P35_2 for Ethernet port 3 + */ + gmac1_pins: gmac1-pins { + pinmux = , /* ETH3_TXCLK */ + , /* ETH3_TXD0 */ + , /* ETH3_TXD1 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + , /* ETH3_TXEN */ + , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + , /* ETH3_RXDV */ + , /* ETH3_TXER */ + , /* ETH3_RXER */ + , /* ETH3_CRS */ + , /* ETH3_COL */ + , /* GMAC1_MDC */ + , /* GMAC1_MDIO */ + ; /* ETH3_REFCLK */ + }; + /* * I2C0 Pin Configuration: * ------------------------ @@ -182,3 +252,31 @@ ; /* OVRCUR */ }; }; + +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; +}; diff --git a/dts/upstream/src/arm64/renesas/r9a09g087.dtsi b/dts/upstream/src/arm64/renesas/r9a09g087.dtsi index f06c19c73ad..361a9235f00 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g087.dtsi +++ b/dts/upstream/src/arm64/renesas/r9a09g087.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a09g087"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -64,6 +65,11 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -71,7 +77,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -265,6 +270,484 @@ status = "disabled"; }; + gmac0: ethernet@80100000 { + compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", + "snps,dwmac-5.20"; + reg = <0 0x80100000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks = <&cpg CPG_MOD 400>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G087_ETCLKB>; + clock-names = "stmmaceth", "pclk", "tx"; + resets = <&cpg 400>, <&cpg 401>; + reset-names = "stmmaceth", "ahb"; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <32>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup0>; + snps,mtl-tx-config = <&mtl_tx_setup0>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0x10>; + snps,map-to-dma-channel = <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority = <0x20>; + snps,map-to-dma-channel = <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority = <0x40>; + snps,map-to-dma-channel = <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority = <0x80>; + snps,map-to-dma-channel = <7>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@92000000 { + compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", + "snps,dwmac-5.20"; + reg = <0 0x92000000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G087_ETCLKB>; + clock-names = "stmmaceth", "pclk", "tx"; + resets = <&cpg 416>, <&cpg 417>; + reset-names = "stmmaceth", "ahb"; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <32>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0x10>; + snps,map-to-dma-channel = <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority = <0x20>; + snps,map-to-dma-channel = <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority = <0x40>; + snps,map-to-dma-channel = <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority = <0x80>; + snps,map-to-dma-channel = <7>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@92010000 { + compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", + "snps,dwmac-5.20"; + reg = <0 0x92010000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "rx-queue-4", "rx-queue-5", + "rx-queue-6", "rx-queue-7", "tx-queue-0", + "tx-queue-1", "tx-queue-2", "tx-queue-3", + "tx-queue-4", "tx-queue-5", "tx-queue-6", + "tx-queue-7"; + clocks = <&cpg CPG_MOD 417>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, + <&cpg CPG_CORE R9A09G087_ETCLKB>; + clock-names = "stmmaceth", "pclk", "tx"; + resets = <&cpg 418>, <&cpg 419>; + reset-names = "stmmaceth", "ahb"; + power-domains = <&cpg>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <32>; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup2>; + snps,mtl-tx-config = <&mtl_tx_setup2>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + status = "disabled"; + + mdio2: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup2: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0x10>; + snps,map-to-dma-channel = <4>; + }; + + queue5 { + snps,dcb-algorithm; + snps,priority = <0x20>; + snps,map-to-dma-channel = <5>; + }; + + queue6 { + snps,dcb-algorithm; + snps,priority = <0x40>; + snps,map-to-dma-channel = <6>; + }; + + queue7 { + snps,dcb-algorithm; + snps,priority = <0x80>; + snps,map-to-dma-channel = <7>; + }; + }; + + mtl_tx_setup2: tx-queues-config { + snps,tx-queues-to-use = <8>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,dcb-algorithm; + }; + + queue3 { + snps,dcb-algorithm; + }; + + queue4 { + snps,dcb-algorithm; + }; + + queue5 { + snps,dcb-algorithm; + }; + + queue6 { + snps,dcb-algorithm; + }; + + queue7 { + snps,dcb-algorithm; + }; + }; + }; + + ethss: ethss@80110000 { + compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic"; + reg = <0 0x80110000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>, + <&cpg CPG_CORE R9A09G087_ETCLKB>, + <&cpg CPG_CORE R9A09G087_ETCLKD>, + <&cpg CPG_MOD 403>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + resets = <&cpg 405>, <&cpg 406>; + reset-names = "rst", "crst"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + mii_conv0: mii-conv@0 { + reg = <0>; + status = "disabled"; + }; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g087-cpg-mssr"; reg = <0 0x80280000 0 0x1000>, @@ -299,6 +782,72 @@ interrupts = ; }; + adc0: adc@90014000 { + compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; + reg = <0 0x90014000 0 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 206>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc1: adc@90014400 { + compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; + reg = <0 0x90014400 0 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 207>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + + adc2: adc@80008000 { + compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; + reg = <0 0x80008000 0 0x400>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names = "adclk", "pclk"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + ohci: usb@92040000 { compatible = "generic-ohci"; reg = <0 0x92040000 0 0x100>; @@ -387,13 +936,20 @@ }; }; + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <16 8 4 0 0 0 0>; + }; + timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupts = , + , + , + , + ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; }; }; diff --git a/dts/upstream/src/arm64/renesas/r9a09g087m44-rzn2h-evk.dts b/dts/upstream/src/arm64/renesas/r9a09g087m44-rzn2h-evk.dts index 084b3a0c805..17c0c79fbd9 100644 --- a/dts/upstream/src/arm64/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/dts/upstream/src/arm64/renesas/r9a09g087m44-rzn2h-evk.dts @@ -186,7 +186,85 @@ status = "okay"; }; +&mdio1_phy { + /* + * PHY3 Reset Configuration: + * + * DSW12[5] OFF; DSW12[6] ON - use pin P03_2 for GMAC_RESETOUT3# + */ + reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>; +}; + +&mdio2_phy { + /* + * PHY2 Reset Configuration: + * + * DSW8[1] ON; DSW8[2] OFF; DSW12[7] OFF; DSW12[8] ON - use pin + * P03_1 for GMAC_RESETOUT2# + */ + reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>; +}; + &pinctrl { + /* + * GMAC2 Pin Configuration: + * + * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 + * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7, + * P31_2, P31_4 and P31_5 are used for Ethernet port 2 + */ + gmac2_pins: gmac2-pins { + pinmux = , /* ETH2_TXCLK */ + , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + , /* ETH2_TXEN */ + , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + , /* ETH2_RXDV */ + , /* ETH2_TXER */ + , /* ETH2_RXER */ + , /* ETH2_CRS */ + , /* ETH2_COL */ + , /* GMAC2_MDC */ + , /* GMAC2_MDIO */ + ; /* ETH2_REFCLK */ + + }; + + /* + * GMAC2 Pin Configuration: + * + * DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6 + * for Ethernet port 3 + * DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3 + */ + gmac1_pins: gmac1-pins { + pinmux = , /* ETH3_TXCLK */ + , /* ETH3_TXD0 */ + , /* ETH3_TXD0 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + , /* ETH3_TXEN */ + , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + , /* ETH3_RXDV */ + , /* ETH3_TXER */ + , /* ETH3_RXER */ + , /* ETH3_CRS */ + , /* ETH3_COL */ + , /* GMAC1_MDC */ + , /* GMAC1_MDIO */ + ; /* ETH3_REFCLK */ + }; + /* * I2C0 Pin Configuration: * ------------------------ @@ -227,3 +305,67 @@ ; /* OVRCUR */ }; }; + +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; + + channel@6 { + reg = <0x6>; + }; + + channel@7 { + reg = <0x7>; + }; + + channel@8 { + reg = <0x8>; + }; + + channel@9 { + reg = <0x9>; + }; + + channel@a { + reg = <0xa>; + }; + + channel@b { + reg = <0xb>; + }; + + channel@c { + reg = <0xc>; + }; + + channel@d { + reg = <0xd>; + }; + + channel@e { + reg = <0xe>; + }; +}; diff --git a/dts/upstream/src/arm64/renesas/rz-smarc-cru-csi-ov5645.dtsi b/dts/upstream/src/arm64/renesas/rz-smarc-cru-csi-ov5645.dtsi index c5bb63c63b4..4d2b0655859 100644 --- a/dts/upstream/src/arm64/renesas/rz-smarc-cru-csi-ov5645.dtsi +++ b/dts/upstream/src/arm64/renesas/rz-smarc-cru-csi-ov5645.dtsi @@ -64,7 +64,6 @@ compatible = "ovti,ov5645"; reg = <0x3c>; clocks = <&ov5645_fixed_clk>; - clock-frequency = <24000000>; vdddo-supply = <&ov5645_vdddo_1v8>; vdda-supply = <&ov5645_vdda_2v8>; vddd-supply = <&ov5645_vddd_1v5>; diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi index 39845faec89..6f25ab61798 100644 --- a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi +++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi @@ -84,10 +84,6 @@ }; }; -&adc { - status = "okay"; -}; - #if SW_CONFIG3 == SW_ON ð0 { pinctrl-0 = <ð0_pins>; diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi index 5e044a4d023..6b0bb2c441a 100644 --- a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi +++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi @@ -92,6 +92,20 @@ clock-frequency = <12288000>; }; +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -132,6 +146,19 @@ }; }; +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + &pinctrl { audio_clock_pins: audio-clock { pins = "AUDIO_CLK1", "AUDIO_CLK2"; @@ -207,6 +234,23 @@ , /* TXD */ ; /* RXD */ }; + + usb0_pins: usb0 { + peri { + pinmux = , /* VBUS */ + ; /* OVC */ + }; + + otg { + pinmux = ; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux = , /* OVC */ + ; /* VBUS */ + }; }; &scif0 { @@ -242,3 +286,16 @@ pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>; status = "okay"; }; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/renesas/rzt2h-n2h-evk-common.dtsi b/dts/upstream/src/arm64/renesas/rzt2h-n2h-evk-common.dtsi index 5c91002c99c..3eed1f3948e 100644 --- a/dts/upstream/src/arm64/renesas/rzt2h-n2h-evk-common.dtsi +++ b/dts/upstream/src/arm64/renesas/rzt2h-n2h-evk-common.dtsi @@ -7,10 +7,14 @@ #include #include +#include +#include #include / { aliases { + ethernet3 = &gmac1; + ethernet2 = &gmac2; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhi0; @@ -70,10 +74,34 @@ status = "okay"; }; +ðss { + status = "okay"; + + renesas,miic-switch-portin = ; +}; + &extal_clk { clock-frequency = <25000000>; }; +&gmac1 { + pinctrl-0 = <&gmac1_pins>; + pinctrl-names = "default"; + phy-handle = <&mdio1_phy>; + phy-mode = "rgmii-id"; + pcs-handle = <&mii_conv3>; + status = "okay"; +}; + +&gmac2 { + pinctrl-0 = <&gmac2_pins>; + pinctrl-names = "default"; + phy-handle = <&mdio2_phy>; + phy-mode = "rgmii-id"; + pcs-handle = <&mii_conv2>; + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; @@ -87,6 +115,48 @@ }; }; +&mdio1 { + mdio1_phy: ethernet-phy@3 { + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg = <3>; + vsc8531,led-0-mode = ; + vsc8531,led-1-mode = ; + reset-assert-us = <2000>; + reset-deassert-us = <15000>; + }; +}; + +&mdio2 { + mdio2_phy: ethernet-phy@2 { + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg = <2>; + vsc8531,led-0-mode = ; + vsc8531,led-1-mode = ; + reset-assert-us = <2000>; + reset-deassert-us = <15000>; + }; +}; + +&mii_conv0 { + renesas,miic-input = ; + status = "okay"; +}; + +&mii_conv1 { + renesas,miic-input = ; + status = "okay"; +}; + +&mii_conv2 { + renesas,miic-input = ; + status = "okay"; +}; + +&mii_conv3 { + renesas,miic-input = ; + status = "okay"; +}; + &ohci { dr_mode = "otg"; status = "okay"; @@ -244,3 +314,82 @@ status = "okay"; timeout-sec = <60>; }; + +/* + * ADC0 AN000 can be connected to a potentiometer on the board or + * exposed on ADC header. + * + * T2H: + * SW17[1] = ON, SW17[2] = OFF - Potentiometer + * SW17[1] = OFF, SW17[2] = ON - CN41 header + * N2H: + * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer + * DSW6[1] = ON, DSW6[2] = OFF - CN3 header + */ +&adc0 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; + +/* + * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. + * + * T2H: + * SW18[1] = ON, SW18[2] = OFF - CN42 header + * SW18[1] = OFF, SW18[2] = ON - mikroBUS + * N2H: + * DSW6[3] = ON, DSW6[4] = OFF - CN4 header + * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS + * + * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[3] = ON, SW18[4] = OFF - CN42 header + * SW18[3] = OFF, SW18[4] = ON - Grove2 + * N2H: + * DSW6[5] = ON, DSW6[6] = OFF - CN4 header + * DSW6[5] = OFF, DSW6[6] = ON - Grove2 + * + * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[5] = ON, SW18[6] = OFF - CN42 header + * SW18[5] = OFF, SW18[6] = ON - Grove2 + * N2H: + * DSW6[7] = ON, DSW6[8] = OFF - CN4 header + * DSW6[7] = OFF, DSW6[8] = ON - Grove2 + */ +&adc1 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; diff --git a/dts/upstream/src/arm64/renesas/salvator-common.dtsi b/dts/upstream/src/arm64/renesas/salvator-common.dtsi index bbb3583372d..fa8bfee07b3 100644 --- a/dts/upstream/src/arm64/renesas/salvator-common.dtsi +++ b/dts/upstream/src/arm64/renesas/salvator-common.dtsi @@ -1004,6 +1004,11 @@ shared-pin; }; +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; + &usb_extal_clk { clock-frequency = <50000000>; }; diff --git a/dts/upstream/src/arm64/renesas/ulcb.dtsi b/dts/upstream/src/arm64/renesas/ulcb.dtsi index 8a30908992a..a9e53b36f1d 100644 --- a/dts/upstream/src/arm64/renesas/ulcb.dtsi +++ b/dts/upstream/src/arm64/renesas/ulcb.dtsi @@ -495,6 +495,11 @@ shared-pin; }; +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; + &usb2_phy1 { pinctrl-0 = <&usb1_pins>; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm64/rockchip/px30.dtsi b/dts/upstream/src/arm64/rockchip/px30.dtsi index 46f64cd33b9..6d457da6fa0 100644 --- a/dts/upstream/src/arm64/rockchip/px30.dtsi +++ b/dts/upstream/src/arm64/rockchip/px30.dtsi @@ -1241,6 +1241,18 @@ status = "disabled"; }; + cif: video-capture@ff490000 { + compatible = "rockchip,px30-vip"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names = "aclk", "hclk", "pclk"; + power-domains = <&power PX30_PD_VI>; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "axi", "ahb", "pclkin"; + status = "disabled"; + }; + isp: isp@ff4a0000 { compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ reg = <0x0 0xff4a0000 0x0 0x8000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts index 7a32972bc24..c1e3098b9a7 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts +++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts @@ -35,7 +35,6 @@ function = LED_FUNCTION_POWER; gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; label = "rockpis:green:power"; - linux,default-trigger = "default-on"; }; blue-led { diff --git a/dts/upstream/src/arm64/rockchip/rk3308-sakurapi-rk3308b.dts b/dts/upstream/src/arm64/rockchip/rk3308-sakurapi-rk3308b.dts index e5e6b800c2d..3473db08b9b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308-sakurapi-rk3308b.dts +++ b/dts/upstream/src/arm64/rockchip/rk3308-sakurapi-rk3308b.dts @@ -199,7 +199,7 @@ compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake>; diff --git a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts index 96c27fc5005..3566c14850c 100644 --- a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts +++ b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts @@ -184,7 +184,7 @@ &gmac2phy { assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - assigned-clock-rate = <50000000>; + assigned-clock-rates = <50000000>; assigned-clocks = <&cru SCLK_MAC2PHY>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3326-odroid-go3.dts b/dts/upstream/src/arm64/rockchip/rk3326-odroid-go3.dts index 35bbaf559ca..6b0563cb4d3 100644 --- a/dts/upstream/src/arm64/rockchip/rk3326-odroid-go3.dts +++ b/dts/upstream/src/arm64/rockchip/rk3326-odroid-go3.dts @@ -14,7 +14,8 @@ joystick_mux_controller: mux-controller { compatible = "gpio-mux"; - pinctrl = <&mux_en_pins>; + pinctrl-0 = <&mux_en_pins>; + pinctrl-names = "default"; #mux-control-cells = <0>; mux-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>, diff --git a/dts/upstream/src/arm64/rockchip/rk3328-evb.dts b/dts/upstream/src/arm64/rockchip/rk3328-evb.dts index 3707df6acf1..76715de886e 100644 --- a/dts/upstream/src/arm64/rockchip/rk3328-evb.dts +++ b/dts/upstream/src/arm64/rockchip/rk3328-evb.dts @@ -101,7 +101,7 @@ &gmac2phy { phy-supply = <&vcc_phy>; clock_in_out = "output"; - assigned-clock-rate = <50000000>; + assigned-clock-rates = <50000000>; assigned-clocks = <&cru SCLK_MAC2PHY>; assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; status = "okay"; diff --git a/dts/upstream/src/arm64/rockchip/rk3368.dtsi b/dts/upstream/src/arm64/rockchip/rk3368.dtsi index 73618df7a88..ce4b112b082 100644 --- a/dts/upstream/src/arm64/rockchip/rk3368.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3368.dtsi @@ -140,6 +140,12 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , @@ -847,6 +853,31 @@ status = "disabled"; }; + vop: vop@ff930000 { + compatible = "rockchip,rk3368-vop"; + reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>; + interrupts = ; + assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + assigned-clock-rates = <400000000>, <200000000>; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3368_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_vop>; + }; + }; + }; + vop_mmu: iommu@ff930300 { compatible = "rockchip,iommu"; reg = <0x0 0xff930300 0x0 0x100>; @@ -858,6 +889,50 @@ status = "disabled"; }; + mipi_dsi: dsi@ff960000 { + compatible = "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x4000>; + interrupts = ; + clocks = <&cru PCLK_MIPI_DSI0>; + clock-names = "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&power RK3368_PD_VIO>; + resets = <&cru SRST_MIPIDSI0>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; + + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + + mipi_out: port@1 { + reg = <1>; + }; + + }; + }; + + dphy: phy@ff968000 { + compatible = "rockchip,rk3368-dsi-dphy"; + reg = <0x0 0xff968000 0x0 0x4000>; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>; + clock-names = "ref", "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_MIPIDPHYTX>; + reset-names = "apb"; + status = "disabled"; + }; + hevc_mmu: iommu@ff9a0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9a0440 0x0 0x40>, diff --git a/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts b/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts index e7d4a2f9a95..b2de018a7d3 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts +++ b/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts @@ -424,9 +424,7 @@ &pcie0 { ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <2>; - pinctrl-names = "default"; status = "okay"; vpcie12v-supply = <&vcc12v_dcin>; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi index 8d94d9f91a5..3a9a10f531b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi @@ -71,7 +71,6 @@ }; &pcie0 { - max-link-speed = <1>; num-lanes = <1>; vpcie3v3-supply = <&vcc3v3_sys>; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-pinebook-pro.dts b/dts/upstream/src/arm64/rockchip/rk3399-pinebook-pro.dts index eaaca08a760..810ab6ff4e6 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-pinebook-pro.dts +++ b/dts/upstream/src/arm64/rockchip/rk3399-pinebook-pro.dts @@ -969,7 +969,6 @@ }; &spi1 { - max-freq = <10000000>; status = "okay"; spiflash: flash@0 { diff --git a/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts b/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts index 2dca1dca20b..5de964d369b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts +++ b/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts @@ -40,13 +40,13 @@ button-up { label = "Volume Up"; linux,code = ; - press-threshold-microvolt = <100000>; + press-threshold-microvolt = <2000>; }; button-down { label = "Volume Down"; linux,code = ; - press-threshold-microvolt = <600000>; + press-threshold-microvolt = <300000>; }; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi index 587e89d7fc5..8299e9d10c7 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi @@ -483,7 +483,7 @@ pinctrl-names = "default"; pinctrl-0 = <&q7_thermal_pin &bios_disable_override_hog_pin>; - gpios { + gpio-pins { bios_disable_override_hog_pin: bios-disable-override-hog-pin { rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts b/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts index 962b8b231c9..6d52e3723a4 100644 --- a/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts +++ b/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts @@ -39,8 +39,8 @@ led-0 { function = LED_FUNCTION_POWER; color = ; + default-state = "on"; gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; }; /* USER_LED2 */ @@ -529,11 +529,11 @@ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; }; - vsel1_gpio: vsel1-gpio { + vsel1_gpio: vsel1-gpio-pin { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; }; - vsel2_gpio: vsel2-gpio { + vsel2_gpio: vsel2-gpio-pin { rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; }; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts index 12eec2c1db2..b3245275615 100644 --- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts +++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts @@ -171,6 +171,10 @@ }; }; +&combphy { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -229,6 +233,14 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pciem1_pins>; + reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + &pinctrl { ethernet { gmac1_rstn_l: gmac1-rstn-l { diff --git a/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts b/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts index c03ae1dd345..0b696d49b71 100644 --- a/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3528-rock-2a.dts @@ -45,7 +45,6 @@ default-state = "on"; function = LED_FUNCTION_STATUS; gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; }; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi index d5f8f7b9bf0..d402f282881 100644 --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -278,10 +279,63 @@ soc { compatible = "simple-bus"; - ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; + ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>; #address-cells = <2>; #size-cells = <2>; + pcie: pcie@fe000000 { + compatible = "rockchip,rk3528-pcie", + "rockchip,rk3568-pcie"; + reg = <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xfe4f0000 0x0 0x010000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xff>; + clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, + <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>, + <&cru CLK_PCIE_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-lanes = <1>; + phys = <&combphy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3528_PD_VPU>; + ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>, + <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>, + <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; + resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = ; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + gic: interrupt-controller@fed01000 { compatible = "arm,gic-400"; reg = <0x0 0xfed01000 0 0x1000>, diff --git a/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b.dtsi index d539570f531..e2f0ccc6dbe 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b.dtsi @@ -435,6 +435,11 @@ }; }; +&i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + &i2s0_8ch { status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts index 6224d72813e..80ac40555e0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts @@ -466,6 +466,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + vcc-supply = <&vcca1v8_pmu>; }; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3.dts b/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3.dts new file mode 100644 index 00000000000..9f3cdaad1c9 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Michael Opdenacker + */ + +/dts-v1/; + +#include "rk3566-tinker-board-3.dtsi" + +/ { + model = "Asus Tinker Board 3"; + compatible = "asus,rk3566-tinker-board-3", "rockchip,rk3566"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3.dtsi new file mode 100644 index 00000000000..d9cb73e71d5 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3.dtsi @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Michael Opdenacker + */ + +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c2 = &i2c2; + mmc1 = &sdmmc0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + act-led { + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + linux,default-trigger="mmc1"; + }; + + rsv-led { + gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + linux,default-trigger="none"; + }; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-5v0-vcc-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&u2_a_vbus_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&eeprom_wc_n>; + }; + + rtc_isl1208: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + interrupt-names = "irq"; + interrupts-extended = <&gpio0 RK_PD3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtcic_int_l>; + }; +}; + +&pinctrl { + eeprom { + eeprom_wc_n: eeprom-wc-n { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtc { + rtcic_int_l: rtcic-int-l { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + u2_a_vbus_en: u2-a-vbus-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + u3_a_vbus_en: u3-a-vbus-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3s.dts new file mode 100644 index 00000000000..3624ebc8a26 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-tinker-board-3s.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Michael Opdenacker + */ + +/dts-v1/; + +#include "rk3566-tinker-board-3.dtsi" + +/ { + model = "Asus Tinker Board 3S"; + compatible = "asus,rk3566-tinker-board-3s", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-9tripod-x3568-v4.dts b/dts/upstream/src/arm64/rockchip/rk3568-9tripod-x3568-v4.dts new file mode 100644 index 00000000000..4db00489be4 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3568-9tripod-x3568-v4.dts @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "9Tripod X3568 v4"; + compatible = "9tripod,x3568-v4", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc2; + rtc0 = &rtc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <50000>; + }; + + button-vol-down { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <500000>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_work: led-0 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + pdm_codec: pdm-codec { + compatible = "dmic-codec"; + num-channels = <2>; + #sound-dai-cells = <0>; + }; + + pdm_sound: pdm-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "microphone"; + + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + + simple-audio-card,codec { + sound-dai = <&pdm_codec>; + }; + }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <300>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + dc_12v: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + pcie30_avdd0v9: regulator-pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en_pin>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + +/* used for usb_host0_xhci */ +&combphy0 { + status = "okay"; +}; + +/* used for usb_host1_xhci */ +&combphy1 { + status = "okay"; +}; + +/* connected to sata2 */ +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + rockchip,mic-in-differential; + }; + }; +}; + +&i2c5 { + status = "okay"; + + rtc0: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +/* used for AP6275S Bluetooth Sound */ +&i2s3_2ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /* Note: The LED polarity is inverted */ + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /* Note: The LED polarity is inverted */ + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pin>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pdm { + status = "okay"; +}; + +&pinctrl { + leds { + led_work_en: led_work_en { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable: wifi-enable { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +/* Required remotectl for IR receiver */ +&pwm7 { + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +/* used for eMMC */ +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +/* used for microSD (TF) Slot */ +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +/* used for AP6275S WiFi */ +&sdmmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* used for Debug */ +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&uart3m1_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4m1_xfer>; + status = "okay"; +}; + +/* used for WiFi/BT AP6275S */ +&uart8 { + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; + status = "okay"; +}; + +&uart9 { + pinctrl-0 = <&uart9m1_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-easepi-r1.dts b/dts/upstream/src/arm64/rockchip/rk3568-easepi-r1.dts new file mode 100644 index 00000000000..12225b631eb --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3568-easepi-r1.dts @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "LinkEase EasePi R1"; + compatible = "linkease,easepi-r1", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&status_led_pin>; + + status_led: led-status { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + dc_12v: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + pcie30_avdd0v9: regulator-pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + regulator-vdd0v95-25glan { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd0v95_25glan_en>; + regulator-name = "vdd0v95_25glan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_nvme: regulator-vcc3v3-nvme { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_nvme_en>; + regulator-name = "vcc3v3_nvme"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-0 = <ð_phy1_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + }; +}; + +/* ETH3 */ +&pcie2x1 { + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +/* ETH2 */ +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +/* M.2 Key for 2280 NVMe */ +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_nvme>; + status = "okay"; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac1 { + eth_phy1_reset_pin: eth-phy1-reset-pin { + rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + status_led_pin: status-led-pin { + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + nvme { + vcc3v3_nvme_en: vcc3v3-nvme-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie-nic { + vdd0v95_25glan_en: vdd0v95-25glan-en { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +/* OTG Only USB2.0, Only device mode */ +&usb_host0_xhci { + dr_mode = "peripheral"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts233.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts233.dts new file mode 100644 index 00000000000..f16d1c62879 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts233.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Heiko Stuebner + */ + +/dts-v1/; + +#include "rk3568-qnap-tsx33.dtsi" + +/ { + model = "Qnap TS-233-2G NAS System 2-Bay"; + compatible = "qnap,ts233", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + }; +}; + +/* connected to sata2 */ +&combphy2 { + status = "okay"; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; +}; + +&i2c1 { + /* eeprom for vital-product-data on the backplane */ + eeprom@56 { + compatible = "giantec,gt24c04a", "atmel,24c04"; + reg = <0x56>; + label = "VPD_BP"; + num-addresses = <2>; + pagesize = <16>; + read-only; + }; +}; + +&leds { + led-1 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + label = "hdd2:green:disk"; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd2_led_pin>; + }; +}; + +&mcu { + compatible = "qnap,ts233-mcu"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@3 { + /* Motorcomm YT8521 phy */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + hdd2_led_pin: hdd2-led-pin { + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata2 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +/* connected to usb_host1_ehci/ohci */ +&usb2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +/* connected to usb_host0_ehci/ohci */ +&usb2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +/* right port backside */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* left port backside */ +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts index 6ae4316761c..d1e3b7e7a28 100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts @@ -6,10 +6,7 @@ /dts-v1/; -#include -#include -#include -#include "rk3568.dtsi" +#include "rk3568-qnap-tsx33.dtsi" / { model = "Qnap TS-433-4G NAS System 4-Bay"; @@ -17,83 +14,6 @@ aliases { ethernet0 = &gmac0; - mmc0 = &sdhci; - rtc0 = &rtc_rv8263; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <©_button_pin>, <&reset_button_pin>; - pinctrl-names = "default"; - - key-copy { - label = "copy"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-reset { - label = "reset"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - label = "hdd1:green:disk"; - linux,default-trigger = "disk-activity"; - pinctrl-names = "default"; - pinctrl-0 = <&hdd1_led_pin>; - }; - - led-1 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; - label = "hdd2:green:disk"; - linux,default-trigger = "disk-activity"; - pinctrl-names = "default"; - pinctrl-0 = <&hdd2_led_pin>; - }; - - led-2 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>; - label = "hdd3:green:disk"; - linux,default-trigger = "disk-activity"; - pinctrl-names = "default"; - pinctrl-0 = <&hdd3_led_pin>; - }; - - led-3 { - color = ; - function = LED_FUNCTION_DISK; - gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; - label = "hdd4:green:disk"; - linux,default-trigger = "disk-activity"; - pinctrl-names = "default"; - pinctrl-0 = <&hdd4_led_pin>; - }; - }; - - dc_12v: regulator-dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; }; vcc3v3_pcie: regulator-vcc3v3-pcie { @@ -105,74 +25,6 @@ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; vin-supply = <&dc_12v>; }; - - vcc3v3_sys: regulator-vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_host: regulator-vcc5v0-host { - compatible = "regulator-fixed"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_otg: regulator-vcc5v0-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sys: regulator-vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb: regulator-vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; -}; - -/* connected to usb_host0_xhci */ -&combphy0 { - status = "okay"; -}; - -/* connected to sata1 */ -&combphy1 { - status = "okay"; }; /* connected to sata2 */ @@ -180,22 +32,6 @@ status = "okay"; }; -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; @@ -212,263 +48,7 @@ status = "okay"; }; -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - /* - * turning this off, breaks access to both - * PCIe controllers, refclk generator perhaps - */ - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1390000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - }; -}; - &i2c1 { - status = "okay"; - - rtc_rv8263: rtc@51 { - compatible = "microcrystal,rv8263"; - reg = <0x51>; - wakeup-source; - }; - - /* eeprom for vital-product-data on the mainboard */ - eeprom@54 { - compatible = "giantec,gt24c04a", "atmel,24c04"; - reg = <0x54>; - label = "VPD_MB"; - num-addresses = <2>; - pagesize = <16>; - read-only; - }; - /* eeprom for vital-product-data on the backplane */ eeprom@56 { compatible = "giantec,gt24c04a", "atmel,24c04"; @@ -480,6 +60,42 @@ }; }; +&leds { + led-1 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + label = "hdd2:green:disk"; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd2_led_pin>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>; + label = "hdd3:green:disk"; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd3_led_pin>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + label = "hdd4:green:disk"; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd4_led_pin>; + }; +}; + +&mcu { + compatible = "qnap,ts433-mcu"; +}; + &mdio0 { rgmii_phy0: ethernet-phy@3 { /* Motorcomm YT8521 phy */ @@ -492,54 +108,6 @@ }; }; -/* - * The MCU can provide system temperature too, but only by polling and of - * course also cannot set trip points. So attach to the cpu thermal-zone - * instead to control the fan. - */ -&cpu_thermal { - trips { - case_fan0: case-fan0 { - hysteresis = <2000>; - temperature = <35000>; - type = "active"; - }; - - case_fan1: case-fan1 { - hysteresis = <2000>; - temperature = <45000>; - type = "active"; - }; - - case_fan2: case-fan2 { - hysteresis = <2000>; - temperature = <65000>; - type = "active"; - }; - }; - - cooling-maps { - /* - * Always provide some air movement, due to small case - * full of harddrives. - */ - map1 { - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - trip = <&case_fan0>; - }; - - map2 { - cooling-device = <&fan 2 3>; - trip = <&case_fan1>; - }; - - map3 { - cooling-device = <&fan 4 THERMAL_NO_LIMIT>; - trip = <&case_fan2>; - }; - }; -}; - &pcie30phy { data-lanes = <1 2>; status = "okay"; @@ -567,21 +135,7 @@ }; }; - keys { - copy_button_pin: copy-button-pin { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - leds { - hdd1_led_pin: hdd1-led-pin { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - hdd2_led_pin: hdd2-led-pin { rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; }; @@ -594,90 +148,12 @@ rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - vccio4-supply = <&vcc_1v8>; - vccio6-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sata1 { - status = "okay"; }; &sata2 { status = "okay"; }; -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -/* - * Connected to an MCU, that provides access to more LEDs, - * buzzer, fan control and more. - */ -&uart0 { - status = "okay"; - - mcu { - compatible = "qnap,ts433-mcu"; - - fan: fan-0 { - #cooling-cells = <2>; - cooling-levels = <0 64 89 128 166 204 221 238>; - }; - }; -}; - -/* - * Pins available on CN3 connector at TTL voltage level (3V3). - * ,_ _. - * |1234| 1=TX 2=VCC - * `----' 3=RX 4=GND - */ -&uart2 { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -/* connected to usb_host0_xhci */ -&usb2phy0_otg { - phy-supply = <&vcc5v0_otg>; - status = "okay"; -}; - &usb2phy1 { status = "okay"; }; @@ -703,12 +179,6 @@ status = "okay"; }; -/* front port */ -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - /* left port backside */ &usb_host1_ehci { status = "okay"; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-tsx33.dtsi b/dts/upstream/src/arm64/rockchip/rk3568-qnap-tsx33.dtsi new file mode 100644 index 00000000000..f009275c72c --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-tsx33.dtsi @@ -0,0 +1,608 @@ +#include +#include +#include +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + rtc0 = &rtc_rv8263; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + pinctrl-names = "default"; + + key-copy { + label = "copy"; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-reset { + label = "reset"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + label = "hdd1:green:disk"; + linux,default-trigger = "disk-activity"; + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_led_pin>; + }; + }; + + dc_12v: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_otg: regulator-vcc5v0-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; +}; + +/* connected to usb_host0_xhci */ +&combphy0 { + status = "okay"; +}; + +/* connected to sata1 */ +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +/* + * The MCU can provide system temperature too, but only by polling and of + * course also cannot set trip points. So attach to the cpu thermal-zone + * instead to control the fan. + */ +&cpu_thermal { + trips { + case_fan0: case-fan0 { + hysteresis = <2000>; + temperature = <35000>; + type = "active"; + }; + + case_fan1: case-fan1 { + hysteresis = <2000>; + temperature = <45000>; + type = "active"; + }; + + case_fan2: case-fan2 { + hysteresis = <2000>; + temperature = <65000>; + type = "active"; + }; + }; + + cooling-maps { + /* + * Always provide some air movement, due to small case + * full of harddrives. + */ + map1 { + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + trip = <&case_fan0>; + }; + + map2 { + cooling-device = <&fan 2 3>; + trip = <&case_fan1>; + }; + + map3 { + cooling-device = <&fan 4 THERMAL_NO_LIMIT>; + trip = <&case_fan2>; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + /* + * turning this off, breaks access to both + * PCIe controllers, refclk generator perhaps + */ + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&i2c1 { + status = "okay"; + + rtc_rv8263: rtc@51 { + compatible = "microcrystal,rv8263"; + reg = <0x51>; + wakeup-source; + }; + + /* eeprom for vital-product-data on the mainboard */ + eeprom@54 { + compatible = "giantec,gt24c04a", "atmel,24c04"; + reg = <0x54>; + label = "VPD_MB"; + num-addresses = <2>; + pagesize = <16>; + read-only; + }; +}; + +&pinctrl { + keys { + copy_button_pin: copy-button-pin { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + hdd1_led_pin: hdd1-led-pin { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio4-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* + * Connected to an MCU, that provides access to more LEDs, + * buzzer, fan control and more. + */ +&uart0 { + status = "okay"; + + mcu: mcu { + fan: fan-0 { + #cooling-cells = <2>; + cooling-levels = <0 64 89 128 166 204 221 238>; + }; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + serial-number@0 { + reg = <0x0 0x13>; + }; + + ext-port@22 { + reg = <0x22 0x2>; + }; + + mac0: mac@24 { + compatible = "mac-base"; + reg = <0x24 0x11>; + #nvmem-cell-cells = <1>; + }; + + mac1: mac@35 { + compatible = "mac-base"; + reg = <0x35 0x11>; + #nvmem-cell-cells = <1>; + }; + + mac2: mac@46 { + compatible = "mac-base"; + reg = <0x46 0x11>; + #nvmem-cell-cells = <1>; + }; + + mac3: mac@57 { + compatible = "mac-base"; + reg = <0x57 0x11>; + #nvmem-cell-cells = <1>; + }; + + mac4: mac@68 { + compatible = "mac-base"; + reg = <0x68 0x11>; + #nvmem-cell-cells = <1>; + }; + + mac5: mac@79 { + compatible = "mac-base"; + reg = <0x79 0x11>; + #nvmem-cell-cells = <1>; + }; + + mac6: mac@8a { + compatible = "mac-base"; + reg = <0x8a 0x11>; + #nvmem-cell-cells = <1>; + }; + + mac7: mac@9b { + compatible = "mac-base"; + reg = <0x9b 0x11>; + #nvmem-cell-cells = <1>; + }; + }; + }; +}; + +/* + * Pins available on CN3 connector at TTL voltage level (3V3). + * ,_ _. + * |1234| 1=TX 2=VCC + * `----' 3=RX 4=GND + */ +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +/* connected to usb_host0_xhci */ +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +/* front port */ +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display-vz.dtso b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display-vz.dtso index 70c23e1bf14..d1a90603191 100644 --- a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display-vz.dtso +++ b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5-display-vz.dtso @@ -11,7 +11,6 @@ #include "rk3568-wolfvision-pf5-display.dtsi" &st7789 { - compatible = "jasonic,jt240mhqs-hwt-ek-e3", - "sitronix,st7789v"; + compatible = "jasonic,jt240mhqs-hwt-ek-e3"; rotation = <270>; }; diff --git a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi index fd2214b6fad..8893b7b6cc9 100644 --- a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi @@ -53,7 +53,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; - clocks = <&scmi_clk 0>; + clocks = <&scmi_clk SCMI_CLK_CPU>; #cooling-cells = <2>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -69,6 +69,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + clocks = <&scmi_clk SCMI_CLK_CPU>; #cooling-cells = <2>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -84,6 +85,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + clocks = <&scmi_clk SCMI_CLK_CPU>; #cooling-cells = <2>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -99,6 +101,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + clocks = <&scmi_clk SCMI_CLK_CPU>; #cooling-cells = <2>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -557,7 +560,7 @@ , ; interrupt-names = "job", "mmu", "gpu"; - clocks = <&scmi_clk 1>, <&cru CLK_GPU>; + clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU>; clock-names = "gpu", "bus"; #cooling-cells = <2>; power-domains = <&power RK3568_PD_GPU>; @@ -616,6 +619,50 @@ #iommu-cells = <0>; }; + vicap: video-capture@fdfe0000 { + compatible = "rockchip,rk3568-vicap"; + reg = <0x0 0xfdfe0000 0x0 0x200>; + interrupts = ; + assigned-clocks = <&cru DCLK_VICAP>; + assigned-clock-rates = <300000000>; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; + clock-names = "aclk", "hclk", "dclk", "iclk"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3568_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, + <&cru SRST_I_VICAP>; + reset-names = "arst", "hrst", "drst", "prst", "irst"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@0 { + reg = <0>; + }; + + vicap_mipi: port@1 { + reg = <1>; + }; + }; + }; + + vicap_mmu: iommu@fdfe0800 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdfe0800 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3568_PD_VI>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + sdmmc2: mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3576-100ask-dshanpi-a1.dts b/dts/upstream/src/arm64/rockchip/rk3576-100ask-dshanpi-a1.dts new file mode 100644 index 00000000000..b19f9b6be6b --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3576-100ask-dshanpi-a1.dts @@ -0,0 +1,838 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model = "100ASK DshanPi A1 board"; + compatible = "100ask,dshanpi-a1", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + es8388_sound: es8388-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "On-board Analog ES8388"; + simple-audio-card,widgets = "Microphone", "Headphone Mic", + "Microphone", "Mic Pads", + "Headphone", "Headphone", + "Line Out", "Line Out"; + simple-audio-card,routing = "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Line Out", "LOUT2", + "Line Out", "ROUT2", + "RINPUT1", "Headphone Mic", + "LINPUT2", "Mic Pads", + "RINPUT2", "Mic Pads"; + simple-audio-card,pin-switches = "Headphone", "Line Out"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "RECOVERY"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + keys-2 { + compatible = "adc-keys"; + io-channels = <&saradc 4>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-user2 { + label = "USER2"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + keys-3 { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_a0_d>; + + button-user1 { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "USER1"; + linux,code = ; + wakeup-source; + }; + }; + + vcc_in: regulator-vcc-12v0-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_m2: regulator-vcc-3v3-m2 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_in>; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren_h>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy0>; + phy-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus>; + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy1>; + phy-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <ð1m0_miim + ð1m0_tx_bus2 + ð1m0_rx_bus2 + ð1m0_rgmii_clk + ð1m0_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_5v0_sys>; + vcc2-supply = <&vcc_5v0_sys>; + vcc3-supply = <&vcc_5v0_sys>; + vcc4-supply = <&vcc_5v0_sys>; + vcc5-supply = <&vcc_5v0_sys>; + vcc6-supply = <&vcc_5v0_sys>; + vcc7-supply = <&vcc_5v0_sys>; + vcc8-supply = <&vcc_5v0_sys>; + vcc9-supply = <&vcc_5v0_sys>; + vcc10-supply = <&vcc_5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; +}; + +&i2c4 { + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru CLK_SAI2_MCLKOUT_TO_IO>; + assigned-clocks = <&cru CLK_SAI2_MCLKOUT_TO_IO>; + assigned-clock-rates = <12288000>; + AVDD-supply = <&vcc_3v3_s0>; + DVDD-supply = <&vcc_3v3_s0>; + HPVDD-supply = <&vcc_3v3_s0>; + PVDD-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset>; + reset-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2>; + status = "okay"; +}; + +&pinctrl { + gmac { + gmac0_rst: gmac0-rst { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + gmac1_rst: gmac1-rst { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-keys { + gpio0_a0_d: gpio0-a0-d { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_reset: pcie-reset { + rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + typec5v_pwren_h: typec5v-pwren-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai2 { + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_pldo2_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc_5v0_sys>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usbdp_phy { + status = "okay"; +}; + +&usb_drd0_dwc3 { + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3576-nanopi-m5.dts b/dts/upstream/src/arm64/rockchip/rk3576-nanopi-m5.dts index cce34c541f7..bb2cc2814b8 100644 --- a/dts/upstream/src/arm64/rockchip/rk3576-nanopi-m5.dts +++ b/dts/upstream/src/arm64/rockchip/rk3576-nanopi-m5.dts @@ -201,6 +201,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hp_det_l>; + simple-audio-card,bitclock-master = <&masterdai>; simple-audio-card,format = "i2s"; simple-audio-card,hp-det-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; simple-audio-card,mclk-fs = <256>; @@ -211,15 +212,16 @@ "Headphones", "HPOR", "IN1P", "Microphone Jack"; simple-audio-card,widgets = - "Headphone", "Headphone Jack", + "Headphone", "Headphones", "Microphone", "Microphone Jack"; simple-audio-card,codec { sound-dai = <&rt5616>; }; - simple-audio-card,cpu { + masterdai: simple-audio-card,cpu { sound-dai = <&sai2>; + system-clock-frequency = <12288000>; }; }; }; @@ -727,10 +729,12 @@ rt5616: audio-codec@1b { compatible = "realtek,rt5616"; reg = <0x1b>; - assigned-clocks = <&cru CLK_SAI2_MCLKOUT>; + assigned-clocks = <&cru CLK_SAI2_MCLKOUT_TO_IO>; assigned-clock-rates = <12288000>; - clocks = <&cru CLK_SAI2_MCLKOUT>; + clocks = <&cru CLK_SAI2_MCLKOUT_TO_IO>; clock-names = "mclk"; + pinctrl-0 = <&sai2m0_mclk>; + pinctrl-names = "default"; #sound-dai-cells = <0>; }; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3576-nanopi-r76s.dts b/dts/upstream/src/arm64/rockchip/rk3576-nanopi-r76s.dts new file mode 100644 index 00000000000..31fbefaecea --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3576-nanopi-r76s.dts @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2025 Tianling Shen + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +#include "rk3576.dtsi" + +/ { + model = "FriendlyElec NanoPi R76S"; + compatible = "friendlyarm,nanopi-r76s", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_but_pin>; + + button-reset { + label = "reset"; + gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + linux,code = ; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led1_h>, <&led_sys_h>, <&led2_h>; + + led-0 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + hdmi-pwr-supply = <&vcc5v_hdmi_tx>; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_rtc_s5"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc5v_dcin: regulator-vcc5v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v_dcin"; + }; + + vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_tx_on_h>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v_hdmi_tx"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc5v0_device_s0: regulator-vcc5v0-device-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_device_s0"; + vin-supply = <&vcc5v_dcin>; + }; + + vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys_s5"; + vin-supply = <&vcc5v_dcin>; + }; + + vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren_h>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb_otg0"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vcc_2v0_pldo_s3"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys_s5>; + vcc2-supply = <&vcc5v0_sys_s5>; + vcc3-supply = <&vcc5v0_sys_s5>; + vcc4-supply = <&vcc5v0_sys_s5>; + vcc5-supply = <&vcc5v0_sys_s5>; + vcc6-supply = <&vcc5v0_sys_s5>; + vcc7-supply = <&vcc5v0_sys_s5>; + vcc8-supply = <&vcc5v0_sys_s5>; + vcc9-supply = <&vcc5v0_sys_s5>; + vcc10-supply = <&vcc5v0_sys_s5>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys_s5>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys_s5>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_perstn>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_perstn>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-keys { + user_but_pin: user-but-pin { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + led_sys_h: led-sys-h { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led1_h: led1-h { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led2_h: led2-h { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_tx_on_h: hdmi-tx-on-h { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie0_perstn: pcie0-perstn { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie1_perstn: pcie1-perstn { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_otg0_pwren_h: usb-otg0-pwren-h { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai6 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + wakeup-source; + status = "okay"; + + rtl8822cs: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_usb_otg0>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_host_h &host_wake_bt_h &bt_reg_on_h>; + }; +}; + +&usbdp_phy { + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "host"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts index 9bc33422ced..7023dc326d0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts +++ b/dts/upstream/src/arm64/rockchip/rk3576-rock-4d.dts @@ -52,9 +52,9 @@ power-led { color = ; + default-state = "on"; function = LED_FUNCTION_STATUS; gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; }; user-led { diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi index a86fc6b4e8c..c72343e7a04 100644 --- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi @@ -1261,7 +1261,7 @@ gpu: gpu@27800000 { compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; - reg = <0x0 0x27800000 0x0 0x200000>; + reg = <0x0 0x27800000 0x0 0x20000>; assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <198000000>; clocks = <&cru CLK_GPU>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi index e2500e31c43..7ab12d1054a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi @@ -1200,7 +1200,7 @@ status = "disabled"; }; - rknn_mmu_1: iommu@fdac9000 { + rknn_mmu_1: iommu@fdaca000 { compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; reg = <0x0 0xfdaca000 0x0 0x100>; interrupts = ; @@ -1230,7 +1230,7 @@ status = "disabled"; }; - rknn_mmu_2: iommu@fdad9000 { + rknn_mmu_2: iommu@fdada000 { compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; reg = <0x0 0xfdada000 0x0 0x100>; interrupts = ; @@ -2181,6 +2181,7 @@ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; reset-names = "core", "bus", "axi", "block", "timer"; + supports-cqe; status = "disabled"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb2-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb2-v10.dts index 91fe810d38d..60ba6ac55b2 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-evb2-v10.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-evb2-v10.dts @@ -25,6 +25,18 @@ stdout-path = "serial2:1500000n8"; }; + dp-con { + compatible = "dp-connector"; + label = "DP OUT"; + type = "full-size"; + + port { + dp_con_in: endpoint { + remote-endpoint = <&dp0_out_con>; + }; + }; + }; + hdmi-con { compatible = "hdmi-connector"; type = "a"; @@ -106,6 +118,24 @@ }; }; +&dp0 { + pinctrl-0 = <&dp0m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp0_in { + dp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_dp0>; + }; +}; + +&dp0_out { + dp0_out_con: endpoint { + remote-endpoint = <&dp_con_in>; + }; +}; + &gpu { mali-supply = <&vdd_gpu_s0>; sram-supply = <&vdd_gpu_mem_s0>; @@ -916,6 +946,17 @@ }; &vop { + /* + * If no dedicated PLL was specified, the GPLL would be automatically + * assigned as the PLL source for dclk_vop2. As the frequency of GPLL + * is 1188 MHz, we can only get typical clock frequencies such as + * 74.25MHz, 148.5MHz, 297MHz, 594MHz. + * + * So here we set the parent clock of VP2 to V0PLL so that we can get + * any frequency. + */ + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; status = "okay"; }; @@ -929,3 +970,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp2 { + vp2_out_dp0: endpoint@a { + reg = ; + remote-endpoint = <&dp0_in_vp2>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts index bc8140883de..172aeabba72 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts @@ -88,8 +88,8 @@ pinctrl-0 = <&led_pins>; power-led1 { + default-state = "on"; gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; }; hdd-led2 { @@ -345,6 +345,10 @@ }; }; +&hdmi1_sound { + status = "okay"; +}; + &hdptxphy1 { status = "okay"; }; @@ -546,6 +550,11 @@ }; }; +/* HDMI1 ("HDMI TX1 8K") audio */ +&i2s6_8ch { + status = "okay"; +}; + &package_thermal { polling-delay = <1000>; @@ -670,6 +679,12 @@ }; }; + mmc { + sdmmc_det_pin: sdmmc-det-pin { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie20x1_2_perstn: pcie20x1-2-perstn { rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -795,12 +810,12 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; - max-frequency = <200000000>; no-sdio; no-mmc; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vccio_sd_s0>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi index 3bbe78810ec..b3e76ad2d86 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -331,12 +331,12 @@ data-role = "dual"; /* fusb302 supports PD Rev 2.0 Ver 1.2 */ pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; - power-role = "sink"; - try-power-role = "sink"; op-sink-microwatt = <1000000>; sink-pdos = , ; + source-pdos = + ; altmodes { displayport { @@ -509,6 +509,12 @@ }; }; + mmc { + sdmmc_det_pin: sdmmc-det-pin { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie2 { pcie2_0_rst: pcie2-0-rst { rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -590,7 +596,6 @@ }; &sdmmc { - max-frequency = <200000000>; no-sdio; no-mmc; bus-width = <4>; @@ -598,6 +603,8 @@ cap-sd-highspeed; cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vccio_sd_s0>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts index 5e984a44120..07a840d9b38 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts @@ -110,6 +110,11 @@ }; }; +&usb_con { + power-role = "dual"; + try-power-role = "sink"; +}; + &usbdp_phy0 { pinctrl-names = "default"; pinctrl-0 = <&usbc_sbu_dc>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts index 8ef01010d98..da13dafcbc8 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts @@ -49,6 +49,10 @@ }; }; +&usb_con { + power-role = "sink"; +}; + &usbdp_phy0 { pinctrl-names = "default"; pinctrl-0 = <&usbc_sbu_dc>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts index c1763835f53..0dd90c74438 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5t.dts @@ -130,6 +130,10 @@ }; }; +&usb_con { + power-role = "source"; +}; + &usbdp_phy0 { pinctrl-names = "default"; pinctrl-0 = <&usbc_sbu_dc>; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts index 0df3e80f2dd..f82050597ab 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts @@ -465,7 +465,6 @@ cap-sd-highspeed; cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; - max-frequency = <150000000>; no-mmc; no-sdio; sd-uhs-sdr104; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts index f5894672fcb..21eb003198f 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts @@ -796,6 +796,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { audio-amplifier { headphone_amplifier_en: headphone-amplifier-en { @@ -979,6 +983,36 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts index 4ec7bc4a9e9..174d299cc6b 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts @@ -11,6 +11,7 @@ / { model = "Indiedroid Nova"; + chassis-type = "embedded"; compatible = "indiedroid,nova", "rockchip,rk3588s"; adc-keys-0 { @@ -189,6 +190,22 @@ cpu-supply = <&vdd_cpu_big1_s0>; }; +&dp0 { + status = "okay"; +}; + +&dp0_in { + dp0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dp0>; + }; +}; + +&dp0_out { + dp0_out_con: endpoint { + remote-endpoint = <&usbdp_phy0_dp_in>; + }; +}; + /* * Add labels for each GPIO pin exposed on the 40 pin header. Note that * voltage of each GPIO pin could be either 3.3v or 1.8v (as noted by @@ -370,28 +387,36 @@ sink-pdos = ; op-sink-microwatt = <1000000>; + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_hs>; }; }; port@1 { reg = <1>; - usbc0_role_sw: endpoint { - remote-endpoint = <&dwc3_0_role_switch>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_ss_out>; }; }; port@2 { reg = <2>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_dp_out>; }; }; }; @@ -405,7 +430,7 @@ clock-output-names = "hym8563"; interrupt-parent = <&gpio0>; interrupts = ; - pinctrl-0 = <&hym8563_int>; + pinctrl-0 = <&hym8563_int>, <&clk32k_in>; pinctrl-names = "default"; wakeup-source; }; @@ -458,8 +483,11 @@ }; &pcie2x1l2 { - pinctrl-0 = <&rtl8111_perstb>; + pinctrl-0 = <&pcie20x1m0_perstn>, <&pcie20x1m0_clkreqn>, + <&pcie20x1m0_waken>; pinctrl-names = "default"; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; status = "okay"; }; @@ -467,6 +495,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { bluetooth-pins { bt_reset: bt-reset { @@ -485,12 +517,6 @@ }; }; - ethernet-pins { - rtl8111_perstb: rtl8111-perstb { - rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - hym8563 { hym8563_int: hym8563-int { @@ -499,13 +525,6 @@ }; }; - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - usb-typec { usbc0_int: usbc0-int { rockchip,pins = @@ -517,6 +536,48 @@ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; }; &saradc { @@ -524,10 +585,10 @@ status = "okay"; }; -/* HS400 modes seemed to cause io errors. */ &sdhci { bus-width = <8>; - no-mmc-hs400; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; no-sd; no-sdio; non-removable; @@ -537,6 +598,7 @@ }; &sdio { + #address-cells = <1>; bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; @@ -548,9 +610,19 @@ no-sd; non-removable; sd-uhs-sdr104; + #size-cells = <0>; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vcc_1v8_s3>; status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-0 = <&wifi_host_wake_irq>; + pinctrl-names = "default"; + }; }; &sdmmc { @@ -896,12 +968,9 @@ status = "okay"; }; -/* DMA seems to interfere with bluetooth device normal operation. */ &uart9 { pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>; pinctrl-names = "default"; - /delete-property/ dma-names; - /delete-property/ dmas; uart-has-rtscts; status = "okay"; @@ -928,9 +997,22 @@ usb-role-switch; status = "okay"; - port { - dwc3_0_role_switch: endpoint { - remote-endpoint = <&usbc0_role_sw>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_host0_xhci_hs: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; + + port@1 { + reg = <1>; + usb_host0_xhci_ss: endpoint { + remote-endpoint = <&usbdp_phy0_ss_in>; + }; }; }; }; @@ -959,14 +1041,24 @@ #address-cells = <1>; #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { + usbdp_phy0_ss_out: endpoint@0 { reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; + remote-endpoint = <&usbc0_ss>; }; - usbdp_phy0_dp_altmode_mux: endpoint@1 { + usbdp_phy0_ss_in: endpoint@1 { reg = <1>; - remote-endpoint = <&dp_altmode_mux>; + remote-endpoint = <&usb_host0_xhci_ss>; + }; + + usbdp_phy0_dp_in: endpoint@2 { + reg = <2>; + remote-endpoint = <&dp0_out_con>; + }; + + usbdp_phy0_dp_out: endpoint@3 { + reg = <3>; + remote-endpoint = <&usbc0_sbu>; }; }; }; @@ -985,3 +1077,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_dp0: endpoint@a { + reg = ; + remote-endpoint = <&dp0_in_vp1>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts index 19a08f7794e..045a853d39e 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -61,9 +61,9 @@ power-led { color = ; + default-state = "on"; function = LED_FUNCTION_POWER; gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; }; }; @@ -228,6 +228,13 @@ regulator-off-in-suspend; }; }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + vcc-supply = <&vcc_3v3_pmu>; + }; }; &i2c2 { @@ -249,12 +256,6 @@ regulator-off-in-suspend; }; }; - - eeprom: eeprom@50 { - compatible = "belling,bl24c16a", "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; }; &i2c3 { @@ -377,6 +378,12 @@ }; }; + mmc { + sdmmc_det_pin: sdmmc-det-pin { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pow_en: pow-en { rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -436,6 +443,8 @@ max-frequency = <150000000>; no-sdio; no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s0>; vqmmc-supply = <&vccio_sd_s0>; @@ -600,7 +609,7 @@ }; }; - vcc_3v3_s3: dcdc-reg8 { + vcc_3v3_pmu: vcc_3v3_s3: dcdc-reg8 { regulator-name = "vcc_3v3_s3"; regulator-always-on; regulator-boot-on; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts index dd7317bab61..b837c4e08ce 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts @@ -473,6 +473,12 @@ }; }; + mmc { + sdmmc_det_pin: sdmmc-det-pin { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 { rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; @@ -533,9 +539,12 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; no-sdio; no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det_pin>; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vccio_sd_s0>; diff --git a/dts/upstream/src/arm64/sprd/sc9860.dtsi b/dts/upstream/src/arm64/sprd/sc9860.dtsi index d2456d633c3..864ef0a1742 100644 --- a/dts/upstream/src/arm64/sprd/sc9860.dtsi +++ b/dts/upstream/src/arm64/sprd/sc9860.dtsi @@ -184,20 +184,6 @@ | IRQ_TYPE_LEVEL_HIGH)>; }; - pmu_gate: pmu-gate { - compatible = "sprd,sc9860-pmu-gate"; - sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ - clocks = <&ext_26m>; - #clock-cells = <1>; - }; - - pll: pll { - compatible = "sprd,sc9860-pll"; - sprd,syscon = <&ana_regs>; /* 0x40400000 */ - clocks = <&pmu_gate 0>; - #clock-cells = <1>; - }; - ap_clk: clock-controller@20000000 { compatible = "sprd,sc9860-ap-clk"; reg = <0 0x20000000 0 0x400>; @@ -214,19 +200,6 @@ #clock-cells = <1>; }; - apahb_gate: apahb-gate { - compatible = "sprd,sc9860-apahb-gate"; - sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - aon_gate: aon-gate { - compatible = "sprd,sc9860-aon-gate"; - sprd,syscon = <&aon_regs>; /* 0x402e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; aonsecure_clk: clock-controller@40880000 { compatible = "sprd,sc9860-aonsecure-clk"; @@ -235,13 +208,6 @@ #clock-cells = <1>; }; - agcp_gate: agcp-gate { - compatible = "sprd,sc9860-agcp-gate"; - sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - gpu_clk: clock-controller@60200000 { compatible = "sprd,sc9860-gpu-clk"; reg = <0 0x60200000 0 0x400>; @@ -256,13 +222,6 @@ #clock-cells = <1>; }; - vsp_gate: vsp-gate { - compatible = "sprd,sc9860-vsp-gate"; - sprd,syscon = <&vsp_regs>; /* 0x61100000 */ - clocks = <&vsp_clk 0>; - #clock-cells = <1>; - }; - cam_clk: clock-controller@62000000 { compatible = "sprd,sc9860-cam-clk"; reg = <0 0x62000000 0 0x4000>; @@ -270,13 +229,6 @@ #clock-cells = <1>; }; - cam_gate: cam-gate { - compatible = "sprd,sc9860-cam-gate"; - sprd,syscon = <&cam_regs>; /* 0x62100000 */ - clocks = <&cam_clk 0>; - #clock-cells = <1>; - }; - disp_clk: clock-controller@63000000 { compatible = "sprd,sc9860-disp-clk"; reg = <0 0x63000000 0 0x400>; @@ -284,20 +236,6 @@ #clock-cells = <1>; }; - disp_gate: disp-gate { - compatible = "sprd,sc9860-disp-gate"; - sprd,syscon = <&disp_regs>; /* 0x63100000 */ - clocks = <&disp_clk 0>; - #clock-cells = <1>; - }; - - apapb_gate: apapb-gate { - compatible = "sprd,sc9860-apapb-gate"; - sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ - clocks = <&ap_clk 0>; - #clock-cells = <1>; - }; - funnel@10001000 { /* SoC Funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x10001000 0 0x1000>; diff --git a/dts/upstream/src/arm64/sprd/whale2.dtsi b/dts/upstream/src/arm64/sprd/whale2.dtsi index a551e14ce82..2ecaa56001b 100644 --- a/dts/upstream/src/arm64/sprd/whale2.dtsi +++ b/dts/upstream/src/arm64/sprd/whale2.dtsi @@ -18,49 +18,67 @@ #size-cells = <2>; ranges; - ap_ahb_regs: syscon@20210000 { - compatible = "syscon"; + apahb_gate: clock-controller@20210000 { reg = <0 0x20210000 0 0x10000>; + compatible = "sprd,sc9860-apahb-gate"; + clocks = <&aon_prediv 0>; + #clock-cells = <1>; }; - pmu_regs: syscon@402b0000 { - compatible = "syscon"; + pmu_gate: clock-controller@402b0000 { reg = <0 0x402b0000 0 0x10000>; + compatible = "sprd,sc9860-pmu-gate"; + clocks = <&ext_26m>; + #clock-cells = <1>; }; - aon_regs: syscon@402e0000 { - compatible = "syscon"; + aon_gate: clock-controller@402e0000 { reg = <0 0x402e0000 0 0x10000>; + compatible = "sprd,sc9860-aon-gate"; + clocks = <&aon_prediv 0>; + #clock-cells = <1>; }; - ana_regs: syscon@40400000 { - compatible = "syscon"; + pll: clock-controller@40400000 { reg = <0 0x40400000 0 0x10000>; + compatible = "sprd,sc9860-pll"; + clocks = <&pmu_gate 0>; + #clock-cells = <1>; }; - agcp_regs: syscon@415e0000 { - compatible = "syscon"; + agcp_gate: clock-controller@415e0000 { reg = <0 0x415e0000 0 0x1000000>; + compatible = "sprd,sc9860-agcp-gate"; + clocks = <&aon_prediv 0>; + #clock-cells = <1>; }; - vsp_regs: syscon@61100000 { - compatible = "syscon"; + vsp_gate: clock-controller@61100000 { reg = <0 0x61100000 0 0x10000>; + compatible = "sprd,sc9860-vsp-gate"; + clocks = <&vsp_clk 0>; + #clock-cells = <1>; }; - cam_regs: syscon@62100000 { - compatible = "syscon"; + cam_gate: clock-controller@62100000 { reg = <0 0x62100000 0 0x10000>; + compatible = "sprd,sc9860-cam-gate"; + clocks = <&cam_clk 0>; + #clock-cells = <1>; }; - disp_regs: syscon@63100000 { - compatible = "syscon"; + disp_gate: clock-controller@63100000 { reg = <0 0x63100000 0 0x10000>; + compatible = "sprd,sc9860-disp-gate"; + clocks = <&disp_clk 0>; + #clock-cells = <1>; }; - ap_apb_regs: syscon@70b00000 { - compatible = "syscon"; + apapb_gate: clock-controller@70b00000 { reg = <0 0x70b00000 0 0x40000>; + compatible = "sprd,sc9860-apapb-gate"; + clocks = <&ap_clk 0>; + #clock-cells = <1>; }; ap-apb@70000000 { diff --git a/dts/upstream/src/arm64/st/stm32mp211.dtsi b/dts/upstream/src/arm64/st/stm32mp211.dtsi index bf888d60cd4..cd078a16065 100644 --- a/dts/upstream/src/arm64/st/stm32mp211.dtsi +++ b/dts/upstream/src/arm64/st/stm32mp211.dtsi @@ -94,18 +94,20 @@ #size-cells = <2>; rifsc: bus@42080000 { - compatible = "simple-bus"; + compatible = "st,stm32mp21-rifsc", "simple-bus"; reg = <0x42080000 0x0 0x1000>; ranges; dma-ranges; #address-cells = <1>; #size-cells = <2>; + #access-controller-cells = <1>; usart2: serial@400e0000 { compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x0 0x400>; interrupts = ; clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; status = "disabled"; }; }; diff --git a/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi b/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi index e0d102eb617..c34cd33cd85 100644 --- a/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi +++ b/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi @@ -38,6 +38,7 @@ bias-disable; drive-push-pull; slew-rate = <3>; + st,io-sync = "data on both edges"; }; pins2 { pinmux = , /* ETH_RGMII_CLK125 */ @@ -53,6 +54,7 @@ , /* ETH_RGMII_RXD3 */ ; /* ETH_RGMII_RX_CTL */ bias-disable; + st,io-sync = "data on both edges"; }; pins4 { pinmux = ; /* ETH_RGMII_RX_CLK */ @@ -142,6 +144,7 @@ bias-disable; drive-push-pull; slew-rate = <3>; + st,io-sync = "data on both edges"; }; pins2 { pinmux = , /* ETH_RGMII_CLK125 */ @@ -164,6 +167,7 @@ , /* ETH_RGMII_RXD3 */ ; /* ETH_RGMII_RX_CTL */ bias-disable; + st,io-sync = "data on both edges"; }; pins5 { pinmux = ; /* ETH_RGMII_RX_CLK */ diff --git a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts index 6e165073f73..bb6d6393d2e 100644 --- a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts +++ b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts @@ -266,6 +266,7 @@ &ommanager { memory-region = <&mm_ospi1>; + memory-region-names = "ospi1"; pinctrl-0 = <&ospi_port1_clk_pins_a &ospi_port1_io03_pins_a &ospi_port1_cs0_pins_a>; diff --git a/dts/upstream/src/arm64/ti/k3-am62-lp-sk-nand.dtso b/dts/upstream/src/arm64/ti/k3-am62-lp-sk-nand.dtso index 173ac60723b..b4daa674eaa 100644 --- a/dts/upstream/src/arm64/ti/k3-am62-lp-sk-nand.dtso +++ b/dts/upstream/src/arm64/ti/k3-am62-lp-sk-nand.dtso @@ -14,7 +14,7 @@ }; &main_pmx0 { - gpmc0_pins_default: gpmc0-pins-default { + gpmc0_pins_default: gpmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */ AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */ diff --git a/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts b/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts index ecfba05fe5c..3e2d8f66953 100644 --- a/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts +++ b/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts @@ -181,6 +181,10 @@ vqmmc-supply = <&vddshv_sdio>; }; +&cpsw3g { + status = "okay"; +}; + &cpsw_port2 { status = "disabled"; }; @@ -276,3 +280,63 @@ &gpmc0 { ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ }; + +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; + status = "okay"; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; + status = "okay"; +}; + +&mcu_pmx0 { + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x038, PIN_INPUT | PIN_WKUP_EN, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x03c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-wakeup-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x040, PIN_INPUT | PIN_WKUP_EN, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi index 40fb3c9e674..c5ee263d34a 100644 --- a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi @@ -76,6 +76,11 @@ assigned-clock-parents = <&k3_clks 157 18>; #clock-cells = <0>; }; + + dss_oldi_io_ctrl: oldi-io-controller@8600 { + compatible = "ti,am625-dss-oldi-io-ctrl", "syscon"; + reg = <0x8600 0x200>; + }; }; dmss: bus@48000000 { @@ -209,6 +214,16 @@ dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, <&main_pktdma 0x7507 0>; dma-names = "tx", "rx1", "rx2"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + rng: rng@40910000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x40910000 0x00 0x7d>; + interrupts = ; + status = "reserved"; /* Reserved for OP-TEE */ + }; }; secure_proxy_sa3: mailbox@43600000 { @@ -723,6 +738,8 @@ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; + status = "disabled"; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; @@ -788,6 +805,53 @@ interrupts = ; status = "disabled"; + oldi-transmitters { + #address-cells = <1>; + #size-cells = <0>; + + oldi0: oldi@0 { + reg = <0>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + oldi0_port0: port@0 { + reg = <0>; + }; + + oldi0_port1: port@1 { + reg = <1>; + }; + }; + }; + + oldi1: oldi@1 { + reg = <1>; + clocks = <&k3_clks 186 0>; + clock-names = "serial"; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + oldi1_port0: port@0 { + reg = <0>; + }; + + oldi1_port1: port@1 { + reg = <1>; + }; + }; + }; + }; + dss_ports: ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi index eeca643fedb..878d267bc66 100644 --- a/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi @@ -211,10 +211,11 @@ &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; + status = "okay"; }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy1>; bootph-all; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi index 5c1284b802a..3d1406acf68 100644 --- a/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi @@ -74,7 +74,7 @@ /* Verdin ETH_2_RGMII */ &cpsw_port2 { phy-handle = <&cpsw3g_phy1>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-ivy.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-ivy.dtsi index 71c29eab0ee..844f59f772e 100644 --- a/dts/upstream/src/arm64/ti/k3-am62-verdin-ivy.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-ivy.dtsi @@ -268,7 +268,7 @@ /* Verdin ETH_2_RGMII */ &cpsw_port2 { phy-handle = <&cpsw3g_phy1>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi index dc4b228a9fd..2a7242a2fef 100644 --- a/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi @@ -845,7 +845,7 @@ /* Verdin ETH_1 (On-module PHY) */ &cpsw_port1 { phy-handle = <&cpsw3g_phy0>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; status = "disabled"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62.dtsi b/dts/upstream/src/arm64/ti/k3-am62.dtsi index 59f6dff552e..b08b7062060 100644 --- a/dts/upstream/src/arm64/ti/k3-am62.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62.dtsi @@ -46,6 +46,28 @@ interrupts = ; }; + system-idle-states { + system_partial_io: system-partial-io { + compatible = "system-idle-state"; + idle-state-name = "off-wake"; + }; + + system_deep_sleep: system-deep-sleep { + compatible = "system-idle-state"; + idle-state-name = "mem"; + }; + + system_mcu_only: system-mcu-only { + compatible = "system-idle-state"; + idle-state-name = "mem-mcu-active"; + }; + + system_standby: system-standby { + compatible = "system-idle-state"; + idle-state-name = "standby"; + }; + }; + cbass_main: bus@f0000 { bootph-all; compatible = "simple-bus"; diff --git a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts index 7028d9835c4..c468b9c5fc0 100644 --- a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts +++ b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts @@ -590,10 +590,11 @@ <&gbe_pmx_obsclk>; assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>; assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>; + status = "okay"; }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-am625-sk-common.dtsi b/dts/upstream/src/arm64/ti/k3-am625-sk-common.dtsi index fe0b98e1d10..9c836268264 100644 --- a/dts/upstream/src/arm64/ti/k3-am625-sk-common.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am625-sk-common.dtsi @@ -212,11 +212,11 @@ &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; + status = "okay"; }; &cpsw_port2 { - /* PCB provides an internal delay of 2ns */ - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy1>; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi index 829f00adea6..9e5b75a4e88 100644 --- a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi @@ -247,6 +247,16 @@ dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, <&main_pktdma 0x7507 0>; dma-names = "tx", "rx1", "rx2"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + rng: rng@40910000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x40910000 0x00 0x7d>; + interrupts = ; + status = "reserved"; /* Reserved for OP-TEE */ + }; }; secure_proxy_sa3: mailbox@43600000 { diff --git a/dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi index b3d012a5a26..b24a63feeab 100644 --- a/dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi @@ -192,7 +192,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy1>; bootph-all; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62a.dtsi b/dts/upstream/src/arm64/ti/k3-am62a.dtsi index 4d79b3e9486..31b2de035f0 100644 --- a/dts/upstream/src/arm64/ti/k3-am62a.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62a.dtsi @@ -46,6 +46,33 @@ interrupts = ; }; + system-idle-states { + system_partial_io: system-partial-io { + compatible = "system-idle-state"; + idle-state-name = "off-wake"; + }; + + system_io_ddr: system-io-ddr { + compatible = "system-idle-state"; + idle-state-name = "mem-deep"; + }; + + system_deep_sleep: system-deep-sleep { + compatible = "system-idle-state"; + idle-state-name = "mem"; + }; + + system_mcu_only: system-mcu-only { + compatible = "system-idle-state"; + idle-state-name = "mem-mcu-active"; + }; + + system_standby: system-standby { + compatible = "system-idle-state"; + idle-state-name = "standby"; + }; + }; + cbass_main: bus@f0000 { compatible = "simple-bus"; #address-cells = <2>; diff --git a/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts b/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts index af591fe6ae4..e99bdbc2e0c 100644 --- a/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts +++ b/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts @@ -233,6 +233,10 @@ &wkup_uart0 { pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + wakeup-source = <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; status = "reserved"; }; @@ -426,6 +430,42 @@ AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ >; }; + + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x038, PIN_INPUT | PIN_WKUP_EN, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-default-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-wakeup-pins { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x040, PIN_INPUT | PIN_WKUP_EN, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; }; &mcu_gpio0 { @@ -731,7 +771,7 @@ &cpsw_port1 { status = "okay"; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; bootph-all; }; @@ -852,4 +892,33 @@ }; }; +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + +&mcu_uart0 { + wakeup-source = <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + #include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/dts/upstream/src/arm64/ti/k3-am62d2-evm.dts b/dts/upstream/src/arm64/ti/k3-am62d2-evm.dts index 83af889e790..2b233bc0323 100644 --- a/dts/upstream/src/arm64/ti/k3-am62d2-evm.dts +++ b/dts/upstream/src/arm64/ti/k3-am62d2-evm.dts @@ -146,6 +146,7 @@ regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_sys>; regulator-boot-on; enable-active-high; gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; @@ -165,14 +166,16 @@ }; vddshv_sdio: regulator-6 { + /* output of TLV7103318QDSERQ1 */ compatible = "regulator-gpio"; regulator-name = "vddshv_sdio"; pinctrl-names = "default"; pinctrl-0 = <&vddshv_sdio_pins_default>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v0>; regulator-boot-on; - gpios = <&main_gpio1 31 GPIO_ACTIVE_HIGH>; + gpios = <&main_gpio0 59 GPIO_ACTIVE_HIGH>; states = <1800000 0x0>, <3300000 0x1>; bootph-all; @@ -198,7 +201,7 @@ pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < - AM62DX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */ + AM62DX_IOPAD(0x01f4, PIN_INPUT, 7) /* (F17) EXTINTn.GPIO1_31 */ >; }; @@ -211,6 +214,14 @@ >; bootph-all; }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x004c, PIN_INPUT, 0) /* (D13) WKUP_I2C0_SCL */ + AM62DX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (E13) WKUP_I2C0_SDA */ + >; + bootph-all; + }; }; /* WKUP UART0 is used for DM firmware logs */ @@ -334,7 +345,7 @@ vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins = < - AM62DX_IOPAD(0x1f4, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO1_31 */ + AM62DX_IOPAD(0x00f0, PIN_INPUT, 7) /* (Y21) GPIO0_59 */ >; bootph-all; }; @@ -355,9 +366,6 @@ pinctrl-single,pins = < AM62DX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */ AM62DX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */ - AM62DX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G19) OSPI0_CSn1 */ - AM62DX_IOPAD(0x0034, PIN_OUTPUT, 0) /* (K20) OSPI0_CSn2 */ - AM62DX_IOPAD(0x0038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */ AM62DX_IOPAD(0x000c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */ AM62DX_IOPAD(0x0010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */ AM62DX_IOPAD(0x0014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */ @@ -461,6 +469,89 @@ status = "okay"; }; +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + tps65224: pmic@48 { + compatible = "ti,tps65224-q1"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells = <2>; + + buck12-supply = <&vcc_3v3_sys>; + buck3-supply = <&vcc_3v3_sys>; + buck4-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&vcc_3v3_sys>; + ldo3-supply = <&vcc_3v3_sys>; + + regulators { + buck12: buck12 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck3: buck3 { + regulator-name = "dvdd1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + buck4: buck4 { + regulator-name = "vdds_ddr"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo1: ldo1 { + regulator-name = "vdda_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo2: ldo2 { + regulator-name = "dvdd3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + + ldo3: ldo3 { + regulator-name = "vddr_core"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + bootph-all; + }; + }; + }; +}; + &sdhci0 { /* eMMC */ non-removable; diff --git a/dts/upstream/src/arm64/ti/k3-am62l-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62l-main.dtsi new file mode 100644 index 00000000000..883beb76ba9 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am62l-main.dtsi @@ -0,0 +1,580 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L main domain peripherals + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01840000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + ranges; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&scmi_pds 34>; + clocks = <&scmi_clk 140>; + clock-names = "gpio"; + ti,ngpio = <126>; + ti,davinci-gpio-unbanked = <0>; + }; + + gpio2: gpio@610000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&scmi_pds 35>; + clocks = <&scmi_clk 141>; + clock-names = "gpio"; + ti,ngpio = <79>; + ti,davinci-gpio-unbanked = <0>; + }; + + timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 58>; + clock-names = "fck"; + power-domains = <&scmi_pds 15>; + ti,timer-pwm; + }; + + timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 63>; + clock-names = "fck"; + power-domains = <&scmi_pds 16>; + ti,timer-pwm; + }; + + timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 77>; + clock-names = "fck"; + power-domains = <&scmi_pds 17>; + ti,timer-pwm; + }; + + timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 82>; + clock-names = "fck"; + power-domains = <&scmi_pds 18>; + ti,timer-pwm; + }; + + uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 89>; + clocks = <&scmi_clk 358>; + clock-names = "fclk"; + status = "disabled"; + }; + + uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 77>; + clocks = <&scmi_clk 312>; + clock-names = "fclk"; + status = "disabled"; + }; + + uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 78>; + clocks = <&scmi_clk 314>; + clock-names = "fclk"; + status = "disabled"; + }; + + uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 79>; + clocks = <&scmi_clk 316>; + clock-names = "fclk"; + status = "disabled"; + }; + + uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 80>; + clocks = <&scmi_clk 318>; + clock-names = "fclk"; + status = "disabled"; + }; + + uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 81>; + clocks = <&scmi_clk 320>; + clock-names = "fclk"; + status = "disabled"; + }; + + uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&scmi_pds 82>; + clocks = <&scmi_clk 322>; + clock-names = "fclk"; + status = "disabled"; + }; + + conf: bus@9000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x09000000 0x380000>; + + phy_gmii_sel: phy@1be000 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x1be000 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@1e9100 { + compatible = "ti,am62-epwm-tbclk"; + reg = <0x1e9100 0x4>; + #clock-cells = <1>; + }; + }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&scmi_clk 331>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&scmi_pds 95>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&scmi_clk 338>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb_phy_ctrl 0x4>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&scmi_pds 96>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,j721e-sdhci-4bit"; + reg = <0x00 0x0fa00000 0x00 0x1000>, + <0x00 0x0fa08000 0x00 0x400>; + interrupts = ; + power-domains = <&scmi_pds 26>; + clocks = <&scmi_clk 106>, <&scmi_clk 109>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&scmi_clk 109>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,itap-del-sel-legacy = <0x0>; + status = "disabled"; + }; + + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x1000>, + <0x00 0xfa18000 0x00 0x400>; + interrupts = ; + power-domains = <&scmi_pds 28>; + clocks = <&scmi_clk 122>, <&scmi_clk 125>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&scmi_clk 125>; + bus-width = <8>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, + <0x00 0x0fa28000 0x00 0x400>; + interrupts = ; + power-domains = <&scmi_pds 27>; + clocks = <&scmi_clk 114>, <&scmi_clk 117>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&scmi_clk 117>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,itap-del-sel-legacy = <0x0>; + status = "disabled"; + }; + + i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 53>; + clocks = <&scmi_clk 246>; + clock-names = "fck"; + status = "disabled"; + }; + + i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 54>; + clocks = <&scmi_clk 250>; + clock-names = "fck"; + status = "disabled"; + }; + + i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 55>; + clocks = <&scmi_clk 254>; + clock-names = "fck"; + status = "disabled"; + }; + + i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 56>; + clocks = <&scmi_clk 258>; + clock-names = "fck"; + status = "disabled"; + }; + + mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&scmi_pds 47>; + clocks = <&scmi_clk 179>, <&scmi_clk 178>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcan1: can@20711000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&scmi_pds 48>; + clocks = <&scmi_clk 185>, <&scmi_clk 184>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcan2: can@20721000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20721000 0x00 0x200>, + <0x00 0x20728000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&scmi_pds 49>; + clocks = <&scmi_clk 191>, <&scmi_clk 190>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 72>; + clocks = <&scmi_clk 299>; + status = "disabled"; + }; + + spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 73>; + clocks = <&scmi_clk 302>; + status = "disabled"; + }; + + spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 74>; + clocks = <&scmi_clk 305>; + status = "disabled"; + }; + + spi3: spi@20130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 75>; + clocks = <&scmi_clk 308>; + status = "disabled"; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&scmi_pds 40>; + clocks = <&epwm_tbclk 0>, <&scmi_clk 164>; + clock-names = "tbclk", "fck"; + #pwm-cells = <3>; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&scmi_pds 41>; + clocks = <&epwm_tbclk 1>, <&scmi_clk 165>; + clock-names = "tbclk", "fck"; + #pwm-cells = <3>; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&scmi_pds 42>; + clocks = <&epwm_tbclk 2>, <&scmi_clk 166>; + clock-names = "tbclk", "fck"; + #pwm-cells = <3>; + status = "disabled"; + }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&scmi_pds 23>; + clocks = <&scmi_clk 99>; + clock-names = "fck"; + #pwm-cells = <3>; + status = "disabled"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&scmi_pds 24>; + clocks = <&scmi_clk 100>; + clock-names = "fck"; + #pwm-cells = <3>; + status = "disabled"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&scmi_pds 25>; + clocks = <&scmi_clk 101>; + clock-names = "fck"; + #pwm-cells = <3>; + status = "disabled"; + }; + + eqep0: counter@23200000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23200000 0x00 0x100>; + power-domains = <&scmi_pds 29>; + clocks = <&scmi_clk 127>; + interrupts = ; + status = "disabled"; + }; + + eqep1: counter@23210000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23210000 0x00 0x100>; + power-domains = <&scmi_pds 30>; + clocks = <&scmi_clk 128>; + interrupts = ; + status = "disabled"; + }; + + eqep2: counter@23220000 { + compatible = "ti,am62-eqep"; + reg = <0x00 0x23220000 0x00 0x100>; + power-domains = <&scmi_pds 31>; + clocks = <&scmi_clk 129>; + interrupts = ; + status = "disabled"; + }; + + elm0: ecc@25010000 { + compatible = "ti,am64-elm"; + reg = <0x00 0x25010000 0x00 0x2000>; + interrupts = ; + power-domains = <&scmi_pds 25>; + clocks = <&scmi_clk 102>; + clock-names = "fck"; + status = "disabled"; + }; + + gpmc0: memory-controller@3b000000 { + compatible = "ti,am64-gpmc"; + power-domains = <&scmi_pds 37>; + clocks = <&scmi_clk 149>; + clock-names = "fck"; + reg = <0x00 0x3b000000 0x00 0x400>, + <0x00 0x50000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = ; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + oc_sram: sram@70800000 { + compatible = "mmio-sram"; + reg = <0x00 0x70800000 0x00 0x10000>; + ranges = <0x00 0x00 0x70800000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x00 0x100>; + bootph-all; + }; + }; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am62l-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am62l-wakeup.dtsi new file mode 100644 index 00000000000..61bfcdcfc66 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am62l-wakeup.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L wakeup domain peripherals + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include + +&cbass_wakeup { + vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&scmi_pds 46>; + #thermal-sensor-cells = <1>; + }; + + pmx0: pinctrl@4084000 { + compatible = "ti,am62l-padconf", "pinctrl-single"; + reg = <0x00 0x4084000 0x00 0x24c>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + #pinctrl-cells = <1>; + }; + + wkup_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x04201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gic500>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&scmi_pds 36>; + clocks = <&scmi_clk 146>; + clock-names = "gpio"; + ti,ngpio = <7>; + ti,davinci-gpio-unbanked = <0>; + status = "disabled"; + }; + + wkup_timer0: timer@2b100000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2b100000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 93>; + clock-names = "fck"; + power-domains = <&scmi_pds 19>; + ti,timer-pwm; + }; + + wkup_timer1: timer@2b110000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2b110000 0x00 0x400>; + interrupts = ; + clocks = <&scmi_clk 98>; + clock-names = "fck"; + power-domains = <&scmi_pds 20>; + ti,timer-pwm; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x2b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&scmi_pds 57>; + clocks = <&scmi_clk 262>; + clock-names = "fck"; + status = "disabled"; + }; + + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names = "rev", "sysc", "syss"; + ranges = <0x00 0x00 0x2b300000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&scmi_pds 83>; + clocks = <&scmi_clk 324>; + clock-names = "fck"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; + status = "disabled"; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x100>; + interrupts = ; + clocks = <&scmi_clk 324>; + assigned-clocks = <&scmi_clk 324>; + clock-names = "fclk"; + status = "disabled"; + }; + }; + + wkup_conf: bus@43000000 { + compatible = "simple-bus"; + ranges = <0x00 0x00 0x43000000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + bootph-all; + }; + + cpsw_mac_syscon: ethernet-mac-syscon@2000 { + compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; + reg = <0x2000 0x8>; + }; + + usb_phy_ctrl: syscon@45000 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x45000 0x1000>; + bootph-all; + }; + }; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am62l.dtsi b/dts/upstream/src/arm64/ti/k3-am62l.dtsi new file mode 100644 index 00000000000..23acdbb301f --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am62l.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree Source for AM62L SoC Family + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model = "Texas Instruments K3 AM62L3 SoC"; + compatible = "ti,am62l3"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82004000>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + bootph-all; + }; + + scmi_pds: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + bootph-all; + }; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + ranges = <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral Window */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Peripheral Window */ + <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */ + <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */ + <0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */ + + /* Wakeup Domain Range */ + <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells = <2>; + #size-cells = <2>; + + cbass_wakeup: bus@a80000 { + compatible = "simple-bus"; + ranges = <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells = <2>; + #size-cells = <2>; + }; + }; +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62l-main.dtsi" +#include "k3-am62l-wakeup.dtsi" diff --git a/dts/upstream/src/arm64/ti/k3-am62l3-evm.dts b/dts/upstream/src/arm64/ti/k3-am62l3-evm.dts new file mode 100644 index 00000000000..cae04cce337 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am62l3-evm.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 Evaluation Module + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + * Data Sheet: https://www.ti.com/lit/pdf/sprspa1 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "k3-am62l3.dtsi" +#include "k3-pinctrl.h" + +/ { + compatible = "ti,am62l3-evm", "ti,am62l3"; + model = "Texas Instruments AM62L3 Evaluation Module"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + bootph-all; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&usr_button_pins_default>; + + usr: button-usr { + label = "User Key"; + linux,code = ; + gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&gpio0 123 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "on"; + }; + }; + + thermal-zones { + wkup0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&vtm0 0>; + + trips { + crit0 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_sys: regulator-1 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-2 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_1v8: regulator-3 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&gpio0 { + bootph-all; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + clock-frequency = <100000>; + status = "okay"; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", "", + "UART1_FET_SEL", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_EN", + "UART1_FET_BUF_EN", "", "", + "", "DSI_GPIO0", "DSI_GPIO1", + "", "BT_UART_WAKE_SOC_3V3", + "USB_TYPEA_OC_INDICATION", "", + "", "WLAN_ALERTn", "", "", + "HDMI_INTn", "TEST_GPIO2", + "MCASP0_FET_EN", "MCASP0_BUF_BT_EN", + "MCASP0_FET_SEL", "DSI_EDID", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + + interrupt-parent = <&gpio0>; + interrupts = <91 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_ioexp_intr_pins_default>; + bootph-all; + }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "BT_EN_SOC", "VOUT0_FET_SEL0", + "", "", + "", "", + "", "", + "WL_LT_EN", "EXP_PS_5V0_EN", + "TP45", "TP48", + "TP46", "TP49", + "TP47", "TP50", + "GPIO_QSPI_NAND_RSTn", "GPIO_HDMI_RSTn", + "GPIO_CPSW1_RST", "GPIO_CPSW2_RST", + "", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; + bootph-all; + }; + +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + typec_pd0: tps658x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; +}; + +&pmx0 { + gpio0_ioexp_intr_pins_default: gpio0-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b0, PIN_INPUT, 7) /* (B12) SPI0_D1.GPIO0_91 */ + >; + bootph-all; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */ + AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */ + >; + bootph-all; + }; + + i2c1_pins_default: i2c1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */ + AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */ + >; + bootph-all; + }; + + i2c2_pins_default: i2c2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01dc, PIN_INPUT_PULLUP, 0) /* (B8) I2C2_SCL */ + AM62LX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D8) I2C2_SDA */ + >; + }; + + mmc0_pins_default: mmc0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (D2) MMC0_CMD */ + AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */ + AM62LX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (D3) MMC0_DAT0 */ + AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */ + AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */ + AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */ + AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */ + AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */ + AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */ + AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */ + >; + bootph-all; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ + AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ + AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ + AM62LX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT_PULLUP, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT_PULLUP, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */ + >; + bootph-all; + }; + + uart0_pins_default: uart0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + >; + bootph-all; + }; + + usb1_default_pins: usb1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */ + >; + }; + + usr_button_pins_default: usr-button-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01ac, PIN_INPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */ + >; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */ + >; + }; + +}; + +&sdhci0 { + /* eMMC */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + non-removable; + status = "okay"; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + vmmc-supply = <&vdd_mmc1>; + disable-wp; + status = "okay"; + bootph-all; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + bootph-all; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_default_pins>; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am62l3.dtsi b/dts/upstream/src/arm64/ti/k3-am62l3.dtsi new file mode 100644 index 00000000000..da220b85151 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am62l3.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 SoC family (Dual Core A53) + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include "k3-am62l.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; + }; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi index 0c05bcf1d77..3cf7c2b3ce2 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi @@ -46,6 +46,24 @@ #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x20000>; + audio_refclk0: clock-controller@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 16>; + #clock-cells = <0>; + }; + + audio_refclk1: clock-controller@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 18>; + assigned-clocks = <&k3_clks 157 18>; + assigned-clock-parents = <&k3_clks 157 34>; + #clock-cells = <0>; + }; + phy_gmii_sel: phy@4044 { compatible = "ti,am654-phy-gmii-sel"; reg = <0x4044 0x8>; diff --git a/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi index 908cc0760e7..13d32cbff18 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi @@ -42,26 +42,6 @@ ti,interrupt-ranges = <5 69 35>; }; -&main_conf { - audio_refclk0: clock-controller@82e0 { - compatible = "ti,am62-audio-refclk"; - reg = <0x82e0 0x4>; - clocks = <&k3_clks 157 0>; - assigned-clocks = <&k3_clks 157 0>; - assigned-clock-parents = <&k3_clks 157 16>; - #clock-cells = <0>; - }; - - audio_refclk1: clock-controller@82e4 { - compatible = "ti,am62-audio-refclk"; - reg = <0x82e4 0x4>; - clocks = <&k3_clks 157 18>; - assigned-clocks = <&k3_clks 157 18>; - assigned-clock-parents = <&k3_clks 157 34>; - #clock-cells = <0>; - }; -}; - &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 22>; diff --git a/dts/upstream/src/arm64/ti/k3-am62p-verdin-dev.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-verdin-dev.dtsi index 0679d76f31b..a0d5b15fc14 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p-verdin-dev.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62p-verdin-dev.dtsi @@ -78,7 +78,7 @@ /* Verdin ETH_2_RGMII */ &cpsw_port2 { phy-handle = <&carrier_eth_phy>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62p-verdin-ivy.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-verdin-ivy.dtsi index 317c8818f9e..04f13edcb16 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p-verdin-ivy.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62p-verdin-ivy.dtsi @@ -275,7 +275,7 @@ /* Verdin ETH_2_RGMII */ &cpsw_port2 { phy-handle = <&carrier_eth_phy>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62p-verdin.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-verdin.dtsi index 99810047614..5e050cbb9ea 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p-verdin.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62p-verdin.dtsi @@ -813,7 +813,7 @@ /* Verdin ETH_1 (On-module PHY) */ &cpsw_port1 { phy-handle = <&som_eth_phy>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; status = "disabled"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62p.dtsi b/dts/upstream/src/arm64/ti/k3-am62p.dtsi index 75a15c368c1..e2c01328eb2 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62p.dtsi @@ -44,6 +44,33 @@ interrupts = ; }; + system-idle-states { + system_partial_io: system-partial-io { + compatible = "system-idle-state"; + idle-state-name = "off-wake"; + }; + + system_io_ddr: system-io-ddr { + compatible = "system-idle-state"; + idle-state-name = "mem-deep"; + }; + + system_deep_sleep: system-deep-sleep { + compatible = "system-idle-state"; + idle-state-name = "mem"; + }; + + system_mcu_only: system-mcu-only { + compatible = "system-idle-state"; + idle-state-name = "mem-mcu-active"; + }; + + system_standby: system-standby { + compatible = "system-idle-state"; + idle-state-name = "standby"; + }; + }; + cbass_main: bus@f0000 { compatible = "simple-bus"; #address-cells = <2>; @@ -59,7 +86,7 @@ <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ - <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ diff --git a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts index a064a632680..ef719c6334f 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts +++ b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts @@ -541,14 +541,14 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; status = "okay"; bootph-all; }; &cpsw_port2 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy1>; status = "okay"; }; @@ -716,12 +716,52 @@ >; bootph-all; }; + + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x038, PIN_INPUT | PIN_WKUP_EN, 0) /* (B3) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /* (E5) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-wakeup-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x040, PIN_INPUT | PIN_WKUP_EN, 0) /* (D4) MCU_MCAN1_RX */ + >; + }; }; &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + wakeup-source = <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; status = "reserved"; bootph-all; }; @@ -763,4 +803,33 @@ status = "okay"; }; +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + +&mcu_uart0 { + wakeup-source = <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + #include "k3-am62p-ti-ipc-firmware.dtsi" diff --git a/dts/upstream/src/arm64/ti/k3-am62p5-var-som.dtsi b/dts/upstream/src/arm64/ti/k3-am62p5-var-som.dtsi index edaa4f99295..fc5a3942cde 100644 --- a/dts/upstream/src/arm64/ti/k3-am62p5-var-som.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62p5-var-som.dtsi @@ -63,18 +63,6 @@ no-map; }; - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x00100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0x00f00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x00100000>; @@ -124,6 +112,38 @@ enable-active-high; regulator-always-on; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "dsp_b"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + }; +}; + +&audio_refclk1 { + assigned-clock-rates = <100000000>; }; &cpsw3g { @@ -161,6 +181,19 @@ pinctrl-0 = <&pinctrl_i2c2>; clock-frequency = <400000>; status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_refclk1>; + clock-names = "mclk"; + AVDD-supply = <®_1v8>; + CPVDD-supply = <®_1v8>; + DBVDD-supply = <®_3v3>; + DCVDD-supply = <®_1v8>; + MICVDD-supply = <®_1v8>; + }; }; &main_i2c3 { @@ -191,6 +224,16 @@ >; }; + pinctrl_mcasp1: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ + AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ + AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + AM62PX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (P24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + pinctrl_mdio1: main-mdio1-default-pins { pinctrl-single,pins = < AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ @@ -279,6 +322,30 @@ pinctrl-0 = <&pinctrl_spi0>; ti,pindir-d0-out-d1-in; status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&main_gpio0>; + interrupts = <48 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; }; &main_uart5 { @@ -292,6 +359,23 @@ }; }; +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* MCASP_IIS_MODE */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + tx-num-evt = <0>; + rx-num-evt = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + &sdhci0 { /* On-module eMMC */ ti,driver-strength-ohm = <50>; @@ -320,44 +404,6 @@ ti,vbus-divider; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; -}; - /* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ &mcu_gpio0 { status = "reserved"; @@ -385,3 +431,5 @@ /* Main UART1 is used by TIFS firmware */ status = "reserved"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" diff --git a/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi index aab74d6019b..d6e70ee1593 100644 --- a/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi @@ -291,7 +291,7 @@ }; &cpsw_port2 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy3>; }; diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi index 58f78c0de29..50ed859ae06 100644 --- a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi @@ -438,7 +438,7 @@ &cpsw_port1 { bootph-all; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi index 02ef1dd92ea..d64fb81b04e 100644 --- a/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi @@ -178,7 +178,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy1>; bootph-all; status = "okay"; diff --git a/dts/upstream/src/arm64/ti/k3-am642-evm.dts b/dts/upstream/src/arm64/ti/k3-am642-evm.dts index 85dcff10493..88093ab7450 100644 --- a/dts/upstream/src/arm64/ti/k3-am642-evm.dts +++ b/dts/upstream/src/arm64/ti/k3-am642-evm.dts @@ -579,13 +579,13 @@ &cpsw_port1 { bootph-all; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; status = "okay"; }; &cpsw_port2 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy3>; status = "okay"; }; @@ -608,6 +608,9 @@ /* ADC is reserved for R5 usage */ status = "reserved"; + dmas = <&main_bcdma 0 0x440f 0>, <&main_bcdma 0 0x4410 0>; + dma-names = "fifo0", "fifo1"; + adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; diff --git a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-peb-c-010.dtso b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-peb-c-010.dtso index 7fc73cfacad..1176a52d560 100644 --- a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-peb-c-010.dtso +++ b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-peb-c-010.dtso @@ -30,13 +30,10 @@ <&main_pktdma 0xc206 15>, /* egress slice 1 */ <&main_pktdma 0xc207 15>, /* egress slice 1 */ <&main_pktdma 0x4200 15>, /* ingress slice 0 */ - <&main_pktdma 0x4201 15>, /* ingress slice 1 */ - <&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */ - <&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", "tx1-0", "tx1-1", "tx1-2", "tx1-3", - "rx0", "rx1", - "rxmgm0", "rxmgm1"; + "rx0", "rx1"; firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", diff --git a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso index 996c42ec425..bea8efa3e90 100644 --- a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso +++ b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso @@ -20,13 +20,13 @@ }; &main_pmx0 { - main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default { + main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */ >; }; - main_spi1_pins_default: main-spi1-pins-default { + main_spi1_pins_default: main-spi1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */ AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ @@ -35,7 +35,7 @@ >; }; - main_uart3_pins_default: main-uart3-pins-default { + main_uart3_pins_default: main-uart3-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */ AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */ @@ -52,7 +52,7 @@ &main_spi1 { pinctrl-names = "default"; pinctrl-0 = <&main_spi1_pins_default>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; status = "okay"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am642-sk.dts b/dts/upstream/src/arm64/ti/k3-am642-sk.dts index 1fb1b91a1ba..34bfa99bd4b 100644 --- a/dts/upstream/src/arm64/ti/k3-am642-sk.dts +++ b/dts/upstream/src/arm64/ti/k3-am642-sk.dts @@ -499,13 +499,13 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; status = "okay"; }; &cpsw_port2 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy1>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 8f64d6272b1..46be6824dd1 100644 --- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -175,6 +175,7 @@ regulator-max-microvolt = <3300000>; gpio = <&main_gpio1 43 GPIO_ACTIVE_HIGH>; enable-active-high; + bootph-all; }; }; @@ -185,7 +186,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; status = "okay"; }; @@ -260,6 +261,7 @@ "", "", "STATUS_OUT_3", "EN_DIG_OUT_4", /* 32-35 */ "", "", "STATUS_OUT_4", "DIG_IN_1", /* 36-39 */ "DIG_IN_2", "DIG_IN_3", "DIG_IN_4"; /* 40- */ + bootph-all; }; &main_gpio1 { @@ -285,6 +287,7 @@ "", "", "", "", /* 60-63 */ "", "", "", "ADC_INT#", /* 64-67 */ "BG95_PWRKEY", "BG95_RESET"; /* 68- */ + bootph-all; line50-hog { /* See also usb0 */ @@ -334,6 +337,7 @@ &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins>; + bootph-pre-ram; status = "okay"; }; @@ -493,6 +497,11 @@ &serdes_ln_ctrl { idle-states = ; + bootph-all; +}; + +&serdes_refclk { + bootph-all; }; &serdes0 { @@ -500,6 +509,7 @@ reg = <0>; #phy-cells = <0>; resets = <&serdes_wiz0 1>; + bootph-all; cdns,num-lanes = <1>; cdns,phy-type = ; }; @@ -512,6 +522,7 @@ cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; + bootph-all; ti,fails-without-test-cd; /* Enabled by overlay */ }; @@ -535,9 +546,11 @@ maximum-speed = "super-speed"; phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; + bootph-all; }; &usbss0 { + bootph-all; ti,vbus-divider; }; @@ -625,6 +638,7 @@ /* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */ AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7) >; + bootph-all; }; main_gpio1_hog_pins: main-gpio1-hog-pins { @@ -748,6 +762,7 @@ /* (#N/A) MMC1_CLKLB */ AM64X_IOPAD(0x0290, PIN_INPUT, 0) >; + bootph-all; }; main_mmc1_reg_pins: main-mmc1-reg-pins { @@ -755,6 +770,7 @@ /* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */ AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) >; + bootph-all; }; main_mmc1_wifi_pwrseq_pins: main-mmc1-wifi-pwrseq-pins { @@ -797,6 +813,7 @@ /* (C16) UART0_TXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) >; + bootph-pre-ram; }; main_uart1_pins: main-uart1-pins { @@ -865,6 +882,7 @@ /* (E19) USB0_DRVVBUS */ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) >; + bootph-all; }; pru_icssg1_mdio_pins: pru-icssg1-mdio-pins { diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi index ff3b2e0b8dd..dde19d0784e 100644 --- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi @@ -17,7 +17,7 @@ device_type = "memory"; /* 1G RAM - default variant */ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; - + bootph-pre-ram; }; reserved_memory: reserved-memory { @@ -54,10 +54,15 @@ }; }; +&fss { + bootph-all; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins>; clock-frequency = <400000>; + bootph-pre-ram; status = "okay"; tmp1075: temperature-sensor@4a { @@ -72,6 +77,7 @@ vcc-supply = <®_1v8>; pagesize = <16>; read-only; + bootph-pre-ram; }; pcf85063: rtc@51 { @@ -89,9 +95,10 @@ }; &ospi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins>; + bootph-all; + status = "okay"; flash@0 { compatible = "jedec,spi-nor"; @@ -99,6 +106,7 @@ spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <84000000>; + bootph-all; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; @@ -121,6 +129,7 @@ disable-wp; no-sdio; no-sd; + bootph-all; ti,driver-strength-ohm = <50>; }; @@ -132,6 +141,7 @@ /* (B18) I2C0_SDA */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) >; + bootph-pre-ram; }; ospi0_pins: ospi0-pins { @@ -159,6 +169,7 @@ /* (N19) OSPI0_DQS */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) >; + bootph-all; }; }; diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi index 42ba3dab2fc..a9a4e7401a4 100644 --- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi @@ -457,10 +457,6 @@ #size-cells = <0>; }; -&mcu_cpsw { - status = "disabled"; -}; - &sdhci1 { status = "okay"; pinctrl-names = "default"; diff --git a/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi index f6d9a577991..74439e0c16a 100644 --- a/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi @@ -354,6 +354,8 @@ "tx4", "tx5", "tx6", "tx7", "rx"; + status = "disabled"; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/ti/k3-am654-base-board.dts b/dts/upstream/src/arm64/ti/k3-am654-base-board.dts index 0c42c486d83..46c58162eca 100644 --- a/dts/upstream/src/arm64/ti/k3-am654-base-board.dts +++ b/dts/upstream/src/arm64/ti/k3-am654-base-board.dts @@ -571,6 +571,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>; + status = "okay"; }; &davinci_mdio { @@ -586,7 +587,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts b/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts index b697035df04..5255e04b9ac 100644 --- a/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts +++ b/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts @@ -249,7 +249,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; status = "okay"; }; diff --git a/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-ads2.dtso b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-ads2.dtso new file mode 100644 index 00000000000..ae5e2b52594 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-ads2.dtso @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Kontron SMARC-sa67 board on the Kontron Eval Carrier 2.2. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_fan_pins_default>; + interrupts-extended = <&main_gpio1 7 IRQ_TYPE_EDGE_FALLING>; + #cooling-cells = <2>; + pwms = <&epwm2 1 4000000 0>; + cooling-levels = <1 128 192 255>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out Jack", + "Microphone", "Microphone Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "LINEOUTR", + "Line Out Jack", "LINEOUTL", + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN2L", "Microphone Jack", + "IN2R", "Microphone Jack"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + + dailink0_master: simple-audio-card,codec { + sound-dai = <&wm8904>; + clocks = <&audio_refclk0>; + }; + }; + + cvcc_1p8v_i2s: regulator-carrier-0 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S0_I2S"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cvcc_1p8v_s0: regulator-carrier-1 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cvcc_3p3v_s0: regulator-carrier-2 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&audio_refclk0 { + status = "okay"; +}; + +&epwm2 { + status = "okay"; +}; + +&main_pmx0 { + pwm_fan_pins_default: pwm-fan-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1ec, PIN_OUTPUT, 8) /* (A22) I2C1_SDA.EHRPWM2_B */ + J722S_IOPAD(0x194, PIN_INPUT, 0) /* (A25) MCASP0_AXR3.GPIO1_7 */ + >; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&mcu_i2c0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wm8904: audio-codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&audio_refclk0>; + clock-names = "mclk"; + AVDD-supply = <&cvcc_1p8v_i2s>; + CPVDD-supply = <&cvcc_1p8v_i2s>; + DBVDD-supply = <&cvcc_1p8v_i2s>; + DCVDD-supply = <&cvcc_1p8v_i2s>; + MICVDD-supply = <&cvcc_1p8v_i2s>; + }; +}; + +&mcu_spi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,fast-read; + vcc-supply = <&cvcc_1p8v_s0>; + }; +}; + +&wkup_i2c0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* SMARC Carrier EEPROM */ + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <&cvcc_3p3v_s0>; + }; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-base.dts b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-base.dts new file mode 100644 index 00000000000..7169d934ada --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-base.dts @@ -0,0 +1,1091 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Kontron SMARC-sAM67 module + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-j722s.dtsi" +#include "k3-serdes.h" + +/ { + compatible = "kontron,sa67", "ti,j722s"; + model = "Kontron SMARC-sAM67"; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart0; + serial2 = &main_uart5; + serial3 = &wkup_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &wkup_rtc0; + }; + + lcd0_backlight: backlight-1 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_backlight_pins_default>; + pwms = <&epwm1 0 50000 0>; + brightness-levels = <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + enable-gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + lcd1_backlight: backlight-2 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_backlight_pins_default>; + pwms = <&epwm1 1 50000 0>; + brightness-levels = <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + enable-gpios = <&main_gpio1 18 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + connector-1 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_connector_pins_default>; + type = "micro"; + id-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + vbus-supply = <&vcc_usb0_vbus>; + + port { + usb0_connector: endpoint { + remote-endpoint = <&usb0_hc>; + }; + }; + + }; + + memory@80000000 { + /* Filled in by bootloader */ + reg = <0x00000000 0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000000 0x00000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x10000000>; + alignment = <0x2000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + }; + + vin_5p0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "V_3V0_5V25_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s5: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_1p8_s5: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s0: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_S0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3p3_s5>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&tps652g1 1 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_s0: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "SDIO_PWR_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3p3_sd_s0_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_vio_s0: regulator-6 { + compatible = "regulator-gpio"; + regulator-name = "V_3V3_1V8_SD_S0"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3p3_sd_vio_s0_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3p3_s0>; + regulator-boot-on; + enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0>, + <1800000 0x1>; + bootph-all; + }; + + vcc_3p3_cam_s0: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_CAM_S0"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3p3_cam_s0_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3p3_s5>; + enable-active-high; + interrupts-extended = <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>; + bootph-all; + }; + + vcc_1p1_s0: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V1_S0"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_1p1_s3>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + /* shared with V_0V75_0V85_CORE_S0 */ + gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_0p85_vcore_s0: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "V_0V75_0V85_CORE_S0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_lcd0_panel: regulator-10 { + compatible = "regulator-fixed"; + regulator-name = "LCD0_VDD_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_lcd0_panel_pins_default>; + enable-active-high; + gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + vcc_lcd1_panel: regulator-11 { + compatible = "regulator-fixed"; + regulator-name = "LCD1_VDD_EN"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_lcd1_panel_pins_default>; + enable-active-high; + gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + }; + + vcc_usb0_vbus: regulator-12 { + compatible = "regulator-fixed"; + regulator-name = "USB0_EN_OC#"; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_usb0_vbus_pins_default>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + }; +}; + +&audio_refclk0 { + pinctrl-names = "default"; + pinctrl-0 = <&audio_refclk0_pins_default>; + status = "disabled"; +}; + +&audio_refclk1 { + pinctrl-names = "default"; + pinctrl-0 = <&audio_refclk1_pins_default>; + status = "disabled"; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw3g_pins_default>, <&rgmii1_pins_default>, + <&rgmii2_pins_default>; + status = "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw3g_mdio_pins_default>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port1 { + phy-connection-type = "rgmii-id"; + phy-handle = <&phy0>; + nvmem-cells = <&base_mac_address 0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&main_gpio0 { + gpio-line-names = + "", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL", + "RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#", + "QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2", + "BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "", + "", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE", + "CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#", + "EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "", + "", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "", + "CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11", + "SLEEP#", "LID#"; + + bootph-all; + status = "okay"; +}; + +&main_gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "", + "GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN", + "LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "", + "GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "", + "USB0_DRVVBUS", "USB1_DRVVBUS"; + + bootph-all; + status = "okay"; +}; + +/* I2C_LOCAL */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <100000>; + bootph-all; + status = "okay"; + + tps652g1: pmic@44 { + compatible = "ti,tps652g1"; + reg = <0x44>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#", + "EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupts-extended = <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>; + + buck1-supply = <&vin_5p0>; + buck2-supply = <&vin_5p0>; + buck3-supply = <&vin_5p0>; + buck4-supply = <&vin_5p0>; + ldo1-supply = <&vin_5p0>; + ldo2-supply = <&vin_5p0>; + ldo3-supply = <&vin_5p0>; + + bootph-all; + + regulators { + vcc_0p85_s0: buck1 { + regulator-name = "V_0V85_S0"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p1_s3: buck2 { + regulator-name = "V_1V1_S3"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s0: buck3 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p2_s0: buck4 { + regulator-name = "V_1V2_S0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_vda_pll_s0: ldo1 { + regulator-name = "V_1V8_VDA_PLL_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s3: ldo2 { + regulator-name = "V_1V8_S3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_ret_s5: ldo3 { + regulator-name = "V_1V8_RET_S5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + system-controller@4a { + compatible = "kontron,sa67mcu", "kontron,sl28cpld"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + + watchdog@4 { + compatible = "kontron,sa67mcu-wdt", "kontron,sl28cpld-wdt"; + reg = <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@8 { + compatible = "kontron,sa67mcu-hwmon"; + reg = <0x8>; + }; + }; +}; + +/* I2C_CAM */ +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <100000>; + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_mux_pins_default>; + + vdd-supply = <&vcc_1p8_s0>; + reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>; + + i2c_cam0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_cam1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_cam2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_cam3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +/* I2C_LCD */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_pmx0 { + audio_refclk0_pins_default: audio-refclk0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0c4, PIN_OUTPUT, 5) /* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ + >; + }; + + audio_refclk1_pins_default: audio-refclk1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + + cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x15c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + cpsw3g_pins_default: cpsw3g-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1b8, PIN_OUTPUT, 1) /* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_COMP */ + >; + }; + + edp_bridge_pins_default: edp-bridge-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x098, PIN_OUTPUT, 7) /* (V21) GPMC0_WAIT0.GPIO0_37 */ + J722S_IOPAD(0x09c, PIN_INPUT, 7) /* (W26) GPMC0_WAIT1.GPIO0_38 */ + >; + }; + + i2c_mux_pins_default: i2c-mux-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x028, PIN_OUTPUT, 7) /* (M27) OSPI0_D7.GPIO0_10 */ + >; + }; + + lcd0_backlight_pins_default: lcd0-backlight-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x074, PIN_OUTPUT, 7) /* (V22) GPMC0_AD14.GPIO0_29 */ + J722S_IOPAD(0x110, PIN_OUTPUT, 4) /* (G27) MMC2_DAT1.EHRPWM1_A */ + >; + }; + + lcd1_backlight_pins_default: lcd1-backlight-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (E19) SPI0_D0.GPIO1_18 */ + J722S_IOPAD(0x114, PIN_OUTPUT, 4) /* (G26) MMC2_DAT0.EHRPWM1_B */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1e0, PIN_INPUT, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x1e4, PIN_INPUT, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0b0, PIN_INPUT, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x0b4, PIN_INPUT, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1d0, PIN_INPUT, 2) /* (E22) UART0_CTSn.I2C3_SCL */ + J722S_IOPAD(0x1d4, PIN_INPUT, 2) /* (B21) UART0_RTSn.I2C3_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0a8, PIN_INPUT, 1) /* (R27) GPMC0_CSn0.I2C4_SCL */ + J722S_IOPAD(0x0ac, PIN_INPUT, 1) /* (P21) GPMC0_CSn1.I2C4_SDA */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1c8, PIN_INPUT, 0) /* (F19) UART0_RXD */ + J722S_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (F20) UART0_TXD */ + >; + bootph-all; + }; + + main_uart5_pins_default: main-uart5-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x108, PIN_INPUT, 3) /* (J27) MMC2_DAT3.UART5_RXD */ + J722S_IOPAD(0x10c, PIN_OUTPUT, 3) /* (H27) MMC2_DAT2.UART5_TXD */ + J722S_IOPAD(0x008, PIN_INPUT, 5) /* (L22) OSPI0_DQS.UART5_CTSn */ + J722S_IOPAD(0x004, PIN_OUTPUT, 5) /* (L23) OSPI0_LBCLKO.UART5_RTSn */ + >; + }; + + mcasp0_pins_default: mcasp0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1a4, PIN_INPUT, 0) /* (D25) MCASP0_ACLKX */ + J722S_IOPAD(0x1a8, PIN_INPUT, 0) /* (C26) MCASP0_AFSX */ + J722S_IOPAD(0x1a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ + J722S_IOPAD(0x19c, PIN_OUTPUT, 0) /* (B25) MCASP0_AXR1 */ + >; + }; + + mcasp2_pins_default: mcasp2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x070, PIN_INPUT, 3) /* (V24) GPMC0_AD13.MCASP2_ACLKX */ + J722S_IOPAD(0x06c, PIN_INPUT, 3) /* (V26) GPMC0_AD12.MCASP2_AFSX */ + J722S_IOPAD(0x05c, PIN_INPUT, 3) /* (U27) GPMC0_AD8.MCASP2_AXR0 */ + J722S_IOPAD(0x060, PIN_OUTPUT, 3) /* (U26) GPMC0_AD9.MCASP2_AXR1 */ + >; + }; + + oldi0_pins_default: oldi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x260, PIN_OUTPUT, 0) /* (AF23) OLDI0_A0N */ + J722S_IOPAD(0x25c, PIN_OUTPUT, 0) /* (AG24) OLDI0_A0P */ + J722S_IOPAD(0x268, PIN_OUTPUT, 0) /* (AG22) OLDI0_A1N */ + J722S_IOPAD(0x264, PIN_OUTPUT, 0) /* (AG23) OLDI0_A1P */ + J722S_IOPAD(0x270, PIN_OUTPUT, 0) /* (AB20) OLDI0_A2N */ + J722S_IOPAD(0x26c, PIN_OUTPUT, 0) /* (AB21) OLDI0_A2P */ + J722S_IOPAD(0x278, PIN_OUTPUT, 0) /* (AG20) OLDI0_A3N */ + J722S_IOPAD(0x274, PIN_OUTPUT, 0) /* (AG21) OLDI0_A3P */ + J722S_IOPAD(0x2a0, PIN_OUTPUT, 0) /* (AF21) OLDI0_CLK0N */ + J722S_IOPAD(0x29c, PIN_OUTPUT, 0) /* (AE20) OLDI0_CLK0P */ + >; + }; + + oldi1_pins_default: oldi1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x280, PIN_OUTPUT, 0) /* (AD21) OLDI0_A4N */ + J722S_IOPAD(0x27c, PIN_OUTPUT, 0) /* (AC21) OLDI0_A4P */ + J722S_IOPAD(0x288, PIN_OUTPUT, 0) /* (AF19) OLDI0_A5N */ + J722S_IOPAD(0x284, PIN_OUTPUT, 0) /* (AF18) OLDI0_A5P */ + J722S_IOPAD(0x290, PIN_OUTPUT, 0) /* (AG17) OLDI0_A6N */ + J722S_IOPAD(0x28c, PIN_OUTPUT, 0) /* (AG18) OLDI0_A6P */ + J722S_IOPAD(0x298, PIN_OUTPUT, 0) /* (AB19) OLDI0_A7N */ + J722S_IOPAD(0x294, PIN_OUTPUT, 0) /* (AA20) OLDI0_A7P */ + J722S_IOPAD(0x2a8, PIN_OUTPUT, 0) /* (AD20) OLDI0_CLK1N */ + J722S_IOPAD(0x2a4, PIN_OUTPUT, 0) /* (AE19) OLDI0_CLK1P */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x02c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x030, PIN_OUTPUT, 0) /* (K23) OSPI0_CSn1 */ + J722S_IOPAD(0x034, PIN_OUTPUT, 0) /* (K22) OSPI0_CSn2 */ + J722S_IOPAD(0x00c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + >; + bootph-all; + }; + + pcie0_rc_pins_default: pcie0-rc-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x2ac, PIN_OUTPUT, 0) /* (F25) PCIE0_CLKREQn */ + J722S_IOPAD(0x1b4, PIN_OUTPUT, 7) /* (B20) SPI0_CS0.GPIO1_15 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x090, PIN_INPUT, 7) /* (P27) GPMC0_BE0n_CLE.GPIO0_35 */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x14c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0f8, PIN_INPUT, 2) /* (AB24) VOUT0_HSYNC.RGMII2_RD0 */ + J722S_IOPAD(0x0fc, PIN_INPUT, 2) /* (AC27) VOUT0_DE.RGMII2_RD1 */ + J722S_IOPAD(0x100, PIN_INPUT, 2) /* (AB23) VOUT0_VSYNC.RGMII2_RD2 */ + J722S_IOPAD(0x104, PIN_INPUT, 2) /* (AC26) VOUT0_PCLK.RGMII2_RD3 */ + J722S_IOPAD(0x0f4, PIN_INPUT, 2) /* (AB27) VOUT0_DATA15.RGMII2_RXC */ + J722S_IOPAD(0x0f0, PIN_INPUT, 2) /* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */ + J722S_IOPAD(0x0e0, PIN_OUTPUT, 2) /* (AA25) VOUT0_DATA10.RGMII2_TD0 */ + J722S_IOPAD(0x0e4, PIN_OUTPUT, 2) /* (AB25) VOUT0_DATA11.RGMII2_TD1 */ + J722S_IOPAD(0x0e8, PIN_OUTPUT, 2) /* (AA23) VOUT0_DATA12.RGMII2_TD2 */ + J722S_IOPAD(0x0ec, PIN_OUTPUT, 2) /* (AA22) VOUT0_DATA13.RGMII2_TD3 */ + J722S_IOPAD(0x0dc, PIN_OUTPUT, 2) /* (AA27) VOUT0_DATA9.RGMII2_TXC */ + J722S_IOPAD(0x0d8, PIN_OUTPUT, 2) /* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */ + >; + }; + + rtc_pins_default: rtc-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 */ + >; + }; + + sdhci1_pins_default: sdhci1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x23c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x22c, PIN_INPUT, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x228, PIN_INPUT, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + J722S_IOPAD(0x244, PIN_INPUT, 0) /* (A24) MMC1_SDWP */ + >; + bootph-all; + }; + + usb0_connector_pins_default: usb0-connector-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7) /* (N23) GPMC0_WEn.GPIO0_34 */ + >; + }; + + usb1_pins_default: usb1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x258, PIN_OUTPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; + + vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01c, PIN_OUTPUT, 7) /* (L21) OSPI0_D4.GPIO0_7 */ + >; + bootph-all; + }; + + vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x020, PIN_OUTPUT, 7) /* (M26) OSPI0_D5.GPIO0_8 */ + >; + bootph-all; + }; + + vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1f0, PIN_OUTPUT, 7) /* (A23) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x078, PIN_OUTPUT, 7) /* (V23) GPMC0_AD15.GPIO0_30 */ + >; + }; + + vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (E20) SPI0_D1.GPIO1_19 */ + >; + }; + + vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ + >; + }; +}; + +/* SER1 */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; + status = "okay"; +}; + +/* SER2 */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart5_pins_default>; + bootph-all; + status = "okay"; +}; + +/* I2S0 */ +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins_default>; + op-mode = <0>; /* I2S */ + tdm-slots = <2>; + serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* I2S2 */ +&mcasp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp2_pins_default>; + op-mode = <0>; /* I2S */ + tdm-slots = <2>; + serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* CAN0 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + status = "okay"; +}; + +/* CAN1 */ +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + status = "okay"; +}; + +&mcu_gpio0 { + gpio-line-names = + "", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12", + "MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13"; +}; + +/* I2C_GP */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <100000>; + status = "okay"; + + /* SMARC Module EEPROM */ + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <&vcc_1p8_s0>; + }; +}; + +&mcu_pmx0 { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ + J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ + >; + }; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ + J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ + J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /* (C1) MCU_MCAN1_TX */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x014, PIN_INPUT, 0) /* (B8) MCU_UART0_RXD */ + J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0) /* (B4) MCU_UART0_TXD */ + J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0) /* (B5) MCU_UART0_CTSn */ + J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0) /* (C5) MCU_UART0_RTSn */ + >; + bootph-all; + }; + + mcu_spi0_pins_default: mcu-spi0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0) /* (A9) MCU_SPI0_CLK */ + J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0) /* (C12) MCU_SPI0_CS0 */ + J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0) /* (A10) MCU_SPI0_CS1 */ + J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0) /* (B12) MCU_SPI0_D0 */ + J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0) /* (C11) MCU_SPI0_D1 */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B3) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0) /* (B9) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT, 0) /* (D11) WKUP_I2C0_SDA */ + >; + }; +}; + +/* SPI0 */ +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; +}; + +/* SER0 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; + status = "okay"; +}; + +/* QSPI0 */ +&ospi0 { + pinctrl-0 = <&ospi0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + m25p,fast-read; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <3>; + vcc-supply = <&vcc_1p8_s0>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x000000 0x400000>; + label = "failsafe bootloader"; + read-only; + }; + }; + + otp-1 { + compatible = "user-otp"; + + nvmem-layout { + compatible = "kontron,sa67-vpd", "kontron,sl28-vpd"; + + serial_number: serial-number { + }; + + base_mac_address: base-mac-address { + #nvmem-cell-cells = <1>; + }; + }; + }; + }; +}; + +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_rc_pins_default>; + + /* + * This is low active, but the driver itself is broken and already + * inverts the logic. + */ + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie>; + phy-names = "pcie-phy"; + status = "okay"; +}; + +&sdhci0 { + disable-wp; + bootph-all; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* SDIO */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci1_pins_default>; + vmmc-supply = <&vcc_3p3_sd_s0>; + vqmmc-supply = <&vcc_3p3_sd_vio_s0>; + bootph-all; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <100>; + ti,fails-without-test-cd; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +&serdes_ln_ctrl { + idle-states = , + ; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&serdes0 { + serdes0_usb3: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + }; +}; + +&serdes1 { + serdes1_pcie: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz1 1>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + }; +}; + +&usb0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + port { + usb0_hc: endpoint { + remote-endpoint = <&usb0_connector>; + }; + }; +}; + +&usb0_phy_ctrl { + /* + * Keep this node in the SPL to be able to use the USB controller to + * boot via DFU. + */ + bootph-all; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; + + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb3>; + phy-names = "cdns3,usb3-phy"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +/* I2C_PM */ +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* SER3 */ +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; + status = "reserved"; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-gbe1.dtso b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-gbe1.dtso new file mode 100644 index 00000000000..5dfb0b8f10d --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-gbe1.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Second ethernet port GBE1. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +&cpsw3g_mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cpsw_port2 { + phy-connection-type = "rgmii-id"; + phy-handle = <&phy1>; + nvmem-cells = <&base_mac_address 1>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-gpios.dtso b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-gpios.dtso new file mode 100644 index 00000000000..a6ae758e0b3 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-gpios.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * SMARC GPIOs. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_pins_default>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_pins_default>; +}; + +&main_pmx0 { + main_gpio0_pins_default: main-gpio0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0d0, PIN_INPUT, 7) /* (Y26) VOUT0_DATA6.GPIO0_51 */ + J722S_IOPAD(0x0d4, PIN_INPUT, 7) /* (Y27) VOUT0_DATA7.GPIO0_52 */ + J722S_IOPAD(0x118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69 */ + J722S_IOPAD(0x120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ + >; + }; + + main_gpio1_pins_default: main-gpio1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x194, PIN_INPUT, 7) /* (A25) MCASP0_AXR3.GPIO1_7 */ + J722S_IOPAD(0x198, PIN_INPUT, 7) /* (A26) MCASP0_AXR2.GPIO1_8 */ + J722S_IOPAD(0x1ac, PIN_INPUT, 7) /* (C27) MCASP0_AFSR.GPIO1_13 */ + J722S_IOPAD(0x1b0, PIN_INPUT, 7) /* (F24) MCASP0_ACLKR.GPIO1_14 */ + J722S_IOPAD(0x1d8, PIN_INPUT, 7) /* (D22) MCAN0_TX.GPIO1_24 */ + J722S_IOPAD(0x1dc, PIN_INPUT, 7) /* (C22) MCAN0_RX.GPIO1_25 */ + J722S_IOPAD(0x1e8, PIN_INPUT, 7) /* (C24) I2C1_SCL.GPIO1_28 */ + J722S_IOPAD(0x1ec, PIN_INPUT, 7) /* (A22) I2C1_SDA.GPIO1_29 */ + >; + }; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio0_pins_default>; +}; + +&mcu_pmx0 { + mcu_gpio0_pins_default: mcu-gpio0-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x02c, PIN_INPUT, 7) /* (C4) WKUP_UART0_CTSn.MCU_GPIO0_11 */ + J722S_IOPAD(0x084, PIN_INPUT, 7) /* (F12) WKUP_CLKOUT0.MCU_GPIO0_23 */ + >; + }; + +}; diff --git a/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso new file mode 100644 index 00000000000..0a3e9f614c4 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Microcrystal RV8263 RTC variant. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + aliases { + rtc0 = "/bus@f0000/i2c@20000000/rtc@51"; /* &rtc */ + rtc1 = "/bus@f0000/bus@b00000/rtc@2b1f0000"; /* &wkup_rtc0 */ + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + rtc: rtc@51 { + compatible = "microcrystal,rv8263"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_pins_default>; + interrupts-extended = <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; + }; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am68-phyboard-izar.dts b/dts/upstream/src/arm64/ti/k3-am68-phyboard-izar.dts index 41c8f8526e1..e221ccb30e9 100644 --- a/dts/upstream/src/arm64/ti/k3-am68-phyboard-izar.dts +++ b/dts/upstream/src/arm64/ti/k3-am68-phyboard-izar.dts @@ -281,7 +281,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; @@ -422,6 +422,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>; + status = "okay"; }; &mcu_i2c1 { diff --git a/dts/upstream/src/arm64/ti/k3-am68-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am68-phycore-som.dtsi index adef02bd804..0ff511028f8 100644 --- a/dts/upstream/src/arm64/ti/k3-am68-phycore-som.dtsi +++ b/dts/upstream/src/arm64/ti/k3-am68-phycore-som.dtsi @@ -175,7 +175,7 @@ &main_cpsw_port1 { phy-handle = <&phy1>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; status = "okay"; }; @@ -258,7 +258,7 @@ bootph-pre-ram; }; - pmic@48 { + pmic: pmic@48 { compatible = "ti,tps6594-q1"; reg = <0x48>; system-power-controller; diff --git a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts index 75a107456ce..88f202f266c 100644 --- a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts +++ b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts @@ -692,6 +692,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status = "okay"; }; &davinci_mdio { @@ -705,7 +706,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; bootph-all; }; diff --git a/dts/upstream/src/arm64/ti/k3-am69-aquila-clover.dts b/dts/upstream/src/arm64/ti/k3-am69-aquila-clover.dts new file mode 100644 index 00000000000..55fd214a82e --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am69-aquila-clover.dts @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 + * https://www.toradex.com/products/carrier-board/clover + */ + +/dts-v1/; + +#include +#include "k3-am69-aquila.dtsi" + +/ { + model = "Toradex Aquila AM69 on Clover Board"; + compatible = "toradex,aquila-am69-clover", + "toradex,aquila-am69", + "ti,j784s4"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + reg_3v3_dp: regulator-3v3-dp { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP (AQUILA B57) */ + gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + /* Aquila DP_1 */ + dp-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_3v3_dp>; + label = "Display Port"; + type = "full-size"; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; +}; + +/* On-module ETH_1 MDIO */ +&davinci_mdio { + status = "okay"; +}; + +&dp0_ports { + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&main0_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main0_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main0_alert1>; + }; + }; +}; + +&main1_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main1_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main1_alert1>; + }; + }; +}; + +&main2_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main2_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main2_alert1>; + }; + }; +}; + +&main3_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main3_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main3_alert1>; + }; + }; +}; + +&main4_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main4_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main4_alert1>; + }; + }; +}; + +/* Aquila ETH_2 */ +&main_cpsw0 { + status = "okay"; +}; + +/* Aquila ETH_2 SGMII PHY */ +&main_cpsw0_port8 { + phy-handle = <&cpsw0_port8_phy4>; + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO */ +&main_cpsw0_mdio { + status = "okay"; + + cpsw0_port8_phy4: ethernet-phy@4 { + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <44 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +/* Aquila PWM_1 */ +&main_ehrpwm0 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&main_ehrpwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_01>, /* Aquila GPIO_01 */ + <&pinctrl_gpio_02>, /* Aquila GPIO_02 */ + <&pinctrl_gpio_03>; /* Aquila GPIO_03 */ +}; + +/* Aquila I2C_6 */ +&main_i2c5 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&main_mcan10 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&main_mcan13 { + status = "okay"; +}; + +/* Aquila SD_1 */ +&main_sdhci1 { + status = "okay"; +}; + +/* Aquila SPI_2 */ +&main_spi0 { + status = "okay"; +}; + +/* Aquila SPI_1 */ +&main_spi2 { + pinctrl-0 = <&pinctrl_main_spi2>, + <&pinctrl_main_spi2_cs0>, + <&pinctrl_gpio_05>; + cs-gpios = <0>, <&wkup_gpio0 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_06>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; +}; + +/* Aquila UART_1 */ +&main_uart4 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux console */ +&main_uart8 { + status = "okay"; +}; + +&mcu_cpsw { + status = "okay"; +}; + +/* On-module ETH_1 RGMII */ +&mcu_cpsw_port1 { + status = "okay"; +}; + +/* Aquila I2C_1 */ +&mcu_i2c0 { + clock-frequency = <100000>; + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan: fan { + cooling-levels = <102 179 255>; + #cooling-cells = <2>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C OTG"; + power-role = "dual"; + try-power-role = "sink"; + self-powered; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <1000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_con_hs: endpoint { + remote-endpoint = <&usb0_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb_1_con_ss: endpoint { + remote-endpoint = <&usb0_ss_mux>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&mcu_i2c1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&mcu_mcan1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +&mhdp { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + cdns,read-delay = <0>; + cdns,tchsh-ns = <3>; + cdns,tsd2d-ns = <10>; + cdns,tshsl-ns = <30>; + cdns,tslch-ns = <8>; + }; +}; + +/* Aquila PCIE_1 */ +&pcie0_rc { + status = "okay"; +}; + +/* Aquila PCIE_2 */ +&pcie1_rc { + status = "okay"; +}; + +&serdes2 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; +}; + +&serdes_wiz2 { + status = "okay"; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +/* Aquila ADC_[1-4] */ +&tscadc0 { + status = "okay"; +}; + +&usbss0 { + status = "okay"; +}; + +&usb0ss_mux { + status = "okay"; + + port { + usb0_ss_mux: endpoint { + remote-endpoint = <&usb_1_con_ss>; + }; + }; +}; + +&usb0 { + status = "okay"; + + port { + usb0_hs: endpoint { + remote-endpoint = <&usb_1_con_hs>; + }; + }; +}; + +&wkup0_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&wkup0_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&wkup0_alert1>; + }; + }; +}; + +&wkup1_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&wkup1_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&wkup1_alert1>; + }; + }; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_04>; /* Aquila GPIO_04 */ +}; + +/* Aquila UART_2 */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am69-aquila-dev.dts b/dts/upstream/src/arm64/ti/k3-am69-aquila-dev.dts new file mode 100644 index 00000000000..c7ce804eac7 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am69-aquila-dev.dts @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 + * https://www.toradex.com/products/carrier-board/aquila-development-board-kit + */ + +/dts-v1/; + +#include +#include "k3-am69-aquila.dtsi" + +/ { + model = "Toradex Aquila AM69 on Aquila Development Board"; + compatible = "toradex,aquila-am69-dev", + "toradex,aquila-am69", + "ti,j784s4"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + reg_1v8_sw: regulator-1v8-sw { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "Carrier_1V8"; + }; + + reg_3v3_dp: regulator-3v3-dp { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP (AQUILA B57) */ + gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_3v3_dp>; + label = "Display Port"; + type = "full-size"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "aquila-wm8904"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Digital Mic"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Digital Mic", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp4>; + }; + }; +}; + +/* Aquila CTRL_PWR_BTN_MICO# */ +&aquila_key_power { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +/* On-module ETH_1 MDIO */ +&davinci_mdio { + status = "okay"; +}; + +&dp0_ports { + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&main0_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main0_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main0_alert1>; + }; + }; +}; + +&main1_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main1_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main1_alert1>; + }; + }; +}; + +&main2_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main2_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main2_alert1>; + }; + }; +}; + +&main3_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main3_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main3_alert1>; + }; + }; +}; + +&main4_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&main4_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&main4_alert1>; + }; + }; +}; + +/* Aquila ETH_2 */ +&main_cpsw0 { + status = "okay"; +}; + +/* Aquila ETH_2 SGMII PHY */ +&main_cpsw0_port8 { + phy-handle = <&cpsw0_port8_phy4>; + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO */ +&main_cpsw0_mdio { + status = "okay"; + + cpsw0_port8_phy4: ethernet-phy@4 { + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <44 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +/* Aquila PWM_1 */ +&main_ehrpwm0 { + status = "okay"; +}; + +/* Aquila PWM_4_DP */ +&main_ehrpwm2 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&main_ehrpwm1 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI */ +&main_ehrpwm5 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_01>, /* Aquila GPIO_01 */ + <&pinctrl_gpio_02>, /* Aquila GPIO_02 */ + <&pinctrl_gpio_03>; /* Aquila GPIO_03 */ +}; + +/* Aquila I2C_3_DSI1 */ +&main_i2c0 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pin #4 and #6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pin #52 and #54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Aquila I2C_4_CSI1 */ +&main_i2c1 { + status = "okay"; +}; + +/* Aquila I2C_5_CSI2 */ +&main_i2c2 { + status = "okay"; +}; + +/* Aquila I2C_6 */ +&main_i2c5 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&main_mcan10 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&main_mcan13 { + status = "okay"; +}; + +/* Aquila SD_1 */ +&main_sdhci1 { + status = "okay"; +}; + +/* Aquila SPI_2 */ +&main_spi0 { + status = "okay"; +}; + +/* Aquila SPI_1 */ +&main_spi2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&main_uart4 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux console */ +&main_uart8 { + status = "okay"; +}; + +/* Aquila I2S_1 */ +&mcasp4 { + status = "okay"; +}; + +&mcu_cpsw { + status = "okay"; +}; + +/* On-module ETH_1 RGMII */ +&mcu_cpsw_port1 { + status = "okay"; +}; + +/* Aquila I2C_1 */ +&mcu_i2c0 { + clock-frequency = <100000>; + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan: fan { + cooling-levels = <102 179 255>; + #cooling-cells = <2>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_extrefclk1>; + #sound-dai-cells = <0>; + clocks = <&audio_refclk1>; + clock-names = "mclk"; + AVDD-supply = <®_1v8_sw>; + CPVDD-supply = <®_1v8_sw>; + DBVDD-supply = <®_1v8_sw>; + DCVDD-supply = <®_1v8_sw>; + MICVDD-supply = <®_1v8_sw>; + + wlf,drc-cfg-names = "default", "peaklimiter"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; + + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + + wlf,in1r-as-dmicdat2; + }; + + /* Current measurement into module VCC */ + hwmon@41 { + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C OTG"; + power-role = "dual"; + try-power-role = "sink"; + self-powered; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <1000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_con_hs: endpoint { + remote-endpoint = <&usb0_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb_1_con_ss: endpoint { + remote-endpoint = <&usb0_ss_mux>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&mcu_i2c1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&mcu_mcan1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +&mhdp { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + cdns,read-delay = <0>; + cdns,tchsh-ns = <3>; + cdns,tsd2d-ns = <10>; + cdns,tshsl-ns = <30>; + cdns,tslch-ns = <8>; + }; +}; + +/* Aquila PCIE_1 */ +&pcie0_rc { + status = "okay"; +}; + +/* Aquila PCIE_2 */ +&pcie1_rc { + status = "okay"; +}; + +&serdes2 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; +}; + +&serdes_wiz2 { + status = "okay"; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +/* Aquila ADC_[1-4] */ +&tscadc0 { + status = "okay"; +}; + +&usbss0 { + status = "okay"; +}; + +&usb0ss_mux { + status = "okay"; + + port { + usb0_ss_mux: endpoint { + remote-endpoint = <&usb_1_con_ss>; + }; + }; +}; + +&usb0 { + status = "okay"; + + port { + usb0_hs: endpoint { + remote-endpoint = <&usb_1_con_hs>; + }; + }; +}; + +&wkup0_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&wkup0_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&wkup0_alert1>; + }; + }; +}; + +&wkup1_thermal { + cooling-maps { + map0 { + cooling-device = <&fan 1 1>; + trip = <&wkup1_alert0>; + }; + + map1 { + cooling-device = <&fan 2 2>; + trip = <&wkup1_alert1>; + }; + }; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_04>, /* Aquila GPIO_04 */ + <&pinctrl_gpio_05>, /* Aquila GPIO_05 */ + <&pinctrl_gpio_06>, /* Aquila GPIO_06 */ + <&pinctrl_gpio_07>, /* Aquila GPIO_07 */ + <&pinctrl_gpio_08>; /* Aquila GPIO_08 */ +}; + +/* Aquila UART_2, through RS485 transceiver */ +&wkup_uart0 { + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/ti/k3-am69-aquila.dtsi b/dts/upstream/src/arm64/ti/k3-am69-aquila.dtsi new file mode 100644 index 00000000000..0866eb8a6f3 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am69-aquila.dtsi @@ -0,0 +1,1840 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 + */ + +#include +#include +#include +#include +#include +#include "k3-j784s4.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + can0 = &main_mcan10; + can1 = &mcu_mcan0; + can2 = &main_mcan13; + can3 = &mcu_mcan1; + eeprom0 = &som_eeprom; + ethernet0 = &mcu_cpsw_port1; + ethernet1 = &main_cpsw0_port8; + i2c0 = &wkup_i2c0; + i2c1 = &mcu_i2c0; + i2c2 = &mcu_i2c1; + i2c3 = &main_i2c0; + i2c4 = &main_i2c1; + i2c5 = &main_i2c2; + i2c6 = &main_i2c5; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + rtc0 = &rtc_i2c; + serial0 = &main_uart4; + serial1 = &wkup_uart0; + serial2 = &main_uart8; + serial3 = &mcu_uart0; + usb0 = &usb0; + }; + + aquila_key_power: gpio-key-power { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwr_btn_int>; + status = "disabled"; + + key-power { + /* Aquila CTRL_PWR_BTN_MICO# (AQUILA B93) */ + gpios = <&wkup_gpio0 36 GPIO_ACTIVE_LOW>; + label = "Power Button"; + linux,code = ; + }; + }; + + aquila_key_wake: gpio-key-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + status = "disabled"; + + key-wakeup { + /* Aquila CTRL_WAKE1_MICO# (AQUILA D6) */ + gpios = <&wkup_gpio0 49 GPIO_ACTIVE_LOW>; + label = "Wake Up"; + linux,code = ; + wakeup-source; + }; + }; + + /* Aquila CTRL_RESET_MICO# (AQUILA B92) */ + gpio-restart { + compatible = "gpio-restart"; + /* COLD_RESET_REQ */ + gpios = <&som_gpio_expander 1 GPIO_ACTIVE_HIGH>; + priority = <192>; + }; + + /* PWR_DOWN_REQ */ + gpio-poweroff { + compatible = "gpio-poweroff"; + /* PWR_DOWN_REQ */ + gpios = <&som_gpio_expander 2 GPIO_ACTIVE_HIGH>; + timeout-ms = <3000>; + }; + + memory@80000000 { + device_type = "memory"; + /* 32G RAM */ + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x08 0x80000000 0x07 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + }; + + /* Module Power Supply (VCC) */ + reg_vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "+V_IN"; + }; + + /* Enabled by EN_3V3_VIO (PMIC_GPIO_9) */ + reg_1v1_usb_bridge: regulator-1v1-vio { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+V1.1_VIO"; + vin-supply = <®_vin>; + }; + + reg_3v3_wifi: regulator-3v3-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_en_3v3_wifi>; + gpio = <&wkup_gpio0 57 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_WIFI"; + startup-delay-us = <20000>; + vin-supply = <®_vin>; + }; + + reg_1v8_stby: regulator-1v8-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_STBY"; + vin-supply = <®_vin>; + }; + + /* Aquila SD_1_PWR_EN */ + reg_sdhc1_vmmc: regulator-sdhci1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Aquila SD_1_PWR_EN (AQUILA A6) */ + gpio = <&main_gpio0 52 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+3V3_SD"; + startup-delay-us = <20000>; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + /* SDIO_PWR_SEL_3.3V */ + gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+VDD_SD_DV"; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + /* On-module USB_1_SS mux */ + usb0ss_mux: gpio-sbu-mux { + compatible = "ti,tmuxhs4212", "gpio-sbu-mux"; + orientation-switch; + /* USB_MUX_SEL */ + select-gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&main_pmx0 { + /* Aquila DP_1_HPD */ + pinctrl_main_dp0_hpd: main-dp0-hpd-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ /* AQUILA B59 */ + >; + }; + + /* Aquila PWM_1 */ + pinctrl_main_ehrpwm0_b: main-ehrpwm0b-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x064, PIN_OUTPUT, 9) /* (AF38) MCAN0_TX.EHRPWM0_B */ /* AQUILA C25 */ + >; + }; + + /* Aquila PWM_2 */ + pinctrl_main_ehrpwm1_a: main-ehrpwm1a-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x060, PIN_OUTPUT, 9) /* (AE36) MCASP2_AXR1.EHRPWM1_A */ /* AQUILA C26 */ + >; + }; + + /* Aquila PWM_3_DSI */ + pinctrl_main_ehrpwm5_a: main-ehrpwm5a-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x084, PIN_OUTPUT, 9) /* (AG38) MCASP0_AXR5.EHRPWM5_A */ /* AQUILA B46 */ + >; + }; + + /* Aquila PWM_4_DP */ + pinctrl_main_ehrpwm2_a: main-ehrpwm2a-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x040, PIN_INPUT, 9) /* (AF37) MCASP0_AXR0.EHRPWM2_A */ /* AQUILA B58 */ + >; + }; + + /* PMIC_INT# */ + pinctrl_pmic_int: main-gpio0-0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTn.GPIO0_0 */ + >; + }; + + /* Aquila GPIO_09_CSI_1 */ + pinctrl_gpio_09_csi_1: main-gpio0-1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ /* AQUILA B17 */ + >; + }; + + /* Aquila GPIO_10_CSI_1 */ + pinctrl_gpio_10_csi_1: main-gpio0-2-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ /* AQUILA B18 */ + >; + }; + + /* Aquila USB_1_OC# */ + pinctrl_usb1_oc: main-gpio0-10-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x028, PIN_INPUT, 7) /* (AE33) MCAN16_RX.GPIO0_10 */ /* AQUILA B75 */ + >; + }; + + /* Aquila USB_1_EN */ + pinctrl_usb1_en_gpio: main-gpio0-11-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x02c, PIN_INPUT, 7) /* (AL32) GPIO0_11 */ /* AQUILA B77 */ + >; + }; + + /* Aquila GPIO_17_DSI_1 */ + pinctrl_gpio_17_dsi_1: main-gpio0-12-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x030, PIN_INPUT, 7) /* (AK37) GPIO0_12 */ /* AQUILA B42 */ + >; + }; + + /* Aquila GPIO_19_DSI_1 */ + pinctrl_gpio_19_dsi_1: main-gpio0-13-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ /* AQUILA B44 */ + >; + }; + + /* Aquila GPIO_02 */ + pinctrl_gpio_02: main-gpio0-17-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x044, PIN_INPUT, 7) /* (AG37) MCASP0_AXR1.GPIO0_17 */ /* AQUILA D24 */ + >; + }; + + /* Aquila GPIO_20_DSI_1 */ + pinctrl_gpio_20_dsi_1: main-gpio0-18-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x048, PIN_INPUT, 7) /* (AK33) MCASP0_AXR2.GPIO0_18 */ /* AQUILA B45 */ + >; + }; + + /* Aquila GPIO_21_DP */ + pinctrl_gpio_21_dp: main-gpio0-21-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x054, PIN_INPUT, 7) /* (AD37) MCASP2_ACLKX.GPIO0_21 */ /* AQUILA B57 */ + >; + }; + + /* Aquila USB_1_INT# */ + pinctrl_usb1_int: main-gpio0-28-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x070, PIN_INPUT, 7) /* (AH38) MCAN1_RX.GPIO0_28 */ /* AQUILA B74 */ + >; + }; + + /* Aquila GPIO_03 */ + pinctrl_gpio_03: main-gpio0-29-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x074, PIN_INPUT, 7) /* (AC33) MCAN2_TX.GPIO0_29 */ /* AQUILA D25 */ + >; + }; + + /* Aquila GPIO_18_DSI_1 */ + pinctrl_gpio_18_dsi_1: main-gpio0-31-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x07c, PIN_INPUT, 7) /* (AJ38) MCASP0_AXR3.GPIO0_31 */ /* AQUILA B43 */ + >; + }; + + /* Aquila PCIE_1_RESET# */ + pinctrl_pcie0_reset: main-gpio0-32-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x080, PIN_INPUT, 7) /* (AK34) MCASP0_AXR4.GPIO0_32 */ /* AQUILA C38 */ + >; + }; + + /* Aquila PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: main-gpio0-33-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x084, PIN_INPUT, 7) /* (AG38) MCASP0_AXR5.GPIO0_33 */ /* AQUILA B46 */ + >; + }; + + /* Aquila GPIO_01 */ + pinctrl_gpio_01: main-gpio0-34-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x088, PIN_INPUT, 7) /* (AF36) MCASP0_AXR6.GPIO0_34 */ /* AQUILA D23 */ + >; + }; + + /* Aquila PCIE_2_RESET# */ + pinctrl_pcie1_reset: main-gpio0-41-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ /* AQUILA C35 */ + >; + }; + + /* Aquila ETH_2_xGMII_INT# */ + pinctrl_eth2_int: main-gpio0-44-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 7) /* (AL33) MCASP1_AXR3.GPIO0_44 */ /* AQUILA B81 */ + >; + }; + + /* Aquila GPIO_11_CSI_1 */ + pinctrl_gpio_11_csi_1: main-gpio0-47-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ /* AQUILA A11 */ + >; + }; + + /* Aquila GPIO_12_CSI_1 */ + pinctrl_gpio_12_csi_1: main-gpio0-48-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ /* AQUILA B19 */ + >; + }; + + /* Aquila SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-52-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0d0, PIN_INPUT, 7) /* (AP38) SPI0_CS1.GPIO0_52 */ /* AQUILA A6 */ + >; + }; + + /* Aquila SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: main-gpio0-58-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0e8, PIN_INPUT_PULLUP, 7) /* (AR38) TIMER_IO0.GPIO0_58 */ /* AQUILA A1 */ + >; + }; + + /* Aquila I2C_3_DSI1 */ + pinctrl_main_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ /* AQUILA B41 */ + J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ /* AQUILA B40 */ + >; + }; + + /* Aquila I2C_4_CSI1 */ + pinctrl_main_i2c1: main-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x020, PIN_INPUT_PULLUP, 12) /* (AJ35) MCAN15_RX.I2C1_SCL */ /* AQUILA A13 */ + J784S4_IOPAD(0x024, PIN_INPUT_PULLUP, 12) /* (AH34) MCAN16_TX.I2C1_SDA */ /* AQUILA A12 */ + >; + }; + + /* Aquila I2C_5_CSI2 */ + pinctrl_main_i2c2: main-i2c2-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (AC32) MCASP1_AXR1.I2C2_SCL */ /* AQUILA C6 */ + J784S4_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (AC37) MCASP1_AXR2.I2C2_SDA */ /* AQUILA C5 */ + >; + }; + + /* Aquila I2C_6 */ + pinctrl_main_i2c5: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ /* AQUILA C19 */ + J784S4_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ /* AQUILA C18 */ + >; + }; + + /* Aquila I2S_1_MCLK */ + pinctrl_audio_extrefclk1: audio-extrefclk1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ /* AQUILA B24 */ + >; + }; + + /* Aquila CAN_1 */ + pinctrl_main_mcan10: main-mcan10-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 0) /* (AC34) MCASP1_ACLKX.MCAN10_RX */ /* AQUILA B49 */ + J784S4_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (AL34) MCASP1_AXR4.MCAN10_TX */ /* AQUILA B48 */ + >; + }; + + /* Aquila CAN_3 */ + pinctrl_main_mcan13: main-mcan13-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x010, PIN_INPUT, 0) /* (AH33) MCAN13_RX */ /* AQUILA B54 */ + J784S4_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AF33) MCAN13_TX */ /* AQUILA B53 */ + >; + }; + + /* Aquila I2S_1 */ + pinctrl_main_mcasp4: main-mcasp4-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c8, PIN_INPUT, 1) /* (AJ32) EXT_REFCLK1.MCASP4_ACLKX */ /* AQUILA B20 */ + J784S4_IOPAD(0x06c, PIN_INPUT, 1) /* (AJ37) MCAN1_TX.MCASP4_AFSX */ /* AQUILA B21 */ + J784S4_IOPAD(0x068, PIN_OUTPUT, 1) /* (AE38) MCAN0_RX.MCASP4_AXR1 */ /* AQUILA B22 */ + J784S4_IOPAD(0x0c4, PIN_INPUT, 1) /* (AD36) ECAP0_IN_APWM_OUT.MCASP4_AXR2 */ /* AQUILA B23 */ + >; + }; + + /* Aquila ETH_2_XGMII_MDIO */ + pinctrl_main_mdio1: main-mdio1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x058, PIN_OUTPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ /* AQUILA B90 */ + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ /* AQUILA B89 */ + >; + }; + + /* Aquila SD_1 */ + pinctrl_main_mmc1: main-mmc1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ /* AQUILA A5 */ + J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ /* AQUILA A7 */ + J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ + J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ /* AQUILA A3 */ + J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ /* AQUILA A2 */ + J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ /* AQUILA A10 */ + J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ /* AQUILA A8 */ + >; + }; + + /* Aquila SPI_2 */ + pinctrl_main_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AN38) SPI0_CLK */ /* AQUILA D14 */ + J784S4_IOPAD(0x0d8, PIN_INPUT, 0) /* (AM35) SPI0_D0 */ /* AQUILA D15 */ + J784S4_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (AM36) SPI0_D1 */ /* AQUILA D17 */ + >; + }; + + /* Aquila SPI_2 CS */ + pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */ + >; + }; + + /* Aquila SPI_1 */ + pinctrl_main_spi2: main-spi2-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0a0, PIN_OUTPUT, 10) /* (AD34) MCASP0_AXR12.SPI2_CLK */ /* AQUILA D12 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 10) /* (AF34) MCASP0_AXR14.SPI2_D0 */ /* AQUILA D10 */ + J784S4_IOPAD(0x0ac, PIN_OUTPUT, 10) /* (AE34) MCASP0_AXR15.SPI2_D1 */ /* AQUILA D11 */ + >; + }; + + /* Aquila SPI_1 CS */ + pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */ + >; + }; + + /* Aquila UART_1 */ + pinctrl_main_uart4: main-uart4-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x094, PIN_INPUT, 11) /* (AG35) MCASP0_AXR9.UART4_CTSn */ /* AQUILA B36 */ + J784S4_IOPAD(0x098, PIN_OUTPUT, 11) /* (AH36) MCASP0_AXR10.UART4_RTSn */ /* AQUILA B38 */ + J784S4_IOPAD(0x08c, PIN_INPUT, 11) /* (AE35) MCASP0_AXR7.UART4_RXD */ /* AQUILA B35 */ + J784S4_IOPAD(0x090, PIN_OUTPUT, 11) /* (AC35) MCASP0_AXR8.UART4_TXD */ /* AQUILA B37 */ + >; + }; + + /* Aquila UART_3, used as the Linux console */ + pinctrl_main_uart8: main-uart8-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x038, PIN_INPUT, 11) /* (AK35) MCASP0_ACLKX.UART8_RXD */ /* AQUILA D19 */ + J784S4_IOPAD(0x03c, PIN_OUTPUT, 11) /* (AK38) MCASP0_AFSX.UART8_TXD */ /* AQUILA D20 */ + >; + }; +}; + +&wkup_pmx0 { + /* Aquila QSPI_1 (4-bit) */ + pinctrl_mcu_ospi0_4bit: mcu-ospi0-4bit-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */ + >; + }; + + /* Aquila QSPI_1 (8-bit) */ + pinctrl_mcu_ospi0_8bit: mcu-ospi0-8bit-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ /* AQUILA B70 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ /* AQUILA B71 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ /* AQUILA B72 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ /* AQUILA B73 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */ + >; + }; + + /* Aquila QSPI_1_CS1# */ + pinctrl_mcu_ospi0_cs0: mcu-ospi0-cs0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ /* AQUILA B66 */ + >; + }; + + /* Aquila QSPI_1_CS2# */ + pinctrl_mcu_ospi0_cs1: mcu-ospi0-cs1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (A33) MCU_OSPI0_CSn1 */ /* AQUILA B62 */ + >; + }; + + /* Aquila QSPI_1_SCK as GPIO */ + pinctrl_wkup_gpio_16: wkup-gpio0-16-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (E32) MCU_OSPI0_CLK.WKUP_GPIO0_16 */ /* AQUILA B65 */ + >; + }; + + /* Aquila GPIO_04 */ + pinctrl_gpio_04: wkup-gpio0-17-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (D32) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */ /* AQUILA C20 */ + >; + }; + + /* Aquila QSPI_1_DQS as GPIO */ + pinctrl_wkup_gpio_18: wkup-gpio0-18-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (C34) MCU_OSPI0_DQS.WKUP_GPIO0_18 */ /* AQUILA B63 */ + >; + }; + + /* Aquila QSPI_1_IO0 as GPIO */ + pinctrl_wkup_gpio_19: wkup-gpio0-19-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (B33) MCU_OSPI0_D0.WKUP_GPIO0_19 */ /* AQUILA B68 */ + >; + }; + + /* Aquila QSPI_1_IO1 as GPIO */ + pinctrl_wkup_gpio_20: wkup-gpio0-20-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (B32) MCU_OSPI0_D1.WKUP_GPIO0_20 */ /* AQUILA B67 */ + >; + }; + + /* Aquila QSPI_1_IO2 as GPIO */ + pinctrl_wkup_gpio_21: wkup-gpio0-21-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (C33) MCU_OSPI0_D2.WKUP_GPIO0_21 */ /* AQUILA B61 */ + >; + }; + + /* Aquila QSPI_1_IO3 as GPIO */ + pinctrl_wkup_gpio_22: wkup-gpio0-22-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 7) /* (C35) MCU_OSPI0_D3.WKUP_GPIO0_22 */ /* AQUILA B60 */ + >; + }; + + /* Aquila QSPI_1_IO4 as GPIO */ + pinctrl_wkup_gpio_23: wkup-gpio0-23-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (D33) MCU_OSPI0_D4.WKUP_GPIO0_23 */ /* AQUILA B70 */ + >; + }; + + /* Aquila QSPI_1_IO5 as GPIO */ + pinctrl_wkup_gpio_24: wkup-gpio0-24-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (D34) MCU_OSPI0_D5.WKUP_GPIO0_24 */ /* AQUILA B71 */ + >; + }; + + /* Aquila QSPI_1_IO6 as GPIO */ + pinctrl_wkup_gpio_25: wkup-gpio0-25-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (E34) MCU_OSPI0_D6.WKUP_GPIO0_25 */ /* AQUILA B72 */ + >; + }; + + /* Aquila QSPI_1_IO7 as GPIO */ + pinctrl_wkup_gpio_26: wkup-gpio0-26-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (E33) MCU_OSPI0_D7.WKUP_GPIO0_26 */ /* AQUILA B73 */ + >; + }; + + /* Aquila QSPI_1_CS#1 as GPIO */ + pinctrl_wkup_gpio_27: wkup-gpio0-27-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 7) /* (A32) MCU_OSPI0_CSn0.WKUP_GPIO0_27 */ /* AQUILA B66 */ + >; + }; + + /* Aquila QSPI_1_CS#2 as GPIO */ + pinctrl_wkup_gpio_28: wkup-gpio0-28-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 7) /* (A33) MCU_OSPI0_CSn1.WKUP_GPIO0_28 */ /* AQUILA B62 */ + >; + }; +}; + +&wkup_pmx1 { + /* Aquila UART_4 (RXD) */ + pinctrl_mcu_uart0_rx: mcu-uart0-rx-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 4) /* (D31) MCU_OSPI1_D1.MCU_UART0_RXD */ /* AQUILA D21 */ + >; + }; + + /* Aquila GPIO_05 */ + pinctrl_gpio_05: wkup-gpio0-29-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (B34) MCU_OSPI0_CSn2.WKUP_GPIO0_29 */ /* AQUILA C21 */ + >; + }; + + /* Aquila GPIO_06 */ + pinctrl_gpio_06: wkup-gpio0-30-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (C32) MCU_OSPI0_CSn3.WKUP_GPIO0_30 */ /* AQUILA C22 */ + >; + }; + + /* Aquila GPIO_07 */ + pinctrl_gpio_07: wkup-gpio0-31-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (F32) MCU_OSPI1_CLK.WKUP_GPIO0_31 */ /* AQUILA C23 */ + >; + }; + + /* Aquila GPIO_13_CSI_2 */ + pinctrl_gpio_13_csi_2: wkup-gpio0-32-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (C31) MCU_OSPI1_LBCLKO.WKUP_GPIO0_32 */ /* AQUILA C1 */ + >; + }; + + /* Aquila GPIO_14_CSI_2 */ + pinctrl_gpio_14_csi_2: wkup-gpio0-33-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (F31) MCU_OSPI1_DQS.WKUP_GPIO0_33 */ /* AQUILA C2 */ + >; + }; + + /* RTC_IRQ# */ + pinctrl_rtc_irq: wkup-gpio0-34-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (E35) MCU_OSPI1_D0.WKUP_GPIO0_34 */ + >; + }; + + /* Aquila CTRL_PWR_BTN_MICO# (PWR_BTN_INT#) */ + pinctrl_pwr_btn_int: wkup-gpio0-36-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT_PULLUP, 7) /* (G31) MCU_OSPI1_D2.WKUP_GPIO0_36 */ /* AQUILA B92 */ + >; + }; + + /* Aquila GPIO_15_CSI_2 */ + pinctrl_gpio_15_csi_2: wkup-gpio0-37-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (F33) MCU_OSPI1_D3.WKUP_GPIO0_37 */ /* AQUILA C3 */ + >; + }; + + /* Aquila GPIO_08 */ + pinctrl_gpio_08: wkup-gpio0-38-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (G32) MCU_OSPI1_CSn0.WKUP_GPIO0_38 */ /* AQUILA C24 */ + >; + }; + + /* Aquila GPIO_16_CSI_2 */ + pinctrl_gpio_16_csi_2: wkup-gpio0-39-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ /* AQUILA C4 */ + >; + }; +}; + +&wkup_pmx2 { + /* Aquila ADC_[1-4] */ + pinctrl_mcu_adc0: mcu-adc0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (P36) MCU_ADC0_AIN0 */ /* AQUILA D1 */ + J784S4_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V36) MCU_ADC0_AIN1 */ /* AQUILA D2 */ + J784S4_WKUP_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (T34) MCU_ADC0_AIN2 */ /* AQUILA D3 */ + J784S4_WKUP_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (T36) MCU_ADC0_AIN3 */ /* AQUILA D4 */ + >; + }; + + /* Aquila CTRL_MCLK_MOCI */ + pinctrl_mcu_clkout0: mcu-clkout0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x084, PIN_OUTPUT, 6) /* (M38) WKUP_GPIO0_11.MCU_CLKOUT0 */ /* AQUILA A14 */ + >; + }; + + /* Aquila I2C_1 */ + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (M35) MCU_I2C0_SCL */ /* AQUILA D8 */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (G34) MCU_I2C0_SDA */ /* AQUILA D7 */ + >; + }; + + /* Aquila I2C_2 */ + pinctrl_mcu_i2c1: mcu-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ /* AQUILA C17 */ + J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ /* AQUILA C16 */ + >; + }; + + /* Aquila CAN_2 */ + pinctrl_mcu_mcan0: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ /* AQUILA B51 */ + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ /* AQUILA B50 */ + >; + }; + + /* Aquila CAN_4 */ + pinctrl_mcu_mcan1: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ /* AQUILA B56 */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ /* AQUILA B55 */ + >; + }; + + /* On-module ETH_1 MDIO */ + pinctrl_mcu_mdio: mcu-mdio-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; + + /* On-module ETH_1 RGMII */ + pinctrl_mcu_rgmii1: mcu-rgmii1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + /* On-module SPI (TPM_SPI) */ + pinctrl_mcu_spi0: mcu-spi0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (G38) MCU_SPI0_CLK */ + J784S4_WKUP_IOPAD(0x044, PIN_OUTPUT, 0) /* (F37) MCU_SPI0_CS0 */ + J784S4_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (H36) MCU_SPI0_D0 */ + J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (J38) MCU_SPI0_D1 */ + >; + }; + + /* Aquila UART_4 (TX) */ + pinctrl_mcu_uart0_tx: mcu-uart0-tx-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 2) /* (L33) WKUP_GPIO0_10.MCU_UART0_TXD */ /* AQUILA D22 */ + >; + }; + + /* On-module Wi-Fi Power Enable */ + pinctrl_en_3v3_wifi: wkup-gpio0-57-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ + >; + }; + + /* On-module TPM IRQ# */ + pinctrl_tpm_irq: wkup-gpio0-81-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 7) /* (V34) MCU_ADC1_AIN2.WKUP_GPIO0_81 */ + >; + }; + + /* On-module I2C - WKUP_I2C0 */ + pinctrl_wkup_i2c0: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + + /* Aquila UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ /* AQUILA B32 */ + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ /* AQUILA B34 */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ /* AQUILA B31 */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ /* AQUILA B33 */ + >; + }; +}; + +&wkup_pmx3 { + /* Aquila CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: wkup-gpio0-49-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_INPUT_PULLUP, 7) /* (M33) WKUP_GPIO0_49 */ /* AQUILA D6 */ + >; + }; +}; + +/* Aquila I2S_1_MCLK */ +&audio_refclk1 { + assigned-clock-rates = <24576000>; +}; + +/* On-module ETH_1 MDIO */ +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mdio>; + status = "disabled"; + + mcu_phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <79 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&dss { + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>; + status = "disabled"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; +}; + +&main0_crit { + temperature = <105000>; +}; + +&main0_thermal { + trips { + main0_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + main0_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&main1_crit { + temperature = <105000>; +}; + +&main1_thermal { + trips { + main1_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + main1_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&main2_crit { + temperature = <105000>; +}; + +&main2_thermal { + trips { + main2_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + main2_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&main3_crit { + temperature = <105000>; +}; + +&main3_thermal { + trips { + main3_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + main3_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&main4_crit { + temperature = <105000>; +}; + +&main4_thermal { + trips { + main4_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + main4_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +/* Aquila ETH_2 SGMII PHY */ +&main_cpsw0_port8 { + phy-mode = "sgmii"; + phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_sgmii_link>; + phy-names = "mac", "serdes"; + status = "disabled"; +}; + +/* Aquila ETH_2_XGMII_MDIO */ +&main_cpsw0_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mdio1>; +}; + +/* Aquila PWM_1 */ +&main_ehrpwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_ehrpwm0_b>; + status = "disabled"; +}; + +/* Aquila PWM_2 */ +&main_ehrpwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_ehrpwm1_a>; + status = "disabled"; +}; + +/* Aquila PWM_4_DP */ +&main_ehrpwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_ehrpwm2_a>; + status = "disabled"; +}; + +/* Aquila PWM_3_DSI */ +&main_ehrpwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_ehrpwm5_a>; + status = "disabled"; +}; + +&main_gpio0 { + gpio-line-names = + "", /* 0 */ + "AQUILA_B17", + "AQUILA_B18", + "AQUILA_B53", + "AQUILA_B54", + "AQUILA_B59", + "AQUILA_C18", + "AQUILA_C19", + "AQUILA_A13", + "AQUILA_A12", + "AQUILA_B75", /* 10 */ + "AQUILA_B77", + "AQUILA_B42", + "AQUILA_B44", + "AQUILA_D19", + "AQUILA_D20", + "AQUILA_B58", + "AQUILA_D24", + "AQUILA_B45", + "AQUILA_C06", + "AQUILA_C05", /* 20 */ + "AQUILA_B57", + "AQUILA_B90", + "AQUILA_B89", + "AQUILA_C26", + "AQUILA_C25", + "AQUILA_B22", + "AQUILA_B21", + "AQUILA_B74", + "AQUILA_D25", + "AQUILA_B24", /* 30 */ + "AQUILA_B43", + "AQUILA_C38", + "AQUILA_B46", + "AQUILA_D23", + "AQUILA_B35", + "AQUILA_B37", + "AQUILA_B36", + "AQUILA_B38", + "AQUILA_D09", + "AQUILA_D12", /* 40 */ + "AQUILA_C35", + "AQUILA_D10", + "AQUILA_D11", + "AQUILA_B81", + "AQUILA_B48", + "AQUILA_B49", + "AQUILA_A11", + "AQUILA_B19", + "AQUILA_B23", + "AQUILA_B20", /* 50 */ + "AQUILA_D16", + "AQUILA_A06", + "AQUILA_D14", + "AQUILA_D15", + "AQUILA_D17", + "AQUILA_B41", + "AQUILA_B40", + "AQUILA_A01", + "", + "AQUILA_A08", /* 60 */ + "AQUILA_A10", + "AQUILA_A02", + "AQUILA_A03", + "AQUILA_A05", + "AQUILA_A07"; + + status = "okay"; +}; + +/* Aquila I2C_3_DSI1 */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c0>; + clock-frequency = <100000>; + status = "disabled"; +}; + +/* Aquila I2C_4_CSI1 */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c1>; + clock-frequency = <400000>; + status = "disabled"; +}; + +/* Aquila I2C_5_CSI2 */ +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c2>; + clock-frequency = <400000>; + status = "disabled"; +}; + +/* Aquila I2C_6 */ +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c5>; + clock-frequency = <400000>; + status = "disabled"; +}; + +/* Aquila CAN_1 */ +&main_mcan10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mcan10>; + status = "disabled"; +}; + +/* Aquila CAN_3 */ +&main_mcan13 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mcan13>; + status = "disabled"; +}; + +/* On-module eMMC */ +&main_sdhci0 { + disable-wp; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Aquila SD_1 */ +&main_sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mmc1>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&main_gpio0 58 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + ti,driver-strength-ohm = <50>; + ti,fails-without-test-cd; + status = "disabled"; +}; + +/* Aquila SPI_2 */ +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>; + status = "disabled"; +}; + +/* Aquila SPI_1 */ +&main_spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>; + status = "disabled"; +}; + +/* Aquila UART_1 */ +&main_uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_uart4>; + status = "disabled"; +}; + +/* Aquila UART_3, used as the Linux console */ +&main_uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_uart8>; + status = "disabled"; +}; + +/* Aquila I2S_1 */ +&mcasp4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mcasp4>; + op-mode = <0>; /* MCASP_I2S_MODE */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 1 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_rgmii1>; + status = "disabled"; +}; + +/* On-module ETH_1 RGMII */ +&mcu_cpsw_port1 { + phy-handle = <&mcu_phy0>; + phy-mode = "rgmii-id"; + status = "disabled"; +}; + +/* Aquila I2C_1 */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c0>; + clock-frequency = <400000>; + status = "disabled"; +}; + +/* Aquila I2C_2 */ +&mcu_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c1>; + clock-frequency = <400000>; + status = "disabled"; +}; + +/* Aquila CAN_2 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan0>; + status = "disabled"; +}; + +/* Aquila CAN_4 */ +&mcu_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan1>; + status = "disabled"; +}; + +/* On-module SPI (TPM_SPI) */ +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_spi0>; + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm_irq>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <81 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <33000000>; + }; +}; + +/* Aquila UART_4 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_uart0_rx>, <&pinctrl_mcu_uart0_tx>; + status = "disabled"; +}; + +&mhdp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_dp0_hpd>; + phy-names = "dpphy"; + phys = <&serdes4_dp0_link>; + status = "disabled"; +}; + +/* Aquila QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_ospi0_8bit>, <&pinctrl_mcu_ospi0_cs0>; + status = "disabled"; +}; + +/* Aquila PCIE_1 */ +&pcie0_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reset>; + clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + num-lanes = <2>; + phy-names = "pcie-phy"; + phys = <&serdes1_pcie0_2l_link>; + reset-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; + status = "disabled"; +}; + +/* Aquila PCIE_2 */ +&pcie1_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1_reset>; + clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + num-lanes = <2>; + phy-names = "pcie-phy"; + phys = <&serdes0_pcie1_2l_link>; + reset-gpios = <&main_gpio0 41 GPIO_ACTIVE_HIGH>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; + status = "disabled"; +}; + +/* On-module PCIe USB Bridge */ +&pcie2_rc { + clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + num-lanes = <1>; + phy-names = "pcie-phy"; + phys = <&serdes1_pcie2_1l_link>; + reset-gpios = <&som_gpio_expander 3 GPIO_ACTIVE_HIGH>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; + status = "okay"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + usb@0 { + compatible = "pci104c,8241"; + reg = <0x0 0x0 0x0 0x0 0x0>; + ti,pwron-active-high; + }; + }; +}; + +/* PCIE for On-module Wi-Fi */ +&pcie3_rc { + clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + num-lanes = <1>; + phy-names = "pcie-phy"; + phys = <&serdes0_pcie3_1l_link>; + reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_HIGH>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; + status = "okay"; +}; + +&serdes0 { + status = "okay"; + + /* Aquila PCIE_2 */ + serdes0_pcie1_2l_link: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + cdns,num-lanes = <2>; + cdns,phy-type = ; + }; + + /* On-module PCIe Wi-Fi */ + serdes0_pcie3_1l_link: phy@2 { + reg = <2>; + #phy-cells = <0>; + resets = <&serdes_wiz0 3>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + }; + + /* Aquila USB0 SS */ + serdes0_usb0_ss_link: phy@3 { + reg = <3>; + #phy-cells = <0>; + resets = <&serdes_wiz0 4>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + }; +}; + +&serdes1 { + status = "okay"; + + /* Aquila PCIE_1 */ + serdes1_pcie0_2l_link: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + cdns,num-lanes = <2>; + cdns,phy-type = ; + }; + + /* On-module PCIe USB Bridge */ + serdes1_pcie2_1l_link: phy@2 { + reg = <2>; + #phy-cells = <0>; + resets = <&serdes_wiz1 3>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + }; +}; + +&serdes2 { + status = "disabled"; + + /* Aquila ETH_2 xGMII */ + serdes2_sgmii_link: phy@3 { + reg = <3>; + #phy-cells = <0>; + resets = <&serdes_wiz2 4>; + cdns,num-lanes = <1>; + cdns,phy-type = ; + }; +}; + +&serdes4 { + status = "disabled"; + + /* Aquila DP_1 */ + serdes4_dp0_link: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + cdns,max-bit-rate = <5400>; + cdns,num-lanes = <4>; + cdns,phy-type = ; + }; +}; + +&serdes_refclk { + clock-frequency = <100000000>; + status = "okay"; +}; + +&serdes_ln_ctrl { + idle-states = , /* Aquila PCIE_2 L0 */ + , /* Aquila PCIE_2 L1 */ + , /* On-module PCIe Wi-Fi */ + , /* Aquila USB0 SS */ + , /* Aquila PCIE_1 L0 */ + , /* Aquila PCIE_1 L1 */ + , /* On-module PCIe USB Bridge */ + , /* Aquila SGMII MSP_9 */ + , /* Aquila SGMII MSP_6 */ + , /* Aquila SGMII MSP_7 */ + , /* Aquila SGMII MSP_8 */ + , /* Aquila ETH_2 xGMII */ + , /* Aquila DP L0 */ + , /* Aquila DP L1 */ + , /* Aquila DP L2 */ + ; /* Aquila DP L3 */ +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes_wiz1 { + status = "okay"; +}; + +&serdes_wiz2 { + status = "disabled"; +}; + +&serdes_wiz4 { + status = "disabled"; +}; + +/* Aquila ADC_[1-4] */ +&tscadc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_adc0>; + status = "disabled"; + + adc { + ti,adc-channels = <0 1 2 3>; + }; +}; + +&usb0 { + phys = <&serdes0_usb0_ss_link>; + phy-names = "cdns3,usb3-phy"; + dr_mode = "otg"; + maximum-speed = "super-speed"; + usb-role-switch; + status = "disabled"; +}; + +&usb_serdes_mux { + idle-states = <0>; /* USB0 to SERDES lane 3 */ +}; + +&usbss0 { + ti,vbus-divider; + status = "disabled"; +}; + +&wkup_gpio0 { + gpio-line-names = + "", /* 0 */ + "", + "", + "AQUILA_C53", + "AQUILA_B55", + "AQUILA_B56", + "AQUILA_B32", + "AQUILA_B34", + "AQUILA_C17", + "AQUILA_C16", + "AQUILA_D22", /* 10 */ + "", + "", + "", + "", + "", + "AQUILA_B65", + "AQUILA_C20", + "AQUILA_B63", + "AQUILA_B68", + "AQUILA_B67", /* 20 */ + "AQUILA_B61", + "AQUILA_B60", + "AQUILA_B70", + "AQUILA_B71", + "AQUILA_B72", + "AQUILC_B73", + "AQUILA_B66", + "AQUILA_B62", + "AQUILA_C21", + "AQUILA_C22", /* 30 */ + "AQUILA_C23", + "AQUILA_C01", + "AQUILA_C02", + "", + "AQUILA_D21", + "", + "AQUILA_C03", + "AQUILA_C24", + "AQUILA_C04", + "AQUILA_B84", /* 40 */ + "", + "AQUILA_B86", + "AQUILA_B87", + "", + "", + "AQUILA_B83", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "AQUILA_B31", + "AQUILA_B33", + "AQUILA_B50", /* 60 */ + "AQUILA_B51", + "", + "", + "", + "AQUILA_D08", + "", + "", + "", + "", + "", /* 70 */ + "AQUILA_D01", + "AQUILA_D02", + "AQUILA_D03", + "AQUILA_D04", + "AQUILA_D54", + "AQUILA_D55", + "AQUILA_C55", + "AQUILA_C56", + "", + "AQUILA_C36", /* 80 */ + "", + "", + "", + "", + "", + "", + "AQUILA_D07", + ""; + + status = "okay"; +}; + +/* On-module I2C - WKUP_I2C0 */ +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + som_gpio_expander: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "USB_MUX_SEL", + "COLD_RESET_REQ", + "PWR_DOWN_REQ", + "PCIE_3_RESET#", + "PCIE_4_RESET#", + "WIFI_DISABLE", + "BT_DISABLE", + "SDIO_PWR_SEL_3.3V"; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + tps62873a: regulator@40 { + compatible = "ti,tps62873"; + reg = <0x40>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <600000>; + regulator-name = "+VDD_CPU_AVS"; + }; + + tps62873b: regulator@43 { + compatible = "ti,tps62873"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <840000>; + regulator-min-microvolt = <760000>; + regulator-name = "+V0.8_VDD_CORE"; + }; + + pmic_tps6594: pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + gpio-controller; + buck12-supply = <®_vin>; + buck3-supply = <®_vin>; + buck4-supply = <®_vin>; + buck5-supply = <®_vin>; + ldo1-supply = <®_vin>; + ldo2-supply = <®_vin>; + ldo3-supply = <®_vin>; + ldo4-supply = <®_vin>; + system-power-controller; + ti,primary-pmic; + + regulators { + reg_vdd_ddr: buck12 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+V1.1_VDD_DDR (PMIC BUCK12)"; + }; + + reg_vdd_ram: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+V0.85_VDD_RAM (PMIC BUCK3)"; + }; + + reg_vdd_io: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_VDD_IO (PMIC BUCK4)"; + }; + + reg_3v3_vio: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_VIO (PMIC BUCK5)"; + }; + + reg_vda_phy: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_VDA_PHY (PMIC LDO1)"; + }; + + reg_2v5_eth: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "+V2.5_ETH (PMIC LDO2)"; + }; + + reg_vda_dll: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <800000>; + regulator-min-microvolt = <800000>; + regulator-name = "+V0.8_VDA_DLL (PMIC LDO3)"; + }; + + reg_vda_pll: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V0.8_VDA_PLL (PMIC LDO4)"; + }; + }; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&wkup0_crit { + temperature = <105000>; +}; + +&wkup0_thermal { + trips { + wkup0_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + wkup0_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&wkup1_crit { + temperature = <105000>; +}; + +&wkup1_thermal { + trips { + wkup1_alert0: trip-point0 { + temperature = <70000>; + hysteresis = <2000>; + type = "active"; + }; + + wkup1_alert1: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&wkup_gpio_intr { + status = "okay"; +}; + +/* Aquila UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + status = "disabled"; +}; + +#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" +#include "k3-j784s4-ti-ipc-firmware.dtsi" diff --git a/dts/upstream/src/arm64/ti/k3-am69-sk.dts b/dts/upstream/src/arm64/ti/k3-am69-sk.dts index 5896e57b5b9..abe2f21e0e1 100644 --- a/dts/upstream/src/arm64/ti/k3-am69-sk.dts +++ b/dts/upstream/src/arm64/ti/k3-am69-sk.dts @@ -236,8 +236,8 @@ main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ - J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ + J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ >; }; @@ -416,8 +416,8 @@ mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ - J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (G34) MCU_I2C0_SDA */ >; }; @@ -771,7 +771,7 @@ &mcu_cpsw_port1 { status = "okay"; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&mcu_phy0>; bootph-all; }; diff --git a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts index f684ce6ad9a..3e5efdfe87f 100644 --- a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts +++ b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts @@ -323,6 +323,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status = "okay"; }; &davinci_mdio { @@ -334,7 +335,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi index 692c4745040..fec1db8b133 100644 --- a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi @@ -432,6 +432,8 @@ "tx4", "tx5", "tx6", "tx7", "rx"; + status = "disabled"; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dts b/dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dts index 352fb60e6ce..8040b6528c1 100644 --- a/dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dts +++ b/dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dts @@ -663,6 +663,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>; + status = "okay"; }; &davinci_mdio { @@ -677,7 +678,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-j721e-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j721e-common-proc-board.dts index 45311438315..47702fb279a 100644 --- a/dts/upstream/src/arm64/ti/k3-j721e-common-proc-board.dts +++ b/dts/upstream/src/arm64/ti/k3-j721e-common-proc-board.dts @@ -769,6 +769,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status = "okay"; }; &davinci_mdio { @@ -780,7 +781,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso b/dts/upstream/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso index f84aa9f9454..3bfe6036a8e 100644 --- a/dts/upstream/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso +++ b/dts/upstream/src/arm64/ti/k3-j721e-evm-gesi-exp-board.dtso @@ -37,7 +37,7 @@ &cpsw0_port1 { status = "okay"; phy-handle = <&cpsw9g_phy12>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 1>; }; @@ -45,7 +45,7 @@ &cpsw0_port2 { status = "okay"; phy-handle = <&cpsw9g_phy15>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 2>; }; @@ -53,7 +53,7 @@ &cpsw0_port3 { status = "okay"; phy-handle = <&cpsw9g_phy0>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 3>; }; @@ -61,7 +61,7 @@ &cpsw0_port4 { status = "okay"; phy-handle = <&cpsw9g_phy3>; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; mac-address = [00 00 00 00 00 00]; phys = <&cpsw0_phy_gmii_sel 4>; }; diff --git a/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi index 42a21398e38..d5e5e89be5e 100644 --- a/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi @@ -551,6 +551,8 @@ "tx4", "tx5", "tx6", "tx7", "rx"; + status = "disabled"; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/ti/k3-j721e-sk.dts b/dts/upstream/src/arm64/ti/k3-j721e-sk.dts index 5e5784ef6f8..050776cb4df 100644 --- a/dts/upstream/src/arm64/ti/k3-j721e-sk.dts +++ b/dts/upstream/src/arm64/ti/k3-j721e-sk.dts @@ -474,6 +474,12 @@ J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ >; }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1dc, PIN_OUTPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */ + >; + }; }; &wkup_pmx0 { @@ -536,12 +542,6 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1dc, PIN_OUTPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */ - >; - }; - wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ @@ -1034,6 +1034,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status = "okay"; }; &davinci_mdio { @@ -1045,7 +1046,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j721s2-common-proc-board.dts index 9e43dcff8ef..4fea9951911 100644 --- a/dts/upstream/src/arm64/ti/k3-j721s2-common-proc-board.dts +++ b/dts/upstream/src/arm64/ti/k3-j721s2-common-proc-board.dts @@ -457,6 +457,7 @@ &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; + status = "okay"; }; &davinci_mdio { @@ -469,7 +470,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso b/dts/upstream/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso index 8583178fa1f..6869a95c621 100644 --- a/dts/upstream/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso +++ b/dts/upstream/src/arm64/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -80,6 +80,6 @@ &main_cpsw_port1 { status = "okay"; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&main_cpsw_phy0>; }; diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi index 837097751c1..2a7f9c51973 100644 --- a/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi @@ -552,6 +552,8 @@ "tx4", "tx5", "tx6", "tx7", "rx"; + status = "disabled"; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts index e0e303da7e1..7baf5764862 100644 --- a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts +++ b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts @@ -228,6 +228,11 @@ }; }; +&audio_refclk1 { + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 15>; +}; + &cpsw_mac_syscon { bootph-all; }; @@ -388,7 +393,7 @@ }; &cpsw_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&cpsw3g_phy0>; status = "okay"; bootph-all; diff --git a/dts/upstream/src/arm64/ti/k3-j722s-main.dtsi b/dts/upstream/src/arm64/ti/k3-j722s-main.dtsi index d57fdd38bdc..873415ec4fa 100644 --- a/dts/upstream/src/arm64/ti/k3-j722s-main.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j722s-main.dtsi @@ -437,24 +437,6 @@ mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */ <0x10 0x3>; /* SERDES1 lane0 select */ }; - - audio_refclk0: clock@82e0 { - compatible = "ti,am62-audio-refclk"; - reg = <0x82e0 0x4>; - clocks = <&k3_clks 157 0>; - assigned-clocks = <&k3_clks 157 0>; - assigned-clock-parents = <&k3_clks 157 15>; - #clock-cells = <0>; - }; - - audio_refclk1: clock@82e4 { - compatible = "ti,am62-audio-refclk"; - reg = <0x82e4 0x4>; - clocks = <&k3_clks 157 18>; - assigned-clocks = <&k3_clks 157 18>; - assigned-clock-parents = <&k3_clks 157 33>; - #clock-cells = <0>; - }; }; &wkup_conf { diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/dts/upstream/src/arm64/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso index 685305092bd..22533d678f7 100644 --- a/dts/upstream/src/arm64/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso +++ b/dts/upstream/src/arm64/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso @@ -75,5 +75,6 @@ dma-coherent; phys = <&serdes0_pcie1_link>; phy-names = "pcie-phy"; + bootph-all; }; }; diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi index 419c1a70e02..e5073557773 100644 --- a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -270,8 +270,8 @@ main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ - J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ + J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ + J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ >; }; @@ -920,7 +920,7 @@ &mcu_cpsw_port1 { status = "okay"; - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&mcu_phy0>; }; @@ -944,7 +944,7 @@ }; &main_cpsw1_port1 { - phy-mode = "rgmii-rxid"; + phy-mode = "rgmii-id"; phy-handle = <&main_cpsw1_phy0>; status = "okay"; }; @@ -970,6 +970,7 @@ &serdes_refclk { status = "okay"; clock-frequency = <100000000>; + bootph-all; }; &dss { @@ -984,6 +985,14 @@ <&k3_clks 218 22>; }; +&pcie1_ctrl { + bootph-all; +}; + +&serdes_ln_ctrl { + bootph-all; +}; + &serdes0 { status = "okay"; @@ -993,6 +1002,7 @@ #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + bootph-all; }; serdes0_usb_link: phy@3 { diff --git a/dts/upstream/src/arm64/ti/k3-pinctrl.h b/dts/upstream/src/arm64/ti/k3-pinctrl.h index e46f7bf5270..dc8e03ae74c 100644 --- a/dts/upstream/src/arm64/ti/k3-pinctrl.h +++ b/dts/upstream/src/arm64/ti/k3-pinctrl.h @@ -123,6 +123,8 @@ #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff --git a/dts/upstream/src/loongarch/loongson-2k0500.dtsi b/dts/upstream/src/loongarch/loongson-2k0500.dtsi index 588ebc3bded..e759fae77dc 100644 --- a/dts/upstream/src/loongarch/loongson-2k0500.dtsi +++ b/dts/upstream/src/loongarch/loongson-2k0500.dtsi @@ -131,6 +131,7 @@ reg-names = "main", "isr0"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <2>; interrupt-parent = <&cpuintc>; interrupts = <2>; @@ -149,6 +150,7 @@ reg-names = "main", "isr0"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <2>; interrupt-parent = <&cpuintc>; interrupts = <4>; @@ -164,6 +166,7 @@ compatible = "loongson,ls2k0500-eiointc"; reg = <0x0 0x1fe11600 0x0 0xea00>; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&cpuintc>; interrupts = <3>; @@ -380,7 +383,7 @@ }; uart0: serial@1ff40800 { - compatible = "ns16550a"; + compatible = "loongson,ls2k0500-uart", "ns16550a"; reg = <0x0 0x1ff40800 0x0 0x10>; clock-frequency = <100000000>; interrupt-parent = <&eiointc>; diff --git a/dts/upstream/src/loongarch/loongson-2k1000.dtsi b/dts/upstream/src/loongarch/loongson-2k1000.dtsi index d8e01e2534d..be4f7d11966 100644 --- a/dts/upstream/src/loongarch/loongson-2k1000.dtsi +++ b/dts/upstream/src/loongarch/loongson-2k1000.dtsi @@ -46,7 +46,7 @@ }; /* i2c of the dvi eeprom edid */ - i2c-gpio-0 { + i2c-0 { compatible = "i2c-gpio"; scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -57,7 +57,7 @@ }; /* i2c of the eeprom edid */ - i2c-gpio-1 { + i2c-1 { compatible = "i2c-gpio"; scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -114,6 +114,7 @@ <0x0 0x1fe01140 0x0 0x8>; reg-names = "main", "isr0", "isr1"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <2>; interrupt-parent = <&cpuintc>; interrupts = <2>; @@ -131,6 +132,7 @@ <0x0 0x1fe01148 0x0 0x8>; reg-names = "main", "isr0", "isr1"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <2>; interrupt-parent = <&cpuintc>; interrupts = <3>; @@ -297,7 +299,7 @@ }; uart0: serial@1fe20000 { - compatible = "ns16550a"; + compatible = "loongson,ls2k1000-uart", "loongson,ls2k0500-uart", "ns16550a"; reg = <0x0 0x1fe20000 0x0 0x10>; clock-frequency = <125000000>; interrupt-parent = <&liointc0>; @@ -437,54 +439,47 @@ gmac0: ethernet@3,0 { reg = <0x1800 0x0 0x0 0x0 0x0>; - interrupt-parent = <&liointc0>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, - <13 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&liointc0 12 IRQ_TYPE_LEVEL_HIGH>, + <&liointc0 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; status = "disabled"; }; gmac1: ethernet@3,1 { reg = <0x1900 0x0 0x0 0x0 0x0>; - interrupt-parent = <&liointc0>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&liointc0 14 IRQ_TYPE_LEVEL_HIGH>, + <&liointc0 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; status = "disabled"; }; ehci0: usb@4,1 { reg = <0x2100 0x0 0x0 0x0 0x0>; - interrupt-parent = <&liointc1>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&liointc1 18 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; ohci0: usb@4,2 { reg = <0x2200 0x0 0x0 0x0 0x0>; - interrupt-parent = <&liointc1>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&liointc1 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; display@6,0 { reg = <0x3000 0x0 0x0 0x0 0x0>; - interrupt-parent = <&liointc0>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&liointc0 28 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; hda@7,0 { reg = <0x3800 0x0 0x0 0x0 0x0>; - interrupt-parent = <&liointc0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&liointc0 4 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sata: sata@8,0 { reg = <0x4000 0x0 0x0 0x0 0x0>; - interrupt-parent = <&liointc0>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&liointc0 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/dts/upstream/src/loongarch/loongson-2k2000.dtsi b/dts/upstream/src/loongarch/loongson-2k2000.dtsi index 00cc485b753..3678c084adf 100644 --- a/dts/upstream/src/loongarch/loongson-2k2000.dtsi +++ b/dts/upstream/src/loongarch/loongson-2k2000.dtsi @@ -126,6 +126,7 @@ reg = <0x0 0x1fe01400 0x0 0x64>; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <2>; interrupt-parent = <&cpuintc>; interrupts = <2>; @@ -140,6 +141,7 @@ compatible = "loongson,ls2k2000-eiointc"; reg = <0x0 0x1fe01600 0x0 0xea00>; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&cpuintc>; interrupts = <3>; @@ -149,6 +151,7 @@ compatible = "loongson,pch-pic-1.0"; reg = <0x0 0x10000000 0x0 0x400>; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <2>; loongson,pic-base-vec = <0>; interrupt-parent = <&eiointc>; @@ -250,7 +253,7 @@ }; uart0: serial@1fe001e0 { - compatible = "ns16550a"; + compatible = "loongson,ls2k2000-uart", "loongson,ls2k1500-uart", "ns16550a"; reg = <0x0 0x1fe001e0 0x0 0x10>; clock-frequency = <100000000>; interrupt-parent = <&liointc>; @@ -291,65 +294,57 @@ gmac0: ethernet@3,0 { reg = <0x1800 0x0 0x0 0x0 0x0>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, - <13 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&pic 12 IRQ_TYPE_LEVEL_HIGH>, + <&pic 13 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; - interrupt-parent = <&pic>; status = "disabled"; }; gmac1: ethernet@3,1 { reg = <0x1900 0x0 0x0 0x0 0x0>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&pic 14 IRQ_TYPE_LEVEL_HIGH>, + <&pic 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; - interrupt-parent = <&pic>; status = "disabled"; }; gmac2: ethernet@3,2 { reg = <0x1a00 0x0 0x0 0x0 0x0>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, - <18 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&pic 17 IRQ_TYPE_LEVEL_HIGH>, + <&pic 18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; - interrupt-parent = <&pic>; status = "disabled"; }; xhci0: usb@4,0 { reg = <0x2000 0x0 0x0 0x0 0x0>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&pic>; + interrupts-extended = <&pic 48 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; xhci1: usb@19,0 { reg = <0xc800 0x0 0x0 0x0 0x0>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&pic>; + interrupts-extended = <&pic 22 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; display@6,1 { reg = <0x3100 0x0 0x0 0x0 0x0>; - interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&pic>; + interrupts-extended = <&pic 28 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; i2s@7,0 { reg = <0x3800 0x0 0x0 0x0 0x0>; - interrupts = <78 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&pic 78 IRQ_TYPE_LEVEL_HIGH>, + <&pic 79 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; - interrupt-parent = <&pic>; status = "disabled"; }; sata: sata@8,0 { reg = <0x4000 0x0 0x0 0x0 0x0>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&pic>; + interrupts-extended = <&pic 16 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/dts/upstream/src/powerpc/asp834x-redboot.dts b/dts/upstream/src/powerpc/asp834x-redboot.dts index 52a84561c4f..33ddb17d187 100644 --- a/dts/upstream/src/powerpc/asp834x-redboot.dts +++ b/dts/upstream/src/powerpc/asp834x-redboot.dts @@ -72,7 +72,7 @@ reg = <0xff000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/fsl/ge_imp3a.dts b/dts/upstream/src/powerpc/fsl/ge_imp3a.dts index da3de8e2b7d..9e5c01cfac2 100644 --- a/dts/upstream/src/powerpc/fsl/ge_imp3a.dts +++ b/dts/upstream/src/powerpc/fsl/ge_imp3a.dts @@ -94,7 +94,7 @@ gpio-controller; }; - wdt@4,800 { + watchdog@4,800 { compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", "gef,fpga-wdt"; reg = <0x4 0x800 0x8>; @@ -103,7 +103,7 @@ }; /* Second watchdog available, driver currently supports one. - wdt@4,808 { + watchdog@4,808 { compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", "gef,fpga-wdt"; reg = <0x4 0x808 0x8>; diff --git a/dts/upstream/src/powerpc/fsl/gef_ppc9a.dts b/dts/upstream/src/powerpc/fsl/gef_ppc9a.dts index fc92bb032c5..48a81430a8a 100644 --- a/dts/upstream/src/powerpc/fsl/gef_ppc9a.dts +++ b/dts/upstream/src/powerpc/fsl/gef_ppc9a.dts @@ -82,7 +82,7 @@ reg = <0x4 0x0 0x40>; }; - wdt@4,2000 { + watchdog@4,2000 { compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00", "gef,fpga-wdt"; reg = <0x4 0x2000 0x8>; @@ -90,7 +90,7 @@ interrupt-parent = <&gef_pic>; }; /* Second watchdog available, driver currently supports one. - wdt@4,2010 { + watchdog@4,2010 { compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00", "gef,fpga-wdt"; reg = <0x4 0x2010 0x8>; diff --git a/dts/upstream/src/powerpc/fsl/gef_sbc310.dts b/dts/upstream/src/powerpc/fsl/gef_sbc310.dts index 47ae85c3463..8eb254b1738 100644 --- a/dts/upstream/src/powerpc/fsl/gef_sbc310.dts +++ b/dts/upstream/src/powerpc/fsl/gef_sbc310.dts @@ -79,7 +79,7 @@ reg = <0x4 0x0 0x40>; }; - wdt@4,2000 { + watchdog@4,2000 { compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", "gef,fpga-wdt"; reg = <0x4 0x2000 0x8>; @@ -87,7 +87,7 @@ interrupt-parent = <&gef_pic>; }; /* - wdt@4,2010 { + watchdog@4,2010 { compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", "gef,fpga-wdt"; reg = <0x4 0x2010 0x8>; diff --git a/dts/upstream/src/powerpc/fsl/gef_sbc610.dts b/dts/upstream/src/powerpc/fsl/gef_sbc610.dts index 5322be44b62..02edbb262b8 100644 --- a/dts/upstream/src/powerpc/fsl/gef_sbc610.dts +++ b/dts/upstream/src/powerpc/fsl/gef_sbc610.dts @@ -82,14 +82,14 @@ reg = <0x4 0x0 0x40>; }; - wdt@4,2000 { + watchdog@4,2000 { compatible = "gef,fpga-wdt"; reg = <0x4 0x2000 0x8>; interrupts = <0x1a 0x4>; interrupt-parent = <&gef_pic>; }; /* Second watchdog available, driver currently supports one. - wdt@4,2010 { + watchdog@4,2010 { compatible = "gef,fpga-wdt"; reg = <0x4 0x2010 0x8>; interrupts = <0x1b 0x4>; diff --git a/dts/upstream/src/powerpc/mpc5121.dtsi b/dts/upstream/src/powerpc/mpc5121.dtsi index d3fc8062fbc..a278fb7b9e7 100644 --- a/dts/upstream/src/powerpc/mpc5121.dtsi +++ b/dts/upstream/src/powerpc/mpc5121.dtsi @@ -112,7 +112,7 @@ }; /* Watchdog timer */ - wdt@900 { + watchdog@900 { compatible = "fsl,mpc5121-wdt"; reg = <0x900 0x100>; }; diff --git a/dts/upstream/src/powerpc/mpc8313erdb.dts b/dts/upstream/src/powerpc/mpc8313erdb.dts index a8315795b2c..09508b4c8c7 100644 --- a/dts/upstream/src/powerpc/mpc8313erdb.dts +++ b/dts/upstream/src/powerpc/mpc8313erdb.dts @@ -99,7 +99,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc8315erdb.dts b/dts/upstream/src/powerpc/mpc8315erdb.dts index a89cb3139ca..a8f68d6e50b 100644 --- a/dts/upstream/src/powerpc/mpc8315erdb.dts +++ b/dts/upstream/src/powerpc/mpc8315erdb.dts @@ -100,7 +100,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc832x_rdb.dts b/dts/upstream/src/powerpc/mpc832x_rdb.dts index ecebc27a289..ba7caaf98fd 100644 --- a/dts/upstream/src/powerpc/mpc832x_rdb.dts +++ b/dts/upstream/src/powerpc/mpc832x_rdb.dts @@ -52,7 +52,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc8349emitx.dts b/dts/upstream/src/powerpc/mpc8349emitx.dts index d4ebbb93de0..13f17232ba8 100644 --- a/dts/upstream/src/powerpc/mpc8349emitx.dts +++ b/dts/upstream/src/powerpc/mpc8349emitx.dts @@ -53,7 +53,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; // from bootloader - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc8349emitxgp.dts b/dts/upstream/src/powerpc/mpc8349emitxgp.dts index bcf68a0a7b5..eae0afd5abb 100644 --- a/dts/upstream/src/powerpc/mpc8349emitxgp.dts +++ b/dts/upstream/src/powerpc/mpc8349emitxgp.dts @@ -51,7 +51,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; // from bootloader - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc836x_rdk.dts b/dts/upstream/src/powerpc/mpc836x_rdk.dts index a0cc1953484..4ff38e1a218 100644 --- a/dts/upstream/src/powerpc/mpc836x_rdk.dts +++ b/dts/upstream/src/powerpc/mpc836x_rdk.dts @@ -62,7 +62,7 @@ /* filled by u-boot */ bus-frequency = <0>; - wdt@200 { + watchdog@200 { compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; }; diff --git a/dts/upstream/src/powerpc/mpc8377_rdb.dts b/dts/upstream/src/powerpc/mpc8377_rdb.dts index 7df452efa95..f137ccb8cfd 100644 --- a/dts/upstream/src/powerpc/mpc8377_rdb.dts +++ b/dts/upstream/src/powerpc/mpc8377_rdb.dts @@ -99,7 +99,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc8377_wlan.dts b/dts/upstream/src/powerpc/mpc8377_wlan.dts index d8e7d40aeae..ce254dd74dd 100644 --- a/dts/upstream/src/powerpc/mpc8377_wlan.dts +++ b/dts/upstream/src/powerpc/mpc8377_wlan.dts @@ -89,7 +89,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc8378_rdb.dts b/dts/upstream/src/powerpc/mpc8378_rdb.dts index bdcfe83a561..19e5473d416 100644 --- a/dts/upstream/src/powerpc/mpc8378_rdb.dts +++ b/dts/upstream/src/powerpc/mpc8378_rdb.dts @@ -99,7 +99,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/powerpc/mpc8379_rdb.dts b/dts/upstream/src/powerpc/mpc8379_rdb.dts index a5f702304a3..61519acca22 100644 --- a/dts/upstream/src/powerpc/mpc8379_rdb.dts +++ b/dts/upstream/src/powerpc/mpc8379_rdb.dts @@ -97,7 +97,7 @@ reg = <0xe0000000 0x00000200>; bus-frequency = <0>; - wdt@200 { + watchdog@200 { device_type = "watchdog"; compatible = "mpc83xx_wdt"; reg = <0x200 0x100>; diff --git a/dts/upstream/src/riscv/anlogic/dr1v90-mlkpai-fs01.dts b/dts/upstream/src/riscv/anlogic/dr1v90-mlkpai-fs01.dts new file mode 100644 index 00000000000..597407655ef --- /dev/null +++ b/dts/upstream/src/riscv/anlogic/dr1v90-mlkpai-fs01.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +#include "dr1v90.dtsi" + +/ { + model = "Milianke MLKPAI-FS01"; + compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/dts/upstream/src/riscv/anlogic/dr1v90.dtsi b/dts/upstream/src/riscv/anlogic/dr1v90.dtsi new file mode 100644 index 00000000000..a5d0765ade3 --- /dev/null +++ b/dts/upstream/src/riscv/anlogic/dr1v90.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Junhui Liu + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Anlogic DR1V90"; + compatible = "anlogic,dr1v90"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <800000000>; + + cpu@0 { + compatible = "nuclei,ux900", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <256>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + reg = <0>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", + "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + "zihintpause", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aclint_mswi: interrupt-controller@68031000 { + compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi"; + reg = <0x0 0x68031000 0x0 0x4000>; + interrupts-extended = <&cpu0_intc 3>; + }; + + aclint_mtimer: timer@68035000 { + compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer"; + reg = <0x0 0x68035000 0x0 0x8000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu0_intc 7>; + }; + + aclint_sswi: interrupt-controller@6803d000 { + compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi"; + reg = <0x0 0x6803d000 0x0 0x3000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 1>; + }; + + plic: interrupt-controller@6c000000 { + compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x6c000000 0x0 0x4000000>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + riscv,ndev = <150>; + }; + + uart0: serial@f8400000 { + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf8400000 0x0 0x1000>; + clock-frequency = <50000000>; + interrupts = <71>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@f8401000 { + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf8401000 0x0 0x1000>; + clock-frequency = <50000000>; + interrupts = <72>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; +}; diff --git a/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire.dts b/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire.dts index 55e30f3636d..f44ad8e6f4e 100644 --- a/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire.dts +++ b/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire.dts @@ -79,6 +79,26 @@ }; +&gpio0 { + interrupts = <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + ngpios = <14>; + status = "okay"; +}; + +&gpio1 { + interrupts = <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <34>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + ngpios = <24>; + status = "okay"; +}; + &gpio2 { interrupts = <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, @@ -199,6 +219,82 @@ status = "okay"; }; +&qspi { + status = "okay"; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>, <&gpio0 12 GPIO_ACTIVE_LOW>; + num-cs = <2>; + + adc@0 { + compatible = "microchip,mcp3464r"; + reg = <0>; /* CE0 */ + spi-cpol; + spi-cpha; + spi-max-frequency = <5000000>; + microchip,hw-device-address = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + /* CH0 to AGND */ + reg = <0>; + label = "CH0"; + }; + + channel@1 { + /* CH1 to AGND */ + reg = <1>; + label = "CH1"; + }; + + channel@2 { + /* CH2 to AGND */ + reg = <2>; + label = "CH2"; + }; + + channel@3 { + /* CH3 to AGND */ + reg = <3>; + label = "CH3"; + }; + + channel@4 { + /* CH4 to AGND */ + reg = <4>; + label = "CH4"; + }; + + channel@5 { + /* CH5 to AGND */ + reg = <5>; + label = "CH5"; + }; + + channel@6 { + /* CH6 to AGND */ + reg = <6>; + label = "CH6"; + }; + + channel@7 { + /* CH7 is connected to AGND */ + reg = <7>; + label = "CH7"; + }; + }; + + mmc@1 { + compatible = "mmc-spi-slot"; + reg = <1>; + gpios = <&gpio2 31 1>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <5000000>; + disable-wp; + }; +}; + + &syscontroller { microchip,bitstream-flash = <&sys_ctrl_flash>; status = "okay"; diff --git a/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts b/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts index 03ce2cee4e9..850fa1d25be 100644 --- a/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts +++ b/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts @@ -47,6 +47,16 @@ gpios = <&gpio 2 GPIO_ACTIVE_LOW>; }; + fan1 { + compatible = "pwm-fan"; + pwms = <&pwm1 2 7812500 0>; + }; + + fan2 { + compatible = "pwm-fan"; + pwms = <&pwm1 3 7812500 0>; + }; + led-controller-1 { compatible = "pwm-leds"; diff --git a/dts/upstream/src/riscv/sophgo/cv1800b-milkv-duo.dts b/dts/upstream/src/riscv/sophgo/cv1800b-milkv-duo.dts index 9feb520eaec..0e6d79e6e3a 100644 --- a/dts/upstream/src/riscv/sophgo/cv1800b-milkv-duo.dts +++ b/dts/upstream/src/riscv/sophgo/cv1800b-milkv-duo.dts @@ -100,3 +100,8 @@ pinctrl-names = "default"; status = "okay"; }; + +&usb { + dr_mode = "host"; + status = "okay"; +}; diff --git a/dts/upstream/src/riscv/sophgo/cv180x.dtsi b/dts/upstream/src/riscv/sophgo/cv180x.dtsi index ccdb4549865..1b2b1969a64 100644 --- a/dts/upstream/src/riscv/sophgo/cv180x.dtsi +++ b/dts/upstream/src/riscv/sophgo/cv180x.dtsi @@ -25,6 +25,32 @@ #size-cells = <1>; ranges; + syscon: syscon@3000000 { + compatible = "sophgo,cv1800b-top-syscon", + "syscon", "simple-mfd"; + reg = <0x03000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usbphy: phy@48 { + compatible = "sophgo,cv1800b-usb2-phy"; + reg = <0x48 0x4>; + #phy-cells = <0>; + clocks = <&clk CLK_USB_125M>, + <&clk CLK_USB_33K>, + <&clk CLK_USB_12M>; + clock-names = "app", "stb", "lpm"; + resets = <&rst RST_COMBO_PHY0>; + }; + + dmamux: dma-router@154 { + compatible = "sophgo,cv1800b-dmamux"; + reg = <0x154 0x8>, <0x298 0x4>; + #dma-cells = <2>; + dma-masters = <&dmac>; + }; + }; + rst: reset-controller@3003000 { compatible = "sophgo,cv1800b-reset"; reg = <0x3003000 0x1000>; @@ -406,6 +432,22 @@ status = "disabled"; }; + usb: usb@4340000 { + compatible = "sophgo,cv1800b-usb"; + reg = <0x04340000 0x10000>; + clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>; + clock-names = "otg", "utmi"; + g-np-tx-fifo-size = <32>; + g-rx-fifo-size = <536>; + g-tx-fifo-size = <768 512 512 384 128 128>; + interrupts = ; + phys = <&usbphy>; + phy-names = "usb2-phy"; + resets = <&rst RST_USB>; + reset-names = "dwc2"; + status = "disabled"; + }; + rtc@5025000 { compatible = "sophgo,cv1800b-rtc", "syscon"; reg = <0x5025000 0x2000>; diff --git a/dts/upstream/src/riscv/sophgo/cv1812h-huashan-pi.dts b/dts/upstream/src/riscv/sophgo/cv1812h-huashan-pi.dts index 4a5835fa9e9..aedf79f4740 100644 --- a/dts/upstream/src/riscv/sophgo/cv1812h-huashan-pi.dts +++ b/dts/upstream/src/riscv/sophgo/cv1812h-huashan-pi.dts @@ -86,3 +86,8 @@ &uart0 { status = "okay"; }; + +&usb { + dr_mode = "host"; + status = "okay"; +}; diff --git a/dts/upstream/src/riscv/sophgo/sg2002-licheerv-nano-b.dts b/dts/upstream/src/riscv/sophgo/sg2002-licheerv-nano-b.dts index 86a712b953a..b1853770d01 100644 --- a/dts/upstream/src/riscv/sophgo/sg2002-licheerv-nano-b.dts +++ b/dts/upstream/src/riscv/sophgo/sg2002-licheerv-nano-b.dts @@ -93,3 +93,8 @@ pinctrl-names = "default"; status = "okay"; }; + +&usb { + dr_mode = "host"; + status = "okay"; +}; diff --git a/dts/upstream/src/riscv/sophgo/sg2042-evb-v1.dts b/dts/upstream/src/riscv/sophgo/sg2042-evb-v1.dts index 3320bc1dd2c..b116dfa904c 100644 --- a/dts/upstream/src/riscv/sophgo/sg2042-evb-v1.dts +++ b/dts/upstream/src/riscv/sophgo/sg2042-evb-v1.dts @@ -164,6 +164,18 @@ }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { @@ -238,6 +250,30 @@ status = "okay"; }; +&spifmc0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; diff --git a/dts/upstream/src/riscv/sophgo/sg2042-evb-v2.dts b/dts/upstream/src/riscv/sophgo/sg2042-evb-v2.dts index 46980e41b88..b2ceae2d882 100644 --- a/dts/upstream/src/riscv/sophgo/sg2042-evb-v2.dts +++ b/dts/upstream/src/riscv/sophgo/sg2042-evb-v2.dts @@ -152,6 +152,18 @@ }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { @@ -226,6 +238,18 @@ status = "okay"; }; +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; diff --git a/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts b/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts index ef3a602172b..54d8386bf9c 100644 --- a/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts +++ b/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts @@ -128,6 +128,18 @@ }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + +&pcie_rc3 { + status = "okay"; +}; + &sd { pinctrl-0 = <&sd_cfg>; pinctrl-names = "default"; @@ -138,6 +150,30 @@ status = "okay"; }; +&spifmc0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; diff --git a/dts/upstream/src/riscv/sophgo/sg2042.dtsi b/dts/upstream/src/riscv/sophgo/sg2042.dtsi index c5e49709b30..ec99da39150 100644 --- a/dts/upstream/src/riscv/sophgo/sg2042.dtsi +++ b/dts/upstream/src/riscv/sophgo/sg2042.dtsi @@ -68,6 +68,30 @@ interrupt-parent = <&intc>; ranges; + spifmc0: spi@7000180000 { + compatible = "sophgo,sg2042-spifmc-nor"; + reg = <0x70 0x00180000 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkgen GATE_CLK_AHB_SF>; + interrupt-parent = <&intc>; + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstgen RST_SF0>; + status = "disabled"; + }; + + spifmc1: spi@7002180000 { + compatible = "sophgo,sg2042-spifmc-nor"; + reg = <0x70 0x02180000 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkgen GATE_CLK_AHB_SF>; + interrupt-parent = <&intc>; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstgen RST_SF1>; + status = "disabled"; + }; + i2c0: i2c@7030005000 { compatible = "snps,designware-i2c"; reg = <0x70 0x30005000 0x0 0x1000>; @@ -240,6 +264,94 @@ #clock-cells = <1>; }; + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; diff --git a/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts b/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts index 2aaaff77831..02f218a1631 100644 --- a/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts +++ b/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts @@ -14,6 +14,8 @@ ethernet0 = ð0; ethernet1 = ð1; serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; }; chosen { @@ -30,6 +32,25 @@ default-state = "on"; }; }; + + reg_dc_in: dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vcc_4v: vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_dc_in>; + }; }; &emmc { @@ -92,6 +113,157 @@ status = "okay"; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ + pagesize = <16>; + read-only; + size = <256>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + + serial-number { + }; + }; + }; +}; + +&i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin-supply = <®_vcc_4v>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; diff --git a/dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts b/dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts new file mode 100644 index 00000000000..29e333b670c --- /dev/null +++ b/dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Yangyu Chen + * Copyright (C) 2025 SpacemiT, Inc + * Copyright (C) 2025 Troy Mitchell + */ + +/dts-v1/; + +#include "k1.dtsi" +#include "k1-pinctrl.dtsi" + +/ { + model = "SpacemiT MusePi Pro"; + compatible = "spacemit,musepi-pro", "spacemit,k1"; + + aliases { + ethernet0 = ð0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "sys-led"; + gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&emmc { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&gmac0_cfg>; + pinctrl-names = "default"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + reset-gpios = <&gpio K1_GPIO(110) GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <100000>; + + rgmii0: phy@1 { + reg = <0x1>; + }; + }; +}; + +&pdma { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_2_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/dts/upstream/src/riscv/spacemit/k1-orangepi-r2s.dts b/dts/upstream/src/riscv/spacemit/k1-orangepi-r2s.dts new file mode 100644 index 00000000000..58098c4a2aa --- /dev/null +++ b/dts/upstream/src/riscv/spacemit/k1-orangepi-r2s.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Michael Opdenacker + */ + +/dts-v1/; + +#include "k1.dtsi" +#include "k1-pinctrl.dtsi" + +/ { + model = "OrangePi R2S"; + compatible = "xunlong,orangepi-r2s", "spacemit,k1"; + + aliases { + serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&emmc { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_cfg>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + reset-gpios = <&gpio K1_GPIO(110) GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <100000>; + + rgmii0: phy@1 { + reg = <0x1>; + }; + }; +}; + +ð1 { + phy-handle = <&rgmii1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_cfg>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <250>; + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + reset-gpios = <&gpio K1_GPIO(115) GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <100000>; + + rgmii1: phy@1 { + reg = <0x1>; + }; + }; +}; + +&pdma { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; +}; diff --git a/dts/upstream/src/riscv/spacemit/k1-orangepi-rv2.dts b/dts/upstream/src/riscv/spacemit/k1-orangepi-rv2.dts index 337240ebb7b..41dc8e35e6e 100644 --- a/dts/upstream/src/riscv/spacemit/k1-orangepi-rv2.dts +++ b/dts/upstream/src/riscv/spacemit/k1-orangepi-rv2.dts @@ -15,6 +15,8 @@ aliases { serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; }; chosen { @@ -33,6 +35,56 @@ }; }; +ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_cfg>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + reset-gpios = <&gpio K1_GPIO(110) GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <100000>; + + rgmii0: phy@1 { + reg = <0x1>; + }; + }; +}; + +ð1 { + phy-handle = <&rgmii1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_cfg>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <250>; + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + reset-gpios = <&gpio K1_GPIO(115) GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <100000>; + + rgmii1: phy@1 { + reg = <0x1>; + }; + }; +}; + +&pdma { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; diff --git a/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi b/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi index aff19c86d5f..e922e05ff85 100644 --- a/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi +++ b/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi @@ -59,11 +59,472 @@ }; }; + i2c2_0_cfg: i2c2-0-cfg { + i2c2-0-pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + i2c8_cfg: i2c8-cfg { + i2c8-0-pins { + pinmux = , /* PWR_SCL */ + ; /* PWR_SDA */ + }; + }; + + qspi_cfg: qspi-cfg { + qspi-pins { + pinmux = , /* QSPI_DATA3 */ + , /* QSPI_DATA2 */ + , /* QSPI_DATA1 */ + , /* QSPI_DATA0 */ + ; /* QSPI_CLK */ + + bias-disable; + drive-strength = <19>; + power-source = <3300>; + }; + + qspi-cs1-pins { + pinmux = ; /* QSPI_CS1 */ + bias-pull-up = <0>; + drive-strength = <19>; + power-source = <3300>; + }; + }; + + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { + pinmux = , /* uart0_txd */ + ; /* uart0_rxd */ + power-source = <3300>; + bias-pull-up = <0>; + drive-strength = <19>; + }; + }; + + /omit-if-no-ref/ + uart0_1_cfg: uart0-1-cfg { + uart0-1-pins { + pinmux = , /* uart0_txd */ + ; /* uart0_rxd */ + power-source = <3300>; + bias-pull-up = <0>; + drive-strength = <19>; + }; + }; + + /omit-if-no-ref/ uart0_2_cfg: uart0-2-cfg { uart0-2-pins { - pinmux = , - ; + pinmux = , /* uart0_txd */ + ; /* uart0_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + /omit-if-no-ref/ + uart2_0_cfg: uart2-0-cfg { + uart2-0-pins { + pinmux = , /* uart2_txd */ + ; /* uart2_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart2_0_cts_rts_cfg: uart2-0-cts-rts-cfg { + uart2-0-pins { + pinmux = , /* uart2_cts */ + ; /* uart2_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart3_0_cfg: uart3-0-cfg { + uart3-0-pins { + pinmux = , /* uart3_txd */ + ; /* uart3_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart3_0_cts_rts_cfg: uart3-0-cts-rts-cfg { + uart3-0-pins { + pinmux = , /* uart3_cts */ + ; /* uart3_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart3_1_cfg: uart3-1-cfg { + uart3-1-pins { + pinmux = , /* uart3_txd */ + ; /* uart3_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart3_1_cts_rts_cfg: uart3-1-cts-rts-cfg { + uart3-1-pins { + pinmux = , /* uart3_cts */ + ; /* uart3_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart3_2_cfg: uart3-2-cfg { + uart3-2-pins { + pinmux = , /* uart3_txd */ + ; /* uart3_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart3_2_cts_rts_cfg: uart3-2-cts-rts-cfg { + uart3-2-pins { + pinmux = , /* uart3_cts */ + ; /* uart3_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart4_0_cfg: uart4-0-cfg { + uart4-0-pins { + pinmux = , /* uart4_txd */ + ; /* uart4_rxd */ + power-source = <3300>; + bias-pull-up = <0>; + drive-strength = <19>; + }; + }; + + /omit-if-no-ref/ + uart4_1_cfg: uart4-1-cfg { + uart4-1-pins { + pinmux = , /* uart4_txd */ + ; /* uart4_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart4_1_cts_rts_cfg: uart4-1-cts-rts-cfg { + uart4-1-pins { + pinmux = , /* uart4_cts */ + ; /* uart4_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart4_2_cfg: uart4-2-cfg { + uart4-2-pins { + pinmux = , /* uart4_txd */ + ; /* uart4_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart4_3_cfg: uart4-3-cfg { + uart4-3-pins { + pinmux = , /* uart4_txd */ + ; /* uart4_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart4_3_cts_rts_cfg: uart4-3-cts-rts-cfg { + uart4-3-pins { + pinmux = , /* uart4_cts */ + ; /* uart4_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart4_4_cfg: uart4-4-cfg { + uart4-4-pins { + pinmux = , /* uart4_txd */ + ; /* uart4_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart4_4_cts_rts_cfg: uart4-4-cts-rts-cfg { + uart4-4-pins { + pinmux = , /* uart4_cts */ + ; /* uart4_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart5_0_cfg: uart5-0-cfg { + uart5-0-pins { + pinmux = , /* uart5_txd */ + ; /* uart5_rxd */ + power-source = <3300>; + bias-pull-up = <0>; + drive-strength = <19>; + }; + }; + + /omit-if-no-ref/ + uart5_1_cfg: uart5-1-cfg { + uart5-1-pins { + pinmux = , /* uart5_txd */ + ; /* uart5_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart5_1_cts_rts_cfg: uart5-1-cts-rts-cfg { + uart5-1-pins { + pinmux = , /* uart5_cts */ + ; /* uart5_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart5_2_cfg: uart5-2-cfg { + uart5-2-pins { + pinmux = , /* uart5_txd */ + ; /* uart5_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart5_2_cts_rts_cfg: uart5-2-cts-rts-cfg { + uart5-2-pins { + pinmux = , /* uart5_cts */ + ; /* uart5_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart5_3_cfg: uart5-3-cfg { + uart5-3-pins { + pinmux = , /* uart5_txd */ + ; /* uart5_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart5_3_cts_rts_cfg: uart5-3-cts-rts-cfg { + uart5-3-pins { + pinmux = , /* uart5_cts */ + ; /* uart5_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart6_0_cfg: uart6-0-cfg { + uart6-0-pins { + pinmux = , /* uart6_txd */ + ; /* uart6_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart6_0_cts_rts_cfg: uart6-0-cts-rts-cfg { + uart6-0-pins { + pinmux = , /* uart6_cts */ + ; /* uart6_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart6_1_cfg: uart6-1-cfg { + uart6-1-pins { + pinmux = , /* uart6_txd */ + ; /* uart6_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart6_1_cts_rts_cfg: uart6-1-cts-rts-cfg { + uart6-1-pins { + pinmux = , /* uart6_cts */ + ; /* uart6_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart6_2_cfg: uart6-2-cfg { + uart6-2-pins { + pinmux = , /* uart6_txd */ + ; /* uart6_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart7_0_cfg: uart7-0-cfg { + uart7-0-pins { + pinmux = , /* uart7_txd */ + ; /* uart7_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart7_1_cfg: uart7-1-cfg { + uart7-1-pins { + pinmux = , /* uart7_txd */ + ; /* uart7_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart7_1_cts_rts_cfg: uart7-1-cts-rts-cfg { + uart7-1-pins { + pinmux = , /* uart7_cts */ + ; /* uart7_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart8_0_cfg: uart8-0-cfg { + uart8-0-pins { + pinmux = , /* uart8_txd */ + ; /* uart8_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart8_1_cfg: uart8-1-cfg { + uart8-1-pins { + pinmux = , /* uart8_txd */ + ; /* uart8_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart8_1_cts_rts_cfg: uart8-1-cts-rts-cfg { + uart8-1-pins { + pinmux = , /* uart8_cts */ + ; /* uart8_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart8_2_cfg: uart8-2-cfg { + uart8-2-pins { + pinmux = , /* uart8_txd */ + ; /* uart8_rxd */ + power-source = <3300>; + bias-pull-up = <0>; + drive-strength = <19>; + }; + }; + + /omit-if-no-ref/ + uart8_2_cts_rts_cfg: uart8-2-cts-rts-cfg { + uart8-2-pins { + pinmux = , /* uart8_cts */ + ; /* uart8_rts */ + power-source = <3300>; + bias-pull-up = <0>; + drive-strength = <19>; + }; + }; + + /omit-if-no-ref/ + uart9_0_cfg: uart9-0-cfg { + uart9-0-pins { + pinmux = , /* uart9_txd */ + ; /* uart9_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart9_1_cfg: uart9-1-cfg { + uart9-1-pins { + pinmux = , /* uart9_txd */ + ; /* uart9_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart9_1_cts_rts_cfg: uart9-1-cts-rts-cfg { + uart9-1-pins { + pinmux = , /* uart9_cts */ + ; /* uart9_rts */ + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + + /omit-if-no-ref/ + uart9_2_cfg: uart9-2-cfg { + uart9-2-pins { + pinmux = , /* uart9_txd */ + ; /* uart9_rxd */ bias-pull-up = <0>; drive-strength = <32>; }; diff --git a/dts/upstream/src/riscv/spacemit/k1.dtsi b/dts/upstream/src/riscv/spacemit/k1.dtsi index 6cdcd80a7c8..7818ca4979b 100644 --- a/dts/upstream/src/riscv/spacemit/k1.dtsi +++ b/dts/upstream/src/riscv/spacemit/k1.dtsi @@ -358,6 +358,71 @@ #reset-cells = <1>; }; + i2c0: i2c@d4010800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4010800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI0>, + <&syscon_apbc CLK_TWSI0_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <36>; + status = "disabled"; + }; + + i2c1: i2c@d4011000 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4011000 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI1>, + <&syscon_apbc CLK_TWSI1_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <37>; + status = "disabled"; + }; + + i2c2: i2c@d4012000 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4012000 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI2>, + <&syscon_apbc CLK_TWSI2_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <38>; + status = "disabled"; + }; + + i2c4: i2c@d4012800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4012800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI4>, + <&syscon_apbc CLK_TWSI4_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <40>; + status = "disabled"; + }; + + i2c5: i2c@d4013800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4013800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI5>, + <&syscon_apbc CLK_TWSI5_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <41>; + status = "disabled"; + }; + syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; @@ -369,6 +434,19 @@ #reset-cells = <1>; }; + i2c6: i2c@d4018800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4018800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI6>, + <&syscon_apbc CLK_TWSI6_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <70>; + status = "disabled"; + }; + gpio: gpio@d4019000 { compatible = "spacemit,k1-gpio"; reg = <0x0 0xd4019000 0x0 0x100>; @@ -459,6 +537,32 @@ status = "disabled"; }; + i2c7: i2c@d401d000 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd401d000 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI7>, + <&syscon_apbc CLK_TWSI7_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <18>; + status = "disabled"; + }; + + i2c8: i2c@d401d800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd401d800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_TWSI8>, + <&syscon_apbc CLK_TWSI8_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + interrupts = <19>; + status = "disabled"; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; reg = <0x0 0xd401e000 0x0 0x400>; @@ -643,6 +747,8 @@ #reset-cells = <1>; }; + /* sec_i2c3: 0xf0614000, not available from Linux */ + camera-bus { compatible = "simple-bus"; ranges; @@ -797,6 +903,22 @@ status = "disabled"; }; + qspi: spi@d420c000 { + compatible = "spacemit,k1-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xd420c000 0x0 0x1000>, + <0x0 0xb8000000 0x0 0xc00000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + clocks = <&syscon_apmu CLK_QSPI_BUS>, + <&syscon_apmu CLK_QSPI>; + clock-names = "qspi_en", "qspi"; + resets = <&syscon_apmu RESET_QSPI>, + <&syscon_apmu RESET_QSPI_BUS>; + interrupts = <117>; + status = "disabled"; + }; + /* sec_uart1: 0xf0612000, not available from Linux */ }; diff --git a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi b/dts/upstream/src/riscv/starfive/jh7110-common.dtsi index 5dc15e48b74..8cfe8033305 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi +++ b/dts/upstream/src/riscv/starfive/jh7110-common.dtsi @@ -281,14 +281,8 @@ assigned-clock-rates = <50000000>; bus-width = <8>; bootph-pre-ram; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - cap-mmc-hw-reset; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&emmc_vdd>; status = "okay"; }; @@ -298,8 +292,6 @@ assigned-clock-rates = <50000000>; bus-width = <4>; bootph-pre-ram; - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; - disable-wp; cap-sd-highspeed; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; @@ -444,17 +436,6 @@ }; mmc0_pins: mmc0-0 { - rst-pins { - pinmux = ; - bias-pull-up; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - mmc-pins { pinmux = , , diff --git a/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts index f2857d021d6..d8db9ed4474 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts +++ b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts @@ -11,6 +11,33 @@ compatible = "deepcomputing,fml13v01", "starfive,jh7110"; }; +&mmc0 { + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; +}; + +&mmc0_pins { + rst-pins { + pinmux = ; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; +}; + +&mmc1 { + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; + disable-wp; +}; + &pcie1 { perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>; phys = <&pciephy1>; diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts index fdaf6b4557d..21873612d99 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts +++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts @@ -22,6 +22,33 @@ status = "okay"; }; +&mmc0 { + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; +}; + +&mmc0_pins { + rst-pins { + pinmux = ; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; +}; + +&mmc1 { + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; + disable-wp; +}; + &pcie0 { status = "okay"; }; diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-emmc.dts b/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-emmc.dts index e568537af2c..ce95496263a 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-emmc.dts +++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-emmc.dts @@ -10,3 +10,12 @@ model = "Milk-V Mars CM"; compatible = "milkv,marscm-emmc", "starfive,jh7110"; }; + +&mmc0 { + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; +}; diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-lite.dts b/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-lite.dts index 6c40d0ec401..63aa94d65ab 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-lite.dts +++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm-lite.dts @@ -14,6 +14,7 @@ &mmc0 { bus-width = <4>; cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; + disable-wp; }; &mmc0_pins { diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm.dtsi b/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm.dtsi index 25b70af564e..025471061d4 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm.dtsi +++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-marscm.dtsi @@ -40,6 +40,19 @@ status = "disabled"; }; +&mmc0_pins { + rst-pins { + pinmux = ; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; +}; + &mmc1 { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/upstream/src/riscv/starfive/jh7110-orangepi-rv.dts b/dts/upstream/src/riscv/starfive/jh7110-orangepi-rv.dts new file mode 100644 index 00000000000..053c35992ec --- /dev/null +++ b/dts/upstream/src/riscv/starfive/jh7110-orangepi-rv.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Icenowy Zheng + */ + +/dts-v1/; +#include "jh7110-common.dtsi" + +/ { + model = "Xunlong Orange Pi RV"; + compatible = "xunlong,orangepi-rv", "starfive,jh7110"; + + /* This regulator is always on by hardware */ + reg_vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3-pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&sysgpio 62 GPIO_ACTIVE_LOW>; + }; +}; + +&gmac0 { + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; + starfive,tx-use-rgmii-clk; + status = "okay"; +}; + +&mmc0 { + #address-cells = <1>; + #size-cells = <0>; + cap-sd-highspeed; + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <®_vcc3v3_pcie>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; + + ap6256: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + /* TODO: out-of-band IRQ on GPIO21, lacking pinctrl support */ + }; +}; + +&mmc1 { + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&phy0 { + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-10-inverted; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; +}; + +&pwmdac { + status = "okay"; +}; diff --git a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts index 31e825be206..aec7ae3d1f5 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts +++ b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts @@ -44,6 +44,33 @@ status = "okay"; }; +&mmc0 { + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; +}; + +&mmc0_pins { + rst-pins { + pinmux = ; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; +}; + +&mmc1 { + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; + disable-wp; +}; + &pcie1 { status = "okay"; }; diff --git a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts new file mode 100644 index 00000000000..e27a662d402 --- /dev/null +++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 StarFive Technology Co., Ltd. + * Copyright (C) 2025 Hal Feng + */ + +/dts-v1/; +#include "jh7110-starfive-visionfive-2-lite.dtsi" + +/ { + model = "StarFive VisionFive 2 Lite eMMC"; + compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s"; +}; + +&mmc0 { + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; +}; diff --git a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite.dts b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite.dts new file mode 100644 index 00000000000..b96eea4fa7d --- /dev/null +++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 StarFive Technology Co., Ltd. + * Copyright (C) 2025 Hal Feng + */ + +/dts-v1/; +#include "jh7110-starfive-visionfive-2-lite.dtsi" + +/ { + model = "StarFive VisionFive 2 Lite"; + compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>; + disable-wp; + cap-sd-highspeed; +}; diff --git a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite.dtsi b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite.dtsi new file mode 100644 index 00000000000..f8797a666db --- /dev/null +++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-lite.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 StarFive Technology Co., Ltd. + * Copyright (C) 2025 Hal Feng + */ + +/dts-v1/; +#include "jh7110-common.dtsi" + +/ { + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc_3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cpu_opp { + /delete-node/ opp-375000000; + /delete-node/ opp-500000000; + /delete-node/ opp-750000000; + /delete-node/ opp-1500000000; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + opp-microvolt = <800000>; + }; + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + opp-microvolt = <800000>; + }; + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-microvolt = <800000>; + }; + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-microvolt = <1000000>; + }; +}; + +&gmac0 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&mmc1 { + max-frequency = <50000000>; + keep-power-in-suspend; + non-removable; +}; + +&pcie1 { + vpcie3v3-supply = <&vcc_3v3_pcie>; + status = "okay"; +}; + +&phy0 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; +}; + +&pwm { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&syscrg { + assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>; +}; + +&sysgpio { + uart1_pins: uart1-0 { + tx-pins { + pinmux = ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + + cts-pins { + pinmux = ; + input-enable; + }; + + rts-pins { + pinmux = ; + input-enable; + }; + }; + + usb0_pins: usb0-0 { + power-pins { + pinmux = ; + input-disable; + }; + + switch-pins { + pinmux = ; + input-disable; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + status = "okay"; +}; + +&usb_cdns3 { + phys = <&usbphy0>, <&pciephy0>; + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; +}; diff --git a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi index 5f14afb2c24..edc8f458813 100644 --- a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi @@ -38,9 +38,33 @@ }; &mmc0 { + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; non-removable; }; +&mmc0_pins { + rst-pins { + pinmux = ; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; +}; + +&mmc1 { + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; + disable-wp; +}; + &pcie0 { status = "okay"; }; diff --git a/dts/upstream/src/riscv/tenstorrent/blackhole-card.dts b/dts/upstream/src/riscv/tenstorrent/blackhole-card.dts new file mode 100644 index 00000000000..f53667ce73a --- /dev/null +++ b/dts/upstream/src/riscv/tenstorrent/blackhole-card.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include "blackhole.dtsi" + +/ { + model = "Tenstorrent Blackhole"; + compatible = "tenstorrent,blackhole-card", "tenstorrent,blackhole"; + + memory@400030000000 { + device_type = "memory"; + reg = <0x4000 0x30000000 0x1 0x00000000>; + }; +}; diff --git a/dts/upstream/src/riscv/tenstorrent/blackhole.dtsi b/dts/upstream/src/riscv/tenstorrent/blackhole.dtsi new file mode 100644 index 00000000000..6408810d8d8 --- /dev/null +++ b/dts/upstream/src/riscv/tenstorrent/blackhole.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright 2025 Tenstorrent AI ULC +/dts-v1/; + +/ { + compatible = "tenstorrent,blackhole"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <50000000>; + + cpu@0 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <0>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@1 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <1>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@2 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <2>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu@3 { + compatible = "sifive,x280", "sifive,rocket0", "riscv"; + device_type = "cpu"; + reg = <3>; + mmu-type = "riscv,sv57"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + clint0: timer@2000000 { + compatible = "tenstorrent,blackhole-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>, + <&cpu1_intc 0x3>, <&cpu1_intc 0x7>, + <&cpu2_intc 0x3>, <&cpu2_intc 0x7>, + <&cpu3_intc 0x3>, <&cpu3_intc 0x7>; + }; + + plic0: interrupt-controller@c000000 { + compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x0c000000 0x0 0x04000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <128>; + }; + }; +}; diff --git a/dts/upstream/src/riscv/thead/th1520-lichee-pi-4a.dts b/dts/upstream/src/riscv/thead/th1520-lichee-pi-4a.dts index 4020c727f09..c58c2085ca9 100644 --- a/dts/upstream/src/riscv/thead/th1520-lichee-pi-4a.dts +++ b/dts/upstream/src/riscv/thead/th1520-lichee-pi-4a.dts @@ -28,9 +28,76 @@ chosen { stdout-path = "serial0:115200n8"; }; + + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <1000>; + thermal-sensors = <&pvt 0>; + + trips { + fan_config0: fan-trip0 { + temperature = <39000>; + hysteresis = <5000>; + type = "active"; + }; + + fan_config1: fan-trip1 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + + fan_config2: fan-trip2 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + }; + + cooling-maps { + map-active-0 { + cooling-device = <&fan 1 1>; + trip = <&fan_config0>; + }; + + map-active-1 { + cooling-device = <&fan 2 2>; + trip = <&fan_config1>; + }; + + map-active-2 { + cooling-device = <&fan 3 3>; + trip = <&fan_config2>; + }; + }; + }; + }; + + fan: pwm-fan { + pinctrl-names = "default"; + pinctrl-0 = <&fan_pins>; + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm 1 10000000 0>; + cooling-levels = <0 66 196 255>; + }; + }; &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { + pins = "GPIO3_3"; /* PWM1 */ + function = "pwm"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins = "UART0_TXD"; diff --git a/dts/upstream/src/riscv/thead/th1520.dtsi b/dts/upstream/src/riscv/thead/th1520.dtsi index e680d1a7c82..bd5d3384088 100644 --- a/dts/upstream/src/riscv/thead/th1520.dtsi +++ b/dts/upstream/src/riscv/thead/th1520.dtsi @@ -24,8 +24,11 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -48,8 +51,11 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -72,8 +78,11 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -96,8 +105,11 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -277,6 +289,12 @@ <&cpu3_intc 3>, <&cpu3_intc 7>; }; + rst_vi: reset-controller@ffe4040100 { + compatible = "thead,th1520-reset-vi"; + reg = <0xff 0xe4040100 0x0 0x8>; + #reset-cells = <1>; + }; + spi0: spi@ffe700c000 { compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; reg = <0xff 0xe700c000 0x0 0x1000>; @@ -502,6 +520,25 @@ status = "disabled"; }; + pwm: pwm@ffec01c000 { + compatible = "thead,th1520-pwm"; + reg = <0xff 0xec01c000 0x0 0x4000>; + clocks = <&clk CLK_PWM>; + #pwm-cells = <3>; + }; + + rst_misc: reset-controller@ffec02c000 { + compatible = "thead,th1520-reset-misc"; + reg = <0xff 0xec02c000 0x0 0x18>; + #reset-cells = <1>; + }; + + rst_vp: reset-controller@ffecc30000 { + compatible = "thead,th1520-reset-vp"; + reg = <0xff 0xecc30000 0x0 0x14>; + #reset-cells = <1>; + }; + clk: clock-controller@ffef010000 { compatible = "thead,th1520-clk-ap"; reg = <0xff 0xef010000 0x0 0x1000>; @@ -509,6 +546,18 @@ #clock-cells = <1>; }; + rst_ap: reset-controller@ffef014000 { + compatible = "thead,th1520-reset-ap"; + reg = <0xff 0xef014000 0x0 0x1000>; + #reset-cells = <1>; + }; + + rst_dsp: reset-controller@ffef040028 { + compatible = "thead,th1520-reset-dsp"; + reg = <0xff 0xef040028 0x0 0x4>; + #reset-cells = <1>; + }; + gpu: gpu@ffef400000 { compatible = "thead,th1520-gpu", "img,img-bxm-4-64", "img,img-rogue"; @@ -681,6 +730,13 @@ }; }; + rst_ao: reset-controller@fffff44000 { + compatible = "thead,th1520-reset-ao"; + reg = <0xff 0xfff44000 0x0 0x2000>; + #reset-cells = <1>; + status = "reserved"; + }; + padctrl_aosys: pinctrl@fffff4a000 { compatible = "thead,th1520-pinctrl"; reg = <0xff 0xfff4a000 0x0 0x2000>; diff --git a/env/Kconfig b/env/Kconfig index b312f9b5324..5979f7faa99 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -259,6 +259,7 @@ config ENV_IS_IN_MMC config ENV_IS_IN_NAND bool "Environment in a NAND device" depends on !CHAIN_OF_TRUST + depends on MTD_RAW_NAND help Define this if you have a NAND device which you want to use for the environment. @@ -975,7 +976,7 @@ config USE_BOOTFILE config BOOTFILE string "'bootfile' environment variable value" - default kernel.itb if SPL_ATF && TARGET_SOCFPGA_SOC64 + default kernel.itb if SPL_ATF && ARCH_SOCFPGA_SOC64 depends on USE_BOOTFILE help The value to set the "bootfile" variable to. diff --git a/env/flash.c b/env/flash.c index 0f7393d830c..31dd1656e72 100644 --- a/env/flash.c +++ b/env/flash.c @@ -108,6 +108,14 @@ static int env_flash_init(void) } else if (flag2 == 0xFF) { gd->env_addr = addr2; gd->env_valid = ENV_REDUND; + } else { + /* + * Unrecognized flag pair (e.g. bit-flip on NOR flash). + * Default to primary copy to prevent unintended pointer + * swap in env_flash_load(). + */ + gd->env_addr = addr1; + gd->env_valid = ENV_REDUND; } return 0; diff --git a/env/sf.c b/env/sf.c index 0e27a020643..14c35324e64 100644 --- a/env/sf.c +++ b/env/sf.c @@ -396,7 +396,8 @@ static int env_sf_init_early(void) if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) { read2_fail = spi_flash_read(env_flash, - CONFIG_ENV_OFFSET_REDUND, + IF_ENABLED_INT(CONFIG_ENV_REDUNDANT, + CONFIG_ENV_OFFSET_REDUND), CONFIG_ENV_SIZE, tmp_env2); ret = env_check_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2, read2_fail); diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig index 19d52238713..9606fa48bbe 100644 --- a/fs/fat/Kconfig +++ b/fs/fat/Kconfig @@ -29,3 +29,11 @@ config FS_FAT_MAX_CLUSTSIZE is the smallest amount of disk space that can be used to hold a file. Unless you have an extremely tight memory memory constraints, leave the default. + +config FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH + bool "Handle FAT sector size mismatch" + default n + depends on FS_FAT + help + Handle filesystems on media where the hardware block size and + the sector size in the FAT metadata do not match. diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 9ce5df59f9b..31c136e3b9e 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -45,11 +45,146 @@ static void downcase(char *str, size_t len) static struct blk_desc *cur_dev; static struct disk_partition cur_part_info; +static int fat_sect_size; #define DOS_BOOT_MAGIC_OFFSET 0x1fe #define DOS_FS_TYPE_OFFSET 0x36 #define DOS_FS32_TYPE_OFFSET 0x52 +#if IS_ENABLED(CONFIG_FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH) +static inline __u32 sect_to_block(__u32 sect, __u32 *off) +{ + const ulong blksz = cur_part_info.blksz; + + *off = 0; + if (fat_sect_size && fat_sect_size < blksz) { + int div = blksz / fat_sect_size; + + *off = sect % div; + return sect / div; + } else if (fat_sect_size && (fat_sect_size > blksz)) { + return sect * (fat_sect_size / blksz); + } + + return sect; +} + +static int disk_rw(__u32 sect, __u32 nr_sect, void *buf, bool read) +{ + int ret; + __u8 *block = NULL; + __u32 rem, size, s, n; + const ulong blksz = cur_part_info.blksz; + const lbaint_t start = cur_part_info.start; + + rem = nr_sect * fat_sect_size; + /* + * block N block N + 1 block N + 2 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | |s|e|c|t|o|r| | |s|e|c|t|o|r| | |s|e|c|t|o|r| | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * . . . | | | | . . . + * ------+---------------+---------------+---------------+------ + * |<--- FAT reads in sectors --->| + * + * | part 1 | part 2 | part 3 | + * + */ + + /* Do part 1 */ + if (fat_sect_size) { + __u32 offset; + + /* Read one block and overwrite the leading sectors */ + block = malloc_cache_aligned(cur_dev->blksz); + if (!block) { + printf("Error: allocating block: %lu\n", cur_dev->blksz); + return -1; + } + + s = sect_to_block(sect, &offset); + offset = offset * fat_sect_size; + + ret = blk_dread(cur_dev, start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + + if (rem > (blksz - offset)) + size = blksz - offset; + else + size = rem; + + if (read) { + memcpy(buf, block + offset, size); + } else { + memcpy(block + offset, buf, size); + ret = blk_dwrite(cur_dev, start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + } + + rem -= size; + buf += size; + s++; + } + + /* Do part 2, read/write directly to/from the given buffer */ + if (rem > blksz) { + n = rem / blksz; + + if (read) + ret = blk_dread(cur_dev, start + s, n, buf); + else + ret = blk_dwrite(cur_dev, start + s, n, buf); + + if (ret != n) { + ret = -1; + goto exit; + } + buf += n * blksz; + rem = rem % blksz; + s += n; + } + + /* Do part 3, read a block and copy the trailing sectors */ + if (rem) { + ret = blk_dread(cur_dev, start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + if (read) { + memcpy(buf, block, rem); + } else { + memcpy(block, buf, rem); + ret = blk_dwrite(cur_dev, start + s, 1, block); + if (ret != 1) { + ret = -1; + goto exit; + } + } + } +exit: + if (block) + free(block); + + return (ret == -1) ? -1 : nr_sect; +} + +static int disk_read(__u32 sect, __u32 nr_sect, void *buf) +{ + return disk_rw(sect, nr_sect, buf, true); +} + +int disk_write(__u32 sect, __u32 nr_sect, void *buf) +{ + return disk_rw(sect, nr_sect, buf, false); +} +#else static int disk_read(__u32 block, __u32 nr_blocks, void *buf) { ulong ret; @@ -64,6 +199,7 @@ static int disk_read(__u32 block, __u32 nr_blocks, void *buf) return ret; } +#endif /* CONFIG_FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH */ int fat_set_blk_dev(struct blk_desc *dev_desc, struct disk_partition *info) { @@ -73,7 +209,7 @@ int fat_set_blk_dev(struct blk_desc *dev_desc, struct disk_partition *info) cur_part_info = *info; /* Make sure it has a valid FAT header */ - if (disk_read(0, 1, buffer) != 1) { + if (blk_dread(cur_dev, cur_part_info.start, 1, buffer) != 1) { cur_dev = NULL; return -1; } @@ -581,7 +717,8 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } - if (disk_read(0, 1, block) < 0) { + fat_sect_size = 0; + if (blk_dread(cur_dev, cur_part_info.start, 1, block) != 1) { debug("Error: reading block\n"); ret = -1; goto out_free; @@ -651,11 +788,16 @@ static int get_fs_info(fsdata *mydata) mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats; mydata->sect_size = get_unaligned_le16(bs.sector_size); + fat_sect_size = mydata->sect_size; mydata->clust_size = bs.cluster_size; if (mydata->sect_size != cur_part_info.blksz) { - log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", - mydata->sect_size, cur_part_info.blksz); - return -1; + if (!IS_ENABLED(CONFIG_FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH)) { + log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n", + mydata->sect_size, cur_part_info.blksz); + return -1; + } + log_info("FAT sector size mismatch (fs=%u, dev=%lu)\n", + mydata->sect_size, cur_part_info.blksz); } if (mydata->clust_size == 0) { log_err("FAT cluster size not set\n"); @@ -690,7 +832,7 @@ static int get_fs_info(fsdata *mydata) } mydata->fatbufnum = -1; - mydata->fat_dirty = 0; + fat_mark_clean(mydata); mydata->fatbuf = malloc_cache_aligned(FATBUFSIZE); if (mydata->fatbuf == NULL) { debug("Error: allocating memory\n"); diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 0b924541187..c98b530f747 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -192,6 +192,7 @@ out: } static int total_sector; +#if !IS_ENABLED(CONFIG_FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH) static int disk_write(__u32 block, __u32 nr_blocks, void *buf) { ulong ret; @@ -211,6 +212,7 @@ static int disk_write(__u32 block, __u32 nr_blocks, void *buf) return ret; } +#endif /* CONFIG_FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH */ /* * Write fat buffer into block device @@ -223,9 +225,9 @@ static int flush_dirty_fat_buffer(fsdata *mydata) __u32 startblock = mydata->fatbufnum * FATBUFBLOCKS; debug("debug: evicting %d, dirty: %d\n", mydata->fatbufnum, - (int)mydata->fat_dirty); + (int)fat_is_dirty(mydata)); - if ((!mydata->fat_dirty) || (mydata->fatbufnum == -1)) + if (!fat_is_dirty(mydata) || (mydata->fatbufnum == -1)) return 0; /* Cap length if fatlength is not a multiple of FATBUFBLOCKS */ @@ -248,7 +250,7 @@ static int flush_dirty_fat_buffer(fsdata *mydata) return -1; } } - mydata->fat_dirty = 0; + fat_mark_clean(mydata); return 0; } @@ -484,8 +486,7 @@ static int set_fatent_value(fsdata *mydata, __u32 entry, __u32 entry_value) mydata->fatbufnum = bufnum; } - /* Mark as dirty */ - mydata->fat_dirty = 1; + fat_mark_dirty(mydata); /* Set the actual entry */ switch (mydata->fatsize) { diff --git a/fs/fs.c b/fs/fs.c index 319c55c440a..8ea50a6c13c 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -34,8 +33,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct blk_desc *fs_dev_desc; static int fs_dev_part; static struct disk_partition fs_partition; diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 9cb8b4afcdd..543db8c7e9e 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -1490,13 +1490,11 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, goto out; } - /* If the user specifies a length, check its sanity */ - if (len) { - if (len > finfo.size) { - ret = -EINVAL; - goto out; - } - + /* + * For FIT loading, the len is ALIGN, so it may exceed the actual size. + * Let's just read the max. + */ + if (len && len < finfo.size) { finfo.size = len; } else { len = finfo.size; diff --git a/fs/squashfs/sqfs_decompressor.c b/fs/squashfs/sqfs_decompressor.c index cfd1153fd74..a156cfe6f65 100644 --- a/fs/squashfs/sqfs_decompressor.c +++ b/fs/squashfs/sqfs_decompressor.c @@ -10,19 +10,19 @@ #include #include -#if IS_ENABLED(CONFIG_LZO) +#if CONFIG_IS_ENABLED(LZO) #include #endif -#if IS_ENABLED(CONFIG_ZLIB) +#if CONFIG_IS_ENABLED(ZLIB) #include #endif -#if IS_ENABLED(CONFIG_LZ4) +#if CONFIG_IS_ENABLED(LZ4) #include #endif -#if IS_ENABLED(CONFIG_ZSTD) +#if CONFIG_IS_ENABLED(ZSTD) #include #endif @@ -33,60 +33,35 @@ int sqfs_decompressor_init(struct squashfs_ctxt *ctxt) { u16 comp_type = get_unaligned_le16(&ctxt->sblk->compression); - switch (comp_type) { -#if IS_ENABLED(CONFIG_LZO) - case SQFS_COMP_LZO: - break; -#endif -#if IS_ENABLED(CONFIG_ZLIB) - case SQFS_COMP_ZLIB: - break; -#endif -#if IS_ENABLED(CONFIG_LZ4) - case SQFS_COMP_LZ4: - break; -#endif -#if IS_ENABLED(CONFIG_ZSTD) - case SQFS_COMP_ZSTD: + if (((CONFIG_IS_ENABLED(LZO) && comp_type == SQFS_COMP_LZO)) || + ((CONFIG_IS_ENABLED(ZLIB) && comp_type == SQFS_COMP_ZLIB)) || + ((CONFIG_IS_ENABLED(LZ4) && comp_type == SQFS_COMP_LZ4))) + return 0; + +#if CONFIG_IS_ENABLED(ZSTD) + if (comp_type == SQFS_COMP_ZSTD) { ctxt->zstd_workspace = malloc(zstd_dctx_workspace_bound()); if (!ctxt->zstd_workspace) return -ENOMEM; - break; -#endif - default: - printf("Error: unknown compression type.\n"); - return -EINVAL; + return 0; } +#endif - return 0; + printf("Error: unknown compression type.\n"); + return -EINVAL; } void sqfs_decompressor_cleanup(struct squashfs_ctxt *ctxt) { +#if CONFIG_IS_ENABLED(ZSTD) u16 comp_type = get_unaligned_le16(&ctxt->sblk->compression); - switch (comp_type) { -#if IS_ENABLED(CONFIG_LZO) - case SQFS_COMP_LZO: - break; -#endif -#if IS_ENABLED(CONFIG_ZLIB) - case SQFS_COMP_ZLIB: - break; -#endif -#if IS_ENABLED(CONFIG_LZ4) - case SQFS_COMP_LZ4: - break; -#endif -#if IS_ENABLED(CONFIG_ZSTD) - case SQFS_COMP_ZSTD: + if (comp_type == SQFS_COMP_ZSTD) free(ctxt->zstd_workspace); - break; #endif - } } -#if IS_ENABLED(CONFIG_ZLIB) +#if CONFIG_IS_ENABLED(ZLIB) static void zlib_decompression_status(int ret) { switch (ret) { @@ -103,7 +78,7 @@ static void zlib_decompression_status(int ret) } #endif -#if IS_ENABLED(CONFIG_ZSTD) +#if CONFIG_IS_ENABLED(ZSTD) static int sqfs_zstd_decompress(struct squashfs_ctxt *ctxt, void *dest, unsigned long dest_len, void *source, u32 src_len) { @@ -129,7 +104,7 @@ int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest, int ret = 0; switch (comp_type) { -#if IS_ENABLED(CONFIG_LZO) +#if CONFIG_IS_ENABLED(LZO) case SQFS_COMP_LZO: { size_t lzo_dest_len = *dest_len; ret = lzo1x_decompress_safe(source, src_len, dest, &lzo_dest_len); @@ -141,7 +116,7 @@ int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest, break; } #endif -#if IS_ENABLED(CONFIG_ZLIB) +#if CONFIG_IS_ENABLED(ZLIB) case SQFS_COMP_ZLIB: ret = uncompress(dest, dest_len, source, src_len); if (ret) { @@ -151,7 +126,7 @@ int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest, break; #endif -#if IS_ENABLED(CONFIG_LZ4) +#if CONFIG_IS_ENABLED(LZ4) case SQFS_COMP_LZ4: ret = LZ4_decompress_safe(source, dest, src_len, *dest_len); if (ret < 0) { @@ -162,7 +137,7 @@ int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest, ret = 0; break; #endif -#if IS_ENABLED(CONFIG_ZSTD) +#if CONFIG_IS_ENABLED(ZSTD) case SQFS_COMP_ZSTD: ret = sqfs_zstd_decompress(ctxt, dest, *dest_len, source, src_len); if (ret) { diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 40bad0e7da7..b0cc0d2e1b2 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "ubifs.h" #include #include @@ -31,8 +30,6 @@ #include #endif -DECLARE_GLOBAL_DATA_PTR; - /* compress.c */ /* diff --git a/include/bootcount.h b/include/bootcount.h index 847c0f02d98..86474569d36 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -10,6 +10,7 @@ #include #include #include +#include #ifdef CONFIG_DM_BOOTCOUNT @@ -59,6 +60,10 @@ int dm_bootcount_set(struct udevice *dev, u32 bootcount); #endif +/* Bit masks for magic and count parts in single word scheme */ +#define BOOTCOUNT_MAGIC_MASK GENMASK(31, 16) +#define BOOTCOUNT_COUNT_MASK GENMASK(15, 0) + /** bootcount_store() - store the current bootcount */ void bootcount_store(ulong); diff --git a/include/bootm.h b/include/bootm.h index 4060cec7fc0..f6958be751a 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -321,4 +321,14 @@ void zimage_dump(struct boot_params *base_ptr, bool show_cmdline); */ int bootm_boot_start(ulong addr, const char *cmdline); +/** + * bootm_final() - Announce and do cleanup before boot + * + * This performs the common pre-boot steps: printing the "Starting kernel" + * message, recording bootstage data, and removing active devices. + * + * @flag: Boot state flags (BOOTM_STATE_OS_FAKE_GO prints a fake-run message) + */ +void bootm_final(int flag); + #endif diff --git a/include/bootstage.h b/include/bootstage.h index 528d0ca0614..62fb99110f0 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -435,6 +435,14 @@ static inline uint32_t bootstage_accum(enum bootstage_id id) return 0; } +static inline void bootstage_report(void) +{ +} + +static inline void bootstage_fdt_add_report(void) +{ +} + static inline int bootstage_stash(void *base, int size) { return 0; /* Pretend to succeed */ diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 404af2cd4c6..38d0bfc315b 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -108,7 +108,8 @@ #define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0) #define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0" + "bootcmd_" #devtypel "=devnum=" #instance "; " \ + #devtypel " init $devnum; run scsi_boot\0" #define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \ "ufs " diff --git a/include/configs/beaglev_fire.h b/include/configs/beaglev_fire.h new file mode 100644 index 00000000000..e3ee0f02f2d --- /dev/null +++ b/include/configs/beaglev_fire.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Microchip Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +/* Environment options */ + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func)\ + BOOT_TARGET_DEVICES_DHCP(func) + +#define BOOTENV_DESIGN_OVERLAYS \ + "design_overlays=" \ + "if test -n ${no_of_overlays}; then " \ + "setenv inc 1; " \ + "setenv idx 0; " \ + "fdt resize ${dtbo_size}; " \ + "while test $idx -ne ${no_of_overlays}; do " \ + "setenv dtbo_name dtbo_image${idx}; " \ + "setenv fdt_cmd \"fdt apply $\"$dtbo_name; " \ + "run fdt_cmd; " \ + "setexpr idx $inc + $idx; " \ + "done; " \ + "fi;\0 " \ + +#include + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x80200000\0" \ + "fdt_addr_r=0x8a000000\0" \ + "fdtoverlay_addr_r=0x8a080000\0" \ + "ramdisk_addr_r=0x8aa00000\0" \ + "scriptaddr=0x8e000000\0" \ + BOOTENV_DESIGN_OVERLAYS \ + BOOTENV \ + +#endif /* __CONFIG_H */ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 7120a44d186..ee13d2ab950 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -38,6 +38,19 @@ #define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV +#ifdef CONFIG_ENV_WRITEABLE_LIST +#define CFG_ENV_FLAGS_LIST_STATIC \ + "bootcount:dw," \ + "bootdelay:sw," \ + "bootlimit:dw," \ + "partitionset_active:sw," \ + "rastate:dw," \ + "sig_a:sw,sig_b:sw," \ + "target_env:sw," \ + "upgrade_available:dw," \ + "ustate:dw" +#endif + /* Default location for tftp and bootm */ /* On CCP board, USDHC1 is for eMMC */ diff --git a/include/configs/imx952_evk.h b/include/configs/imx952_evk.h new file mode 100644 index 00000000000..4ff56eb8adf --- /dev/null +++ b/include/configs/imx952_evk.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025-2026 NXP + */ + +#ifndef __IMX952_EVK_H +#define __IMX952_EVK_H + +#include +#include +#include + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 + +#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */ +#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB */ + +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000 + +#endif diff --git a/include/configs/phycore_imx93.h b/include/configs/phycore_imx91_93.h similarity index 88% rename from include/configs/phycore_imx93.h rename to include/configs/phycore_imx91_93.h index 07364dff403..02fa1d9b274 100644 --- a/include/configs/phycore_imx93.h +++ b/include/configs/phycore_imx91_93.h @@ -6,8 +6,8 @@ * Copyright (C) 2024 Mathieu Othacehe */ -#ifndef __PHYCORE_IMX93_H -#define __PHYCORE_IMX93_H +#ifndef __PHYCORE_IMX91_93_H +#define __PHYCORE_IMX91_93_H #include #include @@ -25,4 +25,4 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR -#endif /* __PHYCORE_IMX93_H */ +#endif /* __PHYCORE_IMX91_93_H */ diff --git a/include/configs/rk3506_common.h b/include/configs/rk3506_common.h new file mode 100644 index 00000000000..5e4ef67289f --- /dev/null +++ b/include/configs/rk3506_common.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __CONFIG_RK3506_COMMON_H +#define __CONFIG_RK3506_COMMON_H + +#define CFG_CPUID_OFFSET 0xa + +#include "rockchip-common.h" + +#define CFG_IRAM_BASE 0xfff80000 + +#define CFG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xc0000000 + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "kernel_addr_r=0x02080000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_size=0x2000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __CONFIG_RK3506_COMMON_H */ diff --git a/include/configs/socfpga_ac501soc.h b/include/configs/socfpga_ac501soc.h new file mode 100644 index 00000000000..703520e7cb8 --- /dev/null +++ b/include/configs/socfpga_ac501soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune + */ +#ifndef __CONFIG_CORESOURCE_AC501SOC_H__ +#define __CONFIG_CORESOURCE_AC501SOC_H__ + +#include + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_CORESOURCE_AC501SOC_H__ */ diff --git a/include/configs/socfpga_ac550soc.h b/include/configs/socfpga_ac550soc.h new file mode 100644 index 00000000000..48e02d61dc5 --- /dev/null +++ b/include/configs/socfpga_ac550soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune + */ +#ifndef __CONFIG_CORESOURCE_AC550SOC_H__ +#define __CONFIG_CORESOURCE_AC550SOC_H__ + +#include + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_CORESOURCE_AC550SOC_H__ */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2acfdc7df4a..36d6bfb3d03 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -11,10 +11,10 @@ * Memory configurations */ #define PHYS_SDRAM_1 0x0 -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 3d09a06f63e..4d333c63ad9 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -41,7 +41,7 @@ /* * U-Boot run time memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_SYS_INIT_RAM_ADDR 0x0 #define CFG_SYS_INIT_RAM_SIZE 0x80000 #else @@ -118,7 +118,7 @@ #include -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x82000000\0" \ @@ -182,7 +182,7 @@ "smc_fid_wr=0xC2000008\0" \ "smc_fid_upd=0xC2000009\0 " \ BOOTENV -#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ +#endif /*#IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)*/ #else @@ -245,7 +245,7 @@ /* * External memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE 0x80000000 @@ -270,7 +270,7 @@ /* * L4 Watchdog */ -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CFG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 5e89cd6937a..00610e76869 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -7,256 +7,22 @@ * Configuration settings for the TQ-Systems TQMa6 module. */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* place code in last 4 MiB of RAM */ +#ifndef __TQMA6_CONFIG_H +#define __TQMA6_CONFIG_H #include "mx6_common.h" -#if defined(CONFIG_TQMA6S) -#define PHYS_SDRAM_SIZE (512u * SZ_1M) -#elif defined(CONFIG_TQMA6DL) -#define PHYS_SDRAM_SIZE (SZ_1G) -#elif defined(CONFIG_TQMA6Q) -#define PHYS_SDRAM_SIZE (SZ_1G) -#endif - -/* SPI Flash */ - -#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K - -#if !defined(CONFIG_DM_PMIC) -#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 -#define TQMA6_PFUZE100_I2C_BUS 2 -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#if defined(CONFIG_TQMA6X_MMC_BOOT) - -#define TQMA6_UBOOT_OFFSET SZ_1K -#define TQMA6_UBOOT_SECTOR_START 0x2 -#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe - -#define TQMA6_FDT_OFFSET (2 * SZ_1M) -#define TQMA6_FDT_SECTOR_START 0x1000 -#define TQMA6_FDT_SECTOR_COUNT 0x800 - -#define TQMA6_KERNEL_SECTOR_START 0x2000 -#define TQMA6_KERNEL_SECTOR_COUNT 0x2000 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "loadimage=mmc dev ${mmcdev}; " \ - "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ - "loadfdt=mmc dev ${mmcdev}; " \ - "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${uboot_size}; then " \ - "mmc write ${loadaddr} ${uboot_start} " \ - "${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_kernel=run kernel_name; " \ - "if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${kernel_size}; then " \ - "mmc write ${loadaddr} " \ - "${kernel_start} ${blkc}; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${fdt_size}; then " \ - "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - -#elif defined(CONFIG_TQMA6X_SPI_BOOT) - -#define TQMA6_UBOOT_OFFSET 0x400 -#define TQMA6_UBOOT_SECTOR_START 0x0 -/* max u-boot size: 512k */ -#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE -#define TQMA6_UBOOT_SECTOR_COUNT 0x8 -#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ - TQMA6_UBOOT_SECTOR_COUNT) - -#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ - CONFIG_ENV_SECT_SIZE) -#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) - -#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ -#define TQMA6_FDT_SECTOR_COUNT 0x01 - -#define TQMA6_KERNEL_SECTOR_START 0x10 -#define TQMA6_KERNEL_SECTOR_COUNT 0x60 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "mmcblkdev=0\0" \ - "uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0" \ - "uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr blkc ${filesize} + " \ - __stringify(TQMA6_UBOOT_OFFSET) "; " \ - "setexpr size ${uboot_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${blkc} <= ${size}; then " \ - "sf probe; " \ - "sf erase 0 ${size}; " \ - "sf write ${loadaddr} ${uboot_offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv blkc; setenv size \0" \ - "update_kernel=run kernel_name; if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "loadimage=sf probe; " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${loadaddr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" \ - "loadfdt=sf probe; " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${fdt_addr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" -#else - -#error "need to define boot source" - -#endif - /* 128 MiB offset as in ARM related docu for linux suggested */ #define TQMA6_FDT_ADDRESS 0x18000000 -/* set to a resonable value, changeable by user */ -#define TQMA6_CMA_SIZE 160M +/* 256KiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_256K) */ +#define TQMA6_FDT_OVERLAY_ADDR 0x18040000 -#define CFG_EXTRA_ENV_SETTINGS \ - "board=tqma6\0" \ - "uimage=uImage\0" \ - "zimage=zImage\0" \ - "boot_type=bootz\0" \ - "kernel_name=if test \"${boot_type}\" != bootz; then " \ - "setenv kernel ${uimage}; " \ - "else setenv kernel ${zimage}; fi\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ - "console=" CONSOLE_DEV "\0" \ - "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \ - "initrd_high=0xffffffff\0" \ - "rootfsmode=ro\0" \ - "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \ - "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ - "addfb=setenv bootargs ${bootargs} " \ - "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ - "mmcpart=2\0" \ - "mmcblkdev=0\0" \ - "mmcargs=run addmmc addtty addfb addcma\0" \ - "addmmc=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \ - "rootwait\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "setenv bootargs; " \ - "run mmcargs; " \ - "run loadimage; " \ - "if run loadfdt; then " \ - "echo boot device tree kernel ...; " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "${boot_type}; " \ - "fi;\0" \ - "setenv bootargs \0" \ - "netdev=eth0\0" \ - "rootpath=/srv/nfs/tqma6\0" \ - "ipmode=static\0" \ - "netargs=run addnfs addip addtty addfb addcma\0" \ - "addnfs=setenv bootargs ${bootargs} " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ - "addip_static=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:${netdev}:off\0" \ - "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test \"${ipmode}\" != static; then " \ - "run addip_dynamic; else run addip_static; fi\0" \ - "set_getcmd=if test \"${ipmode}\" != static; then " \ - "setenv getcmd dhcp; setenv autoload yes; " \ - "else setenv getcmd tftp; setenv autoload no; fi\0" \ - "netboot=echo Booting from net ...; " \ - "run kernel_name; " \ - "run set_getcmd; " \ - "setenv bootargs; " \ - "run netargs; " \ - "if ${getcmd} ${kernel}; then " \ - "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "fi; " \ - "fi; " \ - "echo ... failed\0" \ - "panicboot=echo No boot device !!! reset\0" \ - TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ +/* 16MiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_16M) */ +#define TQMA6_INITRD_ADDRESS 0x19000000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -265,19 +31,11 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* - * All the defines above are for the TQMa6 SoM - * - * Now include the baseboard specific configuration - */ -#ifdef CONFIG_MBA6 -#include "tqma6_mba6.h" -#elif CONFIG_WRU4 -#include "tqma6_wru4.h" -#else -#error "No baseboard for the TQMa6 defined!" -#endif +#define TQMA6_MMC_UBOOT_SECTOR_START 0x2 +#define TQMA6_MMC_UBOOT_SECTOR_COUNT 0x7fe -/* Support at least the sensor on TQMa6 SOM */ +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K +#define TQMA6_SPI_UBOOT_START 0x400 +#define TQMA6_SPI_UBOOT_SIZE 0xc0000 -#endif /* __CONFIG_H */ +#endif /* __TQMA6_CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 9b9f4150951..c30aeae4f29 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -11,9 +11,8 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CFG_FEC_MXC_PHYADDR 0x03 +#include "tqma6.h" #define CFG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" #endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 110bd895a8a..b35e471bd95 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_TQMA6_WRU4_H #define __CONFIG_TQMA6_WRU4_H +#include "tqma6.h" + /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 0x01 diff --git a/include/dt-bindings/clock/mediatek,mt8189-clk.h b/include/dt-bindings/clock/mediatek,mt8189-clk.h new file mode 100644 index 00000000000..ffbc1814f28 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8189-clk.h @@ -0,0 +1,580 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#ifndef _DT_BINDINGS_CLK_MT8189_H +#define _DT_BINDINGS_CLK_MT8189_H + +/* TOPCKGEN */ +#define CLK_TOP_AXI_SEL 0 +#define CLK_TOP_AXI_PERI_SEL 1 +#define CLK_TOP_AXI_U_SEL 2 +#define CLK_TOP_BUS_AXIMEM_SEL 3 +#define CLK_TOP_DISP0_SEL 4 +#define CLK_TOP_MMINFRA_SEL 5 +#define CLK_TOP_UART_SEL 6 +#define CLK_TOP_SPI0_SEL 7 +#define CLK_TOP_SPI1_SEL 8 +#define CLK_TOP_SPI2_SEL 9 +#define CLK_TOP_SPI3_SEL 10 +#define CLK_TOP_SPI4_SEL 11 +#define CLK_TOP_SPI5_SEL 12 +#define CLK_TOP_MSDC_MACRO_0P_SEL 13 +#define CLK_TOP_MSDC50_0_HCLK_SEL 14 +#define CLK_TOP_MSDC50_0_SEL 15 +#define CLK_TOP_AES_MSDCFDE_SEL 16 +#define CLK_TOP_MSDC_MACRO_1P_SEL 17 +#define CLK_TOP_MSDC30_1_SEL 18 +#define CLK_TOP_MSDC30_1_HCLK_SEL 19 +#define CLK_TOP_MSDC_MACRO_2P_SEL 20 +#define CLK_TOP_MSDC30_2_SEL 21 +#define CLK_TOP_MSDC30_2_HCLK_SEL 22 +#define CLK_TOP_AUD_INTBUS_SEL 23 +#define CLK_TOP_ATB_SEL 24 +#define CLK_TOP_DISP_PWM_SEL 25 +#define CLK_TOP_USB_TOP_P0_SEL 26 +#define CLK_TOP_USB_XHCI_P0_SEL 27 +#define CLK_TOP_USB_TOP_P1_SEL 28 +#define CLK_TOP_USB_XHCI_P1_SEL 29 +#define CLK_TOP_USB_TOP_P2_SEL 30 +#define CLK_TOP_USB_XHCI_P2_SEL 31 +#define CLK_TOP_USB_TOP_P3_SEL 32 +#define CLK_TOP_USB_XHCI_P3_SEL 33 +#define CLK_TOP_USB_TOP_P4_SEL 34 +#define CLK_TOP_USB_XHCI_P4_SEL 35 +#define CLK_TOP_I2C_SEL 36 +#define CLK_TOP_SENINF_SEL 37 +#define CLK_TOP_SENINF1_SEL 38 +#define CLK_TOP_AUD_ENGEN1_SEL 39 +#define CLK_TOP_AUD_ENGEN2_SEL 40 +#define CLK_TOP_AES_UFSFDE_SEL 41 +#define CLK_TOP_U_SEL 42 +#define CLK_TOP_U_MBIST_SEL 43 +#define CLK_TOP_AUD_1_SEL 44 +#define CLK_TOP_AUD_2_SEL 45 +#define CLK_TOP_VENC_SEL 46 +#define CLK_TOP_VDEC_SEL 47 +#define CLK_TOP_PWM_SEL 48 +#define CLK_TOP_AUDIO_H_SEL 49 +#define CLK_TOP_MCUPM_SEL 50 +#define CLK_TOP_MEM_SUB_SEL 51 +#define CLK_TOP_MEM_SUB_PERI_SEL 52 +#define CLK_TOP_MEM_SUB_U_SEL 53 +#define CLK_TOP_EMI_N_SEL 54 +#define CLK_TOP_DSI_OCC_SEL 55 +#define CLK_TOP_AP2CONN_HOST_SEL 56 +#define CLK_TOP_IMG1_SEL 57 +#define CLK_TOP_IPE_SEL 58 +#define CLK_TOP_CAM_SEL 59 +#define CLK_TOP_CAMTM_SEL 60 +#define CLK_TOP_DSP_SEL 61 +#define CLK_TOP_SR_PKA_SEL 62 +#define CLK_TOP_DXCC_SEL 63 +#define CLK_TOP_MFG_REF_SEL 64 +#define CLK_TOP_MDP0_SEL 65 +#define CLK_TOP_DP_SEL 66 +#define CLK_TOP_EDP_SEL 67 +#define CLK_TOP_EDP_FAVT_SEL 68 +#define CLK_TOP_ETH_250M_SEL 69 +#define CLK_TOP_ETH_62P4M_PTP_SEL 70 +#define CLK_TOP_ETH_50M_RMII_SEL 71 +#define CLK_TOP_SFLASH_SEL 72 +#define CLK_TOP_GCPU_SEL 73 +#define CLK_TOP_MAC_TL_SEL 74 +#define CLK_TOP_VDSTX_DG_CTS_SEL 75 +#define CLK_TOP_PLL_DPIX_SEL 76 +#define CLK_TOP_ECC_SEL 77 +#define CLK_TOP_APLL_I2SIN0_MCK_SEL 78 +#define CLK_TOP_APLL_I2SIN1_MCK_SEL 79 +#define CLK_TOP_APLL_I2SIN2_MCK_SEL 80 +#define CLK_TOP_APLL_I2SIN3_MCK_SEL 81 +#define CLK_TOP_APLL_I2SIN4_MCK_SEL 82 +#define CLK_TOP_APLL_I2SIN6_MCK_SEL 83 +#define CLK_TOP_APLL_I2SOUT0_MCK_SEL 84 +#define CLK_TOP_APLL_I2SOUT1_MCK_SEL 85 +#define CLK_TOP_APLL_I2SOUT2_MCK_SEL 86 +#define CLK_TOP_APLL_I2SOUT3_MCK_SEL 87 +#define CLK_TOP_APLL_I2SOUT4_MCK_SEL 88 +#define CLK_TOP_APLL_I2SOUT6_MCK_SEL 89 +#define CLK_TOP_APLL_FMI2S_MCK_SEL 90 +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 91 +#define CLK_TOP_MFG_SEL_MFGPLL 92 +#define CLK_TOP_APLL12_CK_DIV_I2SIN0 93 +#define CLK_TOP_APLL12_CK_DIV_I2SIN1 94 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT0 95 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT1 96 +#define CLK_TOP_APLL12_CK_DIV_FMI2S 97 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 98 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 99 +#define CLK_TOP_MAINPLL_D3 100 +#define CLK_TOP_MAINPLL_D4 101 +#define CLK_TOP_MAINPLL_D4_D2 102 +#define CLK_TOP_MAINPLL_D4_D4 103 +#define CLK_TOP_MAINPLL_D4_D8 104 +#define CLK_TOP_MAINPLL_D5 105 +#define CLK_TOP_MAINPLL_D5_D2 106 +#define CLK_TOP_MAINPLL_D5_D4 107 +#define CLK_TOP_MAINPLL_D5_D8 108 +#define CLK_TOP_MAINPLL_D6 109 +#define CLK_TOP_MAINPLL_D6_D2 110 +#define CLK_TOP_MAINPLL_D6_D4 111 +#define CLK_TOP_MAINPLL_D6_D8 112 +#define CLK_TOP_MAINPLL_D7 113 +#define CLK_TOP_MAINPLL_D7_D2 114 +#define CLK_TOP_MAINPLL_D7_D4 115 +#define CLK_TOP_MAINPLL_D7_D8 116 +#define CLK_TOP_MAINPLL_D9 117 +#define CLK_TOP_UNIVPLL_D2 118 +#define CLK_TOP_UNIVPLL_D3 119 +#define CLK_TOP_UNIVPLL_D4 120 +#define CLK_TOP_UNIVPLL_D4_D2 121 +#define CLK_TOP_UNIVPLL_D4_D4 122 +#define CLK_TOP_UNIVPLL_D4_D8 123 +#define CLK_TOP_UNIVPLL_D5 124 +#define CLK_TOP_UNIVPLL_D5_D2 125 +#define CLK_TOP_UNIVPLL_D5_D4 126 +#define CLK_TOP_UNIVPLL_D6 127 +#define CLK_TOP_UNIVPLL_D6_D2 128 +#define CLK_TOP_UNIVPLL_D6_D4 129 +#define CLK_TOP_UNIVPLL_D6_D8 130 +#define CLK_TOP_UNIVPLL_D6_D16 131 +#define CLK_TOP_UNIVPLL_D7 132 +#define CLK_TOP_UNIVPLL_D7_D2 133 +#define CLK_TOP_UNIVPLL_D7_D3 134 +#define CLK_TOP_LVDSTX_DG_CTS 135 +#define CLK_TOP_UNIVPLL_192M 136 +#define CLK_TOP_UNIVPLL_192M_D2 137 +#define CLK_TOP_UNIVPLL_192M_D4 138 +#define CLK_TOP_UNIVPLL_192M_D8 139 +#define CLK_TOP_UNIVPLL_192M_D10 140 +#define CLK_TOP_UNIVPLL_192M_D16 141 +#define CLK_TOP_UNIVPLL_192M_D32 142 +#define CLK_TOP_APLL1_D2 143 +#define CLK_TOP_APLL1_D4 144 +#define CLK_TOP_APLL1_D8 145 +#define CLK_TOP_APLL1_D3 146 +#define CLK_TOP_APLL2_D2 147 +#define CLK_TOP_APLL2_D4 148 +#define CLK_TOP_APLL2_D8 149 +#define CLK_TOP_APLL2_D3 150 +#define CLK_TOP_MMPLL_D4 151 +#define CLK_TOP_MMPLL_D4_D2 152 +#define CLK_TOP_MMPLL_D4_D4 153 +#define CLK_TOP_VPLL_DPIX 154 +#define CLK_TOP_MMPLL_D5 155 +#define CLK_TOP_MMPLL_D5_D2 156 +#define CLK_TOP_MMPLL_D5_D4 157 +#define CLK_TOP_MMPLL_D6 158 +#define CLK_TOP_MMPLL_D6_D2 159 +#define CLK_TOP_MMPLL_D7 160 +#define CLK_TOP_MMPLL_D9 161 +#define CLK_TOP_TVDPLL1_D2 162 +#define CLK_TOP_TVDPLL1_D4 163 +#define CLK_TOP_TVDPLL1_D8 164 +#define CLK_TOP_TVDPLL1_D16 165 +#define CLK_TOP_TVDPLL2_D2 166 +#define CLK_TOP_TVDPLL2_D4 167 +#define CLK_TOP_TVDPLL2_D8 168 +#define CLK_TOP_TVDPLL2_D16 169 +#define CLK_TOP_ETHPLL_D2 170 +#define CLK_TOP_ETHPLL_D8 171 +#define CLK_TOP_ETHPLL_D10 172 +#define CLK_TOP_MSDCPLL_D2 173 +#define CLK_TOP_VOWPLL 174 +#define CLK_TOP_UFSPLL_D2 175 +#define CLK_TOP_F26M_CK_D2 176 +#define CLK_TOP_OSC_D2 177 +#define CLK_TOP_OSC_D4 178 +#define CLK_TOP_OSC_D8 179 +#define CLK_TOP_OSC_D16 180 +#define CLK_TOP_OSC_D3 181 +#define CLK_TOP_OSC_D7 182 +#define CLK_TOP_OSC_D10 183 +#define CLK_TOP_OSC_D20 184 +#define CLK_TOP_FMCNT_P0_EN 185 +#define CLK_TOP_FMCNT_P1_EN 186 +#define CLK_TOP_FMCNT_P2_EN 187 +#define CLK_TOP_FMCNT_P3_EN 188 +#define CLK_TOP_FMCNT_P4_EN 189 +#define CLK_TOP_USB_F26M_CK_EN 190 +#define CLK_TOP_SSPXTP_F26M_CK_EN 191 +#define CLK_TOP_USB2_PHY_RF_P0_EN 192 +#define CLK_TOP_USB2_PHY_RF_P1_EN 193 +#define CLK_TOP_USB2_PHY_RF_P2_EN 194 +#define CLK_TOP_USB2_PHY_RF_P3_EN 195 +#define CLK_TOP_USB2_PHY_RF_P4_EN 196 +#define CLK_TOP_USB2_26M_CK_P0_EN 197 +#define CLK_TOP_USB2_26M_CK_P1_EN 198 +#define CLK_TOP_USB2_26M_CK_P2_EN 199 +#define CLK_TOP_USB2_26M_CK_P3_EN 200 +#define CLK_TOP_USB2_26M_CK_P4_EN 201 +#define CLK_TOP_F26M_CK_EN 202 +#define CLK_TOP_AP2CON_EN 203 +#define CLK_TOP_EINT_N_EN 204 +#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN 205 +#define CLK_TOP_DRAMULP_CK_EN 206 +#define CLK_TOP_EINT_E_EN 207 +#define CLK_TOP_EINT_W_EN 208 +#define CLK_TOP_EINT_S_EN 209 + +/* INFRACFG_AO */ +#define CLK_IFRAO_CQ_DMA_FPC 0 +#define CLK_IFRAO_DEBUGSYS 1 +#define CLK_IFRAO_DBG_TRACE 2 +#define CLK_IFRAO_CQ_DMA 3 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_BL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIVPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_MFGPLL 6 +#define CLK_APMIXED_APLL1 7 +#define CLK_APMIXED_APLL2 8 +#define CLK_APMIXED_EMIPLL 9 +#define CLK_APMIXED_APUPLL2 10 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_TVDPLL1 12 +#define CLK_APMIXED_TVDPLL2 13 +#define CLK_APMIXED_ETHPLL 14 +#define CLK_APMIXED_MSDCPLL 15 +#define CLK_APMIXED_UFSPLL 16 + +/* PERICFG_AO */ +#define CLK_PERAO_UART0 0 +#define CLK_PERAO_UART1 1 +#define CLK_PERAO_UART2 2 +#define CLK_PERAO_UART3 3 +#define CLK_PERAO_PWM_H 4 +#define CLK_PERAO_PWM_B 5 +#define CLK_PERAO_PWM_FB1 6 +#define CLK_PERAO_PWM_FB2 7 +#define CLK_PERAO_PWM_FB3 8 +#define CLK_PERAO_PWM_FB4 9 +#define CLK_PERAO_DISP_PWM0 10 +#define CLK_PERAO_DISP_PWM1 11 +#define CLK_PERAO_SPI0_B 12 +#define CLK_PERAO_SPI1_B 13 +#define CLK_PERAO_SPI2_B 14 +#define CLK_PERAO_SPI3_B 15 +#define CLK_PERAO_SPI4_B 16 +#define CLK_PERAO_SPI5_B 17 +#define CLK_PERAO_SPI0_H 18 +#define CLK_PERAO_SPI1_H 19 +#define CLK_PERAO_SPI2_H 20 +#define CLK_PERAO_SPI3_H 21 +#define CLK_PERAO_SPI4_H 22 +#define CLK_PERAO_SPI5_H 23 +#define CLK_PERAO_AXI 24 +#define CLK_PERAO_AHB_APB 25 +#define CLK_PERAO_TL 26 +#define CLK_PERAO_REF 27 +#define CLK_PERAO_I2C 28 +#define CLK_PERAO_DMA_B 29 +#define CLK_PERAO_SSUSB0_REF 30 +#define CLK_PERAO_SSUSB0_FRMCNT 31 +#define CLK_PERAO_SSUSB0_SYS 32 +#define CLK_PERAO_SSUSB0_XHCI 33 +#define CLK_PERAO_SSUSB0_F 34 +#define CLK_PERAO_SSUSB0_H 35 +#define CLK_PERAO_SSUSB1_REF 36 +#define CLK_PERAO_SSUSB1_FRMCNT 37 +#define CLK_PERAO_SSUSB1_SYS 38 +#define CLK_PERAO_SSUSB1_XHCI 39 +#define CLK_PERAO_SSUSB1_F 40 +#define CLK_PERAO_SSUSB1_H 41 +#define CLK_PERAO_SSUSB2_REF 42 +#define CLK_PERAO_SSUSB2_FRMCNT 43 +#define CLK_PERAO_SSUSB2_SYS 44 +#define CLK_PERAO_SSUSB2_XHCI 45 +#define CLK_PERAO_SSUSB2_F 46 +#define CLK_PERAO_SSUSB2_H 47 +#define CLK_PERAO_SSUSB3_REF 48 +#define CLK_PERAO_SSUSB3_FRMCNT 49 +#define CLK_PERAO_SSUSB3_SYS 50 +#define CLK_PERAO_SSUSB3_XHCI 51 +#define CLK_PERAO_SSUSB3_F 52 +#define CLK_PERAO_SSUSB3_H 53 +#define CLK_PERAO_SSUSB4_REF 54 +#define CLK_PERAO_SSUSB4_FRMCNT 55 +#define CLK_PERAO_SSUSB4_SYS 56 +#define CLK_PERAO_SSUSB4_XHCI 57 +#define CLK_PERAO_SSUSB4_F 58 +#define CLK_PERAO_SSUSB4_H 59 +#define CLK_PERAO_MSDC0 60 +#define CLK_PERAO_MSDC0_H 61 +#define CLK_PERAO_MSDC0_FAES 62 +#define CLK_PERAO_MSDC0_MST_F 63 +#define CLK_PERAO_MSDC0_SLV_H 64 +#define CLK_PERAO_MSDC1 65 +#define CLK_PERAO_MSDC1_H 66 +#define CLK_PERAO_MSDC1_MST_F 67 +#define CLK_PERAO_MSDC1_SLV_H 68 +#define CLK_PERAO_MSDC2 69 +#define CLK_PERAO_MSDC2_H 70 +#define CLK_PERAO_MSDC2_MST_F 71 +#define CLK_PERAO_MSDC2_SLV_H 72 +#define CLK_PERAO_SFLASH 73 +#define CLK_PERAO_SFLASH_F 74 +#define CLK_PERAO_SFLASH_H 75 +#define CLK_PERAO_SFLASH_P 76 +#define CLK_PERAO_AUDIO0 77 +#define CLK_PERAO_AUDIO1 78 +#define CLK_PERAO_AUDIO2 79 +#define CLK_PERAO_AUXADC_26M 80 + +/* UFSCFG_AO_REG */ +#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM 0 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0 1 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1 2 +#define CLK_UFSCFG_AO_REG_UNIPRO_SYS 3 +#define CLK_UFSCFG_AO_REG_U_SAP_CFG 4 +#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS 5 + +/* UFSCFG_PDN_REG */ +#define CLK_UFSCFG_REG_UFSHCI_UFS 0 +#define CLK_UFSCFG_REG_UFSHCI_AES 1 +#define CLK_UFSCFG_REG_UFSHCI_U_AHB 2 +#define CLK_UFSCFG_REG_UFSHCI_U_AXI 3 + +/* IMP_IIC_WRAP_WS */ +#define CLK_IMPWS_I2C2 0 + +/* IMP_IIC_WRAP_E */ +#define CLK_IMPE_I2C0 0 +#define CLK_IMPE_I2C1 1 + +/* IMP_IIC_WRAP_S */ +#define CLK_IMPS_I2C3 0 +#define CLK_IMPS_I2C4 1 +#define CLK_IMPS_I2C5 2 +#define CLK_IMPS_I2C6 3 + +/* IMP_IIC_WRAP_EN */ +#define CLK_IMPEN_I2C7 0 +#define CLK_IMPEN_I2C8 1 + +/* MFG */ +#define CLK_MFG_BG3D 0 + +/* DISPSYS_CONFIG */ +#define CLK_MM_DISP_OVL0_4L 0 +#define CLK_MM_DISP_OVL1_4L 1 +#define CLK_MM_VPP_RSZ0 2 +#define CLK_MM_VPP_RSZ1 3 +#define CLK_MM_DISP_RDMA0 4 +#define CLK_MM_DISP_RDMA1 5 +#define CLK_MM_DISP_COLOR0 6 +#define CLK_MM_DISP_COLOR1 7 +#define CLK_MM_DISP_CCORR0 8 +#define CLK_MM_DISP_CCORR1 9 +#define CLK_MM_DISP_CCORR2 10 +#define CLK_MM_DISP_CCORR3 11 +#define CLK_MM_DISP_AAL0 12 +#define CLK_MM_DISP_AAL1 13 +#define CLK_MM_DISP_GAMMA0 14 +#define CLK_MM_DISP_GAMMA1 15 +#define CLK_MM_DISP_DITHER0 16 +#define CLK_MM_DISP_DITHER1 17 +#define CLK_MM_DISP_DSC_WRAP0 18 +#define CLK_MM_VPP_MERGE0 19 +#define CLK_MMSYS_0_DISP_DVO 20 +#define CLK_MMSYS_0_DISP_DSI0 21 +#define CLK_MM_DP_INTF0 22 +#define CLK_MM_DPI0 23 +#define CLK_MM_DISP_WDMA0 24 +#define CLK_MM_DISP_WDMA1 25 +#define CLK_MM_DISP_FAKE_ENG0 26 +#define CLK_MM_DISP_FAKE_ENG1 27 +#define CLK_MM_SMI_LARB 28 +#define CLK_MM_DISP_MUTEX0 29 +#define CLK_MM_DIPSYS_CONFIG 30 +#define CLK_MM_DUMMY 31 +#define CLK_MMSYS_1_DISP_DSI0 32 +#define CLK_MMSYS_1_LVDS_ENCODER 33 +#define CLK_MMSYS_1_DPI0 34 +#define CLK_MMSYS_1_DISP_DVO 35 +#define CLK_MM_DP_INTF 36 +#define CLK_MMSYS_1_LVDS_ENCODER_CTS 37 +#define CLK_MMSYS_1_DISP_DVO_AVT 38 + +/* IMGSYS1 */ +#define CLK_IMGSYS1_LARB9 0 +#define CLK_IMGSYS1_LARB11 1 +#define CLK_IMGSYS1_DIP 2 +#define CLK_IMGSYS1_GALS 3 + +/* IMGSYS2 */ +#define CLK_IMGSYS2_LARB9 0 +#define CLK_IMGSYS2_LARB11 1 +#define CLK_IMGSYS2_MFB 2 +#define CLK_IMGSYS2_WPE 3 +#define CLK_IMGSYS2_MSS 4 +#define CLK_IMGSYS2_GALS 5 + +/* VDEC_CORE */ +#define CLK_VDEC_CORE_LARB_CKEN 0 +#define CLK_VDEC_CORE_VDEC_CKEN 1 +#define CLK_VDEC_CORE_VDEC_ACTIVE 2 + +/* VENC_GCON */ +#define CLK_VEN1_CKE0_LARB 0 +#define CLK_VEN1_CKE1_VENC 1 +#define CLK_VEN1_CKE2_JPGENC 2 +#define CLK_VEN1_CKE3_JPGDEC 3 +#define CLK_VEN1_CKE4_JPGDEC_C1 4 +#define CLK_VEN1_CKE5_GALS 5 +#define CLK_VEN1_CKE6_GALS_SRAM 6 + +/* VLPCFG_REG */ +#define CLK_VLPCFG_REG_SCP 0 +#define CLK_VLPCFG_REG_RG_R_APXGPT_26M 1 +#define CLK_VLPCFG_REG_DPMSRCK_TEST 2 +#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST 3 +#define CLK_VLPCFG_REG_DPMSRULP_TEST 4 +#define CLK_VLPCFG_REG_SPMI_P_MST 5 +#define CLK_VLPCFG_REG_SPMI_P_MST_32K 6 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS 7 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR 8 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS 9 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR 10 +#define CLK_VLPCFG_REG_DVFSRC 11 +#define CLK_VLPCFG_REG_PWM_VLP 12 +#define CLK_VLPCFG_REG_SRCK 13 +#define CLK_VLPCFG_REG_SSPM_F26M 14 +#define CLK_VLPCFG_REG_SSPM_F32K 15 +#define CLK_VLPCFG_REG_SSPM_ULPOSC 16 +#define CLK_VLPCFG_REG_VLP_32K_COM 17 +#define CLK_VLPCFG_REG_VLP_26M_COM 18 + +/* VLP_CKSYS */ +#define CLK_VLP_CK_SCP_SEL 0 +#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1 +#define CLK_VLP_CK_SPMI_P_MST_SEL 2 +#define CLK_VLP_CK_DVFSRC_SEL 3 +#define CLK_VLP_CK_PWM_VLP_SEL 4 +#define CLK_VLP_CK_AXI_VLP_SEL 5 +#define CLK_VLP_CK_SYSTIMER_26M_SEL 6 +#define CLK_VLP_CK_SSPM_SEL 7 +#define CLK_VLP_CK_SSPM_F26M_SEL 8 +#define CLK_VLP_CK_SRCK_SEL 9 +#define CLK_VLP_CK_SCP_SPI_SEL 10 +#define CLK_VLP_CK_SCP_IIC_SEL 11 +#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL 12 +#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 13 +#define CLK_VLP_CK_SSPM_ULPOSC_SEL 14 +#define CLK_VLP_CK_APXGPT_26M_SEL 15 +#define CLK_VLP_CK_VADSP_SEL 16 +#define CLK_VLP_CK_VADSP_VOWPLL_SEL 17 +#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL 18 +#define CLK_VLP_CK_CAMTG0_SEL 19 +#define CLK_VLP_CK_CAMTG1_SEL 20 +#define CLK_VLP_CK_CAMTG2_SEL 21 +#define CLK_VLP_CK_AUD_ADC_SEL 22 +#define CLK_VLP_CK_KP_IRQ_GEN_SEL 23 +#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24 +#define CLK_VLP_CK_SEJ_13M_EN 25 +#define CLK_VLP_CK_SEJ_26M_EN 26 +#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 27 + +/* SCP_IIC */ +#define CLK_SCP_IIC_I2C0_W1S 0 +#define CLK_SCP_IIC_I2C1_W1S 1 + +/* SCP */ +#define CLK_SCP_SET_SPI0 0 +#define CLK_SCP_SET_SPI1 1 + +/* CAMSYS_MAIN */ +#define CLK_CAM_M_LARB13 0 +#define CLK_CAM_M_LARB14 1 +#define CLK_CAM_M_CAMSYS_MAIN_CAM 2 +#define CLK_CAM_M_CAMSYS_MAIN_CAMTG 3 +#define CLK_CAM_M_SENINF 4 +#define CLK_CAM_M_CAMSV1 5 +#define CLK_CAM_M_CAMSV2 6 +#define CLK_CAM_M_CAMSV3 7 +#define CLK_CAM_M_FAKE_ENG 8 +#define CLK_CAM_M_CAM2MM_GALS 9 +#define CLK_CAM_M_CAMSV4 10 +#define CLK_CAM_M_PDA 11 + +/* CAMSYS_RAWA */ +#define CLK_CAM_RA_CAMSYS_RAWA_LARBX 0 +#define CLK_CAM_RA_CAMSYS_RAWA_CAM 1 +#define CLK_CAM_RA_CAMSYS_RAWA_CAMTG 2 + +/* CAMSYS_RAWB */ +#define CLK_CAM_RB_CAMSYS_RAWB_LARBX 0 +#define CLK_CAM_RB_CAMSYS_RAWB_CAM 1 +#define CLK_CAM_RB_CAMSYS_RAWB_CAMTG 2 + +/* IPESYS */ +#define CLK_IPE_LARB19 0 +#define CLK_IPE_LARB20 1 +#define CLK_IPE_SMI_SUBCOM 2 +#define CLK_IPE_FD 3 +#define CLK_IPE_FE 4 +#define CLK_IPE_RSC 5 +#define CLK_IPESYS_GALS 6 + +/* VLPCFG_AO_REG */ +#define CLK_VLPCFG_AO_APEINT_RX 0 + +/* DVFSRC_TOP */ +#define CLK_DVFSRC_TOP_DVFSRC_EN 0 + +/* MMINFRA_CONFIG */ +#define CLK_MMINFRA_GCE_D 0 +#define CLK_MMINFRA_GCE_M 1 +#define CLK_MMINFRA_SMI 2 +#define CLK_MMINFRA_GCE_26M 3 + +/* GCE_D */ +#define CLK_GCE_D_TOP 0 + +/* GCE_M */ +#define CLK_GCE_M_TOP 0 + +/* MDPSYS_CONFIG */ +#define CLK_MDP_MUTEX0 0 +#define CLK_MDP_APB_BUS 1 +#define CLK_MDP_SMI0 2 +#define CLK_MDP_RDMA0 3 +#define CLK_MDP_RDMA2 4 +#define CLK_MDP_HDR0 5 +#define CLK_MDP_AAL0 6 +#define CLK_MDP_RSZ0 7 +#define CLK_MDP_TDSHP0 8 +#define CLK_MDP_COLOR0 9 +#define CLK_MDP_WROT0 10 +#define CLK_MDP_FAKE_ENG0 11 +#define CLK_MDPSYS_CONFIG 12 +#define CLK_MDP_RDMA1 13 +#define CLK_MDP_RDMA3 14 +#define CLK_MDP_HDR1 15 +#define CLK_MDP_AAL1 16 +#define CLK_MDP_RSZ1 17 +#define CLK_MDP_TDSHP1 18 +#define CLK_MDP_COLOR1 19 +#define CLK_MDP_WROT1 20 +#define CLK_MDP_RSZ2 21 +#define CLK_MDP_WROT2 22 +#define CLK_MDP_RSZ3 23 +#define CLK_MDP_WROT3 24 +#define CLK_MDP_BIRSZ0 25 +#define CLK_MDP_BIRSZ1 26 + +/* DBGAO */ +#define CLK_DBGAO_ATB_EN 0 + +/* DEM */ +#define CLK_DEM_ATB_EN 0 +#define CLK_DEM_BUSCLK_EN 1 +#define CLK_DEM_SYSCLK_EN 2 + +#endif /* _DT_BINDINGS_CLK_MT8189_H */ diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h deleted file mode 100644 index 6a0b70a37d7..00000000000 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018-2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - -#endif diff --git a/include/efi_loader.h b/include/efi_loader.h index 3e70ac07055..3a4d502631c 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -387,6 +387,10 @@ extern const efi_guid_t efi_guid_capsule_report; extern const efi_guid_t efi_guid_firmware_management_protocol; /* GUID for the ESRT */ extern const efi_guid_t efi_esrt_guid; +/* GUID for the ECPT */ +#if CONFIG_IS_ENABLED(EFI_ECPT) +extern const efi_guid_t efi_ecpt_guid; +#endif /* GUID of the SMBIOS table */ extern const efi_guid_t smbios_guid; extern const efi_guid_t smbios3_guid; @@ -1144,6 +1148,9 @@ struct pkcs7_message *efi_parse_pkcs7_header(const void *buf, /* runtime implementation of memcpy() */ void efi_memcpy_runtime(void *dest, const void *src, size_t n); +/* runtime implementation of memcmp() */ +int efi_memcmp_runtime(const void *s1, const void *s2, size_t n); + /* commonly used helper functions */ u16 *efi_create_indexed_name(u16 *buffer, size_t buffer_size, const char *name, unsigned int index); diff --git a/include/efi_variable.h b/include/efi_variable.h index 4065cf45eca..c3229c717d8 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -137,13 +137,11 @@ struct efi_var_file { }; /** - * efi_var_to_file() - save non-volatile variables as file - * - * File ubootefi.var is created on the EFI system partion. + * efi_var_to_storage() - save non-volatile variables * * Return: status code */ -efi_status_t efi_var_to_file(void); +efi_status_t efi_var_to_storage(void); /** * efi_var_collect() - collect variables in buffer @@ -161,6 +159,11 @@ efi_status_t efi_var_to_file(void); efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, u32 check_attr_mask); +/* GUID used by Shim to store the MOK database */ +#define SHIM_LOCK_GUID \ + EFI_GUID(0x605dab50, 0xe046, 0x4300, \ + 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23) + /** * efi_var_restore() - restore EFI variables from buffer * @@ -173,17 +176,14 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t * efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe); /** - * efi_var_from_file() - read variables from file - * - * File ubootefi.var is read from the EFI system partitions and the variables - * stored in the file are created. + * efi_var_from_storage() - read variables * * In case the file does not exist yet or a variable cannot be set EFI_SUCCESS * is returned. * * Return: status code */ -efi_status_t efi_var_from_file(void); +efi_status_t efi_var_from_storage(void); /** * efi_var_mem_init() - set-up variable list @@ -216,6 +216,11 @@ void efi_var_mem_del(struct efi_var_entry *var); * The variable is appended without checking if a variable of the same name * already exists. The two data buffers are concatenated. * + * When @changep is non-NULL and @size2 is 0, the function compares the new + * value against an existing variable with the same name and vendor. If + * attributes and data are identical the insertion is skipped and *@changep + * is set to false, avoiding superfluous writes. + * * @variable_name: variable name * @vendor: GUID * @attributes: variable attributes @@ -224,13 +229,14 @@ void efi_var_mem_del(struct efi_var_entry *var); * @size2: size of the second data field * @data2: second data buffer * @time: time of authentication (as seconds since start of epoch) + * @changep: pointer to change flag (may be NULL) * Result: status code */ efi_status_t efi_var_mem_ins(const u16 *variable_name, const efi_guid_t *vendor, u32 attributes, const efi_uintn_t size1, const void *data1, const efi_uintn_t size2, const void *data2, - const u64 time); + const u64 time, bool *changep); /** * efi_var_mem_free() - determine free memory for variables diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index a0ed83f52ac..62b93eb25c4 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -24,12 +24,10 @@ get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile} run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} bootcmd_ti_mmc= run init_${boot}; -#if CONFIG_CMD_REMOTEPROC - if env exists do_main_cpsw0_qsgmii_phyinit; - then run main_cpsw0_qsgmii_phyinit; + if test -n ${board_init}; then + echo Running board_init ...; + run board_init; fi; - run boot_rprocs; -#endif if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_fit_overlaystring; run run_fit; else; diff --git a/include/env/tq/mmc.env b/include/env/tq/mmc.env new file mode 100644 index 00000000000..abf561f8467 --- /dev/null +++ b/include/env/tq/mmc.env @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared mmc environment for TQ boards + */ + +addmmc= + setenv bootargs "${bootargs}" + root=/dev/mmcblk"${mmcblkdev}"p"${mmcrootpart}" "${rootfsmode}" rootwait; + +get_blockcount= + setexpr blkc "${filesize}" + 0x1ff; + setexpr blkc "${blkc}" / 0x200; + +load_mmc= + mmc dev "${mmcdev}"; mmc rescan; + load mmc "${mmcdev}":"${mmcpart}" "${kernel_addr_r}" /boot/"${image}"; + load mmc "${mmcdev}":"${mmcpart}" "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + load mmc "${mmcdev}":"${mmcpart}" "${fdtoverlay_addr_r}" + /boot/"${overlay}" && fdt apply "${fdtoverlay_addr_r}"; + done; + +mmcargs=run addtty addmmc + +mmcboot= + echo "Booting from mmc ..."; + setenv bootargs && run mmcargs && + if run load_mmc; then + run boot_os; + else + echo "ERROR: loading from mmc"; + fi; + +mmcpart=2 + +mmc_finish_update_uboot= + mmc write "${loadaddr}" "${update_start_blk}" "${blkc}"; + mmc dev "${mmcdev}" 0; + setenv update_part; + setenv update_start_blk; + setenv blkc; + +mmc_prepare_update_uboot= + echo "Write U-Boot to mmc "${mmcdev}" ..."; + mmc dev "${mmcdev}"; mmc rescan; + run get_blockcount; + setenv update_start_blk "${uboot_mmc_start}"; + setenv update_part 0; + +mmc_switch_part= + mmc partconf "${mmcdev}" update_part; + mmc dev "${mmcdev}" "${update_part}"; + +mmcrootpart=2 + +update_uboot_mmc= + run check_ipaddr; + if tftp "${uboot}"; then + run mmc_prepare_update_uboot; + if itest "${blkc}" >= "${uboot_mmc_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + if itest "${mmcdev}" == "${emmc_dev}"; then + run mmc_switch_part; + if itest "${update_part}" > 0 ; then + if env exists emmc_bootp_start; then + setenv update_start_blk "${emmc_bootp_start}"; + else + echo "ERROR: eMMC boot partition block unset"; + exit; + fi; + fi; + fi; + run mmc_finish_update_uboot; + fi; diff --git a/include/env/tq/nfs.env b/include/env/tq/nfs.env new file mode 100644 index 00000000000..53fcbd0d152 --- /dev/null +++ b/include/env/tq/nfs.env @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared nfs environment for TQ boards + */ + +addnfs= + setenv bootargs "${bootargs}" root=/dev/nfs rw + nfsroot="${serverip}":"${rootpath}",v3,tcp + +load_nfs= + nfs "${kernel_addr_r}" "${serverip}":"${rootpath}"/boot/"${image}"; + nfs "${fdt_addr_r}" "${serverip}":"${rootpath}"/boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + nfs "${fdtoverlay_addr_r}" + "${serverip}":"${rootpath}"/boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + +load_tftp= + tftp "${kernel_addr_r}" "${image}"; + tftp "${fdt_addr_r}" "${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + if tftp "${fdtoverlay_addr_r}" "${overlay}"; then + fdt apply "${fdtoverlay_addr_r}"; + else + exit; + fi; + done; + +netargs=run addnfs addip addtty + +netloadcmd=load_tftp + +nfsboot= + echo "Booting from NFS ..."; + setenv bootargs; + run netargs; + run check_ipaddr; + if run ${netloadcmd}; then + run boot_os; + else + echo "ERROR: loading from NFS"; + fi; diff --git a/include/env/tq/spi.env b/include/env/tq/spi.env new file mode 100644 index 00000000000..47dcfea7d3f --- /dev/null +++ b/include/env/tq/spi.env @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared spi environment for TQ boards + */ + +update_uboot_spi= + run check_ipaddr; + if tftp ${uboot}; then + if itest "${filesize}" >= "${uboot_spi_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + echo "Write u-boot image to SPI NOR ..."; + if sf probe; then + run write_uboot_spi; + fi; + fi; + +write_uboot_spi=sf update "${loadaddr}" "${uboot_spi_start}" "${filesize}" diff --git a/include/env/tq/tq-imx-shared.env b/include/env/tq/tq-imx-shared.env new file mode 100644 index 00000000000..d4e42f8b536 --- /dev/null +++ b/include/env/tq/tq-imx-shared.env @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared environment for TQ imx boards + */ + +#ifdef CONFIG_CMD_SF +#include "spi.env" +#ifdef CONFIG_CMD_UBIFS +#include "ubi.env" +#endif /* CONFIG_CMD_UBIFS */ +#endif /* CONFIG_CMD_SF */ + +#ifdef CONFIG_CMD_MMC +#include "mmc.env" +#endif + +#ifdef CONFIG_CMD_NFS +#include "nfs.env" +#endif + +addip= + run check_ipaddr; + setenv bootargs "${bootargs}" + ip="${ipaddr}":"${serverip}":"${gatewayip}":"${netmask}":"${hostname}":"${netdev}":off + +addtty=setenv bootargs "${bootargs}" "${console}" + +check_ipaddr= + if test -z "${ipaddr}" || test -z "${serverip}"; then + echo "ipaddr or serverip unset, falling back to DHCP..."; + dhcp; + fi; + +rootfsmode=ro diff --git a/include/env/tq/ubi.env b/include/env/tq/ubi.env new file mode 100644 index 00000000000..01243d2eb53 --- /dev/null +++ b/include/env/tq/ubi.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared ubi environment for TQ boards + */ + +addubi= + setenv bootargs "${bootargs}" rootfstype=ubifs ubi.mtd="${ubimtdname}" + root=ubi0:"${ubirootfsvol}" "${rootfsmode}" rootwait; + +load_spi= + if sf probe; then + if ubi part "${ubirootfspart}"; then + if ubifsmount ubi0:"${ubirootfsvol}"; then + ubifsload "${kernel_addr_r}" /boot/"${image}"; + ubifsload "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + ubifsload "${fdtoverlay_addr_r}" + /boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + ubifsumount; + fi; + ubi detach; + fi; + fi + +ubiargs=run addubi addtty + +ubiboot= + echo "Booting from UBI ..."; + setenv bootargs; + run ubiargs; + if run load_spi; then + run boot_os; + else + echo "ERROR: loading kernel"; + fi; + +ubimtdname=mtdname +ubirootfspart=ubi +ubirootfsvol=root diff --git a/include/exception.h b/include/exception.h index a7f21e73d75..0d4dff49954 100644 --- a/include/exception.h +++ b/include/exception.h @@ -6,6 +6,7 @@ */ #include +#include static int do_exception(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/include/fat.h b/include/fat.h index bdf430f7067..40da0370a44 100644 --- a/include/fat.h +++ b/include/fat.h @@ -165,7 +165,9 @@ typedef struct { int fatsize; /* Size of FAT in bits */ __u32 fatlength; /* Length of FAT in sectors */ __u16 fat_sect; /* Starting sector of the FAT */ +#ifdef CONFIG_FAT_WRITE __u8 fat_dirty; /* Set if fatbuf has been modified */ +#endif __u32 rootdir_sect; /* Start sector of root directory */ __u16 sect_size; /* Size of sectors in bytes */ __u16 clust_size; /* Size of clusters in sectors */ @@ -190,6 +192,30 @@ static inline u32 sect_to_clust(fsdata *fsdata, int sect) return (sect - fsdata->data_begin) / fsdata->clust_size; } +static inline void fat_mark_clean(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + fsdata->fat_dirty = 0; +#endif +} + +static inline void fat_mark_dirty(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + fsdata->fat_dirty = 1; +#endif +} + +static inline bool fat_is_dirty(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + if (fsdata->fat_dirty) + return true; +#endif + + return false; +} + int file_fat_detectfs(void); int fat_exists(const char *filename); int fat_size(const char *filename, loff_t *size); diff --git a/include/fdtdec.h b/include/fdtdec.h index d9fcd037ed2..4e09f9d718c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -16,6 +16,7 @@ #include #include +#include /* * Support for 64bit fdt addresses. @@ -198,6 +199,29 @@ struct fdtdec_phandle_args { uint32_t args[MAX_PHANDLE_ARGS]; }; +/** + * fdtdec_get_next_memory_node() - Get the next enabled memory node from device tree + * + * @mem: Current memory node to start search from, or ofnode_null() to get first node + * + * This function iterates through device tree nodes with device_type = "memory" + * property, automatically skipping disabled nodes (status != "okay"). + * + * It is used to enumerate multiple memory regions when the system has + * non-contiguous or multiple memory banks defined in the device tree. + * The function continues searching from the given node onwards, looking + * for the next node with the "memory" device_type property and checking + * its status property. + * + * Can be called multiple times to iterate through all memory nodes. + * Pass ofnode_null() on first call, then pass the returned node + * on subsequent calls until an invalid node is returned. + * + * Return: Next valid, enabled memory ofnode, or invalid ofnode if no more + * memory nodes exist + */ +ofnode fdtdec_get_next_memory_node(ofnode mem); + /** * fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list * diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 876d52cac35..7f4ca735663 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -86,6 +86,7 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val); void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); +int sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type); int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx); void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); diff --git a/include/fwu.h b/include/fwu.h index e7bd1d492af..9cee8fb085c 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -80,9 +80,11 @@ struct fwu_mdata_ops { #define FWU_IMAGE_ACCEPTED 0x1 -#define FWU_BANK_INVALID (uint8_t)0xFF -#define FWU_BANK_VALID (uint8_t)0xFE -#define FWU_BANK_ACCEPTED (uint8_t)0xFC +enum fwu_bank_states { + FWU_BANK_INVALID = 0xFF, + FWU_BANK_VALID = 0xFE, + FWU_BANK_ACCEPTED = 0xFC, +}; enum { PRIMARY_PART = 1, @@ -396,24 +398,24 @@ int fwu_get_mdata_size(uint32_t *mdata_size); /** * fwu_state_machine_updates() - Update FWU state of the platform - * @trial_state: Is platform transitioning into Trial State + * @state: FWU bank state * @update_index: Bank number to which images have been updated * - * On successful completion of updates, transition the platform to - * either Trial State or Regular State. + * FWU_BANK_VALID transition the platform to Trial state + * FWU_BANK_ACCEPTED accept the FWU bank state + * FWU_BANK_INVALID invalid the FWU bank state * * To transition the platform to Trial State, start the * TrialStateCtr counter, followed by setting the value of bank_state * field of the metadata to Valid state(applicable only in version 2 * of metadata). * - * In case, the platform is to transition directly to Regular State, - * update the bank_state field of the metadata to Accepted - * state(applicable only in version 2 of metadata). + * Saving the bank_state field of the metadata is only applicable in + * version 2 of metadata. * * Return: 0 if OK, -ve on error */ -int fwu_state_machine_updates(bool trial_state, uint32_t update_index); +int fwu_state_machine_updates(enum fwu_bank_states state, uint32_t update_index); /** * fwu_init() - FWU specific initialisations diff --git a/include/linker_lists.h b/include/linker_lists.h index 0f4a2d686e2..78ba937c8c3 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -288,56 +288,6 @@ #define ll_entry_ref(_type, _name, _list) \ ((_type *)&_u_boot_list_2_##_list##_2_##_name) -/** - * ll_start() - Point to first entry of first linker-generated array - * @_type: Data type of the entry - * - * This function returns ``(_type *)`` pointer to the very first entry of - * the very first linker-generated array. - * - * Since this macro defines the start of the linker-generated arrays, - * its leftmost index must be 1. - * - * Example: - * - * :: - * - * struct my_sub_cmd *msc = ll_start(struct my_sub_cmd); - */ -#define ll_start(_type) \ -({ \ - static char start[0] __aligned(4) __attribute__((unused)) \ - __section("__u_boot_list_1"); \ - _type * tmp = (_type *)&start; \ - asm("":"+r"(tmp)); \ - tmp; \ -}) - -/** - * ll_end() - Point after last entry of last linker-generated array - * @_type: Data type of the entry - * - * This function returns ``(_type *)`` pointer after the very last entry of - * the very last linker-generated array. - * - * Since this macro defines the end of the linker-generated arrays, - * its leftmost index must be 3. - * - * Example: - * - * :: - * - * struct my_sub_cmd *msc = ll_end(struct my_sub_cmd); - */ -#define ll_end(_type) \ -({ \ - static char end[0] __aligned(4) __attribute__((unused)) \ - __section("__u_boot_list_3"); \ - _type * tmp = (_type *)&end; \ - asm("":"+r"(tmp)); \ - tmp; \ -}) - #endif /* __ASSEMBLY__ */ #endif /* __LINKER_LISTS_H__ */ diff --git a/include/mmc.h b/include/mmc.h index 51d3f2f8dd5..9509c9e9543 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -54,6 +54,7 @@ struct bd_info; #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) +#define MMC_VERSION_5_1B MAKE_MMC_VERSION(5, 1, 0xB) #define MMC_CAP(mode) (1 << mode) #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS)) diff --git a/include/part.h b/include/part.h index daebbbc2e68..15daacd7faa 100644 --- a/include/part.h +++ b/include/part.h @@ -461,6 +461,7 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt); #ifdef CONFIG_XPL_BUILD # define part_print_ptr(x) NULL # if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \ + defined(CONFIG_SPL_FS_SQUASHFS) || \ defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \ defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE) # define part_get_info_ptr(x) x @@ -704,6 +705,20 @@ int write_mbr_partitions(struct blk_desc *dev, int layout_mbr_partitions(struct disk_partition *p, int count, lbaint_t total_sectors); +/** + * part_get_mbr() - get the MBR partition record of a partition + * + * This function reads the MBR partition record for a given block + * device and partition number. + * + * @desc: block device descriptor + * @part: partition number for which to return the partition record + * @mbr: MBR partition record + * + * Return: 0 on success, otherwise error + */ +int part_get_mbr(struct blk_desc *desc, int part, dos_partition_t *mbr); + #endif #if CONFIG_IS_ENABLED(PARTITIONS) diff --git a/disk/part_dos.h b/include/part_dos.h similarity index 87% rename from disk/part_dos.h rename to include/part_dos.h index 50558224228..92956d53063 100644 --- a/disk/part_dos.h +++ b/include/part_dos.h @@ -30,8 +30,8 @@ typedef struct dos_partition { unsigned char end_head; /* end head */ unsigned char end_sector; /* end sector */ unsigned char end_cyl; /* end cylinder */ - unsigned char start4[4]; /* starting sector counting from 0 */ - unsigned char size4[4]; /* nr of sectors in partition */ -} dos_partition_t; + __le32 start_sect; /* starting sector counting from 0 */ + __le32 nr_sects; /* nr of sectors in partition */ +} __packed dos_partition_t; #endif /* _DISK_PART_DOS_H */ diff --git a/include/part_efi.h b/include/part_efi.h index fb402df6f13..2cea5088046 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -18,6 +18,7 @@ #define _DISK_PART_EFI_H #include +#include #define MSDOS_MBR_SIGNATURE 0xAA55 #define MSDOS_MBR_BOOT_CODE_SIZE 440 @@ -77,20 +78,6 @@ /* linux/include/efi.h */ typedef u16 efi_char16_t; -/* based on linux/include/genhd.h */ -struct partition { - u8 boot_ind; /* 0x80 - active */ - u8 head; /* starting head */ - u8 sector; /* starting sector */ - u8 cyl; /* starting cylinder */ - u8 sys_ind; /* What partition type */ - u8 end_head; /* end head */ - u8 end_sector; /* end sector */ - u8 end_cyl; /* end cylinder */ - __le32 start_sect; /* starting sector counting from 0 */ - __le32 nr_sects; /* nr of sectors in partition */ -} __packed; - /* based on linux/fs/partitions/efi.h */ typedef struct _gpt_header { __le64 signature; @@ -134,7 +121,7 @@ typedef struct _legacy_mbr { u8 boot_code[MSDOS_MBR_BOOT_CODE_SIZE]; __le32 unique_mbr_signature; __le16 unknown; - struct partition partition_record[4]; + dos_partition_t partition_record[4]; __le16 signature; } __packed legacy_mbr; @@ -153,7 +140,7 @@ struct efi_partition_info { u8 system; u8 reserved[7]; union { - struct partition mbr; + dos_partition_t mbr; gpt_entry gpt; } info; } __packed; diff --git a/include/power/cpcap.h b/include/power/cpcap.h index bb0e28cec55..b035b84840f 100644 --- a/include/power/cpcap.h +++ b/include/power/cpcap.h @@ -297,32 +297,21 @@ static const char * const cpcap_regulator_to_name[] = { }; static const u32 unknown_val_tbl[] = { 0, }; -static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000, - 812500, 825000, 837500, 850000, 862500, - 875000, 887500, 900000, 912500, 925000, - 937500, 950000, 962500, 975000, 987500, - 1000000, 1012500, 1025000, 1037500, - 1050000, 1062500, 1075000, 1087500, - 1100000, 1112500, 1125000, 1137500, - 1150000, 1162500, 1175000, 1187500, - 1200000, 1212500, 1225000, 1237500, - 1250000, 1262500, 1275000, 1287500, - 1300000, 1312500, 1325000, 1337500, - 1350000, 1362500, 1375000, 1387500, - 1400000, 1412500, 1425000, 1437500, - 1450000, 1462500, 1475000 }; -static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000, - 962500, 975000, 987500, 1000000, 1012500, - 1025000, 1037500, 1050000, 1062500, - 1075000, 1087500, 1100000, 1112500, - 1125000, 1137500, 1150000, 1162500, - 1175000, 1187500, 1200000, 1212500, - 1225000, 1237500, 1250000, 1262500, - 1275000, 1287500, 1300000, 1312500, - 1325000, 1337500, 1350000, 1362500, - 1375000, 1387500, 1400000, 1412500, - 1425000, 1437500, 1450000, 1462500, - 1475000 }; +static const u32 sw_val_tbl[] = { 600000, 612500, 625000, 637500, 650000, + 662500, 675000, 687500, 700000, 712500, + 725000, 737500, 750000, 762500, 775000, + 787500, 800000, 812500, 825000, 837500, + 850000, 862500, 875000, 887500, 900000, + 912500, 925000, 937500, 950000, 962500, + 975000, 987500, 1000000, 1012500, 1025000, + 1037500, 1050000, 1062500, 1075000, 1087500, + 1100000, 1112500, 1125000, 1137500, 1150000, + 1162500, 1175000, 1187500, 1200000, 1212500, + 1225000, 1237500, 1250000, 1262500, 1275000, + 1287500, 1300000, 1312500, 1325000, 1337500, + 1350000, 1362500, 1375000, 1387500, 1400000, + 1412500, 1425000, 1437500, 1450000, 1462500, + 1475000, }; static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 }; static const u32 sw5_val_tbl[] = { 0, 5050000 }; static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 }; @@ -361,13 +350,6 @@ struct cpcap_regulator_data { u32 mode_cntr; u32 volt_trans_time; /* in micro seconds */ u32 turn_on_time; /* in micro seconds */ - - /* - * Bit difference between lowest value in val_tbl and start of voltage - * table setting in cpcap. Use this for switchers that have many too - * many voltages to list in val_tbl. - */ - u32 bit_offset_from_cpcap_lowest_voltage; }; #endif /* _CPCAP_H_ */ diff --git a/include/power/mt6357.h b/include/power/mt6357.h new file mode 100644 index 00000000000..b7ee9d64386 --- /dev/null +++ b/include/power/mt6357.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson + */ + +#ifndef _REGULATOR_MT6357_H_ +#define _REGULATOR_MT6357_H_ + +#define MT6357_REGULATOR_DRIVER "mt6357_regulator" + +enum { + /* Bucks */ + MT6357_ID_VCORE, + MT6357_ID_VMODEM, + MT6357_ID_VPA, + MT6357_ID_VPROC, + MT6357_ID_VS1, + + /* LDOs */ + MT6357_ID_VAUX18, + MT6357_ID_VAUD28, + MT6357_ID_VCAMA, + MT6357_ID_VCAMD, + MT6357_ID_VCAMIO, + MT6357_ID_VCN18, + MT6357_ID_VCN28, + MT6357_ID_VCN33_BT, + MT6357_ID_VCN33_WIFI, + MT6357_ID_VDRAM, + MT6357_ID_VEFUSE, + MT6357_ID_VEMC, + MT6357_ID_VFE28, + MT6357_ID_VIBR, + MT6357_ID_VIO18, + MT6357_ID_VIO28, + MT6357_ID_VLDO28, + MT6357_ID_VMC, + MT6357_ID_VMCH, + MT6357_ID_VRF12, + MT6357_ID_VRF18, + MT6357_ID_VSIM1, + MT6357_ID_VSIM2, + MT6357_ID_VSRAM_OTHERS, + MT6357_ID_VSRAM_PROC, + MT6357_ID_VUSB33, + MT6357_ID_VXO22, +}; + +/* PMIC Registers */ +#define MT6357_BUCK_TOP_CLK_CON0 0x140c +#define MT6357_BUCK_TOP_CLK_HWEN_CON0 0x1412 +#define MT6357_BUCK_TOP_CLK_MISC_CON0 0x1418 +#define MT6357_BUCK_TOP_INT_CON0 0x141a +#define MT6357_BUCK_TOP_INT_MASK_CON0 0x1420 +#define MT6357_BUCK_TOP_SLP_CON0 0x142c +#define MT6357_BUCK_TOP_OC_CON0 0x1434 +#define MT6357_BUCK_TOP_K_CON0 0x1436 +#define MT6357_BUCK_VPROC_CON0 0x1488 +#define MT6357_BUCK_VPROC_DBG0 0x14a2 +#define MT6357_BUCK_VPROC_ELR0 0x14aa +#define MT6357_BUCK_VCORE_CON0 0x1508 +#define MT6357_BUCK_VCORE_DBG0 0x1522 +#define MT6357_BUCK_VCORE_ELR0 0x152a +#define MT6357_BUCK_VMODEM_CON0 0x1588 +#define MT6357_BUCK_VMODEM_DBG0 0x15a2 +#define MT6357_BUCK_VMODEM_ELR0 0x15aa +#define MT6357_BUCK_VS1_CON0 0x1608 +#define MT6357_BUCK_VS1_DBG0 0x1622 +#define MT6357_BUCK_VS1_ELR0 0x1632 +#define MT6357_BUCK_VPA_CON0 0x1688 +#define MT6357_BUCK_VPA_CON1 0x168a +#define MT6357_BUCK_VPA_DBG0 0x1692 +#define MT6357_BUCK_VPA_DLC_CON0 0x1698 +#define MT6357_BUCK_VPA_MSFG_CON0 0x169e +#define MT6357_LDO_TOP_CLK_DCM_CON0 0x188c +#define MT6357_LDO_TOP_CLK_VIO28_CON0 0x188e +#define MT6357_LDO_TOP_CLK_VIO18_CON0 0x1890 +#define MT6357_LDO_TOP_CLK_VAUD28_CON0 0x1892 +#define MT6357_LDO_TOP_CLK_VDRAM_CON0 0x1894 +#define MT6357_LDO_TOP_CLK_VSRAM_PROC_CON0 0x1896 +#define MT6357_LDO_TOP_CLK_VSRAM_OTHERS_CON0 0x1898 +#define MT6357_LDO_TOP_CLK_VAUX18_CON0 0x189a +#define MT6357_LDO_TOP_CLK_VUSB33_CON0 0x189c +#define MT6357_LDO_TOP_CLK_VEMC_CON0 0x189e +#define MT6357_LDO_TOP_CLK_VXO22_CON0 0x18a0 +#define MT6357_LDO_TOP_CLK_VSIM1_CON0 0x18a2 +#define MT6357_LDO_TOP_CLK_VSIM2_CON0 0x18a4 +#define MT6357_LDO_TOP_CLK_VCAMD_CON0 0x18a6 +#define MT6357_LDO_TOP_CLK_VCAMIO_CON0 0x18a8 +#define MT6357_LDO_TOP_CLK_VEFUSE_CON0 0x18aa +#define MT6357_LDO_TOP_CLK_VCN33_CON0 0x18ac +#define MT6357_LDO_TOP_CLK_VCN18_CON0 0x18ae +#define MT6357_LDO_TOP_CLK_VCN28_CON0 0x18b0 +#define MT6357_LDO_TOP_CLK_VIBR_CON0 0x18b2 +#define MT6357_LDO_TOP_CLK_VFE28_CON0 0x18b4 +#define MT6357_LDO_TOP_CLK_VMCH_CON0 0x18b6 +#define MT6357_LDO_TOP_CLK_VMC_CON0 0x18b8 +#define MT6357_LDO_TOP_CLK_VRF18_CON0 0x18ba +#define MT6357_LDO_TOP_CLK_VLDO28_CON0 0x18bc +#define MT6357_LDO_TOP_CLK_VRF12_CON0 0x18be +#define MT6357_LDO_TOP_CLK_VCAMA_CON0 0x18c0 +#define MT6357_LDO_TOP_CLK_TREF_CON0 0x18c2 +#define MT6357_LDO_TOP_INT_CON0 0x18c4 +#define MT6357_LDO_TOP_INT_MASK_CON0 0x18d0 +#define MT6357_LDO_TEST_CON0 0x18e4 +#define MT6357_LDO_TOP_WDT_CON0 0x18e6 +#define MT6357_LDO_TOP_RSV_CON0 0x18e8 +#define MT6357_LDO_VXO22_CON0 0x1908 +#define MT6357_LDO_VAUX18_CON0 0x191c +#define MT6357_LDO_VAUD28_CON0 0x1930 +#define MT6357_LDO_VIO28_CON0 0x1944 +#define MT6357_LDO_VIO18_CON0 0x1958 +#define MT6357_LDO_VDRAM_CON0 0x196c +#define MT6357_LDO_VEMC_CON0 0x1988 +#define MT6357_LDO_VUSB33_CON0_0 0x199c +#define MT6357_LDO_VSRAM_PROC_CON0 0x19b2 +#define MT6357_LDO_VSRAM_PROC_DBG0 0x19cc +#define MT6357_LDO_VSRAM_OTHERS_CON0 0x19d0 +#define MT6357_LDO_VSRAM_OTHERS_DBG0 0x19ea +#define MT6357_LDO_VSRAM_WDT_DBG0 0x19f6 +#define MT6357_LDO_VSRAM_CON0 0x19fa +#define MT6357_LDO_VSRAM_CON1 0x19fc +#define MT6357_LDO_VFE28_CON0 0x1a08 +#define MT6357_LDO_VRF18_CON0 0x1a1c +#define MT6357_LDO_VRF12_CON0 0x1a30 +#define MT6357_LDO_VEFUSE_CON0 0x1a44 +#define MT6357_LDO_VCN18_CON0 0x1a58 +#define MT6357_LDO_VCAMA_CON0 0x1a6c +#define MT6357_LDO_VCAMD_CON0 0x1a88 +#define MT6357_LDO_VCAMIO_CON0 0x1a9c +#define MT6357_LDO_VMC_CON0 0x1ab0 +#define MT6357_LDO_VMCH_CON0 0x1ac4 +#define MT6357_LDO_VSIM1_CON0 0x1ad8 +#define MT6357_LDO_VSIM2_CON0 0x1aec +#define MT6357_LDO_VIBR_CON0 0x1b08 +#define MT6357_LDO_VCN33_CON0_0 0x1b1c +#define MT6357_LDO_VCN33_CON0_1 0x1b2a +#define MT6357_LDO_VLDO28_CON0_0 0x1b32 +#define MT6357_LDO_GOFF2_RSV_CON0 0x1b48 +#define MT6357_LDO_VCN28_CON0 0x1b88 +#define MT6357_LDO_TREF_CON0 0x1b9e +#define MT6357_LDO_GOFF3_RSV_CON0 0x1bae +#define MT6357_VXO22_ANA_CON0 0x1c18 +#define MT6357_VCN33_ANA_CON0 0x1c1c +#define MT6357_VEMC_ANA_CON0 0x1c20 +#define MT6357_VLDO28_ANA_CON0 0x1c24 +#define MT6357_VIBR_ANA_CON0 0x1c2c +#define MT6357_VSIM1_ANA_CON0 0x1c30 +#define MT6357_VSIM2_ANA_CON0 0x1c34 +#define MT6357_VMCH_ANA_CON0 0x1c38 +#define MT6357_VMC_ANA_CON0 0x1c3c +#define MT6357_VUSB33_ANA_CON0 0x1c88 +#define MT6357_VCAMA_ANA_CON0 0x1c8c +#define MT6357_VEFUSE_ANA_CON0 0x1c90 +#define MT6357_VCAMD_ANA_CON0 0x1c94 +#define MT6357_VDRAM_ELR_2 0x1cac + +#endif diff --git a/include/power/mt6359.h b/include/power/mt6359.h new file mode 100644 index 00000000000..1e0380e87b0 --- /dev/null +++ b/include/power/mt6359.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen + */ + +#ifndef __MT6359_H_ +#define __MT6359_H_ + +#define MT6359_REGULATOR_DRIVER "mt6359_regulator" + +enum { + MT6359_ID_VS1 = 0, + MT6359_ID_VGPU11, + MT6359_ID_VMODEM, + MT6359_ID_VPU, + MT6359_ID_VCORE, + MT6359_ID_VS2, + MT6359_ID_VPA, + MT6359_ID_VPROC2, + MT6359_ID_VPROC1, + MT6359_ID_VCORE_SSHUB, + MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB, + MT6359_ID_VAUD18 = 10, + MT6359_ID_VSIM1, + MT6359_ID_VIBR, + MT6359_ID_VRF12, + MT6359_ID_VUSB, + MT6359_ID_VSRAM_PROC2, + MT6359_ID_VIO18, + MT6359_ID_VCAMIO, + MT6359_ID_VCN18, + MT6359_ID_VFE28, + MT6359_ID_VCN13, + MT6359_ID_VCN33_1_BT, + MT6359_ID_VCN33_1_WIFI, + MT6359_ID_VAUX18, + MT6359_ID_VSRAM_OTHERS, + MT6359_ID_VEFUSE, + MT6359_ID_VXO22, + MT6359_ID_VRFCK, + MT6359_ID_VBIF28, + MT6359_ID_VIO28, + MT6359_ID_VEMC, + MT6359_ID_VCN33_2_BT, + MT6359_ID_VCN33_2_WIFI, + MT6359_ID_VA12, + MT6359_ID_VA09, + MT6359_ID_VRF18, + MT6359_ID_VSRAM_MD, + MT6359_ID_VUFS, + MT6359_ID_VM18, + MT6359_ID_VBBCK, + MT6359_ID_VSRAM_PROC1, + MT6359_ID_VSIM2, + MT6359_ID_VSRAM_OTHERS_SSHUB, + MT6359_ID_RG_MAX, +}; + + +/* PMIC Registers */ +#define MT6359_BUCK_VPU_CON0 0x1488 +#define MT6359_BUCK_VPU_DBG1 0x14a8 +#define MT6359_BUCK_VPU_ELR0 0x14ac +#define MT6359_BUCK_VCORE_CON0 0x1508 +#define MT6359_BUCK_VCORE_DBG1 0x1528 +#define MT6359_BUCK_VGPU11_CON0 0x1588 +#define MT6359_BUCK_VGPU11_DBG1 0x15a8 +#define MT6359_BUCK_VMODEM_CON0 0x1688 +#define MT6359_BUCK_VMODEM_DBG1 0x16a8 +#define MT6359_BUCK_VMODEM_ELR0 0x16ae +#define MT6359_BUCK_VPROC1_CON0 0x1708 +#define MT6359_BUCK_VPROC1_DBG1 0x1728 +#define MT6359_BUCK_VPROC1_ELR0 0x172e +#define MT6359_BUCK_VPROC2_CON0 0x1788 +#define MT6359_BUCK_VPROC2_DBG1 0x17a8 +#define MT6359_BUCK_VPROC2_ELR0 0x17b2 +#define MT6359_BUCK_VS1_CON0 0x1808 +#define MT6359_BUCK_VS1_DBG1 0x1828 +#define MT6359_BUCK_VS1_ELR0 0x1834 +#define MT6359_BUCK_VS2_CON0 0x1888 +#define MT6359_BUCK_VS2_DBG1 0x18a8 +#define MT6359_BUCK_VS2_ELR0 0x18b4 +#define MT6359_BUCK_VPA_CON0 0x1908 +#define MT6359_BUCK_VPA_CON1 0x190e +#define MT6359_BUCK_VPA_DBG1 0x1916 +#define MT6359_VGPUVCORE_ANA_CON2 0x198e +#define MT6359_VGPUVCORE_ANA_CON13 0x19a4 +#define MT6359_VPROC1_ANA_CON3 0x19b2 +#define MT6359_VPROC2_ANA_CON3 0x1a0e +#define MT6359_VMODEM_ANA_CON3 0x1a1a +#define MT6359_VPU_ANA_CON3 0x1a26 +#define MT6359_VS1_ANA_CON0 0x1a2c +#define MT6359_VS2_ANA_CON0 0x1a34 +#define MT6359_VPA_ANA_CON0 0x1a3c + +#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_SHIFT 1 +#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1 +#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0 +#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1 +#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1 +#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1 +#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1 +#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1 +#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1 +#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0 +#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1 +#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1 +#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0 +#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1 +#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1 +#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0 +#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_SHIFT 1 +#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1 +#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0 +#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_SHIFT 1 +#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1 +#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0 +#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_SHIFT 1 +#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1 +#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F +#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0 +#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1 +#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2 +#define MT6359_RG_VGPU11_FCCM_SHIFT 9 +#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13 +#define MT6359_RG_VCORE_FCCM_SHIFT 5 +#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3 +#define MT6359_RG_VPROC1_FCCM_SHIFT 1 +#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3 +#define MT6359_RG_VPROC2_FCCM_SHIFT 1 +#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3 +#define MT6359_RG_VMODEM_FCCM_SHIFT 1 +#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3 +#define MT6359_RG_VPU_FCCM_SHIFT 1 +#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0 +#define MT6359_RG_VS1_FPWM_SHIFT 3 +#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0 +#define MT6359_RG_VS2_FPWM_SHIFT 3 +#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0 +#define MT6359_RG_VPA_MODESET_SHIFT 1 +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0 +#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15 +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 +#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8 +#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM1_VOSEL_MASK 0xF +#define MT6359_RG_VSIM1_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM2_VOSEL_MASK 0xF +#define MT6359_RG_VSIM2_VOSEL_SHIFT 8 +#define MT6359_RG_VIO28_VOSEL_MASK 0xF +#define MT6359_RG_VIO28_VOSEL_SHIFT 8 +#define MT6359_RG_VIBR_VOSEL_MASK 0xF +#define MT6359_RG_VIBR_VOSEL_SHIFT 8 +#define MT6359_RG_VRF18_VOSEL_MASK 0xF +#define MT6359_RG_VRF18_VOSEL_SHIFT 8 +#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF +#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8 +#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF +#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8 +#define MT6359_RG_VIO18_VOSEL_MASK 0xF +#define MT6359_RG_VIO18_VOSEL_SHIFT 8 +#define MT6359_RG_VM18_VOSEL_MASK 0xF +#define MT6359_RG_VM18_VOSEL_SHIFT 8 +#define MT6359_RG_VUFS_VOSEL_MASK 0xF +#define MT6359_RG_VUFS_VOSEL_SHIFT 8 +#define MT6359_RG_VRF12_VOSEL_MASK 0xF +#define MT6359_RG_VRF12_VOSEL_SHIFT 8 +#define MT6359_RG_VCN13_VOSEL_MASK 0xF +#define MT6359_RG_VCN13_VOSEL_SHIFT 8 +#define MT6359_RG_VA09_VOSEL_MASK 0xF +#define MT6359_RG_VA09_VOSEL_SHIFT 8 +#define MT6359_RG_VA12_VOSEL_MASK 0xF +#define MT6359_RG_VA12_VOSEL_SHIFT 8 +#define MT6359_RG_VXO22_VOSEL_MASK 0xF +#define MT6359_RG_VXO22_VOSEL_SHIFT 8 +#define MT6359_RG_VRFCK_VOSEL_MASK 0xF +#define MT6359_RG_VRFCK_VOSEL_SHIFT 8 + +#endif diff --git a/include/power/mt6359p.h b/include/power/mt6359p.h new file mode 100644 index 00000000000..506b5d38c68 --- /dev/null +++ b/include/power/mt6359p.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen + */ + +#ifndef __MT6359P_H_ +#define __MT6359P_H_ + +#define MT6359P_CHIP_VER 0x5930 + +/* PMIC Registers */ +#define MT6359P_HWCID 0x8 +#define MT6359P_TOP_TRAP 0x50 +#define MT6359P_TOP_TMA_KEY 0x3a8 +#define MT6359P_BUCK_VCORE_ELR0 0x152c +#define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa +#define MT6359P_BUCK_VGPU11_ELR0 0x15b4 +#define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44 +#define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46 +#define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48 +#define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a +#define MT6359P_LDO_VEMC_ELR_0 0x1b4c +#define MT6359P_LDO_VFE28_CON0 0x1b88 +#define MT6359P_LDO_VFE28_MON 0x1b8c +#define MT6359P_LDO_VXO22_CON0 0x1b9a +#define MT6359P_LDO_VXO22_MON 0x1b9e +#define MT6359P_LDO_VRF18_CON0 0x1bac +#define MT6359P_LDO_VRF18_MON 0x1bb0 +#define MT6359P_LDO_VRF12_CON0 0x1bbe +#define MT6359P_LDO_VRF12_MON 0x1bc2 +#define MT6359P_LDO_VEFUSE_CON0 0x1bd0 +#define MT6359P_LDO_VEFUSE_MON 0x1bd4 +#define MT6359P_LDO_VCN33_1_CON0 0x1be2 +#define MT6359P_LDO_VCN33_1_MON 0x1be6 +#define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4 +#define MT6359P_LDO_VCN33_2_CON0 0x1c08 +#define MT6359P_LDO_VCN33_2_MON 0x1c0c +#define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a +#define MT6359P_LDO_VCN13_CON0 0x1c1c +#define MT6359P_LDO_VCN13_MON 0x1c20 +#define MT6359P_LDO_VCN18_CON0 0x1c2e +#define MT6359P_LDO_VCN18_MON 0x1c32 +#define MT6359P_LDO_VA09_CON0 0x1c40 +#define MT6359P_LDO_VA09_MON 0x1c44 +#define MT6359P_LDO_VCAMIO_CON0 0x1c52 +#define MT6359P_LDO_VCAMIO_MON 0x1c56 +#define MT6359P_LDO_VA12_CON0 0x1c64 +#define MT6359P_LDO_VA12_MON 0x1c68 +#define MT6359P_LDO_VAUX18_CON0 0x1c88 +#define MT6359P_LDO_VAUX18_MON 0x1c8c +#define MT6359P_LDO_VAUD18_CON0 0x1c9a +#define MT6359P_LDO_VAUD18_MON 0x1c9e +#define MT6359P_LDO_VIO18_CON0 0x1cac +#define MT6359P_LDO_VIO18_MON 0x1cb0 +#define MT6359P_LDO_VEMC_CON0 0x1cbe +#define MT6359P_LDO_VEMC_MON 0x1cc2 +#define MT6359P_LDO_VSIM1_CON0 0x1cd0 +#define MT6359P_LDO_VSIM1_MON 0x1cd4 +#define MT6359P_LDO_VSIM2_CON0 0x1ce2 +#define MT6359P_LDO_VSIM2_MON 0x1ce6 +#define MT6359P_LDO_VUSB_CON0 0x1d08 +#define MT6359P_LDO_VUSB_MON 0x1d0c +#define MT6359P_LDO_VRFCK_CON0 0x1d1c +#define MT6359P_LDO_VRFCK_MON 0x1d20 +#define MT6359P_LDO_VBBCK_CON0 0x1d2e +#define MT6359P_LDO_VBBCK_MON 0x1d32 +#define MT6359P_LDO_VBIF28_CON0 0x1d40 +#define MT6359P_LDO_VBIF28_MON 0x1d44 +#define MT6359P_LDO_VIBR_CON0 0x1d52 +#define MT6359P_LDO_VIBR_MON 0x1d56 +#define MT6359P_LDO_VIO28_CON0 0x1d64 +#define MT6359P_LDO_VIO28_MON 0x1d68 +#define MT6359P_LDO_VM18_CON0 0x1d88 +#define MT6359P_LDO_VM18_MON 0x1d8c +#define MT6359P_LDO_VUFS_CON0 0x1d9a +#define MT6359P_LDO_VUFS_MON 0x1d9e +#define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88 +#define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c +#define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8 +#define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac +#define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08 +#define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c +#define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28 +#define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e +#define MT6359P_LDO_VSRAM_MD_MON 0x1f32 +#define MT6359P_VCN33_1_ANA_CON0 0x1f98 +#define MT6359P_VCN33_2_ANA_CON0 0x1f9c +#define MT6359P_VSIM1_ANA_CON0 0x1fa2 +#define MT6359P_VSIM2_ANA_CON0 0x1fa6 +#define MT6359P_VIO28_ANA_CON0 0x1faa +#define MT6359P_VIBR_ANA_CON0 0x1fae +#define MT6359P_VFE28_ELR_4 0x1fc0 +#define MT6359P_VRF18_ANA_CON0 0x2008 +#define MT6359P_VEFUSE_ANA_CON0 0x200c +#define MT6359P_VCAMIO_ANA_CON0 0x2014 +#define MT6359P_VIO18_ANA_CON0 0x201c +#define MT6359P_VM18_ANA_CON0 0x2020 +#define MT6359P_VUFS_ANA_CON0 0x2024 +#define MT6359P_VRF12_ANA_CON0 0x202a +#define MT6359P_VCN13_ANA_CON0 0x202e +#define MT6359P_VRF18_ELR_3 0x204e +#define MT6359P_VXO22_ANA_CON0 0x2088 +#define MT6359P_VRFCK_ANA_CON0 0x208c +#define MT6359P_VBBCK_ANA_CON0 0x2096 + +#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4 +#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR +#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR +#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR +#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR +#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0 +#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF +#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0 +#define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0 +#define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON +#define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0 +#define MT6359P_RG_LDO_VXO22_EN_SHIFT 0 +#define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON +#define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0 +#define MT6359P_RG_LDO_VRF18_EN_SHIFT 0 +#define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON +#define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0 +#define MT6359P_RG_LDO_VRF12_EN_SHIFT 0 +#define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON +#define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0 +#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0 +#define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON +#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0 +#define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON +#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW +#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15 +#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0 +#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0 +#define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON +#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW +#define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0 +#define MT6359P_RG_LDO_VCN13_EN_SHIFT 0 +#define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON +#define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0 +#define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON +#define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0 +#define MT6359P_RG_LDO_VA09_EN_SHIFT 0 +#define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON +#define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0 +#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0 +#define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON +#define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0 +#define MT6359P_RG_LDO_VA12_EN_SHIFT 0 +#define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON +#define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0 +#define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON +#define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0 +#define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON +#define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0 +#define MT6359P_RG_LDO_VIO18_EN_SHIFT 0 +#define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON +#define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0 +#define MT6359P_RG_LDO_VEMC_EN_SHIFT 0 +#define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON +#define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0 +#define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0 +#define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON +#define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0 +#define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0 +#define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON +#define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0 +#define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON +#define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0 +#define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0 +#define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON +#define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0 +#define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0 +#define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON +#define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0 +#define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON +#define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0 +#define MT6359P_RG_LDO_VIBR_EN_SHIFT 0 +#define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON +#define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0 +#define MT6359P_RG_LDO_VIO28_EN_SHIFT 0 +#define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON +#define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0 +#define MT6359P_RG_LDO_VM18_EN_SHIFT 0 +#define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON +#define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0 +#define MT6359P_RG_LDO_VUFS_EN_SHIFT 0 +#define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON +#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0 +#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON +#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0 +#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON +#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0 +#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0 +#define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON +#define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0 +#define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0 +#define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0 +#define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0 +#define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0 +#define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0 +#define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0 +#define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0 +#define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0 +#define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0 +#define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0 +#define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0 +#define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0 +#define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0 +#define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VRF18_ELR_3 +#define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4 +#define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0 +#define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_MASK 0xF +#define MT6359P_RG_VBBCK_VOSEL_SHIFT 4 +#define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP +#define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY + +#define MT6359P_TMA_KEY 0x9CA6 + +#endif diff --git a/include/relocate.h b/include/relocate.h index 8ca25e1105e..331be138728 100644 --- a/include/relocate.h +++ b/include/relocate.h @@ -8,9 +8,7 @@ #define _RELOCATE_H_ #ifndef USE_HOSTCC -#include -DECLARE_GLOBAL_DATA_PTR; #endif /** diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index 9b36d3ae67b..c40b448bcba 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -52,7 +52,7 @@ struct scmi_agent_priv { #if IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) struct udevice *voltagedom_dev; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) struct udevice *pinctrl_dev; #endif #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_80) diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index ecab021b472..a8fd0a5a729 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -54,7 +54,8 @@ enum scmi_discovery_id { }; enum scmi_imx_misc_message_id { - SCMI_MISC_ROM_PASSOVER_GET = 0x7 + SCMI_MISC_ROM_PASSOVER_GET = 0x7, + SCMI_MISC_DDR_INFO_GET = 0x22, }; /* @@ -1088,7 +1089,14 @@ struct scmi_voltd_level_get_out { /* SCMI Pinctrl Protocol */ enum scmi_pinctrl_message_id { - SCMI_MSG_PINCTRL_CONFIG_SET = 0x6 + SCMI_PINCTRL_ATTRIBUTES = 0x3, + SCMI_PINCTRL_LIST_ASSOCIATIONS = 0x4, + SCMI_PINCTRL_SETTINGS_GET = 0x5, + SCMI_PINCTRL_SETTINGS_CONFIGURE = 0x6, + SCMI_PINCTRL_REQUEST = 0x7, + SCMI_PINCTRL_RELEASE = 0x8, + SCMI_PINCTRL_NAME_GET = 0x9, + SCMI_PINCTRL_SET_PERMISSIONS = 0xA, }; struct scmi_pin_config { @@ -1100,14 +1108,14 @@ struct scmi_pin_config { * struct scmi_pinctrl_config_set_in - Message payload for PAD_CONFIG_SET command * @identifier: Identifier for the pin or group. * @function_id: Identifier for the function selected to be enabled - * for the selected pin or group. This field is set to - * 0xFFFFFFFF if no function should be enabled by the - * pin or group. + * for the selected pin or group. This field is set to + * 0xFFFFFFFF if no function should be enabled by the + * pin or group. * @attributes: Bits[31:11] Reserved, must be zero. - * Bit[10] Function valid. - * Bits[9:2] Number of configurations to set. - * Bits[1:0] Selector: Whether the identifier field - * refers to a pin or a group. + * Bit[10] Function valid. + * Bits[9:2] Number of configurations to set. + * Bits[1:0] Selector: Whether the identifier field + * refers to a pin or a group. * @configs: Array of configurations. */ struct scmi_pinctrl_config_set_in { @@ -1139,4 +1147,360 @@ struct scmi_perf_in { struct scmi_perf_out { s32 status; }; + +#define SCMI_PIN_NAME_LEN 16 + +struct pin_info { + char name[SCMI_PIN_NAME_LEN]; +}; + +struct group_info { + char name[SCMI_PIN_NAME_LEN]; + u16 *pins; + u32 num_pins; +}; + +struct function_info { + char name[SCMI_PIN_NAME_LEN]; + u16 *groups; + u32 num_groups; +}; + +/* This is used by both the SCMI pinctrl and gpio drivers */ +struct pinctrl_scmi_priv { + int num_pins; + struct pin_info *pin_info; + int num_groups; + struct group_info *group_info; + int num_functions; + struct function_info *function_info; +}; + +/* SCMI Pinctrl selector type */ +enum select_type { + SCMI_PIN, + SCMI_GROUP, + SCMI_FUNCTION, +}; + +/** + * struct scmi_pinctrl_protocol_attrs_out - Response to SCMI_PROTOCOL_ATTRIBUTES + * command. + * @status: SCMI command status + * @attr_low: Number of pins and groups + * @attr_high: Number of functions + */ +struct scmi_pinctrl_protocol_attrs_out { + s32 status; + u32 attr_low; + u32 attr_high; +}; + +/** + * struct scmi_pinctrl_attrs_in - Parameters for SCMI_PINCTRL_ATTRIBUTES command + * @id: Identifier for pin, group or function + * @select_type: Pin, group or function + */ +struct scmi_pinctrl_attrs_in { + u32 id; + u32 select_type; +}; + +/** + * struct scmi_pinctrl_attrs_out - Response to SCMI_PINCTRL_ATTRIBUTES command + * @status: SCMI command status + * @attr: GPIO, number of pins or groups + * @name: Name of pin, group or function + */ +struct scmi_pinctrl_attrs_out { + s32 status; + u32 attr; + u8 name[SCMI_PIN_NAME_LEN]; +}; + +/** + * struct scmi_pinctrl_list_associations_in - Parameters for + * SCMI_PINCTRL_LIST_ASSOCIATIONS command + * @id: Identifier for group or function + * @select_type: Group or function + * @index: Index within the group or function + */ +struct scmi_pinctrl_list_associations_in { + u32 id; + u32 select_type; + u32 index; +}; + +/** + * struct scmi_pinctrl_list_associations_out - Response to + * SCMI_PINCTRL_LIST_ASSOCIATIONS command + * @status: SCMI command status + * @flags: Number of items returned and number still remaining + * @array: List of groups or pins + */ +struct scmi_pinctrl_list_associations_out { + s32 status; + u32 flags; + u16 array[]; +}; + +/** + * struct scmi_pinctrl_settings_get_in - Parameters for + * SCMI_PINCTRL_SETTINGS_GET command + * @id: Identifier for pin or group + * @attr: Config flag: one setting, function or all settings + * Selector: Pin or Group + * Skip: Number of config types to skip + * Config type: Type of config to read + */ +struct scmi_pinctrl_settings_get_in { + u32 id; + u32 attr; +}; + +#define SCMI_PINCTRL_CONFIG_SETTINGS_ALL -2u /* This is an internal magic number */ +#define SCMI_PINCTRL_FUNCTION_NONE 0xFFFFFFFF + +/** + * struct scmi_pinctrl_settings_get_out - Response to SCMI_PINCTRL_SETTINGS_GET + * command + * @status: SCMI command status + * @function_selected: The function enabled by the pin or group + * @num_configs: The number of settings returned and number still remaining + * @configs: The list of config data + */ +struct scmi_pinctrl_settings_get_out { + s32 status; + u32 function_selected; + u32 num_configs; + u32 configs[]; +}; + +/** + * struct scmi_pinctrl_settings_configure_in - Parameters for + * SCMI_PINCTRL_SETTINGS_CONFIGURE command + * @id: Identifier for pin or group + * @function_id: The function to enable for this pin or group (optional) + * @attr: Function id: Set the function or not + * Number of configs to set + * Selector: pin or group + * @configs: List of config type value pairs + */ +struct scmi_pinctrl_settings_configure_in { + u32 id; + u32 function_id; + u32 attr; + u32 configs[]; +}; + +/** + * struct scmi_pinctrl_settings_configure_out - Response to + * SCMI_PINCTRL_SETTINGS_CONFIGURE command + * @status: SCMI command status + */ +struct scmi_pinctrl_settings_configure_out { + s32 status; +}; + +/** + * struct scmi_pinctrl_request_in - Parameters for SCMI_PINCTRL_REQUEST command + * @id: Identifier for pin or group + * @flags: Pin, group or function + */ +struct scmi_pinctrl_request_in { + u32 id; + u32 flags; +}; + +/** + * struct scmi_pinctrl_request_out - Response to SCMI_PINCTRL_REQUEST command + * @status: SCMI command status + */ +struct scmi_pinctrl_request_out { + s32 status; +}; + +/** + * struct scmi_pinctrl_release_in - Parameters for SCMI_PINCTRL_RELEASE command + * @id: Identifier for pin or group + * @flags: Pin, group or function + */ +struct scmi_pinctrl_release_in { + u32 id; + u32 flags; +}; + +/** + * struct scmi_pinctrl_release_out - Response to SCMI_PINCTRL_RELEASE command + * @status: SCMI command status + */ +struct scmi_pinctrl_release_out { + s32 status; +}; + +/* SCMI Pinctrl Config Types */ +enum scmi_config_type { + SCMI_PIN_DEFUALT = 0, + SCMI_PIN_BIAS_BUS_HOLD = 1, + SCMI_PIN_BIAS_DISABLE = 2, + SCMI_PIN_BIAS_HIGH_IMPEDANCE = 3, + SCMI_PIN_BIAS_PULL_UP = 4, + SCMI_PIN_BIAS_PULL_DEFAULT = 5, + SCMI_PIN_BIAS_PULL_DOWN = 6, + SCMI_PIN_DRIVE_OPEN_DRAIN = 7, + SCMI_PIN_DRIVE_OPEN_SOURCE = 8, + SCMI_PIN_DRIVE_PUSH_PULL = 9, + SCMI_PIN_DRIVE_STRENGTH = 10, + SCMI_PIN_INPUT_DEBOUNCE = 11, + SCMI_PIN_INPUT_MODE = 12, + SCMI_PIN_PULL_MODE = 13, + SCMI_PIN_INPUT_VALUE = 14, + SCMI_PIN_INPUT_SCHMITT = 15, + SCMI_PIN_LOW_POWER_MODE = 16, + SCMI_PIN_OUTPUT_MODE = 17, + SCMI_PIN_OUTPUT_VALUE = 18, + SCMI_PIN_POWER_SOURCE = 19, + SCMI_PIN_SLEW_RATE = 20, +}; + +/** + * scmi_pinctrl_protocol_attrs - get pinctrl information + * @dev: SCMI protocol device + * @num_pins: Number of pins + * @num_groups: Number of groups + * @num_functions: Number of functions + * + * Obtain the number of pins, groups and functions. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_protocol_attrs(struct udevice *dev, int *num_pins, + int *num_groups, int *num_functions); + +/** + * scmi_pinctrl_attrs - get information for a specific pin, group or function + * @dev: SCMI protocol device + * @select_type: pin, group or function + * @selector: id of pin, group or function + * @gpio: set to true if the pin or group supports gpio + * @count: number of groups in function or pins in group + * @name: name of pin, group or function + * + * Obtain information about a specific pin, group or function. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_attrs(struct udevice *dev, enum select_type select_type, + unsigned int selector, bool *gpio, unsigned int *count, + char *name); + +/** + * scmi_pinctrl_request - claim a pin or group + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * + * Claim ownership of a pin or group. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_request(struct udevice *dev, enum select_type select_type, + unsigned int selector); +/** + * scmi_pinctrl_release - release a claimed pin or group + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * + * Release a pin or group that you previously claimed. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_release(struct udevice *dev, enum select_type select_type, + unsigned int selector); + +/** + * scmi_pinctrl_list_associations - get list of pins in group or groups in function + * @dev: SCMI protocol device + * @select_type: group or function + * @selector: id of group or function + * @output: list of groups in function or pins in group + * @num_out: How many groups are in the function or pins in the group + * + * Obtain the list of groups or pins in the function or group respectively. + * We know how many items will be in the list from calling scmi_pinctrl_attrs(). + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_list_associations(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + unsigned short *output, + unsigned short num_out); + +/** + * scmi_pinctrl_settings_get_one - get a configuration setting + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @config_type: Which configuration type to read + * @value: returned configuration value + * + * This reads a single config setting. Most importantly the + * SCMI_PIN_INPUT_VALUE setting is used to read from a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_get_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 config_type, u32 *value); + +/** + * scmi_pinctrl_settings_configure - set multiple configuration settings + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @num_configs: number of settings to set + * @configs: Config type and value pairs + * + * Configure multiple settings at once to reduce overhead. The + * SCMI_PIN_OUTPUT_VALUE setting is used to write to a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_configure(struct udevice *dev, enum select_type select_type, + unsigned int selector, u16 num_configs, + u32 *configs); + +/** + * scmi_pinctrl_settings_configure_one - set a configuration setting + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @param: The setting type to configure + * @argument: The value of the configuration + * + * Configure a single setting. The SCMI_PIN_OUTPUT_VALUE setting is used to + * write to a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_configure_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 param, u32 argument); + +/** + * scmi_pinctrl_set_function - set the function for a group or pin + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @function_id: id of the function + * + * Set the function for a group or pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_set_function(struct udevice *dev, enum select_type select_type, + unsigned int selector, u32 function_id); + #endif /* _SCMI_PROTOCOLS_H */ diff --git a/include/smbios.h b/include/smbios.h index f2f7483bce5..39090d3ba18 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -110,10 +110,42 @@ struct __packed smbios_type0 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +#define SMBIOS_TYPE0_LENGTH_V24 0x18 +#define SMBIOS_TYPE0_LENGTH_V31 0x1a + #define SMBIOS_TYPE1_LENGTH_V20 0x08 #define SMBIOS_TYPE1_LENGTH_V21 0x19 #define SMBIOS_TYPE1_LENGTH_V24 0x1b +#define SMBIOS_TYPE4_LENGTH_V20 0x1a +#define SMBIOS_TYPE4_LENGTH_V23 0x23 +#define SMBIOS_TYPE4_LENGTH_V25 0x28 +#define SMBIOS_TYPE4_LENGTH_V26 0x2a +#define SMBIOS_TYPE4_LENGTH_V30 0x30 +#define SMBIOS_TYPE4_LENGTH_V36 0x32 + +#define SMBIOS_TYPE7_LENGTH_V20 0x0f +#define SMBIOS_TYPE7_LENGTH_V21 0x13 +#define SMBIOS_TYPE7_LENGTH_V31 0x1b + +#define SMBIOS_TYPE9_LENGTH_V20 0x0c +#define SMBIOS_TYPE9_LENGTH_V21 0x0d +#define SMBIOS_TYPE9_LENGTH_V26 0x11 + +#define SMBIOS_TYPE16_LENGTH_V21 0x0f +#define SMBIOS_TYPE16_LENGTH_V27 0x17 + +#define SMBIOS_TYPE17_LENGTH_V21 0x15 +#define SMBIOS_TYPE17_LENGTH_V23 0x1b +#define SMBIOS_TYPE17_LENGTH_V26 0x1c +#define SMBIOS_TYPE17_LENGTH_V27 0x22 +#define SMBIOS_TYPE17_LENGTH_V28 0x28 +#define SMBIOS_TYPE17_LENGTH_V32 0x54 +#define SMBIOS_TYPE17_LENGTH_V33 0x5c + +#define SMBIOS_TYPE19_LENGTH_V21 0x0f +#define SMBIOS_TYPE19_LENGTH_V27 0x1f + struct __packed smbios_type1 { struct smbios_header hdr; u8 manufacturer; @@ -264,6 +296,125 @@ struct __packed smbios_type7 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +#define SMBIOS_TYPE9_PGROUP_SIZE 5 + +struct pci_attr_lookup_table { + const char *str; + u8 slot_type; + u8 data_bus_width; + u8 slot_length; + u8 chara1; + u8 chara2; +}; + +union dev_func_num { + struct { + u8 dev_num:5; + u8 func_num:3; + } fields; + u8 data; +}; + +struct __packed smbios_type9 { + struct smbios_header hdr; + u8 socket_design; + u8 slot_type; + u8 slot_data_bus_width; + u8 current_usage; + u8 slot_length; + u16 slot_id; + u8 slot_characteristics_1; + u8 slot_characteristics_2; + u16 segment_group_number; + u8 bus_number; + union dev_func_num device_function_number; + u8 electrical_bus_width; + u8 peer_grouping_count; + /* + * Dynamic bytes will be inserted here to store peer_groups. + * length is equal to 'peer_grouping_count' * 5 + */ + u8 slot_information; + u8 slot_physical_width; + u16 slot_pitch; + u8 slot_height; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +enum { + SMBIOS_MEM_NONE = 0, + SMBIOS_MEM_CUSTOM = 1, + SMBIOS_MEM_FDT_MEM_NODE = 2, + SMBIOS_MEM_FDT_MEMCON_NODE = 3 +}; + +struct __packed smbios_type16 { + struct smbios_header hdr; + u8 location; + u8 use; + u8 mem_err_corr; + u32 max_cap; + u16 mem_err_info_hdl; + u16 num_of_mem_dev; + u64 ext_max_cap; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type17 { + struct smbios_header hdr; + u16 phy_mem_array_hdl; + u16 mem_err_info_hdl; + u16 total_width; + u16 data_width; + u16 size; + u8 form_factor; + u8 dev_set; + u8 dev_locator; + u8 bank_locator; + u8 mem_type; + u16 type_detail; + u16 speed; + u8 manufacturer; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 attributes; + u32 ext_size; + u16 config_mem_speed; + u16 min_voltage; + u16 max_voltage; + u16 config_voltage; + u8 mem_tech; + u16 mem_op_mode_cap; + u8 fw_ver; + u16 module_man_id; + u16 module_prod_id; + u16 mem_subsys_con_man_id; + u16 mem_subsys_con_prod_id; + u64 nonvolatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; + u32 ext_speed; + u32 ext_config_mem_speed; + u16 pmic0_man_id; + u16 pmic0_rev_num; + u16 rcd_man_id; + u16 rcd_rev_num; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + +struct __packed smbios_type19 { + struct smbios_header hdr; + u32 start_addr; + u32 end_addr; + u16 mem_array_hdl; + u8 partition_wid; + u64 ext_start_addr; + u64 ext_end_addr; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + struct __packed smbios_type32 { u8 type; u8 length; diff --git a/include/smbios_def.h b/include/smbios_def.h index 81c5781217f..ae50e1a808e 100644 --- a/include/smbios_def.h +++ b/include/smbios_def.h @@ -191,4 +191,254 @@ #define SMBIOS_CACHE_ASSOC_64WAY 13 #define SMBIOS_CACHE_ASSOC_20WAY 14 +/* + * System Slot + */ + +/* Slot Type */ +#define SMBIOS_SYSSLOT_TYPE_OTHER 1 +#define SMBIOS_SYSSLOT_TYPE_UNKNOWN 2 +#define SMBIOS_SYSSLOT_TYPE_ISA 3 /* ISA */ +#define SMBIOS_SYSSLOT_TYPE_PCI 6 /* PCI */ +#define SMBIOS_SYSSLOT_TYPE_PCMCIA 7 /* PCMCIA */ +#define SMBIOS_SYSSLOT_TYPE_PCIE 0xa5 /* PCI Express */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX1 0xa6 /* PCI Express x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX2 0xa7 /* PCI Express x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX4 0xa8 /* PCI Express x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX8 0xa9 /* PCI Express x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX16 0xaa /* PCI Express x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2 0xab /* PCI Express Gen 2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X1 0xac /* PCI Express Gen 2 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X2 0xad /* PCI Express Gen 2 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X4 0xae /* PCI Express Gen 2 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X8 0xaf /* PCI Express Gen 2 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X16 0xb0 /* PCI Express Gen 2 x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3 0xb1 /* PCI Express Gen 3 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X1 0xb2 /* PCI Express Gen 3 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X2 0xb3 /* PCI Express Gen 3 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X4 0xb4 /* PCI Express Gen 3 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X8 0xb5 /* PCI Express Gen 3 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16 0xb6 /* PCI Express Gen 3 x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4 0xb8 /* PCI Express Gen 4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X1 0xb9 /* PCI Express Gen 4 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X2 0xba /* PCI Express Gen 4 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X4 0xbb /* PCI Express Gen 4 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8 0xbc /* PCI Express Gen 4 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16 0xbd /* PCI Express Gen 4 x16 */ + +/* Slot Data Bus Width */ +#define SMBIOS_SYSSLOT_WIDTH_OTHER 1 +#define SMBIOS_SYSSLOT_WIDTH_UNKNOWN 2 +#define SMBIOS_SYSSLOT_WIDTH_8BIT 3 +#define SMBIOS_SYSSLOT_WIDTH_16BIT 4 +#define SMBIOS_SYSSLOT_WIDTH_32BIT 5 +#define SMBIOS_SYSSLOT_WIDTH_64BIT 6 +#define SMBIOS_SYSSLOT_WIDTH_128BIT 7 +#define SMBIOS_SYSSLOT_WIDTH_1X 8 +#define SMBIOS_SYSSLOT_WIDTH_2X 9 +#define SMBIOS_SYSSLOT_WIDTH_4X 10 +#define SMBIOS_SYSSLOT_WIDTH_8X 11 +#define SMBIOS_SYSSLOT_WIDTH_12X 12 +#define SMBIOS_SYSSLOT_WIDTH_16X 13 +#define SMBIOS_SYSSLOT_WIDTH_32X 14 + +/* Current Usage */ +#define SMBIOS_SYSSLOT_USAGE_OTHER 1 +#define SMBIOS_SYSSLOT_USAGE_UNKNOWN 2 +#define SMBIOS_SYSSLOT_USAGE_AVAILABLE 3 +#define SMBIOS_SYSSLOT_USAGE_INUSE 4 +#define SMBIOS_SYSSLOT_USAGE_NA 5 + +/* Slot Length */ +#define SMBIOS_SYSSLOT_LENG_OTHER 1 +#define SMBIOS_SYSSLOT_LENG_UNKNOWN 2 +#define SMBIOS_SYSSLOT_LENG_SHORT 3 +#define SMBIOS_SYSSLOT_LENG_LONG 4 +#define SMBIOS_SYSSLOT_LENG_2_5INDRV 5 +#define SMBIOS_SYSSLOT_LENG_3_5INDRV 6 + +/* Slot Characteristics 1 */ +#define SMBIOS_SYSSLOT_CHAR_UND 1 /* BIT(0) */ +#define SMBIOS_SYSSLOT_CHAR_5V 2 /* BIT(1) */ +#define SMBIOS_SYSSLOT_CHAR_3_3V 4 /* BIT(2) */ +#define SMBIOS_SYSSLOT_CHAR_SHARED 8 /* BIT(3) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARD16 16 /* BIT(4) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDBUS 32 /* BIT(5) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDZV 64 /* BIT(6) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDMRR 0x80 /* BIT(7) */ + +/* Slot Characteristics 2 */ +#define SMBIOS_SYSSLOT_CHAR_PCIPME 1 /* BIT(0) */ +#define SMBIOS_SYSSLOT_CHAR_HOTPLUG 2 /* BIT(1) */ +#define SMBIOS_SYSSLOT_CHAR_PCISMB 4 /* BIT(2) */ +#define SMBIOS_SYSSLOT_CHAR_PCIBIF 8 /* BIT(3) */ +#define SMBIOS_SYSSLOT_CHAR_ASYNCRM 16 /* BIT(4) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL1 32 /* BIT(5) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL2 64 /* BIT(6) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL3 0x80 /* BIT(7) */ + +/* Slot segment group number */ +#define SMBIOS_SYSSLOT_SGGNUM_UND 0 + +/* Physical Memory Array */ + +/* Location */ +#define SMBIOS_MA_LOCATION_OTHER 1 +#define SMBIOS_MA_LOCATION_UNKNOWN 2 +#define SMBIOS_MA_LOCATION_MOTHERBOARD 3 + +/* Use */ +#define SMBIOS_MA_USE_OTHER 1 +#define SMBIOS_MA_USE_UNKNOWN 2 +#define SMBIOS_MA_USE_SYSTEM 3 +#define SMBIOS_MA_USE_VIDEO 4 +#define SMBIOS_MA_USE_FLASH 5 +#define SMBIOS_MA_USE_NVRAM 6 +#define SMBIOS_MA_USE_CACHE 7 + +/* Error Correction Type */ +#define SMBIOS_MA_ERRCORR_OTHER 1 +#define SMBIOS_MA_ERRCORR_UNKNOWN 2 +#define SMBIOS_MA_ERRCORR_NONE 3 +#define SMBIOS_MA_ERRCORR_PARITY 4 +#define SMBIOS_MA_ERRCORR_SBITECC 5 +#define SMBIOS_MA_ERRCORR_MBITECC 6 +#define SMBIOS_MA_ERRCORR_CRC 7 + +/* Error Information Handle */ +#define SMBIOS_MA_ERRINFO_NONE 0xFFFE +#define SMBIOS_MA_ERRINFO_NOERR 0xFFFF + +/* Memory Device */ + +/* Size */ + +#define SMBIOS_MD_SIZE_UNKNOWN 0xFFFF +#define SMBIOS_MD_SIZE_EXT 0x7FFF + +/* Form Factor */ +#define SMBIOS_MD_FF_OTHER 1 +#define SMBIOS_MD_FF_UNKNOWN 2 +#define SMBIOS_MD_FF_SIMM 3 +#define SMBIOS_MD_FF_SIP 4 +#define SMBIOS_MD_FF_CHIP 5 +#define SMBIOS_MD_FF_DIP 6 +#define SMBIOS_MD_FF_ZIP 7 +#define SMBIOS_MD_FF_PROPCARD 8 +#define SMBIOS_MD_FF_DIMM 9 +#define SMBIOS_MD_FF_TSOP 10 +#define SMBIOS_MD_FF_ROC 11 +#define SMBIOS_MD_FF_RIMM 12 +#define SMBIOS_MD_FF_SODIMM 13 +#define SMBIOS_MD_FF_SRIMM 14 +#define SMBIOS_MD_FF_FBDIMM 15 +#define SMBIOS_MD_FF_DIE 16 + +/* Device set */ +#define SMBIOS_MD_DEVSET_NONE 0 +#define SMBIOS_MD_DEVSET_UNKNOWN 0xFF + +/* Speed */ +#define SMBIOS_MD_SPEED_UNKNOWN 0 +#define SMBIOS_MD_SPEED_EXT 0xFFFF + +/* Attributes */ +#define SMBIOS_MD_ATTR_RANK_UNKNOWN 0 + +/* Configured Memory Speed */ +#define SMBIOS_MD_CONFSPEED_UNKNOWN 0 +#define SMBIOS_MD_CONFSPEED_EXT 0xFFFF + +/* Voltage */ +#define SMBIOS_MD_VOLTAGE_UNKNOWN 0 + +/* Type */ +#define SMBIOS_MD_TYPE_OTHER 1 +#define SMBIOS_MD_TYPE_UNKNOWN 2 +#define SMBIOS_MD_TYPE_DRAM 3 +#define SMBIOS_MD_TYPE_EDRAM 4 +#define SMBIOS_MD_TYPE_VRAM 5 +#define SMBIOS_MD_TYPE_SRAM 6 +#define SMBIOS_MD_TYPE_RAM 7 +#define SMBIOS_MD_TYPE_ROM 8 +#define SMBIOS_MD_TYPE_FLASH 9 +#define SMBIOS_MD_TYPE_EEPROM 10 +#define SMBIOS_MD_TYPE_FEPROM 11 +#define SMBIOS_MD_TYPE_EPROM 12 +#define SMBIOS_MD_TYPE_CDRAM 13 +#define SMBIOS_MD_TYPE_3DRAM 14 +#define SMBIOS_MD_TYPE_SDRAM 15 +#define SMBIOS_MD_TYPE_SGRAM 16 +#define SMBIOS_MD_TYPE_RDRAM 17 +#define SMBIOS_MD_TYPE_DDR 18 +#define SMBIOS_MD_TYPE_DDR2 19 +#define SMBIOS_MD_TYPE_DDR2FBD 20 +#define SMBIOS_MD_TYPE_RSVD1 21 +#define SMBIOS_MD_TYPE_RSVD2 22 +#define SMBIOS_MD_TYPE_DSVD3 23 +#define SMBIOS_MD_TYPE_DDR3 24 +#define SMBIOS_MD_TYPE_FBD2 25 +#define SMBIOS_MD_TYPE_DDR4 26 +#define SMBIOS_MD_TYPE_LPDDR 27 +#define SMBIOS_MD_TYPE_LPDDR2 28 +#define SMBIOS_MD_TYPE_LPDDR3 29 +#define SMBIOS_MD_TYPE_LPDDR4 30 +#define SMBIOS_MD_TYPE_LNVD 31 +#define SMBIOS_MD_TYPE_HBM 32 +#define SMBIOS_MD_TYPE_HBM2 33 +#define SMBIOS_MD_TYPE_DDR5 34 +#define SMBIOS_MD_TYPE_LPDDR5 35 +#define SMBIOS_MD_TYPE_HBM3 36 + +/* Type Detail */ +#define SMBIOS_MD_TD_RSVD 1 /* BIT(0), set to 0 */ +#define SMBIOS_MD_TD_OTHER 2 /* BIT(1) */ +#define SMBIOS_MD_TD_UNKNOWN 4 /* BIT(2) */ +#define SMBIOS_MD_TD_FP 8 /* BIT(3) */ +#define SMBIOS_MD_TD_SC 0x10 /* BIT(4) */ +#define SMBIOS_MD_TD_PS 0x20 /* BIT(5) */ +#define SMBIOS_MD_TD_RAMBUS 0x40 /* BIT(6) */ +#define SMBIOS_MD_TD_SYNC 0x80 /* BIT(7) */ +#define SMBIOS_MD_TD_CMOS 0x100 /* BIT(8) */ +#define SMBIOS_MD_TD_EDO 0x200 /* BIT(9) */ +#define SMBIOS_MD_TD_WINDRAM 0x400 /* BIT(10) */ +#define SMBIOS_MD_TD_CACHEDRAM 0x800 /* BIT(11) */ +#define SMBIOS_MD_TD_NV 0x1000 /* BIT(12) */ +#define SMBIOS_MD_TD_RGSTD 0x2000 /* BIT(13) */ +#define SMBIOS_MD_TD_UNRGSTD 0x4000 /* BIT(14) */ +#define SMBIOS_MD_TD_LRDIMM 0x8000 /* BIT(15) */ + +/* Technology */ +#define SMBIOS_MD_TECH_OTHER 1 +#define SMBIOS_MD_TECH_UNKNOWN 2 +#define SMBIOS_MD_TECH_DRAM 3 +#define SMBIOS_MD_TECH_NVDIMMN 4 +#define SMBIOS_MD_TECH_NVDIMMF 5 +#define SMBIOS_MD_TECH_NVDIMMP 6 +#define SMBIOS_MD_TECH_OPTANE 7 + +/* Operating Mode Capability */ +#define SMBIOS_MD_OPMC_RSVD 1 /* BIT(0), set to 0 */ +#define SMBIOS_MD_OPMC_OTHER 2 /* BIT(1) */ +#define SMBIOS_MD_OPMC_UNKNOWN 4 /* BIT(2) */ +#define SMBIOS_MD_OPMC_VM 8 /* BIT(3) */ +#define SMBIOS_MD_OPMC_BYTEAPM 0x10 /* BIT(4) */ +#define SMBIOS_MD_OPMC_BLKAPM 0x20 /* BIT(5) */ +/* Bit 6:15 Reserved, set to 0 */ + +/* Non-volatile / Volatile / Cache / Logical portion Size */ +#define SMBIOS_MD_PORT_SIZE_NONE 0 +#define SMBIOS_MD_PORT_SIZE_UNKNOWN_HI 0xFFFFFFFF +#define SMBIOS_MD_PORT_SIZE_UNKNOWN_LO 0xFFFFFFFF +#define SMBIOS_MS_PORT_SIZE_UNKNOWN 0xFFFFFFFFFFFFFFFF + +/* Error Information Handle */ +#define SMBIOS_MD_ERRINFO_NONE 0xFFFE +#define SMBIOS_MD_ERRINFO_NOERR 0xFFFF + +/* Memory Array Mapped Address */ + +/* Partition Width */ +#define SMBIOS_MAMA_PW_DEF 1 /* not partitioned */ + #endif /* _SMBIOS_DEF_H_ */ diff --git a/include/spi.h b/include/spi.h index 2783200d663..95e7d5b1556 100644 --- a/include/spi.h +++ b/include/spi.h @@ -657,17 +657,6 @@ int spi_chip_select(struct udevice *slave); */ int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp); -/** - * spi_slave_of_to_plat() - decode standard SPI platform data - * - * This decodes the speed and mode for a slave from a device tree node - * - * @blob: Device tree blob - * @node: Node offset to read from - * @plat: Place to put the decoded information - */ -int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat); - /** * spi_cs_info() - Check information on a chip select * diff --git a/include/spl.h b/include/spl.h index 06dc28362d3..5078d7525ab 100644 --- a/include/spl.h +++ b/include/spl.h @@ -882,6 +882,12 @@ int spl_blk_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, enum uclass_id uclass_id, int devnum, int partnum); +/* SPL SQUASHFS image functions */ +int spl_load_image_sqfs(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + struct blk_desc *block_dev, int partition, + const char *filename); + /** * spl_early_init() - Set up device tree and driver model in SPL if enabled * diff --git a/include/squashfs.h b/include/squashfs.h index 7489eefa1f2..83ed8a49442 100644 --- a/include/squashfs.h +++ b/include/squashfs.h @@ -10,7 +10,10 @@ #ifndef _SQFS_H_ #define _SQFS_H_ -struct disk_partition; +#include +#include +#include +#include int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp); int sqfs_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp); diff --git a/include/status_led.h b/include/status_led.h deleted file mode 100644 index c3ff399b1ae..00000000000 --- a/include/status_led.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * The purpose of this code is to signal the operational status of a - * target which usually boots over the network; while running in - * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply - * message has been received, the LED is turned off. The Linux - * kernel, once it is running, will start blinking the LED again, - * with another frequency. - */ - -#ifndef _STATUS_LED_H_ -#define _STATUS_LED_H_ - -#ifdef CONFIG_LED_STATUS - -#define LED_STATUS_PERIOD (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ) -#ifdef CONFIG_LED_STATUS1 -#define LED_STATUS_PERIOD1 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ1) -#endif /* CONFIG_LED_STATUS1 */ -#ifdef CONFIG_LED_STATUS2 -#define LED_STATUS_PERIOD2 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ2) -#endif /* CONFIG_LED_STATUS2 */ -#ifdef CONFIG_LED_STATUS3 -#define LED_STATUS_PERIOD3 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ3) -#endif /* CONFIG_LED_STATUS3 */ -#ifdef CONFIG_LED_STATUS4 -#define LED_STATUS_PERIOD4 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ4) -#endif /* CONFIG_LED_STATUS4 */ -#ifdef CONFIG_LED_STATUS5 -#define LED_STATUS_PERIOD5 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ5) -#endif /* CONFIG_LED_STATUS5 */ - -void status_led_init(void); -void status_led_tick(unsigned long timestamp); -void status_led_set(int led, int state); - -static inline void status_led_boot_blink(void) -{ -#ifdef CONFIG_LED_STATUS_BOOT_ENABLE - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_BLINKING); -#endif -} - -#if defined(CONFIG_LED_STATUS_BOARD_SPECIFIC) -/* led_id_t is unsigned long mask */ -typedef unsigned long led_id_t; - -extern void __led_toggle (led_id_t mask); -extern void __led_init (led_id_t mask, int state); -extern void __led_set (led_id_t mask, int state); -void __led_blink(led_id_t mask, int freq); -#else -# error Status LED configuration missing -#endif - -#else - -static inline void status_led_init(void) { } -static inline void status_led_set(int led, int state) { } -static inline void status_led_boot_blink(void) { } - -#endif /* CONFIG_LED_STATUS */ -#endif /* _STATUS_LED_H_ */ diff --git a/include/sysinfo.h b/include/sysinfo.h index e87cf969fcd..54eb64a204a 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -12,6 +12,7 @@ struct udevice; #define SYSINFO_CACHE_LVL_MAX 3 +#define SYSINFO_MEM_HANDLE_MAX 8 /* * This uclass encapsulates hardware methods to gather information about a @@ -149,6 +150,9 @@ enum sysinfo_id { SYSID_SM_CACHE_INFO_END = SYSID_SM_CACHE_INST_SIZE2 + SYSINFO_CACHE_LVL_MAX - 1, + /* Memory Array (Type 16) */ + SYSID_SM_MEMARRAY_HANDLE, + /* For show_board_info() */ SYSID_BOARD_MODEL, SYSID_BOARD_MANUFACTURER, diff --git a/include/usb.h b/include/usb.h index be37ed272e1..dab23753f0c 100644 --- a/include/usb.h +++ b/include/usb.h @@ -208,15 +208,6 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue); #define USB_UHCI_VEND_ID 0x8086 #define USB_UHCI_DEV_ID 0x7112 -/* - * PXA25x can only act as USB device. There are drivers - * which works with USB CDC gadgets implementations. - * Some of them have common routines which can be used - * in boards init functions e.g. udc_disconnect() used for - * forced device disconnection from host. - */ -extern void udc_disconnect(void); - /* * board-specific hardware initialization, called by * usb drivers and u-boot commands diff --git a/include/usb/udc.h b/include/usb/udc.h index 749b3a3f015..c5e431813be 100644 --- a/include/usb/udc.h +++ b/include/usb/udc.h @@ -39,7 +39,6 @@ int udc_endpoint_write(struct usb_endpoint_instance *endpoint); void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint); void udc_connect(void); -void udc_disconnect(void); void udc_enable(struct usb_device_instance *device); void udc_disable(void); void udc_startup_events(struct usb_device_instance *device); diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 05df49f292a..f5e72625e53 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -185,6 +185,11 @@ enum pm_query_id { PM_QID_CLOCK_GET_MAX_DIVISOR = 13, }; +#define NUM_GROUPS_PER_RESP 6 +#define NA_GROUP -1 +#define RESERVED_GROUP -2 +#define MAX_FUNC_NAME_LEN 16 + enum pm_pinctrl_config_param { PM_PINCTRL_CONFIG_SLEW_RATE = 0, PM_PINCTRL_CONFIG_BIAS_STATUS = 1, diff --git a/lib/Kconfig b/lib/Kconfig index 931d5206936..46384283c43 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -71,10 +71,14 @@ config DYNAMIC_CRC_TABLE Enable this option to calculate entries for CRC tables at runtime. This can be helpful when reducing the size of the build image -config FW_LOADER - bool "Enable firmware loader using environment script" +config SUPPORTS_FW_LOADER + bool depends on CMDLINE depends on ENV_SUPPORT + +config FW_LOADER + bool "Enable firmware loader using environment script" + depends on SUPPORTS_FW_LOADER help Enable this option to make firmware loading using user-provided U-Boot environment script functionality accessible to U-Boot code. @@ -334,6 +338,7 @@ config SPL_ACPI config GENERATE_ACPI_TABLE bool "Generate an ACPI (Advanced Configuration and Power Interface) table" depends on ACPI + select ACPIGEN if !QFW_ACPI select BLOBLIST select QFW if QEMU help diff --git a/lib/Makefile b/lib/Makefile index 70667f3728c..d0ffabc2b47 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -147,6 +147,7 @@ else obj-$(CONFIG_$(PHASE_)SPRINTF) += vsprintf.o endif obj-$(CONFIG_$(PHASE_)STRTO) += strto.o +obj-$(CONFIG_$(PHASE_)UFS_SUPPORT) += charset.o else # Main U-Boot always uses the full printf support obj-y += vsprintf.o strto.o diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 13e44be1d06..b5f81e0ff53 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -15,6 +15,8 @@ config EFI_LOADER # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT depends on !EFI_APP + # The EFI specification requires 128 KiB or more of stack space + depends on STACK_SIZE >= 0x20000 default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8 select EFI select CHARSET @@ -112,7 +114,8 @@ menu "UEFI Variables" choice prompt "Store for non-volatile UEFI variables" - default EFI_VARIABLE_FILE_STORE + default EFI_VARIABLE_FILE_STORE if FAT_WRITE + default EFI_VARIABLE_NO_STORE help Select where non-volatile UEFI variables shall be stored. @@ -123,6 +126,24 @@ config EFI_VARIABLE_FILE_STORE Select this option if you want non-volatile UEFI variables to be stored as file /ubootefi.var on the EFI system partition. +config EFI_VARIABLE_SF_STORE + bool "Store non-volatile UEFI variables in SPI Flash" + depends on SPI_FLASH + help + Select this option if you want non-volatile UEFI variables to be + stored in SPI Flash. + + Define CONFIG_EFI_VARIABLE_SF_OFFSET as offset in SPI Flash to use as + the storage for variables. CONFIG_EFI_VAR_BUF_SIZE defines the space + needed. + + Note that SPI Flash devices have a limited number of program/erase + cycles. Frequent updates to UEFI variables may cause excessive wear + and can permanently damage the flash device, particularly on SPI NAND + or low-end SPI NOR parts without wear leveling. This option should be + used with care on such systems, and is not recommended for platforms + where UEFI variables are updated frequently. + config EFI_MM_COMM_TEE bool "UEFI variables storage service via the trusted world" depends on OPTEE @@ -193,6 +214,21 @@ config FFA_SHARED_MM_BUF_ADDR the MM SP in secure world. It is assumed that the MM SP knows the address of the shared MM communication buffer. +config EFI_VARIABLE_SF_OFFSET + hex "EFI variables in SPI flash offset" + depends on EFI_VARIABLE_SF_STORE + help + Offset from the start of the SPI Flash where EFI variables will be stored. + This should be aligned to the sector size of SPI Flash. + +config EFI_VARIABLE_SF_DEVICE_INDEX + int "Device Index for target SPI Flash" + depends on EFI_VARIABLE_SF_STORE + default 0 + help + The index of SPI Flash device used for storing EFI variables. This would be + needed if there are more than 1 SPI Flash devices available to use. + config EFI_VARIABLES_PRESEED bool "Initial values for UEFI variables" depends on !COMPILE_TEST diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index f490081f654..d73ad43951b 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -53,7 +53,8 @@ ifeq ($(CONFIG_EFI_MM_COMM_TEE),y) obj-y += efi_variable_tee.o else obj-y += efi_variable.o -obj-y += efi_var_file.o +obj-$(CONFIG_EFI_VARIABLE_FILE_STORE) += efi_var_file.o +obj-$(CONFIG_EFI_VARIABLE_SF_STORE) += efi_var_sf.o obj-$(CONFIG_EFI_VARIABLES_PRESEED) += efi_var_seed.o endif obj-y += efi_watchdog.o diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 89e63ed8dd5..52887f7c274 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -29,8 +28,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID; static const efi_guid_t efi_guid_firmware_management_capsule_id = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID; @@ -465,7 +462,7 @@ static __maybe_unused efi_status_t fwu_empty_capsule_process( log_err("Unable to set the Accept bit for the image %pUs\n", image_guid); - status = fwu_state_machine_updates(0, active_idx); + status = fwu_state_machine_updates(FWU_BANK_ACCEPTED, active_idx); if (status < 0) ret = EFI_DEVICE_ERROR; @@ -510,7 +507,8 @@ static __maybe_unused efi_status_t fwu_post_update_process(bool fw_accept_os) log_err("Failed to update FWU metadata index values\n"); } else { log_debug("Successfully updated the active_index\n"); - status = fwu_state_machine_updates(fw_accept_os ? 1 : 0, + status = fwu_state_machine_updates(fw_accept_os ? + FWU_BANK_VALID : FWU_BANK_ACCEPTED, update_index); if (status < 0) ret = EFI_DEVICE_ERROR; diff --git a/lib/efi_loader/efi_conformance.c b/lib/efi_loader/efi_conformance.c index 2d31800ccb8..470141af483 100644 --- a/lib/efi_loader/efi_conformance.c +++ b/lib/efi_loader/efi_conformance.c @@ -12,7 +12,7 @@ #include #include -static const efi_guid_t efi_ecpt_guid = EFI_CONFORMANCE_PROFILES_TABLE_GUID; +const efi_guid_t efi_ecpt_guid = EFI_CONFORMANCE_PROFILES_TABLE_GUID; /** * efi_ecpt_register() - Install the ECPT system table. diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 130c4db9606..f8a57539ec6 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -475,9 +475,12 @@ static efi_status_t efi_disk_add_dev( #if CONFIG_IS_ENABLED(DOS_PARTITION) case PART_TYPE_DOS: info->type = PARTITION_TYPE_MBR; - - /* TODO: implement support for MBR partition types */ - log_debug("EFI_PARTITION_INFO_PROTOCOL doesn't support MBR\n"); + ret = part_get_mbr(desc, part, &info->info.mbr); + if (ret) { + log_debug("get MBR for part %d failed %ld\n", + part, ret); + goto error; + } break; #endif default: diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index 3abb47d610e..9403e09691e 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -13,9 +13,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static const efi_guid_t efi_gop_guid = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID; diff --git a/lib/efi_loader/efi_rng.c b/lib/efi_loader/efi_rng.c index 4734f95eee1..7810b4e47ea 100644 --- a/lib/efi_loader/efi_rng.c +++ b/lib/efi_loader/efi_rng.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; const efi_guid_t efi_guid_rng_protocol = EFI_RNG_PROTOCOL_GUID; diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 35eb6a77766..73d4097464c 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -209,6 +209,30 @@ void __efi_runtime efi_memcpy_runtime(void *dest, const void *src, size_t n) *d++ = *s++; } +/** + * efi_memcmp_runtime() - compare memory areas + * + * At runtime memcmp() is not available. + * + * @s1: first memory area + * @s2: second memory area + * @n: number of bytes to compare + * Return: 0 if equal, negative if s1 < s2, positive if s1 > s2 + */ +int __efi_runtime efi_memcmp_runtime(const void *s1, const void *s2, size_t n) +{ + const u8 *pos1 = s1; + const u8 *pos2 = s2; + + for (; n; --n) { + if (*pos1 != *pos2) + return *pos1 - *pos2; + ++pos1; + ++pos2; + } + return 0; +} + /** * efi_update_table_header_crc32() - Update crc32 in table header * diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index 4b34a58b4cf..d63c2d1b1cd 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -41,6 +41,7 @@ static const struct efi_auth_var_name_type name_type[] = { static bool efi_secure_boot; static enum efi_secure_mode efi_secure_mode; +static const efi_guid_t shim_lock_guid = SHIM_LOCK_GUID; /** * efi_efi_get_variable() - retrieve value of a UEFI variable @@ -488,3 +489,46 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t * return EFI_SUCCESS; } + +efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) +{ + struct efi_var_entry *var, *last_var; + u16 *data; + efi_status_t ret; + + if (buf->reserved || buf->magic != EFI_VAR_FILE_MAGIC || + buf->length > EFI_VAR_BUF_SIZE || + buf->length < sizeof(struct efi_var_file) || + buf->crc32 != crc32(0, (u8 *)buf->var, + buf->length - sizeof(struct efi_var_file))) { + log_err("Invalid EFI variables file\n"); + return EFI_INVALID_PARAMETER; + } + + last_var = (struct efi_var_entry *)((u8 *)buf + buf->length); + for (var = buf->var; var < last_var; + var = (struct efi_var_entry *)ALIGN((uintptr_t)data + var->length, 8)) { + data = var->name + u16_strlen(var->name) + 1; + + /* + * Secure boot related and volatile variables shall only be + * restored from U-Boot's preseed. + */ + if (!safe && + (efi_auth_var_get_type(var->name, &var->guid) != + EFI_AUTH_VAR_NONE || + !guidcmp(&var->guid, &shim_lock_guid) || + !(var->attr & EFI_VARIABLE_NON_VOLATILE))) + continue; + if (!var->length) + continue; + if (efi_var_mem_find(&var->guid, var->name, NULL)) + continue; + ret = efi_var_mem_ins(var->name, &var->guid, var->attr, + var->length, data, 0, NULL, + var->time, NULL); + if (ret != EFI_SUCCESS) + log_err("Failed to set EFI variable %ls\n", var->name); + } + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index f23a964a418..9cda38f319e 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -14,17 +14,9 @@ #include #include #include -#include #define PART_STR_LEN 10 -/* GUID used by Shim to store the MOK database */ -#define SHIM_LOCK_GUID \ - EFI_GUID(0x605dab50, 0xe046, 0x4300, \ - 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23) - -static const efi_guid_t shim_lock_guid = SHIM_LOCK_GUID; - /** * efi_set_blk_dev_to_system_partition() - select EFI system partition * @@ -51,15 +43,14 @@ static efi_status_t __maybe_unused efi_set_blk_dev_to_system_partition(void) } /** - * efi_var_to_file() - save non-volatile variables as file + * efi_var_to_storage() - save non-volatile variables as file * * File ubootefi.var is created on the EFI system partion. * * Return: status code */ -efi_status_t efi_var_to_file(void) +efi_status_t efi_var_to_storage(void) { -#ifdef CONFIG_EFI_VARIABLE_FILE_STORE efi_status_t ret; struct efi_var_file *buf; loff_t len; @@ -91,56 +82,10 @@ error: out: free(buf); return ret; -#else - return EFI_SUCCESS; -#endif -} - -efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) -{ - struct efi_var_entry *var, *last_var; - u16 *data; - efi_status_t ret; - - if (buf->reserved || buf->magic != EFI_VAR_FILE_MAGIC || - buf->crc32 != crc32(0, (u8 *)buf->var, - buf->length - sizeof(struct efi_var_file))) { - log_err("Invalid EFI variables file\n"); - return EFI_INVALID_PARAMETER; - } - - last_var = (struct efi_var_entry *)((u8 *)buf + buf->length); - for (var = buf->var; var < last_var; - var = (struct efi_var_entry *) - ALIGN((uintptr_t)data + var->length, 8)) { - - data = var->name + u16_strlen(var->name) + 1; - - /* - * Secure boot related and volatile variables shall only be - * restored from U-Boot's preseed. - */ - if (!safe && - (efi_auth_var_get_type(var->name, &var->guid) != - EFI_AUTH_VAR_NONE || - !guidcmp(&var->guid, &shim_lock_guid) || - !(var->attr & EFI_VARIABLE_NON_VOLATILE))) - continue; - if (!var->length) - continue; - if (efi_var_mem_find(&var->guid, var->name, NULL)) - continue; - ret = efi_var_mem_ins(var->name, &var->guid, var->attr, - var->length, data, 0, NULL, - var->time); - if (ret != EFI_SUCCESS) - log_err("Failed to set EFI variable %ls\n", var->name); - } - return EFI_SUCCESS; } /** - * efi_var_from_file() - read variables from file + * efi_var_from_storage() - read variables from file * * File ubootefi.var is read from the EFI system partitions and the variables * stored in the file are created. @@ -153,9 +98,8 @@ efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) * * Return: status code */ -efi_status_t efi_var_from_file(void) +efi_status_t efi_var_from_storage(void) { -#ifdef CONFIG_EFI_VARIABLE_FILE_STORE struct efi_var_file *buf; loff_t len; efi_status_t ret; @@ -180,6 +124,5 @@ efi_status_t efi_var_from_file(void) log_err("Invalid EFI variables file\n"); error: free(buf); -#endif return EFI_SUCCESS; } diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index 31180df9e3a..8d5f99f4870 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -159,12 +159,39 @@ efi_status_t __efi_runtime efi_var_mem_ins( const efi_guid_t *vendor, u32 attributes, const efi_uintn_t size1, const void *data1, const efi_uintn_t size2, const void *data2, - const u64 time) + const u64 time, bool *changep) { u16 *data; struct efi_var_entry *var; u32 var_name_len; + if (changep) + *changep = true; + + /* + * If this is not an append (size2 == 0), check whether the variable + * already exists with identical attributes and data. When nothing + * changed we can skip the write and avoid superfluous erases. + */ + if (!size2 && changep) { + struct efi_var_entry *old; + + old = efi_var_mem_find(vendor, variable_name, NULL); + if (old && old->attr == attributes && + old->length == size1 && old->time == time) { + u16 *old_data; + + for (old_data = old->name; *old_data; ++old_data) + ; + ++old_data; + + if (!efi_memcmp_runtime(old_data, data1, size1)) { + *changep = false; + return EFI_SUCCESS; + } + } + } + var = (struct efi_var_entry *) ((uintptr_t)efi_var_buf + efi_var_buf->length); var_name_len = u16_strlen(variable_name) + 1; diff --git a/lib/efi_loader/efi_var_sf.c b/lib/efi_loader/efi_var_sf.c new file mode 100644 index 00000000000..6eae8d46464 --- /dev/null +++ b/lib/efi_loader/efi_var_sf.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPI Flash interface for UEFI variables + * + * Copyright (c) 2023, Shantur Rathore + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#define LOG_CATEGORY LOGC_EFI + +#include +#include +#include +#include + +efi_status_t efi_var_to_storage(void) +{ + struct efi_var_file *buf; + struct spi_flash *flash; + struct udevice *sfdev; + efi_status_t ret; + size_t erase_len; + loff_t len; + int r; + + ret = efi_var_collect(&buf, &len, EFI_VARIABLE_NON_VOLATILE); + if (ret != EFI_SUCCESS) + goto error; + + if (len > EFI_VAR_BUF_SIZE) { + log_debug("EFI var buffer length more than target SPI Flash size\n"); + ret = EFI_OUT_OF_RESOURCES; + goto error; + } + + log_debug("Got buffer to write buf->len: %d\n", buf->length); + + r = uclass_get_device(UCLASS_SPI_FLASH, + CONFIG_EFI_VARIABLE_SF_DEVICE_INDEX, &sfdev); + if (r) { + ret = EFI_DEVICE_ERROR; + goto error; + } + + flash = dev_get_uclass_priv(sfdev); + if (!flash) { + log_debug("Failed to get SPI Flash priv data\n"); + ret = EFI_DEVICE_ERROR; + goto error; + } + erase_len = ALIGN(len, flash->sector_size); + + r = spi_flash_erase_dm(sfdev, CONFIG_EFI_VARIABLE_SF_OFFSET, + erase_len); + if (r) { + log_debug("Failed to erase SPI Flash\n"); + ret = EFI_DEVICE_ERROR; + goto error; + } + + r = spi_flash_write_dm(sfdev, CONFIG_EFI_VARIABLE_SF_OFFSET, len, buf); + if (r) { + log_debug("Failed to write to SPI Flash: %d\n", r); + ret = EFI_DEVICE_ERROR; + } + +error: + free(buf); + return ret; +} + +efi_status_t efi_var_from_storage(void) +{ + struct efi_var_file *buf; + struct udevice *sfdev; + efi_status_t ret; + int r; + + buf = calloc(1, EFI_VAR_BUF_SIZE); + if (!buf) { + log_err("Unable to allocate buffer\n"); + return EFI_OUT_OF_RESOURCES; + } + + r = uclass_get_device(UCLASS_SPI_FLASH, + CONFIG_EFI_VARIABLE_SF_DEVICE_INDEX, &sfdev); + if (r) { + log_err("Failed to get SPI Flash device: %d\n", r); + ret = EFI_DEVICE_ERROR; + goto error; + } + + r = spi_flash_read_dm(sfdev, CONFIG_EFI_VARIABLE_SF_OFFSET, + EFI_VAR_BUF_SIZE, buf); + if (r) { + log_err("Failed to read from SPI Flash: %d\n", r); + ret = EFI_DEVICE_ERROR; + goto error; + } + + if (efi_var_restore(buf, false) != EFI_SUCCESS) { + log_err("No valid EFI variables in SPI Flash\n"); + ret = EFI_DEVICE_ERROR; + goto error; + } + + ret = EFI_SUCCESS; +error: + free(buf); + return ret; +} diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index f3533f4def3..9923936c1b5 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -277,6 +277,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, struct efi_var_entry *var; efi_uintn_t ret; bool append, delete; + bool changed = false; u64 time = 0; enum efi_auth_var_type var_type; @@ -366,6 +367,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (delete) { /* EFI_NOT_FOUND has been handled before */ attributes = var->attr; + changed = true; ret = EFI_SUCCESS; } else if (append && var) { /* @@ -380,15 +382,19 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, ret = efi_var_mem_ins(variable_name, vendor, attributes & ~EFI_VARIABLE_APPEND_WRITE, var->length, old_data, data_size, data, - time); + time, &changed); } else { ret = efi_var_mem_ins(variable_name, vendor, attributes, - data_size, data, 0, NULL, time); + data_size, data, 0, NULL, time, + &changed); } if (ret != EFI_SUCCESS) return ret; + if (!changed) + return EFI_SUCCESS; + efi_var_mem_del(var); if (var_type == EFI_AUTH_VAR_PK) @@ -396,12 +402,13 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, else ret = EFI_SUCCESS; - /* - * Write non-volatile EFI variables to file - * TODO: check if a value change has occured to avoid superfluous writes - */ - if (attributes & EFI_VARIABLE_NON_VOLATILE) - efi_var_to_file(); + /* Write non-volatile EFI variables to storage */ + if (attributes & EFI_VARIABLE_NON_VOLATILE) { + if (IS_ENABLED(CONFIG_EFI_VARIABLE_NO_STORE)) + return EFI_SUCCESS; + + efi_var_to_storage(); + } return EFI_SUCCESS; } @@ -494,6 +501,7 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, struct efi_var_entry *var; efi_uintn_t ret; bool append, delete; + bool changed = false; u64 time = 0; if (!IS_ENABLED(CONFIG_EFI_RT_VOLATILE_STORE)) @@ -545,6 +553,7 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, if (delete) { /* EFI_NOT_FOUND has been handled before */ attributes = var->attr; + changed = true; ret = EFI_SUCCESS; } else if (append && var) { u16 *old_data = (void *)((uintptr_t)var->name + @@ -552,15 +561,19 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, ret = efi_var_mem_ins(variable_name, vendor, attributes, var->length, old_data, data_size, data, - time); + time, &changed); } else { ret = efi_var_mem_ins(variable_name, vendor, attributes, - data_size, data, 0, NULL, time); + data_size, data, 0, NULL, time, + &changed); } if (ret != EFI_SUCCESS) return ret; - /* We are always inserting new variables, get rid of the old copy */ + + if (!changed) + return EFI_SUCCESS; + efi_var_mem_del(var); return EFI_SUCCESS; @@ -594,9 +607,12 @@ efi_status_t efi_init_variables(void) if (ret != EFI_SUCCESS) return ret; - ret = efi_var_from_file(); - if (ret != EFI_SUCCESS) - return ret; + if (!IS_ENABLED(CONFIG_EFI_VARIABLE_NO_STORE)) { + ret = efi_var_from_storage(); + if (ret != EFI_SUCCESS) + return ret; + } + if (IS_ENABLED(CONFIG_EFI_VARIABLES_PRESEED)) { ret = efi_var_restore((struct efi_var_file *) __efi_var_file_begin, true); diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c index f145e58a267..9c4be834eeb 100644 --- a/lib/efi_selftest/efi_selftest_block_device.c +++ b/lib/efi_selftest/efi_selftest_block_device.c @@ -19,6 +19,7 @@ #include "efi_selftest_disk_image.h" #include #include +#include /* Block size of compressed disk image */ #define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8 @@ -319,6 +320,25 @@ static int execute(void) u64 pos; char block_io_aligned[1 << LB_BLOCK_SIZE] __aligned(1 << LB_BLOCK_SIZE); + /* + * The test disk image is defined in efi_selftest_disk_image.h, + * it contains a single FAT12 partition of 127 sectors size. + */ + static const dos_partition_t mbr_expected = { + .boot_ind = 0x00, + .head = 0x00, + .sector = 0x02, + .cyl = 0x00, + .sys_ind = 0x01, /* FAT12 */ + .end_head = 0x02, + .end_sector = 0x02, + .end_cyl = 0x00, + /* LBA 1 */ + .start_sect = cpu_to_le32(1), + /* Size 127 sectors (0x7f) */ + .nr_sects = cpu_to_le32(127), + }; + /* Connect controller to virtual disk */ ret = boottime->connect_controller(disk_handle, NULL, NULL, 1); if (ret != EFI_SUCCESS) { @@ -405,6 +425,12 @@ static int execute(void) return EFI_ST_FAILURE; } + /* Compare the obtained MBR with the expected one for the test partition */ + if (memcmp(&part_info->info.mbr, &mbr_expected, sizeof(mbr_expected))) { + efi_st_error("MBR partition record mismatch\n"); + return EFI_ST_FAILURE; + } + /* Open the simple file system protocol */ ret = boottime->open_protocol(handle_partition, &guid_simple_file_system_protocol, diff --git a/lib/fdtdec.c b/lib/fdtdec.c index c38738b48c7..fb3375ea157 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1077,13 +1077,12 @@ int fdtdec_setup_mem_size_base(void) gd->ram_size = (phys_size_t)(res.end - res.start + 1); gd->ram_base = (unsigned long)res.start; - debug("%s: Initial DRAM size %llx\n", __func__, - (unsigned long long)gd->ram_size); + debug("%s: Initial DRAM size %pap\n", __func__, &gd->ram_size); return 0; } -ofnode get_next_memory_node(ofnode mem) +static ofnode get_next_memory_node(ofnode mem) { do { mem = ofnode_by_prop_value(mem, "device_type", "memory", 7); @@ -1092,6 +1091,11 @@ ofnode get_next_memory_node(ofnode mem) return mem; } +ofnode fdtdec_get_next_memory_node(ofnode mem) +{ + return get_next_memory_node(mem); +} + int fdtdec_setup_memory_banksize(void) { int bank, ret, reg = 0; @@ -1124,10 +1128,10 @@ int fdtdec_setup_memory_banksize(void) gd->bd->bi_dram[bank].size = (phys_size_t)(res.end - res.start + 1); - debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n", + debug("%s: DRAM Bank #%d: start = %pap, size = %pap\n", __func__, bank, - (unsigned long long)gd->bd->bi_dram[bank].start, - (unsigned long long)gd->bd->bi_dram[bank].size); + &gd->bd->bi_dram[bank].start, + &gd->bd->bi_dram[bank].size); } return 0; diff --git a/lib/fwu_updates/Kconfig b/lib/fwu_updates/Kconfig index a722107c129..b38808e3463 100644 --- a/lib/fwu_updates/Kconfig +++ b/lib/fwu_updates/Kconfig @@ -1,6 +1,7 @@ menuconfig FWU_MULTI_BANK_UPDATE bool "Enable FWU Multi Bank Update Feature" depends on EFI_CAPSULE_ON_DISK + select EFI_PARTITION select PARTITION_TYPE_GUID select FWU_MDATA imply EFI_CAPSULE_ON_DISK_EARLY diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index 0f5ef2ba515..37c613014d1 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -766,6 +766,12 @@ static int fwu_boottime_checks(void) if (boot_idx != active_idx) { log_info("Boot idx %u is not matching active idx %u, changing active_idx\n", boot_idx, active_idx); + + ret = fwu_state_machine_updates(FWU_BANK_INVALID, active_idx); + if (ret) + log_err("Unable to set bank %u state as invalid", + active_idx); + ret = fwu_set_active_index(boot_idx); if (!ret) boottime_check = 1; diff --git a/lib/fwu_updates/fwu_v1.c b/lib/fwu_updates/fwu_v1.c index 974abf216f6..5824cca98cf 100644 --- a/lib/fwu_updates/fwu_v1.c +++ b/lib/fwu_updates/fwu_v1.c @@ -98,27 +98,27 @@ void fwu_populate_mdata_image_info(struct fwu_data *data) /** * fwu_state_machine_updates() - Update FWU state of the platform - * @trial_state: Is platform transitioning into Trial State + * @state: FWU bank state * @update_index: Bank number to which images have been updated * - * On successful completion of updates, transition the platform to - * either Trial State or Regular State. + * FWU_BANK_VALID transition the platform to Trial state + * FWU_BANK_ACCEPTED accept the FWU bank state + * FWU_BANK_INVALID invalid the FWU bank state * * To transition the platform to Trial State, start the * TrialStateCtr counter, followed by setting the value of bank_state * field of the metadata to Valid state(applicable only in version 2 * of metadata). * - * In case, the platform is to transition directly to Regular State, - * update the bank_state field of the metadata to Accepted - * state(applicable only in version 2 of metadata). + * Saving the bank_state field of the metadata is only applicable in + * version 2 of metadata. * * Return: 0 if OK, -ve on error */ -int fwu_state_machine_updates(bool trial_state, +int fwu_state_machine_updates(enum fwu_bank_states state, uint32_t update_index) { - return fwu_trial_state_update(trial_state, update_index); + return fwu_trial_state_update(state == FWU_BANK_VALID, update_index); } /** diff --git a/lib/fwu_updates/fwu_v2.c b/lib/fwu_updates/fwu_v2.c index 159315b45b9..f48b6d1264b 100644 --- a/lib/fwu_updates/fwu_v2.c +++ b/lib/fwu_updates/fwu_v2.c @@ -80,42 +80,27 @@ static int fwu_mdata_sanity_checks(void) return 0; } -static int fwu_bank_state_update(bool trial_state, uint32_t bank) +static int fwu_bank_state_update(enum fwu_bank_states state, uint32_t bank) { int ret; struct fwu_data *data = fwu_get_data(); struct fwu_mdata *mdata = data->fwu_mdata; - if (!trial_state && !fwu_bank_accepted(data, bank)) + if (state == FWU_BANK_ACCEPTED && !fwu_bank_accepted(data, bank)) return 0; - mdata->bank_state[bank] = data->bank_state[bank] = trial_state ? - FWU_BANK_VALID : FWU_BANK_ACCEPTED; + mdata->bank_state[bank] = (uint8_t)state; + data->bank_state[bank] = (uint8_t)state; ret = fwu_sync_mdata(mdata, BOTH_PARTS); if (ret) log_err("Unable to set bank_state for bank %u\n", bank); else - data->trial_state = trial_state; + data->trial_state = state == FWU_BANK_VALID ? 1 : 0; return ret; } -static int fwu_trial_state_start(uint update_index) -{ - int ret; - - ret = fwu_trial_state_ctr_start(); - if (ret) - return ret; - - ret = fwu_bank_state_update(1, update_index); - if (ret) - return ret; - - return 0; -} - static bool fwu_get_mdata_mandatory(uint part) { int ret = 0; @@ -171,27 +156,34 @@ void fwu_populate_mdata_image_info(struct fwu_data *data) /** * fwu_state_machine_updates() - Update FWU state of the platform - * @trial_state: Is platform transitioning into Trial State + * @state: FWU bank state * @update_index: Bank number to which images have been updated * - * On successful completion of updates, transition the platform to - * either Trial State or Regular State. + * FWU_BANK_VALID transition the platform to Trial state + * FWU_BANK_ACCEPTED accept the FWU bank state + * FWU_BANK_INVALID invalid the FWU bank state * * To transition the platform to Trial State, start the * TrialStateCtr counter, followed by setting the value of bank_state * field of the metadata to Valid state(applicable only in version 2 * of metadata). * - * In case, the platform is to transition directly to Regular State, - * update the bank_state field of the metadata to Accepted - * state(applicable only in version 2 of metadata). + * Saving the bank_state field of the metadata is only applicable in + * version 2 of metadata. * * Return: 0 if OK, -ve on error */ -int fwu_state_machine_updates(bool trial_state, uint32_t update_index) +int fwu_state_machine_updates(enum fwu_bank_states state, uint32_t update_index) { - return trial_state ? fwu_trial_state_start(update_index) : - fwu_bank_state_update(0, update_index); + int ret; + + if (state == FWU_BANK_VALID) { + ret = fwu_trial_state_ctr_start(); + if (ret) + return ret; + } + + return fwu_bank_state_update(state, update_index); } /** diff --git a/lib/linux_compat.c b/lib/linux_compat.c index 985e88eb397..e4a3293e3af 100644 --- a/lib/linux_compat.c +++ b/lib/linux_compat.c @@ -32,6 +32,9 @@ struct kmem_cache *get_mem(int element_sz) struct kmem_cache *ret; ret = memalign(ARCH_DMA_MINALIGN, sizeof(struct kmem_cache)); + if (!ret) + return NULL; + ret->sz = element_sz; return ret; diff --git a/lib/lmb.c b/lib/lmb.c index e2d9fe86c14..8f12c6ad8e5 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -611,7 +611,6 @@ static __maybe_unused void lmb_reserve_common_spl(void) static void lmb_add_memory(void) { int i; - phys_addr_t bank_end; phys_size_t size; u64 ram_top = gd->ram_top; struct bd_info *bd = gd->bd; @@ -625,23 +624,9 @@ static void lmb_add_memory(void) for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { size = bd->bi_dram[i].size; - bank_end = bd->bi_dram[i].start + size; - if (size) { + if (size) lmb_add(bd->bi_dram[i].start, size); - - /* - * Reserve memory above ram_top as - * no-overwrite so that it cannot be - * allocated - */ - if (bd->bi_dram[i].start >= ram_top) - lmb_reserve(bd->bi_dram[i].start, size, - LMB_NOOVERWRITE); - else if (bank_end > ram_top) - lmb_reserve(ram_top, bank_end - ram_top, - LMB_NOOVERWRITE); - } } } diff --git a/lib/lwip/u-boot/lwipopts.h b/lib/lwip/u-boot/lwipopts.h index e8a2c9d7a0a..8dae004f1a2 100644 --- a/lib/lwip/u-boot/lwipopts.h +++ b/lib/lwip/u-boot/lwipopts.h @@ -65,7 +65,21 @@ #define MEM_ALIGNMENT 8 #define MEMP_NUM_TCP_SEG 16 + +/* IP fragmentation parameters for TFTP reassembly */ +#define IP_FRAG_MTU_USABLE 1480 +#define PBUF_POOL_HEADROOM 6 +#define PBUF_POOL_RESERVE 4 +#define TFTP_BLOCKSIZE_THRESHOLD 4096 + +#if defined(CONFIG_TFTP_BLOCKSIZE) && (CONFIG_TFTP_BLOCKSIZE > TFTP_BLOCKSIZE_THRESHOLD) +#define PBUF_POOL_SIZE (((CONFIG_TFTP_BLOCKSIZE + (IP_FRAG_MTU_USABLE - 1)) / \ + IP_FRAG_MTU_USABLE) + PBUF_POOL_HEADROOM) +#define IP_REASS_MAX_PBUFS (PBUF_POOL_SIZE - PBUF_POOL_RESERVE) +#else #define PBUF_POOL_SIZE 8 +#define IP_REASS_MAX_PBUFS 4 +#endif #define LWIP_ARP 1 #define ARP_TABLE_SIZE 4 @@ -76,7 +90,7 @@ #define IP_REASSEMBLY 1 #define IP_FRAG 1 #define IP_REASS_MAXAGE 3 -#define IP_REASS_MAX_PBUFS 4 + #define IP_FRAG_USES_STATIC_BUF 0 #define IP_DEFAULT_TTL 255 @@ -121,9 +135,13 @@ #define LWIP_UDP 0 #endif +/* + * PBUF_POOL_BUFSIZE is derived from TCP_MSS even when + * CONFIG_PROT_TCP_LWIP is not defined + */ +#define TCP_MSS 1460 #if defined(CONFIG_PROT_TCP_LWIP) #define LWIP_TCP 1 -#define TCP_MSS 1460 #define TCP_WND CONFIG_LWIP_TCP_WND #define LWIP_WND_SCALE 1 #define TCP_RCV_SCALE 0x7 diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig index 34b9d8afe67..e0de57e2930 100644 --- a/lib/optee/Kconfig +++ b/lib/optee/Kconfig @@ -40,6 +40,7 @@ config OPTEE_TZDRAM_SIZE config BOOTM_OPTEE bool "Support OPTEE bootm command" + depends on LIB_BOOTI || LIB_BOOTM || LIB_BOOTZ select BOOTM_LINUX select OPTEE_IMAGE help diff --git a/lib/smbios.c b/lib/smbios.c index b8c2846277a..d5f18c8bd69 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -66,11 +66,47 @@ struct map_sysinfo { static const struct map_sysinfo sysinfo_to_dt[] = { { .si_node = "system", .si_str = "product", .dt_str = "model", 2 }, - { .si_node = "system", .si_str = "manufacturer", .dt_str = "compatible", 1 }, - { .si_node = "baseboard", .si_str = "product", .dt_str = "model", 2 }, - { .si_node = "baseboard", .si_str = "manufacturer", .dt_str = "compatible", 1 }, + { .si_node = "system", .si_str = "manufacturer", + .dt_str = "compatible", 1 }, + { .si_node = "baseboard", .si_str = "product", + .dt_str = "model", 2 }, + { .si_node = "baseboard", .si_str = "manufacturer", + .dt_str = "compatible", 1 }, + { .si_node = "system-slot", .si_str = "slot-type", + .dt_str = "device_type", 0}, + { .si_node = "system-slot", .si_str = "segment-group-number", + .dt_str = "linux,pci-domain", 0}, }; +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) +static const struct pci_attr_lookup_table pci_attr[] = { + { "pci-host-ecam-generic", SMBIOS_SYSSLOT_TYPE_PCIE, + SMBIOS_SYSSLOT_WIDTH_8X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, SMBIOS_SYSSLOT_CHAR_PCIPME }, + { "pci-host-cam-generic", SMBIOS_SYSSLOT_TYPE_PCI, + SMBIOS_SYSSLOT_WIDTH_32BIT, SMBIOS_SYSSLOT_LENG_SHORT, + SMBIOS_SYSSLOT_CHAR_5V | SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME }, + { "pci-host-thunder-ecam", SMBIOS_SYSSLOT_TYPE_PCIEGEN3, + SMBIOS_SYSSLOT_WIDTH_8X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG }, + { "pci-host-octeontx-ecam", SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16, + SMBIOS_SYSSLOT_WIDTH_16X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG }, + { "pci-host-thunder-pem", SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8, + SMBIOS_SYSSLOT_WIDTH_8X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG }, + { "pci-host-octeontx2-pem", SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16, + SMBIOS_SYSSLOT_WIDTH_16X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG | + SMBIOS_SYSSLOT_CHAR_PCIBIF }, +}; +#endif + /** * struct smbios_ctx - context for writing SMBIOS tables * @@ -95,6 +131,18 @@ struct smbios_ctx { char *last_str; }; +typedef int (*smbios_write_subnode)(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type); + +typedef int (*smbios_write_memnode)(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type); + +typedef int (*smbios_write_memctrlnode)(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + u64 base, u64 sz); + /** * Function prototype to write a specific type of SMBIOS structure * @@ -103,7 +151,7 @@ struct smbios_ctx { * @ctx: context for writing the tables * Return: size of the structure */ -typedef int (*smbios_write_type)(ulong *addr, int handle, +typedef int (*smbios_write_type)(ulong *addr, int *handle, struct smbios_ctx *ctx); /** @@ -222,6 +270,7 @@ static int smbios_get_val_si(struct smbios_ctx * __maybe_unused ctx, { #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) int val; + const struct map_sysinfo *nprop; if (!ctx->dev) return val_def; @@ -240,10 +289,58 @@ static int smbios_get_val_si(struct smbios_ctx * __maybe_unused ctx, */ if (!ofnode_read_u32(ofnode_root(), prop, &val)) return val; + + /* If the node is still missing, try with the mapping values */ + nprop = convert_sysinfo_to_dt(ctx->subnode_name, prop); + if (!ofnode_read_u32(ofnode_root(), nprop->dt_str, &val)) + return val; #endif return val_def; } +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) +static u64 smbios_get_u64_si(struct smbios_ctx * __maybe_unused ctx, + const char * __maybe_unused prop, + int __maybe_unused sysinfo_id, u64 val_def) +{ + size_t len; + void *data; + const fdt32_t *prop_val; + int prop_len; + u64 val = 0; + + if (!ctx->dev) + return val_def; + + if (!sysinfo_get_data(ctx->dev, sysinfo_id, &data, &len)) + return *((u64 *)data); + + if (!IS_ENABLED(CONFIG_OF_CONTROL) || !prop || !ofnode_valid(ctx->node)) + return val_def; + + prop_val = ofnode_read_prop(ctx->node, prop, &prop_len); + if (!prop_val || prop_len < sizeof(fdt32_t) || + prop_len % sizeof(fdt32_t)) { + /* + * If the node or property is not valid fallback and try the root + */ + prop_val = ofnode_read_prop(ofnode_root(), prop, &prop_len); + if (!prop_val || prop_len < sizeof(fdt32_t) || + prop_len % sizeof(fdt32_t)) + return val_def; + } + + /* 64-bit: or 32-bit */ + if (prop_len >= sizeof(fdt32_t) * 2) { + val = ((u64)fdt32_to_cpu(prop_val[0]) << 32) | + fdt32_to_cpu(prop_val[1]); + } else { + val = fdt32_to_cpu(prop_val[0]); + } + return val; +} +#endif + /** * smbios_add_prop_si() - Add a property from the devicetree or sysinfo * @@ -364,7 +461,7 @@ static int smbios_string_table_len(const struct smbios_ctx *ctx) return (ctx->next_ptr + 1) - ctx->eos; } -static int smbios_write_type0(ulong *current, int handle, +static int smbios_write_type0(ulong *current, int *handle, struct smbios_ctx *ctx) { struct smbios_type0 *t; @@ -372,7 +469,7 @@ static int smbios_write_type0(ulong *current, int handle, t = map_sysmem(*current, len); memset(t, 0, len); - fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, handle); + fill_smbios_header(t, SMBIOS_BIOS_INFORMATION, len, *handle); smbios_set_eos(ctx, t->eos); t->vendor = smbios_add_prop_si(ctx, NULL, SYSID_SM_BIOS_VENDOR, "U-Boot"); @@ -423,7 +520,7 @@ static int smbios_write_type0(ulong *current, int handle, return len; } -static int smbios_write_type1(ulong *current, int handle, +static int smbios_write_type1(ulong *current, int *handle, struct smbios_ctx *ctx) { struct smbios_type1 *t; @@ -434,7 +531,7 @@ static int smbios_write_type1(ulong *current, int handle, t = map_sysmem(*current, len); memset(t, 0, len); - fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle); + fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, *handle); smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", @@ -471,7 +568,7 @@ static int smbios_write_type1(ulong *current, int handle, return len; } -static int smbios_write_type2(ulong *current, int handle, +static int smbios_write_type2(ulong *current, int *handle, struct smbios_ctx *ctx) { struct smbios_type2 *t; @@ -485,7 +582,7 @@ static int smbios_write_type2(ulong *current, int handle, */ t = map_sysmem(*current, len); memset(t, 0, len); - fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle); + fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, *handle); /* eos is at the end of the structure */ eos_addr = (u8 *)t + len - sizeof(t->eos); @@ -519,7 +616,7 @@ static int smbios_write_type2(ulong *current, int handle, * t->number_contained_objects = ; */ - t->chassis_handle = handle + 1; + t->chassis_handle = *handle + 1; len = t->hdr.length + smbios_string_table_len(ctx); *current += len; @@ -528,7 +625,7 @@ static int smbios_write_type2(ulong *current, int handle, return len; } -static int smbios_write_type3(ulong *current, int handle, +static int smbios_write_type3(ulong *current, int *handle, struct smbios_ctx *ctx) { struct smbios_type3 *t; @@ -548,7 +645,7 @@ static int smbios_write_type3(ulong *current, int handle, t = map_sysmem(*current, len); memset(t, 0, len); - fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle); + fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, *handle); #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) elem_addr = (u8 *)t + offsetof(struct smbios_type3, sku_number); sku_num_addr = elem_addr + elem_size; @@ -669,7 +766,7 @@ static void smbios_write_type4_dm(struct smbios_type4 *t, #endif } -static int smbios_write_type4(ulong *current, int handle, +static int smbios_write_type4(ulong *current, int *handle, struct smbios_ctx *ctx) { struct smbios_type4 *t; @@ -679,7 +776,7 @@ static int smbios_write_type4(ulong *current, int handle, t = map_sysmem(*current, len); memset(t, 0, len); - fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, handle); + fill_smbios_header(t, SMBIOS_PROCESSOR_INFORMATION, len, *handle); smbios_set_eos(ctx, t->eos); t->socket_design = smbios_add_prop_si(ctx, "socket-design", SYSID_SM_PROCESSOR_SOCKET, NULL); @@ -828,13 +925,14 @@ static int smbios_write_type7_1level(ulong *current, int handle, return len; } -static int smbios_write_type7(ulong *current, int handle, +static int smbios_write_type7(ulong *current, int *handle, struct smbios_ctx *ctx) { int len = 0; int i, level; ofnode parent = ctx->node; struct smbios_ctx ctx_bak; + int hdl_base = *handle; memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); @@ -850,15 +948,1017 @@ static int smbios_write_type7(ulong *current, int handle, return 0; ctx->subnode_name = buf; ctx->node = ofnode_find_subnode(parent, ctx->subnode_name); - len += smbios_write_type7_1level(current, handle++, ctx, i); + *handle = hdl_base + i; + len += smbios_write_type7_1level(current, *handle, ctx, i); memcpy(ctx, &ctx_bak, sizeof(*ctx)); } + + return len; +} + +static int smbios_scan_subnodes(ulong *current, struct smbios_ctx *ctx, + int *handle, smbios_write_subnode cb, int type) +{ + ofnode child; + int i; + int hdl_base = *handle; + int len = 0; + struct smbios_ctx ctx_bak; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + + for (i = 0, child = ofnode_first_subnode(ctx->node); + ofnode_valid(child); child = ofnode_next_subnode(child), i++) { + ctx->node = child; + *handle = hdl_base + i; + len += cb(current, *handle, ctx, i, type); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + } + + return len; +} + +static void smbios_lookup_pci_attr(struct smbios_ctx *ctx, + struct smbios_type9 *t) +{ + const char *compatible; + u32 addr_cells, size_cells, total_cells; + const fdt32_t *reg; + int reglen; + int i; + + /* default attributes */ + t->slot_type = SMBIOS_SYSSLOT_TYPE_PCI; + t->slot_data_bus_width = SMBIOS_SYSSLOT_WIDTH_UNKNOWN; + t->slot_characteristics_1 = SMBIOS_SYSSLOT_CHAR_UND; + t->current_usage = SMBIOS_SYSSLOT_USAGE_UNKNOWN; + t->slot_length = SMBIOS_SYSSLOT_LENG_UNKNOWN; + t->segment_group_number = smbios_get_val_si(ctx, "segment-group-number", + SYSID_NONE, + SMBIOS_SYSSLOT_SGGNUM_UND); + + /* + * Get #address-cells and #size-cells dynamically + * Default 3 for #address-cells and 2 for #size-cells + */ + addr_cells = ofnode_read_u32_default(ctx->node, "#address-cells", 3); + size_cells = ofnode_read_u32_default(ctx->node, "#size-cells", 2); + total_cells = addr_cells + size_cells; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(ctx->node, "reg", ®len); + if (reg && reglen > addr_cells * sizeof(*reg)) { + /* First address-cell: Bus Number */ + if (addr_cells >= 1) + t->bus_number = fdt32_to_cpu(reg[0]); + /* Second address-cell: Device/Function */ + if (addr_cells >= 2) + t->device_function_number.data = fdt32_to_cpu(reg[1]); + /* + * Third address-cell 'Register Offset' and the following + * size-cell bytes are not useful for SMBIOS type 9, just + * ignore them. + */ + /* + * As neither PCI IRQ Routing Table ($PIRQ) nor FDT + * property to represent a Slot ID, try to derive a + * Slot ID programmatically. + */ + t->slot_id = t->device_function_number.fields.dev_num | + (t->bus_number << 5); + } + + /* Read 'compatible' property */ + compatible = ofnode_read_string(ctx->node, "compatible"); + if (!compatible) + return; + + for (i = 0; i < ARRAY_SIZE(pci_attr); i++) { + if (strstr(compatible, pci_attr[i].str)) { + t->slot_type = pci_attr[i].slot_type; + t->slot_data_bus_width = pci_attr[i].data_bus_width; + t->slot_length = pci_attr[i].slot_length; + t->slot_characteristics_1 = pci_attr[i].chara1; + t->slot_characteristics_2 = pci_attr[i].chara2; + /* mark it as in-use arbitrarily */ + t->current_usage = SMBIOS_SYSSLOT_USAGE_INUSE; + return; + } + } +} + +static void smbios_write_type9_fields(struct smbios_ctx *ctx, + struct smbios_type9 *t) +{ + t->slot_type = smbios_get_val_si(ctx, "slot-type", SYSID_NONE, + SMBIOS_SYSSLOT_TYPE_UNKNOWN); + t->slot_data_bus_width = + smbios_get_val_si(ctx, "data-bus-width", + SYSID_NONE, SMBIOS_SYSSLOT_WIDTH_UNKNOWN); + t->current_usage = smbios_get_val_si(ctx, "current-usage", SYSID_NONE, + SMBIOS_SYSSLOT_USAGE_UNKNOWN); + t->slot_length = smbios_get_val_si(ctx, "slot-length", SYSID_NONE, + SMBIOS_SYSSLOT_LENG_UNKNOWN); + t->slot_id = smbios_get_val_si(ctx, "slot-id", SYSID_NONE, 0); + t->slot_characteristics_1 = + smbios_get_val_si(ctx, "slot-characteristics-1", SYSID_NONE, + SMBIOS_SYSSLOT_CHAR_UND); + t->slot_characteristics_2 = smbios_get_val_si(ctx, + "slot-characteristics-2", + SYSID_NONE, 0); + t->segment_group_number = smbios_get_val_si(ctx, "segment-group-number", + SYSID_NONE, 0); + t->bus_number = smbios_get_val_si(ctx, "bus-number", SYSID_NONE, 0); + t->device_function_number.data = + smbios_get_val_si(ctx, "device-function-number", SYSID_NONE, 0); +} + +static int smbios_write_type9_1slot(ulong *current, int handle, + struct smbios_ctx *ctx, + int __maybe_unused idx, int devtype) +{ + struct smbios_type9 *t; + int len = sizeof(*t); + u8 pgroups_cnt; + u8 *eos_addr; + size_t pgroups_size; + void *wp; + + pgroups_cnt = smbios_get_val_si(ctx, "peer-grouping-count", + SYSID_NONE, 0); + pgroups_size = pgroups_cnt * SMBIOS_TYPE9_PGROUP_SIZE; + + /* + * reserve the space for the dynamic bytes of peer_groups. + * TODO: + * peer_groups = * SMBIOS_TYPE9_PGROUP_SIZE + */ + len += pgroups_size; + + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_SYSTEM_SLOTS, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* Write the general fields */ + t->peer_grouping_count = pgroups_cnt; + t->socket_design = smbios_add_prop_si(ctx, "socket-design", SYSID_NONE, + NULL); + t->electrical_bus_width = smbios_get_val_si(ctx, "data-bus-width", + SYSID_NONE, 0); + + /* skip the reserved peer groups and write the following fields from eos */ + /* t->slot_height */ + wp = eos_addr - sizeof(t->slot_height); + *((u8 *)wp) = smbios_get_val_si(ctx, "slot-height", SYSID_NONE, 0); + /* t->slot_pitch */ + wp -= sizeof(t->slot_pitch); + *((u16 *)wp) = smbios_get_val_si(ctx, "slot-pitch", SYSID_NONE, 0); + /* t->slot_physical_width */ + wp -= sizeof(t->slot_physical_width); + *((u8 *)wp) = smbios_get_val_si(ctx, "slot-physical-width", SYSID_NONE, 0); + /* t->slot_information */ + wp -= sizeof(t->slot_information); + *((u8 *)wp) = smbios_get_val_si(ctx, "slot-information", SYSID_NONE, 0); + + /* For PCI, some fields can be extracted from FDT node */ + if (devtype == SMBIOS_SYSSLOT_TYPE_PCI) + /* Populate PCI attributes from existing PCI properties */ + smbios_lookup_pci_attr(ctx, t); + else if (devtype == SMBIOS_SYSSLOT_TYPE_UNKNOWN) { + /* Properties that expected in smbios subnode 'system-slot' */ + smbios_write_type9_fields(ctx, t); + } + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_scan_slot_type(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + int i = 0; + struct smbios_ctx ctx_bak; + ofnode child; + const struct map_sysinfo *prop; + int hdl_base = *handle; + int len = 0; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + prop = convert_sysinfo_to_dt(ctx->subnode_name, "slot-type"); + for (child = ofnode_first_subnode(ofnode_root()); ofnode_valid(child); + child = ofnode_next_subnode(child)) { + const char *dev_type_str; + u8 dev_type = SMBIOS_SYSSLOT_TYPE_UNKNOWN; + + dev_type_str = ofnode_read_string(child, prop->dt_str); + if (!dev_type_str) + continue; + + if (!strcmp(dev_type_str, "pci")) + dev_type = SMBIOS_SYSSLOT_TYPE_PCI; + else if (!strcmp(dev_type_str, "isa")) + dev_type = SMBIOS_SYSSLOT_TYPE_ISA; + else if (!strcmp(dev_type_str, "pcmcia")) + dev_type = SMBIOS_SYSSLOT_TYPE_PCMCIA; + else + continue; + + *handle = hdl_base + i; + ctx->node = child; + len += smbios_write_type9_1slot(current, *handle, ctx, 0, + dev_type); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + i++; + } + + return len; +} + +static int smbios_write_type9(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + int len; + + /* TODO: Get system slot information via pci subsystem */ + if (!IS_ENABLED(CONFIG_OF_CONTROL)) + return 0; /* Error, return 0-length */ + + len = smbios_scan_subnodes(current, ctx, handle, + smbios_write_type9_1slot, + SMBIOS_SYSSLOT_TYPE_UNKNOWN); + if (len) + return len; + + /* if no subnode under 'system-slot', try scan the entire FDT */ + len = smbios_scan_slot_type(current, handle, ctx); + + return len; +} + +static u64 smbios_pop_size_from_memory_node(ofnode node) +{ + const fdt32_t *reg; + int len; + u64 size_bytes; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(node, "reg", &len); + if (!reg || len < sizeof(fdt32_t) * 4 || len % sizeof(fdt32_t)) + return 0; + + /* Combine hi/lo for size (typically 64-bit) */ + size_bytes = ((u64)fdt32_to_cpu(reg[2]) << 32) | fdt32_to_cpu(reg[3]); + + return size_bytes; +} + +static int +smbios_write_type16_sum_memory_nodes(ulong *current, int handle, + struct smbios_ctx *ctx, u16 cnt, u64 size) +{ + struct smbios_type16 *t; + int len = sizeof(*t); + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_PHYS_MEMORY_ARRAY, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* default attributes */ + t->location = SMBIOS_MA_LOCATION_MOTHERBOARD; + t->use = SMBIOS_MA_USE_SYSTEM; + t->mem_err_corr = SMBIOS_MA_ERRCORR_UNKNOWN; + t->mem_err_info_hdl = SMBIOS_MA_ERRINFO_NONE; + t->num_of_mem_dev = cnt; + + /* Use extended field */ + t->max_cap = cpu_to_le32(0x80000000); + t->ext_max_cap = cpu_to_le64(size >> 10); /* In KB */ + + /* Save the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + *((u16 *)hdl) = handle; + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static void +smbios_pop_type16_from_memcontroller_node(ofnode node, struct smbios_type16 *t) +{ + ofnode child; + int count = 0; + u64 total = 0; + + /* default attributes */ + t->location = SMBIOS_MA_LOCATION_MOTHERBOARD; + t->use = SMBIOS_MA_USE_SYSTEM; + t->mem_err_info_hdl = SMBIOS_MA_ERRINFO_NONE; + + /* Check custom property 'ecc-enabled' */ + if (ofnode_read_bool(node, "ecc-enabled")) + t->mem_err_corr = SMBIOS_MA_ERRCORR_SBITECC; + else + t->mem_err_corr = SMBIOS_MA_ERRCORR_UNKNOWN; + + /* Read subnodes with 'size' property */ + for (child = ofnode_first_subnode(node); ofnode_valid(child); + child = ofnode_next_subnode(child)) { + u64 sz = 0; + const fdt32_t *size; + int len; + + size = ofnode_read_prop(child, "size", &len); + if (!size || len < sizeof(fdt32_t) || len % sizeof(fdt32_t)) + continue; + + /* 64-bit size: or 32-bit size */ + if (len >= sizeof(fdt32_t) * 2) + sz = ((u64)fdt32_to_cpu(size[0]) << 32) | + fdt32_to_cpu(size[1]); + else + sz = fdt32_to_cpu(size[0]); + + count++; + total += sz; + } + + /* + * Number of memory devices associated with this array + * (i.e., how many Type17 entries link to this Type16 array) + */ + t->num_of_mem_dev = count; + + /* Use extended field */ + t->max_cap = cpu_to_le32(0x80000000); + t->ext_max_cap = cpu_to_le64(total >> 10); /* In KB */ +} + +static void smbios_pop_type16_si(struct smbios_ctx *ctx, + struct smbios_type16 *t) +{ + t->location = smbios_get_val_si(ctx, "location", SYSID_NONE, + SMBIOS_MA_LOCATION_UNKNOWN); + t->use = smbios_get_val_si(ctx, "use", SYSID_NONE, + SMBIOS_MA_USE_UNKNOWN); + t->mem_err_corr = smbios_get_val_si(ctx, "memory-error-correction", SYSID_NONE, + SMBIOS_MA_ERRCORR_UNKNOWN); + t->max_cap = smbios_get_val_si(ctx, "maximum-capacity", SYSID_NONE, 0); + t->mem_err_info_hdl = smbios_get_val_si(ctx, "memory-error-information-handle", + SYSID_NONE, SMBIOS_MA_ERRINFO_NONE); + t->num_of_mem_dev = smbios_get_val_si(ctx, "number-of-memory-devices", SYSID_NONE, 1); + t->ext_max_cap = smbios_get_u64_si(ctx, "extended-maximum-capacity", SYSID_NONE, 0); +} + +static int smbios_write_type16_1array(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type) +{ + struct smbios_type16 *t; + int len = sizeof(*t); + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_PHYS_MEMORY_ARRAY, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + if (type == SMBIOS_MEM_CUSTOM) + smbios_pop_type16_si(ctx, t); + else if (type == SMBIOS_MEM_FDT_MEMCON_NODE) + smbios_pop_type16_from_memcontroller_node(ctx->node, t); + + /* Save the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + *((u16 *)hdl + idx) = handle; + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type16(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + int len; + struct smbios_ctx ctx_bak; + ofnode child; + int idx; + u64 total = 0; + int count = 0; + int hdl_base = *handle; + + if (!IS_ENABLED(CONFIG_OF_CONTROL)) + return 0; /* Error, return 0-length */ + + /* Step 1: Scan any subnode exists under 'memory-array' */ + len = smbios_scan_subnodes(current, ctx, handle, + smbios_write_type16_1array, + SMBIOS_MEM_CUSTOM); + if (len) + return len; + + /* Step 2: Scan 'memory' node from the entire FDT */ + for (child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *str; + + /* Look up for 'device_type = "memory"' */ + str = ofnode_read_string(child, "device_type"); + if (str && !strcmp(str, "memory")) { + count++; + total += smbios_pop_size_from_memory_node(child); + } + } + /* + * Generate one type16 instance for all 'memory' nodes, + * use idx=0 implicitly + */ + if (count) + len += smbios_write_type16_sum_memory_nodes(current, *handle, + ctx, count, total); + + /* Step 3: Scan 'memory-controller' node from the entire FDT */ + /* idx starts from 1 */ + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + for (idx = 1, child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *compat; + const char *name; + + /* + * Look up for node with name or property 'compatible' + * containing 'memory-controller'. + */ + name = ofnode_get_name(child); + compat = ofnode_read_string(child, "compatible"); + if ((!compat || !strstr(compat, "memory-controller")) && + (!name || !strstr(name, "memory-controller"))) + continue; + + *handle = hdl_base + idx; + ctx->node = child; + /* + * Generate one type16 instance for each 'memory-controller' + * node, sum the 'size' of all subnodes. + */ + len += smbios_write_type16_1array(current, *handle, ctx, idx, + SMBIOS_MEM_FDT_MEMCON_NODE); + idx++; + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + } + + return len; +} + +static void smbios_pop_type17_general_si(struct smbios_ctx *ctx, + struct smbios_type17 *t) +{ + t->mem_err_info_hdl = + smbios_get_val_si(ctx, "memory-error-information-handle", + SYSID_NONE, SMBIOS_MD_ERRINFO_NONE); + t->total_width = smbios_get_val_si(ctx, "total-width", SYSID_NONE, 0); + t->data_width = smbios_get_val_si(ctx, "data-width", SYSID_NONE, 0); + t->form_factor = smbios_get_val_si(ctx, "form-factor", + SYSID_NONE, SMBIOS_MD_FF_UNKNOWN); + t->dev_set = smbios_get_val_si(ctx, "device-set", SYSID_NONE, + SMBIOS_MD_DEVSET_UNKNOWN); + t->dev_locator = smbios_add_prop_si(ctx, "device-locator", SYSID_NONE, + NULL); + t->bank_locator = smbios_add_prop_si(ctx, "bank-locator", SYSID_NONE, + NULL); + t->mem_type = smbios_get_val_si(ctx, "memory-type", + SYSID_NONE, SMBIOS_MD_TYPE_UNKNOWN); + t->type_detail = smbios_get_val_si(ctx, "type-detail", + SYSID_NONE, SMBIOS_MD_TD_UNKNOWN); + t->speed = smbios_get_val_si(ctx, "speed", SYSID_NONE, + SMBIOS_MD_SPEED_UNKNOWN); + t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", SYSID_NONE, + NULL); + t->serial_number = smbios_add_prop_si(ctx, "serial-number", SYSID_NONE, + NULL); + t->asset_tag = smbios_add_prop_si(ctx, "asset-tag", SYSID_NONE, NULL); + t->part_number = smbios_add_prop_si(ctx, "part-number", SYSID_NONE, + NULL); + t->attributes = smbios_get_val_si(ctx, "attributes", SYSID_NONE, + SMBIOS_MD_ATTR_RANK_UNKNOWN); + t->config_mem_speed = smbios_get_val_si(ctx, "configured-memory-speed", + SYSID_NONE, + SMBIOS_MD_CONFSPEED_UNKNOWN); + t->min_voltage = smbios_get_val_si(ctx, "minimum-voltage", SYSID_NONE, + SMBIOS_MD_VOLTAGE_UNKNOWN); + t->max_voltage = smbios_get_val_si(ctx, "maximum-voltage", SYSID_NONE, + SMBIOS_MD_VOLTAGE_UNKNOWN); + t->config_voltage = smbios_get_val_si(ctx, "configured-voltage", + SYSID_NONE, + SMBIOS_MD_VOLTAGE_UNKNOWN); + t->mem_tech = smbios_get_val_si(ctx, "memory-technology", + SYSID_NONE, SMBIOS_MD_TECH_UNKNOWN); + t->mem_op_mode_cap = + smbios_get_val_si(ctx, "memory-operating-mode-capability", + SYSID_NONE, SMBIOS_MD_OPMC_UNKNOWN); + t->fw_ver = smbios_add_prop_si(ctx, "firmware-version", SYSID_NONE, + NULL); + t->module_man_id = smbios_get_val_si(ctx, "module-manufacturer-id", + SYSID_NONE, 0); + t->module_prod_id = smbios_get_val_si(ctx, "module-product-id", + SYSID_NONE, 0); + t->mem_subsys_con_man_id = + smbios_get_val_si(ctx, + "memory-subsystem-controller-manufacturer-id", + SYSID_NONE, 0); + t->mem_subsys_con_prod_id = + smbios_get_val_si(ctx, + "memory-subsystem-controller-product-id", + SYSID_NONE, 0); + t->nonvolatile_size = smbios_get_u64_si(ctx, "non-volatile-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->volatile_size = smbios_get_u64_si(ctx, "volatile-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->cache_size = smbios_get_u64_si(ctx, "cache-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->logical_size = smbios_get_u64_si(ctx, "logical-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->ext_speed = smbios_get_val_si(ctx, "extended-speed", SYSID_NONE, 0); + t->ext_config_mem_speed = + smbios_get_val_si(ctx, "extended-configured-memory-speed", + SYSID_NONE, 0); + t->pmic0_man_id = smbios_get_val_si(ctx, "pmic0-manufacturer-id", + SYSID_NONE, 0); + t->pmic0_rev_num = smbios_get_val_si(ctx, "pmic0-revision-number", + SYSID_NONE, 0); + t->rcd_man_id = smbios_get_val_si(ctx, "rcd-manufacturer-id", + SYSID_NONE, 0); + t->rcd_rev_num = smbios_get_val_si(ctx, "rcd-revision-number", + SYSID_NONE, 0); +} + +static void +smbios_pop_type17_size_from_memory_node(ofnode node, struct smbios_type17 *t) +{ + const fdt32_t *reg; + int len; + u64 sz; + u32 size_mb; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(node, "reg", &len); + if (!reg || len < sizeof(fdt32_t) * 4 || len % sizeof(fdt32_t)) + return; + + /* Combine hi/lo for size (typically 64-bit) */ + sz = ((u64)fdt32_to_cpu(reg[2]) << 32) | fdt32_to_cpu(reg[3]); + + /* Convert size to MB */ + size_mb = (u32)(sz >> 20); /* 1 MB = 2^20 */ + if (size_mb < SMBIOS_MD_SIZE_EXT) { + t->size = cpu_to_le16(size_mb); + t->ext_size = 0; + return; + } + + t->size = cpu_to_le16(SMBIOS_MD_SIZE_EXT); /* Signal extended used */ + t->ext_size = cpu_to_le32((u32)(sz >> 10)); /* In KB */ +} + +static void smbios_pop_type17_size_si(struct smbios_ctx *ctx, + struct smbios_type17 *t) +{ + t->size = smbios_get_val_si(ctx, "size", SYSID_NONE, + SMBIOS_MD_SIZE_UNKNOWN); + t->ext_size = smbios_get_val_si(ctx, "extended-size", SYSID_NONE, 0); +} + +static int +smbios_scan_memctrl_subnode(ulong *current, int *handle, struct smbios_ctx *ctx, + int idx, smbios_write_memctrlnode cb) +{ + int total_len = 0; + ofnode child; + int i = 0; + int hdl_base = *handle; + u64 base = 0; + + /* + * Enumerate all subnodes of 'memory-controller' that contain 'size' + * property and generate one instance for each. + */ + for (child = ofnode_first_subnode(ctx->node); ofnode_valid(child); + child = ofnode_next_subnode(child)) { + u64 sz = 0; + const fdt32_t *size; + int proplen; + + size = ofnode_read_prop(child, "size", &proplen); + if (!size || proplen < sizeof(fdt32_t) || + proplen % sizeof(fdt32_t)) + continue; + + /* 64-bit size: or 32-bit size */ + if (proplen >= sizeof(fdt32_t) * 2) + sz = ((u64)fdt32_to_cpu(size[0]) << 32) | + fdt32_to_cpu(size[1]); + else + sz = fdt32_to_cpu(size[0]); + + *handle = hdl_base + i; + total_len += cb(current, *handle, ctx, idx, base, sz); + base += sz; + i++; + } + + return total_len; +} + +static int +smbios_write_type17_from_memctrl_node(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + u64 __maybe_unused base, u64 sz) +{ + struct smbios_type17 *t; + int len; + u8 *eos_addr; + u32 size_mb; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_DEVICE, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->phy_mem_array_hdl = *((u16 *)hdl + idx); + + /* Convert to MB */ + size_mb = (u32)(sz >> 20); + if (size_mb < SMBIOS_MD_SIZE_EXT) { + /* Use 16-bit size field */ + t->size = cpu_to_le16(size_mb); /* In MB */ + t->ext_size = cpu_to_le32(0); + } else { + /* Signal use of extended size field */ + t->size = cpu_to_le16(SMBIOS_MD_SIZE_EXT); + t->ext_size = cpu_to_le32((u32)(sz >> 10)); /* In KB */ + } + + /* Write other general fields */ + smbios_pop_type17_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type17_mem(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type) +{ + struct smbios_type17 *t; + int len; + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_DEVICE, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + if (type == SMBIOS_MEM_CUSTOM) { + smbios_pop_type17_size_si(ctx, t); + + t->phy_mem_array_hdl = + smbios_get_val_si(ctx, "physical-memory-array-handle", + SYSID_NONE, 0); + } else if (type == SMBIOS_MEM_FDT_MEM_NODE) { + smbios_pop_type17_size_from_memory_node(ctx->node, t); + + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->phy_mem_array_hdl = *((u16 *)hdl + idx); + } + + /* Write other general fields */ + smbios_pop_type17_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_scan_mem_nodes(ulong *current, int *handle, + struct smbios_ctx *ctx, + smbios_write_memnode mem_cb, + int *idx) +{ + int len = 0; + struct smbios_ctx ctx_bak; + ofnode child; + int hdl_base = *handle; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + + for (child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *str; + + /* Look up for 'device_type = "memory"' */ + str = ofnode_read_string(child, "device_type"); + if (!str || strcmp(str, "memory")) + continue; + + ctx->node = child; + *handle = hdl_base + *idx; + /* Generate one instance for each 'memory' node */ + len += mem_cb(current, *handle, ctx, *idx, + SMBIOS_MEM_FDT_MEM_NODE); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + (*idx)++; + } + + return len; +} + +static int smbios_scan_mctrl_subnodes(ulong *current, int *handle, + struct smbios_ctx *ctx, + smbios_write_memctrlnode mctrl_wcb, + int *idx) +{ + int len = 0; + struct smbios_ctx ctx_bak; + ofnode child; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + + for (child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *compat; + const char *name; + + /* + * Look up for node with name or property 'compatible' + * containing 'memory-controller'. + */ + name = ofnode_get_name(child); + compat = ofnode_read_string(child, "compatible"); + if ((!compat || !strstr(compat, "memory-controller")) && + (!name || !strstr(name, "memory-controller"))) + continue; + + (*handle)++; + ctx->node = child; + /* + * Generate one instance for each subnode of + * 'memory-controller' which contains property 'size'. + */ + len += smbios_scan_memctrl_subnode(current, handle, ctx, + *idx, mctrl_wcb); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + (*idx)++; + } return len; } +static int smbios_write_type1719(ulong *current, int *handle, + struct smbios_ctx *ctx, + smbios_write_memnode mem_cb, + smbios_write_memctrlnode mctrl_wcb) +{ + int len = 0; + int idx; + + if (!IS_ENABLED(CONFIG_OF_CONTROL)) + return 0; /* Error, return 0-length */ + + /* Step 1: Scan any subnode exists */ + len = smbios_scan_subnodes(current, ctx, handle, mem_cb, + SMBIOS_MEM_CUSTOM); + if (len) + return len; + + /* Step 2: Scan 'memory' node from the entire FDT */ + idx = 0; + len += smbios_scan_mem_nodes(current, handle, ctx, mem_cb, &idx); + + /* Step 3: Scan 'memory-controller' node from the entire FDT */ + len += smbios_scan_mctrl_subnodes(current, handle, ctx, mctrl_wcb, &idx); + + return len; +} + +static int smbios_write_type17(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + return smbios_write_type1719(current, handle, ctx, + smbios_write_type17_mem, + smbios_write_type17_from_memctrl_node); +} + +static void smbios_pop_type19_general_si(struct smbios_ctx *ctx, + struct smbios_type19 *t) +{ + t->partition_wid = + smbios_get_val_si(ctx, "partition-width ", + SYSID_NONE, SMBIOS_MAMA_PW_DEF); +} + +static void smbios_pop_type19_addr_si(struct smbios_ctx *ctx, + struct smbios_type19 *t) +{ + t->start_addr = smbios_get_val_si(ctx, "starting-address", SYSID_NONE, + 0); + t->end_addr = smbios_get_val_si(ctx, "ending-address", SYSID_NONE, 0); + t->ext_start_addr = smbios_get_u64_si(ctx, "extended-starting-address", + SYSID_NONE, 0); + t->ext_end_addr = smbios_get_u64_si(ctx, "extended-ending-address", + SYSID_NONE, 0); +} + +static void +smbios_pop_type19_addr_from_memory_node(ofnode node, struct smbios_type19 *t) +{ + const fdt32_t *reg; + int len; + u64 sz; + u64 addr; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(node, "reg", &len); + if (!reg || len < sizeof(fdt32_t) * 4 || len % sizeof(fdt32_t)) + return; + + /* Combine hi/lo for size and address (typically 64-bit) */ + sz = ((u64)fdt32_to_cpu(reg[2]) << 32) | fdt32_to_cpu(reg[3]); + addr = ((u64)fdt32_to_cpu(reg[0]) << 32) | fdt32_to_cpu(reg[1]); + + t->ext_start_addr = cpu_to_le64(addr); + t->ext_end_addr = cpu_to_le64(addr + sz - 1); + + /* If address range fits in 32-bit, populate legacy fields */ + if ((addr + sz - 1) <= 0xFFFFFFFFULL) { + t->start_addr = cpu_to_le32((u32)addr); + t->end_addr = cpu_to_le32((u32)(addr + sz - 1)); + } else { + t->start_addr = cpu_to_le32(0xFFFFFFFF); + t->end_addr = cpu_to_le32(0xFFFFFFFF); + } +} + +static int +smbios_write_type19_from_memctrl_node(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + u64 base, u64 sz) +{ + struct smbios_type19 *t; + int len; + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->mem_array_hdl = *((u16 *)hdl + idx); + + t->ext_start_addr = cpu_to_le64(base); + t->ext_end_addr = cpu_to_le64(base + sz - 1); + + if ((base + sz - 1) <= 0xFFFFFFFFULL) { + t->start_addr = cpu_to_le32((u32)base); + t->end_addr = cpu_to_le32((u32)(base + sz - 1)); + } else { + t->start_addr = cpu_to_le32(0xFFFFFFFF); + t->end_addr = cpu_to_le32(0xFFFFFFFF); + } + + /* Write other general fields */ + smbios_pop_type19_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type19_mem(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type) +{ + struct smbios_type19 *t; + int len; + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + if (type == SMBIOS_MEM_CUSTOM) { + smbios_pop_type19_addr_si(ctx, t); + t->mem_array_hdl = smbios_get_val_si(ctx, "memory-array-handle", + SYSID_NONE, 0); + } else if (type == SMBIOS_MEM_FDT_MEM_NODE) { + smbios_pop_type19_addr_from_memory_node(ctx->node, t); + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->mem_array_hdl = *((u16 *)hdl + idx); + } + + /* Write other general fields */ + smbios_pop_type19_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type19(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + return smbios_write_type1719(current, handle, ctx, + smbios_write_type19_mem, + smbios_write_type19_from_memctrl_node); +} + #endif /* #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) */ -static int smbios_write_type32(ulong *current, int handle, +static int smbios_write_type32(ulong *current, int *handle, struct smbios_ctx *ctx) { struct smbios_type32 *t; @@ -866,7 +1966,7 @@ static int smbios_write_type32(ulong *current, int handle, t = map_sysmem(*current, len); memset(t, 0, len); - fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, handle); + fill_smbios_header(t, SMBIOS_SYSTEM_BOOT_INFORMATION, len, *handle); smbios_set_eos(ctx, t->eos); *current += len; @@ -875,7 +1975,7 @@ static int smbios_write_type32(ulong *current, int handle, return len; } -static int smbios_write_type127(ulong *current, int handle, +static int smbios_write_type127(ulong *current, int *handle, struct smbios_ctx *ctx) { struct smbios_type127 *t; @@ -883,7 +1983,7 @@ static int smbios_write_type127(ulong *current, int handle, t = map_sysmem(*current, len); memset(t, 0, len); - fill_smbios_header(t, SMBIOS_END_OF_TABLE, len, handle); + fill_smbios_header(t, SMBIOS_END_OF_TABLE, len, *handle); *current += len; unmap_sysmem(t); @@ -902,6 +2002,12 @@ static struct smbios_write_method smbios_write_funcs[] = { { smbios_write_type7, "cache", }, #endif { smbios_write_type4, "processor"}, +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + { smbios_write_type9, "system-slot"}, + { smbios_write_type16, "memory-array"}, + { smbios_write_type17, "memory-device"}, + { smbios_write_type19, "memory-array-mapped-address"}, +#endif { smbios_write_type32, }, { smbios_write_type127 }, }; @@ -954,7 +2060,8 @@ ulong write_smbios_table(ulong addr) ctx.node = ofnode_find_subnode(parent_node, method->subnode_name); } - len += method->write((ulong *)&addr, handle++, &ctx); + len += method->write((ulong *)&addr, &handle, &ctx); + handle++; } /* diff --git a/lib/uuid.c b/lib/uuid.c index 0a166320e07..3a666d0430d 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -254,6 +254,12 @@ static const struct { NULL, "EFI Conformance Profiles Table", EFI_CONFORMANCE_PROFILES_TABLE_GUID, }, +#if CONFIG_IS_ENABLED(EFI_ECPT) + { + NULL, "EFI EBBR 2.1 Conformance Profile", + EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID, + }, +#endif #ifdef CONFIG_EFI_RISCV_BOOT_PROTOCOL { NULL, "RISC-V Boot", diff --git a/net/bootp.c b/net/bootp.c index 64fca9a42d9..8976936b184 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -19,8 +19,8 @@ #include #include #include "bootp.h" -#ifdef CONFIG_LED_STATUS -#include +#if IS_ENABLED(CONFIG_LED_BOOT) +#include #endif #ifdef CONFIG_BOOTP_RANDOM_DELAY #include "net_rand.h" @@ -87,23 +87,6 @@ static u8 dhcp_option_overload; #define OVERLOAD_SNAME 2 static void dhcp_handler(uchar *pkt, unsigned dest, struct in_addr sip, unsigned src, unsigned len); - -/* For Debug */ -#if 0 -static char *dhcpmsg2str(int type) -{ - switch (type) { - case 1: return "DHCPDISCOVER"; break; - case 2: return "DHCPOFFER"; break; - case 3: return "DHCPREQUEST"; break; - case 4: return "DHCPDECLINE"; break; - case 5: return "DHCPACK"; break; - case 6: return "DHCPNACK"; break; - case 7: return "DHCPRELEASE"; break; - default: return "UNKNOWN/INVALID MSG TYPE"; break; - } -} -#endif #endif static void bootp_add_id(ulong id) @@ -396,8 +379,8 @@ static void bootp_handler(uchar *pkt, unsigned dest, struct in_addr sip, /* * Got a good BOOTP reply. Copy the data into our variables. */ -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF); +#if IS_ENABLED(CONFIG_LED_BOOT) + led_boot_off(); #endif store_net_params(bp); /* Store net parameters from reply */ diff --git a/net/eth-uclass.c b/net/eth-uclass.c index a233912fd8e..5c437143a30 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -14,15 +14,12 @@ #include #include #include -#include #include #include #include #include "eth_internal.h" #include -DECLARE_GLOBAL_DATA_PTR; - /** * struct eth_device_priv - private structure for each Ethernet device * diff --git a/net/lwip/nfs.c b/net/lwip/nfs.c index c3b819a091e..9e6b801e465 100644 --- a/net/lwip/nfs.c +++ b/net/lwip/nfs.c @@ -114,8 +114,10 @@ static int nfs_loop(struct udevice *udev, ulong addr, char *fname, if (!netif) return -1; - nfs_filename = nfs_basename(fname); - nfs_path = nfs_dirname(fname); + strlcpy(nfs_path_buff, fname, sizeof(nfs_path_buff)); + + nfs_filename = nfs_basename(nfs_path_buff); + nfs_path = nfs_dirname(nfs_path_buff); printf("Using %s device\n", udev->name); diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c index 5c3becc68c6..7f3b28b8507 100644 --- a/net/lwip/tftp.c +++ b/net/lwip/tftp.c @@ -368,6 +368,8 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0) ret = CMD_RET_FAILURE; + else + image_load_addr = laddr; out: if (arg != net_boot_file_name) free(arg); diff --git a/net/tftp.c b/net/tftp.c index 5f2e0a2bc06..beb9d08f5a2 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -16,12 +16,9 @@ #include #include #include -#include #include #include "bootp.h" -DECLARE_GLOBAL_DATA_PTR; - /* * We cannot use the 'tftpput' command in xPL phases. Given how the * support is integrated in the code, this is how we disable that support diff --git a/net/wget.c b/net/wget.c index d3642958bf0..49bfb9fcb96 100644 --- a/net/wget.c +++ b/net/wget.c @@ -4,7 +4,6 @@ * Copyright Duncan Hare 2017 */ -#include #include #include #include @@ -17,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* The default, change with environment variable 'httpdstp' */ #define SERVER_PORT 80 diff --git a/scripts/Makefile.xpl b/scripts/Makefile.xpl index 55aeac1038e..c5ddf64c73f 100644 --- a/scripts/Makefile.xpl +++ b/scripts/Makefile.xpl @@ -268,11 +268,11 @@ ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),) INPUTS-y += $(obj)/$(BOARD)-spl.bin endif -ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) +ifneq ($(CONFIG_ARCH_SOCFPGA_GEN5)$(CONFIG_ARCH_SOCFPGA_ARRIA10),) INPUTS-y += $(obj)/$(SPL_BIN).sfp endif -INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex +INPUTS-$(CONFIG_ARCH_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex ifdef CONFIG_ARCH_SUNXI INPUTS-y += $(obj)/sunxi-spl.bin @@ -432,7 +432,7 @@ ifneq ($(CONFIG_$(PHASE_)TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(PHASE_)TEXT_BASE) endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1 else MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage diff --git a/scripts/checkkconfigsymbols.py b/scripts/checkkconfigsymbols.py new file mode 100755 index 00000000000..36c920e7131 --- /dev/null +++ b/scripts/checkkconfigsymbols.py @@ -0,0 +1,482 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0-only + +"""Find Kconfig symbols that are referenced but not defined.""" + +# (c) 2014-2017 Valentin Rothberg +# (c) 2014 Stefan Hengelein +# + + +import argparse +import difflib +import os +import re +import signal +import subprocess +import sys +from multiprocessing import Pool, cpu_count + + +# regex expressions +OPERATORS = r"&|\(|\)|\||\!" +SYMBOL = r"(?:\w*[A-Z0-9]\w*){2,}" +DEF = r"^\s*(?:menu){,1}config\s+(" + SYMBOL + r")\s*" +EXPR = r"(?:" + OPERATORS + r"|\s|" + SYMBOL + r")+" +DEFAULT = r"default\s+.*?(?:if\s.+){,1}" +STMT = r"^\s*(?:if|select|imply|depends\s+on|(?:" + DEFAULT + r"))\s+" + EXPR +SOURCE_SYMBOL = r"(?:\W|\b)+[D]{,1}CONFIG_(" + SYMBOL + r")" + +# regex objects +REGEX_FILE_KCONFIG = re.compile(r".*Kconfig[\.\w+\-]*$") +REGEX_SYMBOL = re.compile(r'(?!\B)' + SYMBOL + r'(?!\B)') +REGEX_SOURCE_SYMBOL = re.compile(SOURCE_SYMBOL) +REGEX_KCONFIG_DEF = re.compile(DEF) +REGEX_KCONFIG_EXPR = re.compile(EXPR) +REGEX_KCONFIG_STMT = re.compile(STMT) +REGEX_FILTER_SYMBOLS = re.compile(r"[A-Za-z0-9]$") +REGEX_NUMERIC = re.compile(r"0[xX][0-9a-fA-F]+|[0-9]+") +REGEX_QUOTES = re.compile("(\"(.*?)\")") + + +def parse_options(): + """The user interface of this module.""" + usage = "Run this tool to detect Kconfig symbols that are referenced but " \ + "not defined in Kconfig. If no option is specified, " \ + "checkkconfigsymbols defaults to check your current tree. " \ + "Please note that specifying commits will 'git reset --hard\' " \ + "your current tree! You may save uncommitted changes to avoid " \ + "losing data." + + parser = argparse.ArgumentParser(description=usage) + + parser.add_argument('-c', '--commit', dest='commit', action='store', + default="", + help="check if the specified commit (hash) introduces " + "undefined Kconfig symbols") + + parser.add_argument('-d', '--diff', dest='diff', action='store', + default="", + help="diff undefined symbols between two commits " + "(e.g., -d commmit1..commit2)") + + parser.add_argument('-f', '--find', dest='find', action='store_true', + default=False, + help="find and show commits that may cause symbols to be " + "missing (required to run with --diff)") + + parser.add_argument('-i', '--ignore', dest='ignore', action='store', + default="", + help="ignore files matching this Python regex " + "(e.g., -i '.*defconfig')") + + parser.add_argument('-s', '--sim', dest='sim', action='store', default="", + help="print a list of max. 10 string-similar symbols") + + parser.add_argument('--force', dest='force', action='store_true', + default=False, + help="reset current Git tree even when it's dirty") + + parser.add_argument('--no-color', dest='color', action='store_false', + default=True, + help="don't print colored output (default when not " + "outputting to a terminal)") + + args = parser.parse_args() + + if args.commit and args.diff: + sys.exit("Please specify only one option at once.") + + if args.diff and not re.match(r"^[\w\-\.\^]+\.\.[\w\-\.\^]+$", args.diff): + sys.exit("Please specify valid input in the following format: " + "\'commit1..commit2\'") + + if args.commit or args.diff: + if not args.force and tree_is_dirty(): + sys.exit("The current Git tree is dirty (see 'git status'). " + "Running this script may\ndelete important data since it " + "calls 'git reset --hard' for some performance\nreasons. " + " Please run this script in a clean Git tree or pass " + "'--force' if you\nwant to ignore this warning and " + "continue.") + + if args.commit: + if args.commit.startswith('HEAD'): + sys.exit("The --commit option can't use the HEAD ref") + + args.find = False + + if args.ignore: + try: + re.match(args.ignore, "this/is/just/a/test.c") + except: + sys.exit("Please specify a valid Python regex.") + + return args + + +def print_undefined_symbols(): + """Main function of this module.""" + args = parse_options() + + global COLOR + COLOR = args.color and sys.stdout.isatty() + + if args.sim and not args.commit and not args.diff: + sims = find_sims(args.sim, args.ignore) + if sims: + print("%s: %s" % (yel("Similar symbols"), ', '.join(sims))) + else: + print("%s: no similar symbols found" % yel("Similar symbols")) + sys.exit(0) + + # dictionary of (un)defined symbols + defined = {} + undefined = {} + + if args.commit or args.diff: + head = get_head() + + # get commit range + commit_a = None + commit_b = None + if args.commit: + commit_a = args.commit + "~" + commit_b = args.commit + elif args.diff: + split = args.diff.split("..") + commit_a = split[0] + commit_b = split[1] + undefined_a = {} + undefined_b = {} + + # get undefined items before the commit + reset(commit_a) + undefined_a, _ = check_symbols(args.ignore) + + # get undefined items for the commit + reset(commit_b) + undefined_b, defined = check_symbols(args.ignore) + + # report cases that are present for the commit but not before + for symbol in sorted(undefined_b): + # symbol has not been undefined before + if symbol not in undefined_a: + files = sorted(undefined_b.get(symbol)) + undefined[symbol] = files + # check if there are new files that reference the undefined symbol + else: + files = sorted(undefined_b.get(symbol) - + undefined_a.get(symbol)) + if files: + undefined[symbol] = files + + # reset to head + reset(head) + + # default to check the entire tree + else: + undefined, defined = check_symbols(args.ignore) + + # now print the output + for symbol in sorted(undefined): + print(red(symbol)) + + files = sorted(undefined.get(symbol)) + print("%s: %s" % (yel("Referencing files"), ", ".join(files))) + + sims = find_sims(symbol, args.ignore, defined) + sims_out = yel("Similar symbols") + if sims: + print("%s: %s" % (sims_out, ', '.join(sims))) + else: + print("%s: %s" % (sims_out, "no similar symbols found")) + + if args.find: + print("%s:" % yel("Commits changing symbol")) + commits = find_commits(symbol, args.diff) + if commits: + for commit in commits: + commit = commit.split(" ", 1) + print("\t- %s (\"%s\")" % (yel(commit[0]), commit[1])) + else: + print("\t- no commit found") + print() # new line + + +def reset(commit): + """Reset current git tree to %commit.""" + execute(["git", "reset", "--hard", commit]) + + +def yel(string): + """ + Color %string yellow. + """ + return "\033[33m%s\033[0m" % string if COLOR else string + + +def red(string): + """ + Color %string red. + """ + return "\033[31m%s\033[0m" % string if COLOR else string + + +def execute(cmd): + """Execute %cmd and return stdout. Exit in case of error.""" + try: + stdout = subprocess.check_output(cmd, stderr=subprocess.STDOUT, shell=False) + stdout = stdout.decode(errors='replace') + except subprocess.CalledProcessError as fail: + exit(fail) + return stdout + + +def find_commits(symbol, diff): + """Find commits changing %symbol in the given range of %diff.""" + commits = execute(["git", "log", "--pretty=oneline", + "--abbrev-commit", "-G", + symbol, diff]) + return [x for x in commits.split("\n") if x] + + +def tree_is_dirty(): + """Return true if the current working tree is dirty (i.e., if any file has + been added, deleted, modified, renamed or copied but not committed).""" + stdout = execute(["git", "status", "--porcelain"]) + for line in stdout: + if re.findall(r"[URMADC]{1}", line[:2]): + return True + return False + + +def get_head(): + """Return commit hash of current HEAD.""" + stdout = execute(["git", "rev-parse", "HEAD"]) + return stdout.strip('\n') + + +def partition(lst, size): + """Partition list @lst into eveni-sized lists of size @size.""" + return [lst[i::size] for i in range(size)] + + +def init_worker(): + """Set signal handler to ignore SIGINT.""" + signal.signal(signal.SIGINT, signal.SIG_IGN) + + +def find_sims(symbol, ignore, defined=[]): + """Return a list of max. ten Kconfig symbols that are string-similar to + @symbol.""" + if defined: + return difflib.get_close_matches(symbol, set(defined), 10) + + pool = Pool(cpu_count(), init_worker) + kfiles = [] + for gitfile in get_files(): + if REGEX_FILE_KCONFIG.match(gitfile): + kfiles.append(gitfile) + + arglist = [] + for part in partition(kfiles, cpu_count()): + arglist.append((part, ignore)) + + for res in pool.map(parse_kconfig_files, arglist): + defined.extend(res[0]) + + return difflib.get_close_matches(symbol, set(defined), 10) + + +def get_files(): + """Return a list of all files in the current git directory.""" + # use 'git ls-files' to get the worklist + stdout = execute(["git", "ls-files"]) + if len(stdout) > 0 and stdout[-1] == "\n": + stdout = stdout[:-1] + + files = [] + for gitfile in stdout.rsplit("\n"): + if ".git" in gitfile or "ChangeLog" in gitfile or \ + ".log" in gitfile or os.path.isdir(gitfile) or \ + gitfile.startswith("tools/"): + continue + files.append(gitfile) + return files + + +def check_symbols(ignore): + """Find undefined Kconfig symbols and return a dict with the symbol as key + and a list of referencing files as value. Files matching %ignore are not + checked for undefined symbols.""" + pool = Pool(cpu_count(), init_worker) + try: + return check_symbols_helper(pool, ignore) + except KeyboardInterrupt: + pool.terminate() + pool.join() + sys.exit(1) + + +def check_symbols_helper(pool, ignore): + """Helper method for check_symbols(). Used to catch keyboard interrupts in + check_symbols() in order to properly terminate running worker processes.""" + source_files = [] + kconfig_files = [] + defined_symbols = [] + referenced_symbols = dict() # {file: [symbols]} + + for gitfile in get_files(): + if REGEX_FILE_KCONFIG.match(gitfile): + kconfig_files.append(gitfile) + else: + if ignore and re.match(ignore, gitfile): + continue + # add source files that do not match the ignore pattern + source_files.append(gitfile) + + # parse source files + arglist = partition(source_files, cpu_count()) + for res in pool.map(parse_source_files, arglist): + referenced_symbols.update(res) + + # parse kconfig files + arglist = [] + for part in partition(kconfig_files, cpu_count()): + arglist.append((part, ignore)) + for res in pool.map(parse_kconfig_files, arglist): + defined_symbols.extend(res[0]) + referenced_symbols.update(res[1]) + defined_symbols = set(defined_symbols) + + # inverse mapping of referenced_symbols to dict(symbol: [files]) + inv_map = dict() + for _file, symbols in referenced_symbols.items(): + for symbol in symbols: + inv_map[symbol] = inv_map.get(symbol, set()) + inv_map[symbol].add(_file) + referenced_symbols = inv_map + + undefined = {} # {symbol: [files]} + for symbol in sorted(referenced_symbols): + # filter some false positives + if symbol == "FOO" or symbol == "BAR" or \ + symbol == "FOO_BAR" or symbol == "XXX": + continue + if symbol not in defined_symbols: + if symbol.endswith("_MODULE"): + # avoid false positives for kernel modules + if symbol[:-len("_MODULE")] in defined_symbols: + continue + undefined[symbol] = referenced_symbols.get(symbol) + return undefined, defined_symbols + + +def parse_source_files(source_files): + """Parse each source file in @source_files and return dictionary with source + files as keys and lists of references Kconfig symbols as values.""" + referenced_symbols = dict() + for sfile in source_files: + referenced_symbols[sfile] = parse_source_file(sfile) + return referenced_symbols + + +def parse_source_file(sfile): + """Parse @sfile and return a list of referenced Kconfig symbols.""" + lines = [] + references = [] + + if not os.path.exists(sfile): + return references + + with open(sfile, "r", encoding='utf-8', errors='replace') as stream: + lines = stream.readlines() + + for line in lines: + if "CONFIG_" not in line: + continue + symbols = REGEX_SOURCE_SYMBOL.findall(line) + for symbol in symbols: + if not REGEX_FILTER_SYMBOLS.search(symbol): + continue + references.append(symbol) + + return references + + +def get_symbols_in_line(line): + """Return mentioned Kconfig symbols in @line.""" + return REGEX_SYMBOL.findall(line) + + +def parse_kconfig_files(args): + """Parse kconfig files and return tuple of defined and references Kconfig + symbols. Note, @args is a tuple of a list of files and the @ignore + pattern.""" + kconfig_files = args[0] + ignore = args[1] + defined_symbols = [] + referenced_symbols = dict() + + for kfile in kconfig_files: + defined, references = parse_kconfig_file(kfile) + defined_symbols.extend(defined) + if ignore and re.match(ignore, kfile): + # do not collect references for files that match the ignore pattern + continue + referenced_symbols[kfile] = references + return (defined_symbols, referenced_symbols) + + +def parse_kconfig_file(kfile): + """Parse @kfile and update symbol definitions and references.""" + lines = [] + defined = [] + references = [] + + if not os.path.exists(kfile): + return defined, references + + with open(kfile, "r", encoding='utf-8', errors='replace') as stream: + lines = stream.readlines() + + for i in range(len(lines)): + line = lines[i] + line = line.strip('\n') + line = line.split("#")[0] # ignore comments + + if REGEX_KCONFIG_DEF.match(line): + symbol_def = REGEX_KCONFIG_DEF.findall(line) + defined.append(symbol_def[0]) + elif REGEX_KCONFIG_STMT.match(line): + line = REGEX_QUOTES.sub("", line) + symbols = get_symbols_in_line(line) + # multi-line statements + while line.endswith("\\"): + i += 1 + line = lines[i] + line = line.strip('\n') + symbols.extend(get_symbols_in_line(line)) + for symbol in set(symbols): + if REGEX_NUMERIC.match(symbol): + # ignore numeric values + continue + references.append(symbol) + + return defined, references + + +def main(): + try: + print_undefined_symbols() + except BrokenPipeError: + # Python flushes standard streams on exit; redirect remaining output + # to devnull to avoid another BrokenPipeError at shutdown + devnull = os.open(os.devnull, os.O_WRONLY) + os.dup2(devnull, sys.stdout.fileno()) + sys.exit(1) # Python exits with error code 1 on EPIPE + + +if __name__ == "__main__": + main() diff --git a/test/Kconfig b/test/Kconfig index 24105c13304..14b5b0e2a9a 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -15,6 +15,7 @@ config SPL_UNIT_TEST bool "Unit tests in SPL" depends on SPL # We need to be able to unbind devices for tests to work + select SPL_DM select SPL_DM_DEVICE_REMOVE help Select this to enable unit tests in SPL. Most test are designed for diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index a56435d053f..56ee1952357 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -31,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; extern U_BOOT_DRIVER(bootmeth_android); extern U_BOOT_DRIVER(bootmeth_cros); +extern U_BOOT_DRIVER(bootmeth_rauc); extern U_BOOT_DRIVER(bootmeth_2script); /* Use this as the vendor for EFI to tell the app to exit boot services */ @@ -1392,6 +1393,62 @@ static int bootflow_efi(struct unit_test_state *uts) } BOOTSTD_TEST(bootflow_efi, UTF_CONSOLE); +/* Test RAUC bootmeth */ +static int bootflow_rauc(struct unit_test_state *uts) +{ + const char *mmc_dev = "mmc10"; + struct bootstd_priv *std; + struct udevice *bootstd; + static const char *order[] = {NULL, NULL}; + const char **old_order; + ofnode root; + ofnode node; + + order[0] = mmc_dev; + + if (!CONFIG_IS_ENABLED(BOOTMETH_RAUC)) + return -EAGAIN; + + /* Enable the requested mmc node since we need a different bootflow */ + root = oftree_root(oftree_default()); + node = ofnode_find_subnode(root, mmc_dev); + ut_assert(ofnode_valid(node)); + ut_assertok(lists_bind_fdt(gd->dm_root, node, NULL, NULL, false)); + + /* Enable the rauc bootmeth */ + ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd)); + ut_assertok(device_bind(bootstd, DM_DRIVER_REF(bootmeth_rauc), + "rauc", 0, ofnode_null(), NULL)); + + /* Change the device and bootmeth order */ + std = dev_get_priv(bootstd); + old_order = std->bootdev_order; + std->bootdev_order = order; + + ut_assertok(bootmeth_set_order("rauc")); + + /* Run scan and list */ + ut_assertok(run_command("bootflow scan", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("bootflow list", 0)); + + ut_assert_nextlinen("Showing all"); + ut_assert_nextlinen("Seq"); + ut_assert_nextlinen("---"); + ut_assert_nextlinen(" 0 rauc ready mmc 0 mmc10.bootdev.whole "); + ut_assert_nextlinen("---"); + ut_assert_skip_to_line("(1 bootflow, 1 valid)"); + + ut_assert_console_end(); + + /* Restore the order used by the device tree */ + std->bootdev_order = old_order; + + return 0; +} +BOOTSTD_TEST(bootflow_rauc, UTF_CONSOLE | UTF_DM | UTF_SCAN_FDT); + /* Check 'bootflow scan' provides a list of images */ static int bootstd_images(struct unit_test_state *uts) { diff --git a/test/cmd/exit.c b/test/cmd/exit.c index fdde054b928..e20bc5f7b98 100644 --- a/test/cmd/exit.c +++ b/test/cmd/exit.c @@ -7,11 +7,8 @@ #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - /* Declare a new exit test */ #define EXIT_TEST(_name, _flags) UNIT_TEST(_name, _flags, exit) diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c index 8b306cc907f..7ed534742f7 100644 --- a/test/cmd/test_echo.c +++ b/test/cmd/test_echo.c @@ -6,14 +6,11 @@ */ #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct test_data { char *cmd; char *expected; diff --git a/test/cmd/test_pause.c b/test/cmd/test_pause.c index 174c31a3852..b2cf60d3e74 100644 --- a/test/cmd/test_pause.c +++ b/test/cmd/test_pause.c @@ -5,12 +5,9 @@ * Copyright 2022, Samuel Dionne-Riel */ -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int lib_test_hush_pause(struct unit_test_state *uts) { /* Test default message */ diff --git a/test/dm/blk.c b/test/dm/blk.c index 1b928b27d9c..f67869107da 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -8,14 +8,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Test that block devices can be created */ static int dm_test_blk_base(struct unit_test_state *uts) { diff --git a/test/dm/i3c.c b/test/dm/i3c.c index 81336e67555..816ecabd722 100644 --- a/test/dm/i3c.c +++ b/test/dm/i3c.c @@ -8,8 +8,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Basic test of the i3c uclass */ static int dm_test_i3c_base(struct unit_test_state *uts) { diff --git a/test/dm/virtio_device.c b/test/dm/virtio_device.c index 53414e4d3a4..c2cd0630d97 100644 --- a/test/dm/virtio_device.c +++ b/test/dm/virtio_device.c @@ -40,6 +40,7 @@ static int dm_test_virtio_base(struct unit_test_state *uts) ut_assertok(virtio_get_status(dev, &status)); ut_asserteq(VIRTIO_CONFIG_S_DRIVER | VIRTIO_CONFIG_S_DRIVER_OK | + VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_FEATURES_OK, status); return 0; diff --git a/test/dm/virtio_rng.c b/test/dm/virtio_rng.c index e404b08484e..5fd56ade586 100644 --- a/test/dm/virtio_rng.c +++ b/test/dm/virtio_rng.c @@ -19,12 +19,19 @@ struct virtio_rng_priv { struct virtqueue *rng_vq; }; +#define BUFFER_SIZE 16 +#define CANARY "CANARYCANARYCANARYCANARY" + /* Test the virtio-rng driver validates the used size */ static int dm_test_virtio_rng_check_len(struct unit_test_state *uts) { struct udevice *bus, *dev; struct virtio_rng_priv *priv; - u8 buffer[16]; + u8 buffer[BUFFER_SIZE + sizeof(CANARY)]; + + /* write known data to buffer */ + memset(buffer, 0xaa, BUFFER_SIZE); + memcpy(buffer + BUFFER_SIZE, CANARY, sizeof(CANARY)); /* check probe success */ ut_assertok(uclass_first_device_err(UCLASS_VIRTIO, &bus)); @@ -44,7 +51,10 @@ static int dm_test_virtio_rng_check_len(struct unit_test_state *uts) priv->rng_vq->vring.used->ring[0].len = U32_MAX; /* check the driver gracefully handles the error */ - ut_asserteq(-EIO, dm_rng_read(dev, buffer, sizeof(buffer))); + dm_rng_read(dev, buffer, BUFFER_SIZE); + + /* check for the canary bytes behind the real buffer */ + ut_asserteq_mem(buffer + BUFFER_SIZE, CANARY, sizeof(CANARY)); return 0; } diff --git a/test/hush/if.c b/test/hush/if.c index ea615b246a9..6117c37e53c 100644 --- a/test/hush/if.c +++ b/test/hush/if.c @@ -32,6 +32,19 @@ static int hush_test_if_base(struct unit_test_state *uts) sprintf(if_formatted, if_format, "false"); ut_asserteq(1, run_command(if_formatted, 0)); + sprintf(if_formatted, if_format, "test"); + ut_asserteq(1, run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "test ''"); + ut_asserteq(1, run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "test 'abc'"); + ut_assertok(run_command(if_formatted, 0)); + + /* Special case: 'test -n' interpreted as 'test -n ""'. */ + sprintf(if_formatted, if_format, "test '-n'"); + ut_asserteq(1, run_command(if_formatted, 0)); + return 0; } HUSH_TEST(hush_test_if_base, 0); @@ -315,3 +328,71 @@ static int hush_test_if_z_operator(struct unit_test_state *uts) return 0; } HUSH_TEST(hush_test_if_z_operator, 0); + +static int hush_test_lbracket_alias(struct unit_test_state *uts) +{ + char if_formatted[128]; + const char *missing_rbracket_error = "[: missing terminating ]"; + + sprintf(if_formatted, if_format, "[ aaa = aaa ]"); + ut_assertok(run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ aaa = bbb ]"); + ut_asserteq(1, run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ aaa = aaa"); + ut_asserteq(1, run_command(if_formatted, 0)); + ut_assert_nextline(missing_rbracket_error); + + sprintf(if_formatted, if_format, "[ aaa = bbb"); + ut_asserteq(1, run_command(if_formatted, 0)); + ut_assert_nextline(missing_rbracket_error); + + sprintf(if_formatted, if_format, "[ aaa = aaa]"); + ut_asserteq(1, run_command(if_formatted, 0)); + ut_assert_nextline(missing_rbracket_error); + + sprintf(if_formatted, if_format, "[ aaa = bbb]"); + ut_asserteq(1, run_command(if_formatted, 0)); + ut_assert_nextline(missing_rbracket_error); + + sprintf(if_formatted, if_format, "[ aaa != aaa -o bbb != bbb ]"); + ut_asserteq(1, run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ aaa != aaa -o bbb = bbb ]"); + ut_assertok(run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ ! aaa != aaa -o ! bbb != bbb ]"); + ut_assertok(run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ ! aaa != aaa -o ! bbb = bbb ]"); + ut_assertok(run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ ]"); + ut_asserteq(1, run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "["); + ut_asserteq(1, run_command(if_formatted, 0)); + ut_assert_nextline(missing_rbracket_error); + + sprintf(if_formatted, if_format, "[ '' ]"); + ut_asserteq(1, run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ ''"); + ut_asserteq(1, run_command(if_formatted, 0)); + ut_assert_nextline(missing_rbracket_error); + + sprintf(if_formatted, if_format, "[ 'abc' ]"); + ut_assertok(run_command(if_formatted, 0)); + + sprintf(if_formatted, if_format, "[ 'abc'"); + ut_asserteq(1, run_command(if_formatted, 0)); + ut_assert_nextline(missing_rbracket_error); + + /* Special case: '[ -n ]' interpreted as '[ -n "" ]'. */ + sprintf(if_formatted, if_format, "[ -n ]"); + ut_asserteq(1, run_command(if_formatted, 0)); + + return 0; +} +HUSH_TEST(hush_test_lbracket_alias, UTF_CONSOLE); diff --git a/test/lib/test_print.c b/test/lib/test_print.c index cd7f3f85769..2aeb034b121 100644 --- a/test/lib/test_print.c +++ b/test/lib/test_print.c @@ -7,13 +7,10 @@ #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int test_print_freq(struct unit_test_state *uts, uint64_t freq, char *expected) { diff --git a/test/log/log_filter.c b/test/log/log_filter.c index 8622dcf2913..147b83980cf 100644 --- a/test/log/log_filter.c +++ b/test/log/log_filter.c @@ -5,12 +5,10 @@ #include #include -#include +#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Test invalid options */ static int log_test_filter_invalid(struct unit_test_state *uts) { diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py index b8a22b22806..800376b1e7d 100644 --- a/test/py/tests/fs_helper.py +++ b/test/py/tests/fs_helper.py @@ -7,9 +7,97 @@ import re import os +import shutil from subprocess import call, check_call, check_output, CalledProcessError +from subprocess import DEVNULL +import tempfile -def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000): +# size_gran (int): Size granularity of file system image in bytes +SIZE_GRAN = 1 << 20 + + +class FsHelper: + """Creating a filesystem containing test files + + Usage: + with FsHelper(ubman.config, 'ext4', 10, 'mmc1') as fsh: + # create files in the self.srcdir directory + fsh.mk_fs() + # Now use the filesystem + + # The filesystem and srcdir are erased after the 'with' statement. + + It is also possible to use an existing srcdir: + + with FsHelper(ubman.config, 'fat32', 10, 'usb2') as fsh: + fsh.srcdir = src_dir + fsh.mk_fs() + ... + + Properties: + fs_img (str): Filename for the filesystem image + """ + def __init__(self, config, fs_type, size_mb, prefix): + """Set up a new object + + Args: + config (u_boot_config): U-Boot configuration + fs_type (str): File system type: one of ext2, ext3, ext4, vfat, + fat12, fat16, fat32, exfat, fs_generic (which means vfat) + size_mb (int): Size of file system in MB + prefix (str): Prefix string of volume's file name + """ + if fs_type not in ['fat12', 'fat16', 'fat32', 'vfat', + 'ext2', 'ext3', 'ext4', + 'exfat', 'fs_generic']: + raise ValueError(f"Unsupported filesystem type '{fs_type}'") + + self.config = config + self.fs_type = fs_type + self.size_mb = size_mb + self.prefix = prefix + self.quiet = True + self.fs_img = None + self.tmpdir = None + self.srcdir = None + self._do_cleanup = False + + def mk_fs(self): + """Make a new filesystem and copy in the files""" + self.setup() + self._do_cleanup = True + self.fs_img = mk_fs(self.config, self.fs_type, self.size_mb << 20, + self.prefix, self.srcdir, quiet=self.quiet) + + def setup(self): + """Set up the srcdir ready to receive files""" + if not self.srcdir: + if self.config: + self.srcdir = os.path.join(self.config.persistent_data_dir, + f'{self.prefix}.{self.fs_type}.tmp') + if os.path.exists(self.srcdir): + shutil.rmtree(self.srcdir) + os.mkdir(self.srcdir) + else: + self.tmpdir = tempfile.TemporaryDirectory('fs_helper') + self.srcdir = self.tmpdir.name + + def cleanup(self): + """Remove created image""" + if self.tmpdir: + self.tmpdir.cleanup() + if self._do_cleanup: + os.remove(self.fs_img) + + def __enter__(self): + self.setup() + return self + + def __exit__(self, extype, value, traceback): + self.cleanup() + + +def mk_fs(config, fs_type, size, prefix, src_dir=None, fs_img=None, quiet=False): """Create a file system volume Args: @@ -18,12 +106,16 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000): size (int): Size of file system in bytes prefix (str): Prefix string of volume's file name src_dir (str): Root directory to use, or None for none - size_gran (int): Size granularity of file system image in bytes + fs_img (str or None): Leaf filename for image, or None to use a + default name. The image is always placed under + persistent_data_dir. + quiet (bool): Suppress non-error output Raises: CalledProcessError: if any error occurs when creating the filesystem """ - fs_img = f'{prefix}.{fs_type}.img' + if not fs_img: + fs_img = f'{prefix}.{fs_type}.img' fs_img = os.path.join(config.persistent_data_dir, fs_img) if fs_type == 'fat12': @@ -48,7 +140,7 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000): elif fs_lnxtype != 'vfat' and fs_lnxtype != 'exfat': raise ValueError(f'src_dir not implemented for fs {fs_lnxtype}') - count = (size + size_gran - 1) // size_gran + count = (size + SIZE_GRAN - 1) // SIZE_GRAN # Some distributions do not add /sbin to the default PATH, where mkfs lives if '/sbin' not in os.environ["PATH"].split(os.pathsep): @@ -56,16 +148,19 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000): try: check_call(f'rm -f {fs_img}', shell=True) - check_call(f'truncate -s $(( {size_gran} * {count} )) {fs_img}', + check_call(f'truncate -s $(( {SIZE_GRAN} * {count} )) {fs_img}', shell=True) - check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True) + check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True, + stdout=DEVNULL if quiet else None) if fs_type == 'ext4': sb_content = check_output(f'tune2fs -l {fs_img}', shell=True).decode() if 'metadata_csum' in sb_content: check_call(f'tune2fs -O ^metadata_csum {fs_img}', shell=True) elif fs_lnxtype == 'vfat' and src_dir: - check_call(f'mcopy -i {fs_img} -vsmpQ {src_dir}/* ::/', shell=True) + flags = f"-smpQ{'' if quiet else 'v'}" + check_call(f'mcopy -i {fs_img} {flags} {src_dir}/* ::/', + shell=True) elif fs_lnxtype == 'exfat' and src_dir: check_call(f'fattools cp {src_dir}/* {fs_img}', shell=True) return fs_img @@ -75,7 +170,7 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000): def setup_image(ubman, devnum, part_type, img_size=20, second_part=False, basename='mmc'): - """Create a disk image with a single partition + """Create a disk image with one or two partitions Args: ubman (ConsoleBase): Console to use diff --git a/test/py/tests/test_efi_ecpt.py b/test/py/tests/test_efi_ecpt.py new file mode 100644 index 00000000000..632a6b90bad --- /dev/null +++ b/test/py/tests/test_efi_ecpt.py @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +""" Unit test for the EFI Conformance Profiles Table (ECPT) +""" + +import pytest + + +@pytest.mark.buildconfigspec('cmd_efidebug') +@pytest.mark.buildconfigspec('efi_ecpt') +def test_efi_ecpt(ubman) -> None: + """ Unit test for the ECPT + This test assumes nothing about the ECPT contents, it just checks that the + ECPT table is there and that the efidebug ecpt command does not fail. + + Args: + ubman -- U-Boot console + """ + response = ubman.run_command('efidebug tables') + assert ('36122546-f7e7-4c8f-bd9b-eb8525b50c0b ' + 'EFI Conformance Profiles Table') in response + + response = ubman.run_command('efidebug ecpt') + assert 'Unknown command' not in response + assert 'Configure UEFI environment' not in response + assert 'Usage:' not in response + assert 'table missing' not in response + + +@pytest.mark.buildconfigspec('cmd_efidebug') +@pytest.mark.buildconfigspec('efi_ecpt') +@pytest.mark.buildconfigspec('efi_ebbr_2_1_conformance') +def test_efi_ecpt_ebbr_2_1(ubman) -> None: + """ Unit test for the ECPT, with EBBR 2.1 profile + This test uses the efidebug ecpt command to dump the ECPT and check that + the EBBR 2.1 conformance profile is there. + + Args: + ubman -- U-Boot console + """ + response = ubman.run_command('efidebug ecpt') + assert ('cce33c35-74ac-4087-bce7-8b29b02eeb27 ' + 'EFI EBBR 2.1 Conformance Profile') in response diff --git a/test/py/tests/test_gpio.py b/test/py/tests/test_gpio.py index 46b674b7653..eba7bab7589 100644 --- a/test/py/tests/test_gpio.py +++ b/test/py/tests/test_gpio.py @@ -4,8 +4,6 @@ # Copyright (c) 2020 Alex Kiernan import pytest -import time -import utils """ test_gpio_input is intended to test the fix 4dbc107f4683. @@ -136,8 +134,12 @@ def test_gpio_set_generic(ubman): if not f: pytest.skip("gpio not configured") - gpio_pin_adr = f['gpio_op_pin']; - gpio_set_value = f['gpio_set_value']; + gpio_pin_adr = f.get('gpio_op_pin') + + if gpio_pin_adr is None: + pytest.skip("gpio_op_pin is not configured") + + gpio_set_value = f['gpio_set_value'] cmd = 'gpio set ' + gpio_pin_adr @@ -160,8 +162,12 @@ def test_gpio_clear_generic(ubman): if not f: pytest.skip("gpio not configured") - gpio_pin_adr = f['gpio_op_pin']; - gpio_clear_value = f['gpio_clear_value']; + gpio_pin_adr = f.get('gpio_op_pin') + + if gpio_pin_adr is None: + pytest.skip("gpio_op_pin is not configured") + + gpio_clear_value = f['gpio_clear_value'] cmd = 'gpio clear ' + gpio_pin_adr @@ -184,9 +190,13 @@ def test_gpio_toggle_generic(ubman): if not f: pytest.skip("gpio not configured") - gpio_pin_adr = f['gpio_op_pin']; - gpio_set_value = f['gpio_set_value']; - gpio_clear_value = f['gpio_clear_value']; + gpio_pin_adr = f.get('gpio_op_pin') + + if gpio_pin_adr is None: + pytest.skip("gpio_op_pin is not configured") + + gpio_set_value = f['gpio_set_value'] + gpio_clear_value = f['gpio_clear_value'] cmd = 'gpio set ' + gpio_pin_adr response = ubman.run_command(cmd) @@ -212,8 +222,8 @@ def test_gpio_input_generic(ubman): if not f: pytest.skip("gpio not configured") - gpio_pin_adr = f['gpio_ip_pin_clear']; - gpio_clear_value = f['gpio_clear_value']; + gpio_pin_adr = f['gpio_ip_pin_clear'] + gpio_clear_value = f['gpio_clear_value'] cmd = 'gpio input ' + gpio_pin_adr @@ -222,8 +232,8 @@ def test_gpio_input_generic(ubman): assert good_response in response - gpio_pin_adr = f['gpio_ip_pin_set']; - gpio_set_value = f['gpio_set_value']; + gpio_pin_adr = f['gpio_ip_pin_set'] + gpio_set_value = f['gpio_set_value'] cmd = 'gpio input ' + gpio_pin_adr diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py index b7166d59943..98641a46c1d 100644 --- a/test/py/tests/test_ut.py +++ b/test/py/tests/test_ut.py @@ -554,6 +554,52 @@ def setup_efi_image(ubman): utils.run_and_log(ubman, f'rm -rf {mnt}') utils.run_and_log(ubman, f'rm -f {fsfile}') +def setup_rauc_image(ubman): + """Create a 40MB disk image with an A/B RAUC system on it""" + mmc_dev = 10 + fname = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img') + mnt = ubman.config.persistent_data_dir + + spec = 'type=c, size=8M, start=1M, bootable\n' \ + 'type=83, size=10M\n' \ + 'type=c, size=8M, bootable\n' \ + 'type=83, size=10M' + + utils.run_and_log(ubman, f'qemu-img create {fname} 40M') + utils.run_and_log(ubman, ['sh', '-c', f'printf "{spec}" | sfdisk {fname}']) + + # Generate boot script + script = '# dummy boot script' + bootdir = os.path.join(mnt, 'boot') + utils.run_and_log(ubman, f'mkdir -p {bootdir}') + cmd_fname = os.path.join(bootdir, 'boot.cmd') + scr_fname = os.path.join(bootdir, 'boot.scr') + with open(cmd_fname, 'w', encoding='ascii') as outf: + print(script, file=outf) + + mkimage = os.path.join(ubman.config.build_dir, 'tools/mkimage') + utils.run_and_log( + ubman, f'{mkimage} -C none -A arm -T script -d {cmd_fname} {scr_fname}') + utils.run_and_log(ubman, f'rm -f {cmd_fname}') + + # Generate empty rootfs + rootdir = os.path.join(mnt, 'root') + utils.run_and_log(ubman, f'mkdir -p {rootdir}') + + # Create boot filesystem image with boot script in it and copy to disk image + fsfile = f'rauc_boot.fat32.img' + fs_helper.mk_fs(ubman.config, 'fat32', 0x800000, fsfile.split('.')[0], bootdir) + utils.run_and_log(ubman, f'dd if={mnt}/{fsfile} of=mmc{mmc_dev}.img bs=1M seek=1 conv=notrunc') + utils.run_and_log(ubman, f'dd if={mnt}/{fsfile} of=mmc{mmc_dev}.img bs=1M seek=19 conv=notrunc') + utils.run_and_log(ubman, f'rm -f {scr_fname}') + + # Create empty root filesystem image and copy to disk image + fsfile = f'rauc_root.ext4.img' + fs_helper.mk_fs(ubman.config, 'ext4', 0xa00000, fsfile.split('.')[0], rootdir) + utils.run_and_log(ubman, f'dd if={mnt}/{fsfile} of=mmc{mmc_dev}.img bs=1M seek=9 conv=notrunc') + utils.run_and_log(ubman, f'dd if={mnt}/{fsfile} of=mmc{mmc_dev}.img bs=1M seek=27 conv=notrunc') + utils.run_and_log(ubman, f'rm -f {fsfile}') + @pytest.mark.buildconfigspec('cmd_bootflow') @pytest.mark.buildconfigspec('sandbox') def test_ut_dm_init_bootstd(ubman): @@ -565,6 +611,7 @@ def test_ut_dm_init_bootstd(ubman): setup_cros_image(ubman) setup_android_image(ubman) setup_efi_image(ubman) + setup_rauc_image(ubman) # Restart so that the new mmc1.img is picked up ubman.restart_uboot() diff --git a/tools/.gitignore b/tools/.gitignore index 6a5c613f772..49943d2cf3a 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -11,6 +11,7 @@ /file2include /fit_check_sign /fit_info +/fwumdata /gdb/gdbcont /gdb/gdbsend /gen_eth_addr @@ -24,6 +25,7 @@ /mkeficapsule /mkenvimage /mkexynosspl +/mkfwumdata /mkimage /mksunxiboot /mxsboot diff --git a/tools/Kconfig b/tools/Kconfig index a1b4d701ac7..ef33295b8ec 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -194,13 +194,6 @@ config LUT_SEQUENCE help Look Up Table Sequence -config TOOLS_MKFWUMDATA - bool "Build mkfwumdata command" - default y if FWU_MULTI_BANK_UPDATE - help - This command allows users to create a raw image of the FWU - metadata for initial installation of the FWU multi bank - update on the board. The installation method depends on - the platform. +source tools/fwumdata_src/Kconfig endmenu diff --git a/tools/Makefile b/tools/Makefile index 5d8e8f349e1..1a5f425ecda 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -272,9 +272,7 @@ mkeficapsule-objs := generated/lib/uuid.o \ mkeficapsule.o hostprogs-always-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule -mkfwumdata-objs := mkfwumdata.o generated/lib/crc32.o -HOSTLDLIBS_mkfwumdata += -luuid -hostprogs-always-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata +include tools/fwumdata_src/fwumdata.mk # We build some files with extra pedantic flags to try to minimize things # that won't build on some weird host compiler -- though there are lots of diff --git a/tools/binman/btool/mkeficapsule.py b/tools/binman/btool/mkeficapsule.py index f7e5a886849..7638c941a8e 100644 --- a/tools/binman/btool/mkeficapsule.py +++ b/tools/binman/btool/mkeficapsule.py @@ -16,7 +16,7 @@ Options: -p, --private-key private key file -c, --certificate signer's certificate file -m, --monotonic-count monotonic count - -d, --dump_sig dump signature (*.p7) + -d, --dump-sig dump signature to .p7 -A, --fw-accept firmware accept capsule, requires GUID, no image blob -R, --fw-revert firmware revert capsule, takes no GUID, no image blob -o, --capoemflag Capsule OEM Flag, an integer between 0x0000 and 0xffff @@ -38,7 +38,8 @@ class Bintoolmkeficapsule(bintool.Bintool): def generate_capsule(self, image_index, image_guid, hardware_instance, payload, output_fname, priv_key, pub_key, - monotonic_count=0, version=0, oemflags=0): + monotonic_count=0, version=0, oemflags=0, + dump_sig=False): """Generate a capsule through commandline-provided parameters Args: @@ -53,6 +54,7 @@ class Bintoolmkeficapsule(bintool.Bintool): monotonic_count (int): Count used when signing an image version (int): Image version (Optional) oemflags (int): Optional 16 bit OEM flags + dump_sig (bool): Dump signature to a file (Optional). Default no. Returns: str: Tool output @@ -73,6 +75,8 @@ class Bintoolmkeficapsule(bintool.Bintool): f'--private-key={priv_key}', f'--certificate={pub_key}' ] + if dump_sig: + args += [f'--dump-sig'] args += [ payload, diff --git a/tools/binman/btool/p11_kit.py b/tools/binman/btool/p11_kit.py new file mode 100644 index 00000000000..9d8d5d848b4 --- /dev/null +++ b/tools/binman/btool/p11_kit.py @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright 2026 Mettler Toledo Technologies GmbH +# +"""Bintool implementation for p11-kit""" + +from binman import bintool + + +class Bintoolp11_kit(bintool.Bintool): + """p11-kit -- support tool for pkcs#11 libraries""" + def __init__(self, name): + super().__init__('p11-kit', + 'Pkcs11 library modules tool', + version_args='list modules') + + def fetch(self, method): + """Install p11-kit via APT """ + if method != bintool.FETCH_BIN: + return None + + return self.apt_install('p11-kit') diff --git a/tools/binman/btool/pkcs11_tool.py b/tools/binman/btool/pkcs11_tool.py new file mode 100644 index 00000000000..673c0ea0ac3 --- /dev/null +++ b/tools/binman/btool/pkcs11_tool.py @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright 2026 Mettler Toledo Technologies GmbH +# +"""Bintool implementation for pkcs11-tool""" + +from binman import bintool + + +class Bintoolpkcs11_tool(bintool.Bintool): + """pkcs11-tool -- support tool for managing pkcs#11 tokens""" + def __init__(self, name): + super().__init__('pkcs11-tool', + 'PKCS #11 tokens managing tool', + version_args='--show-info') + + def fetch(self, method): + """Install opensc via APT """ + if method != bintool.FETCH_BIN: + return None + + return self.apt_install('opensc') diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index a81fcbd3891..91f855f6d7a 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -552,6 +552,10 @@ Properties / Entry arguments: - public-key-cert: Path to PEM formatted .crt public key certificate file. Mandatory property for generating signed capsules. - oem-flags - OEM flags to be passed through capsule header. + - dump-signature: Optional boolean (default: false). Instruct + mkeficapsule to write signature data to a separate file. The + filename will be .p7. It might be used to verify + capsule authentication with external tools. Since this is a subclass of Entry_section, all properties of the parent class also apply here. Except for the properties stated as mandatory, the diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py index 40d74d401a2..7f00358e008 100644 --- a/tools/binman/entry_test.py +++ b/tools/binman/entry_test.py @@ -26,7 +26,7 @@ class TestEntry(unittest.TestCase): def GetNode(self): binman_dir = os.path.dirname(os.path.realpath(sys.argv[0])) fname = fdt_util.EnsureCompiled( - os.path.join(binman_dir,('test/005_simple.dts'))) + os.path.join(binman_dir,('test/pack/simple.dts'))) dtb = fdt.FdtScan(fname) return dtb.GetNode('/binman/u-boot') diff --git a/tools/binman/etype/efi_capsule.py b/tools/binman/etype/efi_capsule.py index 9f06cc88e6e..022d57ee551 100644 --- a/tools/binman/etype/efi_capsule.py +++ b/tools/binman/etype/efi_capsule.py @@ -53,6 +53,10 @@ class Entry_efi_capsule(Entry_section): - public-key-cert: Path to PEM formatted .crt public key certificate file. Mandatory property for generating signed capsules. - oem-flags - OEM flags to be passed through capsule header. + - dump-signature: Optional boolean (default: false). Instruct + mkeficapsule to write signature data to a separate file. The + filename will be .p7. It might be used to verify + capsule authentication with external tools. Since this is a subclass of Entry_section, all properties of the parent class also apply here. Except for the properties stated as mandatory, the @@ -101,6 +105,7 @@ class Entry_efi_capsule(Entry_section): self.private_key = '' self.public_key_cert = '' self.auth = 0 + self.dump_signature = False def ReadNode(self): super().ReadNode() @@ -111,6 +116,7 @@ class Entry_efi_capsule(Entry_section): self.hardware_instance = fdt_util.GetInt(self._node, 'hardware-instance') self.monotonic_count = fdt_util.GetInt(self._node, 'monotonic-count') self.oem_flags = fdt_util.GetInt(self._node, 'oem-flags') + self.dump_signature = fdt_util.GetBool(self._node, 'dump-signature') self.private_key = fdt_util.GetString(self._node, 'private-key') self.public_key_cert = fdt_util.GetString(self._node, 'public-key-cert') @@ -125,10 +131,14 @@ class Entry_efi_capsule(Entry_section): private_key = '' public_key_cert = '' if self.auth: - if not os.path.isabs(self.private_key): + if not os.path.isabs(self.private_key) and not 'pkcs11:' in self.private_key: private_key = tools.get_input_filename(self.private_key) - if not os.path.isabs(self.public_key_cert): + if not os.path.isabs(self.public_key_cert) and not 'pkcs11:' in self.public_key_cert: public_key_cert = tools.get_input_filename(self.public_key_cert) + if 'pkcs11:' in self.private_key: + private_key = self.private_key + if 'pkcs11:' in self.public_key_cert: + public_key_cert = self.public_key_cert data, payload, uniq = self.collect_contents_to_file( self._entries.values(), 'capsule_in') outfile = self._filename if self._filename else 'capsule.%s' % uniq @@ -146,7 +156,8 @@ class Entry_efi_capsule(Entry_section): public_key_cert, self.monotonic_count, self.fw_version, - self.oem_flags) + self.oem_flags, + self.dump_signature) if ret is not None: return tools.read_file(capsule_fname) else: diff --git a/tools/binman/fdt_test.py b/tools/binman/fdt_test.py index 564c1770820..ef81a3262d2 100644 --- a/tools/binman/fdt_test.py +++ b/tools/binman/fdt_test.py @@ -36,12 +36,12 @@ class TestFdt(unittest.TestCase): node.DeleteProp('data') def testFdtNormal(self): - fname = self.GetCompiled('034_x86_ucode.dts') + fname = self.GetCompiled('x86/ucode.dts') dt = FdtScan(fname) self._DeleteProp(dt) def testFdtNormalProp(self): - fname = self.GetCompiled('045_prop_test.dts') + fname = self.GetCompiled('entry/prop_test.dts') dt = FdtScan(fname) node = dt.GetNode('/binman/intel-me') self.assertEqual('intel-me', node.name) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index a53e37f31b3..ca5149ee654 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -7,6 +7,7 @@ # python -m unittest func_test.TestFunctional.testHelp import collections +import configparser import glob import gzip import hashlib @@ -696,7 +697,7 @@ class TestFunctional(unittest.TestCase): @classmethod def _SetupDescriptor(cls): - with open(cls.TestFile('descriptor.bin'), 'rb') as fd: + with open(cls.TestFile('x86/descriptor.bin'), 'rb') as fd: TestFunctional._MakeInputFile('descriptor.bin', fd.read()) @classmethod @@ -816,7 +817,7 @@ class TestFunctional(unittest.TestCase): def testBoard(self): """Test that we can run it with a specific board""" - self._SetupDtb('005_simple.dts', 'sandbox/u-boot.dtb') + self._SetupDtb('pack/simple.dts', 'sandbox/u-boot.dtb') TestFunctional._MakeInputFile('sandbox/u-boot.bin', U_BOOT_DATA) result = self._DoBinman('build', '-n', '-b', 'sandbox') self.assertEqual(0, result) @@ -843,19 +844,19 @@ class TestFunctional(unittest.TestCase): will come from the device-tree compiler (dtc). """ with self.assertRaises(Exception) as e: - self._RunBinman('build', '-d', self.TestFile('001_invalid.dts')) + self._RunBinman('build', '-d', self.TestFile('pack/invalid.dts')) self.assertIn("FATAL ERROR: Unable to parse input tree", str(e.exception)) def testMissingNode(self): """Test that a device tree without a 'binman' node generates an error""" with self.assertRaises(Exception) as e: - self._DoBinman('build', '-d', self.TestFile('002_missing_node.dts')) + self._DoBinman('build', '-d', self.TestFile('pack/missing_node.dts')) self.assertIn("does not have a 'binman' node", str(e.exception)) def testEmpty(self): """Test that an empty binman node works OK (i.e. does nothing)""" - result = self._RunBinman('build', '-d', self.TestFile('003_empty.dts')) + result = self._RunBinman('build', '-d', self.TestFile('pack/empty.dts')) self.assertEqual(0, len(result.stderr)) self.assertEqual(0, result.return_code) @@ -863,25 +864,25 @@ class TestFunctional(unittest.TestCase): """Test that an invalid entry is flagged""" with self.assertRaises(Exception) as e: result = self._RunBinman('build', '-d', - self.TestFile('004_invalid_entry.dts')) + self.TestFile('pack/invalid_entry.dts')) self.assertIn("Unknown entry type 'not-a-valid-type' in node " "'/binman/not-a-valid-type'", str(e.exception)) def testSimple(self): """Test a simple binman with a single file""" - data = self._DoReadFile('005_simple.dts') + data = self._DoReadFile('pack/simple.dts') self.assertEqual(U_BOOT_DATA, data) def testSimpleDebug(self): """Test a simple binman run with debugging enabled""" - self._DoTestFile('005_simple.dts', debug=True) + self._DoTestFile('pack/simple.dts', debug=True) def testDual(self): """Test that we can handle creating two images This also tests image padding. """ - retcode = self._DoTestFile('006_dual_image.dts') + retcode = self._DoTestFile('pack/dual_image.dts') self.assertEqual(0, retcode) image = control.images['image1'] @@ -905,13 +906,13 @@ class TestFunctional(unittest.TestCase): def testBadAlign(self): """Test that an invalid alignment value is detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('007_bad_align.dts') + self._DoTestFile('pack/bad_align.dts') self.assertIn("Node '/binman/u-boot': Alignment 23 must be a power " "of two", str(e.exception)) def testPackSimple(self): """Test that packing works as expected""" - retcode = self._DoTestFile('008_pack.dts') + retcode = self._DoTestFile('pack/pack.dts') self.assertEqual(0, retcode) self.assertIn('image', control.images) image = control.images['image'] @@ -953,7 +954,7 @@ class TestFunctional(unittest.TestCase): def testPackExtra(self): """Test that extra packing feature works as expected""" - data, _, _, out_dtb_fname = self._DoReadFileDtb('009_pack_extra.dts', + data, _, _, out_dtb_fname = self._DoReadFileDtb('pack/pack_extra.dts', update_dtb=True) self.assertIn('image', control.images) @@ -1059,35 +1060,35 @@ class TestFunctional(unittest.TestCase): def testPackAlignPowerOf2(self): """Test that invalid entry alignment is detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('010_pack_align_power2.dts') + self._DoTestFile('pack/pack_align_power2.dts') self.assertIn("Node '/binman/u-boot': Alignment 5 must be a power " "of two", str(e.exception)) def testPackAlignSizePowerOf2(self): """Test that invalid entry size alignment is detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('011_pack_align_size_power2.dts') + self._DoTestFile('pack/pack_align_size_power2.dts') self.assertIn("Node '/binman/u-boot': Alignment size 55 must be a " "power of two", str(e.exception)) def testPackInvalidAlign(self): """Test detection of an offset that does not match its alignment""" with self.assertRaises(ValueError) as e: - self._DoTestFile('012_pack_inv_align.dts') + self._DoTestFile('pack/pack_inv_align.dts') self.assertIn("Node '/binman/u-boot': Offset 0x5 (5) does not match " "align 0x4 (4)", str(e.exception)) def testPackInvalidSizeAlign(self): """Test that invalid entry size alignment is detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('013_pack_inv_size_align.dts') + self._DoTestFile('pack/pack_inv_size_align.dts') self.assertIn("Node '/binman/u-boot': Size 0x5 (5) does not match " "align-size 0x4 (4)", str(e.exception)) def testPackOverlap(self): """Test that overlapping regions are detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('014_pack_overlap.dts') + self._DoTestFile('pack/pack_overlap.dts') self.assertIn("Node '/binman/u-boot-align': Offset 0x3 (3) overlaps " "with previous entry '/binman/u-boot' ending at 0x4 (4)", str(e.exception)) @@ -1095,20 +1096,20 @@ class TestFunctional(unittest.TestCase): def testPackEntryOverflow(self): """Test that entries that overflow their size are detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('015_pack_overflow.dts') + self._DoTestFile('pack/pack_overflow.dts') self.assertIn("Node '/binman/u-boot': Entry contents size is 0x4 (4) " "but entry size is 0x3 (3)", str(e.exception)) def testPackImageOverflow(self): """Test that entries which overflow the image size are detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('016_pack_image_overflow.dts') + self._DoTestFile('pack/pack_image_overflow.dts') self.assertIn("Section '/binman': contents size 0x4 (4) exceeds section " "size 0x3 (3)", str(e.exception)) def testPackImageSize(self): """Test that the image size can be set""" - retcode = self._DoTestFile('017_pack_image_size.dts') + retcode = self._DoTestFile('pack/pack_image_size.dts') self.assertEqual(0, retcode) self.assertIn('image', control.images) image = control.images['image'] @@ -1116,7 +1117,7 @@ class TestFunctional(unittest.TestCase): def testPackImageSizeAlign(self): """Test that image size alignemnt works as expected""" - retcode = self._DoTestFile('018_pack_image_align.dts') + retcode = self._DoTestFile('pack/pack_image_align.dts') self.assertEqual(0, retcode) self.assertIn('image', control.images) image = control.images['image'] @@ -1125,27 +1126,27 @@ class TestFunctional(unittest.TestCase): def testPackInvalidImageAlign(self): """Test that invalid image alignment is detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('019_pack_inv_image_align.dts') + self._DoTestFile('pack/pack_inv_image_align.dts') self.assertIn("Section '/binman': Size 0x7 (7) does not match " "align-size 0x8 (8)", str(e.exception)) def testPackAlignPowerOf2Inv(self): """Test that invalid image alignment is detected""" with self.assertRaises(ValueError) as e: - self._DoTestFile('020_pack_inv_image_align_power2.dts') + self._DoTestFile('pack/pack_inv_image_align_power2.dts') self.assertIn("Image '/binman': Alignment size 131 must be a power of " "two", str(e.exception)) def testImagePadByte(self): """Test that the image pad byte can be specified""" self._SetupSplElf() - data = self._DoReadFile('021_image_pad.dts') + data = self._DoReadFile('pack/image_pad.dts') self.assertEqual(U_BOOT_SPL_DATA + tools.get_bytes(0xff, 1) + U_BOOT_DATA, data) def testImageName(self): """Test that image files can be named""" - retcode = self._DoTestFile('022_image_name.dts') + retcode = self._DoTestFile('pack/image_name.dts') self.assertEqual(0, retcode) image = control.images['image1'] fname = tools.get_output_filename('test-name') @@ -1157,13 +1158,13 @@ class TestFunctional(unittest.TestCase): def testBlobFilename(self): """Test that generic blobs can be provided by filename""" - data = self._DoReadFile('023_blob.dts') + data = self._DoReadFile('blob/blob.dts') self.assertEqual(BLOB_DATA, data) def testPackSorted(self): """Test that entries can be sorted""" self._SetupSplElf() - data = self._DoReadFile('024_sorted.dts') + data = self._DoReadFile('pack/sorted.dts') self.assertEqual(tools.get_bytes(0, 1) + U_BOOT_SPL_DATA + tools.get_bytes(0, 2) + U_BOOT_DATA, data) @@ -1171,21 +1172,21 @@ class TestFunctional(unittest.TestCase): """Test that an entry at offset 0 is not given a new offset""" self._SetupSplElf() with self.assertRaises(ValueError) as e: - self._DoTestFile('025_pack_zero_size.dts') + self._DoTestFile('pack/pack_zero_size.dts') self.assertIn("Node '/binman/u-boot-spl': Offset 0x0 (0) overlaps " "with previous entry '/binman/u-boot' ending at 0x4 (4)", str(e.exception)) def testPackUbootDtb(self): """Test that a device tree can be added to U-Boot""" - data = self._DoReadFile('026_pack_u_boot_dtb.dts') + data = self._DoReadFile('xpl/pack_dtb.dts') self.assertEqual(U_BOOT_NODTB_DATA + U_BOOT_DTB_DATA, data) def testPackX86RomNoSize(self): """Test that the end-at-4gb property requires a size property""" self._SetupSplElf() with self.assertRaises(ValueError) as e: - self._DoTestFile('027_pack_4gb_no_size.dts') + self._DoTestFile('pack/pack_4gb_no_size.dts') self.assertIn("Image '/binman': Section size must be provided when " "using end-at-4gb", str(e.exception)) @@ -1194,7 +1195,7 @@ class TestFunctional(unittest.TestCase): together""" self._SetupSplElf() with self.assertRaises(ValueError) as e: - self._DoTestFile('098_4gb_and_skip_at_start_together.dts') + self._DoTestFile('pack/4gb_and_skip_at_start_together.dts') self.assertIn("Image '/binman': Provide either 'end-at-4gb' or " "'skip-at-start'", str(e.exception)) @@ -1202,7 +1203,7 @@ class TestFunctional(unittest.TestCase): """Test that the end-at-4gb property checks for offset boundaries""" self._SetupSplElf() with self.assertRaises(ValueError) as e: - self._DoTestFile('028_pack_4gb_outside.dts') + self._DoTestFile('pack/pack_4gb_outside.dts') self.assertIn("Node '/binman/u-boot': Offset 0x0 (0) size 0x4 (4) " "is outside the section '/binman' starting at " '0xffffffe0 (4294967264) of size 0x20 (32)', @@ -1211,7 +1212,7 @@ class TestFunctional(unittest.TestCase): def testPackX86Rom(self): """Test that a basic x86 ROM can be created""" self._SetupSplElf() - data = self._DoReadFile('029_x86_rom.dts') + data = self._DoReadFile('x86/rom.dts') self.assertEqual(U_BOOT_DATA + tools.get_bytes(0, 3) + U_BOOT_SPL_DATA + tools.get_bytes(0, 2), data) @@ -1220,7 +1221,7 @@ class TestFunctional(unittest.TestCase): try: TestFunctional._MakeInputFile('descriptor-empty.bin', b'') with self.assertRaises(ValueError) as e: - self._DoTestFile('163_x86_rom_me_empty.dts') + self._DoTestFile('x86/rom_me_empty.dts') self.assertIn("Node '/binman/intel-descriptor': Cannot find Intel Flash Descriptor (FD) signature", str(e.exception)) finally: @@ -1229,33 +1230,33 @@ class TestFunctional(unittest.TestCase): def testPackX86RomBadDesc(self): """Test that the Intel requires a descriptor entry""" with self.assertRaises(ValueError) as e: - self._DoTestFile('030_x86_rom_me_no_desc.dts') + self._DoTestFile('x86/rom_me_no_desc.dts') self.assertIn("Node '/binman/intel-me': No offset set with " "offset-unset: should another entry provide this correct " "offset?", str(e.exception)) def testPackX86RomMe(self): """Test that an x86 ROM with an ME region can be created""" - data = self._DoReadFile('031_x86_rom_me.dts') - expected_desc = tools.read_file(self.TestFile('descriptor.bin')) + data = self._DoReadFile('x86/rom_me.dts') + expected_desc = tools.read_file(self.TestFile('x86/descriptor.bin')) if data[:0x1000] != expected_desc: self.fail('Expected descriptor binary at start of image') self.assertEqual(ME_DATA, data[0x1000:0x1000 + len(ME_DATA)]) def testPackVga(self): """Test that an image with a VGA binary can be created""" - data = self._DoReadFile('032_intel_vga.dts') + data = self._DoReadFile('x86/intel_vga.dts') self.assertEqual(VGA_DATA, data[:len(VGA_DATA)]) def testPackStart16(self): """Test that an image with an x86 start16 region can be created""" - data = self._DoReadFile('033_x86_start16.dts') + data = self._DoReadFile('x86/start16.dts') self.assertEqual(X86_START16_DATA, data[:len(X86_START16_DATA)]) def testPackPowerpcMpc85xxBootpgResetvec(self): """Test that an image with powerpc-mpc85xx-bootpg-resetvec can be created""" - data = self._DoReadFile('150_powerpc_mpc85xx_bootpg_resetvec.dts') + data = self._DoReadFile('vendor/powerpc_mpc85xx_bootpg_resetvec.dts') self.assertEqual(PPC_MPC85XX_BR_DATA, data[:len(PPC_MPC85XX_BR_DATA)]) def _RunMicrocodeTest(self, dts_fname, nodtb_data, ucode_second=False): @@ -1318,7 +1319,7 @@ class TestFunctional(unittest.TestCase): u-boot.dtb with the microcode removed the microcode """ - first, pos_and_size = self._RunMicrocodeTest('034_x86_ucode.dts', + first, pos_and_size = self._RunMicrocodeTest('x86/ucode.dts', U_BOOT_NODTB_DATA) self.assertEqual(b'nodtb with microcode' + pos_and_size + b' somewhere in here', first) @@ -1335,7 +1336,7 @@ class TestFunctional(unittest.TestCase): # We need the libfdt library to run this test since only that allows # finding the offset of a property. This is required by # Entry_u_boot_dtb_with_ucode.ObtainContents(). - data = self._DoReadFile('035_x86_single_ucode.dts', True) + data = self._DoReadFile('x86/single_ucode.dts', True) second = data[len(U_BOOT_NODTB_DATA):] @@ -1362,27 +1363,27 @@ class TestFunctional(unittest.TestCase): def testUBootImg(self): """Test that u-boot.img can be put in a file""" - data = self._DoReadFile('036_u_boot_img.dts') + data = self._DoReadFile('xpl/u-boot-img.dts') self.assertEqual(U_BOOT_IMG_DATA, data) def testNoMicrocode(self): """Test that a missing microcode region is detected""" with self.assertRaises(ValueError) as e: - self._DoReadFile('037_x86_no_ucode.dts', True) + self._DoReadFile('x86/no_ucode.dts', True) self.assertIn("Node '/binman/u-boot-dtb-with-ucode': No /microcode " "node found in ", str(e.exception)) def testMicrocodeWithoutNode(self): """Test that a missing u-boot-dtb-with-ucode node is detected""" with self.assertRaises(ValueError) as e: - self._DoReadFile('038_x86_ucode_missing_node.dts', True) + self._DoReadFile('x86/ucode_missing_node.dts', True) self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Cannot find " "microcode region u-boot-dtb-with-ucode", str(e.exception)) def testMicrocodeWithoutNode2(self): """Test that a missing u-boot-ucode node is detected""" with self.assertRaises(ValueError) as e: - self._DoReadFile('039_x86_ucode_missing_node2.dts', True) + self._DoReadFile('x86/ucode_missing_node2.dts', True) self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Cannot find " "microcode region u-boot-ucode", str(e.exception)) @@ -1406,7 +1407,7 @@ class TestFunctional(unittest.TestCase): def testMicrocodeNotInImage(self): """Test that microcode must be placed within the image""" with self.assertRaises(ValueError) as e: - self._DoReadFile('040_x86_ucode_not_in_image.dts', True) + self._DoReadFile('x86/ucode_not_in_image.dts', True) self.assertIn("Node '/binman/u-boot-with-ucode-ptr': Microcode " "pointer _dt_ucode_base_size at fffffe14 is outside the " "section ranging from 00000000 to 0000002e", str(e.exception)) @@ -1415,7 +1416,7 @@ class TestFunctional(unittest.TestCase): """Test that we can cope with an image without microcode (e.g. qemu)""" TestFunctional._MakeInputFile('u-boot', tools.read_file(self.ElfTestFile('u_boot_no_ucode_ptr'))) - data, dtb, _, _ = self._DoReadFileDtb('044_x86_optional_ucode.dts', True) + data, dtb, _, _ = self._DoReadFileDtb('x86/optional_ucode.dts', True) # Now check the device tree has no microcode self.assertEqual(U_BOOT_NODTB_DATA, data[:len(U_BOOT_NODTB_DATA)]) @@ -1431,30 +1432,30 @@ class TestFunctional(unittest.TestCase): def testUnknownPosSize(self): """Test that microcode must be placed within the image""" with self.assertRaises(ValueError) as e: - self._DoReadFile('041_unknown_pos_size.dts', True) + self._DoReadFile('entry/unknown_pos_size.dts', True) self.assertIn("Section '/binman': Unable to set offset/size for unknown " "entry 'invalid-entry'", str(e.exception)) def testPackFsp(self): """Test that an image with a FSP binary can be created""" - data = self._DoReadFile('042_intel_fsp.dts') + data = self._DoReadFile('x86/intel_fsp.dts') self.assertEqual(FSP_DATA, data[:len(FSP_DATA)]) def testPackCmc(self): """Test that an image with a CMC binary can be created""" - data = self._DoReadFile('043_intel_cmc.dts') + data = self._DoReadFile('x86/intel_cmc.dts') self.assertEqual(CMC_DATA, data[:len(CMC_DATA)]) def testPackVbt(self): """Test that an image with a VBT binary can be created""" - data = self._DoReadFile('046_intel_vbt.dts') + data = self._DoReadFile('x86/intel_vbt.dts') self.assertEqual(VBT_DATA, data[:len(VBT_DATA)]) def testSplBssPad(self): """Test that we can pad SPL's BSS with zeros""" # ELF file with a '__bss_size' symbol self._SetupSplElf() - data = self._DoReadFile('047_spl_bss_pad.dts') + data = self._DoReadFile('xpl/spl_bss_pad.dts') self.assertEqual(U_BOOT_SPL_DATA + tools.get_bytes(0, 10) + U_BOOT_DATA, data) @@ -1462,13 +1463,13 @@ class TestFunctional(unittest.TestCase): """Test that a missing symbol is detected""" self._SetupSplElf('u_boot_ucode_ptr') with self.assertRaises(ValueError) as e: - self._DoReadFile('047_spl_bss_pad.dts') + self._DoReadFile('xpl/spl_bss_pad.dts') self.assertIn('Expected __bss_size symbol in spl/u-boot-spl', str(e.exception)) def testPackStart16Spl(self): """Test that an image with an x86 start16 SPL region can be created""" - data = self._DoReadFile('048_x86_start16_spl.dts') + data = self._DoReadFile('x86/start16_spl.dts') self.assertEqual(X86_START16_SPL_DATA, data[:len(X86_START16_SPL_DATA)]) def _PackUbootSplMicrocode(self, dts, ucode_second=False): @@ -1494,7 +1495,7 @@ class TestFunctional(unittest.TestCase): def testPackUbootSplMicrocode(self): """Test that x86 microcode can be handled correctly in SPL""" self._SetupSplElf() - self._PackUbootSplMicrocode('049_x86_ucode_spl.dts') + self._PackUbootSplMicrocode('x86/ucode_spl.dts') def testPackUbootSplMicrocodeReorder(self): """Test that order doesn't matter for microcode entries @@ -1503,24 +1504,24 @@ class TestFunctional(unittest.TestCase): u-boot-ucode entry we have not yet seen the u-boot-dtb-with-ucode entry, so we reply on binman to try later. """ - self._PackUbootSplMicrocode('058_x86_ucode_spl_needs_retry.dts', + self._PackUbootSplMicrocode('x86/ucode_spl_needs_retry.dts', ucode_second=True) def testPackMrc(self): """Test that an image with an MRC binary can be created""" - data = self._DoReadFile('050_intel_mrc.dts') + data = self._DoReadFile('x86/intel_mrc.dts') self.assertEqual(MRC_DATA, data[:len(MRC_DATA)]) def testSplDtb(self): """Test that an image with spl/u-boot-spl.dtb can be created""" self._SetupSplElf() - data = self._DoReadFile('051_u_boot_spl_dtb.dts') + data = self._DoReadFile('xpl/u-boot-spl-dtb.dts') self.assertEqual(U_BOOT_SPL_DTB_DATA, data[:len(U_BOOT_SPL_DTB_DATA)]) def testSplNoDtb(self): """Test that an image with spl/u-boot-spl-nodtb.bin can be created""" self._SetupSplElf() - data = self._DoReadFile('052_u_boot_spl_nodtb.dts') + data = self._DoReadFile('xpl/u-boot-spl-nodtb.dts') self.assertEqual(U_BOOT_SPL_NODTB_DATA, data[:len(U_BOOT_SPL_NODTB_DATA)]) def checkSymbols(self, dts, base_data, u_boot_offset, entry_args=None, @@ -1611,22 +1612,22 @@ class TestFunctional(unittest.TestCase): def testSymbols(self): """Test binman can assign symbols embedded in U-Boot""" - self.checkSymbols('053_symbols.dts', U_BOOT_SPL_DATA, 0x1c) + self.checkSymbols('symbols/symbols.dts', U_BOOT_SPL_DATA, 0x1c) def testSymbolsNoDtb(self): """Test binman can assign symbols embedded in U-Boot SPL""" - self.checkSymbols('196_symbols_nodtb.dts', + self.checkSymbols('symbols/nodtb.dts', U_BOOT_SPL_NODTB_DATA + U_BOOT_SPL_DTB_DATA, 0x38) def testPackUnitAddress(self): """Test that we support multiple binaries with the same name""" - data = self._DoReadFile('054_unit_address.dts') + data = self._DoReadFile('pack/unit_address.dts') self.assertEqual(U_BOOT_DATA + U_BOOT_DATA, data) def testSections(self): """Basic test of sections""" - data = self._DoReadFile('055_sections.dts') + data = self._DoReadFile('entry/sections.dts') expected = (U_BOOT_DATA + tools.get_bytes(ord('!'), 12) + U_BOOT_DATA + tools.get_bytes(ord('a'), 12) + U_BOOT_DATA + tools.get_bytes(ord('&'), 4)) @@ -1634,7 +1635,7 @@ class TestFunctional(unittest.TestCase): def testMap(self): """Tests outputting a map of the images""" - _, _, map_data, _ = self._DoReadFileDtb('055_sections.dts', map=True) + _, _, map_data, _ = self._DoReadFileDtb('entry/sections.dts', map=True) self.assertEqual('''ImagePos Offset Size Name 00000000 00000000 00000028 image 00000000 00000000 00000010 section@0 @@ -1647,7 +1648,7 @@ class TestFunctional(unittest.TestCase): def testNamePrefix(self): """Tests that name prefixes are used""" - _, _, map_data, _ = self._DoReadFileDtb('056_name_prefix.dts', map=True) + _, _, map_data, _ = self._DoReadFileDtb('entry/name_prefix.dts', map=True) self.assertEqual('''ImagePos Offset Size Name 00000000 00000000 00000028 image 00000000 00000000 00000010 section@0 @@ -1659,7 +1660,7 @@ class TestFunctional(unittest.TestCase): def testUnknownContents(self): """Test that obtaining the contents works as expected""" with self.assertRaises(ValueError) as e: - self._DoReadFile('057_unknown_contents.dts', True) + self._DoReadFile('entry/unknown_contents.dts', True) self.assertIn("Image '/binman': Internal error: Could not complete " "processing of contents: remaining [" "I', len(U_BOOT_TPL_DATA)) expect += struct.pack('>I', len(U_BOOT_SPL_DATA)) @@ -6291,7 +6292,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'spl-bss-pad': 'y', 'spl-dtb': 'y', } - data = self._DoReadFileDtb('252_mkimage_mult_data.dts', + data = self._DoReadFileDtb('mkimage/mult_data.dts', use_expanded=True, entry_args=entry_args)[0] pad_len = 10 tpl_expect = U_BOOT_TPL_DATA @@ -6320,14 +6321,14 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test passing multiple data files to mkimage with one data file having no content""" self._SetupSplElf() with self.assertRaises(ValueError) as exc: - self._DoReadFile('253_mkimage_mult_no_content.dts') + self._DoReadFile('mkimage/mult_no_content.dts') self.assertIn('Could not complete processing of contents', str(exc.exception)) def testMkimageFilename(self): """Test using mkimage to build a binary with a filename""" self._SetupSplElf() - retcode = self._DoTestFile('254_mkimage_filename.dts') + retcode = self._DoTestFile('mkimage/filename.dts') self.assertEqual(0, retcode) fname = tools.get_output_filename('mkimage-test.bin') self.assertTrue(os.path.exists(fname)) @@ -6336,13 +6337,13 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test that an image with VPL and its device tree can be created""" # ELF file with a '__bss_size' symbol self._SetupVplElf() - data = self._DoReadFile('255_u_boot_vpl.dts') + data = self._DoReadFile('xpl/vpl.dts') self.assertEqual(U_BOOT_VPL_DATA + U_BOOT_VPL_DTB_DATA, data) def testVplNoDtb(self): """Test that an image with vpl/u-boot-vpl-nodtb.bin can be created""" self._SetupVplElf() - data = self._DoReadFile('256_u_boot_vpl_nodtb.dts') + data = self._DoReadFile('xpl/u-boot-vpl-nodtb.dts') self.assertEqual(U_BOOT_VPL_NODTB_DATA, data[:len(U_BOOT_VPL_NODTB_DATA)]) @@ -6354,7 +6355,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'vpl-bss-pad': 'y', 'vpl-dtb': 'y', } - self._DoReadFileDtb('257_fdt_incl_vpl.dts', use_expanded=True, + self._DoReadFileDtb('fdt/incl_vpl.dts', use_expanded=True, entry_args=entry_args) image = control.images['image'] entries = image.GetEntries() @@ -6374,13 +6375,13 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test that a missing symbol is detected""" self._SetupVplElf('u_boot_ucode_ptr') with self.assertRaises(ValueError) as e: - self._DoReadFile('258_vpl_bss_pad.dts') + self._DoReadFile('xpl/vpl_bss_pad.dts') self.assertIn('Expected __bss_size symbol in vpl/u-boot-vpl', str(e.exception)) def testSymlink(self): """Test that image files can be symlinked""" - retcode = self._DoTestFile('259_symlink.dts', debug=True, map=True) + retcode = self._DoTestFile('entry/symlink.dts', debug=True, map=True) self.assertEqual(0, retcode) image = control.images['test_image'] fname = tools.get_output_filename('test_image.bin') @@ -6391,9 +6392,9 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testSymlinkOverwrite(self): """Test that symlinked images can be overwritten""" testdir = TestFunctional._MakeInputDir('symlinktest') - self._DoTestFile('259_symlink.dts', debug=True, map=True, output_dir=testdir) + self._DoTestFile('entry/symlink.dts', debug=True, map=True, output_dir=testdir) # build the same image again in the same directory so that existing symlink is present - self._DoTestFile('259_symlink.dts', debug=True, map=True, output_dir=testdir) + self._DoTestFile('entry/symlink.dts', debug=True, map=True, output_dir=testdir) fname = tools.get_output_filename('test_image.bin') sname = tools.get_output_filename('symlink_to_test.bin') self.assertTrue(os.path.islink(sname)) @@ -6406,7 +6407,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap self._SetupTplElf('u_boot_binman_syms') self._SetupVplElf('u_boot_binman_syms') self._SetupSplElf('u_boot_binman_syms') - data = self._DoReadFileDtb('260_symbols_elf.dts')[0] + data = self._DoReadFileDtb('symbols/elf.dts')[0] image_fname = tools.get_output_filename('image.bin') image = control.images['image'] @@ -6449,7 +6450,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap try: elf.ELF_TOOLS = False with self.assertRaises(ValueError) as exc: - self._DoReadFileDtb('260_symbols_elf.dts') + self._DoReadFileDtb('symbols/elf.dts') finally: elf.ELF_TOOLS = True self.assertIn( @@ -6459,7 +6460,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testSectionFilename(self): """Check writing of section contents to a file""" - data = self._DoReadFile('261_section_fname.dts') + data = self._DoReadFile('entry/section_fname.dts') expected = (b'&&' + U_BOOT_DATA + b'&&&' + tools.get_bytes(ord('!'), 7) + U_BOOT_DATA + tools.get_bytes(ord('&'), 12)) @@ -6472,7 +6473,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testAbsent(self): """Check handling of absent entries""" - data = self._DoReadFile('262_absent.dts') + data = self._DoReadFile('entry/absent.dts') self.assertEqual(U_BOOT_DATA + b'aa' + U_BOOT_IMG_DATA, data) def testPackTeeOsElf(self): @@ -6481,7 +6482,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'tee-os-path': 'tee.elf', } tee_path = self.tee_elf_path - data = self._DoReadFileDtb('263_tee_os_opt.dts', + data = self._DoReadFileDtb('entry/tee_os_opt.dts', entry_args=entry_args)[0] self.assertEqual(U_BOOT_DATA + tools.read_file(tee_path) + U_BOOT_IMG_DATA, data) @@ -6510,7 +6511,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testFitTeeOsOptionalFit(self): """Test an image with a FIT with an optional OP-TEE binary""" - data = self.checkFitTee('264_tee_os_opt_fit.dts', 'tee.bin') + data = self.checkFitTee('fit/tee_os_opt.dts', 'tee.bin') # There should be only one node, holding the data set up in SetUpClass() # for tee.bin @@ -6524,7 +6525,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap self.assertEqual(U_BOOT_DATA, node.props['data'].bytes) with terminal.capture() as (stdout, stderr): - self.checkFitTee('264_tee_os_opt_fit.dts', '') + self.checkFitTee('fit/tee_os_opt.dts', '') err = stderr.getvalue() self.assertRegex( err, @@ -6536,7 +6537,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testFitTeeOsOptionalFitBad(self): """Test an image with a FIT with an optional OP-TEE binary""" with self.assertRaises(ValueError) as exc: - self.checkFitTee('265_tee_os_opt_fit_bad.dts', 'tee.bin') + self.checkFitTee('fit/tee_os_opt_bad.dts', 'tee.bin') self.assertIn( "Node '/binman/fit': subnode 'images/@tee-SEQ': Failed to read ELF file: Magic number does not match", str(exc.exception)) @@ -6545,14 +6546,14 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test an OP-TEE binary with wrong formats""" self.make_tee_bin('tee.bad1', 123) with self.assertRaises(ValueError) as exc: - self.checkFitTee('264_tee_os_opt_fit.dts', 'tee.bad1') + self.checkFitTee('fit/tee_os_opt.dts', 'tee.bad1') self.assertIn( "Node '/binman/fit/images/@tee-SEQ/tee-os': OP-TEE paged mode not supported", str(exc.exception)) self.make_tee_bin('tee.bad2', 0, b'extra data') with self.assertRaises(ValueError) as exc: - self.checkFitTee('264_tee_os_opt_fit.dts', 'tee.bad2') + self.checkFitTee('fit/tee_os_opt.dts', 'tee.bad2') self.assertIn( "Node '/binman/fit/images/@tee-SEQ/tee-os': Invalid OP-TEE file: size mismatch (expected 0x4, have 0xe)", str(exc.exception)) @@ -6560,7 +6561,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testExtblobMissingOptional(self): """Test an image with an external blob that is optional""" with terminal.capture() as (stdout, stderr): - data = self._DoReadFileDtb('266_blob_ext_opt.dts', + data = self._DoReadFileDtb('blob/ext_opt.dts', allow_fake_blobs=False)[0] self.assertEqual(REFCODE_DATA, data) self.assertNotIn(MISSING_DATA, data) @@ -6568,7 +6569,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testExtblobFakedOptional(self): """Test an image with an external blob that is optional""" with terminal.capture() as (stdout, stderr): - data = self._DoReadFile('266_blob_ext_opt.dts') + data = self._DoReadFile('blob/ext_opt.dts') self.assertEqual(REFCODE_DATA, data) err = stderr.getvalue() self.assertRegex( @@ -6580,18 +6581,18 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testSectionInner(self): """Test an inner section with a size""" - data = self._DoReadFile('267_section_inner.dts') + data = self._DoReadFile('pack/section_inner.dts') expected = U_BOOT_DATA + tools.get_bytes(0, 12) self.assertEqual(expected, data) def testNull(self): """Test an image with a null entry""" - data = self._DoReadFile('268_null.dts') + data = self._DoReadFile('entry/null.dts') self.assertEqual(U_BOOT_DATA + b'\xff\xff\xff\xff' + U_BOOT_IMG_DATA, data) def testOverlap(self): """Test an image with a overlapping entry""" - data = self._DoReadFile('269_overlap.dts') + data = self._DoReadFile('entry/overlap.dts') self.assertEqual(U_BOOT_DATA[:1] + b'aa' + U_BOOT_DATA[3:], data) image = control.images['image'] @@ -6605,7 +6606,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testOverlapNull(self): """Test an image with a null overlap""" - data = self._DoReadFile('270_overlap_null.dts') + data = self._DoReadFile('entry/overlap_null.dts') self.assertEqual(U_BOOT_DATA, data[:len(U_BOOT_DATA)]) # Check the FMAP @@ -6639,7 +6640,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testOverlapBad(self): """Test an image with a bad overlapping entry""" with self.assertRaises(ValueError) as exc: - self._DoReadFile('271_overlap_bad.dts') + self._DoReadFile('entry/overlap_bad.dts') self.assertIn( "Node '/binman/inset': Offset 0x10 (16) ending at 0x12 (18) must overlap with existing entries", str(exc.exception)) @@ -6647,7 +6648,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testOverlapNoOffset(self): """Test an image with a bad overlapping entry""" with self.assertRaises(ValueError) as exc: - self._DoReadFile('272_overlap_no_size.dts') + self._DoReadFile('entry/overlap_no_size.dts') self.assertIn( "Node '/binman/inset': 'fill' entry is missing properties: size", str(exc.exception)) @@ -6659,7 +6660,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap TestFunctional._MakeInputFile('blob_syms.bin', tools.read_file(self.ElfTestFile('blob_syms.bin'))) - data = self._DoReadFile('273_blob_symbol.dts') + data = self._DoReadFile('blob/symbol.dts') syms = elf.GetSymbols(elf_fname, ['binman', 'image']) addr = elf.GetSymbolAddress(elf_fname, '__my_start_sym') @@ -6678,7 +6679,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap TestFunctional._MakeInputFile('blob_syms.bin', tools.read_file(self.ElfTestFile('blob_syms.bin'))) - data = self._DoReadFile('274_offset_from_elf.dts') + data = self._DoReadFile('entry/offset_from_elf.dts') syms = elf.GetSymbols(elf_fname, ['binman', 'image']) base = elf.GetSymbolAddress(elf_fname, '__my_start_sym') @@ -6701,7 +6702,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testFitAlign(self): """Test an image with an FIT with aligned external data""" - data = self._DoReadFile('275_fit_align.dts') + data = self._DoReadFile('fit/align.dts') self.assertEqual(4096, len(data)) dtb = fdt.Fdt.FromData(data) @@ -6728,7 +6729,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap test_subdir = os.path.join(self._indir, TEST_FDT_SUBDIR) with terminal.capture() as (stdout, stderr): data = self._DoReadFileDtb( - '276_fit_firmware_loadables.dts', + 'fit/firmware_loadables.dts', entry_args=entry_args, extra_indirs=[test_subdir])[0] @@ -6781,7 +6782,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test replacing an entry in a section""" expect_data = b'w' * len(U_BOOT_DATA + COMPRESS_DATA) entry_data, expected_fdtmap, image = self._RunReplaceCmd('section/blob', - expect_data, dts='241_replace_section_simple.dts') + expect_data, dts='entry/replace_section_simple.dts') self.assertEqual(expect_data, entry_data) entries = image.GetEntries() @@ -6808,7 +6809,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap expect_data = b'w' * len(U_BOOT_DATA + COMPRESS_DATA) entry_data, expected_fdtmap, image = self._RunReplaceCmd( 'section/section/blob', expect_data, - dts='278_replace_section_deep.dts') + dts='entry/replace_section_deep.dts') self.assertEqual(expect_data, entry_data) entries = image.GetEntries() @@ -6838,7 +6839,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test an image with a FIT inside where we replace its sibling""" self._SetupSplElf() fname = TestFunctional._MakeInputFile('once', b'available once') - self._DoReadFileRealDtb('277_replace_fit_sibling.dts') + self._DoReadFileRealDtb('fit/replace_sibling.dts') os.remove(fname) try: @@ -6859,11 +6860,11 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testX509Cert(self): """Test creating an X509 certificate""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': keyfile, } - data = self._DoReadFileDtb('279_x509_cert.dts', + data = self._DoReadFileDtb('security/x509_cert.dts', entry_args=entry_args)[0] cert = data[:-4] self.assertEqual(U_BOOT_DATA, data[-4:]) @@ -6872,12 +6873,12 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testX509CertMissing(self): """Test that binman still produces an image if openssl is missing""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': 'keyfile', } with terminal.capture() as (_, stderr): - self._DoTestFile('279_x509_cert.dts', + self._DoTestFile('security/x509_cert.dts', force_missing_bintools='openssl', entry_args=entry_args) err = stderr.getvalue() @@ -6885,21 +6886,21 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testPackRockchipTpl(self): """Test that an image with a Rockchip TPL binary can be created""" - data = self._DoReadFile('291_rockchip_tpl.dts') + data = self._DoReadFile('vendor/rockchip_tpl.dts') self.assertEqual(ROCKCHIP_TPL_DATA, data[:len(ROCKCHIP_TPL_DATA)]) def testMkimageMissingBlobMultiple(self): """Test missing blob with mkimage entry and multiple-data-files""" with terminal.capture() as (stdout, stderr): - self._DoTestFile('292_mkimage_missing_multiple.dts', allow_missing=True) + self._DoTestFile('mkimage/missing_multiple.dts', allow_missing=True) err = stderr.getvalue() self.assertIn("is missing external blobs and is non-functional", err) with self.assertRaises(ValueError) as e: - self._DoTestFile('292_mkimage_missing_multiple.dts', allow_missing=False) + self._DoTestFile('mkimage/missing_multiple.dts', allow_missing=False) self.assertIn("not found in input path", str(e.exception)) - def _PrepareSignEnv(self, dts='280_fit_sign.dts'): + def _PrepareSignEnv(self, dts='fit/sign.dts'): """Prepare sign environment Create private and public keys, add pubkey into dtb. @@ -6963,7 +6964,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test a non-FIT entry cannot be signed""" is_signed = False fit, fname, private_key, _ = self._PrepareSignEnv( - '281_sign_non_fit.dts') + 'security/sign_non_fit.dts') # do sign with private key with self.assertRaises(ValueError) as e: @@ -6987,7 +6988,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testSymbolNoWrite(self): """Test disabling of symbol writing""" self._SetupSplElf() - self.checkSymbols('282_symbols_disable.dts', U_BOOT_SPL_DATA, 0x1c, + self.checkSymbols('symbols/disable.dts', U_BOOT_SPL_DATA, 0x1c, no_write_symbols=True) def testSymbolNoWriteExpanded(self): @@ -6995,14 +6996,14 @@ fdt fdtmap Extract the devicetree blob from the fdtmap entry_args = { 'spl-dtb': '1', } - self.checkSymbols('282_symbols_disable.dts', U_BOOT_SPL_NODTB_DATA + + self.checkSymbols('symbols/disable.dts', U_BOOT_SPL_NODTB_DATA + U_BOOT_SPL_DTB_DATA, 0x38, entry_args=entry_args, use_expanded=True, no_write_symbols=True) def testMkimageSpecial(self): """Test mkimage ignores special hash-1 node""" - data = self._DoReadFile('283_mkimage_special.dts') + data = self._DoReadFile('mkimage/special.dts') # Just check that the data appears in the file somewhere self.assertIn(U_BOOT_DATA, data) @@ -7013,7 +7014,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'default-dt': 'test-fdt2', } data = self._DoReadFileDtb( - '284_fit_fdt_list.dts', + 'fit/fdt_list.dts', entry_args=entry_args, extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0] self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):]) @@ -7028,13 +7029,13 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'spl-bss-pad': 'y', 'spl-dtb': 'y', } - data = self._DoReadFileDtb('285_spl_expand.dts', + data = self._DoReadFileDtb('xpl/u-boot-spl.dts', use_expanded=True, entry_args=entry_args)[0] def testTemplate(self): """Test using a template""" TestFunctional._MakeInputFile('vga2.bin', b'#' + VGA_DATA) - data = self._DoReadFile('286_template.dts') + data = self._DoReadFile('entry/template.dts') first = U_BOOT_DATA + VGA_DATA + U_BOOT_DTB_DATA second = U_BOOT_DATA + b'#' + VGA_DATA + U_BOOT_DTB_DATA self.assertEqual(U_BOOT_IMG_DATA + first + second, data) @@ -7059,7 +7060,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test using a template with 'multiple-images' enabled""" TestFunctional._MakeInputFile('my-blob.bin', b'blob') TestFunctional._MakeInputFile('my-blob2.bin', b'other') - retcode = self._DoTestFile('287_template_multi.dts') + retcode = self._DoTestFile('entry/template_multi.dts') self.assertEqual(0, retcode) image = control.images['image'] @@ -7069,7 +7070,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testTemplateFit(self): """Test using a template in a FIT""" - fit_data = self._DoReadFile('288_template_fit.dts') + fit_data = self._DoReadFile('fit/template.dts') fname = os.path.join(self._indir, 'fit_data.fit') tools.write_file(fname, fit_data) out = tools.run('dumpimage', '-l', fname) @@ -7077,7 +7078,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testTemplateSection(self): """Test using a template in a section (not at top level)""" TestFunctional._MakeInputFile('vga2.bin', b'#' + VGA_DATA) - data = self._DoReadFile('289_template_section.dts') + data = self._DoReadFile('entry/template_section.dts') first = U_BOOT_DATA + VGA_DATA + U_BOOT_DTB_DATA second = U_BOOT_DATA + b'#' + VGA_DATA + U_BOOT_DTB_DATA self.assertEqual(U_BOOT_IMG_DATA + first + second + first, data) @@ -7085,7 +7086,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testMkimageSymbols(self): """Test using mkimage to build an image with symbols in it""" self._SetupSplElf('u_boot_binman_syms') - data = self._DoReadFile('290_mkimage_sym.dts') + data = self._DoReadFile('mkimage/sym.dts') image = control.images['image'] entries = image.GetEntries() @@ -7151,7 +7152,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap entry_args = { 'atf-bl31-path': 'bl31.elf', } - data = self._DoReadFileDtb('309_template_phandle.dts', + data = self._DoReadFileDtb('entry/template_phandle.dts', entry_args=entry_args) fname = tools.get_output_filename('image.bin') out = tools.run('dumpimage', '-l', fname) @@ -7167,7 +7168,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap 'atf-bl31-path': 'bl31.elf', } with self.assertRaises(ValueError) as e: - self._DoReadFileDtb('310_template_phandle_dup.dts', + self._DoReadFileDtb('entry/template_phandle_dup.dts', entry_args=entry_args) self.assertIn( 'Duplicate phandle 1 in nodes /binman/image/fit/images/atf/atf-bl31 and /binman/image-2/fit/images/atf/atf-bl31', @@ -7175,69 +7176,69 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testTIBoardConfig(self): """Test that a schema validated board config file can be generated""" - data = self._DoReadFile('293_ti_board_cfg.dts') + data = self._DoReadFile('vendor/ti_board_cfg.dts') self.assertEqual(TI_BOARD_CONFIG_DATA, data) def testTIBoardConfigLint(self): """Test that an incorrectly linted config file would generate error""" with self.assertRaises(ValueError) as e: - data = self._DoReadFile('323_ti_board_cfg_phony.dts') + data = self._DoReadFile('vendor/ti_board_cfg_phony.dts') self.assertIn("Yamllint error", str(e.exception)) def testTIBoardConfigCombined(self): """Test that a schema validated combined board config file can be generated""" - data = self._DoReadFile('294_ti_board_cfg_combined.dts') + data = self._DoReadFile('vendor/ti_board_cfg_combined.dts') configlen_noheader = TI_BOARD_CONFIG_DATA * 4 self.assertGreater(data, configlen_noheader) def testTIBoardConfigNoDataType(self): """Test that error is thrown when data type is not supported""" with self.assertRaises(ValueError) as e: - data = self._DoReadFile('295_ti_board_cfg_no_type.dts') + data = self._DoReadFile('vendor/ti_board_cfg_no_type.dts') self.assertIn("Schema validation error", str(e.exception)) def testPackTiSecure(self): """Test that an image with a TI secured binary can be created""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': keyfile, } - data = self._DoReadFileDtb('296_ti_secure.dts', + data = self._DoReadFileDtb('vendor/ti_secure.dts', entry_args=entry_args)[0] self.assertGreater(len(data), len(TI_UNSECURE_DATA)) def testPackTiSecureFirewall(self): """Test that an image with a TI secured binary can be created""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': keyfile, } - data_no_firewall = self._DoReadFileDtb('296_ti_secure.dts', + data_no_firewall = self._DoReadFileDtb('vendor/ti_secure.dts', entry_args=entry_args)[0] - data_firewall = self._DoReadFileDtb('324_ti_secure_firewall.dts', + data_firewall = self._DoReadFileDtb('vendor/ti_secure_firewall.dts', entry_args=entry_args)[0] self.assertGreater(len(data_firewall),len(data_no_firewall)) def testPackTiSecureFirewallMissingProperty(self): """Test that an image with a TI secured binary can be created""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': keyfile, } with self.assertRaises(ValueError) as e: - data_firewall = self._DoReadFileDtb('325_ti_secure_firewall_missing_property.dts', + data_firewall = self._DoReadFileDtb('vendor/ti_secure_firewall_missing_property.dts', entry_args=entry_args)[0] self.assertRegex(str(e.exception), "Node '/binman/ti-secure': Subnode 'firewall-0-2' is missing properties: id,region") def testPackTiSecureMissingTool(self): """Test that an image with a TI secured binary (non-functional) can be created when openssl is missing""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': keyfile, } with terminal.capture() as (_, stderr): - self._DoTestFile('296_ti_secure.dts', + self._DoTestFile('vendor/ti_secure.dts', force_missing_bintools='openssl', entry_args=entry_args) err = stderr.getvalue() @@ -7245,15 +7246,15 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testPackTiSecureROM(self): """Test that a ROM image with a TI secured binary can be created""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': keyfile, } - data = self._DoReadFileDtb('297_ti_secure_rom.dts', + data = self._DoReadFileDtb('vendor/ti_secure_rom.dts', entry_args=entry_args)[0] - data_a = self._DoReadFileDtb('299_ti_secure_rom_a.dts', + data_a = self._DoReadFileDtb('vendor/ti_secure_rom_a.dts', entry_args=entry_args)[0] - data_b = self._DoReadFileDtb('300_ti_secure_rom_b.dts', + data_b = self._DoReadFileDtb('vendor/ti_secure_rom_b.dts', entry_args=entry_args)[0] self.assertGreater(len(data), len(TI_UNSECURE_DATA)) self.assertGreater(len(data_a), len(TI_UNSECURE_DATA)) @@ -7261,18 +7262,18 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testPackTiSecureROMCombined(self): """Test that a ROM image with a TI secured binary can be created""" - keyfile = self.TestFile('key.key') + keyfile = self.TestFile('security/key.key') entry_args = { 'keyfile': keyfile, } - data = self._DoReadFileDtb('298_ti_secure_rom_combined.dts', + data = self._DoReadFileDtb('vendor/ti_secure_rom_combined.dts', entry_args=entry_args)[0] self.assertGreater(len(data), len(TI_UNSECURE_DATA)) def testEncryptedNoAlgo(self): """Test encrypted node with missing required properties""" with self.assertRaises(ValueError) as e: - self._DoReadFileDtb('301_encrypted_no_algo.dts') + self._DoReadFileDtb('security/encrypted_no_algo.dts') self.assertIn( "Node '/binman/fit/images/u-boot/encrypted': 'encrypted' entry is missing properties: algo iv-filename", str(e.exception)) @@ -7280,21 +7281,21 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testEncryptedInvalidIvfile(self): """Test encrypted node with invalid iv file""" with self.assertRaises(ValueError) as e: - self._DoReadFileDtb('302_encrypted_invalid_iv_file.dts') + self._DoReadFileDtb('security/encrypted_invalid_iv_file.dts') self.assertIn("Filename 'invalid-iv-file' not found in input path", str(e.exception)) def testEncryptedMissingKey(self): """Test encrypted node with missing key properties""" with self.assertRaises(ValueError) as e: - self._DoReadFileDtb('303_encrypted_missing_key.dts') + self._DoReadFileDtb('security/encrypted_missing_key.dts') self.assertIn( "Node '/binman/fit/images/u-boot/encrypted': Provide either 'key-filename' or 'key-source'", str(e.exception)) def testEncryptedKeySource(self): """Test encrypted node with key-source property""" - data = self._DoReadFileDtb('304_encrypted_key_source.dts')[0] + data = self._DoReadFileDtb('security/encrypted_key_source.dts')[0] dtb = fdt.Fdt.FromData(data) dtb.Scan() @@ -7308,7 +7309,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testEncryptedKeyFile(self): """Test encrypted node with key-filename property""" - data = self._DoReadFileDtb('305_encrypted_key_file.dts')[0] + data = self._DoReadFileDtb('security/encrypted_key_file.dts')[0] dtb = fdt.Fdt.FromData(data) dtb.Scan() @@ -7324,16 +7325,16 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testKeyNameHintIsPathSplPubkeyDtb(self): """Test that binman errors out on key-name-hint being a path""" with self.assertRaises(ValueError) as e: - self._DoReadFile('348_key_name_hint_dir_spl_pubkey_dtb.dts') + self._DoReadFile('security/key_name_hint_dir_spl_pubkey_dtb.dts') self.assertIn( 'Node \'/binman/u-boot-spl-pubkey-dtb\': \'keys/key\' is a path not a filename', str(e.exception)) def testSplPubkeyDtb(self): """Test u_boot_spl_pubkey_dtb etype""" - data = tools.read_file(self.TestFile("key.pem")) + data = tools.read_file(self.TestFile("security/key.pem")) self._MakeInputFile("key.crt", data) - self._DoReadFileRealDtb('306_spl_pubkey_dtb.dts') + self._DoReadFileRealDtb('security/spl_pubkey_dtb.dts') image = control.images['image'] entries = image.GetEntries() dtb_entry = entries['u-boot-spl-pubkey-dtb'] @@ -7353,12 +7354,12 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test xilinx-bootgen etype""" bootgen = bintool.Bintool.create('bootgen') self._CheckBintool(bootgen) - data = tools.read_file(self.TestFile("key.key")) + data = tools.read_file(self.TestFile("security/key.key")) self._MakeInputFile("psk.pem", data) self._MakeInputFile("ssk.pem", data) self._SetupPmuFwlElf() self._SetupSplElf() - self._DoReadFileRealDtb('307_xilinx_bootgen_sign.dts') + self._DoReadFileRealDtb('security/xilinx_bootgen_sign.dts') image_fname = tools.get_output_filename('image.bin') # Read partition header table and check if authentication is enabled @@ -7382,12 +7383,12 @@ fdt fdtmap Extract the devicetree blob from the fdtmap """Test xilinx-bootgen etype""" bootgen = bintool.Bintool.create('bootgen') self._CheckBintool(bootgen) - data = tools.read_file(self.TestFile("key.key")) + data = tools.read_file(self.TestFile("security/key.key")) self._MakeInputFile("psk.pem", data) self._MakeInputFile("ssk.pem", data) self._SetupPmuFwlElf() self._SetupSplElf() - self._DoReadFileRealDtb('308_xilinx_bootgen_sign_enc.dts') + self._DoReadFileRealDtb('security/xilinx_bootgen_sign_enc.dts') image_fname = tools.get_output_filename('image.bin') # Read boot header in order to verify encryption source and @@ -7414,13 +7415,13 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testXilinxBootgenMissing(self): """Test that binman still produces an image if bootgen is missing""" - data = tools.read_file(self.TestFile("key.key")) + data = tools.read_file(self.TestFile("security/key.key")) self._MakeInputFile("psk.pem", data) self._MakeInputFile("ssk.pem", data) self._SetupPmuFwlElf() self._SetupSplElf() with terminal.capture() as (_, stderr): - self._DoTestFile('307_xilinx_bootgen_sign.dts', + self._DoTestFile('security/xilinx_bootgen_sign.dts', force_missing_bintools='bootgen') err = stderr.getvalue() self.assertRegex(err, @@ -7517,48 +7518,120 @@ fdt fdtmap Extract the devicetree blob from the fdtmap def testCapsuleGen(self): """Test generation of EFI capsule""" - data = self._DoReadFile('311_capsule.dts') + data = self._DoReadFile('capsule/capsule.dts') self._CheckCapsule(data) def testSignedCapsuleGen(self): """Test generation of EFI capsule""" - data = tools.read_file(self.TestFile("key.key")) + data = tools.read_file(self.TestFile("security/key.key")) self._MakeInputFile("key.key", data) - data = tools.read_file(self.TestFile("key.pem")) + data = tools.read_file(self.TestFile("security/key.pem")) self._MakeInputFile("key.crt", data) - data = self._DoReadFile('312_capsule_signed.dts') + data = self._DoReadFile('capsule/signed.dts') self._CheckCapsule(data, signed_capsule=True) + def testPkcs11SignedCapsuleGen(self): + """Test generation of EFI capsule (with PKCS11)""" + data = tools.read_file(self.TestFile("security/key.key")) + private_key = self._MakeInputFile("key.key", data) + data = tools.read_file(self.TestFile("security/key.pem")) + cert_file = self._MakeInputFile("key.crt", data) + + softhsm2_util = bintool.Bintool.create('softhsm2_util') + self._CheckBintool(softhsm2_util) + + pkcs11_tool = bintool.Bintool.create('pkcs11-tool') + self._CheckBintool(pkcs11_tool) + + prefix = "testPkcs11SignedCapsuleGen." + # Configure SoftHSMv2 + data = tools.read_file(self.TestFile('fit/softhsm2.conf')) + softhsm2_conf = self._MakeInputFile(f'{prefix}softhsm2.conf', data) + softhsm2_tokens_dir = self._MakeInputDir(f'{prefix}softhsm2.tokens') + + with open(softhsm2_conf, 'a') as f: + f.write(f'directories.tokendir = {softhsm2_tokens_dir}\n') + + # Find the path to softhsm2 library + p11_kit = bintool.Bintool.create('p11-kit') + self._CheckBintool(p11_kit) + + p11_kit_config = configparser.ConfigParser() + out = tools.run('p11-kit', 'print-config') + p11_kit_config.read_string(out) + softhsm2_lib = p11_kit_config.get('softhsm2', 'module', + fallback=None) + self.assertIsNotNone(softhsm2_lib) + + with unittest.mock.patch.dict('os.environ', + {'SOFTHSM2_CONF': softhsm2_conf, + 'PKCS11_MODULE_PATH': softhsm2_lib}): + tools.run('softhsm2-util', '--init-token', '--free', '--label', + 'U-Boot token', '--pin', '1111', '--so-pin', + '222222') + tools.run('pkcs11-tool', '--module', softhsm2_lib, + '--write-object', cert_file, '--pin', '1111', + '--type', 'cert', '--id', '999999', '--label', + 'test_cert', '--login') + tools.run('softhsm2-util', '--import', private_key, '--token', + 'U-Boot token', '--label', 'test_key', '--id', '999999', + '--pin', '1111') + data = self._DoReadFile('capsule/signed_pkcs11.dts') + + self._CheckCapsule(data, signed_capsule=True) + + hdr = self._GetCapsuleHeaders(data) + monotonic_count = hdr['EFI_FIRMWARE_IMAGE_AUTH.MONOTONIC_COUNT'] + + # UEFI standard requires that signature is checked over payload followed + # by a monotonic count as little endian 64-bit integer. + sig_input = self._MakeInputFile("sig_input", EFI_CAPSULE_DATA) + with open(sig_input, 'ab') as f: + f.write(struct.pack('; - #size-cells = <1>; - - binman { - u-boot { - }; - }; -}; diff --git a/tools/binman/test/Makefile b/tools/binman/test/Makefile index d5e4c0f556a..6b42db6559f 100644 --- a/tools/binman/test/Makefile +++ b/tools/binman/test/Makefile @@ -85,7 +85,7 @@ blob_syms: blob_syms.c elf_sections: CFLAGS += $(LDS_EFL_SECTIONS) elf_sections: elf_sections.c -dummy-rsa-engine.so: dummy-rsa-engine.c +dummy-rsa-engine.so: $(SRC)fit/dummy-rsa-engine.c $(CC) -fPIC -shared -lcrypto -lssl -o $@ $< clean: diff --git a/tools/binman/test/023_blob.dts b/tools/binman/test/blob/blob.dts similarity index 100% rename from tools/binman/test/023_blob.dts rename to tools/binman/test/blob/blob.dts diff --git a/tools/binman/test/157_blob_ext.dts b/tools/binman/test/blob/ext.dts similarity index 100% rename from tools/binman/test/157_blob_ext.dts rename to tools/binman/test/blob/ext.dts diff --git a/tools/binman/test/215_blob_ext_list.dts b/tools/binman/test/blob/ext_list.dts similarity index 100% rename from tools/binman/test/215_blob_ext_list.dts rename to tools/binman/test/blob/ext_list.dts diff --git a/tools/binman/test/218_blob_ext_list_fake.dts b/tools/binman/test/blob/ext_list_fake.dts similarity index 100% rename from tools/binman/test/218_blob_ext_list_fake.dts rename to tools/binman/test/blob/ext_list_fake.dts diff --git a/tools/binman/test/216_blob_ext_list_missing.dts b/tools/binman/test/blob/ext_list_missing.dts similarity index 100% rename from tools/binman/test/216_blob_ext_list_missing.dts rename to tools/binman/test/blob/ext_list_missing.dts diff --git a/tools/binman/test/158_blob_ext_missing.dts b/tools/binman/test/blob/ext_missing.dts similarity index 100% rename from tools/binman/test/158_blob_ext_missing.dts rename to tools/binman/test/blob/ext_missing.dts diff --git a/tools/binman/test/159_blob_ext_missing_sect.dts b/tools/binman/test/blob/ext_missing_sect.dts similarity index 100% rename from tools/binman/test/159_blob_ext_missing_sect.dts rename to tools/binman/test/blob/ext_missing_sect.dts diff --git a/tools/binman/test/266_blob_ext_opt.dts b/tools/binman/test/blob/ext_opt.dts similarity index 100% rename from tools/binman/test/266_blob_ext_opt.dts rename to tools/binman/test/blob/ext_opt.dts diff --git a/tools/binman/test/217_fake_blob.dts b/tools/binman/test/blob/fake.dts similarity index 100% rename from tools/binman/test/217_fake_blob.dts rename to tools/binman/test/blob/fake.dts diff --git a/tools/binman/test/173_missing_blob.dts b/tools/binman/test/blob/missing.dts similarity index 100% rename from tools/binman/test/173_missing_blob.dts rename to tools/binman/test/blob/missing.dts diff --git a/tools/binman/test/068_blob_named_by_arg.dts b/tools/binman/test/blob/named_by_arg.dts similarity index 100% rename from tools/binman/test/068_blob_named_by_arg.dts rename to tools/binman/test/blob/named_by_arg.dts diff --git a/tools/binman/test/273_blob_symbol.dts b/tools/binman/test/blob/symbol.dts similarity index 100% rename from tools/binman/test/273_blob_symbol.dts rename to tools/binman/test/blob/symbol.dts diff --git a/tools/binman/test/319_capsule_accept.dts b/tools/binman/test/capsule/accept.dts similarity index 100% rename from tools/binman/test/319_capsule_accept.dts rename to tools/binman/test/capsule/accept.dts diff --git a/tools/binman/test/321_capsule_accept_missing_guid.dts b/tools/binman/test/capsule/accept_missing_guid.dts similarity index 100% rename from tools/binman/test/321_capsule_accept_missing_guid.dts rename to tools/binman/test/capsule/accept_missing_guid.dts diff --git a/tools/binman/test/323_capsule_accept_revert_missing.dts b/tools/binman/test/capsule/accept_revert_missing.dts similarity index 100% rename from tools/binman/test/323_capsule_accept_revert_missing.dts rename to tools/binman/test/capsule/accept_revert_missing.dts diff --git a/tools/binman/test/311_capsule.dts b/tools/binman/test/capsule/capsule.dts similarity index 100% rename from tools/binman/test/311_capsule.dts rename to tools/binman/test/capsule/capsule.dts diff --git a/tools/binman/test/322_empty_capsule_type_missing.dts b/tools/binman/test/capsule/empty_type_missing.dts similarity index 100% rename from tools/binman/test/322_empty_capsule_type_missing.dts rename to tools/binman/test/capsule/empty_type_missing.dts diff --git a/tools/binman/test/318_capsule_missing_guid.dts b/tools/binman/test/capsule/missing_guid.dts similarity index 100% rename from tools/binman/test/318_capsule_missing_guid.dts rename to tools/binman/test/capsule/missing_guid.dts diff --git a/tools/binman/test/317_capsule_missing_index.dts b/tools/binman/test/capsule/missing_index.dts similarity index 100% rename from tools/binman/test/317_capsule_missing_index.dts rename to tools/binman/test/capsule/missing_index.dts diff --git a/tools/binman/test/316_capsule_missing_key.dts b/tools/binman/test/capsule/missing_key.dts similarity index 100% rename from tools/binman/test/316_capsule_missing_key.dts rename to tools/binman/test/capsule/missing_key.dts diff --git a/tools/binman/test/315_capsule_oemflags.dts b/tools/binman/test/capsule/oemflags.dts similarity index 100% rename from tools/binman/test/315_capsule_oemflags.dts rename to tools/binman/test/capsule/oemflags.dts diff --git a/tools/binman/test/320_capsule_revert.dts b/tools/binman/test/capsule/revert.dts similarity index 100% rename from tools/binman/test/320_capsule_revert.dts rename to tools/binman/test/capsule/revert.dts diff --git a/tools/binman/test/312_capsule_signed.dts b/tools/binman/test/capsule/signed.dts similarity index 100% rename from tools/binman/test/312_capsule_signed.dts rename to tools/binman/test/capsule/signed.dts diff --git a/tools/binman/test/capsule/signed_pkcs11.dts b/tools/binman/test/capsule/signed_pkcs11.dts new file mode 100644 index 00000000000..bb87e18a15f --- /dev/null +++ b/tools/binman/test/capsule/signed_pkcs11.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + binman { + efi-capsule { + image-index = <0x1>; + /* Image GUID for testing capsule update */ + image-guid = "binman-test"; + hardware-instance = <0x0>; + monotonic-count = <0x1>; + dump-signature; + private-key = "pkcs11:token=U-Boot%20token;object=test_key;type=private;pin-value=1111"; + public-key-cert = "pkcs11:token=U-Boot%20token;object=test_cert;type=cert;pin-value=1111"; + + blob { + filename = "capsule_input.bin"; + }; + }; + }; +}; diff --git a/tools/binman/test/314_capsule_signed_ver.dts b/tools/binman/test/capsule/signed_ver.dts similarity index 100% rename from tools/binman/test/314_capsule_signed_ver.dts rename to tools/binman/test/capsule/signed_ver.dts diff --git a/tools/binman/test/313_capsule_version.dts b/tools/binman/test/capsule/version.dts similarity index 100% rename from tools/binman/test/313_capsule_version.dts rename to tools/binman/test/capsule/version.dts diff --git a/tools/binman/test/106_cbfs_bad_arch.dts b/tools/binman/test/cbfs/bad_arch.dts similarity index 100% rename from tools/binman/test/106_cbfs_bad_arch.dts rename to tools/binman/test/cbfs/bad_arch.dts diff --git a/tools/binman/test/109_cbfs_bad_compress.dts b/tools/binman/test/cbfs/bad_compress.dts similarity index 100% rename from tools/binman/test/109_cbfs_bad_compress.dts rename to tools/binman/test/cbfs/bad_compress.dts diff --git a/tools/binman/test/126_cbfs_bad_type.dts b/tools/binman/test/cbfs/bad_type.dts similarity index 100% rename from tools/binman/test/126_cbfs_bad_type.dts rename to tools/binman/test/cbfs/bad_type.dts diff --git a/tools/binman/test/110_cbfs_name.dts b/tools/binman/test/cbfs/name.dts similarity index 100% rename from tools/binman/test/110_cbfs_name.dts rename to tools/binman/test/cbfs/name.dts diff --git a/tools/binman/test/108_cbfs_no_contents.dts b/tools/binman/test/cbfs/no_contents.dts similarity index 100% rename from tools/binman/test/108_cbfs_no_contents.dts rename to tools/binman/test/cbfs/no_contents.dts diff --git a/tools/binman/test/107_cbfs_no_size.dts b/tools/binman/test/cbfs/no_size.dts similarity index 100% rename from tools/binman/test/107_cbfs_no_size.dts rename to tools/binman/test/cbfs/no_size.dts diff --git a/tools/binman/test/114_cbfs_offset.dts b/tools/binman/test/cbfs/offset.dts similarity index 100% rename from tools/binman/test/114_cbfs_offset.dts rename to tools/binman/test/cbfs/offset.dts diff --git a/tools/binman/test/102_cbfs_raw.dts b/tools/binman/test/cbfs/raw.dts similarity index 100% rename from tools/binman/test/102_cbfs_raw.dts rename to tools/binman/test/cbfs/raw.dts diff --git a/tools/binman/test/105_cbfs_raw_compress.dts b/tools/binman/test/cbfs/raw_compress.dts similarity index 100% rename from tools/binman/test/105_cbfs_raw_compress.dts rename to tools/binman/test/cbfs/raw_compress.dts diff --git a/tools/binman/test/103_cbfs_raw_ppc.dts b/tools/binman/test/cbfs/raw_ppc.dts similarity index 100% rename from tools/binman/test/103_cbfs_raw_ppc.dts rename to tools/binman/test/cbfs/raw_ppc.dts diff --git a/tools/binman/test/142_replace_cbfs.dts b/tools/binman/test/cbfs/replace.dts similarity index 100% rename from tools/binman/test/142_replace_cbfs.dts rename to tools/binman/test/cbfs/replace.dts diff --git a/tools/binman/test/104_cbfs_stage.dts b/tools/binman/test/cbfs/stage.dts similarity index 100% rename from tools/binman/test/104_cbfs_stage.dts rename to tools/binman/test/cbfs/stage.dts diff --git a/tools/binman/test/125_cbfs_update.dts b/tools/binman/test/cbfs/update.dts similarity index 100% rename from tools/binman/test/125_cbfs_update.dts rename to tools/binman/test/cbfs/update.dts diff --git a/tools/binman/test/067_fmap.dts b/tools/binman/test/cros/fmap.dts similarity index 100% rename from tools/binman/test/067_fmap.dts rename to tools/binman/test/cros/fmap.dts diff --git a/tools/binman/test/071_gbb.dts b/tools/binman/test/cros/gbb.dts similarity index 100% rename from tools/binman/test/071_gbb.dts rename to tools/binman/test/cros/gbb.dts diff --git a/tools/binman/test/073_gbb_no_size.dts b/tools/binman/test/cros/gbb_no_size.dts similarity index 100% rename from tools/binman/test/073_gbb_no_size.dts rename to tools/binman/test/cros/gbb_no_size.dts diff --git a/tools/binman/test/072_gbb_too_small.dts b/tools/binman/test/cros/gbb_too_small.dts similarity index 100% rename from tools/binman/test/072_gbb_too_small.dts rename to tools/binman/test/cros/gbb_too_small.dts diff --git a/tools/binman/test/074_vblock.dts b/tools/binman/test/cros/vblock.dts similarity index 100% rename from tools/binman/test/074_vblock.dts rename to tools/binman/test/cros/vblock.dts diff --git a/tools/binman/test/077_vblock_bad_entry.dts b/tools/binman/test/cros/vblock_bad_entry.dts similarity index 100% rename from tools/binman/test/077_vblock_bad_entry.dts rename to tools/binman/test/cros/vblock_bad_entry.dts diff --git a/tools/binman/test/076_vblock_bad_phandle.dts b/tools/binman/test/cros/vblock_bad_phandle.dts similarity index 100% rename from tools/binman/test/076_vblock_bad_phandle.dts rename to tools/binman/test/cros/vblock_bad_phandle.dts diff --git a/tools/binman/test/189_vblock_content.dts b/tools/binman/test/cros/vblock_content.dts similarity index 100% rename from tools/binman/test/189_vblock_content.dts rename to tools/binman/test/cros/vblock_content.dts diff --git a/tools/binman/test/075_vblock_no_content.dts b/tools/binman/test/cros/vblock_no_content.dts similarity index 100% rename from tools/binman/test/075_vblock_no_content.dts rename to tools/binman/test/cros/vblock_no_content.dts diff --git a/tools/binman/test/262_absent.dts b/tools/binman/test/entry/absent.dts similarity index 100% rename from tools/binman/test/262_absent.dts rename to tools/binman/test/entry/absent.dts diff --git a/tools/binman/test/198_collection.dts b/tools/binman/test/entry/collection.dts similarity index 100% rename from tools/binman/test/198_collection.dts rename to tools/binman/test/entry/collection.dts diff --git a/tools/binman/test/246_collection_other.dts b/tools/binman/test/entry/collection_other.dts similarity index 100% rename from tools/binman/test/246_collection_other.dts rename to tools/binman/test/entry/collection_other.dts diff --git a/tools/binman/test/199_collection_section.dts b/tools/binman/test/entry/collection_section.dts similarity index 100% rename from tools/binman/test/199_collection_section.dts rename to tools/binman/test/entry/collection_section.dts diff --git a/tools/binman/test/083_compress.dts b/tools/binman/test/entry/compress.dts similarity index 100% rename from tools/binman/test/083_compress.dts rename to tools/binman/test/entry/compress.dts diff --git a/tools/binman/test/186_compress_extra.dts b/tools/binman/test/entry/compress_extra.dts similarity index 100% rename from tools/binman/test/186_compress_extra.dts rename to tools/binman/test/entry/compress_extra.dts diff --git a/tools/binman/test/182_compress_image.dts b/tools/binman/test/entry/compress_image.dts similarity index 100% rename from tools/binman/test/182_compress_image.dts rename to tools/binman/test/entry/compress_image.dts diff --git a/tools/binman/test/183_compress_image_less.dts b/tools/binman/test/entry/compress_image_less.dts similarity index 100% rename from tools/binman/test/183_compress_image_less.dts rename to tools/binman/test/entry/compress_image_less.dts diff --git a/tools/binman/test/185_compress_section.dts b/tools/binman/test/entry/compress_section.dts similarity index 100% rename from tools/binman/test/185_compress_section.dts rename to tools/binman/test/entry/compress_section.dts diff --git a/tools/binman/test/184_compress_section_size.dts b/tools/binman/test/entry/compress_section_size.dts similarity index 100% rename from tools/binman/test/184_compress_section_size.dts rename to tools/binman/test/entry/compress_section_size.dts diff --git a/tools/binman/test/096_elf.dts b/tools/binman/test/entry/elf.dts similarity index 100% rename from tools/binman/test/096_elf.dts rename to tools/binman/test/entry/elf.dts diff --git a/tools/binman/test/097_elf_strip.dts b/tools/binman/test/entry/elf_strip.dts similarity index 100% rename from tools/binman/test/097_elf_strip.dts rename to tools/binman/test/entry/elf_strip.dts diff --git a/tools/binman/test/062_entry_args.dts b/tools/binman/test/entry/entry_args.dts similarity index 100% rename from tools/binman/test/062_entry_args.dts rename to tools/binman/test/entry/entry_args.dts diff --git a/tools/binman/test/063_entry_args_missing.dts b/tools/binman/test/entry/entry_args_missing.dts similarity index 100% rename from tools/binman/test/063_entry_args_missing.dts rename to tools/binman/test/entry/entry_args_missing.dts diff --git a/tools/binman/test/064_entry_args_required.dts b/tools/binman/test/entry/entry_args_required.dts similarity index 100% rename from tools/binman/test/064_entry_args_required.dts rename to tools/binman/test/entry/entry_args_required.dts diff --git a/tools/binman/test/065_entry_args_unknown_datatype.dts b/tools/binman/test/entry/entry_args_unknown_datatype.dts similarity index 100% rename from tools/binman/test/065_entry_args_unknown_datatype.dts rename to tools/binman/test/entry/entry_args_unknown_datatype.dts diff --git a/tools/binman/test/174_env.dts b/tools/binman/test/entry/env.dts similarity index 100% rename from tools/binman/test/174_env.dts rename to tools/binman/test/entry/env.dts diff --git a/tools/binman/test/175_env_no_size.dts b/tools/binman/test/entry/env_no_size.dts similarity index 100% rename from tools/binman/test/175_env_no_size.dts rename to tools/binman/test/entry/env_no_size.dts diff --git a/tools/binman/test/176_env_too_small.dts b/tools/binman/test/entry/env_too_small.dts similarity index 100% rename from tools/binman/test/176_env_too_small.dts rename to tools/binman/test/entry/env_too_small.dts diff --git a/tools/binman/test/084_files.dts b/tools/binman/test/entry/files.dts similarity index 100% rename from tools/binman/test/084_files.dts rename to tools/binman/test/entry/files.dts diff --git a/tools/binman/test/190_files_align.dts b/tools/binman/test/entry/files_align.dts similarity index 100% rename from tools/binman/test/190_files_align.dts rename to tools/binman/test/entry/files_align.dts diff --git a/tools/binman/test/085_files_compress.dts b/tools/binman/test/entry/files_compress.dts similarity index 100% rename from tools/binman/test/085_files_compress.dts rename to tools/binman/test/entry/files_compress.dts diff --git a/tools/binman/test/087_files_no_pattern.dts b/tools/binman/test/entry/files_no_pattern.dts similarity index 100% rename from tools/binman/test/087_files_no_pattern.dts rename to tools/binman/test/entry/files_no_pattern.dts diff --git a/tools/binman/test/086_files_none.dts b/tools/binman/test/entry/files_none.dts similarity index 100% rename from tools/binman/test/086_files_none.dts rename to tools/binman/test/entry/files_none.dts diff --git a/tools/binman/test/069_fill.dts b/tools/binman/test/entry/fill.dts similarity index 100% rename from tools/binman/test/069_fill.dts rename to tools/binman/test/entry/fill.dts diff --git a/tools/binman/test/080_fill_empty.dts b/tools/binman/test/entry/fill_empty.dts similarity index 100% rename from tools/binman/test/080_fill_empty.dts rename to tools/binman/test/entry/fill_empty.dts diff --git a/tools/binman/test/070_fill_no_size.dts b/tools/binman/test/entry/fill_no_size.dts similarity index 100% rename from tools/binman/test/070_fill_no_size.dts rename to tools/binman/test/entry/fill_no_size.dts diff --git a/tools/binman/test/188_image_entryarg.dts b/tools/binman/test/entry/image_entryarg.dts similarity index 100% rename from tools/binman/test/188_image_entryarg.dts rename to tools/binman/test/entry/image_entryarg.dts diff --git a/tools/binman/test/127_list.dts b/tools/binman/test/entry/list.dts similarity index 100% rename from tools/binman/test/127_list.dts rename to tools/binman/test/entry/list.dts diff --git a/tools/binman/test/056_name_prefix.dts b/tools/binman/test/entry/name_prefix.dts similarity index 100% rename from tools/binman/test/056_name_prefix.dts rename to tools/binman/test/entry/name_prefix.dts diff --git a/tools/binman/test/268_null.dts b/tools/binman/test/entry/null.dts similarity index 100% rename from tools/binman/test/268_null.dts rename to tools/binman/test/entry/null.dts diff --git a/tools/binman/test/274_offset_from_elf.dts b/tools/binman/test/entry/offset_from_elf.dts similarity index 100% rename from tools/binman/test/274_offset_from_elf.dts rename to tools/binman/test/entry/offset_from_elf.dts diff --git a/tools/binman/test/269_overlap.dts b/tools/binman/test/entry/overlap.dts similarity index 100% rename from tools/binman/test/269_overlap.dts rename to tools/binman/test/entry/overlap.dts diff --git a/tools/binman/test/271_overlap_bad.dts b/tools/binman/test/entry/overlap_bad.dts similarity index 100% rename from tools/binman/test/271_overlap_bad.dts rename to tools/binman/test/entry/overlap_bad.dts diff --git a/tools/binman/test/272_overlap_no_size.dts b/tools/binman/test/entry/overlap_no_size.dts similarity index 100% rename from tools/binman/test/272_overlap_no_size.dts rename to tools/binman/test/entry/overlap_no_size.dts diff --git a/tools/binman/test/270_overlap_null.dts b/tools/binman/test/entry/overlap_null.dts similarity index 100% rename from tools/binman/test/270_overlap_null.dts rename to tools/binman/test/entry/overlap_null.dts diff --git a/tools/binman/test/045_prop_test.dts b/tools/binman/test/entry/prop_test.dts similarity index 100% rename from tools/binman/test/045_prop_test.dts rename to tools/binman/test/entry/prop_test.dts diff --git a/tools/binman/test/191_read_image_skip.dts b/tools/binman/test/entry/read_image_skip.dts similarity index 100% rename from tools/binman/test/191_read_image_skip.dts rename to tools/binman/test/entry/read_image_skip.dts diff --git a/tools/binman/test/346_remove_template.dts b/tools/binman/test/entry/remove_template.dts similarity index 100% rename from tools/binman/test/346_remove_template.dts rename to tools/binman/test/entry/remove_template.dts diff --git a/tools/binman/test/132_replace.dts b/tools/binman/test/entry/replace.dts similarity index 100% rename from tools/binman/test/132_replace.dts rename to tools/binman/test/entry/replace.dts diff --git a/tools/binman/test/143_replace_all.dts b/tools/binman/test/entry/replace_all.dts similarity index 100% rename from tools/binman/test/143_replace_all.dts rename to tools/binman/test/entry/replace_all.dts diff --git a/tools/binman/test/133_replace_multi.dts b/tools/binman/test/entry/replace_multi.dts similarity index 100% rename from tools/binman/test/133_replace_multi.dts rename to tools/binman/test/entry/replace_multi.dts diff --git a/tools/binman/test/139_replace_repack.dts b/tools/binman/test/entry/replace_repack.dts similarity index 100% rename from tools/binman/test/139_replace_repack.dts rename to tools/binman/test/entry/replace_repack.dts diff --git a/tools/binman/test/278_replace_section_deep.dts b/tools/binman/test/entry/replace_section_deep.dts similarity index 100% rename from tools/binman/test/278_replace_section_deep.dts rename to tools/binman/test/entry/replace_section_deep.dts diff --git a/tools/binman/test/241_replace_section_simple.dts b/tools/binman/test/entry/replace_section_simple.dts similarity index 100% rename from tools/binman/test/241_replace_section_simple.dts rename to tools/binman/test/entry/replace_section_simple.dts diff --git a/tools/binman/test/239_replace_with_bintool.dts b/tools/binman/test/entry/replace_with_bintool.dts similarity index 100% rename from tools/binman/test/239_replace_with_bintool.dts rename to tools/binman/test/entry/replace_with_bintool.dts diff --git a/tools/binman/test/261_section_fname.dts b/tools/binman/test/entry/section_fname.dts similarity index 100% rename from tools/binman/test/261_section_fname.dts rename to tools/binman/test/entry/section_fname.dts diff --git a/tools/binman/test/202_section_timeout.dts b/tools/binman/test/entry/section_timeout.dts similarity index 100% rename from tools/binman/test/202_section_timeout.dts rename to tools/binman/test/entry/section_timeout.dts diff --git a/tools/binman/test/055_sections.dts b/tools/binman/test/entry/sections.dts similarity index 100% rename from tools/binman/test/055_sections.dts rename to tools/binman/test/entry/sections.dts diff --git a/tools/binman/test/259_symlink.dts b/tools/binman/test/entry/symlink.dts similarity index 100% rename from tools/binman/test/259_symlink.dts rename to tools/binman/test/entry/symlink.dts diff --git a/tools/binman/test/222_tee_os.dts b/tools/binman/test/entry/tee_os.dts similarity index 100% rename from tools/binman/test/222_tee_os.dts rename to tools/binman/test/entry/tee_os.dts diff --git a/tools/binman/test/263_tee_os_opt.dts b/tools/binman/test/entry/tee_os_opt.dts similarity index 100% rename from tools/binman/test/263_tee_os_opt.dts rename to tools/binman/test/entry/tee_os_opt.dts diff --git a/tools/binman/test/286_template.dts b/tools/binman/test/entry/template.dts similarity index 100% rename from tools/binman/test/286_template.dts rename to tools/binman/test/entry/template.dts diff --git a/tools/binman/test/287_template_multi.dts b/tools/binman/test/entry/template_multi.dts similarity index 100% rename from tools/binman/test/287_template_multi.dts rename to tools/binman/test/entry/template_multi.dts diff --git a/tools/binman/test/309_template_phandle.dts b/tools/binman/test/entry/template_phandle.dts similarity index 100% rename from tools/binman/test/309_template_phandle.dts rename to tools/binman/test/entry/template_phandle.dts diff --git a/tools/binman/test/310_template_phandle_dup.dts b/tools/binman/test/entry/template_phandle_dup.dts similarity index 100% rename from tools/binman/test/310_template_phandle_dup.dts rename to tools/binman/test/entry/template_phandle_dup.dts diff --git a/tools/binman/test/289_template_section.dts b/tools/binman/test/entry/template_section.dts similarity index 100% rename from tools/binman/test/289_template_section.dts rename to tools/binman/test/entry/template_section.dts diff --git a/tools/binman/test/066_text.dts b/tools/binman/test/entry/text.dts similarity index 100% rename from tools/binman/test/066_text.dts rename to tools/binman/test/entry/text.dts diff --git a/tools/binman/test/237_unique_names.dts b/tools/binman/test/entry/unique_names.dts similarity index 100% rename from tools/binman/test/237_unique_names.dts rename to tools/binman/test/entry/unique_names.dts diff --git a/tools/binman/test/238_unique_names_multi.dts b/tools/binman/test/entry/unique_names_multi.dts similarity index 100% rename from tools/binman/test/238_unique_names_multi.dts rename to tools/binman/test/entry/unique_names_multi.dts diff --git a/tools/binman/test/057_unknown_contents.dts b/tools/binman/test/entry/unknown_contents.dts similarity index 100% rename from tools/binman/test/057_unknown_contents.dts rename to tools/binman/test/entry/unknown_contents.dts diff --git a/tools/binman/test/041_unknown_pos_size.dts b/tools/binman/test/entry/unknown_pos_size.dts similarity index 100% rename from tools/binman/test/041_unknown_pos_size.dts rename to tools/binman/test/entry/unknown_pos_size.dts diff --git a/tools/binman/test/328_alternates_fdt.dts b/tools/binman/test/fdt/alternates_fdt.dts similarity index 100% rename from tools/binman/test/328_alternates_fdt.dts rename to tools/binman/test/fdt/alternates_fdt.dts diff --git a/tools/binman/test/329_alternates_fdtgrep.dts b/tools/binman/test/fdt/alternates_fdtgrep.dts similarity index 100% rename from tools/binman/test/329_alternates_fdtgrep.dts rename to tools/binman/test/fdt/alternates_fdtgrep.dts diff --git a/tools/binman/test/332_alternates_inval.dts b/tools/binman/test/fdt/alternates_inval.dts similarity index 100% rename from tools/binman/test/332_alternates_inval.dts rename to tools/binman/test/fdt/alternates_inval.dts diff --git a/tools/binman/test/331_alternates_spl.dts b/tools/binman/test/fdt/alternates_spl.dts similarity index 100% rename from tools/binman/test/331_alternates_spl.dts rename to tools/binman/test/fdt/alternates_spl.dts diff --git a/tools/binman/test/330_alternates_vpl.dts b/tools/binman/test/fdt/alternates_vpl.dts similarity index 100% rename from tools/binman/test/330_alternates_vpl.dts rename to tools/binman/test/fdt/alternates_vpl.dts diff --git a/tools/binman/test/347_bootph_prop.dts b/tools/binman/test/fdt/bootph_prop.dts similarity index 100% rename from tools/binman/test/347_bootph_prop.dts rename to tools/binman/test/fdt/bootph_prop.dts diff --git a/tools/binman/test/124_compress_dtb.dts b/tools/binman/test/fdt/compress_dtb.dts similarity index 100% rename from tools/binman/test/124_compress_dtb.dts rename to tools/binman/test/fdt/compress_dtb.dts diff --git a/tools/binman/test/250_compress_dtb_invalid.dts b/tools/binman/test/fdt/compress_dtb_invalid.dts similarity index 100% rename from tools/binman/test/250_compress_dtb_invalid.dts rename to tools/binman/test/fdt/compress_dtb_invalid.dts diff --git a/tools/binman/test/248_compress_dtb_prepend_invalid.dts b/tools/binman/test/fdt/compress_dtb_prepend_invalid.dts similarity index 100% rename from tools/binman/test/248_compress_dtb_prepend_invalid.dts rename to tools/binman/test/fdt/compress_dtb_prepend_invalid.dts diff --git a/tools/binman/test/249_compress_dtb_prepend_length.dts b/tools/binman/test/fdt/compress_dtb_prepend_length.dts similarity index 100% rename from tools/binman/test/249_compress_dtb_prepend_length.dts rename to tools/binman/test/fdt/compress_dtb_prepend_length.dts diff --git a/tools/binman/test/251_compress_dtb_zstd.dts b/tools/binman/test/fdt/compress_dtb_zstd.dts similarity index 100% rename from tools/binman/test/251_compress_dtb_zstd.dts rename to tools/binman/test/fdt/compress_dtb_zstd.dts diff --git a/tools/binman/test/128_decode_image.dts b/tools/binman/test/fdt/decode_image.dts similarity index 100% rename from tools/binman/test/128_decode_image.dts rename to tools/binman/test/fdt/decode_image.dts diff --git a/tools/binman/test/129_decode_image_nohdr.dts b/tools/binman/test/fdt/decode_image_nohdr.dts similarity index 100% rename from tools/binman/test/129_decode_image_nohdr.dts rename to tools/binman/test/fdt/decode_image_nohdr.dts diff --git a/tools/binman/test/115_fdtmap.dts b/tools/binman/test/fdt/fdtmap.dts similarity index 100% rename from tools/binman/test/115_fdtmap.dts rename to tools/binman/test/fdt/fdtmap.dts diff --git a/tools/binman/test/213_fdtmap_alt_format.dts b/tools/binman/test/fdt/fdtmap_alt_format.dts similarity index 100% rename from tools/binman/test/213_fdtmap_alt_format.dts rename to tools/binman/test/fdt/fdtmap_alt_format.dts diff --git a/tools/binman/test/116_fdtmap_hdr.dts b/tools/binman/test/fdt/fdtmap_hdr.dts similarity index 100% rename from tools/binman/test/116_fdtmap_hdr.dts rename to tools/binman/test/fdt/fdtmap_hdr.dts diff --git a/tools/binman/test/137_fdtmap_hdr_endbad.dts b/tools/binman/test/fdt/fdtmap_hdr_endbad.dts similarity index 100% rename from tools/binman/test/137_fdtmap_hdr_endbad.dts rename to tools/binman/test/fdt/fdtmap_hdr_endbad.dts diff --git a/tools/binman/test/135_fdtmap_hdr_middle.dts b/tools/binman/test/fdt/fdtmap_hdr_middle.dts similarity index 100% rename from tools/binman/test/135_fdtmap_hdr_middle.dts rename to tools/binman/test/fdt/fdtmap_hdr_middle.dts diff --git a/tools/binman/test/119_fdtmap_hdr_missing.dts b/tools/binman/test/fdt/fdtmap_hdr_missing.dts similarity index 100% rename from tools/binman/test/119_fdtmap_hdr_missing.dts rename to tools/binman/test/fdt/fdtmap_hdr_missing.dts diff --git a/tools/binman/test/138_fdtmap_hdr_nosize.dts b/tools/binman/test/fdt/fdtmap_hdr_nosize.dts similarity index 100% rename from tools/binman/test/138_fdtmap_hdr_nosize.dts rename to tools/binman/test/fdt/fdtmap_hdr_nosize.dts diff --git a/tools/binman/test/118_fdtmap_hdr_pos.dts b/tools/binman/test/fdt/fdtmap_hdr_pos.dts similarity index 100% rename from tools/binman/test/118_fdtmap_hdr_pos.dts rename to tools/binman/test/fdt/fdtmap_hdr_pos.dts diff --git a/tools/binman/test/117_fdtmap_hdr_start.dts b/tools/binman/test/fdt/fdtmap_hdr_start.dts similarity index 100% rename from tools/binman/test/117_fdtmap_hdr_start.dts rename to tools/binman/test/fdt/fdtmap_hdr_start.dts diff --git a/tools/binman/test/136_fdtmap_hdr_startbad.dts b/tools/binman/test/fdt/fdtmap_hdr_startbad.dts similarity index 100% rename from tools/binman/test/136_fdtmap_hdr_startbad.dts rename to tools/binman/test/fdt/fdtmap_hdr_startbad.dts diff --git a/tools/binman/test/120_hdr_no_location.dts b/tools/binman/test/fdt/hdr_no_location.dts similarity index 100% rename from tools/binman/test/120_hdr_no_location.dts rename to tools/binman/test/fdt/hdr_no_location.dts diff --git a/tools/binman/test/194_fdt_incl.dts b/tools/binman/test/fdt/incl.dts similarity index 100% rename from tools/binman/test/194_fdt_incl.dts rename to tools/binman/test/fdt/incl.dts diff --git a/tools/binman/test/195_fdt_incl_tpl.dts b/tools/binman/test/fdt/incl_tpl.dts similarity index 100% rename from tools/binman/test/195_fdt_incl_tpl.dts rename to tools/binman/test/fdt/incl_tpl.dts diff --git a/tools/binman/test/257_fdt_incl_vpl.dts b/tools/binman/test/fdt/incl_vpl.dts similarity index 100% rename from tools/binman/test/257_fdt_incl_vpl.dts rename to tools/binman/test/fdt/incl_vpl.dts diff --git a/tools/binman/test/130_list_fdtmap.dts b/tools/binman/test/fdt/list_fdtmap.dts similarity index 100% rename from tools/binman/test/130_list_fdtmap.dts rename to tools/binman/test/fdt/list_fdtmap.dts diff --git a/tools/binman/test/060_fdt_update.dts b/tools/binman/test/fdt/update.dts similarity index 100% rename from tools/binman/test/060_fdt_update.dts rename to tools/binman/test/fdt/update.dts diff --git a/tools/binman/test/082_fdt_update_all.dts b/tools/binman/test/fdt/update_all.dts similarity index 100% rename from tools/binman/test/082_fdt_update_all.dts rename to tools/binman/test/fdt/update_all.dts diff --git a/tools/binman/test/134_fdt_update_all_repack.dts b/tools/binman/test/fdt/update_all_repack.dts similarity index 100% rename from tools/binman/test/134_fdt_update_all_repack.dts rename to tools/binman/test/fdt/update_all_repack.dts diff --git a/tools/binman/test/061_fdt_update_bad.dts b/tools/binman/test/fdt/update_bad.dts similarity index 100% rename from tools/binman/test/061_fdt_update_bad.dts rename to tools/binman/test/fdt/update_bad.dts diff --git a/tools/binman/test/169_atf_bl31.dts b/tools/binman/test/fip/atf_bl31.dts similarity index 100% rename from tools/binman/test/169_atf_bl31.dts rename to tools/binman/test/fip/atf_bl31.dts diff --git a/tools/binman/test/211_fip_bad_align.dts b/tools/binman/test/fip/bad_align.dts similarity index 100% rename from tools/binman/test/211_fip_bad_align.dts rename to tools/binman/test/fip/bad_align.dts diff --git a/tools/binman/test/347_bl1.dts b/tools/binman/test/fip/bl1.dts similarity index 100% rename from tools/binman/test/347_bl1.dts rename to tools/binman/test/fip/bl1.dts diff --git a/tools/binman/test/212_fip_collection.dts b/tools/binman/test/fip/collection.dts similarity index 100% rename from tools/binman/test/212_fip_collection.dts rename to tools/binman/test/fip/collection.dts diff --git a/tools/binman/test/203_fip.dts b/tools/binman/test/fip/fip.dts similarity index 100% rename from tools/binman/test/203_fip.dts rename to tools/binman/test/fip/fip.dts diff --git a/tools/binman/test/207_fip_ls.dts b/tools/binman/test/fip/ls.dts similarity index 100% rename from tools/binman/test/207_fip_ls.dts rename to tools/binman/test/fip/ls.dts diff --git a/tools/binman/test/209_fip_missing.dts b/tools/binman/test/fip/missing.dts similarity index 100% rename from tools/binman/test/209_fip_missing.dts rename to tools/binman/test/fip/missing.dts diff --git a/tools/binman/test/205_fip_no_type.dts b/tools/binman/test/fip/no_type.dts similarity index 100% rename from tools/binman/test/205_fip_no_type.dts rename to tools/binman/test/fip/no_type.dts diff --git a/tools/binman/test/201_opensbi.dts b/tools/binman/test/fip/opensbi.dts similarity index 100% rename from tools/binman/test/201_opensbi.dts rename to tools/binman/test/fip/opensbi.dts diff --git a/tools/binman/test/204_fip_other.dts b/tools/binman/test/fip/other.dts similarity index 100% rename from tools/binman/test/204_fip_other.dts rename to tools/binman/test/fip/other.dts diff --git a/tools/binman/test/208_fip_replace.dts b/tools/binman/test/fip/replace.dts similarity index 100% rename from tools/binman/test/208_fip_replace.dts rename to tools/binman/test/fip/replace.dts diff --git a/tools/binman/test/172_scp.dts b/tools/binman/test/fip/scp.dts similarity index 100% rename from tools/binman/test/172_scp.dts rename to tools/binman/test/fip/scp.dts diff --git a/tools/binman/test/210_fip_size.dts b/tools/binman/test/fip/size.dts similarity index 100% rename from tools/binman/test/210_fip_size.dts rename to tools/binman/test/fip/size.dts diff --git a/tools/binman/test/206_fip_uuid.dts b/tools/binman/test/fip/uuid.dts similarity index 100% rename from tools/binman/test/206_fip_uuid.dts rename to tools/binman/test/fip/uuid.dts diff --git a/tools/binman/test/aes256.bin b/tools/binman/test/fit/aes256.bin similarity index 100% rename from tools/binman/test/aes256.bin rename to tools/binman/test/fit/aes256.bin diff --git a/tools/binman/test/275_fit_align.dts b/tools/binman/test/fit/align.dts similarity index 100% rename from tools/binman/test/275_fit_align.dts rename to tools/binman/test/fit/align.dts diff --git a/tools/binman/test/227_fit_bad_dir.dts b/tools/binman/test/fit/bad_dir.dts similarity index 71% rename from tools/binman/test/227_fit_bad_dir.dts rename to tools/binman/test/fit/bad_dir.dts index 51f4816c4c2..c6d5c7b0a87 100644 --- a/tools/binman/test/227_fit_bad_dir.dts +++ b/tools/binman/test/fit/bad_dir.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "226_fit_split_elf.dts" +#include "split_elf.dts" &atf { fit,something = "bad"; diff --git a/tools/binman/test/228_fit_bad_dir_config.dts b/tools/binman/test/fit/bad_dir_config.dts similarity index 71% rename from tools/binman/test/228_fit_bad_dir_config.dts rename to tools/binman/test/fit/bad_dir_config.dts index 825a346c3e6..bae805a9523 100644 --- a/tools/binman/test/228_fit_bad_dir_config.dts +++ b/tools/binman/test/fit/bad_dir_config.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "226_fit_split_elf.dts" +#include "split_elf.dts" &config { fit,config = "bad"; diff --git a/tools/binman/test/224_fit_bad_oper.dts b/tools/binman/test/fit/bad_oper.dts similarity index 100% rename from tools/binman/test/224_fit_bad_oper.dts rename to tools/binman/test/fit/bad_oper.dts diff --git a/tools/binman/test/dummy-rsa-engine.c b/tools/binman/test/fit/dummy-rsa-engine.c similarity index 100% rename from tools/binman/test/dummy-rsa-engine.c rename to tools/binman/test/fit/dummy-rsa-engine.c diff --git a/tools/binman/test/340_dummy-rsa4096.crt b/tools/binman/test/fit/dummy-rsa4096.crt similarity index 100% rename from tools/binman/test/340_dummy-rsa4096.crt rename to tools/binman/test/fit/dummy-rsa4096.crt diff --git a/tools/binman/test/343_fit_encrypt_data.dts b/tools/binman/test/fit/encrypt_data.dts similarity index 100% rename from tools/binman/test/343_fit_encrypt_data.dts rename to tools/binman/test/fit/encrypt_data.dts diff --git a/tools/binman/test/344_fit_encrypt_data_no_key.dts b/tools/binman/test/fit/encrypt_data_no_key.dts similarity index 100% rename from tools/binman/test/344_fit_encrypt_data_no_key.dts rename to tools/binman/test/fit/encrypt_data_no_key.dts diff --git a/tools/binman/test/162_fit_external.dts b/tools/binman/test/fit/external.dts similarity index 100% rename from tools/binman/test/162_fit_external.dts rename to tools/binman/test/fit/external.dts diff --git a/tools/binman/test/240_fit_extract_replace.dts b/tools/binman/test/fit/extract_replace.dts similarity index 100% rename from tools/binman/test/240_fit_extract_replace.dts rename to tools/binman/test/fit/extract_replace.dts diff --git a/tools/binman/test/170_fit_fdt.dts b/tools/binman/test/fit/fdt.dts similarity index 100% rename from tools/binman/test/170_fit_fdt.dts rename to tools/binman/test/fit/fdt.dts diff --git a/tools/binman/test/334_fit_fdt_compat.dts b/tools/binman/test/fit/fdt_compat.dts similarity index 100% rename from tools/binman/test/334_fit_fdt_compat.dts rename to tools/binman/test/fit/fdt_compat.dts diff --git a/tools/binman/test/333_fit_fdt_dir.dts b/tools/binman/test/fit/fdt_dir.dts similarity index 100% rename from tools/binman/test/333_fit_fdt_dir.dts rename to tools/binman/test/fit/fdt_dir.dts diff --git a/tools/binman/test/284_fit_fdt_list.dts b/tools/binman/test/fit/fdt_list.dts similarity index 100% rename from tools/binman/test/284_fit_fdt_list.dts rename to tools/binman/test/fit/fdt_list.dts diff --git a/tools/binman/test/171_fit_fdt_missing_prop.dts b/tools/binman/test/fit/fdt_missing_prop.dts similarity index 100% rename from tools/binman/test/171_fit_fdt_missing_prop.dts rename to tools/binman/test/fit/fdt_missing_prop.dts diff --git a/tools/binman/test/345_fit_fdt_name.dts b/tools/binman/test/fit/fdt_name.dts similarity index 100% rename from tools/binman/test/345_fit_fdt_name.dts rename to tools/binman/test/fit/fdt_name.dts diff --git a/tools/binman/test/223_fit_fdt_oper.dts b/tools/binman/test/fit/fdt_oper.dts similarity index 100% rename from tools/binman/test/223_fit_fdt_oper.dts rename to tools/binman/test/fit/fdt_oper.dts diff --git a/tools/binman/test/335_fit_fdt_phase.dts b/tools/binman/test/fit/fdt_phase.dts similarity index 100% rename from tools/binman/test/335_fit_fdt_phase.dts rename to tools/binman/test/fit/fdt_phase.dts diff --git a/tools/binman/test/276_fit_firmware_loadables.dts b/tools/binman/test/fit/firmware_loadables.dts similarity index 100% rename from tools/binman/test/276_fit_firmware_loadables.dts rename to tools/binman/test/fit/firmware_loadables.dts diff --git a/tools/binman/test/161_fit.dts b/tools/binman/test/fit/fit.dts similarity index 100% rename from tools/binman/test/161_fit.dts rename to tools/binman/test/fit/fit.dts diff --git a/tools/binman/test/219_fit_gennode.dts b/tools/binman/test/fit/gennode.dts similarity index 100% rename from tools/binman/test/219_fit_gennode.dts rename to tools/binman/test/fit/gennode.dts diff --git a/tools/binman/test/167_fit_image_subentry_alignment.dts b/tools/binman/test/fit/image_subentry_alignment.dts similarity index 100% rename from tools/binman/test/167_fit_image_subentry_alignment.dts rename to tools/binman/test/fit/image_subentry_alignment.dts diff --git a/tools/binman/test/347_key_name_hint_dir_fit_signature.dts b/tools/binman/test/fit/key_name_hint_dir_signature.dts similarity index 100% rename from tools/binman/test/347_key_name_hint_dir_fit_signature.dts rename to tools/binman/test/fit/key_name_hint_dir_signature.dts diff --git a/tools/binman/test/168_fit_missing_blob.dts b/tools/binman/test/fit/missing_blob.dts similarity index 100% rename from tools/binman/test/168_fit_missing_blob.dts rename to tools/binman/test/fit/missing_blob.dts diff --git a/tools/binman/test/340_openssl.conf b/tools/binman/test/fit/openssl.conf similarity index 100% rename from tools/binman/test/340_openssl.conf rename to tools/binman/test/fit/openssl.conf diff --git a/tools/binman/test/277_replace_fit_sibling.dts b/tools/binman/test/fit/replace_sibling.dts similarity index 100% rename from tools/binman/test/277_replace_fit_sibling.dts rename to tools/binman/test/fit/replace_sibling.dts diff --git a/tools/binman/test/340_rsa2048.key b/tools/binman/test/fit/rsa2048.key similarity index 100% rename from tools/binman/test/340_rsa2048.key rename to tools/binman/test/fit/rsa2048.key diff --git a/tools/binman/test/280_fit_sign.dts b/tools/binman/test/fit/sign.dts similarity index 100% rename from tools/binman/test/280_fit_sign.dts rename to tools/binman/test/fit/sign.dts diff --git a/tools/binman/test/340_fit_signature.dts b/tools/binman/test/fit/signature.dts similarity index 100% rename from tools/binman/test/340_fit_signature.dts rename to tools/binman/test/fit/signature.dts diff --git a/tools/binman/test/340_fit_signature_engine.dts b/tools/binman/test/fit/signature_engine.dts similarity index 100% rename from tools/binman/test/340_fit_signature_engine.dts rename to tools/binman/test/fit/signature_engine.dts diff --git a/tools/binman/test/340_fit_signature_engine_encrypt.dts b/tools/binman/test/fit/signature_engine_encrypt.dts similarity index 100% rename from tools/binman/test/340_fit_signature_engine_encrypt.dts rename to tools/binman/test/fit/signature_engine_encrypt.dts diff --git a/tools/binman/test/340_fit_signature_engine_pkcs11.dts b/tools/binman/test/fit/signature_engine_pkcs11.dts similarity index 100% rename from tools/binman/test/340_fit_signature_engine_pkcs11.dts rename to tools/binman/test/fit/signature_engine_pkcs11.dts diff --git a/tools/binman/test/340_fit_signature_engine_pkcs11_object.dts b/tools/binman/test/fit/signature_engine_pkcs11_object.dts similarity index 100% rename from tools/binman/test/340_fit_signature_engine_pkcs11_object.dts rename to tools/binman/test/fit/signature_engine_pkcs11_object.dts diff --git a/tools/binman/test/341_fit_signature.dts b/tools/binman/test/fit/signature_multi_key.dts similarity index 100% rename from tools/binman/test/341_fit_signature.dts rename to tools/binman/test/fit/signature_multi_key.dts diff --git a/tools/binman/test/342_fit_signature.dts b/tools/binman/test/fit/signature_no_nodes.dts similarity index 100% rename from tools/binman/test/342_fit_signature.dts rename to tools/binman/test/fit/signature_no_nodes.dts diff --git a/tools/binman/test/340_softhsm2.conf b/tools/binman/test/fit/softhsm2.conf similarity index 100% rename from tools/binman/test/340_softhsm2.conf rename to tools/binman/test/fit/softhsm2.conf diff --git a/tools/binman/test/226_fit_split_elf.dts b/tools/binman/test/fit/split_elf.dts similarity index 100% rename from tools/binman/test/226_fit_split_elf.dts rename to tools/binman/test/fit/split_elf.dts diff --git a/tools/binman/test/220_fit_subentry_bintool.dts b/tools/binman/test/fit/subentry_bintool.dts similarity index 100% rename from tools/binman/test/220_fit_subentry_bintool.dts rename to tools/binman/test/fit/subentry_bintool.dts diff --git a/tools/binman/test/221_fit_subentry_hash.dts b/tools/binman/test/fit/subentry_hash.dts similarity index 100% rename from tools/binman/test/221_fit_subentry_hash.dts rename to tools/binman/test/fit/subentry_hash.dts diff --git a/tools/binman/test/264_tee_os_opt_fit.dts b/tools/binman/test/fit/tee_os_opt.dts similarity index 100% rename from tools/binman/test/264_tee_os_opt_fit.dts rename to tools/binman/test/fit/tee_os_opt.dts diff --git a/tools/binman/test/265_tee_os_opt_fit_bad.dts b/tools/binman/test/fit/tee_os_opt_bad.dts similarity index 100% rename from tools/binman/test/265_tee_os_opt_fit_bad.dts rename to tools/binman/test/fit/tee_os_opt_bad.dts diff --git a/tools/binman/test/288_template_fit.dts b/tools/binman/test/fit/template.dts similarity index 100% rename from tools/binman/test/288_template_fit.dts rename to tools/binman/test/fit/template.dts diff --git a/tools/binman/test/247_mkimage_coll.dts b/tools/binman/test/mkimage/coll.dts similarity index 100% rename from tools/binman/test/247_mkimage_coll.dts rename to tools/binman/test/mkimage/coll.dts diff --git a/tools/binman/test/254_mkimage_filename.dts b/tools/binman/test/mkimage/filename.dts similarity index 100% rename from tools/binman/test/254_mkimage_filename.dts rename to tools/binman/test/mkimage/filename.dts diff --git a/tools/binman/test/243_mkimage_image.dts b/tools/binman/test/mkimage/image.dts similarity index 100% rename from tools/binman/test/243_mkimage_image.dts rename to tools/binman/test/mkimage/image.dts diff --git a/tools/binman/test/245_mkimage_image_bad.dts b/tools/binman/test/mkimage/image_bad.dts similarity index 100% rename from tools/binman/test/245_mkimage_image_bad.dts rename to tools/binman/test/mkimage/image_bad.dts diff --git a/tools/binman/test/244_mkimage_image_no_content.dts b/tools/binman/test/mkimage/image_no_content.dts similarity index 100% rename from tools/binman/test/244_mkimage_image_no_content.dts rename to tools/binman/test/mkimage/image_no_content.dts diff --git a/tools/binman/test/229_mkimage_missing.dts b/tools/binman/test/mkimage/missing.dts similarity index 100% rename from tools/binman/test/229_mkimage_missing.dts rename to tools/binman/test/mkimage/missing.dts diff --git a/tools/binman/test/292_mkimage_missing_multiple.dts b/tools/binman/test/mkimage/missing_multiple.dts similarity index 100% rename from tools/binman/test/292_mkimage_missing_multiple.dts rename to tools/binman/test/mkimage/missing_multiple.dts diff --git a/tools/binman/test/156_mkimage.dts b/tools/binman/test/mkimage/mkimage.dts similarity index 100% rename from tools/binman/test/156_mkimage.dts rename to tools/binman/test/mkimage/mkimage.dts diff --git a/tools/binman/test/252_mkimage_mult_data.dts b/tools/binman/test/mkimage/mult_data.dts similarity index 100% rename from tools/binman/test/252_mkimage_mult_data.dts rename to tools/binman/test/mkimage/mult_data.dts diff --git a/tools/binman/test/253_mkimage_mult_no_content.dts b/tools/binman/test/mkimage/mult_no_content.dts similarity index 100% rename from tools/binman/test/253_mkimage_mult_no_content.dts rename to tools/binman/test/mkimage/mult_no_content.dts diff --git a/tools/binman/test/242_mkimage_name.dts b/tools/binman/test/mkimage/name.dts similarity index 100% rename from tools/binman/test/242_mkimage_name.dts rename to tools/binman/test/mkimage/name.dts diff --git a/tools/binman/test/283_mkimage_special.dts b/tools/binman/test/mkimage/special.dts similarity index 100% rename from tools/binman/test/283_mkimage_special.dts rename to tools/binman/test/mkimage/special.dts diff --git a/tools/binman/test/290_mkimage_sym.dts b/tools/binman/test/mkimage/sym.dts similarity index 100% rename from tools/binman/test/290_mkimage_sym.dts rename to tools/binman/test/mkimage/sym.dts diff --git a/tools/binman/test/098_4gb_and_skip_at_start_together.dts b/tools/binman/test/pack/4gb_and_skip_at_start_together.dts similarity index 100% rename from tools/binman/test/098_4gb_and_skip_at_start_together.dts rename to tools/binman/test/pack/4gb_and_skip_at_start_together.dts diff --git a/tools/binman/test/200_align_default.dts b/tools/binman/test/pack/align_default.dts similarity index 100% rename from tools/binman/test/200_align_default.dts rename to tools/binman/test/pack/align_default.dts diff --git a/tools/binman/test/326_assume_size.dts b/tools/binman/test/pack/assume_size.dts similarity index 100% rename from tools/binman/test/326_assume_size.dts rename to tools/binman/test/pack/assume_size.dts diff --git a/tools/binman/test/327_assume_size_ok.dts b/tools/binman/test/pack/assume_size_ok.dts similarity index 100% rename from tools/binman/test/327_assume_size_ok.dts rename to tools/binman/test/pack/assume_size_ok.dts diff --git a/tools/binman/test/007_bad_align.dts b/tools/binman/test/pack/bad_align.dts similarity index 100% rename from tools/binman/test/007_bad_align.dts rename to tools/binman/test/pack/bad_align.dts diff --git a/tools/binman/test/059_change_size.dts b/tools/binman/test/pack/change_size.dts similarity index 100% rename from tools/binman/test/059_change_size.dts rename to tools/binman/test/pack/change_size.dts diff --git a/tools/binman/test/006_dual_image.dts b/tools/binman/test/pack/dual_image.dts similarity index 100% rename from tools/binman/test/006_dual_image.dts rename to tools/binman/test/pack/dual_image.dts diff --git a/tools/binman/test/003_empty.dts b/tools/binman/test/pack/empty.dts similarity index 100% rename from tools/binman/test/003_empty.dts rename to tools/binman/test/pack/empty.dts diff --git a/tools/binman/test/121_entry_extend.dts b/tools/binman/test/pack/entry_extend.dts similarity index 100% rename from tools/binman/test/121_entry_extend.dts rename to tools/binman/test/pack/entry_extend.dts diff --git a/tools/binman/test/123_entry_extend_section.dts b/tools/binman/test/pack/entry_extend_section.dts similarity index 100% rename from tools/binman/test/123_entry_extend_section.dts rename to tools/binman/test/pack/entry_extend_section.dts diff --git a/tools/binman/test/122_entry_extend_twice.dts b/tools/binman/test/pack/entry_extend_twice.dts similarity index 100% rename from tools/binman/test/122_entry_extend_twice.dts rename to tools/binman/test/pack/entry_extend_twice.dts diff --git a/tools/binman/test/140_entry_shrink.dts b/tools/binman/test/pack/entry_shrink.dts similarity index 100% rename from tools/binman/test/140_entry_shrink.dts rename to tools/binman/test/pack/entry_shrink.dts diff --git a/tools/binman/test/225_expand_size_bad.dts b/tools/binman/test/pack/expand_size_bad.dts similarity index 100% rename from tools/binman/test/225_expand_size_bad.dts rename to tools/binman/test/pack/expand_size_bad.dts diff --git a/tools/binman/test/088_extend_size.dts b/tools/binman/test/pack/extend_size.dts similarity index 100% rename from tools/binman/test/088_extend_size.dts rename to tools/binman/test/pack/extend_size.dts diff --git a/tools/binman/test/089_extend_size_bad.dts b/tools/binman/test/pack/extend_size_bad.dts similarity index 100% rename from tools/binman/test/089_extend_size_bad.dts rename to tools/binman/test/pack/extend_size_bad.dts diff --git a/tools/binman/test/022_image_name.dts b/tools/binman/test/pack/image_name.dts similarity index 100% rename from tools/binman/test/022_image_name.dts rename to tools/binman/test/pack/image_name.dts diff --git a/tools/binman/test/021_image_pad.dts b/tools/binman/test/pack/image_pad.dts similarity index 100% rename from tools/binman/test/021_image_pad.dts rename to tools/binman/test/pack/image_pad.dts diff --git a/tools/binman/test/001_invalid.dts b/tools/binman/test/pack/invalid.dts similarity index 100% rename from tools/binman/test/001_invalid.dts rename to tools/binman/test/pack/invalid.dts diff --git a/tools/binman/test/004_invalid_entry.dts b/tools/binman/test/pack/invalid_entry.dts similarity index 100% rename from tools/binman/test/004_invalid_entry.dts rename to tools/binman/test/pack/invalid_entry.dts diff --git a/tools/binman/test/002_missing_node.dts b/tools/binman/test/pack/missing_node.dts similarity index 100% rename from tools/binman/test/002_missing_node.dts rename to tools/binman/test/pack/missing_node.dts diff --git a/tools/binman/test/008_pack.dts b/tools/binman/test/pack/pack.dts similarity index 100% rename from tools/binman/test/008_pack.dts rename to tools/binman/test/pack/pack.dts diff --git a/tools/binman/test/027_pack_4gb_no_size.dts b/tools/binman/test/pack/pack_4gb_no_size.dts similarity index 100% rename from tools/binman/test/027_pack_4gb_no_size.dts rename to tools/binman/test/pack/pack_4gb_no_size.dts diff --git a/tools/binman/test/028_pack_4gb_outside.dts b/tools/binman/test/pack/pack_4gb_outside.dts similarity index 100% rename from tools/binman/test/028_pack_4gb_outside.dts rename to tools/binman/test/pack/pack_4gb_outside.dts diff --git a/tools/binman/test/010_pack_align_power2.dts b/tools/binman/test/pack/pack_align_power2.dts similarity index 100% rename from tools/binman/test/010_pack_align_power2.dts rename to tools/binman/test/pack/pack_align_power2.dts diff --git a/tools/binman/test/131_pack_align_section.dts b/tools/binman/test/pack/pack_align_section.dts similarity index 100% rename from tools/binman/test/131_pack_align_section.dts rename to tools/binman/test/pack/pack_align_section.dts diff --git a/tools/binman/test/011_pack_align_size_power2.dts b/tools/binman/test/pack/pack_align_size_power2.dts similarity index 100% rename from tools/binman/test/011_pack_align_size_power2.dts rename to tools/binman/test/pack/pack_align_size_power2.dts diff --git a/tools/binman/test/009_pack_extra.dts b/tools/binman/test/pack/pack_extra.dts similarity index 100% rename from tools/binman/test/009_pack_extra.dts rename to tools/binman/test/pack/pack_extra.dts diff --git a/tools/binman/test/018_pack_image_align.dts b/tools/binman/test/pack/pack_image_align.dts similarity index 100% rename from tools/binman/test/018_pack_image_align.dts rename to tools/binman/test/pack/pack_image_align.dts diff --git a/tools/binman/test/016_pack_image_overflow.dts b/tools/binman/test/pack/pack_image_overflow.dts similarity index 100% rename from tools/binman/test/016_pack_image_overflow.dts rename to tools/binman/test/pack/pack_image_overflow.dts diff --git a/tools/binman/test/017_pack_image_size.dts b/tools/binman/test/pack/pack_image_size.dts similarity index 100% rename from tools/binman/test/017_pack_image_size.dts rename to tools/binman/test/pack/pack_image_size.dts diff --git a/tools/binman/test/012_pack_inv_align.dts b/tools/binman/test/pack/pack_inv_align.dts similarity index 100% rename from tools/binman/test/012_pack_inv_align.dts rename to tools/binman/test/pack/pack_inv_align.dts diff --git a/tools/binman/test/019_pack_inv_image_align.dts b/tools/binman/test/pack/pack_inv_image_align.dts similarity index 100% rename from tools/binman/test/019_pack_inv_image_align.dts rename to tools/binman/test/pack/pack_inv_image_align.dts diff --git a/tools/binman/test/020_pack_inv_image_align_power2.dts b/tools/binman/test/pack/pack_inv_image_align_power2.dts similarity index 100% rename from tools/binman/test/020_pack_inv_image_align_power2.dts rename to tools/binman/test/pack/pack_inv_image_align_power2.dts diff --git a/tools/binman/test/013_pack_inv_size_align.dts b/tools/binman/test/pack/pack_inv_size_align.dts similarity index 100% rename from tools/binman/test/013_pack_inv_size_align.dts rename to tools/binman/test/pack/pack_inv_size_align.dts diff --git a/tools/binman/test/015_pack_overflow.dts b/tools/binman/test/pack/pack_overflow.dts similarity index 100% rename from tools/binman/test/015_pack_overflow.dts rename to tools/binman/test/pack/pack_overflow.dts diff --git a/tools/binman/test/014_pack_overlap.dts b/tools/binman/test/pack/pack_overlap.dts similarity index 100% rename from tools/binman/test/014_pack_overlap.dts rename to tools/binman/test/pack/pack_overlap.dts diff --git a/tools/binman/test/160_pack_overlap_zero.dts b/tools/binman/test/pack/pack_overlap_zero.dts similarity index 100% rename from tools/binman/test/160_pack_overlap_zero.dts rename to tools/binman/test/pack/pack_overlap_zero.dts diff --git a/tools/binman/test/025_pack_zero_size.dts b/tools/binman/test/pack/pack_zero_size.dts similarity index 100% rename from tools/binman/test/025_pack_zero_size.dts rename to tools/binman/test/pack/pack_zero_size.dts diff --git a/tools/binman/test/166_pad_in_sections.dts b/tools/binman/test/pack/pad_in_sections.dts similarity index 100% rename from tools/binman/test/166_pad_in_sections.dts rename to tools/binman/test/pack/pad_in_sections.dts diff --git a/tools/binman/test/181_section_align.dts b/tools/binman/test/pack/section_align.dts similarity index 100% rename from tools/binman/test/181_section_align.dts rename to tools/binman/test/pack/section_align.dts diff --git a/tools/binman/test/267_section_inner.dts b/tools/binman/test/pack/section_inner.dts similarity index 100% rename from tools/binman/test/267_section_inner.dts rename to tools/binman/test/pack/section_inner.dts diff --git a/tools/binman/test/180_section_pad.dts b/tools/binman/test/pack/section_pad.dts similarity index 100% rename from tools/binman/test/180_section_pad.dts rename to tools/binman/test/pack/section_pad.dts diff --git a/tools/binman/test/101_sections_offset.dts b/tools/binman/test/pack/sections_offset.dts similarity index 100% rename from tools/binman/test/101_sections_offset.dts rename to tools/binman/test/pack/sections_offset.dts diff --git a/tools/binman/test/005_simple.dts b/tools/binman/test/pack/simple.dts similarity index 100% rename from tools/binman/test/005_simple.dts rename to tools/binman/test/pack/simple.dts diff --git a/tools/binman/test/177_skip_at_start.dts b/tools/binman/test/pack/skip_at_start.dts similarity index 100% rename from tools/binman/test/177_skip_at_start.dts rename to tools/binman/test/pack/skip_at_start.dts diff --git a/tools/binman/test/178_skip_at_start_pad.dts b/tools/binman/test/pack/skip_at_start_pad.dts similarity index 100% rename from tools/binman/test/178_skip_at_start_pad.dts rename to tools/binman/test/pack/skip_at_start_pad.dts diff --git a/tools/binman/test/179_skip_at_start_section_pad.dts b/tools/binman/test/pack/skip_at_start_section_pad.dts similarity index 100% rename from tools/binman/test/179_skip_at_start_section_pad.dts rename to tools/binman/test/pack/skip_at_start_section_pad.dts diff --git a/tools/binman/test/024_sorted.dts b/tools/binman/test/pack/sorted.dts similarity index 100% rename from tools/binman/test/024_sorted.dts rename to tools/binman/test/pack/sorted.dts diff --git a/tools/binman/test/054_unit_address.dts b/tools/binman/test/pack/unit_address.dts similarity index 100% rename from tools/binman/test/054_unit_address.dts rename to tools/binman/test/pack/unit_address.dts diff --git a/tools/binman/test/079_uses_pos.dts b/tools/binman/test/pack/uses_pos.dts similarity index 100% rename from tools/binman/test/079_uses_pos.dts rename to tools/binman/test/pack/uses_pos.dts diff --git a/tools/binman/test/302_encrypted_invalid_iv_file.dts b/tools/binman/test/security/encrypted_invalid_iv_file.dts similarity index 100% rename from tools/binman/test/302_encrypted_invalid_iv_file.dts rename to tools/binman/test/security/encrypted_invalid_iv_file.dts diff --git a/tools/binman/test/305_encrypted_key_file.dts b/tools/binman/test/security/encrypted_key_file.dts similarity index 100% rename from tools/binman/test/305_encrypted_key_file.dts rename to tools/binman/test/security/encrypted_key_file.dts diff --git a/tools/binman/test/304_encrypted_key_source.dts b/tools/binman/test/security/encrypted_key_source.dts similarity index 100% rename from tools/binman/test/304_encrypted_key_source.dts rename to tools/binman/test/security/encrypted_key_source.dts diff --git a/tools/binman/test/303_encrypted_missing_key.dts b/tools/binman/test/security/encrypted_missing_key.dts similarity index 100% rename from tools/binman/test/303_encrypted_missing_key.dts rename to tools/binman/test/security/encrypted_missing_key.dts diff --git a/tools/binman/test/301_encrypted_no_algo.dts b/tools/binman/test/security/encrypted_no_algo.dts similarity index 100% rename from tools/binman/test/301_encrypted_no_algo.dts rename to tools/binman/test/security/encrypted_no_algo.dts diff --git a/tools/binman/test/090_hash.dts b/tools/binman/test/security/hash.dts similarity index 100% rename from tools/binman/test/090_hash.dts rename to tools/binman/test/security/hash.dts diff --git a/tools/binman/test/092_hash_bad_algo.dts b/tools/binman/test/security/hash_bad_algo.dts similarity index 100% rename from tools/binman/test/092_hash_bad_algo.dts rename to tools/binman/test/security/hash_bad_algo.dts diff --git a/tools/binman/test/091_hash_no_algo.dts b/tools/binman/test/security/hash_no_algo.dts similarity index 100% rename from tools/binman/test/091_hash_no_algo.dts rename to tools/binman/test/security/hash_no_algo.dts diff --git a/tools/binman/test/099_hash_section.dts b/tools/binman/test/security/hash_section.dts similarity index 100% rename from tools/binman/test/099_hash_section.dts rename to tools/binman/test/security/hash_section.dts diff --git a/tools/binman/test/key.key b/tools/binman/test/security/key.key similarity index 100% rename from tools/binman/test/key.key rename to tools/binman/test/security/key.key diff --git a/tools/binman/test/key.pem b/tools/binman/test/security/key.pem similarity index 100% rename from tools/binman/test/key.pem rename to tools/binman/test/security/key.pem diff --git a/tools/binman/test/348_key_name_hint_dir_spl_pubkey_dtb.dts b/tools/binman/test/security/key_name_hint_dir_spl_pubkey_dtb.dts similarity index 100% rename from tools/binman/test/348_key_name_hint_dir_spl_pubkey_dtb.dts rename to tools/binman/test/security/key_name_hint_dir_spl_pubkey_dtb.dts diff --git a/tools/binman/test/230_pre_load.dts b/tools/binman/test/security/pre_load.dts similarity index 100% rename from tools/binman/test/230_pre_load.dts rename to tools/binman/test/security/pre_load.dts diff --git a/tools/binman/test/235_pre_load_invalid_algo.dts b/tools/binman/test/security/pre_load_invalid_algo.dts similarity index 100% rename from tools/binman/test/235_pre_load_invalid_algo.dts rename to tools/binman/test/security/pre_load_invalid_algo.dts diff --git a/tools/binman/test/236_pre_load_invalid_key.dts b/tools/binman/test/security/pre_load_invalid_key.dts similarity index 100% rename from tools/binman/test/236_pre_load_invalid_key.dts rename to tools/binman/test/security/pre_load_invalid_key.dts diff --git a/tools/binman/test/233_pre_load_invalid_padding.dts b/tools/binman/test/security/pre_load_invalid_padding.dts similarity index 100% rename from tools/binman/test/233_pre_load_invalid_padding.dts rename to tools/binman/test/security/pre_load_invalid_padding.dts diff --git a/tools/binman/test/234_pre_load_invalid_sha.dts b/tools/binman/test/security/pre_load_invalid_sha.dts similarity index 100% rename from tools/binman/test/234_pre_load_invalid_sha.dts rename to tools/binman/test/security/pre_load_invalid_sha.dts diff --git a/tools/binman/test/231_pre_load_pkcs.dts b/tools/binman/test/security/pre_load_pkcs.dts similarity index 100% rename from tools/binman/test/231_pre_load_pkcs.dts rename to tools/binman/test/security/pre_load_pkcs.dts diff --git a/tools/binman/test/232_pre_load_pss.dts b/tools/binman/test/security/pre_load_pss.dts similarity index 100% rename from tools/binman/test/232_pre_load_pss.dts rename to tools/binman/test/security/pre_load_pss.dts diff --git a/tools/binman/test/165_section_ignore_hash_signature.dts b/tools/binman/test/security/section_ignore_hash_signature.dts similarity index 100% rename from tools/binman/test/165_section_ignore_hash_signature.dts rename to tools/binman/test/security/section_ignore_hash_signature.dts diff --git a/tools/binman/test/281_sign_non_fit.dts b/tools/binman/test/security/sign_non_fit.dts similarity index 100% rename from tools/binman/test/281_sign_non_fit.dts rename to tools/binman/test/security/sign_non_fit.dts diff --git a/tools/binman/test/306_spl_pubkey_dtb.dts b/tools/binman/test/security/spl_pubkey_dtb.dts similarity index 100% rename from tools/binman/test/306_spl_pubkey_dtb.dts rename to tools/binman/test/security/spl_pubkey_dtb.dts diff --git a/tools/binman/test/279_x509_cert.dts b/tools/binman/test/security/x509_cert.dts similarity index 100% rename from tools/binman/test/279_x509_cert.dts rename to tools/binman/test/security/x509_cert.dts diff --git a/tools/binman/test/307_xilinx_bootgen_sign.dts b/tools/binman/test/security/xilinx_bootgen_sign.dts similarity index 100% rename from tools/binman/test/307_xilinx_bootgen_sign.dts rename to tools/binman/test/security/xilinx_bootgen_sign.dts diff --git a/tools/binman/test/308_xilinx_bootgen_sign_enc.dts b/tools/binman/test/security/xilinx_bootgen_sign_enc.dts similarity index 100% rename from tools/binman/test/308_xilinx_bootgen_sign_enc.dts rename to tools/binman/test/security/xilinx_bootgen_sign_enc.dts diff --git a/tools/binman/test/336_symbols_base.dts b/tools/binman/test/symbols/base.dts similarity index 100% rename from tools/binman/test/336_symbols_base.dts rename to tools/binman/test/symbols/base.dts diff --git a/tools/binman/test/337_symbols_base_expand.dts b/tools/binman/test/symbols/base_expand.dts similarity index 100% rename from tools/binman/test/337_symbols_base_expand.dts rename to tools/binman/test/symbols/base_expand.dts diff --git a/tools/binman/test/338_symbols_comp.dts b/tools/binman/test/symbols/comp.dts similarity index 100% rename from tools/binman/test/338_symbols_comp.dts rename to tools/binman/test/symbols/comp.dts diff --git a/tools/binman/test/282_symbols_disable.dts b/tools/binman/test/symbols/disable.dts similarity index 100% rename from tools/binman/test/282_symbols_disable.dts rename to tools/binman/test/symbols/disable.dts diff --git a/tools/binman/test/260_symbols_elf.dts b/tools/binman/test/symbols/elf.dts similarity index 100% rename from tools/binman/test/260_symbols_elf.dts rename to tools/binman/test/symbols/elf.dts diff --git a/tools/binman/test/197_symbols_expand.dts b/tools/binman/test/symbols/expand.dts similarity index 100% rename from tools/binman/test/197_symbols_expand.dts rename to tools/binman/test/symbols/expand.dts diff --git a/tools/binman/test/196_symbols_nodtb.dts b/tools/binman/test/symbols/nodtb.dts similarity index 100% rename from tools/binman/test/196_symbols_nodtb.dts rename to tools/binman/test/symbols/nodtb.dts diff --git a/tools/binman/test/187_symbols_sub.dts b/tools/binman/test/symbols/sub.dts similarity index 100% rename from tools/binman/test/187_symbols_sub.dts rename to tools/binman/test/symbols/sub.dts diff --git a/tools/binman/test/053_symbols.dts b/tools/binman/test/symbols/symbols.dts similarity index 100% rename from tools/binman/test/053_symbols.dts rename to tools/binman/test/symbols/symbols.dts diff --git a/tools/binman/test/149_symbols_tpl.dts b/tools/binman/test/symbols/tpl.dts similarity index 100% rename from tools/binman/test/149_symbols_tpl.dts rename to tools/binman/test/symbols/tpl.dts diff --git a/tools/binman/test/346_nxp_ddrfw_imx95.dts b/tools/binman/test/vendor/nxp_ddrfw_imx95.dts similarity index 100% rename from tools/binman/test/346_nxp_ddrfw_imx95.dts rename to tools/binman/test/vendor/nxp_ddrfw_imx95.dts diff --git a/tools/binman/test/339_nxp_imx8.dts b/tools/binman/test/vendor/nxp_imx8.dts similarity index 93% rename from tools/binman/test/339_nxp_imx8.dts rename to tools/binman/test/vendor/nxp_imx8.dts index cb512ae9aa2..d9fc86635b4 100644 --- a/tools/binman/test/339_nxp_imx8.dts +++ b/tools/binman/test/vendor/nxp_imx8.dts @@ -12,6 +12,9 @@ nxp,boot-from = "sd"; nxp,rom-version = <1>; nxp,loader-address = <0x10>; + + u-boot { + }; }; }; }; diff --git a/tools/binman/test/vendor/nxp_imx8_csf.dts b/tools/binman/test/vendor/nxp_imx8_csf.dts new file mode 100644 index 00000000000..148f4668bb9 --- /dev/null +++ b/tools/binman/test/vendor/nxp_imx8_csf.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + nxp-imx8mcst { + args; + nxp,loader-address = <0x10>; + + blob { + filename = "imx8m-ivt.bin"; + }; + + imagename { + type = "section"; + + u-boot { + }; + }; + }; + }; +}; diff --git a/tools/binman/test/vendor/nxp_imx8_csf_fast_auth.dts b/tools/binman/test/vendor/nxp_imx8_csf_fast_auth.dts new file mode 100644 index 00000000000..af35f2569df --- /dev/null +++ b/tools/binman/test/vendor/nxp_imx8_csf_fast_auth.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + nxp-imx8mcst { + args; + nxp,loader-address = <0x10>; + nxp,fast-auth; + nxp,unlock; + + blob { + filename = "imx8m-fit.bin"; + }; + }; + }; +}; diff --git a/tools/binman/test/vendor/nxp_imx8_imagename.dts b/tools/binman/test/vendor/nxp_imx8_imagename.dts new file mode 100644 index 00000000000..58dd1ca3d5d --- /dev/null +++ b/tools/binman/test/vendor/nxp_imx8_imagename.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + nxp-imx8mimage { + args; /* TODO: Needed by mkimage etype superclass */ + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = <0x10>; + + u-boot { + }; + + imagename { + type = "section"; + + u-boot { + }; + }; + }; + }; +}; diff --git a/tools/binman/test/350_nxp_imx95.dts b/tools/binman/test/vendor/nxp_imx95.dts similarity index 100% rename from tools/binman/test/350_nxp_imx95.dts rename to tools/binman/test/vendor/nxp_imx95.dts diff --git a/tools/binman/test/150_powerpc_mpc85xx_bootpg_resetvec.dts b/tools/binman/test/vendor/powerpc_mpc85xx_bootpg_resetvec.dts similarity index 100% rename from tools/binman/test/150_powerpc_mpc85xx_bootpg_resetvec.dts rename to tools/binman/test/vendor/powerpc_mpc85xx_bootpg_resetvec.dts diff --git a/tools/binman/test/348_renesas_rcar4_sa0.dts b/tools/binman/test/vendor/renesas_rcar4_sa0.dts similarity index 100% rename from tools/binman/test/348_renesas_rcar4_sa0.dts rename to tools/binman/test/vendor/renesas_rcar4_sa0.dts diff --git a/tools/binman/test/349_renesas_rcar4_sa0_size.dts b/tools/binman/test/vendor/renesas_rcar4_sa0_size.dts similarity index 100% rename from tools/binman/test/349_renesas_rcar4_sa0_size.dts rename to tools/binman/test/vendor/renesas_rcar4_sa0_size.dts diff --git a/tools/binman/test/291_rockchip_tpl.dts b/tools/binman/test/vendor/rockchip_tpl.dts similarity index 100% rename from tools/binman/test/291_rockchip_tpl.dts rename to tools/binman/test/vendor/rockchip_tpl.dts diff --git a/tools/binman/test/293_ti_board_cfg.dts b/tools/binman/test/vendor/ti_board_cfg.dts similarity index 100% rename from tools/binman/test/293_ti_board_cfg.dts rename to tools/binman/test/vendor/ti_board_cfg.dts diff --git a/tools/binman/test/294_ti_board_cfg_combined.dts b/tools/binman/test/vendor/ti_board_cfg_combined.dts similarity index 100% rename from tools/binman/test/294_ti_board_cfg_combined.dts rename to tools/binman/test/vendor/ti_board_cfg_combined.dts diff --git a/tools/binman/test/295_ti_board_cfg_no_type.dts b/tools/binman/test/vendor/ti_board_cfg_no_type.dts similarity index 100% rename from tools/binman/test/295_ti_board_cfg_no_type.dts rename to tools/binman/test/vendor/ti_board_cfg_no_type.dts diff --git a/tools/binman/test/323_ti_board_cfg_phony.dts b/tools/binman/test/vendor/ti_board_cfg_phony.dts similarity index 100% rename from tools/binman/test/323_ti_board_cfg_phony.dts rename to tools/binman/test/vendor/ti_board_cfg_phony.dts diff --git a/tools/binman/test/225_ti_dm.dts b/tools/binman/test/vendor/ti_dm.dts similarity index 100% rename from tools/binman/test/225_ti_dm.dts rename to tools/binman/test/vendor/ti_dm.dts diff --git a/tools/binman/test/296_ti_secure.dts b/tools/binman/test/vendor/ti_secure.dts similarity index 100% rename from tools/binman/test/296_ti_secure.dts rename to tools/binman/test/vendor/ti_secure.dts diff --git a/tools/binman/test/324_ti_secure_firewall.dts b/tools/binman/test/vendor/ti_secure_firewall.dts similarity index 100% rename from tools/binman/test/324_ti_secure_firewall.dts rename to tools/binman/test/vendor/ti_secure_firewall.dts diff --git a/tools/binman/test/325_ti_secure_firewall_missing_property.dts b/tools/binman/test/vendor/ti_secure_firewall_missing_property.dts similarity index 100% rename from tools/binman/test/325_ti_secure_firewall_missing_property.dts rename to tools/binman/test/vendor/ti_secure_firewall_missing_property.dts diff --git a/tools/binman/test/297_ti_secure_rom.dts b/tools/binman/test/vendor/ti_secure_rom.dts similarity index 100% rename from tools/binman/test/297_ti_secure_rom.dts rename to tools/binman/test/vendor/ti_secure_rom.dts diff --git a/tools/binman/test/299_ti_secure_rom_a.dts b/tools/binman/test/vendor/ti_secure_rom_a.dts similarity index 100% rename from tools/binman/test/299_ti_secure_rom_a.dts rename to tools/binman/test/vendor/ti_secure_rom_a.dts diff --git a/tools/binman/test/300_ti_secure_rom_b.dts b/tools/binman/test/vendor/ti_secure_rom_b.dts similarity index 100% rename from tools/binman/test/300_ti_secure_rom_b.dts rename to tools/binman/test/vendor/ti_secure_rom_b.dts diff --git a/tools/binman/test/298_ti_secure_rom_combined.dts b/tools/binman/test/vendor/ti_secure_rom_combined.dts similarity index 100% rename from tools/binman/test/298_ti_secure_rom_combined.dts rename to tools/binman/test/vendor/ti_secure_rom_combined.dts diff --git a/tools/binman/test/descriptor.bin b/tools/binman/test/x86/descriptor.bin similarity index 100% rename from tools/binman/test/descriptor.bin rename to tools/binman/test/x86/descriptor.bin diff --git a/tools/binman/test/141_descriptor_offset.dts b/tools/binman/test/x86/descriptor_offset.dts similarity index 100% rename from tools/binman/test/141_descriptor_offset.dts rename to tools/binman/test/x86/descriptor_offset.dts diff --git a/tools/binman/test/fitimage.bin.gz b/tools/binman/test/x86/fitimage.bin.gz similarity index 100% rename from tools/binman/test/fitimage.bin.gz rename to tools/binman/test/x86/fitimage.bin.gz diff --git a/tools/binman/test/094_fmap_x86.dts b/tools/binman/test/x86/fmap.dts similarity index 100% rename from tools/binman/test/094_fmap_x86.dts rename to tools/binman/test/x86/fmap.dts diff --git a/tools/binman/test/095_fmap_x86_section.dts b/tools/binman/test/x86/fmap_section.dts similarity index 100% rename from tools/binman/test/095_fmap_x86_section.dts rename to tools/binman/test/x86/fmap_section.dts diff --git a/tools/binman/test/ifwi.bin.gz b/tools/binman/test/x86/ifwi.bin.gz similarity index 100% rename from tools/binman/test/ifwi.bin.gz rename to tools/binman/test/x86/ifwi.bin.gz diff --git a/tools/binman/test/043_intel_cmc.dts b/tools/binman/test/x86/intel_cmc.dts similarity index 100% rename from tools/binman/test/043_intel_cmc.dts rename to tools/binman/test/x86/intel_cmc.dts diff --git a/tools/binman/test/147_intel_fit.dts b/tools/binman/test/x86/intel_fit.dts similarity index 100% rename from tools/binman/test/147_intel_fit.dts rename to tools/binman/test/x86/intel_fit.dts diff --git a/tools/binman/test/148_intel_fit_missing.dts b/tools/binman/test/x86/intel_fit_missing.dts similarity index 100% rename from tools/binman/test/148_intel_fit_missing.dts rename to tools/binman/test/x86/intel_fit_missing.dts diff --git a/tools/binman/test/042_intel_fsp.dts b/tools/binman/test/x86/intel_fsp.dts similarity index 100% rename from tools/binman/test/042_intel_fsp.dts rename to tools/binman/test/x86/intel_fsp.dts diff --git a/tools/binman/test/152_intel_fsp_m.dts b/tools/binman/test/x86/intel_fsp_m.dts similarity index 100% rename from tools/binman/test/152_intel_fsp_m.dts rename to tools/binman/test/x86/intel_fsp_m.dts diff --git a/tools/binman/test/153_intel_fsp_s.dts b/tools/binman/test/x86/intel_fsp_s.dts similarity index 100% rename from tools/binman/test/153_intel_fsp_s.dts rename to tools/binman/test/x86/intel_fsp_s.dts diff --git a/tools/binman/test/154_intel_fsp_t.dts b/tools/binman/test/x86/intel_fsp_t.dts similarity index 100% rename from tools/binman/test/154_intel_fsp_t.dts rename to tools/binman/test/x86/intel_fsp_t.dts diff --git a/tools/binman/test/050_intel_mrc.dts b/tools/binman/test/x86/intel_mrc.dts similarity index 100% rename from tools/binman/test/050_intel_mrc.dts rename to tools/binman/test/x86/intel_mrc.dts diff --git a/tools/binman/test/100_intel_refcode.dts b/tools/binman/test/x86/intel_refcode.dts similarity index 100% rename from tools/binman/test/100_intel_refcode.dts rename to tools/binman/test/x86/intel_refcode.dts diff --git a/tools/binman/test/046_intel_vbt.dts b/tools/binman/test/x86/intel_vbt.dts similarity index 100% rename from tools/binman/test/046_intel_vbt.dts rename to tools/binman/test/x86/intel_vbt.dts diff --git a/tools/binman/test/032_intel_vga.dts b/tools/binman/test/x86/intel_vga.dts similarity index 100% rename from tools/binman/test/032_intel_vga.dts rename to tools/binman/test/x86/intel_vga.dts diff --git a/tools/binman/test/037_x86_no_ucode.dts b/tools/binman/test/x86/no_ucode.dts similarity index 100% rename from tools/binman/test/037_x86_no_ucode.dts rename to tools/binman/test/x86/no_ucode.dts diff --git a/tools/binman/test/044_x86_optional_ucode.dts b/tools/binman/test/x86/optional_ucode.dts similarity index 100% rename from tools/binman/test/044_x86_optional_ucode.dts rename to tools/binman/test/x86/optional_ucode.dts diff --git a/tools/binman/test/144_x86_reset16.dts b/tools/binman/test/x86/reset16.dts similarity index 100% rename from tools/binman/test/144_x86_reset16.dts rename to tools/binman/test/x86/reset16.dts diff --git a/tools/binman/test/145_x86_reset16_spl.dts b/tools/binman/test/x86/reset16_spl.dts similarity index 100% rename from tools/binman/test/145_x86_reset16_spl.dts rename to tools/binman/test/x86/reset16_spl.dts diff --git a/tools/binman/test/146_x86_reset16_tpl.dts b/tools/binman/test/x86/reset16_tpl.dts similarity index 100% rename from tools/binman/test/146_x86_reset16_tpl.dts rename to tools/binman/test/x86/reset16_tpl.dts diff --git a/tools/binman/test/029_x86_rom.dts b/tools/binman/test/x86/rom.dts similarity index 100% rename from tools/binman/test/029_x86_rom.dts rename to tools/binman/test/x86/rom.dts diff --git a/tools/binman/test/111_x86_rom_ifwi.dts b/tools/binman/test/x86/rom_ifwi.dts similarity index 100% rename from tools/binman/test/111_x86_rom_ifwi.dts rename to tools/binman/test/x86/rom_ifwi.dts diff --git a/tools/binman/test/113_x86_rom_ifwi_nodata.dts b/tools/binman/test/x86/rom_ifwi_nodata.dts similarity index 100% rename from tools/binman/test/113_x86_rom_ifwi_nodata.dts rename to tools/binman/test/x86/rom_ifwi_nodata.dts diff --git a/tools/binman/test/112_x86_rom_ifwi_nodesc.dts b/tools/binman/test/x86/rom_ifwi_nodesc.dts similarity index 100% rename from tools/binman/test/112_x86_rom_ifwi_nodesc.dts rename to tools/binman/test/x86/rom_ifwi_nodesc.dts diff --git a/tools/binman/test/151_x86_rom_ifwi_section.dts b/tools/binman/test/x86/rom_ifwi_section.dts similarity index 100% rename from tools/binman/test/151_x86_rom_ifwi_section.dts rename to tools/binman/test/x86/rom_ifwi_section.dts diff --git a/tools/binman/test/031_x86_rom_me.dts b/tools/binman/test/x86/rom_me.dts similarity index 100% rename from tools/binman/test/031_x86_rom_me.dts rename to tools/binman/test/x86/rom_me.dts diff --git a/tools/binman/test/163_x86_rom_me_empty.dts b/tools/binman/test/x86/rom_me_empty.dts similarity index 100% rename from tools/binman/test/163_x86_rom_me_empty.dts rename to tools/binman/test/x86/rom_me_empty.dts diff --git a/tools/binman/test/164_x86_rom_me_missing.dts b/tools/binman/test/x86/rom_me_missing.dts similarity index 100% rename from tools/binman/test/164_x86_rom_me_missing.dts rename to tools/binman/test/x86/rom_me_missing.dts diff --git a/tools/binman/test/030_x86_rom_me_no_desc.dts b/tools/binman/test/x86/rom_me_no_desc.dts similarity index 100% rename from tools/binman/test/030_x86_rom_me_no_desc.dts rename to tools/binman/test/x86/rom_me_no_desc.dts diff --git a/tools/binman/test/035_x86_single_ucode.dts b/tools/binman/test/x86/single_ucode.dts similarity index 100% rename from tools/binman/test/035_x86_single_ucode.dts rename to tools/binman/test/x86/single_ucode.dts diff --git a/tools/binman/test/033_x86_start16.dts b/tools/binman/test/x86/start16.dts similarity index 100% rename from tools/binman/test/033_x86_start16.dts rename to tools/binman/test/x86/start16.dts diff --git a/tools/binman/test/048_x86_start16_spl.dts b/tools/binman/test/x86/start16_spl.dts similarity index 100% rename from tools/binman/test/048_x86_start16_spl.dts rename to tools/binman/test/x86/start16_spl.dts diff --git a/tools/binman/test/081_x86_start16_tpl.dts b/tools/binman/test/x86/start16_tpl.dts similarity index 100% rename from tools/binman/test/081_x86_start16_tpl.dts rename to tools/binman/test/x86/start16_tpl.dts diff --git a/tools/binman/test/155_symbols_tpl_x86.dts b/tools/binman/test/x86/symbols_tpl.dts similarity index 100% rename from tools/binman/test/155_symbols_tpl_x86.dts rename to tools/binman/test/x86/symbols_tpl.dts diff --git a/tools/binman/test/093_x86_tpl_ucode.dts b/tools/binman/test/x86/tpl_ucode.dts similarity index 100% rename from tools/binman/test/093_x86_tpl_ucode.dts rename to tools/binman/test/x86/tpl_ucode.dts diff --git a/tools/binman/test/034_x86_ucode.dts b/tools/binman/test/x86/ucode.dts similarity index 100% rename from tools/binman/test/034_x86_ucode.dts rename to tools/binman/test/x86/ucode.dts diff --git a/tools/binman/test/038_x86_ucode_missing_node.dts b/tools/binman/test/x86/ucode_missing_node.dts similarity index 100% rename from tools/binman/test/038_x86_ucode_missing_node.dts rename to tools/binman/test/x86/ucode_missing_node.dts diff --git a/tools/binman/test/039_x86_ucode_missing_node2.dts b/tools/binman/test/x86/ucode_missing_node2.dts similarity index 100% rename from tools/binman/test/039_x86_ucode_missing_node2.dts rename to tools/binman/test/x86/ucode_missing_node2.dts diff --git a/tools/binman/test/040_x86_ucode_not_in_image.dts b/tools/binman/test/x86/ucode_not_in_image.dts similarity index 100% rename from tools/binman/test/040_x86_ucode_not_in_image.dts rename to tools/binman/test/x86/ucode_not_in_image.dts diff --git a/tools/binman/test/049_x86_ucode_spl.dts b/tools/binman/test/x86/ucode_spl.dts similarity index 100% rename from tools/binman/test/049_x86_ucode_spl.dts rename to tools/binman/test/x86/ucode_spl.dts diff --git a/tools/binman/test/058_x86_ucode_spl_needs_retry.dts b/tools/binman/test/x86/ucode_spl_needs_retry.dts similarity index 100% rename from tools/binman/test/058_x86_ucode_spl_needs_retry.dts rename to tools/binman/test/x86/ucode_spl_needs_retry.dts diff --git a/tools/binman/test/026_pack_u_boot_dtb.dts b/tools/binman/test/xpl/pack_dtb.dts similarity index 100% rename from tools/binman/test/026_pack_u_boot_dtb.dts rename to tools/binman/test/xpl/pack_dtb.dts diff --git a/tools/binman/test/047_spl_bss_pad.dts b/tools/binman/test/xpl/spl_bss_pad.dts similarity index 100% rename from tools/binman/test/047_spl_bss_pad.dts rename to tools/binman/test/xpl/spl_bss_pad.dts diff --git a/tools/binman/test/078_u_boot_tpl.dts b/tools/binman/test/xpl/tpl.dts similarity index 100% rename from tools/binman/test/078_u_boot_tpl.dts rename to tools/binman/test/xpl/tpl.dts diff --git a/tools/binman/test/193_tpl_bss_pad.dts b/tools/binman/test/xpl/tpl_bss_pad.dts similarity index 100% rename from tools/binman/test/193_tpl_bss_pad.dts rename to tools/binman/test/xpl/tpl_bss_pad.dts diff --git a/tools/binman/test/036_u_boot_img.dts b/tools/binman/test/xpl/u-boot-img.dts similarity index 100% rename from tools/binman/test/036_u_boot_img.dts rename to tools/binman/test/xpl/u-boot-img.dts diff --git a/tools/binman/test/051_u_boot_spl_dtb.dts b/tools/binman/test/xpl/u-boot-spl-dtb.dts similarity index 100% rename from tools/binman/test/051_u_boot_spl_dtb.dts rename to tools/binman/test/xpl/u-boot-spl-dtb.dts diff --git a/tools/binman/test/052_u_boot_spl_nodtb.dts b/tools/binman/test/xpl/u-boot-spl-nodtb.dts similarity index 100% rename from tools/binman/test/052_u_boot_spl_nodtb.dts rename to tools/binman/test/xpl/u-boot-spl-nodtb.dts diff --git a/tools/binman/test/285_spl_expand.dts b/tools/binman/test/xpl/u-boot-spl.dts similarity index 100% rename from tools/binman/test/285_spl_expand.dts rename to tools/binman/test/xpl/u-boot-spl.dts diff --git a/tools/binman/test/192_u_boot_tpl_nodtb.dts b/tools/binman/test/xpl/u-boot-tpl-nodtb.dts similarity index 100% rename from tools/binman/test/192_u_boot_tpl_nodtb.dts rename to tools/binman/test/xpl/u-boot-tpl-nodtb.dts diff --git a/tools/binman/test/256_u_boot_vpl_nodtb.dts b/tools/binman/test/xpl/u-boot-vpl-nodtb.dts similarity index 100% rename from tools/binman/test/256_u_boot_vpl_nodtb.dts rename to tools/binman/test/xpl/u-boot-vpl-nodtb.dts diff --git a/tools/binman/test/255_u_boot_vpl.dts b/tools/binman/test/xpl/vpl.dts similarity index 100% rename from tools/binman/test/255_u_boot_vpl.dts rename to tools/binman/test/xpl/vpl.dts diff --git a/tools/binman/test/258_vpl_bss_pad.dts b/tools/binman/test/xpl/vpl_bss_pad.dts similarity index 100% rename from tools/binman/test/258_vpl_bss_pad.dts rename to tools/binman/test/xpl/vpl_bss_pad.dts diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 425faf380fb..49a068d91cc 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -50,6 +50,7 @@ struct env_opts default_opts = { }; #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) +#define ROUND_UP(x, y) (DIV_ROUND_UP(x, y) * (y)) #define min(x, y) ({ \ typeof(x) _min1 = (x); \ @@ -983,9 +984,6 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count) { void *data; struct erase_info_user erase; - size_t blocklen; /* length of NAND block / NOR erase sector */ - size_t erase_len; /* whole area that can be erased - may include - bad blocks */ size_t erasesize; /* erase / write length - one block on NAND, whole area on NOR */ size_t processed = 0; /* progress counter */ @@ -1004,20 +1002,21 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count) * For mtd devices only offset and size of the environment do matter */ if (DEVTYPE(dev) == MTD_ABSENT) { - blocklen = count; - erase_len = blocklen; - blockstart = DEVOFFSET(dev); + erasesize = count; block_seek = 0; - write_total = blocklen; + write_total = count; } else { - blocklen = DEVESIZE(dev); - erase_offset = DEVOFFSET(dev); - /* Maximum area we may use */ - erase_len = environment_end(dev) - erase_offset; - - blockstart = erase_offset; + if (DEVTYPE(dev) == MTD_NANDFLASH) { + /* + * NAND: calculate which blocks we are writing. We have + * to write one block at a time to skip bad blocks. + */ + erasesize = DEVESIZE(dev); + } else { + erasesize = environment_end(dev) - erase_offset; + } /* Offset inside a block */ block_seek = DEVOFFSET(dev) - erase_offset; @@ -1027,8 +1026,7 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count) * to the start of the data, then count bytes of data, and * to the end of the block */ - write_total = ((block_seek + count + blocklen - 1) / - blocklen) * blocklen; + write_total = ROUND_UP(block_seek + count, DEVESIZE(dev)); } /* @@ -1037,11 +1035,11 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count) * block back again. */ if (write_total > count) { - data = malloc(erase_len); + data = malloc(write_total); if (!data) { fprintf(stderr, "Cannot malloc %zu bytes: %s\n", - erase_len, strerror(errno)); + write_total, strerror(errno)); return -1; } @@ -1067,24 +1065,15 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count) } else { /* * We get here, iff offset is block-aligned and count is a - * multiple of blocklen - see write_total calculation above + * multiple of erase size - see write_total calculation above */ data = buf; } - if (DEVTYPE(dev) == MTD_NANDFLASH) { - /* - * NAND: calculate which blocks we are writing. We have - * to write one block at a time to skip bad blocks. - */ - erasesize = blocklen; - } else { - erasesize = erase_len; - } - erase.length = erasesize; /* This only runs once on NOR flash and SPI-dataflash */ + blockstart = DEVOFFSET(dev); while (processed < write_total) { rc = flash_bad_block(fd, DEVTYPE(dev), blockstart); if (rc < 0) /* block test failed */ @@ -1096,7 +1085,7 @@ static int flash_write_buf(int dev, int fd, void *buf, size_t count) } if (rc) { /* block is bad */ - blockstart += blocklen; + blockstart += erasesize; continue; } diff --git a/tools/fwumdata_src/Kconfig b/tools/fwumdata_src/Kconfig new file mode 100644 index 00000000000..af1f3bb3f57 --- /dev/null +++ b/tools/fwumdata_src/Kconfig @@ -0,0 +1,19 @@ +config TOOLS_MKFWUMDATA + bool "Build mkfwumdata command" + default y if FWU_MULTI_BANK_UPDATE + help + This command allows users to create a raw image of the FWU + metadata for initial installation of the FWU multi bank + update on the board. The installation method depends on + the platform. + +config TOOLS_FWUMDATA + bool "Build fwumdata command" + default y if FWU_MULTI_BANK_UPDATE + help + This command allows users to read, display, and modify FWU + (Firmware Update) metadata from Linux userspace. It provides + functionality similar to fw_printenv/fw_setenv but for FWU + metadata. Users can view metadata, change active/previous + bank indices, modify bank states, and set image acceptance + flags. Configuration is done via fwumdata.config file. diff --git a/tools/fwumdata_src/fwumdata.c b/tools/fwumdata_src/fwumdata.c new file mode 100644 index 00000000000..c5b0f56842d --- /dev/null +++ b/tools/fwumdata_src/fwumdata.c @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * FWU Metadata Read/Write Tool + * Copyright (c) 2025, Kory Maincent + * + * Tool to read, display, and modify FWU (Firmware Update) metadata + * from Linux userspace. Similar to fw_printenv/fw_setenv for U-Boot + * environment, but for FWU metadata. + * + * Usage: + * fwumdata - Print all metadata + * fwumdata -u - Print metadata and update it if CRC corrupted + * fwumdata -c - Use custom config file + * fwumdata -a - Set active bank + * fwumdata -p - Set previous bank + * fwumdata -s - Set bank state (V2 only) + * fwumdata -i -b -A - Accept image + * fwumdata -i -b -C - Clear image acceptance + * fwumdata -i -b + * -B + * -I -C - Clear image acceptance (V1 only) + * fwumdata -l - List detailed info with GUIDs + */ + +#include +#include +#include +#include +#include +#include +#include +#include "fwumdata.h" + +/* Device configuration */ +struct fwumdata_device { + const char *devname; + long long devoff; + unsigned long mdata_size; + unsigned long erase_size; + int fd; + bool is_mtd; +}; + +/* Global state */ +static struct fwumdata_device devices[2]; /* Primary and secondary */ +static struct fwu_mdata *mdata; +static int have_redundant; +static struct fwu_mdata *valid_mdata; +static bool mdata_mod; +static const char *config_file; +static int nbanks, nimages; /* For V1 only */ +static const char * const default_config_files[] = { + "./fwumdata.config", + "/etc/fwumdata.config", + NULL +}; + +/* GUID/UUID utilities */ +static void guid_to_string(const struct efi_guid *guid, char *str) +{ + sprintf(str, "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", + guid->time_high, guid->time_low, guid->reserved, + guid->family, guid->node[0], + guid->node[1], guid->node[2], guid->node[3], + guid->node[4], guid->node[5], guid->node[6]); +} + +/* Config file parsing */ +static int parse_config(const char *fname) +{ + size_t linesize = 0; + char *line = NULL; + char *devname; + int i = 0; + FILE *fp; + int rc; + + fp = fopen(fname, "r"); + if (!fp) + return -ENOENT; + + while (i < 2 && getline(&line, &linesize, fp) != -1) { + /* Skip comments and empty lines */ + if (line[0] == '#' || line[0] == '\n') + continue; + + rc = sscanf(line, "%ms %lli %lx %lx", + &devname, + &devices[i].devoff, + &devices[i].mdata_size, + &devices[i].erase_size); + + if (rc < 3) { + free(devname); + continue; + } + + if (rc < 4) + devices[i].erase_size = devices[i].mdata_size; + + devices[i].devname = devname; + i++; + } + + free(line); + fclose(fp); + + if (i == 2) { + have_redundant = true; + if (devices[0].mdata_size != devices[1].mdata_size) { + fprintf(stderr, + "Size mismatch between the two metadata\n"); + return -EINVAL; + } + } + + if (!i) { + fprintf(stderr, + "Can't read config %s content\n", fname); + return -EINVAL; + } + + return 0; +} + +static int find_parse_config(void) +{ + int i; + + if (config_file) + return parse_config(config_file); + + for (i = 0; default_config_files[i]; i++) { + int ret; + + ret = parse_config(default_config_files[i]); + if (ret == -ENOENT) + continue; + if (ret) + return ret; + + config_file = default_config_files[i]; + return 0; + } + + fprintf(stderr, "Error: Cannot find config file\n"); + return -ENOENT; +} + +static int open_device(struct fwumdata_device *dev) +{ + if (strstr(dev->devname, "/dev/mtd")) + dev->is_mtd = true; + + dev->fd = open(dev->devname, O_RDWR | O_SYNC); + if (dev->fd < 0) { + fprintf(stderr, "Cannot open %s: %s\n", dev->devname, + strerror(errno)); + return -ENODEV; + } + + return 0; +} + +static int mtd_erase(int fd, unsigned long offset, unsigned long size) +{ + struct erase_info_user erase; + int ret; + + erase.start = offset; + erase.length = size; + + ret = ioctl(fd, MEMERASE, &erase); + if (ret < 0) { + fprintf(stderr, "MTD erase failed: %s\n", strerror(errno)); + return -errno; + } + + return 0; +} + +static int read_device(struct fwumdata_device *dev, void *buf, size_t count) +{ + if (lseek(dev->fd, dev->devoff, SEEK_SET) < 0) { + fprintf(stderr, "Seek failed: %s\n", strerror(errno)); + return -errno; + } + + if (read(dev->fd, buf, count) < 0) { + fprintf(stderr, "Read failed: %s\n", strerror(errno)); + return -errno; + } + + return 0; +} + +static int write_device(struct fwumdata_device *dev, const void *buf, + size_t count) +{ + int ret; + + /* Erase if MTD device */ + if (dev->is_mtd) { + ret = mtd_erase(dev->fd, dev->devoff, dev->erase_size); + if (ret) + return ret; + } + + if (lseek(dev->fd, dev->devoff, SEEK_SET) < 0) { + fprintf(stderr, "Seek failed: %s\n", strerror(errno)); + return -errno; + } + + if (write(dev->fd, buf, count) < 0) { + fprintf(stderr, "Write failed: %s\n", strerror(errno)); + return -errno; + } + + return 0; +} + +/* Metadata operations */ +static int validate_crc(struct fwu_mdata *mdata, size_t size) +{ + u32 calc_crc, stored_crc; + + stored_crc = mdata->crc32; + calc_crc = crc32(0, (const u8 *)&mdata->version, size - sizeof(u32)); + + if (calc_crc != stored_crc) { + fprintf(stderr, + "CRC mismatch: calculated 0x%08x, stored 0x%08x\n", + calc_crc, stored_crc); + if (mdata->version == 1) + fprintf(stderr, + "Metadata is V1, this may be size description issue\n"); + return -1; + } + + return 0; +} + +static void update_crc(struct fwu_mdata *mdata, size_t size) +{ + mdata->crc32 = crc32(0, (const u8 *)&mdata->version, size - sizeof(u32)); +} + +static int read_one_metadata(int mdata_id, size_t size) +{ + int ret; + + ret = open_device(&devices[mdata_id]); + if (ret) + return ret; + + ret = read_device(&devices[mdata_id], &mdata[mdata_id], size); + if (ret) + return ret; + + if (mdata[mdata_id].version != 1 && mdata[mdata_id].version != 2) { + fprintf(stderr, "Invalid metadata %d version: %u\n", + mdata_id, mdata[mdata_id].version); + } + + return 0; +} + +static int read_metadata(bool update) +{ + size_t alloc_size; + int ret; + + /* Allocate initial buffer */ + alloc_size = devices[0].mdata_size; + mdata = calloc(have_redundant ? 2 : 1, alloc_size); + if (!mdata) { + fprintf(stderr, "Memory allocation failed\n"); + return -ENOMEM; + } + + ret = read_one_metadata(0, alloc_size); + if (ret) + return ret; + + if (validate_crc(&mdata[0], alloc_size) < 0) { + fprintf(stderr, + "Warning: Primary metadata CRC validation failed\n"); + mdata_mod = update; + } else { + valid_mdata = &mdata[0]; + } + + if (have_redundant) { + ret = read_one_metadata(1, alloc_size); + if (ret) + return ret; + + if (validate_crc(&mdata[1], alloc_size) < 0) { + fprintf(stderr, + "Warning: Secondary metadata CRC validation failed\n"); + mdata_mod = update; + } else if (valid_mdata && mdata[0].crc32 != mdata[1].crc32) { + fprintf(stderr, + "Metadatas valid but not equal, use first one as default\n"); + mdata_mod = update; + } else { + valid_mdata = &mdata[1]; + } + } + + if (!valid_mdata) { + fprintf(stderr, + "No metadata valid, use first one as default\n"); + mdata_mod = update; + valid_mdata = &mdata[0]; + } + + if (valid_mdata->version == 2) { + struct fwu_mdata_ext *mdata_ext; + + mdata_ext = fwu_get_fw_mdata_ext(valid_mdata); + if (mdata_ext->metadata_size != alloc_size) { + fprintf(stderr, + "Metadata real size 0x%x mismatch with the config 0x%zx\n", + mdata_ext->metadata_size, alloc_size); + return -EINVAL; + } + } + + return 0; +} + +static int write_metadata(void) +{ + size_t write_size = devices[0].mdata_size; + int ret; + + if (!mdata_mod) + return 0; + + /* Update CRC */ + update_crc(valid_mdata, write_size); + + /* Write primary */ + ret = write_device(&devices[0], valid_mdata, write_size); + if (ret < 0) { + fprintf(stderr, "Failed to write primary metadata\n"); + return ret; + } + + /* Write secondary if redundant */ + if (have_redundant) { + ret = write_device(&devices[1], valid_mdata, write_size); + if (ret < 0) { + fprintf(stderr, "Failed to write secondary metadata\n"); + return -1; + } + } + + printf("FWU metadata updated successfully\n"); + mdata_mod = 0; + + return 0; +} + +/* Display functions */ +static const char *bank_state_to_string(u8 state) +{ + switch (state) { + case FWU_BANK_ACCEPTED: + return "accepted"; + case FWU_BANK_VALID: + return "valid"; + case FWU_BANK_INVALID: + return "invalid"; + default: + return "unknown"; + } +} + +static void print_metadata_summary(void) +{ + int i; + + printf("FWU Metadata:\n"); + printf("\tVersion: %u\n", valid_mdata->version); + printf("\tActive Index: %u\n", valid_mdata->active_index); + printf("\tPrevious Index: %u\n", valid_mdata->previous_active_index); + printf("\tCRC32: 0x%08x\n", valid_mdata->crc32); + + if (valid_mdata->version == 2) { + struct fwu_fw_store_desc *fw_desc; + struct fwu_mdata_ext *mdata_ext; + + mdata_ext = fwu_get_fw_mdata_ext(valid_mdata); + printf("\tMetadata Size: %u bytes\n", mdata_ext->metadata_size); + printf("\tDescriptor Offset: %u\n", mdata_ext->desc_offset); + printf("\tBank States:\n"); + + fw_desc = fwu_get_fw_desc(valid_mdata); + for (i = 0; i < fw_desc->num_banks && i < MAX_BANKS_V2; i++) { + printf("\t\tBank %d: %s (0x%02x)\n", i, + bank_state_to_string(mdata_ext->bank_state[i]), + mdata_ext->bank_state[i]); + } + } +} + +static void print_metadata_detailed(void) +{ + struct fwu_fw_store_desc *fw_desc = NULL; + struct fwu_image_bank_info *bank_info; + struct fwu_image_entry *img_entry; + int num_images, num_banks; + char guid_str[64]; + int i, j; + + print_metadata_summary(); + + if (valid_mdata->version == 1) { + num_images = nimages; + num_banks = nbanks; + } else { + fw_desc = fwu_get_fw_desc(valid_mdata); + num_images = fw_desc->num_images; + num_banks = fw_desc->num_banks; + } + + if (fw_desc) { + printf("\n\tFirmware Store Descriptor:\n"); + printf("\t\tNumber of Banks: %u\n", num_banks); + printf("\t\tNumber of Images: %u\n", num_images); + printf("\t\tImage Entry Size: %u\n", fw_desc->img_entry_size); + printf("\t\tBank Info Entry Size: %u\n", fw_desc->bank_info_entry_size); + } + + printf("\n\tImages:\n"); + for (i = 0; i < num_images; i++) { + img_entry = fwu_get_image_entry(valid_mdata, valid_mdata->version, + num_banks, i); + + printf("\t\tImage %d:\n", i); + + guid_to_string(&img_entry->image_type_guid, guid_str); + printf("\t\t\tImage Type GUID: %s\n", guid_str); + + guid_to_string(&img_entry->location_guid, guid_str); + printf("\t\t\tLocation GUID: %s\n", guid_str); + + printf("\t\t\tBanks:\n"); + for (j = 0; j < num_banks; j++) { + bank_info = fwu_get_bank_info(valid_mdata, + valid_mdata->version, + num_banks, i, j); + + guid_to_string(&bank_info->image_guid, guid_str); + printf("\t\t\t\tBank %d:\n", j); + printf("\t\t\t\t\tImage GUID: %s\n", guid_str); + printf("\t\t\t\t\tAccepted: %s (%u)\n", + (bank_info->accepted & FWU_IMAGE_ACCEPTED) ? "yes" : "no", + bank_info->accepted); + } + } +} + +/* Modification functions */ +static int set_active_index(int bank) +{ + struct fwu_fw_store_desc *fw_desc; + int num_banks; + + if (valid_mdata->version == 2) { + fw_desc = fwu_get_fw_desc(valid_mdata); + num_banks = fw_desc->num_banks; + } else { + num_banks = nbanks; + } + + if (bank < 0 || bank >= num_banks) { + fprintf(stderr, "Error: Invalid bank %d (must be 0-%d)\n", + bank, num_banks - 1); + return -EINVAL; + } + + if (valid_mdata->active_index == bank) + return 0; + + valid_mdata->active_index = bank; + mdata_mod = 1; + + printf("Active bank set to %d\n", bank); + return 0; +} + +static int set_previous_index(int bank) +{ + struct fwu_fw_store_desc *fw_desc; + int num_banks; + + if (valid_mdata->version == 2) { + fw_desc = fwu_get_fw_desc(valid_mdata); + num_banks = fw_desc->num_banks; + } else { + num_banks = nbanks; + } + + if (bank < 0 || bank >= num_banks) { + fprintf(stderr, "Error: Invalid bank %d (must be 0-%d)\n", + bank, num_banks - 1); + return -EINVAL; + } + + if (valid_mdata->previous_active_index == bank) + return 0; + + valid_mdata->previous_active_index = bank; + mdata_mod = 1; + + printf("Previous bank set to %d\n", bank); + return 0; +} + +static int set_image_accepted(int image, int bank, int accept) +{ + struct fwu_image_bank_info *bank_info; + int num_images, num_banks; + + if (valid_mdata->version == 1) { + num_images = nimages; + num_banks = nbanks; + } else { + struct fwu_fw_store_desc *fw_desc; + + fw_desc = fwu_get_fw_desc(valid_mdata); + num_images = fw_desc->num_images; + num_banks = fw_desc->num_banks; + } + + if (bank < 0 || bank >= num_banks) { + fprintf(stderr, "Error: Invalid bank %d (must be 0-%d)\n", + bank, num_banks - 1); + return -EINVAL; + } + + if (image < 0 || image >= num_images) { + fprintf(stderr, "Error: Invalid image %d (must be 0-%d)\n", + image, num_images - 1); + return -EINVAL; + } + + bank_info = fwu_get_bank_info(valid_mdata, valid_mdata->version, + num_banks, image, bank); + if (accept == bank_info->accepted) + return 0; + + if (accept) { + bank_info->accepted = FWU_IMAGE_ACCEPTED; + } else { + bank_info->accepted = 0; + + /* According to the spec: bank_state[index] have to be set + * to invalid before any content in the img_bank_info[index] + * is overwritten. + */ + if (valid_mdata->version == 2) { + struct fwu_mdata_ext *mdata_ext; + + mdata_ext = fwu_get_fw_mdata_ext(valid_mdata); + mdata_ext->bank_state[bank] = FWU_BANK_INVALID; + } + } + + mdata_mod = 1; + printf("Image %d in bank %d: acceptance %s\n", + image, bank, accept ? "set" : "cleared"); + + return 0; +} + +static int set_bank_state(int bank, const char *state_str) +{ + struct fwu_fw_store_desc *fw_desc; + struct fwu_mdata_ext *mdata_ext; + u8 state; + int i; + + if (valid_mdata->version != 2) { + fprintf(stderr, + "Error: Bank state is only supported in V2 metadata\n"); + return -EINVAL; + } + + fw_desc = fwu_get_fw_desc(valid_mdata); + mdata_ext = fwu_get_fw_mdata_ext(valid_mdata); + + if (bank < 0 || bank >= fw_desc->num_banks || bank >= MAX_BANKS_V2) { + fprintf(stderr, "Error: Invalid bank %d (must be 0-%d)\n", + bank, fw_desc->num_banks - 1); + return -EINVAL; + } + + /* Parse state string */ + if (!strcmp(state_str, "accepted")) { + state = FWU_BANK_ACCEPTED; + } else if (!strcmp(state_str, "valid")) { + state = FWU_BANK_VALID; + } else if (!strcmp(state_str, "invalid")) { + state = FWU_BANK_INVALID; + } else { + fprintf(stderr, + "Error: Invalid state '%s' (must be accepted/valid/invalid)\n", + state_str); + return -EINVAL; + } + + if (mdata_ext->bank_state[bank] == state) + return 0; + + /* If a bank is set in a accepted state all firmware images in + * that bank must be marked as accepted as described in the spec. + */ + if (state == FWU_BANK_ACCEPTED) { + for (i = 0; i < fw_desc->num_images; i++) { + int ret; + + ret = set_image_accepted(i, bank, true); + if (ret) + return ret; + } + } + mdata_ext->bank_state[bank] = state; + mdata_mod = 1; + + printf("Bank %d state set to %s (0x%02x)\n", bank, state_str, state); + return 0; +} + +static int metadata_v1_validate_size(void) +{ + int calc_size; + + calc_size = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * nbanks) * nimages; + + if (devices[0].mdata_size != calc_size) { + fprintf(stderr, + "Metadata calculate size (-B and -I options) 0x%x mismatch with the config 0x%zx\n", + calc_size, devices[0].mdata_size); + return -EINVAL; + } + + return 0; +} + +/* Command-line interface */ +static void print_usage(void) +{ + fprintf(stderr, "Usage: fwumdata [options]\n\n"); + fprintf(stderr, "Options:\n" + "\t-c, --config Use custom config file, defaults:\n" + "\t ./fwumdata.config or /etc/fwumdata.config\n" + "\t-l, --list List detailed metadata with GUIDs\n" + "\t-a, --active Set active bank index\n" + "\t-p, --previous Set previous bank index\n" + "\t-s, --state Set bank state (V2 only)\n" + "\t state: accepted|valid|invalid\n" + "\t-i, --image Image number (for -A/-C)\n" + "\t-b, --bank Bank number (for -A/-C)\n" + "\t-A, --accept Accept image (requires -i and -b)\n" + "\t-C, --clear Clear image acceptance (requires -i and -b)\n" + "\t-u, --update Update metadata if there is a checksum issue\n" + "\t-B, --nbanks Number of banks (required for V1 metadata)\n" + "\t-I, --nimages Number of images (required for V1 metadata)\n" + "\t-h, --help Print this help\n\n"); + fprintf(stderr, "Config file format (fwumdata.config):\n" + "\t# Device Name Device Offset Metadata Size Erase Size\n" + "\t/dev/mtd0 0x0 0x78 0x1000\n" + "\t/dev/mtd1 0x0 0x78 0x1000\n\n"); + fprintf(stderr, "Examples:\n" + "\tfwumdata # Print metadata summary\n" + "\tfwumdata -l # Print detailed metadata\n" + "\tfwumdata -a 1 # Set active bank to 1\n" + "\tfwumdata -s 1 accepted # Set bank 1 to accepted state\n" + "\tfwumdata -i 0 -b 0 -A # Accept image in bank 0\n" + "\tfwumdata -B 2 -I 2 -i 1 -b 1 -A -l # Accept image 1 in bank 1 with metadata V1\n"); +} + +int main(int argc, char *argv[]) +{ + char *bank_state_str = NULL; + bool list_detailed = false; + int bank_state_num = -1; + int active_index = -1; + int bank_id = -1; + int prev_index = -1; + bool do_accept = 0; + bool do_clear = 0; + bool do_update = 0; + int image_id = -1; + int ret = 0; + int opt; + + static struct option long_options[] = { + {"config", required_argument, 0, 'c'}, + {"list", no_argument, 0, 'l'}, + {"active", required_argument, 0, 'a'}, + {"previous", required_argument, 0, 'p'}, + {"state", required_argument, 0, 's'}, + {"image", required_argument, 0, 'i'}, + {"bank", required_argument, 0, 'b'}, + {"accept", no_argument, 0, 'A'}, + {"clear", no_argument, 0, 'C'}, + {"update", no_argument, 0, 'u'}, + {"nbanks", required_argument, 0, 'B'}, + {"nimages", required_argument, 0, 'I'}, + {"help", no_argument, 0, 'h'}, + {0, 0, 0, 0} + }; + + /* Parse arguments */ + while ((opt = getopt_long(argc, argv, "c:la:p:s:i:b:ACuB:I:h", long_options, NULL)) != -1) { + switch (opt) { + case 'c': + config_file = optarg; + break; + case 'l': + list_detailed = 1; + break; + case 'a': + active_index = atoi(optarg); + break; + case 'p': + prev_index = atoi(optarg); + break; + case 's': + bank_state_num = atoi(optarg); + if (optind < argc && argv[optind][0] != '-') { + bank_state_str = argv[optind++]; + } else { + fprintf(stderr, + "Error: -s requires bank number and state\n"); + return 1; + } + break; + case 'i': + image_id = atoi(optarg); + break; + case 'b': + bank_id = atoi(optarg); + break; + case 'A': + do_accept = 1; + break; + case 'C': + do_clear = 1; + break; + case 'u': + do_update = 1; + break; + case 'B': + nbanks = atoi(optarg); + break; + case 'I': + nimages = atoi(optarg); + break; + case 'h': + print_usage(); + return 0; + default: + print_usage(); + return 1; + } + } + + ret = find_parse_config(); + if (ret < 0) { + fprintf(stderr, "Error: Cannot read configuration\n"); + return ret; + } + + ret = read_metadata(do_update); + if (ret < 0) { + fprintf(stderr, "Error: Cannot read metadata\n"); + goto cleanup; + } + + if (valid_mdata->version == 1) { + ret = metadata_v1_validate_size(); + if (ret) + goto cleanup; + } + + /* Perform operations */ + if (active_index >= 0) { + ret = set_active_index(active_index); + if (ret < 0) + goto cleanup; + } + + if (prev_index >= 0) { + ret = set_previous_index(prev_index); + if (ret < 0) + goto cleanup; + } + + if (do_accept || do_clear) { + if (image_id < 0 || bank_id < 0) { + fprintf(stderr, + "Error: -A/-C requires both -i and -b \n"); + ret = -EINVAL; + goto cleanup; + } + + ret = set_image_accepted(image_id, bank_id, do_accept); + if (ret < 0) + goto cleanup; + } + + if (bank_state_num >= 0 && bank_state_str) { + ret = set_bank_state(bank_state_num, bank_state_str); + if (ret < 0) + goto cleanup; + } + + /* Write back if modified */ + if (mdata_mod) { + ret = write_metadata(); + if (ret) + goto cleanup; + } + + /* Display metadata if no modifications or list requested */ + if (list_detailed) + print_metadata_detailed(); + else + print_metadata_summary(); + +cleanup: + /* Close devices and free memory */ + if (devices[0].fd) + close(devices[0].fd); + if (devices[1].fd) + close(devices[1].fd); + + free(mdata); + + for (int i = 0; i < 2; i++) { + if (devices[i].devname) + free((void *)devices[i].devname); + } + + return ret; +} diff --git a/tools/fwumdata_src/fwumdata.config b/tools/fwumdata_src/fwumdata.config new file mode 100644 index 00000000000..7e83f7a5909 --- /dev/null +++ b/tools/fwumdata_src/fwumdata.config @@ -0,0 +1,33 @@ +# FWU Metadata Configuration File +# +# Format: +# +# This file describes where the FWU metadata is stored. You can specify +# up to two entries for redundant metadata copies. +# +# Device: MTD device (/dev/mtdX), block device (/dev/mmcblkX), or file path +# Offset: Byte offset from start of device (hex with 0x prefix) +# Metadata Size: Size of metadata structure in bytes (hex with 0x prefix) +# Erase Size: Sector/erase block size (hex with 0x prefix, defaults to +# metadata_size, required only for MTD device) +# +# Examples: +# +# MTD devices (NOR/NAND flash): +# /dev/mtd0 0x0 0x1000 0x1000 +# /dev/mtd1 0x0 0x1000 0x1000 +# +# Block device (eMMC/SD): +# /dev/mmcblk0 0x100000 0x78 +# /dev/mmcblk0 0x101000 0x78 +# +# or: +# /dev/disk/by-partlabel/metadata1 0 0x78 +# /dev/disk/by-partlabel/metadata2 0 0x78 +# +# Regular file: +# /boot/fwu-mdata.bin 0x0 0x78 +# +# Default configuration (update for your platform): +/dev/mtd0 0x0 0x78 0x1000 +/dev/mtd1 0x0 0x78 0x1000 diff --git a/tools/fwumdata_src/fwumdata.h b/tools/fwumdata_src/fwumdata.h new file mode 100644 index 00000000000..5e2c45d0fb0 --- /dev/null +++ b/tools/fwumdata_src/fwumdata.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2025, Kory Maincent + */ + +#ifndef _FWUMDATA_H_ +#define _FWUMDATA_H_ + +#include + +/* Type definitions for U-Boot compatibility */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +/* FWU Constants */ +#define FWU_IMAGE_ACCEPTED 0x1 +#define FWU_BANK_INVALID (uint8_t)0xFF +#define FWU_BANK_VALID (uint8_t)0xFE +#define FWU_BANK_ACCEPTED (uint8_t)0xFC +#define MAX_BANKS_V2 4 + +/* EFI GUID structure */ +struct efi_guid { + u32 time_high; + u16 time_low; + u16 reserved; + u8 family; + u8 node[7]; +} __packed; + +/* FWU Metadata structures */ +struct fwu_image_bank_info { + struct efi_guid image_guid; + u32 accepted; + u32 reserved; +} __packed; + +struct fwu_image_entry { + struct efi_guid image_type_guid; + struct efi_guid location_guid; + struct fwu_image_bank_info img_bank_info[0]; /* Variable length */ +} __packed; + +struct fwu_fw_store_desc { + u8 num_banks; + u8 reserved; + u16 num_images; + u16 img_entry_size; + u16 bank_info_entry_size; + struct fwu_image_entry img_entry[0]; /* Variable length */ +} __packed; + +struct fwu_mdata { + u32 crc32; + u32 version; + u32 active_index; + u32 previous_active_index; + /* Followed by image entries or fwu_mdata_ext */ +} __packed; + +struct fwu_mdata_ext { /* V2 only */ + u32 metadata_size; + u16 desc_offset; + u16 reserved1; + u8 bank_state[4]; + u32 reserved2; +} __packed; + +/* Metadata access helpers */ +struct fwu_image_entry *fwu_get_image_entry(struct fwu_mdata *mdata, + int version, int num_banks, + int img_id) +{ + size_t offset; + + if (version == 1) { + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * num_banks) * img_id; + } else { + /* V2: skip fwu_fw_store_desc header */ + offset = sizeof(struct fwu_mdata) + + sizeof(struct fwu_mdata_ext) + + sizeof(struct fwu_fw_store_desc) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * num_banks) * img_id; + } + + return (struct fwu_image_entry *)((char *)mdata + offset); +} + +struct fwu_image_bank_info *fwu_get_bank_info(struct fwu_mdata *mdata, + int version, int num_banks, + int img_id, int bank_id) +{ + size_t offset; + + if (version == 1) { + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * num_banks) * img_id + + sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * bank_id; + } else { + offset = sizeof(struct fwu_mdata) + + sizeof(struct fwu_mdata_ext) + + sizeof(struct fwu_fw_store_desc) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * num_banks) * img_id + + sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * bank_id; + } + + return (struct fwu_image_bank_info *)((char *)mdata + offset); +} + +struct fwu_fw_store_desc *fwu_get_fw_desc(struct fwu_mdata *mdata) +{ + size_t offset; + + offset = sizeof(struct fwu_mdata) + + sizeof(struct fwu_mdata_ext); + + return (struct fwu_fw_store_desc *)((char *)mdata + offset); +} + +struct fwu_mdata_ext *fwu_get_fw_mdata_ext(struct fwu_mdata *mdata) +{ + size_t offset; + + offset = sizeof(struct fwu_mdata); + + return (struct fwu_mdata_ext *)((char *)mdata + offset); +} + +#endif /* _FWUMDATA_H_ */ diff --git a/tools/fwumdata_src/fwumdata.mk b/tools/fwumdata_src/fwumdata.mk new file mode 100644 index 00000000000..e91d72bf3e8 --- /dev/null +++ b/tools/fwumdata_src/fwumdata.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2025, Kory Maincent + +mkfwumdata-objs := fwumdata_src/mkfwumdata.o generated/lib/crc32.o +HOSTLDLIBS_mkfwumdata += -luuid +hostprogs-always-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata + +fwumdata-objs := fwumdata_src/fwumdata.o generated/lib/crc32.o +hostprogs-always-$(CONFIG_TOOLS_FWUMDATA) += fwumdata diff --git a/tools/mkfwumdata.c b/tools/fwumdata_src/mkfwumdata.c similarity index 79% rename from tools/mkfwumdata.c rename to tools/fwumdata_src/mkfwumdata.c index fbc2067bc12..b8b60473b91 100644 --- a/tools/mkfwumdata.c +++ b/tools/fwumdata_src/mkfwumdata.c @@ -17,26 +17,7 @@ #include #include -typedef uint8_t u8; -typedef int16_t s16; -typedef uint16_t u16; -typedef uint32_t u32; -typedef uint64_t u64; - -#undef CONFIG_FWU_NUM_BANKS -#undef CONFIG_FWU_NUM_IMAGES_PER_BANK - -/* This will dynamically allocate the fwu_mdata */ -#define CONFIG_FWU_NUM_BANKS 0 -#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0 - -/* version 2 supports maximum of 4 banks */ -#define MAX_BANKS_V2 4 - -#define BANK_INVALID (u8)0xFF -#define BANK_ACCEPTED (u8)0xFC - -#include +#include "fwumdata.h" static const char *opts_short = "b:i:a:p:v:V:gh"; @@ -116,6 +97,7 @@ static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks, sizeof(struct fwu_image_bank_info) * banks) * images; } else { mobj->size = sizeof(struct fwu_mdata) + + sizeof(struct fwu_mdata_ext) + sizeof(struct fwu_fw_store_desc) + (sizeof(struct fwu_image_entry) + sizeof(struct fwu_image_bank_info) * banks) * images; @@ -146,50 +128,6 @@ alloc_err: return NULL; } -static struct fwu_image_entry * -fwu_get_image(struct fwu_mdata_object *mobj, size_t idx) -{ - size_t offset; - - if (mobj->version == 1) { - offset = sizeof(struct fwu_mdata) + - (sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * mobj->banks) * - idx; - } else { - offset = sizeof(struct fwu_mdata) + - sizeof(struct fwu_fw_store_desc) + - (sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * mobj->banks) * - idx; - } - - return (struct fwu_image_entry *)((char *)mobj->mdata + offset); -} - -static struct fwu_image_bank_info * -fwu_get_bank(struct fwu_mdata_object *mobj, size_t img_idx, size_t bnk_idx) -{ - size_t offset; - - if (mobj->version == 1) { - offset = sizeof(struct fwu_mdata) + - (sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * mobj->banks) * - img_idx + sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * bnk_idx; - } else { - offset = sizeof(struct fwu_mdata) + - sizeof(struct fwu_fw_store_desc) + - (sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * mobj->banks) * - img_idx + sizeof(struct fwu_image_entry) + - sizeof(struct fwu_image_bank_info) * bnk_idx; - } - - return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset); -} - /** * convert_uuid_to_guid() - convert UUID to GUID * @buf: UUID binary @@ -239,11 +177,13 @@ static int fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, size_t idx, char *uuids) { - struct fwu_image_entry *image = fwu_get_image(mobj, idx); struct fwu_image_bank_info *bank; + struct fwu_image_entry *image; char *p = uuids, *uuid; int i; + image = fwu_get_image_entry(mobj->mdata, mobj->version, + mobj->banks, idx); if (!image) return -ENOENT; @@ -266,7 +206,8 @@ fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, /* Fill bank image-UUID */ for (i = 0; i < mobj->banks; i++) { - bank = fwu_get_bank(mobj, idx, i); + bank = fwu_get_bank_info(mobj->mdata, mobj->version, + mobj->banks, idx, i); if (!bank) return -ENOENT; bank->accepted = 1; @@ -281,25 +222,22 @@ fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, return 0; } -#if defined(CONFIG_FWU_MDATA_V1) -static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj) -{ -} -#else static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj) { int i; struct fwu_fw_store_desc *fw_desc; - struct fwu_mdata *mdata = mobj->mdata; + struct fwu_mdata_ext *mdata_ext; - mdata->metadata_size = mobj->size; - mdata->desc_offset = sizeof(struct fwu_mdata); + mdata_ext = fwu_get_fw_mdata_ext(mobj->mdata); + mdata_ext->metadata_size = mobj->size; + mdata_ext->desc_offset = sizeof(struct fwu_mdata) + + sizeof(struct fwu_mdata_ext); for (i = 0; i < MAX_BANKS_V2; i++) - mdata->bank_state[i] = i < mobj->banks ? - BANK_ACCEPTED : BANK_INVALID; + mdata_ext->bank_state[i] = i < mobj->banks ? + FWU_BANK_ACCEPTED : FWU_BANK_INVALID; - fw_desc = (struct fwu_fw_store_desc *)((u8 *)mdata + sizeof(*mdata)); + fw_desc = fwu_get_fw_desc(mobj->mdata); fw_desc->num_banks = mobj->banks; fw_desc->num_images = mobj->images; fw_desc->img_entry_size = sizeof(struct fwu_image_entry) + @@ -307,7 +245,6 @@ static void fwu_fill_version_specific_mdata(struct fwu_mdata_object *mobj) fw_desc->bank_info_entry_size = sizeof(struct fwu_image_bank_info); } -#endif /* CONFIG_FWU_MDATA_V1 */ /* Caller must ensure that @uuids[] has @mobj->images entries. */ static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) @@ -320,7 +257,8 @@ static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) mdata->active_index = active_bank; mdata->previous_active_index = previous_bank; - fwu_fill_version_specific_mdata(mobj); + if (mdata->version == 2) + fwu_fill_version_specific_mdata(mobj); for (i = 0; i < mobj->images; i++) { ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]); @@ -471,9 +409,17 @@ int main(int argc, char *argv[]) return -EINVAL; } + if (version == 2 && banks > MAX_BANKS_V2) { + fprintf(stderr, "Error: Version 2 supports maximum %d banks, %ld requested.\n", + MAX_BANKS_V2, banks); + return -EINVAL; + } + /* This command takes UUIDs * images and output file. */ if (optind + images + 1 != argc) { - fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n"); + fprintf(stderr, + "Error: Expected %ld UUID string(s) and 1 output file, got %d argument(s).\n", + images, argc - optind); print_usage(); return -ERANGE; } diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index 0f41cdb64f5..ec640c57e8a 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -56,6 +56,7 @@ static struct option options[] = { {"fw-revert", no_argument, NULL, 'R'}, {"capoemflag", required_argument, NULL, 'o'}, {"dump-capsule", no_argument, NULL, 'D'}, + {"dump-sig", no_argument, NULL, 'd'}, {"help", no_argument, NULL, 'h'}, {NULL, 0, NULL, 0}, }; @@ -83,7 +84,7 @@ static void print_usage_mkeficapsule(void) "\t-p, --private-key private key file\n" "\t-c, --certificate signer's certificate file\n" "\t-m, --monotonic-count monotonic count\n" - "\t-d, --dump_sig dump signature (*.p7)\n" + "\t-d, --dump-sig dump signature to .p7\n" "\t-A, --fw-accept firmware accept capsule, requires GUID, no image blob\n" "\t-R, --fw-revert firmware revert capsule, takes no GUID, no image blob\n" "\t-o, --capoemflag Capsule OEM Flag, an integer between 0x0000 and 0xffff\n" @@ -228,21 +229,54 @@ static int create_auth_data(struct auth_context *ctx) gnutls_pkcs7_t pkcs7; gnutls_datum_t data; gnutls_datum_t signature; + gnutls_pkcs11_obj_t *obj_list; + unsigned int obj_list_size = 0; + const char *lib; int ret; + bool pkcs11_cert = false; + bool pkcs11_key = false; - ret = read_bin_file(ctx->cert_file, &cert.data, &file_size); - if (ret < 0) - return -1; - if (file_size > UINT_MAX) - return -1; - cert.size = file_size; + if (!strncmp(ctx->cert_file, "pkcs11:", strlen("pkcs11:"))) + pkcs11_cert = true; - ret = read_bin_file(ctx->key_file, &key.data, &file_size); - if (ret < 0) - return -1; - if (file_size > UINT_MAX) - return -1; - key.size = file_size; + if (!strncmp(ctx->key_file, "pkcs11:", strlen("pkcs11:"))) + pkcs11_key = true; + + if (pkcs11_cert || pkcs11_key) { + lib = getenv("PKCS11_MODULE_PATH"); + if (!lib) { + fprintf(stdout, + "PKCS11_MODULE_PATH not set in the environment\n"); + return -1; + } + + gnutls_pkcs11_init(GNUTLS_PKCS11_FLAG_MANUAL, NULL); + gnutls_global_init(); + + ret = gnutls_pkcs11_add_provider(lib, "trusted"); + if (ret < 0) { + fprintf(stdout, "Failed to add pkcs11 provider\n"); + return -1; + } + } + + if (!pkcs11_cert) { + ret = read_bin_file(ctx->cert_file, &cert.data, &file_size); + if (ret < 0) + return -1; + if (file_size > UINT_MAX) + return -1; + cert.size = file_size; + } + + if (!pkcs11_key) { + ret = read_bin_file(ctx->key_file, &key.data, &file_size); + if (ret < 0) + return -1; + if (file_size > UINT_MAX) + return -1; + key.size = file_size; + } /* * For debugging, @@ -265,22 +299,42 @@ static int create_auth_data(struct auth_context *ctx) return -1; } - /* load a private key */ - ret = gnutls_privkey_import_x509_raw(pkey, &key, GNUTLS_X509_FMT_PEM, - 0, 0); - if (ret < 0) { - fprintf(stderr, - "error in gnutls_privkey_import_x509_raw(): %s\n", - gnutls_strerror(ret)); - return -1; + /* load x509 certificate */ + if (pkcs11_cert) { + ret = gnutls_pkcs11_obj_list_import_url4(&obj_list, &obj_list_size, + ctx->cert_file, 0); + if (ret < 0 || obj_list_size == 0) { + fprintf(stdout, "Failed to import crt_file URI objects\n"); + return -1; + } + + gnutls_x509_crt_import_pkcs11(x509, obj_list[0]); + } else { + ret = gnutls_x509_crt_import(x509, &cert, GNUTLS_X509_FMT_PEM); + if (ret < 0) { + fprintf(stderr, "error in gnutls_x509_crt_import(): %s\n", + gnutls_strerror(ret)); + return -1; + } } - /* load x509 certificate */ - ret = gnutls_x509_crt_import(x509, &cert, GNUTLS_X509_FMT_PEM); - if (ret < 0) { - fprintf(stderr, "error in gnutls_x509_crt_import(): %s\n", - gnutls_strerror(ret)); - return -1; + /* load a private key */ + if (pkcs11_key) { + ret = gnutls_privkey_import_pkcs11_url(pkey, ctx->key_file); + if (ret < 0) { + fprintf(stderr, "error in %d: %s\n", __LINE__, + gnutls_strerror(ret)); + return -1; + } + } else { + ret = gnutls_privkey_import_x509_raw(pkey, &key, GNUTLS_X509_FMT_PEM, + 0, 0); + if (ret < 0) { + fprintf(stderr, + "error in gnutls_privkey_import_x509_raw(): %s\n", + gnutls_strerror(ret)); + return -1; + } } /* generate a PKCS #7 structure */ @@ -349,6 +403,11 @@ static int create_auth_data(struct auth_context *ctx) * gnutls_free(signature.data); */ + if (pkcs11_cert || pkcs11_key) { + gnutls_global_deinit(); + gnutls_pkcs11_deinit(); + } + return 0; } diff --git a/tools/rkcommon.c b/tools/rkcommon.c index e7e78ef7e5b..cb2d30bfd57 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -148,12 +148,13 @@ static struct spl_info spl_infos[] = { { "rk3328", "RK32", 0x8000 - 0x800, false, RK_HEADER_V1 }, { "rk3368", "RK33", 0x8000 - 0x1000, false, RK_HEADER_V1 }, { "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 }, - { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 }, - { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 }, + { "rk3506", "RK35", 0xC000 - 0x1000, false, RK_HEADER_V2 }, { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 }, { "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 }, { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 }, { "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 }, + { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 }, + { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 }, }; /** diff --git a/tools/u_boot_pylib/test_util.py b/tools/u_boot_pylib/test_util.py index d258a1935c9..364596d7a0c 100644 --- a/tools/u_boot_pylib/test_util.py +++ b/tools/u_boot_pylib/test_util.py @@ -24,7 +24,7 @@ except: def run_test_coverage(prog, filter_fname, exclude_list, build_dir, required=None, extra_args=None, single_thread='-P1', - args=None, allow_failures=None): + args=None): """Run tests and check that we get 100% coverage Args: @@ -95,19 +95,6 @@ def run_test_coverage(prog, filter_fname, exclude_list, build_dir, print('Coverage error: %s, but should be 100%%' % coverage) ok = False if not ok: - if allow_failures: - # for line in lines: - # print('.', line, re.match(r'^(tools/.*py) *\d+ *(\d+) *(\d+)%$', line)) - lines = [re.match(r'^(tools/.*py) *\d+ *(\d+) *\d+%$', line) - for line in stdout.splitlines()] - bad = [] - for mat in lines: - if mat and mat.group(2) != '0': - fname = mat.group(1) - if fname not in allow_failures: - bad.append(fname) - if not bad: - return raise ValueError('Test coverage failure')