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arch: bcm281xx: Initial commit of bcm281xx architecture code

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Add bcm281xx architecture support code including a clock framework and
chip reset.  Define register block base addresses for the bcm281xx
architecture and create an empty gpio header file required when
CONFIG_CMD_GPIO is set.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
This commit is contained in:
Darwin Rambo
2014-02-11 11:06:34 -08:00
committed by Albert ARIBAUD
parent b3134fce89
commit 989ce04999
10 changed files with 1792 additions and 0 deletions
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15
arch/arm/include/asm/arch-bcm281xx/gpio.h Normal file
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/*
* Copyright 2013 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ARCH_BCM281XX_GPIO_H
#define __ARCH_BCM281XX_GPIO_H
/*
* Empty file - cmd_gpio.c requires this. The implementation
* is in drivers/gpio/kona_gpio.c instead of inlined here.
*/
#endif

25
arch/arm/include/asm/arch-bcm281xx/sysmap.h Normal file
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/*
* Copyright 2013 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ARCH_BCM281XX_SYSMAP_H
#define BSC1_BASE_ADDR 0x3e016000
#define BSC2_BASE_ADDR 0x3e017000
#define BSC3_BASE_ADDR 0x3e018000
#define GPIO2_BASE_ADDR 0x35003000
#define KONA_MST_CLK_BASE_ADDR 0x3f001000
#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
#define PMU_BSC_BASE_ADDR 0x3500d000
#define PWRMGR_BASE_ADDR 0x35010000
#define SDIO1_BASE_ADDR 0x3f180000
#define SDIO2_BASE_ADDR 0x3f190000
#define SDIO3_BASE_ADDR 0x3f1a0000
#define SDIO4_BASE_ADDR 0x3f1b0000
#define SECWD_BASE_ADDR 0x3500c000
#define SECWD2_BASE_ADDR 0x35002f40
#define TIMER_BASE_ADDR 0x3e00d000
#endif