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mx7ulp: Select the SCG1 APLL PFD as a system clock source

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Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
2019-05-15 09:56:59 +00:00
committed by Stefano Babic
parent 285aea01d2
commit 9c1563e3fd
2 changed files with 2 additions and 2 deletions
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2
board/freescale/mx7ulp_evk/plugin.S
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@@ -18,7 +18,7 @@
ldr r3, =0x80808080
str r3, [r2, #0x50c]
ldr r3, =0x00160000
ldr r3, =0x00160002
str r3, [r2, #0x508]
ldr r3, =0x00000002
str r3, [r2, #0x510]