riscv: Add AST2700 SoC initial platform support

AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.

This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Chia-Wei Wang
2024-09-10 17:39:16 +08:00
committed by Leo Yu-Chi Liang
parent 717002f8ff
commit 9efcb10a09
20 changed files with 728 additions and 0 deletions

View File

@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) Aspeed Technology Inc.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
#define CFG_SYS_SDRAM_BASE 0x80000000
#endif /* __CONFIG_H */