diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index 5e777a1f305..0499c719396 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -9,6 +9,11 @@ #include "k3-binman.dtsi" #ifdef CONFIG_TARGET_PHYCORE_AM62X_R5 + +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62x-hs-phycore-som.bin { filename = "tiboot3-am62x-hs-phycore-som.bin"; diff --git a/board/phytec/phycore_am62x/tifs-rm-cfg.yaml b/board/phytec/phycore_am62x/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..8510fe9526e --- /dev/null +++ b/board/phytec/phycore_am62x/tifs-rm-cfg.yaml @@ -0,0 +1,867 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62X +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 824 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1677 + host_id: 128 + reserved: 0 + - + start_resource: 54 + num_resource: 18 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 35 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 78 + num_resource: 2 + type: 1678 + host_id: 30 + reserved: 0 + - + start_resource: 80 + num_resource: 2 + type: 1678 + host_id: 128 + reserved: 0 + - + start_resource: 32 + num_resource: 12 + type: 1679 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 36 + reserved: 0 + - + start_resource: 50 + num_resource: 2 + type: 1679 + host_id: 30 + reserved: 0 + - + start_resource: 52 + num_resource: 2 + type: 1679 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1696 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1696 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1696 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1697 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1697 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 2 + type: 1697 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 12 + type: 1698 + host_id: 12 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 35 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 36 + reserved: 0 + - + start_resource: 18 + num_resource: 2 + type: 1698 + host_id: 30 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 1698 + host_id: 128 + reserved: 0 + - + start_resource: 5 + num_resource: 35 + type: 1802 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 35 + type: 1802 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 35 + type: 1802 + host_id: 36 + reserved: 0 + - + start_resource: 168 + num_resource: 7 + type: 1802 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 1024 + type: 1807 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 29 + type: 1808 + host_id: 128 + reserved: 0 + - + start_resource: 4608 + num_resource: 99 + type: 1809 + host_id: 128 + reserved: 0 + - + start_resource: 5120 + num_resource: 24 + type: 1810 + host_id: 128 + reserved: 0 + - + start_resource: 5632 + num_resource: 51 + type: 1811 + host_id: 128 + reserved: 0 + - + start_resource: 6144 + num_resource: 51 + type: 1812 + host_id: 128 + reserved: 0 + - + start_resource: 6656 + num_resource: 51 + type: 1813 + host_id: 128 + reserved: 0 + - + start_resource: 8192 + num_resource: 32 + type: 1814 + host_id: 128 + reserved: 0 + - + start_resource: 8704 + num_resource: 32 + type: 1815 + host_id: 128 + reserved: 0 + - + start_resource: 9216 + num_resource: 32 + type: 1816 + host_id: 128 + reserved: 0 + - + start_resource: 9728 + num_resource: 22 + type: 1817 + host_id: 128 + reserved: 0 + - + start_resource: 10240 + num_resource: 22 + type: 1818 + host_id: 128 + reserved: 0 + - + start_resource: 10752 + num_resource: 22 + type: 1819 + host_id: 128 + reserved: 0 + - + start_resource: 11264 + num_resource: 28 + type: 1820 + host_id: 128 + reserved: 0 + - + start_resource: 11776 + num_resource: 28 + type: 1821 + host_id: 128 + reserved: 0 + - + start_resource: 12288 + num_resource: 28 + type: 1822 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1936 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1936 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1936 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 36 + reserved: 0 + - + start_resource: 83 + num_resource: 8 + type: 1938 + host_id: 12 + reserved: 0 + - + start_resource: 91 + num_resource: 8 + type: 1939 + host_id: 12 + reserved: 0 + - + start_resource: 99 + num_resource: 10 + type: 1942 + host_id: 12 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 35 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 36 + reserved: 0 + - + start_resource: 112 + num_resource: 3 + type: 1942 + host_id: 30 + reserved: 0 + - + start_resource: 115 + num_resource: 3 + type: 1942 + host_id: 128 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 36 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1944 + host_id: 12 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1945 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1946 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1947 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1955 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1955 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1955 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 36 + reserved: 0 + - + start_resource: 27 + num_resource: 1 + type: 1957 + host_id: 12 + reserved: 0 + - + start_resource: 28 + num_resource: 1 + type: 1958 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1961 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1961 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1961 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1962 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1962 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1962 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 36 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 36 + reserved: 0 + - + start_resource: 20 + num_resource: 1 + type: 1965 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1966 + host_id: 12 + reserved: 0 + - + start_resource: 21 + num_resource: 1 + type: 1967 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1968 + host_id: 12 + reserved: 0 + - + start_resource: 22 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 diff --git a/board/phytec/phycore_am68x/rm-cfg.yaml b/board/phytec/phycore_am68x/rm-cfg.yaml index 8796463129d..728bfe241a4 100644 --- a/board/phytec/phycore_am68x/rm-cfg.yaml +++ b/board/phytec/phycore_am68x/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J721S2 # @@ -429,24 +429,24 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 100 + num_resource: 98 type: 14528 host_id: 12 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 32 type: 14528 host_id: 13 reserved: 0 - - start_resource: 142 + start_resource: 140 num_resource: 21 type: 14528 host_id: 21 reserved: 0 - - start_resource: 163 + start_resource: 161 num_resource: 21 type: 14528 host_id: 23 @@ -1431,7 +1431,7 @@ rm-cfg: reserved: 0 - start_resource: 236 - num_resource: 20 + num_resource: 18 type: 16970 host_id: 128 reserved: 0 @@ -1497,7 +1497,7 @@ rm-cfg: reserved: 0 - start_resource: 3426 - num_resource: 1182 + num_resource: 1180 type: 16973 host_id: 128 reserved: 0 diff --git a/doc/board/phytec/k3-common.rst b/doc/board/phytec/k3-common.rst index ffb50b51ad6..3adb176ea8a 100644 --- a/doc/board/phytec/k3-common.rst +++ b/doc/board/phytec/k3-common.rst @@ -1,6 +1,53 @@ .. SPDX-License-Identifier: GPL-2.0+ .. sectionauthor:: Wadim Egorov +Boot Flow +--------- + +The default `bootcmd` performs three steps: + +.. code-block:: + + run start_watchdog; bootflow scan -lb; run ${boot}boot + +Boot devices are scanned in the order given by `boot_targets`: + +.. code-block:: + + mmc1 mmc0 spi_flash dhcp + +For each device, U-Boot tries the boot methods listed in `bootmeths`: + +.. code-block:: + + [rauc] script efi extlinux pxe + +The `rauc` bootmeth is only present when `CONFIG_BOOTMETH_RAUC=y` is set in +the A53 defconfig. RAUC slot selection is handled entirely by the bootmeth; +no environment-side configuration is required. + +The legacy `${boot}boot` chain (`mmcboot`, `spiboot`, `netboot`) is kept for +backwards compatibility and prints a deprecation warning when run. New +deployments should rely on the standard boot mechanism (`bootflow`) only. + + +Watchdog +-------- + +`bootcmd` runs `start_watchdog` before starting the boot flow. When +`CONFIG_WATCHDOG_TIMEOUT_MSECS` is set to a non-zero value and the +`watchdog` environment variable points to a watchdog device, U-Boot enables +the watchdog with that timeout. + +After this point the OS is responsible for servicing the watchdog. If it +does not feed the watchdog before the timeout expires, the SoC will reset. +Make sure the watchdog driver is enabled and configured in the kernel and +userspace before relying on this. + +To skip the watchdog start, either build with `CONFIG_WATCHDOG_TIMEOUT_MSECS=0` +or set `watchdog_timeout_ms=0` in the environment. + + Environment ----------- diff --git a/doc/board/phytec/phycore-am62ax.rst b/doc/board/phytec/phycore-am62ax.rst index e1f741011e7..aa3518a07ff 100644 --- a/doc/board/phytec/phycore-am62ax.rst +++ b/doc/board/phytec/phycore-am62ax.rst @@ -9,7 +9,7 @@ SoM (System on Module) featuring TI's AM62Ax SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62Ax family. -A development Kit, called `phyBOARD-Lyra `_ +A development Kit, called `phyBOARD-Lyra `_ is used as a carrier board reference design around the AM62Ax SoM. Quickstart @@ -57,10 +57,10 @@ Set the variables corresponding to this platform: $ export UBOOT_CFG_CORTEXR=phycore_am62ax_r5_defconfig $ export UBOOT_CFG_CORTEXA=phycore_am62ax_a53_defconfig $ export TFA_BOARD=lite - $ # we dont use any extra TFA parameters + $ # we don't use any extra TFA parameters $ unset TFA_EXTRA_ARGS $ export OPTEE_PLATFORM=k3-am62ax - $ # we dont use any extra OPTEE parameters + $ # we don't use any extra OPTEE parameters $ unset OPTEE_EXTRA_ARGS 1. Trusted Firmware-A: @@ -147,7 +147,7 @@ the main domain serial port: Boot Modes ---------- -The phyCORE-AM62x development kit supports booting from many different +The phyCORE-AM62Ax development kit supports booting from many different interfaces. By default, the development kit is set to boot from the micro-SD card. To change the boot device, DIP switches S5 and S6 can be used. Boot switches should be changed with power off. diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index bd61d0c16cf..5349ba429d4 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -60,7 +60,7 @@ Set the variables corresponding to this platform: $ # we don't use any extra TFA parameters $ unset TFA_EXTRA_ARGS $ export OPTEE_PLATFORM=k3-am62x - $ # we dont use any extra OPTEE parameters + $ # we don't use any extra OPTEE parameters $ unset OPTEE_EXTRA_ARGS .. include:: ../ti/am62x_sk.rst @@ -177,6 +177,25 @@ Boot switches should be changed with power off. - 11001010 - 00100000 +DDR RAM Size +------------ + +By default, the R5 SPL detects the populated DDR size by reading the SoM +EEPROM and configures the DDR controller and the U-Boot device-tree memory +node accordingly. The phyCORE-AM62x is available with 1 GB, 2 GB, or 4 GB of +DDR. If the EEPROM cannot be read or is invalid, the SPL falls back to a +2 GB configuration. + +EEPROM-based detection can be bypassed by enabling +`CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of: + +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB` +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB` +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB` + +This is mainly useful if no detection is needed or for boards without a +populated SoM EEPROM. + .. include:: k3-common.rst Further Information diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst index 71f1fd7b404..20887d443a9 100644 --- a/doc/board/phytec/phycore-am64x.rst +++ b/doc/board/phytec/phycore-am64x.rst @@ -60,8 +60,8 @@ Set the variables corresponding to this platform: $ # we don't use any extra TFA parameters $ unset TFA_EXTRA_ARGS $ export OPTEE_PLATFORM=k3-am64x - # we don't use any extra OPTEE parameters - unset OPTEE_EXTRA_ARGS + $ # we don't use any extra OPTEE parameters + $ unset OPTEE_EXTRA_ARGS .. include:: ../ti/am62x_sk.rst :start-after: .. am62x_evm_rst_include_start_build_steps @@ -148,7 +148,7 @@ Boot Modes The phyCORE-AM64x development kit supports booting from many different interfaces. By default, the development kit is set to boot from the micro-SD -card. To change the boot device, DIP switches S5 and S6 can be used. +card. To change the boot device, DIP switches SW3 and SW4 can be used. Boot switches should be changed with power off. .. list-table:: Boot Modes @@ -175,6 +175,24 @@ Boot switches should be changed with power off. - 11011100 - 00000000 +DDR RAM Size +------------ + +By default, the R5 SPL detects the populated DDR size by reading the SoM +EEPROM and configures the DDR controller and the U-Boot device-tree memory +node accordingly. The phyCORE-AM64x is available with 1 GB or 2 GB of DDR. +If the EEPROM cannot be read or is invalid, the SPL falls back to a 2 GB +configuration. + +EEPROM-based detection can be bypassed by enabling +`CONFIG_PHYCORE_AM64X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of: + +* `CONFIG_PHYCORE_AM64X_RAM_SIZE_1GB` +* `CONFIG_PHYCORE_AM64X_RAM_SIZE_2GB` + +This is mainly useful if no detection is needed or for boards without a +populated SoM EEPROM. + .. include:: k3-common.rst Further Information diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index 95d0204b6da..8129b35ea5e 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -7,15 +7,13 @@ /* Logic for TI K3 based SoCs to boot from a MMC device. */ #include -#include mmcargs=setenv bootargs console=${console} earlycon=${earlycon} - root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw + root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw ${optargs} mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} mmcboot=echo DEPRECATION WARNING: mmcboot will be removed in future versions. Use standard boot instead.; - if test ${doraucboot} = 1; then run raucinit; fi; run mmcargs; mmc dev ${mmcdev}; mmc rescan; diff --git a/include/env/phytec/rauc.env b/include/env/phytec/rauc.env deleted file mode 100644 index 89e17ff70ec..00000000000 --- a/include/env/phytec/rauc.env +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -/* Logic to select a boot partition based on environment variables and switch - * to the other if the boot fails. */ - -doraucboot=0 - -raucbootpart0=1 -raucrootpart0=5 -raucbootpart1=2 -raucrootpart1=6 - -raucinit= - echo Booting RAUC A/B system; - test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1"; - test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3; - test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3; - env set raucstatus; - for BOOT_SLOT in "${BOOT_ORDER}"; do - if test "x${raucstatus}" != "x"; then - echo Skipping remaing slots!; - elif test "x${BOOT_SLOT}" = "xsystem0"; then - if test ${BOOT_system0_LEFT} -gt 0; then - echo Found valid slot A, ${BOOT_system0_LEFT} attempts remaining; - setexpr BOOT_system0_LEFT ${BOOT_system0_LEFT} - 1; - env set mmcpart ${raucbootpart0}; - env set mmcroot ${raucrootpart0}; - env set raucargs rauc.slot=system0; - env set raucstatus success; - fi; - elif test "x${BOOT_SLOT}" = "xsystem1"; then - if test ${BOOT_system1_LEFT} -gt 0; then - echo Found valid slot B, ${BOOT_system1_LEFT} attempts remaining; - setexpr BOOT_system1_LEFT ${BOOT_system1_LEFT} - 1; - env set mmcpart ${raucbootpart1}; - env set mmcroot ${raucrootpart1}; - env set raucargs rauc.slot=system1; - env set raucstatus success; - fi; - fi; - done; - if test -n "${raucstatus}"; then - env delete raucstatus; - env save; - else - echo WARN: No valid slot found; - env set BOOT_system0_LEFT 3; - env set BOOT_system1_LEFT 3; - env delete raucstatus; - env save; - reset; - fi;