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video: tegra: parametrize PCLK and DE polarity

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Configure pixel clock and data enable polarity according to panel flags.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Svyatoslav Ryhel
2025-04-18 09:12:03 +03:00
parent d564f395bc
commit aa291c5f8b
2 changed files with 19 additions and 0 deletions
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3
arch/arm/include/asm/arch-tegra/dc.h
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@@ -448,6 +448,9 @@ enum win_color_depth_id {
#define LVS_OUTPUT_POLARITY_LOW BIT(28)
#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
/* DC_COM_PIN_OUTPUT_POLARITY3 0x309 */
#define LSPI_OUTPUT_POLARITY_LOW BIT(8)
/* DC_COM_PIN_OUTPUT_SELECT6 0x31a */
#define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */