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global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

Browse Source 
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini
2022-11-16 13:10:37 -05:00
parent aec118ebe6
commit aa6e94deab
589 changed files with 1197 additions and 1197 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
View File

@@ -29,7 +29,7 @@
*/
static void __secure ls1_save_ddr_head(void)
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
const char *src = (const char *)CFG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;

6
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@@ -1441,7 +1441,7 @@ int dram_init_banksize(void)
}
#endif
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
@@ -1571,7 +1571,7 @@ void update_early_mmu_table(void)
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_BASE,
gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@@ -1579,7 +1579,7 @@ void update_early_mmu_table(void)
PTE_TYPE_VALID);
} else {
mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |

4
arch/arm/dts/rockchip-optee.dtsi
View File

@@ -32,8 +32,8 @@
arch = "arm";
os = "tee";
compression = "none";
load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
blob-ext {
filename = "tee.bin";

2
arch/arm/include/asm/emif.h
View File

@@ -583,7 +583,7 @@
(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
(CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
(CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\

2
arch/arm/include/asm/iproc-common/configs.h
View File

@@ -12,6 +12,6 @@
#define CONFIG_IPROC
/* Memory Info */
#define CONFIG_SYS_SDRAM_BASE 0x61000000
#define CFG_SYS_SDRAM_BASE 0x61000000
#endif /* __IPROC_COMMON_CONFIGS_H */

2
arch/arm/mach-aspeed/ast2500/board_common.c
View File

@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
arch/arm/mach-aspeed/ast2600/board_common.c
View File

@@ -54,7 +54,7 @@ int board_init(void)
int i = 0, rc;
struct udevice *dev;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
while (1) {
rc = uclass_get_device(UCLASS_MISC, i++, &dev);

48
arch/arm/mach-at91/arm920t/lowlevel_init.S
View File

@@ -114,38 +114,38 @@ SMRDATA1:
.word CONFIG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CONFIG_SYS_SDRAM1
.word CONFIG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM1
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CONFIG_SYS_SDRAM
.word CONFIG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
SMRDATA1E:
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

48
arch/arm/mach-at91/arm926ejs/lowlevel_init.S
View File

@@ -201,38 +201,38 @@ SMRDATA1:
.word CONFIG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL1
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL2
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL3
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL4
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL5
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL6
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL7
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL8
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL9
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL3
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL4
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL5
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL6
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL7
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL8
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL10
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL11
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
.word CONFIG_SYS_SDRAM_BASE
.word CONFIG_SYS_SDRAM_VAL12
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL

4
arch/arm/mach-davinci/misc.c
View File

@@ -26,14 +26,14 @@ int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
(void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;

2
arch/arm/mach-exynos/dmc_init_ddr3.c
View File

@@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
* better have similar timings, since there's only a single adjustment that is
* shared by both chips).
*/
const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
const unsigned int test_addr = CFG_SYS_SDRAM_BASE;
/* Test pattern with which RAM will be tested */
static const unsigned int test_pattern[] = {

2
arch/arm/mach-imx/imx8m/soc.c
View File

@@ -178,7 +178,7 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void)
int i;
for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */

2
arch/arm/mach-imx/imx8ulp/soc.c
View File

@@ -373,7 +373,7 @@ static unsigned int imx8ulp_find_dram_entry_in_mem_map(void)
int i;
for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */

2
arch/arm/mach-imx/mx6/litesom.c
View File

@@ -172,7 +172,7 @@ static void spl_dram_init(void)
* Get actual RAM size, so we can adjust DDR row size for <512M
* memories
*/
ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M);
if (ram_size < SZ_512M) {
mem_ddr.rowaddr = 14;
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);

2
arch/arm/mach-imx/mx6/opos6ul.c
View File

@@ -44,7 +44,7 @@ static int setup_fec(void)
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec();

2
arch/arm/mach-imx/spl.c
View File

@@ -349,7 +349,7 @@ void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = imx_ddr_size();
return 0;

2
arch/arm/mach-k3/common.c
View File

@@ -561,7 +561,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
void spl_enable_dcache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
dram_init();

2
arch/arm/mach-k3/r5_mpu.c
View File

@@ -24,7 +24,7 @@ struct mpu_region_config k3_mpu_regions[16] = {
O_I_WB_RD_WR_ALLOC, REGION_8MB},
/* U-Boot's code area marking it as WB and Write allocate */
{CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
{CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_2GB},
/* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
{0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,

2
arch/arm/mach-keystone/ddr3.c
View File

@@ -318,7 +318,7 @@ void ddr3_init_ecc(u32 base, u32 ddr3_size)
}
ddr3_ecc_init_range(base);
ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)

4
arch/arm/mach-mediatek/mt7623/init.c
View File

@@ -25,7 +25,7 @@ int dram_init(void)
{
u32 i;
if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) &&
((size_t)preloader_param % sizeof(size_t) == 0) &&
preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
preloader_param->dram_rank_num <=
@@ -35,7 +35,7 @@ int dram_init(void)
for (i = 0; i < preloader_param->dram_rank_num; i++)
gd->ram_size += preloader_param->dram_rank_size[i];
} else {
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
SZ_2G);
}

2
arch/arm/mach-mediatek/mt7981/init.c
View File

@@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}

2
arch/arm/mach-mediatek/mt7986/init.c
View File

@@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
return 0;
}

6
arch/arm/mach-mvebu/alleycat5/cpu.c
View File

@@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
static struct mm_region ac5_mem_map[] = {
{
/* RAM */
.phys = CONFIG_SYS_SDRAM_BASE,
.virt = CONFIG_SYS_SDRAM_BASE,
.phys = CFG_SYS_SDRAM_BASE,
.virt = CFG_SYS_SDRAM_BASE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
@@ -102,7 +102,7 @@ int alleycat5_dram_init_banksize(void)
/*
* Config single DRAM bank
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;

2
arch/arm/mach-mvebu/arm64-common.c
View File

@@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE);
return (gd->ram_top > top) ? top : gd->ram_top;
}

2
arch/arm/mach-mvebu/armada8k/dram.c
View File

@@ -38,7 +38,7 @@ int a8k_dram_init_banksize(void)
*/
phys_size_t max_bank0_size = SZ_4G - SZ_1G;
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size <= max_bank0_size) {
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;

6
arch/arm/mach-omap2/am33xx/board.c
View File

@@ -72,14 +72,14 @@ int dram_init(void)
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
(void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
@@ -520,7 +520,7 @@ void board_init_f(ulong dummy)
sdram_init();
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
(void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
}
#endif

8
arch/arm/mach-omap2/emif-common.c
View File

@@ -389,7 +389,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
/* Set region1 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_1 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -400,7 +400,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
/* Set region2 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
rgn = rgn_start + CFG_SYS_SDRAM_BASE;
size = (regs->emif_ecc_address_range_2 &
EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
@@ -1340,7 +1340,7 @@ void dmm_init(u32 base)
mapped_size = 0;
section_cnt = 3;
sys_addr = CONFIG_SYS_SDRAM_BASE;
sys_addr = CFG_SYS_SDRAM_BASE;
emif1_size = get_emif_mem_size(EMIF1_BASE);
emif2_size = get_emif_mem_size(EMIF2_BASE);
debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
@@ -1568,7 +1568,7 @@ void sdram_init(void)
size_prog = log_2_n_round_down(size_prog);
size_prog = (1 << size_prog);
size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
size_prog);
/* Compare with the size programmed */
if (size_detect != size_prog) {

4
arch/arm/mach-omap2/sec-common.c
View File

@@ -198,11 +198,11 @@ u32 get_sec_mem_start(void)
*/
if (sec_mem_start == 0)
sec_mem_start =
(CONFIG_SYS_SDRAM_BASE + (
(CFG_SYS_SDRAM_BASE + (
#if defined(CONFIG_OMAP54XX)
omap_sdram_size()
#else
get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE)
#endif
- sec_mem_size));

2
arch/arm/mach-owl/soc.c
View File

@@ -50,7 +50,7 @@ int dram_init(void)
/* This is called after dram_init() so use get_ram_size result */
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;

16
arch/arm/mach-rockchip/sdram.c
View File

@@ -37,7 +37,7 @@ struct tos_parameter_t {
int dram_init_banksize(void)
{
size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE),
(unsigned long)(gd->ram_top));
#ifdef CONFIG_ARM64
@@ -48,26 +48,26 @@ int dram_init_banksize(void)
#ifdef CONFIG_SPL_OPTEE_IMAGE
struct tos_parameter_t *tos_parameter;
tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE +
TRUST_PARAMETER_OFFSET);
if (tos_parameter->tee_mem.flags == 1) {
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
- CONFIG_SYS_SDRAM_BASE;
- CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
} else {
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x2000000;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
}
#else
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
#endif
#endif
@@ -207,7 +207,7 @@ int dram_init(void)
phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
return (gd->ram_top > top) ? top : gd->ram_top;
}

2
arch/arm/mach-socfpga/board.c
View File

@@ -46,7 +46,7 @@ void s_init(void) {
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

8
arch/arm/mach-sunxi/dram_helpers.c
View File

@@ -33,11 +33,11 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val)
bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
writel(0, CFG_SYS_SDRAM_BASE);
writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
dsb();
/* Check if the same value is actually observed when reading back */
return readl(CONFIG_SYS_SDRAM_BASE) ==
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
return readl(CFG_SYS_SDRAM_BASE) ==
readl((ulong)CFG_SYS_SDRAM_BASE + offset);
}
#endif

20
arch/arm/mach-sunxi/dram_suniv.c
View File

@@ -175,9 +175,9 @@ static int sdr_readpipe_scan(void)
u32 k = 0;
for (k = 0; k < 32; k++)
writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k);
writel(k, CFG_SYS_SDRAM_BASE + 4 * k);
for (k = 0; k < 32; k++) {
if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k)
if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k)
return 0;
}
return 1;
@@ -266,11 +266,11 @@ static u32 dram_get_dram_size(struct dram_para *para)
dram_para_setup(para);
dram_scan_readpipe(para);
for (i = 0; i < 32; i++) {
*((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
*((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
*((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
*((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
}
for (i = 0; i < 32; i++) {
val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i));
val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i));
if (val1 == 0x22)
count++;
}
@@ -283,11 +283,11 @@ static u32 dram_get_dram_size(struct dram_para *para)
para->row_width = rowflag;
dram_para_setup(para);
if (colflag == 10) {
addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000;
addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000;
addr1 = CFG_SYS_SDRAM_BASE + 0x400000;
addr2 = CFG_SYS_SDRAM_BASE + 0xc00000;
} else {
addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000;
addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000;
addr1 = CFG_SYS_SDRAM_BASE + 0x200000;
addr2 = CFG_SYS_SDRAM_BASE + 0x600000;
}
for (i = 0; i < 32; i++) {
*((u8 *)(addr1 + i)) = 0x33;
@@ -319,7 +319,7 @@ static u32 dram_get_dram_size(struct dram_para *para)
static void simple_dram_check(void)
{
volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE;
volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE;
int i;
for (i = 0; i < 0x40; i++)

6
arch/arm/mach-sunxi/dram_sunxi_dw.c
View File

@@ -711,7 +711,7 @@ static unsigned long mctl_calc_rank_size(struct rank_para *rank)
*/
static void mctl_r40_detect_rank_count(struct dram_para *para)
{
ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE +
mctl_calc_rank_size(&para->ranks[0]);
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
@@ -744,10 +744,10 @@ static void mctl_r40_detect_rank_count(struct dram_para *para)
static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
{
mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, &para->ranks[0]);
mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, &para->ranks[0]);
if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(&para->ranks[0]), &para->ranks[1]);
mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(&para->ranks[0]), &para->ranks[1]);
}
}

4
arch/arm/mach-tegra/board2.c
View File

@@ -370,7 +370,7 @@ int dram_init_banksize(void)
/* fall back to default DRAM bank size computation */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
#ifdef CONFIG_PCI
@@ -412,5 +412,5 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size)
/* fall back to default usable RAM computation */
return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
}

2
arch/arm/mach-zynq/cpu.c
View File

@@ -54,7 +54,7 @@ int arch_cpu_init(void)
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
#if (CONFIG_SYS_SDRAM_BASE == 0)
#if (CFG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);