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powerpc, 8xx: Migrate to Kconfig
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
committed by
Tom Rini
parent
6f65e75a8a
commit
b1e41d1cee
15
README
15
README
@@ -324,9 +324,6 @@ The following options need to be configured:
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multiple fs option at one time
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for marvell soc family
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- 8xx CPU Options: (if using an MPC8xx CPU)
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CONFIG_8xx_GCLK_FREQ - CPU clock
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- 85xx CPU Options:
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CONFIG_SYS_PPC64
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@@ -3989,16 +3986,6 @@ Low Level (hardware related) configuration options:
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point to an otherwise UNUSED address space between
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the top of RAM and the start of the PCI space.
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- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
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- CONFIG_SYS_SYPCR: System Protection Control (11-9)
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- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
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- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
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- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
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- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
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- CONFIG_SYS_OR_TIMING_SDRAM:
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@@ -4007,8 +3994,6 @@ Low Level (hardware related) configuration options:
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- CONFIG_SYS_MAMR_PTA:
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periodic timer for refresh
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- CONFIG_SYS_DER: Debug Event Register (37-47)
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- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
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CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
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CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
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