mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx
Porting to DM and i.MX8 ------------------------ - warp7 to DM - kp_imx53 to DM - Warnings in DT - MX8QM support - colibri-imx6ull to DM - imx7d-pico to DM - ocotp for MX8
This commit is contained in:
Tom Rini
@@ -138,12 +138,12 @@
|
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x20000000\0" \
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"fdt_addr_r=0x12000000\0" \
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"fdt_addr_r=0x12100000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x11000000\0" \
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"pxefile_addr_r=0x17100000\0" \
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"ramdisk_addr_r=0x12100000\0" \
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"ramdisk_addr_r=0x12200000\0" \
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"scriptaddr=0x17000000\0"
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#define NFS_BOOTCMD \
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 Toradex AG
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* Copyright 2018-2019 Toradex AG
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*
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* Configuration settings for the Colibri iMX6ULL module.
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*
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@@ -19,10 +19,6 @@
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#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
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/* Network */
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_IP_DEFRAG
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#define CONFIG_TFTP_BLOCKSIZE 16352
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#define CONFIG_TFTP_TSIZE
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@@ -30,7 +26,7 @@
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/* ENET1 */
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#define IMX_FEC_BASE ENET2_BASE_ADDR
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/* MMC Config*/
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/* MMC Config */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_USDHC_NUM 1
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@@ -48,12 +44,12 @@
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"fdt_addr_r=0x82000000\0" \
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"fdt_addr_r=0x82100000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x81000000\0" \
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"pxefile_addr_r=0x87100000\0" \
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"ramdisk_addr_r=0x82100000\0" \
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"ramdisk_addr_r=0x82200000\0" \
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"scriptaddr=0x87000000\0"
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#define NFS_BOOTCMD \
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@@ -182,4 +178,4 @@
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#define CONFIG_VIDEO_BMP_LOGO
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#endif
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#endif
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#endif /* __COLIBRI_IMX6ULL_CONFIG_H */
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@@ -115,25 +115,31 @@
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"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
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#define EMMC_BOOTCMD \
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"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
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"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\
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"rw,noatime rootfstype=ext4 " \
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"rootwait\0" \
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"emmcboot=run setup; " \
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"emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
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"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
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"${vidargs}; echo Booting from internal eMMC chip...; " \
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"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
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"${boot_file} && run fdt_fixup && " \
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"run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \
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"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
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"bootz ${kernel_addr_r} ${dtbparam}\0" \
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"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
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"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
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"emmcbootpart=1\0" \
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"emmcdev=0\0" \
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"emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
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"${fdt_addr_r} ${fdt_file} && " \
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"setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \
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"emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
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"emmcrootpart=2\0"
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"fdt_addr_r=0x12000000\0" \
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"fdt_addr_r=0x12100000\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr_r=0x11000000\0" \
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"pxefile_addr_r=0x17100000\0" \
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"ramdisk_addr_r=0x12100000\0" \
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"ramdisk_addr_r=0x12200000\0" \
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"scriptaddr=0x17000000\0"
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#define NFS_BOOTCMD \
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@@ -147,27 +153,40 @@
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"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
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#define SD_BOOTCMD \
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"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
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"rootwait\0" \
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"sdboot=run setup; " \
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"set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw,noatime " \
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"rootfstype=ext4 rootwait\0" \
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"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
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"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
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"${vidargs}; echo Booting from SD card; " \
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"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
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"${boot_file} && run fdt_fixup && " \
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"run sddtbload; load mmc ${sddev}:${sdbootpart} "\
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"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
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"bootz ${kernel_addr_r} ${dtbparam}\0" \
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"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
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"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
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"sdbootpart=1\0" \
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"sddev=1\0" \
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"sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
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"${fdt_addr_r} ${fdt_file} && setenv dtbparam \" - " \
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"${fdt_addr_r}\" && true\0" \
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"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
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"sdrootpart=2\0"
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#define USB_BOOTCMD \
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"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
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"rootwait\0" \
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"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
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"set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \
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"rootfstype=ext4 rootwait\0" \
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"usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
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"setenv bootargs ${defargs} ${setupargs} " \
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"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
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"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
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"run usbdtbload; " \
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"load usb ${usbdev}:${usbbootpart} ${kernel_addr_r} " \
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"${boot_file} && run fdt_fixup && " \
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"bootz ${kernel_addr_r} ${dtbparam}\0" \
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"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
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"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
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"usbbootpart=1\0" \
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"usbdev=0\0" \
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"usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
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"${fdt_addr_r} " \
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"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && " \
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"true\0" \
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"usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
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"usbrootpart=2\0"
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#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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@@ -186,6 +205,7 @@
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MEM_LAYOUT_ENV_SETTINGS \
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NFS_BOOTCMD \
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SD_BOOTCMD \
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USB_BOOTCMD \
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"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
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"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
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"flash_eth.img && source ${loadaddr}\0" \
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131
include/configs/dart_6ul.h
Normal file
131
include/configs/dart_6ul.h
Normal file
@@ -0,0 +1,131 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Board configuration file for Variscite DART-6UL Evaluation Kit
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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*/
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#ifndef __DART_6UL_H
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#define __DART_6UL_H
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#include <linux/sizes.h>
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#include "mx6_common.h"
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/* SPL options */
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#include "imx6_spl.h"
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/* NAND pin conflicts with usdhc2 */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_FSL_USDHC_NUM 1
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#else
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#endif
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_ENET_DEV 0
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#if (CONFIG_FEC_ENET_DEV == 0)
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "eth0"
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#elif (CONFIG_FEC_ENET_DEV == 1)
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#define IMX_FEC_BASE ENET2_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x3
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "eth1"
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#endif
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#endif
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
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/* Environment settings */
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#define CONFIG_ENV_SIZE SZ_8K
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#define CONFIG_ENV_OFFSET (14 * SZ_64K)
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_ENV_OFFSET_REDUND \
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(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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/* Environment in SD */
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_PART 0
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#define MMC_ROOTFS_DEV 0
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#define MMC_ROOTFS_PART 2
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/* Console configs */
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/* MMC Configs */
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
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#define CONFIG_SUPPORT_EMMC_BOOT
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/* I2C configs */
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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/* Physical Memory Map */
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define PHYS_SDRAM_SIZE SZ_512M
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* USB Configs */
|
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
|
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
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|
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#define CONFIG_IMX_THERMAL
|
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|
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#define ENV_MMC \
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"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
|
||||
"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
|
||||
"fitpart=1\0" \
|
||||
"bootdelay=3\0" \
|
||||
"silent=1\0" \
|
||||
"optargs=rw rootwait\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcrootfstype=ext4\0" \
|
||||
"mmcfit_name=fitImage\0" \
|
||||
"mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
|
||||
"${mmcfit_name}\0" \
|
||||
"mmcargs=setenv bootargs " \
|
||||
"root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
|
||||
"console=${console} rootfstype=${mmcrootfstype}\0" \
|
||||
"mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
|
||||
|
||||
/* Default environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"console=ttymxc0,115200n8\0" \
|
||||
"addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
|
||||
"fit_addr=0x82000000\0" \
|
||||
ENV_MMC
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#endif /* __DART_6UL_H */
|
||||
@@ -46,11 +46,11 @@
|
||||
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
|
||||
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate}" \
|
||||
" root=PARTUUID=${uuid} rootwait rw\0 ${mtdparts}\0" \
|
||||
" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
|
||||
"nandargs=setenv bootargs console=${console},${baudrate}" \
|
||||
" ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
|
||||
" ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \
|
||||
"ramargs=setenv bootargs console=${console},${baudrate}" \
|
||||
" root=/dev/ram rw ${mtdparts}\0" \
|
||||
" root=/dev/ram rw ${mtdparts} ${optargs}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...;" \
|
||||
|
||||
176
include/configs/imx8qm_mek.h
Normal file
176
include/configs/imx8qm_mek.h
Normal file
@@ -0,0 +1,176 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8QM_MEK_H
|
||||
#define __IMX8QM_MEK_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_TEXT_BASE 0x0
|
||||
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x013E000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
|
||||
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
|
||||
#define CONFIG_SYS_ICACHE_OFF
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_MALLOC_F_ADDR 0x00120000
|
||||
|
||||
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#define CONFIG_OF_EMBED
|
||||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* Flat Device Tree Definitions */
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#undef CONFIG_CMD_EXPORTENV
|
||||
#undef CONFIG_CMD_IMPORTENV
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#undef CONFIG_CMD_CRC32
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define USDHC1_BASE_ADDR 0x5B010000
|
||||
#define USDHC2_BASE_ADDR 0x5B020000
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"panel=NULL\0" \
|
||||
"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=fsl-imx8qxp-mek.dtb\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x80280000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
|
||||
|
||||
/* Default environment is in SD */
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_2 0x880000000
|
||||
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
|
||||
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
|
||||
|
||||
/* Serial */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
/* Networking */
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#endif /* __IMX8QM_MEK_H */
|
||||
@@ -64,11 +64,11 @@
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"panel=NULL\0" \
|
||||
"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
|
||||
"console=ttyLP0,${baudrate} earlycon\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=fsl-imx8qxp-mek.dtb\0" \
|
||||
"fdt_file=imx8qxp-mek.dtb\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
@@ -158,7 +158,6 @@
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
|
||||
@@ -15,14 +15,7 @@
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
@@ -57,7 +50,7 @@
|
||||
"setexpr blkc ${blkc} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${blkc}" \
|
||||
"; fi\0" \
|
||||
"upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\
|
||||
"upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\
|
||||
"if tftp ${loadaddr} ${wic_file}; then " \
|
||||
"setexpr blkc ${filesize} / 0x200; " \
|
||||
"setexpr blkc ${blkc} + 1; " \
|
||||
|
||||
@@ -118,7 +118,6 @@
|
||||
* USB
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
@@ -61,7 +61,6 @@
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
|
||||
#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
|
||||
|
||||
@@ -41,7 +41,6 @@
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
@@ -38,7 +38,6 @@
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
@@ -37,7 +37,6 @@
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_USB_ETHER_MCS7830
|
||||
|
||||
@@ -65,7 +65,7 @@
|
||||
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
|
||||
"nandrootfstype=ubifs rootwait\0" \
|
||||
@@ -104,7 +104,8 @@
|
||||
"ramargs=setenv bootargs "\
|
||||
"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
|
||||
"mmcargs=setenv bootargs "\
|
||||
"root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
|
||||
"root=PARTUUID=${uuid} " \
|
||||
"rootfstype=${mmcrootfstype} rw\0" \
|
||||
"nandargs=setenv bootargs "\
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
@@ -118,6 +119,7 @@
|
||||
"loadfdt=mmc rescan; " \
|
||||
"load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
|
||||
"mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \
|
||||
"run finduuid; "\
|
||||
"run mmcargs; " \
|
||||
"run common_bootargs; " \
|
||||
"run dump_bootargs; " \
|
||||
|
||||
@@ -46,7 +46,7 @@
|
||||
#define CONFIG_DFU_ENV_SETTINGS \
|
||||
"dfu_alt_info=" \
|
||||
"spl raw 0x2 0x400;" \
|
||||
"u-boot raw 0x8a 0x400;" \
|
||||
"u-boot raw 0x8a 0x1000;" \
|
||||
"/boot/zImage ext4 0 1;" \
|
||||
"/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \
|
||||
"/boot/imx7d-pico-pi.dtb ext4 0 1;" \
|
||||
|
||||
@@ -31,7 +31,6 @@
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_EHCI_MX5
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
@@ -24,8 +24,6 @@
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
|
||||
|
||||
@@ -39,7 +37,7 @@
|
||||
#define CONFIG_SERIAL_TAG
|
||||
|
||||
#define CONFIG_DFU_ENV_SETTINGS \
|
||||
"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
|
||||
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_DFU_ENV_SETTINGS \
|
||||
|
||||
846
include/dt-bindings/clock/imx8qm-clock.h
Normal file
846
include/dt-bindings/clock/imx8qm-clock.h
Normal file
@@ -0,0 +1,846 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8QM_H
|
||||
|
||||
#define IMX8QM_CLK_DUMMY 0
|
||||
|
||||
#define IMX8QM_A53_DIV 1
|
||||
#define IMX8QM_A53_CLK 2
|
||||
#define IMX8QM_A72_DIV 3
|
||||
#define IMX8QM_A72_CLK 4
|
||||
|
||||
/* SC Clocks. */
|
||||
#define IMX8QM_SC_I2C_DIV 5
|
||||
#define IMX8QM_SC_I2C_CLK 6
|
||||
#define IMX8QM_SC_PID0_DIV 7
|
||||
#define IMX8QM_SC_PID0_CLK 8
|
||||
#define IMX8QM_SC_PIT_DIV 9
|
||||
#define IMX8QM_SC_PIT_CLK 10
|
||||
#define IMX8QM_SC_TPM_DIV 11
|
||||
#define IMX8QM_SC_TPM_CLK 12
|
||||
#define IMX8QM_SC_UART_DIV 13
|
||||
#define IMX8QM_SC_UART_CLK 14
|
||||
|
||||
/* LSIO */
|
||||
#define IMX8QM_PWM0_DIV 15
|
||||
#define IMX8QM_PWM0_CLK 16
|
||||
#define IMX8QM_PWM1_DIV 17
|
||||
#define IMX8QM_PWM1_CLK 18
|
||||
#define IMX8QM_PWM2_DIV 19
|
||||
#define IMX8QM_PWM2_CLK 20
|
||||
#define IMX8QM_PWM3_DIV 21
|
||||
#define IMX8QM_PWM3_CLK 22
|
||||
#define IMX8QM_PWM4_DIV 23
|
||||
#define IMX8QM_PWM4_CLK 24
|
||||
#define IMX8QM_PWM5_DIV 26
|
||||
#define IMX8QM_PWM5_CLK 27
|
||||
#define IMX8QM_PWM6_DIV 28
|
||||
#define IMX8QM_PWM6_CLK 29
|
||||
#define IMX8QM_PWM7_DIV 30
|
||||
#define IMX8QM_PWM7_CLK 31
|
||||
#define IMX8QM_FSPI0_DIV 32
|
||||
#define IMX8QM_FSPI0_CLK 33
|
||||
#define IMX8QM_FSPI1_DIV 34
|
||||
#define IMX8QM_FSPI1_CLK 35
|
||||
#define IMX8QM_GPT0_DIV 36
|
||||
#define IMX8QM_GPT0_CLK 37
|
||||
#define IMX8QM_GPT1_DIV 38
|
||||
#define IMX8QM_GPT1_CLK 39
|
||||
#define IMX8QM_GPT2_DIV 40
|
||||
#define IMX8QM_GPT2_CLK 41
|
||||
#define IMX8QM_GPT3_DIV 42
|
||||
#define IMX8QM_GPT3_CLK 43
|
||||
#define IMX8QM_GPT4_DIV 44
|
||||
#define IMX8QM_GPT4_CLK 45
|
||||
|
||||
/* Connectivity */
|
||||
#define IMX8QM_APBHDMA_CLK 46
|
||||
#define IMX8QM_GPMI_APB_CLK 47
|
||||
#define IMX8QM_GPMI_APB_BCH_CLK 48
|
||||
#define IMX8QM_GPMI_BCH_IO_DIV 49
|
||||
#define IMX8QM_GPMI_BCH_IO_CLK 50
|
||||
#define IMX8QM_GPMI_BCH_DIV 51
|
||||
#define IMX8QM_GPMI_BCH_CLK 52
|
||||
#define IMX8QM_SDHC0_IPG_CLK 53
|
||||
#define IMX8QM_SDHC0_DIV 54
|
||||
#define IMX8QM_SDHC0_CLK 55
|
||||
#define IMX8QM_SDHC1_IPG_CLK 56
|
||||
#define IMX8QM_SDHC1_DIV 57
|
||||
#define IMX8QM_SDHC1_CLK 58
|
||||
#define IMX8QM_SDHC2_IPG_CLK 59
|
||||
#define IMX8QM_SDHC2_DIV 60
|
||||
#define IMX8QM_SDHC2_CLK 61
|
||||
#define IMX8QM_USB2_OH_AHB_CLK 62
|
||||
#define IMX8QM_USB2_OH_IPG_S_CLK 63
|
||||
#define IMX8QM_USB2_OH_IPG_S_PL301_CLK 64
|
||||
#define IMX8QM_USB2_PHY_IPG_CLK 65
|
||||
#define IMX8QM_USB3_IPG_CLK 66
|
||||
#define IMX8QM_USB3_CORE_PCLK 67
|
||||
#define IMX8QM_USB3_PHY_CLK 68
|
||||
#define IMX8QM_USB3_ACLK_DIV 69
|
||||
#define IMX8QM_USB3_ACLK 70
|
||||
#define IMX8QM_USB3_BUS_DIV 71
|
||||
#define IMX8QM_USB3_BUS_CLK 72
|
||||
#define IMX8QM_USB3_LPM_DIV 73
|
||||
#define IMX8QM_USB3_LPM_CLK 74
|
||||
#define IMX8QM_ENET0_AHB_CLK 75
|
||||
#define IMX8QM_ENET0_IPG_S_CLK 76
|
||||
#define IMX8QM_ENET0_IPG_CLK 77
|
||||
#define IMX8QM_ENET0_RGMII_DIV 78
|
||||
#define IMX8QM_ENET0_RGMII_TX_CLK 79
|
||||
#define IMX8QM_ENET0_ROOT_DIV 80
|
||||
#define IMX8QM_ENET0_TX_CLK 81
|
||||
#define IMX8QM_ENET0_ROOT_CLK 82
|
||||
#define IMX8QM_ENET0_PTP_CLK 83
|
||||
#define IMX8QM_ENET0_BYPASS_DIV 84
|
||||
#define IMX8QM_ENET1_AHB_CLK 85
|
||||
#define IMX8QM_ENET1_IPG_S_CLK 86
|
||||
#define IMX8QM_ENET1_IPG_CLK 87
|
||||
#define IMX8QM_ENET1_RGMII_DIV 88
|
||||
#define IMX8QM_ENET1_RGMII_TX_CLK 89
|
||||
#define IMX8QM_ENET1_ROOT_DIV 90
|
||||
#define IMX8QM_ENET1_TX_CLK 91
|
||||
#define IMX8QM_ENET1_ROOT_CLK 92
|
||||
#define IMX8QM_ENET1_PTP_CLK 93
|
||||
#define IMX8QM_ENET1_BYPASS_DIV 94
|
||||
#define IMX8QM_MLB_CLK 95
|
||||
#define IMX8QM_MLB_HCLK 96
|
||||
#define IMX8QM_MLB_IPG_CLK 97
|
||||
#define IMX8QM_EDMA_CLK 98
|
||||
#define IMX8QM_EDMA_IPG_CLK 99
|
||||
|
||||
/* DMA */
|
||||
#define IMX8QM_SPI0_IPG_CLK 100
|
||||
#define IMX8QM_SPI0_DIV 101
|
||||
#define IMX8QM_SPI0_CLK 102
|
||||
#define IMX8QM_SPI1_IPG_CLK 103
|
||||
#define IMX8QM_SPI1_DIV 104
|
||||
#define IMX8QM_SPI1_CLK 105
|
||||
#define IMX8QM_SPI2_IPG_CLK 106
|
||||
#define IMX8QM_SPI2_DIV 107
|
||||
#define IMX8QM_SPI2_CLK 108
|
||||
#define IMX8QM_SPI3_IPG_CLK 109
|
||||
#define IMX8QM_SPI3_DIV 110
|
||||
#define IMX8QM_SPI3_CLK 111
|
||||
#define IMX8QM_UART0_IPG_CLK 112
|
||||
#define IMX8QM_UART0_DIV 113
|
||||
#define IMX8QM_UART0_CLK 114
|
||||
#define IMX8QM_UART1_IPG_CLK 115
|
||||
#define IMX8QM_UART1_DIV 116
|
||||
#define IMX8QM_UART1_CLK 117
|
||||
#define IMX8QM_UART2_IPG_CLK 118
|
||||
#define IMX8QM_UART2_DIV 119
|
||||
#define IMX8QM_UART2_CLK 120
|
||||
#define IMX8QM_UART3_IPG_CLK 121
|
||||
#define IMX8QM_UART3_DIV 122
|
||||
#define IMX8QM_UART3_CLK 123
|
||||
#define IMX8QM_UART4_IPG_CLK 124
|
||||
#define IMX8QM_UART4_DIV 125
|
||||
#define IMX8QM_EMVSIM0_IPG_CLK 126
|
||||
#define IMX8QM_UART4_CLK 127
|
||||
#define IMX8QM_EMVSIM0_DIV 128
|
||||
#define IMX8QM_EMVSIM0_CLK 129
|
||||
#define IMX8QM_EMVSIM1_IPG_CLK 130
|
||||
#define IMX8QM_EMVSIM1_DIV 131
|
||||
#define IMX8QM_EMVSIM1_CLK 132
|
||||
#define IMX8QM_CAN0_IPG_CHI_CLK 133
|
||||
#define IMX8QM_CAN0_IPG_CLK 134
|
||||
#define IMX8QM_CAN0_DIV 135
|
||||
#define IMX8QM_CAN0_CLK 136
|
||||
#define IMX8QM_CAN1_IPG_CHI_CLK 137
|
||||
#define IMX8QM_CAN1_IPG_CLK 138
|
||||
#define IMX8QM_CAN1_DIV 139
|
||||
#define IMX8QM_CAN1_CLK 140
|
||||
#define IMX8QM_CAN2_IPG_CHI_CLK 141
|
||||
#define IMX8QM_CAN2_IPG_CLK 142
|
||||
#define IMX8QM_CAN2_DIV 143
|
||||
#define IMX8QM_CAN2_CLK 144
|
||||
#define IMX8QM_I2C0_IPG_CLK 145
|
||||
#define IMX8QM_I2C0_DIV 146
|
||||
#define IMX8QM_I2C0_CLK 147
|
||||
#define IMX8QM_I2C1_IPG_CLK 148
|
||||
#define IMX8QM_I2C1_DIV 149
|
||||
#define IMX8QM_I2C1_CLK 150
|
||||
#define IMX8QM_I2C2_IPG_CLK 151
|
||||
#define IMX8QM_I2C2_DIV 152
|
||||
#define IMX8QM_I2C2_CLK 153
|
||||
#define IMX8QM_I2C3_IPG_CLK 154
|
||||
#define IMX8QM_I2C3_DIV 155
|
||||
#define IMX8QM_I2C3_CLK 156
|
||||
#define IMX8QM_I2C4_IPG_CLK 157
|
||||
#define IMX8QM_I2C4_DIV 158
|
||||
#define IMX8QM_I2C4_CLK 159
|
||||
#define IMX8QM_FTM0_IPG_CLK 160
|
||||
#define IMX8QM_FTM0_DIV 161
|
||||
#define IMX8QM_FTM0_CLK 162
|
||||
#define IMX8QM_FTM1_IPG_CLK 163
|
||||
#define IMX8QM_FTM1_DIV 164
|
||||
#define IMX8QM_FTM1_CLK 165
|
||||
#define IMX8QM_ADC0_IPG_CLK 166
|
||||
#define IMX8QM_ADC0_DIV 167
|
||||
#define IMX8QM_ADC0_CLK 168
|
||||
#define IMX8QM_ADC1_IPG_CLK 169
|
||||
#define IMX8QM_ADC1_DIV 170
|
||||
#define IMX8QM_ADC1_CLK 171
|
||||
|
||||
/* Audio */
|
||||
#define IMX8QM_AUD_PLL0_DIV 172
|
||||
#define IMX8QM_AUD_PLL0 173
|
||||
#define IMX8QM_AUD_PLL1_DIV 174
|
||||
#define IMX8QM_AUD_PLL1 175
|
||||
#define IMX8QM_AUD_AMIX_IPG 182
|
||||
#define IMX8QM_AUD_ESAI_0_IPG 183
|
||||
#define IMX8QM_AUD_ESAI_1_IPG 184
|
||||
#define IMX8QM_AUD_ESAI_0_EXTAL_IPG 185
|
||||
#define IMX8QM_AUD_ESAI_1_EXTAL_IPG 186
|
||||
#define IMX8QM_AUD_SAI_0_IPG 187
|
||||
#define IMX8QM_AUD_SAI_0_IPG_S 188
|
||||
#define IMX8QM_AUD_SAI_0_MCLK 189
|
||||
#define IMX8QM_AUD_SAI_1_IPG 190
|
||||
#define IMX8QM_AUD_SAI_1_IPG_S 191
|
||||
#define IMX8QM_AUD_SAI_1_MCLK 192
|
||||
#define IMX8QM_AUD_SAI_2_IPG 193
|
||||
#define IMX8QM_AUD_SAI_2_IPG_S 194
|
||||
#define IMX8QM_AUD_SAI_2_MCLK 195
|
||||
#define IMX8QM_AUD_SAI_3_IPG 196
|
||||
#define IMX8QM_AUD_SAI_3_IPG_S 197
|
||||
#define IMX8QM_AUD_SAI_3_MCLK 198
|
||||
#define IMX8QM_AUD_SAI_6_IPG 199
|
||||
#define IMX8QM_AUD_SAI_6_IPG_S 200
|
||||
#define IMX8QM_AUD_SAI_6_MCLK 201
|
||||
#define IMX8QM_AUD_SAI_7_IPG 202
|
||||
#define IMX8QM_AUD_SAI_7_IPG_S 203
|
||||
#define IMX8QM_AUD_SAI_7_MCLK 204
|
||||
#define IMX8QM_AUD_SAI_HDMIRX0_IPG 205
|
||||
#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S 206
|
||||
#define IMX8QM_AUD_SAI_HDMIRX0_MCLK 207
|
||||
#define IMX8QM_AUD_SAI_HDMITX0_IPG 208
|
||||
#define IMX8QM_AUD_SAI_HDMITX0_IPG_S 209
|
||||
#define IMX8QM_AUD_SAI_HDMITX0_MCLK 210
|
||||
#define IMX8QM_AUD_MQS_IPG 211
|
||||
#define IMX8QM_AUD_MQS_HMCLK 212
|
||||
#define IMX8QM_AUD_GPT5_IPG_S 213
|
||||
#define IMX8QM_AUD_GPT5_CLKIN 214
|
||||
#define IMX8QM_AUD_GPT5_24M_CLK 215
|
||||
#define IMX8QM_AUD_GPT6_IPG_S 216
|
||||
#define IMX8QM_AUD_GPT6_CLKIN 217
|
||||
#define IMX8QM_AUD_GPT6_24M_CLK 218
|
||||
#define IMX8QM_AUD_GPT7_IPG_S 219
|
||||
#define IMX8QM_AUD_GPT7_CLKIN 220
|
||||
#define IMX8QM_AUD_GPT7_24M_CLK 221
|
||||
#define IMX8QM_AUD_GPT8_IPG_S 222
|
||||
#define IMX8QM_AUD_GPT8_CLKIN 223
|
||||
#define IMX8QM_AUD_GPT8_24M_CLK 224
|
||||
#define IMX8QM_AUD_GPT9_IPG_S 225
|
||||
#define IMX8QM_AUD_GPT9_CLKIN 226
|
||||
#define IMX8QM_AUD_GPT9_24M_CLK 227
|
||||
#define IMX8QM_AUD_GPT10_IPG_S 228
|
||||
#define IMX8QM_AUD_GPT10_CLKIN 229
|
||||
#define IMX8QM_AUD_GPT10_24M_CLK 230
|
||||
#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV 232
|
||||
#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK 233
|
||||
#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV 234
|
||||
#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK 235
|
||||
#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV 236
|
||||
#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK 237
|
||||
#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV 238
|
||||
#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK 239
|
||||
#define IMX8QM_AUD_MCLKOUT0 240
|
||||
#define IMX8QM_AUD_MCLKOUT1 241
|
||||
#define IMX8QM_AUD_SPDIF_0_TX_CLK 242
|
||||
#define IMX8QM_AUD_SPDIF_0_GCLKW 243
|
||||
#define IMX8QM_AUD_SPDIF_0_IPG_S 244
|
||||
#define IMX8QM_AUD_SPDIF_1_TX_CLK 245
|
||||
#define IMX8QM_AUD_SPDIF_1_GCLKW 246
|
||||
#define IMX8QM_AUD_SPDIF_1_IPG_S 247
|
||||
#define IMX8QM_AUD_ASRC_0_IPG 248
|
||||
#define IMX8QM_AUD_ASRC_0_MEM 249
|
||||
#define IMX8QM_AUD_ASRC_1_IPG 250
|
||||
#define IMX8QM_AUD_ASRC_1_MEM 251
|
||||
|
||||
/* VPU */
|
||||
#define IMX8QM_VPU_CORE_DIV 252
|
||||
#define IMX8QM_VPU_CORE_CLK 253
|
||||
#define IMX8QM_VPU_UART_DIV 254
|
||||
#define IMX8QM_VPU_UART_CLK 255
|
||||
#define IMX8QM_VPU_DDR_DIV 256
|
||||
#define IMX8QM_VPU_DDR_CLK 257
|
||||
#define IMX8QM_VPU_SYS_DIV 258
|
||||
#define IMX8QM_VPU_SYS_CLK 259
|
||||
#define IMX8QM_VPU_XUVI_DIV 260
|
||||
#define IMX8QM_VPU_XUVI_CLK 261
|
||||
|
||||
/* GPU Clocks. */
|
||||
#define IMX8QM_GPU0_CORE_DIV 262
|
||||
#define IMX8QM_GPU0_CORE_CLK 263
|
||||
#define IMX8QM_GPU0_SHADER_DIV 264
|
||||
#define IMX8QM_GPU0_SHADER_CLK 265
|
||||
#define IMX8QM_GPU1_CORE_DIV 266
|
||||
#define IMX8QM_GPU1_CORE_CLK 267
|
||||
#define IMX8QM_GPU1_SHADER_DIV 268
|
||||
#define IMX8QM_GPU1_SHADER_CLK 269
|
||||
|
||||
/* MIPI CSI */
|
||||
#define IMX8QM_CSI0_IPG_CLK_S 270
|
||||
#define IMX8QM_CSI0_LIS_IPG_CLK 271
|
||||
#define IMX8QM_CSI0_APB_CLK 272
|
||||
#define IMX8QM_CSI0_I2C0_DIV 273
|
||||
#define IMX8QM_CSI0_I2C0_CLK 274
|
||||
#define IMX8QM_CSI0_PWM0_DIV 275
|
||||
#define IMX8QM_CSI0_PWM0_CLK 276
|
||||
#define IMX8QM_CSI0_CORE_DIV 277
|
||||
#define IMX8QM_CSI0_CORE_CLK 278
|
||||
#define IMX8QM_CSI0_ESC_DIV 279
|
||||
#define IMX8QM_CSI0_ESC_CLK 280
|
||||
#define IMX8QM_CSI1_IPG_CLK_S 281
|
||||
#define IMX8QM_CSI1_LIS_IPG_CLK 282
|
||||
#define IMX8QM_CSI1_APB_CLK 283
|
||||
#define IMX8QM_CSI1_I2C0_DIV 284
|
||||
#define IMX8QM_CSI1_I2C0_CLK 285
|
||||
#define IMX8QM_CSI1_PWM0_DIV 286
|
||||
#define IMX8QM_CSI1_PWM0_CLK 287
|
||||
#define IMX8QM_CSI1_CORE_DIV 288
|
||||
#define IMX8QM_CSI1_CORE_CLK 289
|
||||
#define IMX8QM_CSI1_ESC_DIV 290
|
||||
#define IMX8QM_CSI1_ESC_CLK 291
|
||||
|
||||
/* Display */
|
||||
#define IMX8QM_DC0_PLL0_DIV 292
|
||||
#define IMX8QM_DC0_PLL0_CLK 293
|
||||
#define IMX8QM_DC0_PLL1_DIV 294
|
||||
#define IMX8QM_DC0_PLL1_CLK 295
|
||||
#define IMX8QM_DC0_DISP0_DIV 296
|
||||
#define IMX8QM_DC0_DISP0_CLK 297
|
||||
#define IMX8QM_DC0_DISP1_DIV 298
|
||||
#define IMX8QM_DC0_DISP1_CLK 299
|
||||
#define IMX8QM_DC0_BYPASS_0_DIV 300
|
||||
#define IMX8QM_DC0_BYPASS_1_DIV 301
|
||||
#define IMX8QM_DC0_IRIS_AXI_CLK 302
|
||||
#define IMX8AM_DC0_IRIS_MVPL_CLK 303
|
||||
#define IMX8QM_DC0_DISP0_MSI_CLK 304
|
||||
#define IMX8QM_DC0_LIS_IPG_CLK 305
|
||||
#define IMX8QM_DC0_PXL_CMB_APB_CLK 306
|
||||
#define IMX8QM_DC0_PRG0_RTRAM_CLK 307
|
||||
#define IMX8QM_DC0_PRG1_RTRAM_CLK 308
|
||||
#define IMX8QM_DC0_PRG2_RTRAM_CLK 309
|
||||
#define IMX8QM_DC0_PRG3_RTRAM_CLK 310
|
||||
#define IMX8QM_DC0_PRG4_RTRAM_CLK 311
|
||||
#define IMX8QM_DC0_PRG5_RTRAM_CLK 312
|
||||
#define IMX8QM_DC0_PRG6_RTRAM_CLK 313
|
||||
#define IMX8QM_DC0_PRG7_RTRAM_CLK 314
|
||||
#define IMX8QM_DC0_PRG8_RTRAM_CLK 315
|
||||
#define IMX8QM_DC0_PRG0_APB_CLK 316
|
||||
#define IMX8QM_DC0_PRG1_APB_CLK 317
|
||||
#define IMX8QM_DC0_PRG2_APB_CLK 318
|
||||
#define IMX8QM_DC0_PRG3_APB_CLK 319
|
||||
#define IMX8QM_DC0_PRG4_APB_CLK 320
|
||||
#define IMX8QM_DC0_PRG5_APB_CLK 321
|
||||
#define IMX8QM_DC0_PRG6_APB_CLK 322
|
||||
#define IMX8QM_DC0_PRG7_APB_CLK 323
|
||||
#define IMX8QM_DC0_PRG8_APB_CLK 324
|
||||
#define IMX8QM_DC0_DPR0_APB_CLK 325
|
||||
#define IMX8QM_DC0_DPR1_APB_CLK 326
|
||||
#define IMX8QM_DC0_RTRAM0_CLK 327
|
||||
#define IMX8QM_DC0_RTRAM1_CLK 328
|
||||
#define IMX8QM_DC1_PLL0_DIV 329
|
||||
#define IMX8QM_DC1_PLL0_CLK 330
|
||||
#define IMX8QM_DC1_PLL1_DIV 331
|
||||
#define IMX8QM_DC1_PLL1_CLK 332
|
||||
#define IMX8QM_DC1_DISP0_DIV 333
|
||||
#define IMX8QM_DC1_DISP0_CLK 334
|
||||
#define IMX8QM_DC1_BYPASS_0_DIV 335
|
||||
#define IMX8QM_DC1_BYPASS_1_DIV 336
|
||||
#define IMX8QM_DC1_DISP1_DIV 337
|
||||
#define IMX8QM_DC1_DISP1_CLK 338
|
||||
#define IMX8QM_DC1_IRIS_AXI_CLK 339
|
||||
#define IMX8AM_DC1_IRIS_MVPL_CLK 340
|
||||
#define IMX8QM_DC1_DISP0_MSI_CLK 341
|
||||
#define IMX8QM_DC1_LIS_IPG_CLK 342
|
||||
#define IMX8QM_DC1_PXL_CMB_APB_CLK 343
|
||||
#define IMX8QM_DC1_PRG0_RTRAM_CLK 344
|
||||
#define IMX8QM_DC1_PRG1_RTRAM_CLK 345
|
||||
#define IMX8QM_DC1_PRG2_RTRAM_CLK 346
|
||||
#define IMX8QM_DC1_PRG3_RTRAM_CLK 347
|
||||
#define IMX8QM_DC1_PRG4_RTRAM_CLK 348
|
||||
#define IMX8QM_DC1_PRG5_RTRAM_CLK 349
|
||||
#define IMX8QM_DC1_PRG6_RTRAM_CLK 350
|
||||
#define IMX8QM_DC1_PRG7_RTRAM_CLK 351
|
||||
#define IMX8QM_DC1_PRG8_RTRAM_CLK 352
|
||||
#define IMX8QM_DC1_PRG0_APB_CLK 353
|
||||
#define IMX8QM_DC1_PRG1_APB_CLK 354
|
||||
#define IMX8QM_DC1_PRG2_APB_CLK 355
|
||||
#define IMX8QM_DC1_PRG3_APB_CLK 356
|
||||
#define IMX8QM_DC1_PRG4_APB_CLK 357
|
||||
#define IMX8QM_DC1_PRG5_APB_CLK 358
|
||||
#define IMX8QM_DC1_PRG6_APB_CLK 359
|
||||
#define IMX8QM_DC1_PRG7_APB_CLK 360
|
||||
#define IMX8QM_DC1_PRG8_APB_CLK 361
|
||||
#define IMX8QM_DC1_DPR0_APB_CLK 362
|
||||
#define IMX8QM_DC1_DPR1_APB_CLK 363
|
||||
#define IMX8QM_DC1_RTRAM0_CLK 364
|
||||
#define IMX8QM_DC1_RTRAM1_CLK 365
|
||||
|
||||
/* DRC */
|
||||
#define IMX8QM_DRC0_PLL0_DIV 366
|
||||
#define IMX8QM_DRC0_PLL0_CLK 367
|
||||
#define IMX8QM_DRC0_DIV 368
|
||||
#define IMX8QM_DRC0_CLK 369
|
||||
#define IMX8QM_DRC1_PLL0_DIV 370
|
||||
#define IMX8QM_DRC1_PLL0_CLK 371
|
||||
#define IMX8QM_DRC1_DIV 372
|
||||
#define IMX8QM_DRC1_CLK 373
|
||||
|
||||
/* HDMI */
|
||||
#define IMX8QM_HDMI_AV_PLL_DIV 374
|
||||
#define IMX8QM_HDMI_AV_PLL_CLK 375
|
||||
#define IMX8QM_HDMI_I2S_BYPASS_CLK 376
|
||||
#define IMX8QM_HDMI_I2C0_DIV 377
|
||||
#define IMX8QM_HDMI_I2C0_CLK 378
|
||||
#define IMX8QM_HDMI_PXL_DIV 379
|
||||
#define IMX8QM_HDMI_PXL_CLK 380
|
||||
#define IMX8QM_HDMI_PXL_LINK_DIV 381
|
||||
#define IMX8QM_HDMI_PXL_LINK_CLK 382
|
||||
#define IMX8QM_HDMI_PXL_MUX_DIV 383
|
||||
#define IMX8QM_HDMI_PXL_MUX_CLK 384
|
||||
#define IMX8QM_HDMI_I2S_DIV 385
|
||||
#define IMX8QM_HDMI_I2S_CLK 386
|
||||
#define IMX8QM_HDMI_HDP_CORE_DIV 387
|
||||
#define IMX8QM_HDMI_HDP_CORE_CLK 388
|
||||
#define IMX8QM_HDMI_I2C_IPG_S_CLK 389
|
||||
#define IMX8QM_HDMI_I2C_IPG_CLK 390
|
||||
#define IMX8QM_HDMI_PWM_IPG_S_CLK 391
|
||||
#define IMX8QM_HDMI_PWM_IPG_CLK 392
|
||||
#define IMX8QM_HDMI_PWM_32K_CLK 393
|
||||
#define IMX8QM_HDMI_GPIO_IPG_CLK 394
|
||||
#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK 395
|
||||
#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK 396
|
||||
#define IMX8QM_HDMI_LIS_IPG_CLK 397
|
||||
#define IMX8QM_HDMI_MSI_HCLK 398
|
||||
#define IMX8QM_HDMI_PXL_EVEN_CLK 399
|
||||
#define IMX8QM_HDMI_HDP_CLK 400
|
||||
#define IMX8QM_HDMI_PXL_DBL_CLK 401
|
||||
#define IMX8QM_HDMI_APB_CLK 402
|
||||
#define IMX8QM_HDMI_PXL_LPCG_CLK 403
|
||||
#define IMX8QM_HDMI_HDP_PHY_CLK 404
|
||||
#define IMX8QM_HDMI_IPG_DIV 405
|
||||
#define IMX8QM_HDMI_VIF_CLK 406
|
||||
#define IMX8QM_HDMI_DIG_PLL_DIV 407
|
||||
#define IMX8QM_HDMI_DIG_PLL_CLK 408
|
||||
#define IMX8QM_HDMI_APB_MUX_CSR_CLK 409
|
||||
#define IMX8QM_HDMI_APB_MUX_CTRL_CLK 410
|
||||
|
||||
/* RX-HDMI */
|
||||
#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK 411
|
||||
#define IMX8QM_HDMI_RX_BYPASS_CLK 412
|
||||
#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK 413
|
||||
#define IMX8QM_HDMI_RX_I2C0_DIV 414
|
||||
#define IMX8QM_HDMI_RX_I2C0_CLK 415
|
||||
#define IMX8QM_HDMI_RX_SPDIF_DIV 416
|
||||
#define IMX8QM_HDMI_RX_SPDIF_CLK 417
|
||||
#define IMX8QM_HDMI_RX_HD_REF_DIV 418
|
||||
#define IMX8QM_HDMI_RX_HD_REF_CLK 419
|
||||
#define IMX8QM_HDMI_RX_HD_CORE_DIV 420
|
||||
#define IMX8QM_HDMI_RX_HD_CORE_CLK 421
|
||||
#define IMX8QM_HDMI_RX_PXL_DIV 422
|
||||
#define IMX8QM_HDMI_RX_PXL_CLK 423
|
||||
#define IMX8QM_HDMI_RX_I2S_DIV 424
|
||||
#define IMX8QM_HDMI_RX_I2S_CLK 425
|
||||
#define IMX8QM_HDMI_RX_PWM_DIV 426
|
||||
#define IMX8QM_HDMI_RX_PWM_CLK 427
|
||||
|
||||
/* LVDS */
|
||||
#define IMX8QM_LVDS0_BYPASS_CLK 428
|
||||
#define IMX8QM_LVDS0_PIXEL_DIV 429
|
||||
#define IMX8QM_LVDS0_PIXEL_CLK 430
|
||||
#define IMX8QM_LVDS0_PHY_DIV 431
|
||||
#define IMX8QM_LVDS0_PHY_CLK 432
|
||||
#define IMX8QM_LVDS0_I2C0_IPG_CLK 433
|
||||
#define IMX8QM_LVDS0_I2C0_DIV 434
|
||||
#define IMX8QM_LVDS0_I2C0_CLK 435
|
||||
#define IMX8QM_LVDS0_I2C1_IPG_CLK 436
|
||||
#define IMX8QM_LVDS0_I2C1_DIV 437
|
||||
#define IMX8QM_LVDS0_I2C1_CLK 438
|
||||
#define IMX8QM_LVDS0_PWM0_IPG_CLK 439
|
||||
#define IMX8QM_LVDS0_PWM0_DIV 440
|
||||
#define IMX8QM_LVDS0_PWM0_CLK 441
|
||||
#define IMX8QM_LVDS0_GPIO_IPG_CLK 444
|
||||
#define IMX8QM_LVDS1_BYPASS_DIV 445
|
||||
#define IMX8QM_LVDS1_BYPASS_CLK 446
|
||||
#define IMX8QM_LVDS1_PIXEL_DIV 447
|
||||
#define IMX8QM_LVDS1_PIXEL_CLK 448
|
||||
#define IMX8QM_LVDS1_PHY_DIV 449
|
||||
#define IMX8QM_LVDS1_PHY_CLK 450
|
||||
#define IMX8QM_LVDS1_I2C0_IPG_CLK 451
|
||||
#define IMX8QM_LVDS1_I2C0_DIV 452
|
||||
#define IMX8QM_LVDS1_I2C0_CLK 453
|
||||
#define IMX8QM_LVDS1_I2C1_IPG_CLK 454
|
||||
#define IMX8QM_LVDS1_I2C1_DIV 455
|
||||
#define IMX8QM_LVDS1_I2C1_CLK 456
|
||||
#define IMX8QM_LVDS1_PWM0_IPG_CLK 457
|
||||
#define IMX8QM_LVDS1_PWM0_DIV 458
|
||||
#define IMX8QM_LVDS1_PWM0_CLK 459
|
||||
#define IMX8QM_LVDS1_GPIO_IPG_CLK 462
|
||||
|
||||
/* MIPI */
|
||||
#define IMX8QM_MIPI0_BYPASS_CLK 465
|
||||
#define IMX8QM_MIPI0_I2C0_DIV 466
|
||||
#define IMX8QM_MIPI0_I2C0_CLK 467
|
||||
#define IMX8QM_MIPI0_I2C1_DIV 468
|
||||
#define IMX8QM_MIPI0_I2C1_CLK 469
|
||||
#define IMX8QM_MIPI0_PWM0_DIV 470
|
||||
#define IMX8QM_MIPI0_PWM0_CLK 471
|
||||
#define IMX8QM_MIPI0_DSI_TX_ESC_DIV 472
|
||||
#define IMX8QM_MIPI0_DSI_TX_ESC_CLK 473
|
||||
#define IMX8QM_MIPI0_DSI_RX_ESC_DIV 474
|
||||
#define IMX8QM_MIPI0_DSI_RX_ESC_CLK 475
|
||||
#define IMX8QM_MIPI0_PXL_DIV 476
|
||||
#define IMX8QM_MIPI0_PXL_CLK 477
|
||||
#define IMX8QM_MIPI1_BYPASS_CLK 479
|
||||
#define IMX8QM_MIPI1_I2C0_DIV 480
|
||||
#define IMX8QM_MIPI1_I2C0_CLK 481
|
||||
#define IMX8QM_MIPI1_I2C1_DIV 482
|
||||
#define IMX8QM_MIPI1_I2C1_CLK 483
|
||||
#define IMX8QM_MIPI1_PWM0_DIV 484
|
||||
#define IMX8QM_MIPI1_PWM0_CLK 485
|
||||
#define IMX8QM_MIPI1_DSI_TX_ESC_DIV 486
|
||||
#define IMX8QM_MIPI1_DSI_TX_ESC_CLK 487
|
||||
#define IMX8QM_MIPI1_DSI_RX_ESC_DIV 488
|
||||
#define IMX8QM_MIPI1_DSI_RX_ESC_CLK 489
|
||||
#define IMX8QM_MIPI1_PXL_DIV 490
|
||||
#define IMX8QM_MIPI1_PXL_CLK 491
|
||||
|
||||
/* Imaging */
|
||||
#define IMX8QM_IMG_JPEG_ENC_IPG_CLK 492
|
||||
#define IMX8QM_IMG_JPEG_ENC_CLK 493
|
||||
#define IMX8QM_IMG_JPEG_DEC_IPG_CLK 494
|
||||
#define IMX8QM_IMG_JPEG_DEC_CLK 495
|
||||
#define IMX8QM_IMG_PXL_LINK_DC0_CLK 496
|
||||
#define IMX8QM_IMG_PXL_LINK_DC1_CLK 497
|
||||
#define IMX8QM_IMG_PXL_LINK_CSI0_CLK 498
|
||||
#define IMX8QM_IMG_PXL_LINK_CSI1_CLK 499
|
||||
#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK 500
|
||||
#define IMX8QM_IMG_PDMA_0_CLK 501
|
||||
#define IMX8QM_IMG_PDMA_1_CLK 502
|
||||
#define IMX8QM_IMG_PDMA_2_CLK 503
|
||||
#define IMX8QM_IMG_PDMA_3_CLK 504
|
||||
#define IMX8QM_IMG_PDMA_4_CLK 505
|
||||
#define IMX8QM_IMG_PDMA_5_CLK 506
|
||||
#define IMX8QM_IMG_PDMA_6_CLK 507
|
||||
#define IMX8QM_IMG_PDMA_7_CLK 508
|
||||
|
||||
/* HSIO */
|
||||
#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK 509
|
||||
#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK 510
|
||||
#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK 511
|
||||
#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK 512
|
||||
#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK 513
|
||||
#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK 514
|
||||
#define IMX8QM_HSIO_PCIE_X1_PER_CLK 515
|
||||
#define IMX8QM_HSIO_PCIE_X2_PER_CLK 516
|
||||
#define IMX8QM_HSIO_SATA_PER_CLK 517
|
||||
#define IMX8QM_HSIO_PHY_X1_PER_CLK 518
|
||||
#define IMX8QM_HSIO_PHY_X2_PER_CLK 519
|
||||
#define IMX8QM_HSIO_MISC_PER_CLK 520
|
||||
#define IMX8QM_HSIO_PHY_X1_APB_CLK 521
|
||||
#define IMX8QM_HSIO_PHY_X2_APB_0_CLK 522
|
||||
#define IMX8QM_HSIO_PHY_X2_APB_1_CLK 523
|
||||
#define IMX8QM_HSIO_SATA_CLK 524
|
||||
#define IMX8QM_HSIO_GPIO_CLK 525
|
||||
#define IMX8QM_HSIO_PHY_X1_PCLK 526
|
||||
#define IMX8QM_HSIO_PHY_X2_PCLK_0 527
|
||||
#define IMX8QM_HSIO_PHY_X2_PCLK_1 528
|
||||
#define IMX8QM_HSIO_SATA_EPCS_RX_CLK 529
|
||||
#define IMX8QM_HSIO_SATA_EPCS_TX_CLK 530
|
||||
|
||||
/* M4 */
|
||||
#define IMX8QM_M4_0_CORE_DIV 531
|
||||
#define IMX8QM_M4_0_CORE_CLK 532
|
||||
#define IMX8QM_M4_0_I2C_DIV 533
|
||||
#define IMX8QM_M4_0_I2C_CLK 534
|
||||
#define IMX8QM_M4_0_PIT_DIV 535
|
||||
#define IMX8QM_M4_0_PIT_CLK 536
|
||||
#define IMX8QM_M4_0_TPM_DIV 537
|
||||
#define IMX8QM_M4_0_TPM_CLK 538
|
||||
#define IMX8QM_M4_0_UART_DIV 539
|
||||
#define IMX8QM_M4_0_UART_CLK 540
|
||||
#define IMX8QM_M4_0_WDOG_DIV 541
|
||||
#define IMX8QM_M4_0_WDOG_CLK 542
|
||||
#define IMX8QM_M4_1_CORE_DIV 543
|
||||
#define IMX8QM_M4_1_CORE_CLK 544
|
||||
#define IMX8QM_M4_1_I2C_DIV 545
|
||||
#define IMX8QM_M4_1_I2C_CLK 546
|
||||
#define IMX8QM_M4_1_PIT_DIV 547
|
||||
#define IMX8QM_M4_1_PIT_CLK 548
|
||||
#define IMX8QM_M4_1_TPM_DIV 549
|
||||
#define IMX8QM_M4_1_TPM_CLK 550
|
||||
#define IMX8QM_M4_1_UART_DIV 551
|
||||
#define IMX8QM_M4_1_UART_CLK 552
|
||||
#define IMX8QM_M4_1_WDOG_DIV 553
|
||||
#define IMX8QM_M4_1_WDOG_CLK 554
|
||||
|
||||
/* IPG clocks */
|
||||
#define IMX8QM_24MHZ 555
|
||||
#define IMX8QM_GPT_3M 556
|
||||
#define IMX8QM_IPG_DMA_CLK_ROOT 557
|
||||
#define IMX8QM_IPG_AUD_CLK_ROOT 558
|
||||
#define IMX8QM_IPG_CONN_CLK_ROOT 559
|
||||
#define IMX8QM_AHB_CONN_CLK_ROOT 560
|
||||
#define IMX8QM_AXI_CONN_CLK_ROOT 561
|
||||
#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT 562
|
||||
#define IMX8QM_DC_AXI_EXT_CLK 563
|
||||
#define IMX8QM_DC_AXI_INT_CLK 564
|
||||
#define IMX8QM_DC_CFG_CLK 565
|
||||
#define IMX8QM_HDMI_IPG_CLK 566
|
||||
#define IMX8QM_LVDS_IPG_CLK 567
|
||||
#define IMX8QM_IMG_AXI_CLK 568
|
||||
#define IMX8QM_IMG_IPG_CLK 569
|
||||
#define IMX8QM_IMG_PXL_CLK 570
|
||||
#define IMX8QM_CSI0_I2C0_IPG_CLK 571
|
||||
#define IMX8QM_CSI0_PWM0_IPG_CLK 572
|
||||
#define IMX8QM_CSI1_I2C0_IPG_CLK 573
|
||||
#define IMX8QM_CSI1_PWM0_IPG_CLK 574
|
||||
#define IMX8QM_DC0_DPR0_B_CLK 575
|
||||
#define IMX8QM_DC0_DPR1_B_CLK 576
|
||||
#define IMX8QM_DC1_DPR0_B_CLK 577
|
||||
#define IMX8QM_DC1_DPR1_B_CLK 578
|
||||
#define IMX8QM_32KHZ 579
|
||||
#define IMX8QM_HSIO_AXI_CLK 580
|
||||
#define IMX8QM_HSIO_PER_CLK 581
|
||||
#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK 582
|
||||
#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK 583
|
||||
#define IMX8QM_HDMI_RX_PWM_IPG_CLK 584
|
||||
#define IMX8QM_HDMI_RX_I2C_DIV_CLK 585
|
||||
#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK 586
|
||||
#define IMX8QM_HDMI_RX_I2C_IPG_CLK 587
|
||||
#define IMX8QM_HDMI_RX_SINK_PCLK 588
|
||||
#define IMX8QM_HDMI_RX_SINK_SCLK 589
|
||||
#define IMX8QM_HDMI_RX_PXL_ENC_CLK 590
|
||||
#define IMX8QM_HDMI_RX_IPG_CLK 591
|
||||
|
||||
/* ACM */
|
||||
#define IMX8QM_HDMI_RX_MCLK 592
|
||||
#define IMX8QM_EXT_AUD_MCLK0 593
|
||||
#define IMX8QM_EXT_AUD_MCLK1 594
|
||||
#define IMX8QM_ESAI0_RX_CLK 595
|
||||
#define IMX8QM_ESAI0_RX_HF_CLK 596
|
||||
#define IMX8QM_ESAI0_TX_CLK 597
|
||||
#define IMX8QM_ESAI0_TX_HF_CLK 598
|
||||
#define IMX8QM_ESAI1_RX_CLK 599
|
||||
#define IMX8QM_ESAI1_RX_HF_CLK 600
|
||||
#define IMX8QM_ESAI1_TX_CLK 601
|
||||
#define IMX8QM_ESAI1_TX_HF_CLK 602
|
||||
#define IMX8QM_SPDIF0_RX 603
|
||||
#define IMX8QM_SPDIF1_RX 604
|
||||
#define IMX8QM_SAI0_RX_BCLK 605
|
||||
#define IMX8QM_SAI0_TX_BCLK 606
|
||||
#define IMX8QM_SAI1_RX_BCLK 607
|
||||
#define IMX8QM_SAI1_TX_BCLK 608
|
||||
#define IMX8QM_SAI2_RX_BCLK 609
|
||||
#define IMX8QM_SAI3_RX_BCLK 610
|
||||
#define IMX8QM_HDMI_RX_SAI0_RX_BCLK 611
|
||||
#define IMX8QM_SAI6_RX_BCLK 612
|
||||
#define IMX8QM_HDMI_TX_SAI0_TX_BCLK 613
|
||||
|
||||
#define IMX8QM_ACM_AUD_CLK0_SEL 614
|
||||
#define IMX8QM_ACM_AUD_CLK0_CLK 615
|
||||
#define IMX8QM_ACM_AUD_CLK1_SEL 616
|
||||
#define IMX8QM_ACM_AUD_CLK1_CLK 617
|
||||
#define IMX8QM_ACM_MCLKOUT0_SEL 618
|
||||
#define IMX8QM_ACM_MCLKOUT0_CLK 619
|
||||
#define IMX8QM_ACM_MCLKOUT1_SEL 620
|
||||
#define IMX8QM_ACM_MCLKOUT1_CLK 621
|
||||
#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL 622
|
||||
#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK 623
|
||||
#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL 624
|
||||
#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK 625
|
||||
#define IMX8QM_ACM_ESAI0_MCLK_SEL 626
|
||||
#define IMX8QM_ACM_ESAI0_MCLK_CLK 627
|
||||
#define IMX8QM_ACM_ESAI1_MCLK_SEL 628
|
||||
#define IMX8QM_ACM_ESAI1_MCLK_CLK 629
|
||||
#define IMX8QM_ACM_GPT0_MUX_CLK_SEL 630
|
||||
#define IMX8QM_ACM_GPT0_MUX_CLK_CLK 631
|
||||
#define IMX8QM_ACM_GPT1_MUX_CLK_SEL 632
|
||||
#define IMX8QM_ACM_GPT1_MUX_CLK_CLK 633
|
||||
#define IMX8QM_ACM_GPT2_MUX_CLK_SEL 634
|
||||
#define IMX8QM_ACM_GPT2_MUX_CLK_CLK 635
|
||||
#define IMX8QM_ACM_GPT3_MUX_CLK_SEL 636
|
||||
#define IMX8QM_ACM_GPT3_MUX_CLK_CLK 637
|
||||
#define IMX8QM_ACM_GPT4_MUX_CLK_SEL 638
|
||||
#define IMX8QM_ACM_GPT4_MUX_CLK_CLK 639
|
||||
#define IMX8QM_ACM_GPT5_MUX_CLK_SEL 640
|
||||
#define IMX8QM_ACM_GPT5_MUX_CLK_CLK 641
|
||||
#define IMX8QM_ACM_SAI0_MCLK_SEL 642
|
||||
#define IMX8QM_ACM_SAI0_MCLK_CLK 643
|
||||
#define IMX8QM_ACM_SAI1_MCLK_SEL 644
|
||||
#define IMX8QM_ACM_SAI1_MCLK_CLK 645
|
||||
#define IMX8QM_ACM_SAI2_MCLK_SEL 646
|
||||
#define IMX8QM_ACM_SAI2_MCLK_CLK 647
|
||||
#define IMX8QM_ACM_SAI3_MCLK_SEL 648
|
||||
#define IMX8QM_ACM_SAI3_MCLK_CLK 649
|
||||
#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL 650
|
||||
#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK 651
|
||||
#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL 652
|
||||
#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK 653
|
||||
#define IMX8QM_ACM_SAI6_MCLK_SEL 654
|
||||
#define IMX8QM_ACM_SAI6_MCLK_CLK 655
|
||||
#define IMX8QM_ACM_SAI7_MCLK_SEL 656
|
||||
#define IMX8QM_ACM_SAI7_MCLK_CLK 657
|
||||
#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL 658
|
||||
#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK 659
|
||||
#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL 660
|
||||
#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK 661
|
||||
#define IMX8QM_ACM_MQS_TX_CLK_SEL 662
|
||||
#define IMX8QM_ACM_MQS_TX_CLK_CLK 663
|
||||
|
||||
#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL 664
|
||||
#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK 665
|
||||
#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL 666
|
||||
#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK 667
|
||||
#define IMX8QM_ENET0_REF_50MHZ_CLK 668
|
||||
#define IMX8QM_ENET1_REF_50MHZ_CLK 669
|
||||
#define IMX8QM_ENET_25MHZ_CLK 670
|
||||
#define IMX8QM_ENET_125MHZ_CLK 671
|
||||
#define IMX8QM_ENET0_REF_DIV 672
|
||||
#define IMX8QM_ENET0_REF_CLK 673
|
||||
#define IMX8QM_ENET1_REF_DIV 674
|
||||
#define IMX8QM_ENET1_REF_CLK 675
|
||||
#define IMX8QM_ENET0_RMII_TX_CLK 676
|
||||
#define IMX8QM_ENET1_RMII_TX_CLK 677
|
||||
#define IMX8QM_ENET0_RMII_TX_SEL 678
|
||||
#define IMX8QM_ENET1_RMII_TX_SEL 679
|
||||
#define IMX8QM_ENET0_RMII_RX_CLK 680
|
||||
#define IMX8QM_ENET1_RMII_RX_CLK 681
|
||||
|
||||
#define IMX8QM_KPP_CLK 683
|
||||
#define IMX8QM_GPT0_HF_CLK 684
|
||||
#define IMX8QM_GPT0_IPG_S_CLK 685
|
||||
#define IMX8QM_GPT0_IPG_SLV_CLK 686
|
||||
#define IMX8QM_GPT0_IPG_MSTR_CLK 687
|
||||
#define IMX8QM_GPT1_HF_CLK 688
|
||||
#define IMX8QM_GPT1_IPG_S_CLK 689
|
||||
#define IMX8QM_GPT1_IPG_SLV_CLK 690
|
||||
#define IMX8QM_GPT1_IPG_MSTR_CLK 691
|
||||
#define IMX8QM_GPT2_HF_CLK 692
|
||||
#define IMX8QM_GPT2_IPG_S_CLK 693
|
||||
#define IMX8QM_GPT2_IPG_SLV_CLK 694
|
||||
#define IMX8QM_GPT2_IPG_MSTR_CLK 695
|
||||
#define IMX8QM_GPT3_HF_CLK 696
|
||||
#define IMX8QM_GPT3_IPG_S_CLK 697
|
||||
#define IMX8QM_GPT3_IPG_SLV_CLK 698
|
||||
#define IMX8QM_GPT3_IPG_MSTR_CLK 699
|
||||
#define IMX8QM_GPT4_HF_CLK 700
|
||||
#define IMX8QM_GPT4_IPG_S_CLK 701
|
||||
#define IMX8QM_GPT4_IPG_SLV_CLK 702
|
||||
#define IMX8QM_GPT4_IPG_MSTR_CLK 703
|
||||
#define IMX8QM_PWM0_HF_CLK 704
|
||||
#define IMX8QM_PWM0_IPG_S_CLK 705
|
||||
#define IMX8QM_PWM0_IPG_SLV_CLK 706
|
||||
#define IMX8QM_PWM0_IPG_MSTR_CLK 707
|
||||
#define IMX8QM_PWM1_HF_CLK 708
|
||||
#define IMX8QM_PWM1_IPG_S_CLK 709
|
||||
#define IMX8QM_PWM1_IPG_SLV_CLK 710
|
||||
#define IMX8QM_PWM1_IPG_MSTR_CLK 711
|
||||
#define IMX8QM_PWM2_HF_CLK 712
|
||||
#define IMX8QM_PWM2_IPG_S_CLK 713
|
||||
#define IMX8QM_PWM2_IPG_SLV_CLK 714
|
||||
#define IMX8QM_PWM2_IPG_MSTR_CLK 715
|
||||
#define IMX8QM_PWM3_HF_CLK 716
|
||||
#define IMX8QM_PWM3_IPG_S_CLK 717
|
||||
#define IMX8QM_PWM3_IPG_SLV_CLK 718
|
||||
#define IMX8QM_PWM3_IPG_MSTR_CLK 719
|
||||
#define IMX8QM_PWM4_HF_CLK 720
|
||||
#define IMX8QM_PWM4_IPG_S_CLK 721
|
||||
#define IMX8QM_PWM4_IPG_SLV_CLK 722
|
||||
#define IMX8QM_PWM4_IPG_MSTR_CLK 723
|
||||
#define IMX8QM_PWM5_HF_CLK 724
|
||||
#define IMX8QM_PWM5_IPG_S_CLK 725
|
||||
#define IMX8QM_PWM5_IPG_SLV_CLK 726
|
||||
#define IMX8QM_PWM5_IPG_MSTR_CLK 727
|
||||
#define IMX8QM_PWM6_HF_CLK 728
|
||||
#define IMX8QM_PWM6_IPG_S_CLK 729
|
||||
#define IMX8QM_PWM6_IPG_SLV_CLK 730
|
||||
#define IMX8QM_PWM6_IPG_MSTR_CLK 731
|
||||
#define IMX8QM_PWM7_HF_CLK 732
|
||||
#define IMX8QM_PWM7_IPG_S_CLK 733
|
||||
#define IMX8QM_PWM7_IPG_SLV_CLK 734
|
||||
#define IMX8QM_PWM7_IPG_MSTR_CLK 735
|
||||
#define IMX8QM_FSPI0_HCLK 736
|
||||
#define IMX8QM_FSPI0_IPG_CLK 737
|
||||
#define IMX8QM_FSPI0_IPG_S_CLK 738
|
||||
#define IMX8QM_FSPI1_HCLK 736
|
||||
#define IMX8QM_FSPI1_IPG_CLK 737
|
||||
#define IMX8QM_FSPI1_IPG_S_CLK 738
|
||||
#define IMX8QM_GPIO0_IPG_S_CLK 739
|
||||
#define IMX8QM_GPIO1_IPG_S_CLK 740
|
||||
#define IMX8QM_GPIO2_IPG_S_CLK 741
|
||||
#define IMX8QM_GPIO3_IPG_S_CLK 742
|
||||
#define IMX8QM_GPIO4_IPG_S_CLK 743
|
||||
#define IMX8QM_GPIO5_IPG_S_CLK 744
|
||||
#define IMX8QM_GPIO6_IPG_S_CLK 745
|
||||
#define IMX8QM_GPIO7_IPG_S_CLK 746
|
||||
#define IMX8QM_ROMCP_CLK 747
|
||||
#define IMX8QM_ROMCP_REG_CLK 748
|
||||
#define IMX8QM_96KROM_CLK 749
|
||||
#define IMX8QM_OCRAM_MEM_CLK 750
|
||||
#define IMX8QM_OCRAM_CTRL_CLK 751
|
||||
#define IMX8QM_LSIO_BUS_CLK 752
|
||||
#define IMX8QM_LSIO_MEM_CLK 753
|
||||
#define IMX8QM_LVDS0_LIS_IPG_CLK 754
|
||||
#define IMX8QM_LVDS1_LIS_IPG_CLK 755
|
||||
#define IMX8QM_MIPI0_LIS_IPG_CLK 756
|
||||
#define IMX8QM_MIPI0_I2C0_IPG_S_CLK 757
|
||||
#define IMX8QM_MIPI0_I2C0_IPG_CLK 758
|
||||
#define IMX8QM_MIPI0_I2C1_IPG_S_CLK 759
|
||||
#define IMX8QM_MIPI0_I2C1_IPG_CLK 760
|
||||
#define IMX8QM_MIPI0_CLK_ROOT 761
|
||||
#define IMX8QM_MIPI1_LIS_IPG_CLK 762
|
||||
#define IMX8QM_MIPI1_I2C0_IPG_S_CLK 763
|
||||
#define IMX8QM_MIPI1_I2C0_IPG_CLK 764
|
||||
#define IMX8QM_MIPI1_I2C1_IPG_S_CLK 765
|
||||
#define IMX8QM_MIPI1_I2C1_IPG_CLK 766
|
||||
#define IMX8QM_MIPI1_CLK_ROOT 767
|
||||
#define IMX8QM_DC0_DISP0_SEL 768
|
||||
#define IMX8QM_DC0_DISP1_SEL 769
|
||||
#define IMX8QM_DC1_DISP0_SEL 770
|
||||
#define IMX8QM_DC1_DISP1_SEL 771
|
||||
|
||||
/* CM40 */
|
||||
#define IMX8QM_CM40_IPG_CLK 772
|
||||
#define IMX8QM_CM40_I2C_DIV 773
|
||||
#define IMX8QM_CM40_I2C_CLK 774
|
||||
#define IMX8QM_CM40_I2C_IPG_CLK 775
|
||||
|
||||
/* CM41 */
|
||||
#define IMX8QM_CM41_IPG_CLK 776
|
||||
#define IMX8QM_CM41_I2C_DIV 777
|
||||
#define IMX8QM_CM41_I2C_CLK 778
|
||||
#define IMX8QM_CM41_I2C_IPG_CLK 779
|
||||
|
||||
#define IMX8QM_HDMI_PXL_SEL 780
|
||||
#define IMX8QM_HDMI_PXL_LINK_SEL 781
|
||||
#define IMX8QM_HDMI_PXL_MUX_SEL 782
|
||||
#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK 783
|
||||
|
||||
#define IMX8QM_HDMI_RX_PXL_SEL 784
|
||||
#define IMX8QM_HDMI_RX_HD_REF_SEL 785
|
||||
#define IMX8QM_HDMI_RX_HD_CORE_SEL 786
|
||||
#define IMX8QM_HDMI_RX_DIG_PLL_CLK 787
|
||||
|
||||
#define IMX8QM_LSIO_MU5A_IPG_S_CLK 788
|
||||
#define IMX8QM_LSIO_MU5A_IPG_CLK 789
|
||||
#define IMX8QM_LSIO_MU6A_IPG_S_CLK 790
|
||||
#define IMX8QM_LSIO_MU6A_IPG_CLK 791
|
||||
|
||||
/* DSP */
|
||||
#define IMX8QM_AUD_DSP_ADB_ACLK 792
|
||||
#define IMX8QM_AUD_DSP_IPG 793
|
||||
#define IMX8QM_AUD_DSP_CORE_CLK 794
|
||||
#define IMX8QM_AUD_OCRAM_IPG 795
|
||||
|
||||
#define IMX8QM_CLK_END 796
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
|
||||
961
include/dt-bindings/pinctrl/pads-imx8qm.h
Normal file
961
include/dt-bindings/pinctrl/pads-imx8qm.h
Normal file
@@ -0,0 +1,961 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef SC_PADS_H
|
||||
#define SC_PADS_H
|
||||
|
||||
#define SC_P_SIM0_CLK 0 /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
|
||||
#define SC_P_SIM0_RST 1 /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
|
||||
#define SC_P_SIM0_IO 2 /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
|
||||
#define SC_P_SIM0_PD 3 /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
|
||||
#define SC_P_SIM0_POWER_EN 4 /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
|
||||
#define SC_P_SIM0_GPIO0_00 5 /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6 /* */
|
||||
#define SC_P_M40_I2C0_SCL 7 /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
|
||||
#define SC_P_M40_I2C0_SDA 8 /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
|
||||
#define SC_P_M40_GPIO0_00 9 /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
|
||||
#define SC_P_M40_GPIO0_01 10 /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
|
||||
#define SC_P_M41_I2C0_SCL 11 /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
|
||||
#define SC_P_M41_I2C0_SDA 12 /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
|
||||
#define SC_P_M41_GPIO0_00 13 /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
|
||||
#define SC_P_M41_GPIO0_01 14 /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
|
||||
#define SC_P_GPT0_CLK 15 /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
|
||||
#define SC_P_GPT0_CAPTURE 16 /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
|
||||
#define SC_P_GPT0_COMPARE 17 /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
|
||||
#define SC_P_GPT1_CLK 18 /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
|
||||
#define SC_P_GPT1_CAPTURE 19 /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
|
||||
#define SC_P_GPT1_COMPARE 20 /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
|
||||
#define SC_P_UART0_RX 21 /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
|
||||
#define SC_P_UART0_TX 22 /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
|
||||
#define SC_P_UART0_RTS_B 23 /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
|
||||
#define SC_P_UART0_CTS_B 24 /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
|
||||
#define SC_P_UART1_TX 25 /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
|
||||
#define SC_P_UART1_RX 26 /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
|
||||
#define SC_P_UART1_RTS_B 27 /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
|
||||
#define SC_P_UART1_CTS_B 28 /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 /* */
|
||||
#define SC_P_SCU_PMIC_MEMC_ON 30 /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
|
||||
#define SC_P_SCU_WDOG_OUT 31 /* SCU.WDOG0.WDOG_OUT */
|
||||
#define SC_P_PMIC_I2C_SDA 32 /* SCU.PMIC_I2C.SDA */
|
||||
#define SC_P_PMIC_I2C_SCL 33 /* SCU.PMIC_I2C.SCL */
|
||||
#define SC_P_PMIC_EARLY_WARNING 34 /* SCU.PMIC_EARLY_WARNING */
|
||||
#define SC_P_PMIC_INT_B 35 /* SCU.DSC.PMIC_INT_B */
|
||||
#define SC_P_SCU_GPIO0_00 36 /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
|
||||
#define SC_P_SCU_GPIO0_01 37 /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
|
||||
#define SC_P_SCU_GPIO0_02 38 /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
|
||||
#define SC_P_SCU_GPIO0_03 39 /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
|
||||
#define SC_P_SCU_GPIO0_04 40 /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
|
||||
#define SC_P_SCU_GPIO0_05 41 /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
|
||||
#define SC_P_SCU_GPIO0_06 42 /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
|
||||
#define SC_P_SCU_GPIO0_07 43 /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
|
||||
#define SC_P_SCU_BOOT_MODE0 44 /* SCU.DSC.BOOT_MODE0 */
|
||||
#define SC_P_SCU_BOOT_MODE1 45 /* SCU.DSC.BOOT_MODE1 */
|
||||
#define SC_P_SCU_BOOT_MODE2 46 /* SCU.DSC.BOOT_MODE2 */
|
||||
#define SC_P_SCU_BOOT_MODE3 47 /* SCU.DSC.BOOT_MODE3 */
|
||||
#define SC_P_SCU_BOOT_MODE4 48 /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
|
||||
#define SC_P_SCU_BOOT_MODE5 49 /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
|
||||
#define SC_P_LVDS0_GPIO00 50 /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
|
||||
#define SC_P_LVDS0_GPIO01 51 /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
|
||||
#define SC_P_LVDS0_I2C0_SCL 52 /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
|
||||
#define SC_P_LVDS0_I2C0_SDA 53 /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
|
||||
#define SC_P_LVDS0_I2C1_SCL 54 /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
|
||||
#define SC_P_LVDS0_I2C1_SDA 55 /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
|
||||
#define SC_P_LVDS1_GPIO00 56 /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
|
||||
#define SC_P_LVDS1_GPIO01 57 /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
|
||||
#define SC_P_LVDS1_I2C0_SCL 58 /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
|
||||
#define SC_P_LVDS1_I2C0_SDA 59 /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
|
||||
#define SC_P_LVDS1_I2C1_SCL 60 /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
|
||||
#define SC_P_LVDS1_I2C1_SDA 61 /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 /* */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL 63 /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA 64 /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00 65 /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01 66 /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL 67 /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA 68 /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00 69 /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01 70 /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 /* */
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT 72 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL 73 /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA 74 /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00 75 /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01 76 /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
|
||||
#define SC_P_MIPI_CSI1_MCLK_OUT 77 /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
|
||||
#define SC_P_MIPI_CSI1_GPIO0_00 78 /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
|
||||
#define SC_P_MIPI_CSI1_GPIO0_01 79 /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
|
||||
#define SC_P_MIPI_CSI1_I2C0_SCL 80 /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
|
||||
#define SC_P_MIPI_CSI1_I2C0_SDA 81 /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
|
||||
#define SC_P_HDMI_TX0_TS_SCL 82 /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
|
||||
#define SC_P_HDMI_TX0_TS_SDA 83 /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
|
||||
#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84 /* */
|
||||
#define SC_P_ESAI1_FSR 85 /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
|
||||
#define SC_P_ESAI1_FST 86 /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
|
||||
#define SC_P_ESAI1_SCKR 87 /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
|
||||
#define SC_P_ESAI1_SCKT 88 /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
|
||||
#define SC_P_ESAI1_TX0 89 /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
|
||||
#define SC_P_ESAI1_TX1 90 /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
|
||||
#define SC_P_ESAI1_TX2_RX3 91 /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
|
||||
#define SC_P_ESAI1_TX3_RX2 92 /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
|
||||
#define SC_P_ESAI1_TX4_RX1 93 /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
|
||||
#define SC_P_ESAI1_TX5_RX0 94 /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
|
||||
#define SC_P_SPDIF0_RX 95 /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
|
||||
#define SC_P_SPDIF0_TX 96 /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
|
||||
#define SC_P_SPDIF0_EXT_CLK 97 /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
|
||||
#define SC_P_SPI3_SCK 98 /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
|
||||
#define SC_P_SPI3_SDO 99 /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
|
||||
#define SC_P_SPI3_SDI 100 /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
|
||||
#define SC_P_SPI3_CS0 101 /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
|
||||
#define SC_P_SPI3_CS1 102 /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 /* */
|
||||
#define SC_P_ESAI0_FSR 104 /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
|
||||
#define SC_P_ESAI0_FST 105 /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
|
||||
#define SC_P_ESAI0_SCKR 106 /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
|
||||
#define SC_P_ESAI0_SCKT 107 /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
|
||||
#define SC_P_ESAI0_TX0 108 /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
|
||||
#define SC_P_ESAI0_TX1 109 /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
|
||||
#define SC_P_ESAI0_TX2_RX3 110 /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
|
||||
#define SC_P_ESAI0_TX3_RX2 111 /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
|
||||
#define SC_P_ESAI0_TX4_RX1 112 /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
|
||||
#define SC_P_ESAI0_TX5_RX0 113 /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
|
||||
#define SC_P_MCLK_IN0 114 /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
|
||||
#define SC_P_MCLK_OUT0 115 /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 /* */
|
||||
#define SC_P_SPI0_SCK 117 /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
|
||||
#define SC_P_SPI0_SDO 118 /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
|
||||
#define SC_P_SPI0_SDI 119 /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
|
||||
#define SC_P_SPI0_CS0 120 /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
|
||||
#define SC_P_SPI0_CS1 121 /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
|
||||
#define SC_P_SPI2_SCK 122 /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
|
||||
#define SC_P_SPI2_SDO 123 /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
|
||||
#define SC_P_SPI2_SDI 124 /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
|
||||
#define SC_P_SPI2_CS0 125 /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
|
||||
#define SC_P_SPI2_CS1 126 /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
|
||||
#define SC_P_SAI1_RXC 127 /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
|
||||
#define SC_P_SAI1_RXD 128 /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
|
||||
#define SC_P_SAI1_RXFS 129 /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
|
||||
#define SC_P_SAI1_TXC 130 /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
|
||||
#define SC_P_SAI1_TXD 131 /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
|
||||
#define SC_P_SAI1_TXFS 132 /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 /* */
|
||||
#define SC_P_ADC_IN7 134 /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
|
||||
#define SC_P_ADC_IN6 135 /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
|
||||
#define SC_P_ADC_IN5 136 /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
|
||||
#define SC_P_ADC_IN4 137 /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
|
||||
#define SC_P_ADC_IN3 138 /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
|
||||
#define SC_P_ADC_IN2 139 /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
|
||||
#define SC_P_ADC_IN1 140 /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
|
||||
#define SC_P_ADC_IN0 141 /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
|
||||
#define SC_P_MLB_SIG 142 /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
|
||||
#define SC_P_MLB_CLK 143 /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
|
||||
#define SC_P_MLB_DATA 144 /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 /* */
|
||||
#define SC_P_FLEXCAN0_RX 146 /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
|
||||
#define SC_P_FLEXCAN0_TX 147 /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
|
||||
#define SC_P_FLEXCAN1_RX 148 /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
|
||||
#define SC_P_FLEXCAN1_TX 149 /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
|
||||
#define SC_P_FLEXCAN2_RX 150 /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
|
||||
#define SC_P_FLEXCAN2_TX 151 /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 /* */
|
||||
#define SC_P_USB_SS3_TC0 153 /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
|
||||
#define SC_P_USB_SS3_TC1 154 /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
|
||||
#define SC_P_USB_SS3_TC2 155 /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
|
||||
#define SC_P_USB_SS3_TC3 156 /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
|
||||
#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157 /* */
|
||||
#define SC_P_USDHC1_RESET_B 158 /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
|
||||
#define SC_P_USDHC1_VSELECT 159 /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
|
||||
#define SC_P_USDHC2_RESET_B 160 /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
|
||||
#define SC_P_USDHC2_VSELECT 161 /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
|
||||
#define SC_P_USDHC2_WP 162 /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
|
||||
#define SC_P_USDHC2_CD_B 163 /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 /* */
|
||||
#define SC_P_ENET0_MDIO 165 /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
|
||||
#define SC_P_ENET0_MDC 166 /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
|
||||
#define SC_P_ENET0_REFCLK_125M_25M 167 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
|
||||
#define SC_P_ENET1_REFCLK_125M_25M 168 /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
|
||||
#define SC_P_ENET1_MDIO 169 /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
|
||||
#define SC_P_ENET1_MDC 170 /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 /* */
|
||||
#define SC_P_QSPI1A_SS0_B 172 /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
|
||||
#define SC_P_QSPI1A_SS1_B 173 /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
|
||||
#define SC_P_QSPI1A_SCLK 174 /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
|
||||
#define SC_P_QSPI1A_DQS 175 /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
|
||||
#define SC_P_QSPI1A_DATA3 176 /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
|
||||
#define SC_P_QSPI1A_DATA2 177 /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
|
||||
#define SC_P_QSPI1A_DATA1 178 /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
|
||||
#define SC_P_QSPI1A_DATA0 179 /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 /* */
|
||||
#define SC_P_QSPI0A_DATA0 181 /* LSIO.QSPI0A.DATA0 */
|
||||
#define SC_P_QSPI0A_DATA1 182 /* LSIO.QSPI0A.DATA1 */
|
||||
#define SC_P_QSPI0A_DATA2 183 /* LSIO.QSPI0A.DATA2 */
|
||||
#define SC_P_QSPI0A_DATA3 184 /* LSIO.QSPI0A.DATA3 */
|
||||
#define SC_P_QSPI0A_DQS 185 /* LSIO.QSPI0A.DQS */
|
||||
#define SC_P_QSPI0A_SS0_B 186 /* LSIO.QSPI0A.SS0_B */
|
||||
#define SC_P_QSPI0A_SS1_B 187 /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
|
||||
#define SC_P_QSPI0A_SCLK 188 /* LSIO.QSPI0A.SCLK */
|
||||
#define SC_P_QSPI0B_SCLK 189 /* LSIO.QSPI0B.SCLK */
|
||||
#define SC_P_QSPI0B_DATA0 190 /* LSIO.QSPI0B.DATA0 */
|
||||
#define SC_P_QSPI0B_DATA1 191 /* LSIO.QSPI0B.DATA1 */
|
||||
#define SC_P_QSPI0B_DATA2 192 /* LSIO.QSPI0B.DATA2 */
|
||||
#define SC_P_QSPI0B_DATA3 193 /* LSIO.QSPI0B.DATA3 */
|
||||
#define SC_P_QSPI0B_DQS 194 /* LSIO.QSPI0B.DQS */
|
||||
#define SC_P_QSPI0B_SS0_B 195 /* LSIO.QSPI0B.SS0_B */
|
||||
#define SC_P_QSPI0B_SS1_B 196 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 /* */
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B 198 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B 199 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
|
||||
#define SC_P_PCIE_CTRL0_PERST_B 200 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
|
||||
#define SC_P_PCIE_CTRL1_CLKREQ_B 201 /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
|
||||
#define SC_P_PCIE_CTRL1_WAKE_B 202 /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
|
||||
#define SC_P_PCIE_CTRL1_PERST_B 203 /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 /* */
|
||||
#define SC_P_USB_HSIC0_DATA 205 /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
|
||||
#define SC_P_USB_HSIC0_STROBE 206 /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
|
||||
#define SC_P_CALIBRATION_0_HSIC 207 /* */
|
||||
#define SC_P_CALIBRATION_1_HSIC 208 /* */
|
||||
#define SC_P_EMMC0_CLK 209 /* CONN.EMMC0.CLK, CONN.NAND.READY_B */
|
||||
#define SC_P_EMMC0_CMD 210 /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
|
||||
#define SC_P_EMMC0_DATA0 211 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
|
||||
#define SC_P_EMMC0_DATA1 212 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
|
||||
#define SC_P_EMMC0_DATA2 213 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
|
||||
#define SC_P_EMMC0_DATA3 214 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
|
||||
#define SC_P_EMMC0_DATA4 215 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
|
||||
#define SC_P_EMMC0_DATA5 216 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
|
||||
#define SC_P_EMMC0_DATA6 217 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
|
||||
#define SC_P_EMMC0_DATA7 218 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
|
||||
#define SC_P_EMMC0_STROBE 219 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
|
||||
#define SC_P_EMMC0_RESET_B 220 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 /* */
|
||||
#define SC_P_USDHC1_CLK 222 /* CONN.USDHC1.CLK, AUD.MQS.R */
|
||||
#define SC_P_USDHC1_CMD 223 /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
|
||||
#define SC_P_USDHC1_DATA0 224 /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
|
||||
#define SC_P_USDHC1_DATA1 225 /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
|
||||
#define SC_P_CTL_NAND_RE_P_N 226 /* */
|
||||
#define SC_P_USDHC1_DATA2 227 /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
|
||||
#define SC_P_USDHC1_DATA3 228 /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
|
||||
#define SC_P_CTL_NAND_DQS_P_N 229 /* */
|
||||
#define SC_P_USDHC1_DATA4 230 /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
|
||||
#define SC_P_USDHC1_DATA5 231 /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
|
||||
#define SC_P_USDHC1_DATA6 232 /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
|
||||
#define SC_P_USDHC1_DATA7 233 /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
|
||||
#define SC_P_USDHC1_STROBE 234 /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 /* */
|
||||
#define SC_P_USDHC2_CLK 236 /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
|
||||
#define SC_P_USDHC2_CMD 237 /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
|
||||
#define SC_P_USDHC2_DATA0 238 /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
|
||||
#define SC_P_USDHC2_DATA1 239 /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
|
||||
#define SC_P_USDHC2_DATA2 240 /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
|
||||
#define SC_P_USDHC2_DATA3 241 /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 /* */
|
||||
#define SC_P_ENET0_RGMII_TXC 243 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
|
||||
#define SC_P_ENET0_RGMII_TX_CTL 244 /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
|
||||
#define SC_P_ENET0_RGMII_TXD0 245 /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
|
||||
#define SC_P_ENET0_RGMII_TXD1 246 /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
|
||||
#define SC_P_ENET0_RGMII_TXD2 247 /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
|
||||
#define SC_P_ENET0_RGMII_TXD3 248 /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
|
||||
#define SC_P_ENET0_RGMII_RXC 249 /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
|
||||
#define SC_P_ENET0_RGMII_RX_CTL 250 /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
|
||||
#define SC_P_ENET0_RGMII_RXD0 251 /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
|
||||
#define SC_P_ENET0_RGMII_RXD1 252 /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
|
||||
#define SC_P_ENET0_RGMII_RXD2 253 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
|
||||
#define SC_P_ENET0_RGMII_RXD3 254 /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 /* */
|
||||
#define SC_P_ENET1_RGMII_TXC 256 /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
|
||||
#define SC_P_ENET1_RGMII_TX_CTL 257 /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
|
||||
#define SC_P_ENET1_RGMII_TXD0 258 /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
|
||||
#define SC_P_ENET1_RGMII_TXD1 259 /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
|
||||
#define SC_P_ENET1_RGMII_TXD2 260 /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
|
||||
#define SC_P_ENET1_RGMII_TXD3 261 /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
|
||||
#define SC_P_ENET1_RGMII_RXC 262 /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
|
||||
#define SC_P_ENET1_RGMII_RX_CTL 263 /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
|
||||
#define SC_P_ENET1_RGMII_RXD0 264 /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
|
||||
#define SC_P_ENET1_RGMII_RXD1 265 /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
|
||||
#define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
|
||||
#define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Pad Mux Definitions
|
||||
* format: name padid padmux
|
||||
*/
|
||||
/*@{*/
|
||||
#define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0
|
||||
#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3
|
||||
#define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0
|
||||
#define SC_P_SIM0_RST_LSIO_GPIO0_IO01 SC_P_SIM0_RST 3
|
||||
#define SC_P_SIM0_IO_DMA_SIM0_IO SC_P_SIM0_IO 0
|
||||
#define SC_P_SIM0_IO_LSIO_GPIO0_IO02 SC_P_SIM0_IO 3
|
||||
#define SC_P_SIM0_PD_DMA_SIM0_PD SC_P_SIM0_PD 0
|
||||
#define SC_P_SIM0_PD_DMA_I2C3_SCL SC_P_SIM0_PD 1
|
||||
#define SC_P_SIM0_PD_LSIO_GPIO0_IO03 SC_P_SIM0_PD 3
|
||||
#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN SC_P_SIM0_POWER_EN 0
|
||||
#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA SC_P_SIM0_POWER_EN 1
|
||||
#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04 SC_P_SIM0_POWER_EN 3
|
||||
#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN SC_P_SIM0_GPIO0_00 0
|
||||
#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 SC_P_SIM0_GPIO0_00 3
|
||||
#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL SC_P_M40_I2C0_SCL 0
|
||||
#define SC_P_M40_I2C0_SCL_M40_UART0_RX SC_P_M40_I2C0_SCL 1
|
||||
#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02 SC_P_M40_I2C0_SCL 2
|
||||
#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 SC_P_M40_I2C0_SCL 3
|
||||
#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA SC_P_M40_I2C0_SDA 0
|
||||
#define SC_P_M40_I2C0_SDA_M40_UART0_TX SC_P_M40_I2C0_SDA 1
|
||||
#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03 SC_P_M40_I2C0_SDA 2
|
||||
#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 SC_P_M40_I2C0_SDA 3
|
||||
#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00 SC_P_M40_GPIO0_00 0
|
||||
#define SC_P_M40_GPIO0_00_M40_TPM0_CH0 SC_P_M40_GPIO0_00 1
|
||||
#define SC_P_M40_GPIO0_00_DMA_UART4_RX SC_P_M40_GPIO0_00 2
|
||||
#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 SC_P_M40_GPIO0_00 3
|
||||
#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01 SC_P_M40_GPIO0_01 0
|
||||
#define SC_P_M40_GPIO0_01_M40_TPM0_CH1 SC_P_M40_GPIO0_01 1
|
||||
#define SC_P_M40_GPIO0_01_DMA_UART4_TX SC_P_M40_GPIO0_01 2
|
||||
#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 SC_P_M40_GPIO0_01 3
|
||||
#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL SC_P_M41_I2C0_SCL 0
|
||||
#define SC_P_M41_I2C0_SCL_M41_UART0_RX SC_P_M41_I2C0_SCL 1
|
||||
#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02 SC_P_M41_I2C0_SCL 2
|
||||
#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 SC_P_M41_I2C0_SCL 3
|
||||
#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA SC_P_M41_I2C0_SDA 0
|
||||
#define SC_P_M41_I2C0_SDA_M41_UART0_TX SC_P_M41_I2C0_SDA 1
|
||||
#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03 SC_P_M41_I2C0_SDA 2
|
||||
#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 SC_P_M41_I2C0_SDA 3
|
||||
#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00 SC_P_M41_GPIO0_00 0
|
||||
#define SC_P_M41_GPIO0_00_M41_TPM0_CH0 SC_P_M41_GPIO0_00 1
|
||||
#define SC_P_M41_GPIO0_00_DMA_UART3_RX SC_P_M41_GPIO0_00 2
|
||||
#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 SC_P_M41_GPIO0_00 3
|
||||
#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01 SC_P_M41_GPIO0_01 0
|
||||
#define SC_P_M41_GPIO0_01_M41_TPM0_CH1 SC_P_M41_GPIO0_01 1
|
||||
#define SC_P_M41_GPIO0_01_DMA_UART3_TX SC_P_M41_GPIO0_01 2
|
||||
#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 SC_P_M41_GPIO0_01 3
|
||||
#define SC_P_GPT0_CLK_LSIO_GPT0_CLK SC_P_GPT0_CLK 0
|
||||
#define SC_P_GPT0_CLK_DMA_I2C1_SCL SC_P_GPT0_CLK 1
|
||||
#define SC_P_GPT0_CLK_LSIO_KPP0_COL4 SC_P_GPT0_CLK 2
|
||||
#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14 SC_P_GPT0_CLK 3
|
||||
#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE SC_P_GPT0_CAPTURE 0
|
||||
#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA SC_P_GPT0_CAPTURE 1
|
||||
#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5 SC_P_GPT0_CAPTURE 2
|
||||
#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15 SC_P_GPT0_CAPTURE 3
|
||||
#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE SC_P_GPT0_COMPARE 0
|
||||
#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT SC_P_GPT0_COMPARE 1
|
||||
#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6 SC_P_GPT0_COMPARE 2
|
||||
#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 SC_P_GPT0_COMPARE 3
|
||||
#define SC_P_GPT1_CLK_LSIO_GPT1_CLK SC_P_GPT1_CLK 0
|
||||
#define SC_P_GPT1_CLK_DMA_I2C2_SCL SC_P_GPT1_CLK 1
|
||||
#define SC_P_GPT1_CLK_LSIO_KPP0_COL7 SC_P_GPT1_CLK 2
|
||||
#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17 SC_P_GPT1_CLK 3
|
||||
#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE SC_P_GPT1_CAPTURE 0
|
||||
#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA SC_P_GPT1_CAPTURE 1
|
||||
#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4 SC_P_GPT1_CAPTURE 2
|
||||
#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18 SC_P_GPT1_CAPTURE 3
|
||||
#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE SC_P_GPT1_COMPARE 0
|
||||
#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT SC_P_GPT1_COMPARE 1
|
||||
#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5 SC_P_GPT1_COMPARE 2
|
||||
#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 SC_P_GPT1_COMPARE 3
|
||||
#define SC_P_UART0_RX_DMA_UART0_RX SC_P_UART0_RX 0
|
||||
#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 1
|
||||
#define SC_P_UART0_RX_LSIO_GPIO0_IO20 SC_P_UART0_RX 3
|
||||
#define SC_P_UART0_TX_DMA_UART0_TX SC_P_UART0_TX 0
|
||||
#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 1
|
||||
#define SC_P_UART0_TX_LSIO_GPIO0_IO21 SC_P_UART0_TX 3
|
||||
#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B SC_P_UART0_RTS_B 0
|
||||
#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT SC_P_UART0_RTS_B 1
|
||||
#define SC_P_UART0_RTS_B_DMA_UART2_RX SC_P_UART0_RTS_B 2
|
||||
#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 SC_P_UART0_RTS_B 3
|
||||
#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B SC_P_UART0_CTS_B 0
|
||||
#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT SC_P_UART0_CTS_B 1
|
||||
#define SC_P_UART0_CTS_B_DMA_UART2_TX SC_P_UART0_CTS_B 2
|
||||
#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 SC_P_UART0_CTS_B 3
|
||||
#define SC_P_UART1_TX_DMA_UART1_TX SC_P_UART1_TX 0
|
||||
#define SC_P_UART1_TX_DMA_SPI3_SCK SC_P_UART1_TX 1
|
||||
#define SC_P_UART1_TX_LSIO_GPIO0_IO24 SC_P_UART1_TX 3
|
||||
#define SC_P_UART1_RX_DMA_UART1_RX SC_P_UART1_RX 0
|
||||
#define SC_P_UART1_RX_DMA_SPI3_SDO SC_P_UART1_RX 1
|
||||
#define SC_P_UART1_RX_LSIO_GPIO0_IO25 SC_P_UART1_RX 3
|
||||
#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B SC_P_UART1_RTS_B 0
|
||||
#define SC_P_UART1_RTS_B_DMA_SPI3_SDI SC_P_UART1_RTS_B 1
|
||||
#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B SC_P_UART1_RTS_B 2
|
||||
#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26 SC_P_UART1_RTS_B 3
|
||||
#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B SC_P_UART1_CTS_B 0
|
||||
#define SC_P_UART1_CTS_B_DMA_SPI3_CS0 SC_P_UART1_CTS_B 1
|
||||
#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B SC_P_UART1_CTS_B 2
|
||||
#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27 SC_P_UART1_CTS_B 3
|
||||
#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON SC_P_SCU_PMIC_MEMC_ON 0
|
||||
#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT SC_P_SCU_WDOG_OUT 0
|
||||
#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
|
||||
#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
|
||||
#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING SC_P_PMIC_EARLY_WARNING 0
|
||||
#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
|
||||
#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
|
||||
#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
|
||||
#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28 SC_P_SCU_GPIO0_00 3
|
||||
#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
|
||||
#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
|
||||
#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29 SC_P_SCU_GPIO0_01 3
|
||||
#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02 SC_P_SCU_GPIO0_02 0
|
||||
#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON SC_P_SCU_GPIO0_02 1
|
||||
#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 SC_P_SCU_GPIO0_02 3
|
||||
#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03 SC_P_SCU_GPIO0_03 0
|
||||
#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON SC_P_SCU_GPIO0_03 1
|
||||
#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 SC_P_SCU_GPIO0_03 3
|
||||
#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04 SC_P_SCU_GPIO0_04 0
|
||||
#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON SC_P_SCU_GPIO0_04 1
|
||||
#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00 SC_P_SCU_GPIO0_04 3
|
||||
#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05 SC_P_SCU_GPIO0_05 0
|
||||
#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON SC_P_SCU_GPIO0_05 1
|
||||
#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 SC_P_SCU_GPIO0_05 3
|
||||
#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06 SC_P_SCU_GPIO0_06 0
|
||||
#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0 SC_P_SCU_GPIO0_06 1
|
||||
#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 SC_P_SCU_GPIO0_06 3
|
||||
#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07 SC_P_SCU_GPIO0_07 0
|
||||
#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1 SC_P_SCU_GPIO0_07 1
|
||||
#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_GPIO0_07 2
|
||||
#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03 SC_P_SCU_GPIO0_07 3
|
||||
#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
|
||||
#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
|
||||
#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
|
||||
#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
|
||||
#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 SC_P_SCU_BOOT_MODE4 0
|
||||
#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE4 1
|
||||
#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 SC_P_SCU_BOOT_MODE5 0
|
||||
#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE5 1
|
||||
#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00 SC_P_LVDS0_GPIO00 0
|
||||
#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT SC_P_LVDS0_GPIO00 1
|
||||
#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 SC_P_LVDS0_GPIO00 3
|
||||
#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01 SC_P_LVDS0_GPIO01 0
|
||||
#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05 SC_P_LVDS0_GPIO01 3
|
||||
#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL SC_P_LVDS0_I2C0_SCL 0
|
||||
#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 SC_P_LVDS0_I2C0_SCL 1
|
||||
#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 SC_P_LVDS0_I2C0_SCL 3
|
||||
#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA SC_P_LVDS0_I2C0_SDA 0
|
||||
#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 SC_P_LVDS0_I2C0_SDA 1
|
||||
#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 SC_P_LVDS0_I2C0_SDA 3
|
||||
#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL SC_P_LVDS0_I2C1_SCL 0
|
||||
#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX SC_P_LVDS0_I2C1_SCL 1
|
||||
#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 SC_P_LVDS0_I2C1_SCL 3
|
||||
#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA SC_P_LVDS0_I2C1_SDA 0
|
||||
#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX SC_P_LVDS0_I2C1_SDA 1
|
||||
#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 SC_P_LVDS0_I2C1_SDA 3
|
||||
#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 SC_P_LVDS1_GPIO00 0
|
||||
#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT SC_P_LVDS1_GPIO00 1
|
||||
#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10 SC_P_LVDS1_GPIO00 3
|
||||
#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01 SC_P_LVDS1_GPIO01 0
|
||||
#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 SC_P_LVDS1_GPIO01 3
|
||||
#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL SC_P_LVDS1_I2C0_SCL 0
|
||||
#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 SC_P_LVDS1_I2C0_SCL 1
|
||||
#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 SC_P_LVDS1_I2C0_SCL 3
|
||||
#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA SC_P_LVDS1_I2C0_SDA 0
|
||||
#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 SC_P_LVDS1_I2C0_SDA 1
|
||||
#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 SC_P_LVDS1_I2C0_SDA 3
|
||||
#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL SC_P_LVDS1_I2C1_SCL 0
|
||||
#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX SC_P_LVDS1_I2C1_SCL 1
|
||||
#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 SC_P_LVDS1_I2C1_SCL 3
|
||||
#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA SC_P_LVDS1_I2C1_SDA 0
|
||||
#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX SC_P_LVDS1_I2C1_SDA 1
|
||||
#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 SC_P_LVDS1_I2C1_SDA 3
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
|
||||
#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 SC_P_MIPI_DSI0_I2C0_SCL 3
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
|
||||
#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 SC_P_MIPI_DSI0_I2C0_SDA 3
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 1
|
||||
#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 SC_P_MIPI_DSI0_GPIO0_00 3
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
|
||||
#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 SC_P_MIPI_DSI0_GPIO0_01 3
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
|
||||
#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 SC_P_MIPI_DSI1_I2C0_SCL 3
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
|
||||
#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 SC_P_MIPI_DSI1_I2C0_SDA 3
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 1
|
||||
#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 SC_P_MIPI_DSI1_GPIO0_00 3
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
|
||||
#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 SC_P_MIPI_DSI1_GPIO0_01 3
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
|
||||
#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 SC_P_MIPI_CSI0_MCLK_OUT 3
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
|
||||
#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_CSI0_I2C0_SCL 3
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
|
||||
#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_CSI0_I2C0_SDA 3
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 2
|
||||
#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_CSI0_GPIO0_00 3
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 2
|
||||
#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_CSI0_GPIO0_01 3
|
||||
#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT SC_P_MIPI_CSI1_MCLK_OUT 0
|
||||
#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 SC_P_MIPI_CSI1_MCLK_OUT 3
|
||||
#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 SC_P_MIPI_CSI1_GPIO0_00 0
|
||||
#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX SC_P_MIPI_CSI1_GPIO0_00 1
|
||||
#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 SC_P_MIPI_CSI1_GPIO0_00 3
|
||||
#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 SC_P_MIPI_CSI1_GPIO0_01 0
|
||||
#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX SC_P_MIPI_CSI1_GPIO0_01 1
|
||||
#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 SC_P_MIPI_CSI1_GPIO0_01 3
|
||||
#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL SC_P_MIPI_CSI1_I2C0_SCL 0
|
||||
#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 SC_P_MIPI_CSI1_I2C0_SCL 3
|
||||
#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA SC_P_MIPI_CSI1_I2C0_SDA 0
|
||||
#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 SC_P_MIPI_CSI1_I2C0_SDA 3
|
||||
#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 0
|
||||
#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL SC_P_HDMI_TX0_TS_SCL 1
|
||||
#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 SC_P_HDMI_TX0_TS_SCL 3
|
||||
#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 0
|
||||
#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA SC_P_HDMI_TX0_TS_SDA 1
|
||||
#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 SC_P_HDMI_TX0_TS_SDA 3
|
||||
#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR SC_P_ESAI1_FSR 0
|
||||
#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 SC_P_ESAI1_FSR 3
|
||||
#define SC_P_ESAI1_FST_AUD_ESAI1_FST SC_P_ESAI1_FST 0
|
||||
#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_FST 1
|
||||
#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05 SC_P_ESAI1_FST 3
|
||||
#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR SC_P_ESAI1_SCKR 0
|
||||
#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06 SC_P_ESAI1_SCKR 3
|
||||
#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT SC_P_ESAI1_SCKT 0
|
||||
#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC SC_P_ESAI1_SCKT 1
|
||||
#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK SC_P_ESAI1_SCKT 2
|
||||
#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 SC_P_ESAI1_SCKT 3
|
||||
#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0 SC_P_ESAI1_TX0 0
|
||||
#define SC_P_ESAI1_TX0_AUD_SAI2_RXD SC_P_ESAI1_TX0 1
|
||||
#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX SC_P_ESAI1_TX0 2
|
||||
#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 SC_P_ESAI1_TX0 3
|
||||
#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1 SC_P_ESAI1_TX1 0
|
||||
#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS SC_P_ESAI1_TX1 1
|
||||
#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX SC_P_ESAI1_TX1 2
|
||||
#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 SC_P_ESAI1_TX1 3
|
||||
#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 SC_P_ESAI1_TX2_RX3 0
|
||||
#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX SC_P_ESAI1_TX2_RX3 1
|
||||
#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 SC_P_ESAI1_TX2_RX3 3
|
||||
#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 SC_P_ESAI1_TX3_RX2 0
|
||||
#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX SC_P_ESAI1_TX3_RX2 1
|
||||
#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 SC_P_ESAI1_TX3_RX2 3
|
||||
#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 SC_P_ESAI1_TX4_RX1 0
|
||||
#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 SC_P_ESAI1_TX4_RX1 3
|
||||
#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 SC_P_ESAI1_TX5_RX0 0
|
||||
#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 SC_P_ESAI1_TX5_RX0 3
|
||||
#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX SC_P_SPDIF0_RX 0
|
||||
#define SC_P_SPDIF0_RX_AUD_MQS_R SC_P_SPDIF0_RX 1
|
||||
#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1 SC_P_SPDIF0_RX 2
|
||||
#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14 SC_P_SPDIF0_RX 3
|
||||
#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX SC_P_SPDIF0_TX 0
|
||||
#define SC_P_SPDIF0_TX_AUD_MQS_L SC_P_SPDIF0_TX 1
|
||||
#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1 SC_P_SPDIF0_TX 2
|
||||
#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 SC_P_SPDIF0_TX 3
|
||||
#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
|
||||
#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 SC_P_SPDIF0_EXT_CLK 1
|
||||
#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 SC_P_SPDIF0_EXT_CLK 3
|
||||
#define SC_P_SPI3_SCK_DMA_SPI3_SCK SC_P_SPI3_SCK 0
|
||||
#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17 SC_P_SPI3_SCK 3
|
||||
#define SC_P_SPI3_SDO_DMA_SPI3_SDO SC_P_SPI3_SDO 0
|
||||
#define SC_P_SPI3_SDO_DMA_FTM_CH0 SC_P_SPI3_SDO 1
|
||||
#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18 SC_P_SPI3_SDO 3
|
||||
#define SC_P_SPI3_SDI_DMA_SPI3_SDI SC_P_SPI3_SDI 0
|
||||
#define SC_P_SPI3_SDI_DMA_FTM_CH1 SC_P_SPI3_SDI 1
|
||||
#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19 SC_P_SPI3_SDI 3
|
||||
#define SC_P_SPI3_CS0_DMA_SPI3_CS0 SC_P_SPI3_CS0 0
|
||||
#define SC_P_SPI3_CS0_DMA_FTM_CH2 SC_P_SPI3_CS0 1
|
||||
#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20 SC_P_SPI3_CS0 3
|
||||
#define SC_P_SPI3_CS1_DMA_SPI3_CS1 SC_P_SPI3_CS1 0
|
||||
#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21 SC_P_SPI3_CS1 3
|
||||
#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR SC_P_ESAI0_FSR 0
|
||||
#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 SC_P_ESAI0_FSR 3
|
||||
#define SC_P_ESAI0_FST_AUD_ESAI0_FST SC_P_ESAI0_FST 0
|
||||
#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23 SC_P_ESAI0_FST 3
|
||||
#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR SC_P_ESAI0_SCKR 0
|
||||
#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 SC_P_ESAI0_SCKR 3
|
||||
#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT SC_P_ESAI0_SCKT 0
|
||||
#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 SC_P_ESAI0_SCKT 3
|
||||
#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0 SC_P_ESAI0_TX0 0
|
||||
#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 SC_P_ESAI0_TX0 3
|
||||
#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1 SC_P_ESAI0_TX1 0
|
||||
#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 SC_P_ESAI0_TX1 3
|
||||
#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
|
||||
#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 SC_P_ESAI0_TX2_RX3 3
|
||||
#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
|
||||
#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 SC_P_ESAI0_TX3_RX2 3
|
||||
#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
|
||||
#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 SC_P_ESAI0_TX4_RX1 3
|
||||
#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
|
||||
#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 SC_P_ESAI0_TX5_RX0 3
|
||||
#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
|
||||
#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
|
||||
#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK SC_P_MCLK_IN0 2
|
||||
#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00 SC_P_MCLK_IN0 3
|
||||
#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
|
||||
#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
|
||||
#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK SC_P_MCLK_OUT0 2
|
||||
#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01 SC_P_MCLK_OUT0 3
|
||||
#define SC_P_SPI0_SCK_DMA_SPI0_SCK SC_P_SPI0_SCK 0
|
||||
#define SC_P_SPI0_SCK_AUD_SAI0_RXC SC_P_SPI0_SCK 1
|
||||
#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02 SC_P_SPI0_SCK 3
|
||||
#define SC_P_SPI0_SDO_DMA_SPI0_SDO SC_P_SPI0_SDO 0
|
||||
#define SC_P_SPI0_SDO_AUD_SAI0_TXD SC_P_SPI0_SDO 1
|
||||
#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03 SC_P_SPI0_SDO 3
|
||||
#define SC_P_SPI0_SDI_DMA_SPI0_SDI SC_P_SPI0_SDI 0
|
||||
#define SC_P_SPI0_SDI_AUD_SAI0_RXD SC_P_SPI0_SDI 1
|
||||
#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04 SC_P_SPI0_SDI 3
|
||||
#define SC_P_SPI0_CS0_DMA_SPI0_CS0 SC_P_SPI0_CS0 0
|
||||
#define SC_P_SPI0_CS0_AUD_SAI0_RXFS SC_P_SPI0_CS0 1
|
||||
#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05 SC_P_SPI0_CS0 3
|
||||
#define SC_P_SPI0_CS1_DMA_SPI0_CS1 SC_P_SPI0_CS1 0
|
||||
#define SC_P_SPI0_CS1_AUD_SAI0_TXC SC_P_SPI0_CS1 1
|
||||
#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06 SC_P_SPI0_CS1 3
|
||||
#define SC_P_SPI2_SCK_DMA_SPI2_SCK SC_P_SPI2_SCK 0
|
||||
#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07 SC_P_SPI2_SCK 3
|
||||
#define SC_P_SPI2_SDO_DMA_SPI2_SDO SC_P_SPI2_SDO 0
|
||||
#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08 SC_P_SPI2_SDO 3
|
||||
#define SC_P_SPI2_SDI_DMA_SPI2_SDI SC_P_SPI2_SDI 0
|
||||
#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09 SC_P_SPI2_SDI 3
|
||||
#define SC_P_SPI2_CS0_DMA_SPI2_CS0 SC_P_SPI2_CS0 0
|
||||
#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10 SC_P_SPI2_CS0 3
|
||||
#define SC_P_SPI2_CS1_DMA_SPI2_CS1 SC_P_SPI2_CS1 0
|
||||
#define SC_P_SPI2_CS1_AUD_SAI0_TXFS SC_P_SPI2_CS1 1
|
||||
#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11 SC_P_SPI2_CS1 3
|
||||
#define SC_P_SAI1_RXC_AUD_SAI1_RXC SC_P_SAI1_RXC 0
|
||||
#define SC_P_SAI1_RXC_AUD_SAI0_TXD SC_P_SAI1_RXC 1
|
||||
#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12 SC_P_SAI1_RXC 3
|
||||
#define SC_P_SAI1_RXD_AUD_SAI1_RXD SC_P_SAI1_RXD 0
|
||||
#define SC_P_SAI1_RXD_AUD_SAI0_TXFS SC_P_SAI1_RXD 1
|
||||
#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13 SC_P_SAI1_RXD 3
|
||||
#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS SC_P_SAI1_RXFS 0
|
||||
#define SC_P_SAI1_RXFS_AUD_SAI0_RXD SC_P_SAI1_RXFS 1
|
||||
#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 SC_P_SAI1_RXFS 3
|
||||
#define SC_P_SAI1_TXC_AUD_SAI1_TXC SC_P_SAI1_TXC 0
|
||||
#define SC_P_SAI1_TXC_AUD_SAI0_TXC SC_P_SAI1_TXC 1
|
||||
#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15 SC_P_SAI1_TXC 3
|
||||
#define SC_P_SAI1_TXD_AUD_SAI1_TXD SC_P_SAI1_TXD 0
|
||||
#define SC_P_SAI1_TXD_AUD_SAI1_RXC SC_P_SAI1_TXD 1
|
||||
#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16 SC_P_SAI1_TXD 3
|
||||
#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS SC_P_SAI1_TXFS 0
|
||||
#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS SC_P_SAI1_TXFS 1
|
||||
#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17 SC_P_SAI1_TXFS 3
|
||||
#define SC_P_ADC_IN7_DMA_ADC1_IN3 SC_P_ADC_IN7 0
|
||||
#define SC_P_ADC_IN7_DMA_SPI1_CS1 SC_P_ADC_IN7 1
|
||||
#define SC_P_ADC_IN7_LSIO_KPP0_ROW3 SC_P_ADC_IN7 2
|
||||
#define SC_P_ADC_IN7_LSIO_GPIO3_IO25 SC_P_ADC_IN7 3
|
||||
#define SC_P_ADC_IN6_DMA_ADC1_IN2 SC_P_ADC_IN6 0
|
||||
#define SC_P_ADC_IN6_DMA_SPI1_CS0 SC_P_ADC_IN6 1
|
||||
#define SC_P_ADC_IN6_LSIO_KPP0_ROW2 SC_P_ADC_IN6 2
|
||||
#define SC_P_ADC_IN6_LSIO_GPIO3_IO24 SC_P_ADC_IN6 3
|
||||
#define SC_P_ADC_IN5_DMA_ADC1_IN1 SC_P_ADC_IN5 0
|
||||
#define SC_P_ADC_IN5_DMA_SPI1_SDI SC_P_ADC_IN5 1
|
||||
#define SC_P_ADC_IN5_LSIO_KPP0_ROW1 SC_P_ADC_IN5 2
|
||||
#define SC_P_ADC_IN5_LSIO_GPIO3_IO23 SC_P_ADC_IN5 3
|
||||
#define SC_P_ADC_IN4_DMA_ADC1_IN0 SC_P_ADC_IN4 0
|
||||
#define SC_P_ADC_IN4_DMA_SPI1_SDO SC_P_ADC_IN4 1
|
||||
#define SC_P_ADC_IN4_LSIO_KPP0_ROW0 SC_P_ADC_IN4 2
|
||||
#define SC_P_ADC_IN4_LSIO_GPIO3_IO22 SC_P_ADC_IN4 3
|
||||
#define SC_P_ADC_IN3_DMA_ADC0_IN3 SC_P_ADC_IN3 0
|
||||
#define SC_P_ADC_IN3_DMA_SPI1_SCK SC_P_ADC_IN3 1
|
||||
#define SC_P_ADC_IN3_LSIO_KPP0_COL3 SC_P_ADC_IN3 2
|
||||
#define SC_P_ADC_IN3_LSIO_GPIO3_IO21 SC_P_ADC_IN3 3
|
||||
#define SC_P_ADC_IN2_DMA_ADC0_IN2 SC_P_ADC_IN2 0
|
||||
#define SC_P_ADC_IN2_LSIO_KPP0_COL2 SC_P_ADC_IN2 2
|
||||
#define SC_P_ADC_IN2_LSIO_GPIO3_IO20 SC_P_ADC_IN2 3
|
||||
#define SC_P_ADC_IN1_DMA_ADC0_IN1 SC_P_ADC_IN1 0
|
||||
#define SC_P_ADC_IN1_LSIO_KPP0_COL1 SC_P_ADC_IN1 2
|
||||
#define SC_P_ADC_IN1_LSIO_GPIO3_IO19 SC_P_ADC_IN1 3
|
||||
#define SC_P_ADC_IN0_DMA_ADC0_IN0 SC_P_ADC_IN0 0
|
||||
#define SC_P_ADC_IN0_LSIO_KPP0_COL0 SC_P_ADC_IN0 2
|
||||
#define SC_P_ADC_IN0_LSIO_GPIO3_IO18 SC_P_ADC_IN0 3
|
||||
#define SC_P_MLB_SIG_CONN_MLB_SIG SC_P_MLB_SIG 0
|
||||
#define SC_P_MLB_SIG_AUD_SAI3_RXC SC_P_MLB_SIG 1
|
||||
#define SC_P_MLB_SIG_LSIO_GPIO3_IO26 SC_P_MLB_SIG 3
|
||||
#define SC_P_MLB_CLK_CONN_MLB_CLK SC_P_MLB_CLK 0
|
||||
#define SC_P_MLB_CLK_AUD_SAI3_RXFS SC_P_MLB_CLK 1
|
||||
#define SC_P_MLB_CLK_LSIO_GPIO3_IO27 SC_P_MLB_CLK 3
|
||||
#define SC_P_MLB_DATA_CONN_MLB_DATA SC_P_MLB_DATA 0
|
||||
#define SC_P_MLB_DATA_AUD_SAI3_RXD SC_P_MLB_DATA 1
|
||||
#define SC_P_MLB_DATA_LSIO_GPIO3_IO28 SC_P_MLB_DATA 3
|
||||
#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
|
||||
#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29 SC_P_FLEXCAN0_RX 3
|
||||
#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
|
||||
#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30 SC_P_FLEXCAN0_TX 3
|
||||
#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
|
||||
#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 SC_P_FLEXCAN1_RX 3
|
||||
#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
|
||||
#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 SC_P_FLEXCAN1_TX 3
|
||||
#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
|
||||
#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 SC_P_FLEXCAN2_RX 3
|
||||
#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
|
||||
#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 SC_P_FLEXCAN2_TX 3
|
||||
#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL SC_P_USB_SS3_TC0 0
|
||||
#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
|
||||
#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 3
|
||||
#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL SC_P_USB_SS3_TC1 0
|
||||
#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
|
||||
#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 3
|
||||
#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA SC_P_USB_SS3_TC2 0
|
||||
#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
|
||||
#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 3
|
||||
#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA SC_P_USB_SS3_TC3 0
|
||||
#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
|
||||
#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 3
|
||||
#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
|
||||
#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 SC_P_USDHC1_RESET_B 3
|
||||
#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
|
||||
#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 SC_P_USDHC1_VSELECT 3
|
||||
#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B SC_P_USDHC2_RESET_B 0
|
||||
#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 SC_P_USDHC2_RESET_B 3
|
||||
#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT SC_P_USDHC2_VSELECT 0
|
||||
#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10 SC_P_USDHC2_VSELECT 3
|
||||
#define SC_P_USDHC2_WP_CONN_USDHC2_WP SC_P_USDHC2_WP 0
|
||||
#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11 SC_P_USDHC2_WP 3
|
||||
#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B SC_P_USDHC2_CD_B 0
|
||||
#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 SC_P_USDHC2_CD_B 3
|
||||
#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
|
||||
#define SC_P_ENET0_MDIO_DMA_I2C4_SDA SC_P_ENET0_MDIO 1
|
||||
#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13 SC_P_ENET0_MDIO 3
|
||||
#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
|
||||
#define SC_P_ENET0_MDC_DMA_I2C4_SCL SC_P_ENET0_MDC 1
|
||||
#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14 SC_P_ENET0_MDC 3
|
||||
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
|
||||
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
|
||||
#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 SC_P_ENET0_REFCLK_125M_25M 3
|
||||
#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 0
|
||||
#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET1_REFCLK_125M_25M 1
|
||||
#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 SC_P_ENET1_REFCLK_125M_25M 3
|
||||
#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO SC_P_ENET1_MDIO 0
|
||||
#define SC_P_ENET1_MDIO_DMA_I2C4_SDA SC_P_ENET1_MDIO 1
|
||||
#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 SC_P_ENET1_MDIO 3
|
||||
#define SC_P_ENET1_MDC_CONN_ENET1_MDC SC_P_ENET1_MDC 0
|
||||
#define SC_P_ENET1_MDC_DMA_I2C4_SCL SC_P_ENET1_MDC 1
|
||||
#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18 SC_P_ENET1_MDC 3
|
||||
#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI1A_SS0_B 0
|
||||
#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 SC_P_QSPI1A_SS0_B 3
|
||||
#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI1A_SS1_B 0
|
||||
#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 SC_P_QSPI1A_SS1_B 1
|
||||
#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 SC_P_QSPI1A_SS1_B 3
|
||||
#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI1A_SCLK 0
|
||||
#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 SC_P_QSPI1A_SCLK 3
|
||||
#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS SC_P_QSPI1A_DQS 0
|
||||
#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 SC_P_QSPI1A_DQS 3
|
||||
#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI1A_DATA3 0
|
||||
#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA SC_P_QSPI1A_DATA3 1
|
||||
#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC SC_P_QSPI1A_DATA3 2
|
||||
#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 SC_P_QSPI1A_DATA3 3
|
||||
#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI1A_DATA2 0
|
||||
#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL SC_P_QSPI1A_DATA2 1
|
||||
#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR SC_P_QSPI1A_DATA2 2
|
||||
#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 SC_P_QSPI1A_DATA2 3
|
||||
#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI1A_DATA1 0
|
||||
#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA SC_P_QSPI1A_DATA1 1
|
||||
#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC SC_P_QSPI1A_DATA1 2
|
||||
#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 SC_P_QSPI1A_DATA1 3
|
||||
#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI1A_DATA0 0
|
||||
#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 SC_P_QSPI1A_DATA0 3
|
||||
#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
|
||||
#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
|
||||
#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
|
||||
#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
|
||||
#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
|
||||
#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
|
||||
#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
|
||||
#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 SC_P_QSPI0A_SS1_B 1
|
||||
#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
|
||||
#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
|
||||
#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
|
||||
#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
|
||||
#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
|
||||
#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
|
||||
#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
|
||||
#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
|
||||
#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
|
||||
#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 SC_P_QSPI0B_SS1_B 1
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
|
||||
#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 SC_P_PCIE_CTRL0_CLKREQ_B 3
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
|
||||
#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 SC_P_PCIE_CTRL0_WAKE_B 3
|
||||
#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
|
||||
#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 SC_P_PCIE_CTRL0_PERST_B 3
|
||||
#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B SC_P_PCIE_CTRL1_CLKREQ_B 0
|
||||
#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA SC_P_PCIE_CTRL1_CLKREQ_B 1
|
||||
#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC SC_P_PCIE_CTRL1_CLKREQ_B 2
|
||||
#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 SC_P_PCIE_CTRL1_CLKREQ_B 3
|
||||
#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B SC_P_PCIE_CTRL1_WAKE_B 0
|
||||
#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_WAKE_B 1
|
||||
#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR SC_P_PCIE_CTRL1_WAKE_B 2
|
||||
#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 SC_P_PCIE_CTRL1_WAKE_B 3
|
||||
#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B SC_P_PCIE_CTRL1_PERST_B 0
|
||||
#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL SC_P_PCIE_CTRL1_PERST_B 1
|
||||
#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR SC_P_PCIE_CTRL1_PERST_B 2
|
||||
#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 SC_P_PCIE_CTRL1_PERST_B 3
|
||||
#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA SC_P_USB_HSIC0_DATA 0
|
||||
#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA SC_P_USB_HSIC0_DATA 1
|
||||
#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01 SC_P_USB_HSIC0_DATA 3
|
||||
#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE SC_P_USB_HSIC0_STROBE 0
|
||||
#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL SC_P_USB_HSIC0_STROBE 1
|
||||
#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 SC_P_USB_HSIC0_STROBE 3
|
||||
#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
|
||||
#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
|
||||
#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
|
||||
#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
|
||||
#define SC_P_EMMC0_CMD_AUD_MQS_R SC_P_EMMC0_CMD 2
|
||||
#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03 SC_P_EMMC0_CMD 3
|
||||
#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
|
||||
#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
|
||||
#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04 SC_P_EMMC0_DATA0 3
|
||||
#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
|
||||
#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
|
||||
#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05 SC_P_EMMC0_DATA1 3
|
||||
#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
|
||||
#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
|
||||
#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06 SC_P_EMMC0_DATA2 3
|
||||
#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
|
||||
#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
|
||||
#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07 SC_P_EMMC0_DATA3 3
|
||||
#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
|
||||
#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
|
||||
#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08 SC_P_EMMC0_DATA4 3
|
||||
#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
|
||||
#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
|
||||
#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09 SC_P_EMMC0_DATA5 3
|
||||
#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
|
||||
#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
|
||||
#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10 SC_P_EMMC0_DATA6 3
|
||||
#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
|
||||
#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
|
||||
#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11 SC_P_EMMC0_DATA7 3
|
||||
#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
|
||||
#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
|
||||
#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12 SC_P_EMMC0_STROBE 3
|
||||
#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
|
||||
#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
|
||||
#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT SC_P_EMMC0_RESET_B 2
|
||||
#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13 SC_P_EMMC0_RESET_B 3
|
||||
#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
|
||||
#define SC_P_USDHC1_CLK_AUD_MQS_R SC_P_USDHC1_CLK 1
|
||||
#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
|
||||
#define SC_P_USDHC1_CMD_AUD_MQS_L SC_P_USDHC1_CMD 1
|
||||
#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14 SC_P_USDHC1_CMD 3
|
||||
#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
|
||||
#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N SC_P_USDHC1_DATA0 1
|
||||
#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15 SC_P_USDHC1_DATA0 3
|
||||
#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
|
||||
#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P SC_P_USDHC1_DATA1 1
|
||||
#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16 SC_P_USDHC1_DATA1 3
|
||||
#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
|
||||
#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N SC_P_USDHC1_DATA2 1
|
||||
#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17 SC_P_USDHC1_DATA2 3
|
||||
#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
|
||||
#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P SC_P_USDHC1_DATA3 1
|
||||
#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18 SC_P_USDHC1_DATA3 3
|
||||
#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 SC_P_USDHC1_DATA4 0
|
||||
#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B SC_P_USDHC1_DATA4 1
|
||||
#define SC_P_USDHC1_DATA4_AUD_MQS_R SC_P_USDHC1_DATA4 2
|
||||
#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19 SC_P_USDHC1_DATA4 3
|
||||
#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 SC_P_USDHC1_DATA5 0
|
||||
#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B SC_P_USDHC1_DATA5 1
|
||||
#define SC_P_USDHC1_DATA5_AUD_MQS_L SC_P_USDHC1_DATA5 2
|
||||
#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 SC_P_USDHC1_DATA5 3
|
||||
#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 SC_P_USDHC1_DATA6 0
|
||||
#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B SC_P_USDHC1_DATA6 1
|
||||
#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP SC_P_USDHC1_DATA6 2
|
||||
#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 SC_P_USDHC1_DATA6 3
|
||||
#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 SC_P_USDHC1_DATA7 0
|
||||
#define SC_P_USDHC1_DATA7_CONN_NAND_ALE SC_P_USDHC1_DATA7 1
|
||||
#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B SC_P_USDHC1_DATA7 2
|
||||
#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 SC_P_USDHC1_DATA7 3
|
||||
#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE SC_P_USDHC1_STROBE 0
|
||||
#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B SC_P_USDHC1_STROBE 1
|
||||
#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B SC_P_USDHC1_STROBE 2
|
||||
#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 SC_P_USDHC1_STROBE 3
|
||||
#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK SC_P_USDHC2_CLK 0
|
||||
#define SC_P_USDHC2_CLK_AUD_MQS_R SC_P_USDHC2_CLK 1
|
||||
#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24 SC_P_USDHC2_CLK 3
|
||||
#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD SC_P_USDHC2_CMD 0
|
||||
#define SC_P_USDHC2_CMD_AUD_MQS_L SC_P_USDHC2_CMD 1
|
||||
#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 SC_P_USDHC2_CMD 3
|
||||
#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 SC_P_USDHC2_DATA0 0
|
||||
#define SC_P_USDHC2_DATA0_DMA_UART4_RX SC_P_USDHC2_DATA0 1
|
||||
#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26 SC_P_USDHC2_DATA0 3
|
||||
#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 SC_P_USDHC2_DATA1 0
|
||||
#define SC_P_USDHC2_DATA1_DMA_UART4_TX SC_P_USDHC2_DATA1 1
|
||||
#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 SC_P_USDHC2_DATA1 3
|
||||
#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 SC_P_USDHC2_DATA2 0
|
||||
#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B SC_P_USDHC2_DATA2 1
|
||||
#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28 SC_P_USDHC2_DATA2 3
|
||||
#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 SC_P_USDHC2_DATA3 0
|
||||
#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B SC_P_USDHC2_DATA3 1
|
||||
#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 SC_P_USDHC2_DATA3 3
|
||||
#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
|
||||
#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
|
||||
#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
|
||||
#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 SC_P_ENET0_RGMII_TXC 3
|
||||
#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
|
||||
#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 SC_P_ENET0_RGMII_TX_CTL 3
|
||||
#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
|
||||
#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 SC_P_ENET0_RGMII_TXD0 3
|
||||
#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
|
||||
#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 SC_P_ENET0_RGMII_TXD1 3
|
||||
#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
|
||||
#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX SC_P_ENET0_RGMII_TXD2 1
|
||||
#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET0_RGMII_TXD2 2
|
||||
#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 SC_P_ENET0_RGMII_TXD2 3
|
||||
#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
|
||||
#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET0_RGMII_TXD3 1
|
||||
#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET0_RGMII_TXD3 2
|
||||
#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 SC_P_ENET0_RGMII_TXD3 3
|
||||
#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
|
||||
#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET0_RGMII_RXC 1
|
||||
#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET0_RGMII_RXC 2
|
||||
#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 SC_P_ENET0_RGMII_RXC 3
|
||||
#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
|
||||
#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET0_RGMII_RX_CTL 2
|
||||
#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET0_RGMII_RX_CTL 3
|
||||
#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
|
||||
#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET0_RGMII_RXD0 2
|
||||
#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 SC_P_ENET0_RGMII_RXD0 3
|
||||
#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
|
||||
#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET0_RGMII_RXD1 2
|
||||
#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 SC_P_ENET0_RGMII_RXD1 3
|
||||
#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
|
||||
#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
|
||||
#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET0_RGMII_RXD2 2
|
||||
#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 SC_P_ENET0_RGMII_RXD2 3
|
||||
#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
|
||||
#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX SC_P_ENET0_RGMII_RXD3 1
|
||||
#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET0_RGMII_RXD3 2
|
||||
#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 SC_P_ENET0_RGMII_RXD3 3
|
||||
#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC SC_P_ENET1_RGMII_TXC 0
|
||||
#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1
|
||||
#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN SC_P_ENET1_RGMII_TXC 2
|
||||
#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 SC_P_ENET1_RGMII_TXC 3
|
||||
#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 0
|
||||
#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 SC_P_ENET1_RGMII_TX_CTL 3
|
||||
#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 0
|
||||
#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 SC_P_ENET1_RGMII_TXD0 3
|
||||
#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 0
|
||||
#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 SC_P_ENET1_RGMII_TXD1 3
|
||||
#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 0
|
||||
#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX SC_P_ENET1_RGMII_TXD2 1
|
||||
#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID SC_P_ENET1_RGMII_TXD2 2
|
||||
#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 SC_P_ENET1_RGMII_TXD2 3
|
||||
#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 0
|
||||
#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B SC_P_ENET1_RGMII_TXD3 1
|
||||
#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC SC_P_ENET1_RGMII_TXD3 2
|
||||
#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 SC_P_ENET1_RGMII_TXD3 3
|
||||
#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC SC_P_ENET1_RGMII_RXC 0
|
||||
#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B SC_P_ENET1_RGMII_RXC 1
|
||||
#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA SC_P_ENET1_RGMII_RXC 2
|
||||
#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 SC_P_ENET1_RGMII_RXC 3
|
||||
#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 0
|
||||
#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID SC_P_ENET1_RGMII_RX_CTL 2
|
||||
#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 SC_P_ENET1_RGMII_RX_CTL 3
|
||||
#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 0
|
||||
#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC SC_P_ENET1_RGMII_RXD0 2
|
||||
#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 SC_P_ENET1_RGMII_RXD0 3
|
||||
#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 0
|
||||
#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA SC_P_ENET1_RGMII_RXD1 2
|
||||
#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 SC_P_ENET1_RGMII_RXD1 3
|
||||
#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 0
|
||||
#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER SC_P_ENET1_RGMII_RXD2 1
|
||||
#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK SC_P_ENET1_RGMII_RXD2 2
|
||||
#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 SC_P_ENET1_RGMII_RXD2 3
|
||||
#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 0
|
||||
#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1
|
||||
#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2
|
||||
#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0
|
||||
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0
|
||||
|
||||
#endif /* SC_PADS_H */
|
||||
Reference in New Issue
Block a user