Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

ARM: k2g: Add pll data

Browse Source 
Add pll data for k2g

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Vitaly Andrianov
2015-09-19 16:26:40 +05:30
committed by Tom Rini
parent f9c4a51c3e
commit bda920c65e
6 changed files with 95 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/mach-keystone/clock.c
View File

@@ -31,6 +31,7 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
[UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
};
inline void pll_pa_clk_sel(void)
@@ -313,6 +314,10 @@ static unsigned long pll_freq_get(int pll)
ret = external_clk[ddr3b_clk];
reg = KS2_DDR3BPLLCTL0;
break;
case UART_PLL:
ret = external_clk[uart_clk];
reg = KS2_UARTPLLCTL0;
break;
default:
return 0;
}

18
arch/arm/mach-keystone/include/mach/clock-k2g.h Normal file
View File

@@ -0,0 +1,18 @@
/*
* K2G: Clock data
*
* (C) Copyright 2015
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK_K2G_H
#define __ASM_ARCH_CLOCK_K2G_H
#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
#define DEV_SUPPORTED_SPEEDS 0xfff
#define ARM_SUPPORTED_SPEEDS 0xfff
#endif

6
arch/arm/mach-keystone/include/mach/clock.h
View File

@@ -24,8 +24,13 @@
#include <asm/arch/clock-k2l.h>
#endif
#ifdef CONFIG_SOC_K2G
#include <asm/arch/clock-k2g.h>
#endif
#define CORE_PLL MAIN_PLL
#define DDR3_PLL DDR3A_PLL
#define NSS_PLL PASS_PLL
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
@@ -75,6 +80,7 @@ enum {
PASS_PLL,
DDR3A_PLL,
DDR3B_PLL,
UART_PLL,
MAX_PLL_COUNT,
};

2
arch/arm/mach-keystone/include/mach/hardware.h
View File

@@ -167,6 +167,8 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
#define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
#define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
#define KS2_PLL_CNTRL_BASE 0x02310000
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE