diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
index cf2a7b7d105..4fb45ac5c76 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -8,10 +8,13 @@
 
 enum {
 	DDR4 = 0,
-	DDR3 = 0x3,
-	LPDDR2 = 0x5,
-	LPDDR3 = 0x6,
-	LPDDR4 = 0x7,
+	DDR3 = 3,
+	LPDDR2 = 5,
+	LPDDR3 = 6,
+	LPDDR4 = 7,
+	LPDDR4X = 8,
+	LPDDR5 = 9,
+	DDR5 = 10,
 	UNUSED = 0xFF
 };
 
@@ -21,16 +24,16 @@ enum {
  * [30]		row_3_4_ch0
  * [29:28]	chinfo
  * [27]		rank_ch1
- * [26:25]	col_ch1
+ * [26:25]	cs0_col_ch1
  * [24]		bk_ch1
  * [23:22]	low bits of cs0_row_ch1
  * [21:20]	low bits of cs1_row_ch1
  * [19:18]	bw_ch1
- * [17:16]	dbw_ch1;
- * [15:13]	ddrtype
+ * [17:16]	dbw_ch1
+ * [15:13]	low bits of ddrtype
  * [12]		channelnum
- * [11]		rank_ch0
- * [10:9]	col_ch0,
+ * [11]		low bit of rank_ch0
+ * [10:9]	cs0_col_ch0
  * [8]		bk_ch0
  * [7:6]	low bits of cs0_row_ch0
  * [5:4]	low bits of cs1_row_ch0
@@ -61,6 +64,11 @@ enum {
 
 /*
  * sys_reg3 bitfield struct
+ * [31:28]	version
+ * [16]		cs3_delta_row
+ * [15]		cs2_delta_row
+ * [14]		high bit of rank_ch0
+ * [13:12]	high bits of ddrtype
  * [7]		high bit of cs0_row_ch1
  * [6]		high bit of cs1_row_ch1
  * [5]		high bit of cs0_row_ch0
@@ -70,6 +78,8 @@ enum {
  */
 #define SYS_REG_VERSION_SHIFT			28
 #define SYS_REG_VERSION_MASK			0xf
+#define SYS_REG_EXTEND_DDRTYPE_SHIFT		12
+#define SYS_REG_EXTEND_DDRTYPE_MASK		3
 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch)	(5 + (ch) * 2)
 #define SYS_REG_EXTEND_CS0_ROW_MASK		1
 #define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch)	(4 + (ch) * 2)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index e086c47f3c0..91951e4b8cc 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -88,9 +88,15 @@ size_t rockchip_sdram_size(phys_addr_t reg)
 	u32 sys_reg3 = readl(reg + 4);
 	u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
 		       & SYS_REG_NUM_CH_MASK);
+	u32 version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) &
+		      SYS_REG_VERSION_MASK;
 
 	dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
+	if (version >= 3)
+		dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
+			      SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
 	debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
+	debug("%s %x %x\n", __func__, (u32)reg + 4, sys_reg3);
 	for (ch = 0; ch < ch_num; ch++) {
 		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
 			SYS_REG_RANK_MASK);
@@ -98,8 +104,7 @@ size_t rockchip_sdram_size(phys_addr_t reg)
 			  SYS_REG_COL_MASK);
 		cs1_col = cs0_col;
 		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
-		if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
-		     SYS_REG_VERSION_MASK) == 0x2) {
+		if (version >= 2) {
 			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
 				  SYS_REG_CS1_COL_MASK);
 			if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &