mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
* Some code cleanup
* Patch by Josef Baumgartner, 10 Feb 2004: Fixes for Coldfire port * Patch by Brad Kemp, 11 Feb 2004: Fix CFI flash driver problems
This commit is contained in:
wdenk
18
include/asm-m68k/bitops.h
Normal file
18
include/asm-m68k/bitops.h
Normal file
@@ -0,0 +1,18 @@
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/*
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* bitops.h: Bit string operations on the m68k
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*/
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#ifndef _M68K_BITOPS_H
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#define _M68K_BITOPS_H
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#include <linux/config.h>
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#include <asm/byteorder.h>
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extern void set_bit(int nr, volatile void *addr);
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extern void clear_bit(int nr, volatile void *addr);
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extern void change_bit(int nr, volatile void *addr);
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extern int test_and_set_bit(int nr, volatile void *addr);
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extern int test_and_clear_bit(int nr, volatile void *addr);
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extern int test_and_change_bit(int nr, volatile void *addr);
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#endif /* _M68K_BITOPS_H */
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7
include/asm-m68k/byteorder.h
Normal file
7
include/asm-m68k/byteorder.h
Normal file
@@ -0,0 +1,7 @@
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#ifndef _M68K_BYTEORDER_H
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#define _M68K_BYTEORDER_H
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#include <asm/types.h>
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#include <linux/byteorder/big_endian.h>
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#endif /* _M68K_BYTEORDER_H */
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86
include/asm-m68k/fec.h
Normal file
86
include/asm-m68k/fec.h
Normal file
@@ -0,0 +1,86 @@
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/*
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* fec.h -- Fast Ethernet Controller definitions
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*
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* Some definitions copied from commproc.h for MPC8xx:
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* MPC8xx Communication Processor Module.
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef fec_h
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#define fec_h
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/* Buffer descriptors used FEC.
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*/
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typedef struct cpm_buf_desc {
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ushort cbd_sc; /* Status and Control */
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ushort cbd_datlen; /* Data length in buffer */
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uint cbd_bufaddr; /* Buffer address in host memory */
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} cbd_t;
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#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
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#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
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#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
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/* Buffer descriptor control/status used by Ethernet receive.
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*/
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#define BD_ENET_RX_EMPTY ((ushort)0x8000)
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#define BD_ENET_RX_WRAP ((ushort)0x2000)
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#define BD_ENET_RX_INTR ((ushort)0x1000)
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#define BD_ENET_RX_LAST ((ushort)0x0800)
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#define BD_ENET_RX_FIRST ((ushort)0x0400)
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#define BD_ENET_RX_MISS ((ushort)0x0100)
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#define BD_ENET_RX_LG ((ushort)0x0020)
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#define BD_ENET_RX_NO ((ushort)0x0010)
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#define BD_ENET_RX_SH ((ushort)0x0008)
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#define BD_ENET_RX_CR ((ushort)0x0004)
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#define BD_ENET_RX_OV ((ushort)0x0002)
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#define BD_ENET_RX_CL ((ushort)0x0001)
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#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
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/* Buffer descriptor control/status used by Ethernet transmit.
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*/
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#define BD_ENET_TX_READY ((ushort)0x8000)
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#define BD_ENET_TX_PAD ((ushort)0x4000)
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#define BD_ENET_TX_WRAP ((ushort)0x2000)
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#define BD_ENET_TX_INTR ((ushort)0x1000)
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#define BD_ENET_TX_LAST ((ushort)0x0800)
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#define BD_ENET_TX_TC ((ushort)0x0400)
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#define BD_ENET_TX_DEF ((ushort)0x0200)
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#define BD_ENET_TX_HB ((ushort)0x0100)
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#define BD_ENET_TX_LC ((ushort)0x0080)
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#define BD_ENET_TX_RL ((ushort)0x0040)
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#define BD_ENET_TX_RCMASK ((ushort)0x003c)
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#define BD_ENET_TX_UN ((ushort)0x0002)
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#define BD_ENET_TX_CSL ((ushort)0x0001)
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#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
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#endif /* fec_h */
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@@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2002-2003
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* (C) Copyright 2002 - 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@@ -48,6 +48,7 @@ typedef struct global_data {
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#ifdef CONFIG_BOARD_TYPES
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unsigned long board_type;
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#endif
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void **jt; /* Standalone app jump table */
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} gd_t;
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/*
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@@ -56,7 +57,11 @@ typedef struct global_data {
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#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
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#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
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#if 0
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extern gd_t *global_data;
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#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data
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#else
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#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7")
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#endif
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#endif /* __ASM_GBL_DATA_H */
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447
include/asm-m68k/immap_5272.h
Normal file
447
include/asm-m68k/immap_5272.h
Normal file
@@ -0,0 +1,447 @@
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/*
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* MCF5272 Internal Memory Map
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*
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* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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||||
* project.
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||||
*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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||||
* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5272__
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#define __IMMAP_5272__
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/* System configuration registers
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*/
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typedef struct sys_ctrl {
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uint sc_mbar;
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ushort sc_scr;
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ushort sc_spr;
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uint sc_pmr;
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char res1[2];
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ushort sc_alpr;
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uint sc_dir;
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char res2[12];
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} sysctrl_t;
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/* Interrupt module registers
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*/
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typedef struct int_ctrl {
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uint int_icr1;
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uint int_icr2;
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uint int_icr3;
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uint int_icr4;
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uint int_isr;
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uint int_pitr;
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uint int_piwr;
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uchar res1[3];
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uchar int_pivr;
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} intctrl_t;
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/* Chip select module registers.
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*/
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typedef struct cs_ctlr {
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uint cs_br0;
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uint cs_or0;
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uint cs_br1;
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uint cs_or1;
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uint cs_br2;
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uint cs_or2;
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uint cs_br3;
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uint cs_or3;
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uint cs_br4;
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uint cs_or4;
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uint cs_br5;
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uint cs_or5;
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uint cs_br6;
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uint cs_or6;
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uint cs_br7;
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uint cs_or7;
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} csctrl_t;
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/* GPIO port registers
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*/
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typedef struct gpio_ctrl {
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uint gpio_pacnt;
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ushort gpio_paddr;
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ushort gpio_padat;
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uint gpio_pbcnt;
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ushort gpio_pbddr;
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ushort gpio_pbdat;
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uchar res1[4];
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ushort gpio_pcddr;
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ushort gpio_pcdat;
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uint gpio_pdcnt;
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uchar res2[4];
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} gpio_t;
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/* QSPI module registers
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*/
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typedef struct qspi_ctrl {
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ushort qspi_qmr;
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uchar res1[2];
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ushort qspi_qdlyr;
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uchar res2[2];
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ushort qspi_qwr;
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uchar res3[2];
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ushort qspi_qir;
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uchar res4[2];
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ushort qspi_qar;
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uchar res5[2];
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ushort qspi_qdr;
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uchar res6[10];
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} qspi_t;
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/* PWM module registers
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*/
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typedef struct pwm_ctrl {
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uchar pwm_pwcr0;
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uchar res1[3];
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uchar pwm_pwcr1;
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uchar res2[3];
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uchar pwm_pwcr2;
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uchar res3[7];
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uchar pwm_pwwd0;
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uchar res4[3];
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uchar pwm_pwwd1;
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uchar res5[3];
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uchar pwm_pwwd2;
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uchar res6[7];
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} pwm_t;
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/* DMA module registers
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*/
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typedef struct dma_ctrl {
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ulong dma_dmr;
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uchar res1[2];
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ushort dma_dir;
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ulong dma_dbcr;
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ulong dma_dsar;
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ulong dma_ddar;
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uchar res2[12];
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} dma_t;
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||||
|
||||
/* UART module registers
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||||
*/
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||||
typedef struct uart_ctrl {
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||||
uchar uart_umr;
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||||
uchar res1[3];
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||||
uchar uart_usr_ucsr;
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||||
uchar res2[3];
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||||
uchar uart_ucr;
|
||||
uchar res3[3];
|
||||
uchar uart_urb_utb;
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||||
uchar res4[3];
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||||
uchar uart_uipcr_uacr;
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||||
uchar res5[3];
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||||
uchar uart_uisr_uimr;
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||||
uchar res6[3];
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||||
uchar uart_udu;
|
||||
uchar res7[3];
|
||||
uchar uart_udl;
|
||||
uchar res8[3];
|
||||
uchar uart_uabu;
|
||||
uchar res9[3];
|
||||
uchar uart_uabl;
|
||||
uchar res10[3];
|
||||
uchar uart_utf;
|
||||
uchar res11[3];
|
||||
uchar uart_urf;
|
||||
uchar res12[3];
|
||||
uchar uart_ufpd;
|
||||
uchar res13[3];
|
||||
uchar uart_uip;
|
||||
uchar res14[3];
|
||||
uchar uart_uop1;
|
||||
uchar res15[3];
|
||||
uchar uart_uop0;
|
||||
uchar res16[3];
|
||||
} uart_t;
|
||||
|
||||
/* SDRAM controller registers, offset: 0x180
|
||||
*/
|
||||
typedef struct sdram_ctrl {
|
||||
uchar res1[2];
|
||||
ushort sdram_sdcr;
|
||||
uchar res2[2];
|
||||
ushort sdram_sdtr;
|
||||
uchar res3[120];
|
||||
} sdramctrl_t;
|
||||
|
||||
/* Timer module registers
|
||||
*/
|
||||
typedef struct timer_ctrl {
|
||||
ushort timer_tmr;
|
||||
ushort res1;
|
||||
ushort timer_trr;
|
||||
ushort res2;
|
||||
ushort timer_tcap;
|
||||
ushort res3;
|
||||
ushort timer_tcn;
|
||||
ushort res4;
|
||||
ushort timer_ter;
|
||||
uchar res5[14];
|
||||
} timer_t;
|
||||
|
||||
/* Watchdog registers
|
||||
*/
|
||||
typedef struct wdog_ctrl {
|
||||
ushort wdog_wrrr;
|
||||
ushort res1;
|
||||
ushort wdog_wirr;
|
||||
ushort res2;
|
||||
ushort wdog_wcr;
|
||||
ushort res3;
|
||||
ushort wdog_wer;
|
||||
uchar res4[114];
|
||||
} wdog_t;
|
||||
|
||||
/* PLIC module registers
|
||||
*/
|
||||
typedef struct plic_ctrl {
|
||||
ulong plic_p0b1rr;
|
||||
ulong plic_p1b1rr;
|
||||
ulong plic_p2b1rr;
|
||||
ulong plic_p3b1rr;
|
||||
ulong plic_p0b2rr;
|
||||
ulong plic_p1b2rr;
|
||||
ulong plic_p2b2rr;
|
||||
ulong plic_p3b2rr;
|
||||
uchar plic_p0drr;
|
||||
uchar plic_p1drr;
|
||||
uchar plic_p2drr;
|
||||
uchar plic_p3drr;
|
||||
uchar res1[4];
|
||||
ulong plic_p0b1tr;
|
||||
ulong plic_p1b1tr;
|
||||
ulong plic_p2b1tr;
|
||||
ulong plic_p3b1tr;
|
||||
ulong plic_p0b2tr;
|
||||
ulong plic_p1b2tr;
|
||||
ulong plic_p2b2tr;
|
||||
ulong plic_p3b2tr;
|
||||
uchar plic_p0dtr;
|
||||
uchar plic_p1dtr;
|
||||
uchar plic_p2dtr;
|
||||
uchar plic_p3dtr;
|
||||
uchar res2[4];
|
||||
ushort plic_p0cr;
|
||||
ushort plic_p1cr;
|
||||
ushort plic_p2cr;
|
||||
ushort plic_p3cr;
|
||||
ushort plic_p0icr;
|
||||
ushort plic_p1icr;
|
||||
ushort plic_p2icr;
|
||||
ushort plic_p3icr;
|
||||
ushort plic_p0gmr;
|
||||
ushort plic_p1gmr;
|
||||
ushort plic_p2gmr;
|
||||
ushort plic_p3gmr;
|
||||
ushort plic_p0gmt;
|
||||
ushort plic_p1gmt;
|
||||
ushort plic_p2gmt;
|
||||
ushort plic_p3gmt;
|
||||
uchar res3;
|
||||
uchar plic_pgmts;
|
||||
uchar plic_pgmta;
|
||||
uchar res4;
|
||||
uchar plic_p0gcir;
|
||||
uchar plic_p1gcir;
|
||||
uchar plic_p2gcir;
|
||||
uchar plic_p3gcir;
|
||||
uchar plic_p0gcit;
|
||||
uchar plic_p1gcit;
|
||||
uchar plic_p2gcit;
|
||||
uchar plic_p3gcit;
|
||||
uchar res5[3];
|
||||
uchar plic_pgcitsr;
|
||||
uchar res6[3];
|
||||
uchar plic_pdcsr;
|
||||
ushort plic_p0psr;
|
||||
ushort plic_p1psr;
|
||||
ushort plic_p2psr;
|
||||
ushort plic_p3psr;
|
||||
ushort plic_pasr;
|
||||
uchar res7;
|
||||
uchar plic_plcr;
|
||||
ushort res8;
|
||||
ushort plic_pdrqr;
|
||||
ushort plic_p0sdr;
|
||||
ushort plic_p1sdr;
|
||||
ushort plic_p2sdr;
|
||||
ushort plic_p3sdr;
|
||||
ushort res9;
|
||||
ushort plic_pcsr;
|
||||
uchar res10[1184];
|
||||
} plic_t;
|
||||
|
||||
/* Fast ethernet controller registers
|
||||
*/
|
||||
typedef struct fec {
|
||||
uint fec_ecntrl; /* ethernet control register */
|
||||
uint fec_ievent; /* interrupt event register */
|
||||
uint fec_imask; /* interrupt mask register */
|
||||
uint fec_ivec; /* interrupt level and vector status */
|
||||
uint fec_r_des_active; /* Rx ring updated flag */
|
||||
uint fec_x_des_active; /* Tx ring updated flag */
|
||||
uint res3[10]; /* reserved */
|
||||
uint fec_mii_data; /* MII data register */
|
||||
uint fec_mii_speed; /* MII speed control register */
|
||||
uint res4[17]; /* reserved */
|
||||
uint fec_r_bound; /* end of RAM (read-only) */
|
||||
uint fec_r_fstart; /* Rx FIFO start address */
|
||||
uint res5[6]; /* reserved */
|
||||
uint fec_x_fstart; /* Tx FIFO start address */
|
||||
uint res7[21]; /* reserved */
|
||||
uint fec_r_cntrl; /* Rx control register */
|
||||
uint fec_r_hash; /* Rx hash register */
|
||||
uint res8[14]; /* reserved */
|
||||
uint fec_x_cntrl; /* Tx control register */
|
||||
uint res9[0x9e]; /* reserved */
|
||||
uint fec_addr_low; /* lower 32 bits of station address */
|
||||
uint fec_addr_high; /* upper 16 bits of station address */
|
||||
uint fec_hash_table_high; /* upper 32-bits of hash table */
|
||||
uint fec_hash_table_low; /* lower 32-bits of hash table */
|
||||
uint fec_r_des_start; /* beginning of Rx descriptor ring */
|
||||
uint fec_x_des_start; /* beginning of Tx descriptor ring */
|
||||
uint fec_r_buff_size; /* Rx buffer size */
|
||||
uint res2[9]; /* reserved */
|
||||
uchar fec_fifo[960]; /* fifo RAM */
|
||||
} fec_t;
|
||||
|
||||
/* USB module registers
|
||||
*/
|
||||
typedef struct usb {
|
||||
ushort res1;
|
||||
ushort usb_fnr;
|
||||
ushort res2;
|
||||
ushort usb_fnmr;
|
||||
ushort res3;
|
||||
ushort usb_rfmr;
|
||||
ushort res4;
|
||||
ushort usb_rfmmr;
|
||||
uchar res5[3];
|
||||
uchar usb_far;
|
||||
ulong usb_asr;
|
||||
ulong usb_drr1;
|
||||
ulong usb_drr2;
|
||||
ushort res6;
|
||||
ushort usb_specr;
|
||||
ushort res7;
|
||||
ushort usb_ep0sr;
|
||||
ulong usb_iep0cfg;
|
||||
ulong usb_oep0cfg;
|
||||
ulong usb_ep1cfg;
|
||||
ulong usb_ep2cfg;
|
||||
ulong usb_ep3cfg;
|
||||
ulong usb_ep4cfg;
|
||||
ulong usb_ep5cfg;
|
||||
ulong usb_ep6cfg;
|
||||
ulong usb_ep7cfg;
|
||||
ulong usb_ep0ctl;
|
||||
ushort res8;
|
||||
ushort usb_ep1ctl;
|
||||
ushort res9;
|
||||
ushort usb_ep2ctl;
|
||||
ushort res10;
|
||||
ushort usb_ep3ctl;
|
||||
ushort res11;
|
||||
ushort usb_ep4ctl;
|
||||
ushort res12;
|
||||
ushort usb_ep5ctl;
|
||||
ushort res13;
|
||||
ushort usb_ep6ctl;
|
||||
ushort res14;
|
||||
ushort usb_ep7ctl;
|
||||
ulong usb_ep0isr;
|
||||
ushort res15;
|
||||
ushort usb_ep1isr;
|
||||
ushort res16;
|
||||
ushort usb_ep2isr;
|
||||
ushort res17;
|
||||
ushort usb_ep3isr;
|
||||
ushort res18;
|
||||
ushort usb_ep4isr;
|
||||
ushort res19;
|
||||
ushort usb_ep5isr;
|
||||
ushort res20;
|
||||
ushort usb_ep6isr;
|
||||
ushort res21;
|
||||
ushort usb_ep7isr;
|
||||
ulong usb_ep0imr;
|
||||
ushort res22;
|
||||
ushort usb_ep1imr;
|
||||
ushort res23;
|
||||
ushort usb_ep2imr;
|
||||
ushort res24;
|
||||
ushort usb_ep3imr;
|
||||
ushort res25;
|
||||
ushort usb_ep4imr;
|
||||
ushort res26;
|
||||
ushort usb_ep5imr;
|
||||
ushort res27;
|
||||
ushort usb_ep6imr;
|
||||
ushort res28;
|
||||
ushort usb_ep7imr;
|
||||
ulong usb_ep0dr;
|
||||
ulong usb_ep1dr;
|
||||
ulong usb_ep2dr;
|
||||
ulong usb_ep3dr;
|
||||
ulong usb_ep4dr;
|
||||
ulong usb_ep5dr;
|
||||
ulong usb_ep6dr;
|
||||
ulong usb_ep7dr;
|
||||
ushort res29;
|
||||
ushort usb_ep0dpr;
|
||||
ushort res30;
|
||||
ushort usb_ep1dpr;
|
||||
ushort res31;
|
||||
ushort usb_ep2dpr;
|
||||
ushort res32;
|
||||
ushort usb_ep3dpr;
|
||||
ushort res33;
|
||||
ushort usb_ep4dpr;
|
||||
ushort res34;
|
||||
ushort usb_ep5dpr;
|
||||
ushort res35;
|
||||
ushort usb_ep6dpr;
|
||||
ushort res36;
|
||||
ushort usb_ep7dpr;
|
||||
uchar res37[788];
|
||||
uchar usb_cfgram[1024];
|
||||
} usb_t;
|
||||
|
||||
/* Internal memory map.
|
||||
*/
|
||||
typedef struct immap {
|
||||
sysctrl_t sysctrl_reg; /* System configuration registers */
|
||||
intctrl_t intctrl_reg; /* Interrupt controller registers */
|
||||
csctrl_t csctrl_reg; /* Chip select controller registers */
|
||||
gpio_t gpio_reg; /* GPIO controller registers */
|
||||
qspi_t qspi_reg; /* QSPI controller registers */
|
||||
pwm_t pwm_reg; /* Pulse width modulation registers */
|
||||
dma_t dma_reg; /* DMA registers */
|
||||
uart_t uart_reg[2]; /* UART registers */
|
||||
sdramctrl_t sdram_reg; /* SDRAM controller registers */
|
||||
timer_t timer_reg[4]; /* Timer registers */
|
||||
wdog_t wdog_reg; /* Watchdog registers */
|
||||
plic_t plic_reg; /* Physical layer interface registers */
|
||||
fec_t fec_reg; /* Fast ethernet controller registers */
|
||||
usb_t usb_reg; /* USB controller registers */
|
||||
} immap_t;
|
||||
|
||||
#endif /* __IMMAP_5272__ */
|
||||
63
include/asm-m68k/immap_5282.h
Normal file
63
include/asm-m68k/immap_5282.h
Normal file
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* MCF5282 Internal Memory Map
|
||||
*
|
||||
* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __IMMAP_5282__
|
||||
#define __IMMAP_5282__
|
||||
|
||||
|
||||
/* Fast ethernet controller registers
|
||||
*/
|
||||
typedef struct fec {
|
||||
uint fec_ecntrl; /* ethernet control register */
|
||||
uint fec_ievent; /* interrupt event register */
|
||||
uint fec_imask; /* interrupt mask register */
|
||||
uint fec_ivec; /* interrupt level and vector status */
|
||||
uint fec_r_des_active; /* Rx ring updated flag */
|
||||
uint fec_x_des_active; /* Tx ring updated flag */
|
||||
uint res3[10]; /* reserved */
|
||||
uint fec_mii_data; /* MII data register */
|
||||
uint fec_mii_speed; /* MII speed control register */
|
||||
uint res4[17]; /* reserved */
|
||||
uint fec_r_bound; /* end of RAM (read-only) */
|
||||
uint fec_r_fstart; /* Rx FIFO start address */
|
||||
uint res5[6]; /* reserved */
|
||||
uint fec_x_fstart; /* Tx FIFO start address */
|
||||
uint res7[21]; /* reserved */
|
||||
uint fec_r_cntrl; /* Rx control register */
|
||||
uint fec_r_hash; /* Rx hash register */
|
||||
uint res8[14]; /* reserved */
|
||||
uint fec_x_cntrl; /* Tx control register */
|
||||
uint res9[0x9e]; /* reserved */
|
||||
uint fec_addr_low; /* lower 32 bits of station address */
|
||||
uint fec_addr_high; /* upper 16 bits of station address */
|
||||
uint fec_hash_table_high; /* upper 32-bits of hash table */
|
||||
uint fec_hash_table_low; /* lower 32-bits of hash table */
|
||||
uint fec_r_des_start; /* beginning of Rx descriptor ring */
|
||||
uint fec_x_des_start; /* beginning of Tx descriptor ring */
|
||||
uint fec_r_buff_size; /* Rx buffer size */
|
||||
uint res2[9]; /* reserved */
|
||||
uchar fec_fifo[960]; /* fifo RAM */
|
||||
} fec_t;
|
||||
|
||||
#endif /* __IMMAP_5282__ */
|
||||
99
include/asm-m68k/m5272.h
Normal file
99
include/asm-m68k/m5272.h
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* mcf5272.h -- Definitions for Motorola Coldfire 5272
|
||||
*
|
||||
* Based on mcf5272sim.h of uCLinux distribution:
|
||||
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
|
||||
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef mcf5272_h
|
||||
#define mcf5272_h
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Size of internal RAM
|
||||
*/
|
||||
|
||||
#define INT_RAM_SIZE 4096
|
||||
|
||||
|
||||
/*
|
||||
* Define the 5272 SIM register set addresses.
|
||||
*/
|
||||
#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
|
||||
#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
|
||||
#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
|
||||
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
|
||||
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
|
||||
|
||||
#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
|
||||
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
|
||||
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
|
||||
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
|
||||
|
||||
#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
|
||||
#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
|
||||
#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
|
||||
#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
|
||||
|
||||
#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
|
||||
#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
|
||||
#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
|
||||
#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
|
||||
|
||||
#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
|
||||
#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
|
||||
#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
|
||||
#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
|
||||
#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
|
||||
#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
|
||||
#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
|
||||
#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
|
||||
|
||||
#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
|
||||
#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
|
||||
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
|
||||
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
|
||||
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
|
||||
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
|
||||
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
|
||||
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
|
||||
|
||||
#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
|
||||
#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
|
||||
#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
|
||||
#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
|
||||
#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
|
||||
#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
|
||||
#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
|
||||
#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
|
||||
#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
|
||||
|
||||
#endif /* mcf5272_h */
|
||||
60
include/asm-m68k/m5282.h
Normal file
60
include/asm-m68k/m5282.h
Normal file
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* mcf5282.h -- Definitions for Motorola Coldfire 5282
|
||||
*
|
||||
* Based on mcf5282sim.h of uCLinux distribution:
|
||||
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
#ifndef m5282_h
|
||||
#define m5282_h
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Size of internal RAM
|
||||
*/
|
||||
|
||||
#define INT_RAM_SIZE 65536
|
||||
|
||||
|
||||
/*
|
||||
* Define the 5282 SIM register set addresses.
|
||||
*/
|
||||
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
|
||||
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
|
||||
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
|
||||
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
|
||||
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
|
||||
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
|
||||
#define MCFINTC_IRLR 0x18 /* */
|
||||
#define MCFINTC_IACKL 0x19 /* */
|
||||
#define MCFINTC_ICR0 0x40 /* Base ICR register */
|
||||
|
||||
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
|
||||
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
|
||||
|
||||
#define MCF5282_GPIO_PUAPAR 0x10005C
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* m5282_h */
|
||||
113
include/asm-m68k/mcftimer.h
Normal file
113
include/asm-m68k/mcftimer.h
Normal file
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* mcftimer.h -- ColdFire internal TIMER support defines.
|
||||
*
|
||||
* Based on mcftimer.h of uCLinux distribution:
|
||||
* (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
|
||||
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
#ifndef mcftimer_h
|
||||
#define mcftimer_h
|
||||
/****************************************************************************/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
/*
|
||||
* Get address specific defines for this ColdFire member.
|
||||
*/
|
||||
#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
|
||||
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
|
||||
#elif defined(CONFIG_M5272)
|
||||
#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */
|
||||
#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */
|
||||
#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
|
||||
#elif defined(CONFIG_M5282)
|
||||
#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */
|
||||
#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */
|
||||
#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */
|
||||
#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the TIMER register set addresses.
|
||||
*/
|
||||
#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
|
||||
#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
|
||||
#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
|
||||
#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
|
||||
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
|
||||
|
||||
|
||||
/*
|
||||
* Define the TIMER register set addresses for 5282.
|
||||
*/
|
||||
#define MCFTIMER_PCSR 0
|
||||
#define MCFTIMER_PMR 1
|
||||
#define MCFTIMER_PCNTR 2
|
||||
|
||||
/*
|
||||
* Bit definitions for the Timer Mode Register (TMR).
|
||||
* Register bit flags are common accross ColdFires.
|
||||
*/
|
||||
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
|
||||
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
|
||||
#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
|
||||
#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
|
||||
#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
|
||||
#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
|
||||
#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
|
||||
#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
|
||||
#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
|
||||
#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
|
||||
#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
|
||||
#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
|
||||
#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
|
||||
#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
|
||||
#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
|
||||
#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
|
||||
#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
|
||||
|
||||
/*
|
||||
* Bit definitions for the Timer Event Registers (TER).
|
||||
*/
|
||||
#define MCFTIMER_TER_CAP 0x01 /* Capture event */
|
||||
#define MCFTIMER_TER_REF 0x02 /* Refernece event */
|
||||
|
||||
/*
|
||||
* Bit definitions for the 5282 PIT Control and Status Register (PCSR).
|
||||
*/
|
||||
#define MCFTIMER_PCSR_EN 0x0001
|
||||
#define MCFTIMER_PCSR_RLD 0x0002
|
||||
#define MCFTIMER_PCSR_PIF 0x0004
|
||||
#define MCFTIMER_PCSR_PIE 0x0008
|
||||
#define MCFTIMER_PCSR_OVW 0x0010
|
||||
#define MCFTIMER_PCSR_HALTED 0x0020
|
||||
#define MCFTIMER_PCSR_DOZE 0x0040
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* mcftimer_h */
|
||||
217
include/asm-m68k/mcfuart.h
Normal file
217
include/asm-m68k/mcfuart.h
Normal file
@@ -0,0 +1,217 @@
|
||||
/*
|
||||
* mcfuart.h -- ColdFire internal UART support defines.
|
||||
*
|
||||
* File copied from mcfuart.h of uCLinux distribution:
|
||||
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
|
||||
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/****************************************************************************/
|
||||
#ifndef mcfuart_h
|
||||
#define mcfuart_h
|
||||
/****************************************************************************/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
/*
|
||||
* Define the base address of the UARTS within the MBAR address
|
||||
* space.
|
||||
*/
|
||||
#if defined(CONFIG_M5272)
|
||||
#define MCFUART_BASE1 0x100 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
|
||||
#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
|
||||
#if defined(CONFIG_NETtel)
|
||||
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
|
||||
#else
|
||||
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
|
||||
#endif
|
||||
#elif defined(CONFIG_M5282)
|
||||
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x240 /* Base address of UART2 */
|
||||
#define MCFUART_BASE3 0x280 /* Base address of UART3 */
|
||||
#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
|
||||
#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
|
||||
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
|
||||
#else
|
||||
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
|
||||
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Define the ColdFire UART register set addresses.
|
||||
*/
|
||||
#define MCFUART_UMR 0x00 /* Mode register (r/w) */
|
||||
#define MCFUART_USR 0x04 /* Status register (r) */
|
||||
#define MCFUART_UCSR 0x04 /* Clock Select (w) */
|
||||
#define MCFUART_UCR 0x08 /* Command register (w) */
|
||||
#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
|
||||
#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
|
||||
#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
|
||||
#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
|
||||
#define MCFUART_UISR 0x14 /* Interrup Status (r) */
|
||||
#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
|
||||
#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
|
||||
#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
|
||||
#ifdef CONFIG_M5272
|
||||
#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
|
||||
#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
|
||||
#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
|
||||
#else
|
||||
#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
|
||||
#endif
|
||||
#define MCFUART_UIPR 0x34 /* Input Port (r) */
|
||||
#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
|
||||
#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
|
||||
|
||||
|
||||
/*
|
||||
* Define bit flags in Mode Register 1 (MR1).
|
||||
*/
|
||||
#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
|
||||
#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
|
||||
#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
|
||||
#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
|
||||
#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
|
||||
|
||||
#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
|
||||
#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
|
||||
#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
|
||||
#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
|
||||
#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
|
||||
|
||||
#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
|
||||
#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
|
||||
#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
|
||||
#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
|
||||
|
||||
/*
|
||||
* Define bit flags in Mode Register 2 (MR2).
|
||||
*/
|
||||
#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
|
||||
#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
|
||||
#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
|
||||
#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
|
||||
#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
|
||||
|
||||
#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
|
||||
#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
|
||||
#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
|
||||
|
||||
/*
|
||||
* Define bit flags in Status Register (USR).
|
||||
*/
|
||||
#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
|
||||
#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
|
||||
#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
|
||||
#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
|
||||
#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
|
||||
#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
|
||||
#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
|
||||
#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
|
||||
|
||||
#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
|
||||
MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
|
||||
|
||||
/*
|
||||
* Define bit flags in Clock Select Register (UCSR).
|
||||
*/
|
||||
#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
|
||||
#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
|
||||
#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
|
||||
|
||||
#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
|
||||
#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
|
||||
#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
|
||||
|
||||
/*
|
||||
* Define bit flags in Command Register (UCR).
|
||||
*/
|
||||
#define MCFUART_UCR_CMDNULL 0x00 /* No command */
|
||||
#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
|
||||
#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
|
||||
#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
|
||||
#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
|
||||
#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
|
||||
#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
|
||||
#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
|
||||
|
||||
#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
|
||||
#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
|
||||
#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
|
||||
#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
|
||||
#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
|
||||
#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
|
||||
|
||||
/*
|
||||
* Define bit flags in Input Port Change Register (UIPCR).
|
||||
*/
|
||||
#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
|
||||
#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
|
||||
|
||||
/*
|
||||
* Define bit flags in Input Port Register (UIP).
|
||||
*/
|
||||
#define MCFUART_UIPR_CTS 0x01 /* CTS value */
|
||||
|
||||
/*
|
||||
* Define bit flags in Output Port Registers (UOP).
|
||||
* Clear bit by writing to UOP0, set by writing to UOP1.
|
||||
*/
|
||||
#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
|
||||
|
||||
/*
|
||||
* Define bit flags in the Auxiliary Control Register (UACR).
|
||||
*/
|
||||
#define MCFUART_UACR_IEC 0x01 /* Input enable control */
|
||||
|
||||
/*
|
||||
* Define bit flags in Interrupt Status Register (UISR).
|
||||
* These same bits are used for the Interrupt Mask Register (UIMR).
|
||||
*/
|
||||
#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
|
||||
#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
|
||||
#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
|
||||
#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
|
||||
|
||||
#ifdef CONFIG_M5272
|
||||
/*
|
||||
* Define bit flags in the Transmitter FIFO Register (UTF).
|
||||
*/
|
||||
#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
|
||||
#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
|
||||
#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
|
||||
|
||||
/*
|
||||
* Define bit flags in the Receiver FIFO Register (URF).
|
||||
*/
|
||||
#define MCFUART_URF_RXB 0x1f /* receiver data level */
|
||||
#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
|
||||
#define MCFUART_URF_RXS 0xc0 /* receiver status */
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* mcfuart_h */
|
||||
18
include/asm-m68k/processor.h
Normal file
18
include/asm-m68k/processor.h
Normal file
@@ -0,0 +1,18 @@
|
||||
#ifndef __ASM_M68K_PROCESSOR_H
|
||||
#define __ASM_M68K_PROCESSOR_H
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
#define _GLOBAL(n)\
|
||||
.globl n;\
|
||||
n:
|
||||
|
||||
/* Macros for setting and retrieving special purpose registers */
|
||||
#define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#endif /* ifndef ASSEMBLY*/
|
||||
|
||||
#endif /* __ASM_M68K_PROCESSOR_H */
|
||||
@@ -1,107 +1,59 @@
|
||||
/*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _M68K_PTRACE_H
|
||||
#define _M68K_PTRACE_H
|
||||
|
||||
/*
|
||||
* This struct defines the way the registers are stored on the
|
||||
* kernel stack during a system call or other kernel entry.
|
||||
*
|
||||
* this should only contain volatile regs
|
||||
* since we can keep non-volatile in the thread_struct
|
||||
* should set this up when only volatiles are saved
|
||||
* by intr code.
|
||||
*
|
||||
* Since this is going on the stack, *CARE MUST BE TAKEN* to insure
|
||||
* that the overall structure is a multiple of 16 bytes in length.
|
||||
*
|
||||
* Note that the offsets of the fields in this struct correspond with
|
||||
* the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
|
||||
* kernel stack during an exception.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_M68K64BRIDGE
|
||||
#define M68K_REG unsigned long /*long*/
|
||||
#else
|
||||
#define M68K_REG unsigned long
|
||||
#endif
|
||||
|
||||
struct pt_regs {
|
||||
M68K_REG gpr[32];
|
||||
M68K_REG nip;
|
||||
M68K_REG msr;
|
||||
M68K_REG orig_gpr3; /* Used for restarting system calls */
|
||||
M68K_REG ctr;
|
||||
M68K_REG link;
|
||||
M68K_REG xer;
|
||||
M68K_REG ccr;
|
||||
M68K_REG mq; /* 601 only (not used at present) */
|
||||
/* Used on APUS to hold IPL value. */
|
||||
M68K_REG trap; /* Reason for being here */
|
||||
M68K_REG dar; /* Fault registers */
|
||||
M68K_REG dsisr;
|
||||
M68K_REG result; /* Result of a system call */
|
||||
ulong d0;
|
||||
ulong d1;
|
||||
ulong d2;
|
||||
ulong d3;
|
||||
ulong d4;
|
||||
ulong d5;
|
||||
ulong d6;
|
||||
ulong d7;
|
||||
ulong a0;
|
||||
ulong a1;
|
||||
ulong a2;
|
||||
ulong a3;
|
||||
ulong a4;
|
||||
ulong a5;
|
||||
ulong a6;
|
||||
#if defined(CONFIG_M5272) || defined(CONFIG_M5282)
|
||||
unsigned format : 4; /* frame format specifier */
|
||||
unsigned vector : 12; /* vector offset */
|
||||
unsigned short sr;
|
||||
unsigned long pc;
|
||||
#else
|
||||
unsigned short sr;
|
||||
unsigned long pc;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
|
||||
#endif /* #ifndef __ASSEMBLY__ */
|
||||
|
||||
/* Size of stack frame allocated when calling signal handler. */
|
||||
#define __SIGNAL_FRAMESIZE 64
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->nip)
|
||||
#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
|
||||
|
||||
/*
|
||||
* Offsets used by 'ptrace' system call interface.
|
||||
* These can't be changed without breaking binary compatibility
|
||||
* with MkLinux, etc.
|
||||
*/
|
||||
#define PT_R0 0
|
||||
#define PT_R1 1
|
||||
#define PT_R2 2
|
||||
#define PT_R3 3
|
||||
#define PT_R4 4
|
||||
#define PT_R5 5
|
||||
#define PT_R6 6
|
||||
#define PT_R7 7
|
||||
#define PT_R8 8
|
||||
#define PT_R9 9
|
||||
#define PT_R10 10
|
||||
#define PT_R11 11
|
||||
#define PT_R12 12
|
||||
#define PT_R13 13
|
||||
#define PT_R14 14
|
||||
#define PT_R15 15
|
||||
#define PT_R16 16
|
||||
#define PT_R17 17
|
||||
#define PT_R18 18
|
||||
#define PT_R19 19
|
||||
#define PT_R20 20
|
||||
#define PT_R21 21
|
||||
#define PT_R22 22
|
||||
#define PT_R23 23
|
||||
#define PT_R24 24
|
||||
#define PT_R25 25
|
||||
#define PT_R26 26
|
||||
#define PT_R27 27
|
||||
#define PT_R28 28
|
||||
#define PT_R29 29
|
||||
#define PT_R30 30
|
||||
#define PT_R31 31
|
||||
|
||||
#define PT_NIP 32
|
||||
#define PT_MSR 33
|
||||
#ifdef __KERNEL__
|
||||
#define PT_ORIG_R3 34
|
||||
#endif
|
||||
#define PT_CTR 35
|
||||
#define PT_LNK 36
|
||||
#define PT_XER 37
|
||||
#define PT_CCR 38
|
||||
#define PT_MQ 39
|
||||
|
||||
#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
|
||||
#define PT_FPR31 (PT_FPR0 + 2*31)
|
||||
#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
|
||||
|
||||
#endif
|
||||
#endif /* #ifndef _M68K_PTRACE_H */
|
||||
|
||||
@@ -38,10 +38,11 @@ typedef struct bd_info {
|
||||
unsigned long bi_flashoffset; /* reserved area for startup monitor */
|
||||
unsigned long bi_sramstart; /* start of SRAM memory */
|
||||
unsigned long bi_sramsize; /* size of SRAM memory */
|
||||
unsigned long bi_mbar_base; /* base of internal registers */
|
||||
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
|
||||
unsigned long bi_boot_params; /* where this board expects params */
|
||||
unsigned long bi_boot_params; /* where this board expects params */
|
||||
unsigned long bi_ip_addr; /* IP Address */
|
||||
unsigned char bi_enetaddr[6]; /* Ethernet adress */
|
||||
unsigned char bi_enetaddr[6]; /* Ethernet adress */
|
||||
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
|
||||
unsigned long bi_intfreq; /* Internal Freq, in MHz */
|
||||
unsigned long bi_busfreq; /* Bus Freq, in MHz */
|
||||
@@ -49,21 +50,5 @@ typedef struct bd_info {
|
||||
} bd_t;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* The following data structure is placed in DPRAM to allow for a
|
||||
* minimum set of global variables during system initialization
|
||||
* (until we have set up the memory controller so that we can use
|
||||
* RAM).
|
||||
*
|
||||
* Keep it *SMALL* and remember to set CFG_INIT_DATA_SIZE > sizeof(init_data_t)
|
||||
*/
|
||||
typedef struct init_data {
|
||||
unsigned long cpu_clk; /* VCOOUT = CPU clock in Hz! */
|
||||
unsigned long env_addr; /* Address of Environment struct */
|
||||
unsigned long env_valid; /* Checksum of Environment valid? */
|
||||
unsigned long relocated; /* Relocat. offset when running in RAM */
|
||||
unsigned long have_console; /* serial_init() was called */
|
||||
#ifdef CONFIG_LCD
|
||||
unsigned long lcd_base; /* Base address of LCD frambuffer mem */
|
||||
#endif
|
||||
} init_data_t;
|
||||
|
||||
#endif /* __U_BOOT_H__ */
|
||||
|
||||
@@ -397,9 +397,10 @@ void get_sys_info ( sys_info_t * );
|
||||
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
|
||||
void cpu_init_f (volatile immap_t *immr);
|
||||
#endif
|
||||
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx)
|
||||
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2)
|
||||
void cpu_init_f (void);
|
||||
#endif
|
||||
|
||||
int cpu_init_r (void);
|
||||
#if defined(CONFIG_8260)
|
||||
int prt_8260_rsr (void);
|
||||
|
||||
@@ -1,40 +1,189 @@
|
||||
#ifndef _CONFIG_M5272C3_H
|
||||
#define _CONFIG_M5272C3_H
|
||||
/*
|
||||
* Configuation settings for the Motorola MC5272C3 board.
|
||||
*
|
||||
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
|
||||
#include <cmd_confdefs.h>
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 11
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
#define CFG_MALLOC_LEN (256 << 10)
|
||||
#define CFG_INIT_RAM_ADDR 0x20000000
|
||||
#define CFG_INIT_RAM_SIZE 0x1000
|
||||
#define CFG_INIT_DATA_OFFSET 0
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
#define CFG_MONITOR_BASE 0x3e0000
|
||||
#define CFG_MONITOR_LEN 0x20000
|
||||
#define CFG_SDRAM_BASE 0
|
||||
#define CFG_FLASH_BASE 0xffe00000
|
||||
#define CFG_PROMPT "MCF5272C3> "
|
||||
#define CFG_CBSIZE 1024
|
||||
#define CFG_MAXARGS 64
|
||||
#define CFG_LOAD_ADDR 0x20000
|
||||
#define CFG_BOOTMAPSZ 0
|
||||
#define CFG_BARGSIZE CFG_CBSIZE
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
#define CFG_ENV_ADDR 0xffe04000
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_PBSIZE 1024
|
||||
#define CFG_MAX_FLASH_BANKS 1
|
||||
#define CFG_MEMTEST_START 0x400
|
||||
#define CFG_MEMTEST_END 0x380000
|
||||
#define CFG_HZ 1000000
|
||||
#define CFG_FLASH_ERASE_TOUT 10000000
|
||||
#ifndef _M5272C3_H
|
||||
#define _M5272C3_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_MCF52x2 /* define processor family */
|
||||
#define CONFIG_M5272 /* define processor type */
|
||||
|
||||
#define FEC_ENET
|
||||
|
||||
#define CONFIG_M5272
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
|
||||
#endif /* _CONFIG_M5272C3_H */
|
||||
#define CONFIG_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
|
||||
|
||||
#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
|
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_ENV_OFFSET 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_IS_EMBEDDED 1
|
||||
#else
|
||||
#define CFG_ENV_ADDR 0xffe04000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \
|
||||
CFG_CMD_MII)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
#define CFG_PROMPT "-> "
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x20000
|
||||
|
||||
#define CFG_MEMTEST_START 0x400
|
||||
#define CFG_MEMTEST_END 0x380000
|
||||
|
||||
#define CFG_HZ 1000
|
||||
#define CFG_CLK 66000000
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CFG_MBAR 0x10000000 /* Register Base Addrs */
|
||||
|
||||
#define CFG_SCR 0x0003;
|
||||
#define CFG_SPR 0xffff;
|
||||
|
||||
#define CFG_DISCOVER_PHY
|
||||
#define CFG_ENET_BD_BASE 0x380000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR 0x20000000
|
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
|
||||
#define CFG_FLASH_BASE 0xffe00000
|
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_MONITOR_BASE 0x20000
|
||||
#else
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN 0x20000
|
||||
#define CFG_MALLOC_LEN (256 << 10)
|
||||
#define CFG_BOOTPARAMS_LEN 64*1024
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_ERASE_TOUT 1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions
|
||||
*/
|
||||
#define CFG_BR0_PRELIM 0xFFE00201
|
||||
#define CFG_OR0_PRELIM 0xFFE00014
|
||||
|
||||
#define CFG_BR1_PRELIM 0
|
||||
#define CFG_OR1_PRELIM 0
|
||||
|
||||
#define CFG_BR2_PRELIM 0x30000001
|
||||
#define CFG_OR2_PRELIM 0xFFF80000
|
||||
|
||||
#define CFG_BR3_PRELIM 0
|
||||
#define CFG_OR3_PRELIM 0
|
||||
|
||||
#define CFG_BR4_PRELIM 0
|
||||
#define CFG_OR4_PRELIM 0
|
||||
|
||||
#define CFG_BR5_PRELIM 0
|
||||
#define CFG_OR5_PRELIM 0
|
||||
|
||||
#define CFG_BR6_PRELIM 0
|
||||
#define CFG_OR6_PRELIM 0
|
||||
|
||||
#define CFG_BR7_PRELIM 0x00000701
|
||||
#define CFG_OR7_PRELIM 0xFFC0007C
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Port configuration
|
||||
*/
|
||||
#define CFG_PACNT 0x00000000
|
||||
#define CFG_PADDR 0x0000
|
||||
#define CFG_PADAT 0x0000
|
||||
#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */
|
||||
#define CFG_PBDDR 0x0000
|
||||
#define CFG_PBDAT 0x0000
|
||||
#define CFG_PDCNT 0x00000000
|
||||
|
||||
#endif /* _M5272C3_H */
|
||||
|
||||
@@ -1,40 +1,151 @@
|
||||
/*
|
||||
* Configuation settings for the Motorola MC5282EVB board.
|
||||
*
|
||||
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_M5282EVB_H
|
||||
#define _CONFIG_M5282EVB_H
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
|
||||
#include <cmd_confdefs.h>
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 35
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
#define CFG_MALLOC_LEN (256 << 10)
|
||||
#define CFG_INIT_RAM_ADDR 0x20000000
|
||||
#define CFG_INIT_RAM_SIZE 0x1000
|
||||
#define CFG_INIT_DATA_OFFSET 0
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
#define CFG_MONITOR_BASE 0x3e0000
|
||||
#define CFG_MONITOR_LEN 0x20000
|
||||
#define CFG_SDRAM_BASE 0
|
||||
#define CFG_FLASH_BASE 0xffe00000
|
||||
#define CFG_PROMPT "M5282EVB> "
|
||||
#define CFG_CBSIZE 1024
|
||||
#define CFG_MAXARGS 64
|
||||
#define CFG_LOAD_ADDR 0x20000
|
||||
#define CFG_BOOTMAPSZ 0
|
||||
#define CFG_BARGSIZE CFG_CBSIZE
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
#define CFG_ENV_ADDR 0xffe04000
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_PBSIZE 1024
|
||||
#define CFG_MAX_FLASH_BANKS 1
|
||||
#define CFG_MEMTEST_START 0x400
|
||||
#define CFG_MEMTEST_END 0x380000
|
||||
#define CFG_HZ 1000000
|
||||
#define CFG_FLASH_ERASE_TOUT 10000000
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_MCF52x2 /* define processor family */
|
||||
#define CONFIG_M5282 /* define processor type */
|
||||
|
||||
#define FEC_ENET
|
||||
|
||||
#define CONFIG_M5282
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
|
||||
#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
|
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#define CFG_ENV_ADDR 0xffe04000
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
#define CFG_PROMPT "-> "
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x20000
|
||||
|
||||
#define CFG_MEMTEST_START 0x400
|
||||
#define CFG_MEMTEST_END 0x380000
|
||||
|
||||
#define CFG_HZ 1000000
|
||||
#define CFG_CLK 64000000
|
||||
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
#define CFG_MBAR 0x40000000
|
||||
|
||||
#undef CFG_DISCOVER_PHY
|
||||
#define CFG_ENET_BD_BASE 0x380000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR 0x20000000
|
||||
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */
|
||||
#define CFG_FLASH_BASE 0xffe00000
|
||||
#define CFG_INT_FLASH_BASE 0xf0000000
|
||||
|
||||
/* If M5282 port is fully implemented the monitor base will be behind
|
||||
* the vector table. */
|
||||
/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */
|
||||
#define CFG_MONITOR_BASE 0x20000
|
||||
|
||||
#define CFG_MONITOR_LEN 0x20000
|
||||
#define CFG_MALLOC_LEN (256 << 10)
|
||||
#define CFG_BOOTPARAMS_LEN 64*1024
|
||||
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_SECT 35
|
||||
#define CFG_MAX_FLASH_BANKS 1
|
||||
#define CFG_FLASH_ERASE_TOUT 10000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions
|
||||
*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Port configuration
|
||||
*/
|
||||
|
||||
|
||||
#endif /* _CONFIG_M5282EVB_H */
|
||||
|
||||
@@ -445,6 +445,7 @@
|
||||
*/
|
||||
|
||||
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
|
||||
|
||||
@@ -44,6 +44,7 @@ typedef struct {
|
||||
ulong buffer_write_tout; /* maximum buffer write timeout */
|
||||
ushort vendor; /* the primary vendor id */
|
||||
ushort cmd_reset; /* Vendor specific reset command */
|
||||
ushort interface; /* used for x8/x16 adjustments */
|
||||
#endif
|
||||
} flash_info_t;
|
||||
|
||||
@@ -61,6 +62,14 @@ typedef struct {
|
||||
#define FLASH_CFI_BY16 0x02
|
||||
#define FLASH_CFI_BY32 0x04
|
||||
#define FLASH_CFI_BY64 0x08
|
||||
/* convert between bit value and numeric value */
|
||||
#define CFI_FLASH_SHIFT_WIDTH 3
|
||||
/*
|
||||
* Values for the flash device interface
|
||||
*/
|
||||
#define FLASH_CFI_X8 0x00
|
||||
#define FLASH_CFI_X16 0x01
|
||||
#define FLASH_CFI_X8X16 0x02
|
||||
|
||||
/* convert between bit value and numeric value */
|
||||
#define CFI_FLASH_SHIFT_WIDTH 3
|
||||
@@ -185,6 +194,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
||||
|
||||
#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
|
||||
#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
|
||||
#define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
|
||||
|
||||
#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
|
||||
#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
|
||||
@@ -340,6 +350,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
||||
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
|
||||
#define FLASH_AMDL163B 0x00B3
|
||||
|
||||
#define FLASH_FUJLV650 0x00B4 /* Fujitsu MBM 29LV650UE/651UE */
|
||||
|
||||
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user