ARM: OMAP4+: Make control module register structure generic

A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2026-06-13 15:03:58 +03:00 · 2013-02-04 04:22:04 +00:00
parent e05a4f1f54
commit c43c8339fe
11 changed files with 269 additions and 206 deletions
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -132,34 +132,6 @@ struct s32ktimer {
 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
 #define DEVICE_GP 0x3

-struct omap_sys_ctrl_regs {
-	unsigned int pad1[129];
-	unsigned int control_id_code;			/* 0x4A002204 */
-	unsigned int pad11[22];
-	unsigned int control_std_fuse_opp_bgap;		/* 0x4a002260 */
-	unsigned int pad2[24];				/* 0x4a002264 */
-	unsigned int control_status;			/* 0x4a0022c4 */
-	unsigned int pad3[22];				/* 0x4a0022c8 */
-	unsigned int control_ldosram_iva_voltage_ctrl;	/* 0x4A002320 */
-	unsigned int control_ldosram_mpu_voltage_ctrl;	/* 0x4A002324 */
-	unsigned int control_ldosram_core_voltage_ctrl;	/* 0x4A002328 */
-	unsigned int pad4[260277];
-	unsigned int control_pbiaslite;                 /* 0x4A100600 */
-	unsigned int pad5[63];
-	unsigned int control_efuse_1;			/* 0x4A100700 */
-	unsigned int control_efuse_2;			/* 0x4A100704 */
-};
-
-struct control_lpddr2io_regs {
-	unsigned int control_lpddr2io1_0;
-	unsigned int control_lpddr2io1_1;
-	unsigned int control_lpddr2io1_2;
-	unsigned int control_lpddr2io1_3;
-	unsigned int control_lpddr2io2_0;
-	unsigned int control_lpddr2io2_1;
-	unsigned int control_lpddr2io2_2;
-	unsigned int control_lpddr2io2_3;
-};
 #endif /* __ASSEMBLY__ */

 /*
@@ -181,7 +153,8 @@ struct control_lpddr2io_regs {
 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR	(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP4_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x24)

 /* ROM code defines */
 /* Boot device */
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -131,87 +131,6 @@ struct s32ktimer {
 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
 #define DEVICE_GP 0x3

-struct omap_sys_ctrl_regs {
-	u32 pad0[77]; /* 0x4A002000 */
-	u32 control_status; /* 0x4A002134 */
-	u32 pad1[794]; /* 0x4A002138 */
-	u32 control_paconf_global; /* 0x4A002DA0 */
-	u32 control_paconf_mode;  /* 0x4A002DA4 */
-	u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
-	u32 control_smart1io_padconf_1; /* 0x4A002DAC */
-	u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
-	u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
-	u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
-	u32 control_smart2io_padconf_2; /* 0x4A002DBC */
-	u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
-	u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
-	u32 pad2[14];
-	u32 control_pbias; /* 0x4A002E00 */
-	u32 control_i2c_0; /* 0x4A002E04 */
-	u32 control_camera_rx; /* 0x4A002E08 */
-	u32 control_hdmi_tx_phy; /* 0x4A002E0C */
-	u32 control_uniportm; /* 0x4A002E10 */
-	u32 control_dsiphy; /* 0x4A002E14 */
-	u32 control_mcbsplp; /* 0x4A002E18 */
-	u32 control_usb2phycore; /* 0x4A002E1C */
-	u32 control_hdmi_1; /*0x4A002E20*/
-	u32 control_hsi; /*0x4A002E24*/
-	u32 pad3[2];
-	u32 control_ddr3ch1_0; /*0x4A002E30*/
-	u32 control_ddr3ch2_0; /*0x4A002E34*/
-	u32 control_ddrch1_0;	/*0x4A002E38*/
-	u32 control_ddrch1_1;	/*0x4A002E3C*/
-	u32 control_ddrch2_0;	/*0x4A002E40*/
-	u32 control_ddrch2_1;	/*0x4A002E44*/
-	u32 control_lpddr2ch1_0; /*0x4A002E48*/
-	u32 control_lpddr2ch1_1; /*0x4A002E4C*/
-	u32 control_ddrio_0;  /*0x4A002E50*/
-	u32 control_ddrio_1;  /*0x4A002E54*/
-	u32 control_ddrio_2;  /*0x4A002E58*/
-	u32 control_hyst_1; /*0x4A002E5C*/
-	u32 control_usbb_hsic_control; /*0x4A002E60*/
-	u32 control_c2c; /*0x4A002E64*/
-	u32 control_core_control_spare_rw; /*0x4A002E68*/
-	u32 control_core_control_spare_r; /*0x4A002E6C*/
-	u32 control_core_control_spare_r_c0; /*0x4A002E70*/
-	u32 control_srcomp_north_side; /*0x4A002E74*/
-	u32 control_srcomp_south_side; /*0x4A002E78*/
-	u32 control_srcomp_east_side; /*0x4A002E7C*/
-	u32 control_srcomp_west_side; /*0x4A002E80*/
-	u32 control_srcomp_code_latch; /*0x4A002E84*/
-	u32 pad4[3679394];
-	u32 control_port_emif1_sdram_config;		/*0x4AE0C110*/
-	u32 control_port_emif1_lpddr2_nvm_config;	/*0x4AE0C114*/
-	u32 control_port_emif2_sdram_config;		/*0x4AE0C118*/
-	u32 pad5[10];
-	u32 control_emif1_sdram_config_ext;		/* 0x4AE0C144 */
-	u32 control_emif2_sdram_config_ext;		/* 0x4AE0C148 */
-	u32 pad6[789];
-	u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
-	u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
-	u32 control_padconf_mode; /* 0x4AE0CDA8 */
-	u32 control_xtal_oscillator; /* 0x4AE0CDAC */
-	u32 control_i2c_2; /* 0x4AE0CDB0 */
-	u32 control_ckobuffer; /* 0x4AE0CDB4 */
-	u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
-	u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
-	u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
-	u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
-	u32 control_efuse_1; /* 0x4AE0CDC8 */
-	u32 control_efuse_2; /* 0x4AE0CDCC */
-	u32 control_efuse_3; /* 0x4AE0CDD0 */
-	u32 control_efuse_4; /* 0x4AE0CDD4 */
-	u32 control_efuse_5; /* 0x4AE0CDD8 */
-	u32 control_efuse_6; /* 0x4AE0CDDC */
-	u32 control_efuse_7; /* 0x4AE0CDE0 */
-	u32 control_efuse_8; /* 0x4AE0CDE4 */
-	u32 control_efuse_9; /* 0x4AE0CDE8 */
-	u32 control_efuse_10; /* 0x4AE0CDEC */
-	u32 control_efuse_11; /* 0x4AE0CDF0 */
-	u32 control_efuse_12; /* 0x4AE0CDF4 */
-	u32 control_efuse_13; /* 0x4AE0CDF8 */
-};
-
 /* Output impedance control */
 #define ds_120_ohm	0x0
 #define ds_60_ohm	0x1
@@ -274,7 +193,8 @@ struct omap_sys_ctrl_regs {
 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP5_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x24)

 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -326,6 +326,94 @@ struct prcm_regs {
 	u32 prm_vc_cfg_channel;
 };

+struct omap_sys_ctrl_regs {
+	u32 control_status;
+	u32 control_id_code;
+	u32 control_std_fuse_opp_bgap;
+	u32 control_ldosram_iva_voltage_ctrl;
+	u32 control_ldosram_mpu_voltage_ctrl;
+	u32 control_ldosram_core_voltage_ctrl;
+	u32 control_paconf_global;
+	u32 control_paconf_mode;
+	u32 control_smart1io_padconf_0;
+	u32 control_smart1io_padconf_1;
+	u32 control_smart1io_padconf_2;
+	u32 control_smart2io_padconf_0;
+	u32 control_smart2io_padconf_1;
+	u32 control_smart2io_padconf_2;
+	u32 control_smart3io_padconf_0;
+	u32 control_smart3io_padconf_1;
+	u32 control_pbias;
+	u32 control_i2c_0;
+	u32 control_camera_rx;
+	u32 control_hdmi_tx_phy;
+	u32 control_uniportm;
+	u32 control_dsiphy;
+	u32 control_mcbsplp;
+	u32 control_usb2phycore;
+	u32 control_hdmi_1;
+	u32 control_hsi;
+	u32 control_ddr3ch1_0;
+	u32 control_ddr3ch2_0;
+	u32 control_ddrch1_0;
+	u32 control_ddrch1_1;
+	u32 control_ddrch2_0;
+	u32 control_ddrch2_1;
+	u32 control_lpddr2ch1_0;
+	u32 control_lpddr2ch1_1;
+	u32 control_ddrio_0;
+	u32 control_ddrio_1;
+	u32 control_ddrio_2;
+	u32 control_lpddr2io1_0;
+	u32 control_lpddr2io1_1;
+	u32 control_lpddr2io1_2;
+	u32 control_lpddr2io1_3;
+	u32 control_lpddr2io2_0;
+	u32 control_lpddr2io2_1;
+	u32 control_lpddr2io2_2;
+	u32 control_lpddr2io2_3;
+	u32 control_hyst_1;
+	u32 control_usbb_hsic_control;
+	u32 control_c2c;
+	u32 control_core_control_spare_rw;
+	u32 control_core_control_spare_r;
+	u32 control_core_control_spare_r_c0;
+	u32 control_srcomp_north_side;
+	u32 control_srcomp_south_side;
+	u32 control_srcomp_east_side;
+	u32 control_srcomp_west_side;
+	u32 control_srcomp_code_latch;
+	u32 control_pbiaslite;
+	u32 control_port_emif1_sdram_config;
+	u32 control_port_emif1_lpddr2_nvm_config;
+	u32 control_port_emif2_sdram_config;
+	u32 control_emif1_sdram_config_ext;
+	u32 control_emif2_sdram_config_ext;
+	u32 control_smart1nopmio_padconf_0;
+	u32 control_smart1nopmio_padconf_1;
+	u32 control_padconf_mode;
+	u32 control_xtal_oscillator;
+	u32 control_i2c_2;
+	u32 control_ckobuffer;
+	u32 control_wkup_control_spare_rw;
+	u32 control_wkup_control_spare_r;
+	u32 control_wkup_control_spare_r_c0;
+	u32 control_srcomp_east_side_wkup;
+	u32 control_efuse_1;
+	u32 control_efuse_2;
+	u32 control_efuse_3;
+	u32 control_efuse_4;
+	u32 control_efuse_5;
+	u32 control_efuse_6;
+	u32 control_efuse_7;
+	u32 control_efuse_8;
+	u32 control_efuse_9;
+	u32 control_efuse_10;
+	u32 control_efuse_11;
+	u32 control_efuse_12;
+	u32 control_efuse_13;
+};
+
 struct dpll_params {
 	u32 m;
 	u32 n;
@@ -390,6 +478,9 @@ extern struct prcm_regs const omap4_prcm;
 extern struct dplls const **dplls_data;
 extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];
+extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const omap4_ctrl;
+extern struct omap_sys_ctrl_regs const omap5_ctrl;

 void hw_data_init(void);