mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge with git://www.denx.de/git/u-boot.git
This commit is contained in:
Markus Klotzbuecher
@@ -105,6 +105,11 @@ static inline void sync(void)
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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static inline void isync(void)
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{
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__asm__ __volatile__ ("isync" : : : "memory");
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}
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/* Enforce in-order execution of data I/O.
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* No distinction between read/write on PPC; use eieio for all three.
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*/
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@@ -114,74 +119,90 @@ static inline void sync(void)
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/*
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* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
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*
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* Read operations have additional twi & isync to make sure the read
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* is actually performed (i.e. the data has come back) before we start
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* executing any following instructions.
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*/
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extern inline int in_8(volatile u8 *addr)
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#define __iomem
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extern inline int in_8(const volatile unsigned char __iomem *addr)
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{
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int ret;
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int ret;
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__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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return ret;
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__asm__ __volatile__(
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"sync; lbz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_8(volatile u8 *addr, int val)
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extern inline void out_8(volatile unsigned char __iomem *addr, int val)
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{
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__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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extern inline int in_le16(volatile u16 *addr)
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extern inline int in_le16(const volatile unsigned short __iomem *addr)
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{
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int ret;
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int ret;
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__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline int in_be16(volatile u16 *addr)
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extern inline int in_be16(const volatile unsigned short __iomem *addr)
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{
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int ret;
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int ret;
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__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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return ret;
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__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le16(volatile u16 *addr, int val)
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extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
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{
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__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
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"r" (val), "r" (addr));
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__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be16(volatile u16 *addr, int val)
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extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
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{
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__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
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}
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extern inline unsigned in_le32(volatile u32 *addr)
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extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
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{
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unsigned ret;
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unsigned ret;
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__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline unsigned in_be32(volatile u32 *addr)
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extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
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{
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unsigned ret;
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unsigned ret;
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__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
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return ret;
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__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le32(volatile unsigned *addr, int val)
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extern inline void out_le32(volatile unsigned __iomem *addr, int val)
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{
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__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
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"r" (val), "r" (addr));
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__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be32(volatile unsigned *addr, int val)
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extern inline void out_be32(volatile unsigned __iomem *addr, int val)
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{
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__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
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}
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#endif
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@@ -50,7 +50,7 @@
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
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#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
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@@ -104,14 +104,11 @@
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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/*
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* Define here the location of the environment variables (FLASH or EEPROM).
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* Note: DENX encourages to use redundant environment in FLASH.
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*/
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#if 1
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
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#endif
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/*-----------------------------------------------------------------------
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@@ -133,7 +130,7 @@
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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@@ -141,22 +138,89 @@
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*
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* IPL (Initial Program Loader, integrated inside CPU)
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* Will load first 4k from NAND (SPL) into cache and execute it from there.
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*
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* SPL (Secondary Program Loader)
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* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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* controller and the NAND controller so that the special U-Boot image can be
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* loaded from NAND to SDRAM.
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*
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* NUB (NAND U-Boot)
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* This NAND U-Boot (NUB) is a special U-Boot version which can be started
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* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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*
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* On 440EPx the SPL is copied to SDRAM before the NAND controller is
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* set up. While still running from cache, I experienced problems accessing
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* the NAND controller. sr - 2006-08-25
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*/
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
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#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
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/*
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* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
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*/
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#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
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#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
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#define CFG_NAND_ECCSIZE 256
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#define CFG_NAND_ECCBYTES 3
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#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
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#define CFG_NAND_OOBSIZE 16
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#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
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#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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#ifdef CFG_ENV_IS_IN_NAND
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
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*/
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#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
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#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_CS 1
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#define CFG_MAX_NAND_DEVICE 2
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#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
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#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
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#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_NAND_CS 1
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#else
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#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
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/* Memory Bank 0 (NAND-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x018003c0
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#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
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#endif
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------------- */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#undef CONFIG_DDR_ECC /* don't use ECC */
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#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
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#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
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#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
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#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
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/*-----------------------------------------------------------------------
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* I2C
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@@ -135,7 +135,8 @@
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
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#undef CONFIG_DDR_ECC /* no ECC support for now */
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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#define CFG_44x_DDR2_CKTR_180 1 /* use 180 deg advance */
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/*-----------------------------------------------------------------------
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* I2C
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@@ -168,12 +168,19 @@
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/*
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* Now the NAND chip has to be defined (no autodetection used!)
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*/
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#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
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#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
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#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
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#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
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#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
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#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
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#define CFG_NAND_ECCSIZE 256
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#define CFG_NAND_ECCBYTES 3
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#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
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#define CFG_NAND_OOBSIZE 16
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#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
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#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
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#ifdef CFG_ENV_IS_IN_NAND
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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@@ -80,16 +80,20 @@
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* This address, however, is used to configure a 256M local bus
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* window that includes the Config latch below.
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*/
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#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
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#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
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#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
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/* There are various flash options used, we configure for the largest,
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* which is 64Mbytes. The CFI works fine and will discover the proper
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* sizes.
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*/
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#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
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#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
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#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
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#ifdef CONFIG_STXSSA_4M
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#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
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#else
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#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
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#endif
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
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#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_CFI_DRIVER 1
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@@ -104,9 +108,9 @@
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/* The configuration latch is Chip Select 1.
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* It's an 8-bit latch in the lower 8 bits of the word.
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*/
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#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
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#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
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#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
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#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
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#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
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#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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@@ -300,17 +304,20 @@
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/* Environment - default config is in flash, see below */
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#if 0 /* in EEPROM */
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_OFFSET 0
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#define CFG_ENV_SIZE 2048
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# define CFG_ENV_IS_IN_EEPROM 1
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# define CFG_ENV_OFFSET 0
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# define CFG_ENV_SIZE 2048
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#else /* in flash */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SECT_SIZE 0x40000
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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# define CFG_ENV_IS_IN_FLASH 1
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# ifdef CONFIG_STXSSA_4M
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# define CFG_ENV_SECT_SIZE 0x20000
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# else /* default configuration - 64 MiB flash */
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# define CFG_ENV_SECT_SIZE 0x40000
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# endif
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# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
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# define CFG_ENV_SIZE 0x4000
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# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
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# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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