mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP
This commit is contained in:
Tom Rini
@@ -15,17 +15,8 @@
|
||||
#ifdef CONFIG_SPL_BUILD
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||||
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x930000
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/* For RAW image gives a error info not panic */
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#endif
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#define MEM_LAYOUT_ENV_SETTINGS \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"fdt_addr_r=0x50200000\0" \
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"scriptaddr=0x50280000\0" \
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"ramdisk_addr_r=0x50300000\0" \
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"kernel_comp_addr_r=0x40200000\0"
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/* Enable Distro Boot */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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@@ -34,45 +25,9 @@
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func(USB, usb, 1) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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MEM_LAYOUT_ENV_SETTINGS \
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"script=boot.scr\0" \
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"bootm_size=0x10000000\0" \
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"dev=2\0" \
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"preboot=gsc wd-disable\0" \
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"console=ttymxc1,115200\0" \
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"update_firmware=" \
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"tftpboot $loadaddr $image && " \
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"setexpr blkcnt $filesize + 0x1ff && " \
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"setexpr blkcnt $blkcnt / 0x200 && " \
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"mmc dev $dev && " \
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"mmc write $loadaddr 0x42 $blkcnt\0" \
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"loadfdt=" \
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"if $fsload $fdt_addr_r $dir/$fdt_file1; " \
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"then echo loaded $fdt_file1; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
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"then echo loaded $fdt_file2; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
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"then echo loaded $fdt_file3; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
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"then echo loaded $fdt_file4; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
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"then echo loaded $fdt_file5; " \
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"fi\0" \
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"boot_net=" \
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"setenv fsload tftpboot; " \
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"run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
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"booti $kernel_addr_r - $fdt_addr_r\0" \
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"update_rootfs=" \
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"tftpboot $loadaddr $image && " \
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"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
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"update_all=" \
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"tftpboot $loadaddr $image && " \
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"gzwrite mmc $dev $loadaddr $filesize\0" \
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"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
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"splblk=0x42\0" \
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BOOTENV
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
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@@ -83,8 +38,4 @@
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_4G
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/* FEC */
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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#endif
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@@ -12,14 +12,6 @@
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x184000
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/* For RAW image gives a error info not panic */
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#endif /* CONFIG_SPL_BUILD */
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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@@ -3,8 +3,8 @@
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* Copyright 2022 Gateworks Corporation
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*/
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#ifndef __IMX8MM_VENICE_H
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#define __IMX8MM_VENICE_H
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#ifndef __IMX8MN_VENICE_H
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#define __IMX8MN_VENICE_H
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#include <asm/arch/imx-regs.h>
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#include <linux/sizes.h>
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@@ -12,17 +12,6 @@
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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/* For RAW image gives a error info not panic */
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#endif
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#define MEM_LAYOUT_ENV_SETTINGS \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"fdt_addr_r=0x50200000\0" \
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||||
"scriptaddr=0x50280000\0" \
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"ramdisk_addr_r=0x50300000\0" \
|
||||
"kernel_comp_addr_r=0x40200000\0"
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||||
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/* Enable Distro Boot */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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@@ -30,45 +19,9 @@
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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||||
BOOTENV \
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MEM_LAYOUT_ENV_SETTINGS \
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"script=boot.scr\0" \
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"bootm_size=0x10000000\0" \
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||||
"dev=2\0" \
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||||
"preboot=gsc wd-disable\0" \
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||||
"console=ttymxc1,115200\0" \
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"update_firmware=" \
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||||
"tftpboot $loadaddr $image && " \
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||||
"setexpr blkcnt $filesize + 0x1ff && " \
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"setexpr blkcnt $blkcnt / 0x200 && " \
|
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"mmc dev $dev && " \
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"mmc write $loadaddr 0x40 $blkcnt\0" \
|
||||
"loadfdt=" \
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"if $fsload $fdt_addr_r $dir/$fdt_file1; " \
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"then echo loaded $fdt_file1; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
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"then echo loaded $fdt_file2; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
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||||
"then echo loaded $fdt_file3; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
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"then echo loaded $fdt_file4; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
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"then echo loaded $fdt_file5; " \
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"fi\0" \
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"boot_net=" \
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"setenv fsload tftpboot; " \
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"run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
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"booti $kernel_addr_r - $fdt_addr_r\0" \
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"update_rootfs=" \
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"tftpboot $loadaddr $image && " \
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"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
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"update_all=" \
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"tftpboot $loadaddr $image && " \
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"gzwrite mmc $dev $loadaddr $filesize\0" \
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"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
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"splblk=0x40\0" \
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BOOTENV
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
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@@ -79,8 +32,4 @@
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE SZ_4G
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/* FEC */
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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#endif
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@@ -12,17 +12,6 @@
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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/* For RAW image gives a error info not panic */
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#endif
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#define MEM_LAYOUT_ENV_SETTINGS \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"fdt_addr_r=0x50200000\0" \
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||||
"scriptaddr=0x50280000\0" \
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"ramdisk_addr_r=0x50300000\0" \
|
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"kernel_comp_addr_r=0x40200000\0"
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/* Enable Distro Boot */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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@@ -30,45 +19,9 @@
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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|
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/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
BOOTENV \
|
||||
MEM_LAYOUT_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"dev=2\0" \
|
||||
"preboot=gsc wd-disable\0" \
|
||||
"console=ttymxc1,115200\0" \
|
||||
"update_firmware=" \
|
||||
"tftpboot $loadaddr $image && " \
|
||||
"setexpr blkcnt $filesize + 0x1ff && " \
|
||||
"setexpr blkcnt $blkcnt / 0x200 && " \
|
||||
"mmc dev $dev && " \
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"mmc write $loadaddr 0x40 $blkcnt\0" \
|
||||
"loadfdt=" \
|
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"if $fsload $fdt_addr_r $dir/$fdt_file1; " \
|
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"then echo loaded $fdt_file1; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
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"then echo loaded $fdt_file2; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
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"then echo loaded $fdt_file3; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
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"then echo loaded $fdt_file4; " \
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"elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
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"then echo loaded $fdt_file5; " \
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"fi\0" \
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"boot_net=" \
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"setenv fsload tftpboot; " \
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"run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
|
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"booti $kernel_addr_r - $fdt_addr_r\0" \
|
||||
"update_rootfs=" \
|
||||
"tftpboot $loadaddr $image && " \
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||||
"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
|
||||
"update_all=" \
|
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"tftpboot $loadaddr $image && " \
|
||||
"gzwrite mmc $dev $loadaddr $filesize\0" \
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||||
"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
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"splblk=0x40\0" \
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BOOTENV
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
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63
include/configs/msc_sm2s_imx8mp.h
Normal file
63
include/configs/msc_sm2s_imx8mp.h
Normal file
@@ -0,0 +1,63 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Based on vendor support provided by AVNET Embedded
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*
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* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
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* Copyright 2021 General Electric Company
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* Copyright 2021 Collabora Ltd.
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*/
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#ifndef __MSC_SM2S_IMX8MP_H
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#define __MSC_SM2S_IMX8MP_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
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|
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#if defined(CONFIG_CMD_NET)
|
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#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
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#endif
|
||||
|
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#ifndef CONFIG_SPL_BUILD
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
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func(MMC, mmc, 2)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#endif
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
BOOTENV \
|
||||
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc1,115200\0" \
|
||||
"fdt_addr_r=0x43000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
||||
|
||||
/* Link Definitions */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
|
||||
#define PHYS_SDRAM_2 0xc0000000
|
||||
#define PHYS_SDRAM_2_SIZE 0x0
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
|
||||
|
||||
#define CFG_SYS_FSL_USDHC_NUM 2
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#endif
|
||||
@@ -117,7 +117,6 @@
|
||||
#define IMX8MP_CLK_AUDIO_AHB 108
|
||||
#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
|
||||
#define IMX8MP_CLK_IPG_ROOT 110
|
||||
#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
|
||||
#define IMX8MP_CLK_DRAM_ALT 112
|
||||
#define IMX8MP_CLK_DRAM_APB 113
|
||||
#define IMX8MP_CLK_VPU_G1 114
|
||||
@@ -125,7 +124,6 @@
|
||||
#define IMX8MP_CLK_CAN1 116
|
||||
#define IMX8MP_CLK_CAN2 117
|
||||
#define IMX8MP_CLK_MEMREPAIR 118
|
||||
#define IMX8MP_CLK_PCIE_PHY 119
|
||||
#define IMX8MP_CLK_PCIE_AUX 120
|
||||
#define IMX8MP_CLK_I2C5 121
|
||||
#define IMX8MP_CLK_I2C6 122
|
||||
@@ -182,8 +180,6 @@
|
||||
#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
|
||||
#define IMX8MP_CLK_MEDIA_LDB 174
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
|
||||
#define IMX8MP_CLK_PCIE2_CTRL 176
|
||||
#define IMX8MP_CLK_PCIE2_PHY 177
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
|
||||
#define IMX8MP_CLK_ECSPI3 179
|
||||
#define IMX8MP_CLK_PDM 180
|
||||
@@ -321,8 +317,15 @@
|
||||
#define IMX8MP_CLK_AUDIO_AXI 310
|
||||
#define IMX8MP_CLK_HSIO_AXI 311
|
||||
#define IMX8MP_CLK_MEDIA_ISP 312
|
||||
#define IMX8MP_CLK_MEDIA_DISP2_PIX 313
|
||||
#define IMX8MP_CLK_CLKOUT1_SEL 314
|
||||
#define IMX8MP_CLK_CLKOUT1_DIV 315
|
||||
#define IMX8MP_CLK_CLKOUT1 316
|
||||
#define IMX8MP_CLK_CLKOUT2_SEL 317
|
||||
#define IMX8MP_CLK_CLKOUT2_DIV 318
|
||||
#define IMX8MP_CLK_CLKOUT2 319
|
||||
|
||||
#define IMX8MP_CLK_END 313
|
||||
#define IMX8MP_CLK_END 320
|
||||
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
|
||||
|
||||
@@ -1,16 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
|
||||
/*
|
||||
* Copyright 2020 NXP
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8ULP_H
|
||||
|
||||
#define IMX8ULP_CLK_DUMMY 0
|
||||
#define IMX8ULP_CLK_ROSC 1
|
||||
#define IMX8ULP_CLK_FROSC 2
|
||||
#define IMX8ULP_CLK_LPOSC 3
|
||||
#define IMX8ULP_CLK_SOSC 4
|
||||
|
||||
/* CGC1 */
|
||||
#define IMX8ULP_CLK_SPLL2 5
|
||||
#define IMX8ULP_CLK_SPLL3 6
|
||||
#define IMX8ULP_CLK_A35_SEL 7
|
||||
@@ -57,14 +55,15 @@
|
||||
#define IMX8ULP_CLK_FROSC_DIV1_GATE 48
|
||||
#define IMX8ULP_CLK_FROSC_DIV2_GATE 49
|
||||
#define IMX8ULP_CLK_FROSC_DIV3_GATE 50
|
||||
#define IMX8ULP_CLK_ENETSTAMP_SEL 51
|
||||
#define IMX8ULP_CLK_SAI4_SEL 52
|
||||
#define IMX8ULP_CLK_SAI5_SEL 53
|
||||
#define IMX8ULP_CLK_AUD_CLK1 54
|
||||
#define IMX8ULP_CLK_ARM 55
|
||||
#define IMX8ULP_CLK_SAI4_SEL 51
|
||||
#define IMX8ULP_CLK_SAI5_SEL 52
|
||||
#define IMX8ULP_CLK_AUD_CLK1 53
|
||||
#define IMX8ULP_CLK_ARM 54
|
||||
#define IMX8ULP_CLK_ENET_TS_SEL 55
|
||||
|
||||
#define IMX8ULP_CLK_CGC1_END 56
|
||||
|
||||
/* CGC2 */
|
||||
#define IMX8ULP_CLK_PLL4_PRE_SEL 0
|
||||
#define IMX8ULP_CLK_PLL4 1
|
||||
#define IMX8ULP_CLK_PLL4_VCODIV 2
|
||||
@@ -110,8 +109,12 @@
|
||||
#define IMX8ULP_CLK_SAI6_SEL 42
|
||||
#define IMX8ULP_CLK_SAI7_SEL 43
|
||||
#define IMX8ULP_CLK_SPDIF_SEL 44
|
||||
#define IMX8ULP_CLK_HIFI_SEL 45
|
||||
#define IMX8ULP_CLK_HIFI_DIVCORE 46
|
||||
#define IMX8ULP_CLK_HIFI_DIVPLAT 47
|
||||
#define IMX8ULP_CLK_DSI_PHY_REF 48
|
||||
|
||||
#define IMX8ULP_CLK_CGC2_END 45
|
||||
#define IMX8ULP_CLK_CGC2_END 49
|
||||
|
||||
/* PCC3 */
|
||||
#define IMX8ULP_CLK_WDOG3 0
|
||||
@@ -160,9 +163,12 @@
|
||||
#define IMX8ULP_CLK_DMA1_CH29 43
|
||||
#define IMX8ULP_CLK_DMA1_CH30 44
|
||||
#define IMX8ULP_CLK_DMA1_CH31 45
|
||||
#define IMX8ULP_CLK_MU3_A 46
|
||||
#define IMX8ULP_CLK_MU0_B 47
|
||||
|
||||
#define IMX8ULP_CLK_PCC3_END 46
|
||||
#define IMX8ULP_CLK_PCC3_END 48
|
||||
|
||||
/* PCC4 */
|
||||
#define IMX8ULP_CLK_FLEXSPI2 0
|
||||
#define IMX8ULP_CLK_TPM6 1
|
||||
#define IMX8ULP_CLK_TPM7 2
|
||||
@@ -189,24 +195,25 @@
|
||||
|
||||
#define IMX8ULP_CLK_PCC4_END 23
|
||||
|
||||
/* PCC5 */
|
||||
#define IMX8ULP_CLK_TPM8 0
|
||||
#define IMX8ULP_CLK_SAI6 1
|
||||
#define IMX8ULP_CLK_SAI7 2
|
||||
#define IMX8ULP_CLK_SPDIF 3
|
||||
#define IMX8ULP_CLK_ISI 4
|
||||
#define IMX8ULP_CLK_CSI_REGS 5
|
||||
#define IMX8ULP_CLK_ISI 4
|
||||
#define IMX8ULP_CLK_CSI_REGS 5
|
||||
#define IMX8ULP_CLK_PCTLD 6
|
||||
#define IMX8ULP_CLK_CSI 7
|
||||
#define IMX8ULP_CLK_DSI 8
|
||||
#define IMX8ULP_CLK_CSI 7
|
||||
#define IMX8ULP_CLK_DSI 8
|
||||
#define IMX8ULP_CLK_WDOG5 9
|
||||
#define IMX8ULP_CLK_EPDC 10
|
||||
#define IMX8ULP_CLK_PXP 11
|
||||
#define IMX8ULP_CLK_PXP 11
|
||||
#define IMX8ULP_CLK_SFA2 12
|
||||
#define IMX8ULP_CLK_GPU2D 13
|
||||
#define IMX8ULP_CLK_GPU3D 14
|
||||
#define IMX8ULP_CLK_DC_NANO 15
|
||||
#define IMX8ULP_CLK_CSI_CLK_UI 16
|
||||
#define IMX8ULP_CLK_CSI_CLK_ESC 17
|
||||
#define IMX8ULP_CLK_CSI_CLK_UI 16
|
||||
#define IMX8ULP_CLK_CSI_CLK_ESC 17
|
||||
#define IMX8ULP_CLK_RGPIOD 18
|
||||
#define IMX8ULP_CLK_DMA2_MP 19
|
||||
#define IMX8ULP_CLK_DMA2_CH0 20
|
||||
@@ -241,7 +248,11 @@
|
||||
#define IMX8ULP_CLK_DMA2_CH29 49
|
||||
#define IMX8ULP_CLK_DMA2_CH30 50
|
||||
#define IMX8ULP_CLK_DMA2_CH31 51
|
||||
#define IMX8ULP_CLK_MU2_B 52
|
||||
#define IMX8ULP_CLK_MU3_B 53
|
||||
#define IMX8ULP_CLK_AVD_SIM 54
|
||||
#define IMX8ULP_CLK_DSI_TX_ESC 55
|
||||
|
||||
#define IMX8ULP_CLK_PCC5_END 52
|
||||
#define IMX8ULP_CLK_PCC5_END 56
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright(C) 2019
|
||||
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
@@ -62,6 +62,11 @@
|
||||
#define IMXRT1050_CLK_PLL7_USB_HOST 53
|
||||
#define IMXRT1050_CLK_LCDIF_PIX 54
|
||||
#define IMXRT1050_CLK_USBOH3 55
|
||||
#define IMXRT1050_CLK_END 56
|
||||
#define IMXRT1050_CLK_IPG_PDOF 56
|
||||
#define IMXRT1050_CLK_PER_CLK_SEL 57
|
||||
#define IMXRT1050_CLK_PER_PDOF 58
|
||||
#define IMXRT1050_CLK_DMA 59
|
||||
#define IMXRT1050_CLK_DMA_MUX 60
|
||||
#define IMXRT1050_CLK_END 61
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
|
||||
|
||||
59
include/dt-bindings/interconnect/fsl,imx8mp.h
Normal file
59
include/dt-bindings/interconnect/fsl,imx8mp.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* Interconnect framework driver for i.MX SoC
|
||||
*
|
||||
* Copyright 2022 NXP
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H
|
||||
|
||||
#define IMX8MP_ICN_NOC 0
|
||||
#define IMX8MP_ICN_MAIN 1
|
||||
#define IMX8MP_ICS_DRAM 2
|
||||
#define IMX8MP_ICS_OCRAM 3
|
||||
#define IMX8MP_ICM_A53 4
|
||||
#define IMX8MP_ICM_SUPERMIX 5
|
||||
#define IMX8MP_ICM_GIC 6
|
||||
#define IMX8MP_ICM_MLMIX 7
|
||||
|
||||
#define IMX8MP_ICN_AUDIO 8
|
||||
#define IMX8MP_ICM_DSP 9
|
||||
#define IMX8MP_ICM_SDMA2PER 10
|
||||
#define IMX8MP_ICM_SDMA2BURST 11
|
||||
#define IMX8MP_ICM_SDMA3PER 12
|
||||
#define IMX8MP_ICM_SDMA3BURST 13
|
||||
#define IMX8MP_ICM_EDMA 14
|
||||
|
||||
#define IMX8MP_ICN_GPU 15
|
||||
#define IMX8MP_ICM_GPU2D 16
|
||||
#define IMX8MP_ICM_GPU3D 17
|
||||
|
||||
#define IMX8MP_ICN_HDMI 18
|
||||
#define IMX8MP_ICM_HRV 19
|
||||
#define IMX8MP_ICM_LCDIF_HDMI 20
|
||||
#define IMX8MP_ICM_HDCP 21
|
||||
|
||||
#define IMX8MP_ICN_HSIO 22
|
||||
#define IMX8MP_ICM_NOC_PCIE 23
|
||||
#define IMX8MP_ICM_USB1 24
|
||||
#define IMX8MP_ICM_USB2 25
|
||||
#define IMX8MP_ICM_PCIE 26
|
||||
|
||||
#define IMX8MP_ICN_MEDIA 27
|
||||
#define IMX8MP_ICM_LCDIF_RD 28
|
||||
#define IMX8MP_ICM_LCDIF_WR 29
|
||||
#define IMX8MP_ICM_ISI0 30
|
||||
#define IMX8MP_ICM_ISI1 31
|
||||
#define IMX8MP_ICM_ISI2 32
|
||||
#define IMX8MP_ICM_ISP0 33
|
||||
#define IMX8MP_ICM_ISP1 34
|
||||
#define IMX8MP_ICM_DWE 35
|
||||
|
||||
#define IMX8MP_ICN_VIDEO 36
|
||||
#define IMX8MP_ICM_VPU_G1 37
|
||||
#define IMX8MP_ICM_VPU_G2 38
|
||||
#define IMX8MP_ICM_VPU_H1 39
|
||||
|
||||
#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */
|
||||
50
include/dt-bindings/interconnect/imx8mm.h
Normal file
50
include/dt-bindings/interconnect/imx8mm.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Interconnect framework driver for i.MX SoC
|
||||
*
|
||||
* Copyright (c) 2019, BayLibre
|
||||
* Copyright (c) 2019-2020, NXP
|
||||
* Author: Alexandre Bailon <abailon@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H
|
||||
|
||||
#define IMX8MM_ICN_NOC 1
|
||||
#define IMX8MM_ICS_DRAM 2
|
||||
#define IMX8MM_ICS_OCRAM 3
|
||||
#define IMX8MM_ICM_A53 4
|
||||
|
||||
#define IMX8MM_ICM_VPU_H1 5
|
||||
#define IMX8MM_ICM_VPU_G1 6
|
||||
#define IMX8MM_ICM_VPU_G2 7
|
||||
#define IMX8MM_ICN_VIDEO 8
|
||||
|
||||
#define IMX8MM_ICM_GPU2D 9
|
||||
#define IMX8MM_ICM_GPU3D 10
|
||||
#define IMX8MM_ICN_GPU 11
|
||||
|
||||
#define IMX8MM_ICM_CSI 12
|
||||
#define IMX8MM_ICM_LCDIF 13
|
||||
#define IMX8MM_ICN_MIPI 14
|
||||
|
||||
#define IMX8MM_ICM_USB1 15
|
||||
#define IMX8MM_ICM_USB2 16
|
||||
#define IMX8MM_ICM_PCIE 17
|
||||
#define IMX8MM_ICN_HSIO 18
|
||||
|
||||
#define IMX8MM_ICM_SDMA2 19
|
||||
#define IMX8MM_ICM_SDMA3 20
|
||||
#define IMX8MM_ICN_AUDIO 21
|
||||
|
||||
#define IMX8MM_ICN_ENET 22
|
||||
#define IMX8MM_ICM_ENET 23
|
||||
|
||||
#define IMX8MM_ICN_MAIN 24
|
||||
#define IMX8MM_ICM_NAND 25
|
||||
#define IMX8MM_ICM_SDMA1 26
|
||||
#define IMX8MM_ICM_USDHC1 27
|
||||
#define IMX8MM_ICM_USDHC2 28
|
||||
#define IMX8MM_ICM_USDHC3 29
|
||||
|
||||
#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */
|
||||
41
include/dt-bindings/interconnect/imx8mn.h
Normal file
41
include/dt-bindings/interconnect/imx8mn.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Interconnect framework driver for i.MX SoC
|
||||
*
|
||||
* Copyright (c) 2019-2020, NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H
|
||||
|
||||
#define IMX8MN_ICN_NOC 1
|
||||
#define IMX8MN_ICS_DRAM 2
|
||||
#define IMX8MN_ICS_OCRAM 3
|
||||
#define IMX8MN_ICM_A53 4
|
||||
|
||||
#define IMX8MN_ICM_GPU 5
|
||||
#define IMX8MN_ICN_GPU 6
|
||||
|
||||
#define IMX8MN_ICM_CSI1 7
|
||||
#define IMX8MN_ICM_CSI2 8
|
||||
#define IMX8MN_ICM_ISI 9
|
||||
#define IMX8MN_ICM_LCDIF 10
|
||||
#define IMX8MN_ICN_MIPI 11
|
||||
|
||||
#define IMX8MN_ICM_USB 12
|
||||
|
||||
#define IMX8MN_ICM_SDMA2 13
|
||||
#define IMX8MN_ICM_SDMA3 14
|
||||
#define IMX8MN_ICN_AUDIO 15
|
||||
|
||||
#define IMX8MN_ICN_ENET 16
|
||||
#define IMX8MN_ICM_ENET 17
|
||||
|
||||
#define IMX8MN_ICM_NAND 18
|
||||
#define IMX8MN_ICM_SDMA1 19
|
||||
#define IMX8MN_ICM_USDHC1 20
|
||||
#define IMX8MN_ICM_USDHC2 21
|
||||
#define IMX8MN_ICM_USDHC3 22
|
||||
#define IMX8MN_ICN_MAIN 23
|
||||
|
||||
#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */
|
||||
@@ -38,9 +38,22 @@
|
||||
#define IMX8MP_MEDIABLK_PD_ISI 3
|
||||
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
|
||||
#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
|
||||
#define IMX8MP_MEDIABLK_PD_ISP2 6
|
||||
#define IMX8MP_MEDIABLK_PD_ISP1 7
|
||||
#define IMX8MP_MEDIABLK_PD_DWE 8
|
||||
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9
|
||||
#define IMX8MP_MEDIABLK_PD_ISP 6
|
||||
#define IMX8MP_MEDIABLK_PD_DWE 7
|
||||
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
|
||||
|
||||
#define IMX8MP_HDMIBLK_PD_IRQSTEER 0
|
||||
#define IMX8MP_HDMIBLK_PD_LCDIF 1
|
||||
#define IMX8MP_HDMIBLK_PD_PAI 2
|
||||
#define IMX8MP_HDMIBLK_PD_PVI 3
|
||||
#define IMX8MP_HDMIBLK_PD_TRNG 4
|
||||
#define IMX8MP_HDMIBLK_PD_HDMI_TX 5
|
||||
#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
|
||||
#define IMX8MP_HDMIBLK_PD_HDCP 7
|
||||
#define IMX8MP_HDMIBLK_PD_HRV 8
|
||||
|
||||
#define IMX8MP_VPUBLK_PD_G1 0
|
||||
#define IMX8MP_VPUBLK_PD_G2 1
|
||||
#define IMX8MP_VPUBLK_PD_VC8000E 2
|
||||
|
||||
#endif
|
||||
|
||||
26
include/dt-bindings/power/imx8ulp-power.h
Normal file
26
include/dt-bindings/power/imx8ulp-power.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__
|
||||
#define __DT_BINDINGS_IMX8ULP_POWER_H__
|
||||
|
||||
#define IMX8ULP_PD_DMA1 0
|
||||
#define IMX8ULP_PD_FLEXSPI2 1
|
||||
#define IMX8ULP_PD_USB0 2
|
||||
#define IMX8ULP_PD_USDHC0 3
|
||||
#define IMX8ULP_PD_USDHC1 4
|
||||
#define IMX8ULP_PD_USDHC2_USB1 5
|
||||
#define IMX8ULP_PD_DCNANO 6
|
||||
#define IMX8ULP_PD_EPDC 7
|
||||
#define IMX8ULP_PD_DMA2 8
|
||||
#define IMX8ULP_PD_GPU2D 9
|
||||
#define IMX8ULP_PD_GPU3D 10
|
||||
#define IMX8ULP_PD_HIFI4 11
|
||||
#define IMX8ULP_PD_ISI 12
|
||||
#define IMX8ULP_PD_MIPI_CSI 13
|
||||
#define IMX8ULP_PD_MIPI_DSI 14
|
||||
#define IMX8ULP_PD_PXP 15
|
||||
|
||||
#endif
|
||||
50
include/dt-bindings/reset/imx8mp-reset.h
Normal file
50
include/dt-bindings/reset/imx8mp-reset.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2020 NXP
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDING_RESET_IMX8MP_H
|
||||
#define DT_BINDING_RESET_IMX8MP_H
|
||||
|
||||
#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
|
||||
#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
|
||||
#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
|
||||
#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
|
||||
#define IMX8MP_RESET_A53_CORE_RESET0 4
|
||||
#define IMX8MP_RESET_A53_CORE_RESET1 5
|
||||
#define IMX8MP_RESET_A53_CORE_RESET2 6
|
||||
#define IMX8MP_RESET_A53_CORE_RESET3 7
|
||||
#define IMX8MP_RESET_A53_DBG_RESET0 8
|
||||
#define IMX8MP_RESET_A53_DBG_RESET1 9
|
||||
#define IMX8MP_RESET_A53_DBG_RESET2 10
|
||||
#define IMX8MP_RESET_A53_DBG_RESET3 11
|
||||
#define IMX8MP_RESET_A53_ETM_RESET0 12
|
||||
#define IMX8MP_RESET_A53_ETM_RESET1 13
|
||||
#define IMX8MP_RESET_A53_ETM_RESET2 14
|
||||
#define IMX8MP_RESET_A53_ETM_RESET3 15
|
||||
#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
|
||||
#define IMX8MP_RESET_A53_L2RESET 17
|
||||
#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
|
||||
#define IMX8MP_RESET_OTG1_PHY_RESET 19
|
||||
#define IMX8MP_RESET_OTG2_PHY_RESET 20
|
||||
#define IMX8MP_RESET_SUPERMIX_RESET 21
|
||||
#define IMX8MP_RESET_AUDIOMIX_RESET 22
|
||||
#define IMX8MP_RESET_MLMIX_RESET 23
|
||||
#define IMX8MP_RESET_PCIEPHY 24
|
||||
#define IMX8MP_RESET_PCIEPHY_PERST 25
|
||||
#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
|
||||
#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
|
||||
#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
|
||||
#define IMX8MP_RESET_MEDIA_RESET 29
|
||||
#define IMX8MP_RESET_GPU2D_RESET 30
|
||||
#define IMX8MP_RESET_GPU3D_RESET 31
|
||||
#define IMX8MP_RESET_GPU_RESET 32
|
||||
#define IMX8MP_RESET_VPU_RESET 33
|
||||
#define IMX8MP_RESET_VPU_G1_RESET 34
|
||||
#define IMX8MP_RESET_VPU_G2_RESET 35
|
||||
#define IMX8MP_RESET_VPUVC8KE_RESET 36
|
||||
#define IMX8MP_RESET_NOC_RESET 37
|
||||
|
||||
#define IMX8MP_RESET_NUM 38
|
||||
|
||||
#endif
|
||||
@@ -28,37 +28,40 @@
|
||||
#define IMX8MQ_RESET_A53_L2RESET 17
|
||||
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
|
||||
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
|
||||
#define IMX8MQ_RESET_OTG2_PHY_RESET 20
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
|
||||
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
|
||||
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
|
||||
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
|
||||
#define IMX8MQ_RESET_PCIEPHY 26
|
||||
#define IMX8MQ_RESET_PCIEPHY_PERST 27
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
|
||||
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DISP_RESET 31
|
||||
#define IMX8MQ_RESET_GPU_RESET 32
|
||||
#define IMX8MQ_RESET_VPU_RESET 33
|
||||
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PRST 44
|
||||
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
|
||||
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
|
||||
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_SW_M4C_RST 50
|
||||
#define IMX8MQ_RESET_SW_M4P_RST 51
|
||||
#define IMX8MQ_RESET_M4_ENABLE 52
|
||||
|
||||
#define IMX8MQ_RESET_NUM 50
|
||||
#define IMX8MQ_RESET_NUM 53
|
||||
|
||||
#endif
|
||||
|
||||
59
include/dt-bindings/reset/imx8ulp-pcc-reset.h
Normal file
59
include/dt-bindings/reset/imx8ulp-pcc-reset.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
|
||||
#define DT_BINDING_PCC_RESET_IMX8ULP_H
|
||||
|
||||
/* PCC3 */
|
||||
#define PCC3_WDOG3_SWRST 0
|
||||
#define PCC3_WDOG4_SWRST 1
|
||||
#define PCC3_LPIT1_SWRST 2
|
||||
#define PCC3_TPM4_SWRST 3
|
||||
#define PCC3_TPM5_SWRST 4
|
||||
#define PCC3_FLEXIO1_SWRST 5
|
||||
#define PCC3_I3C2_SWRST 6
|
||||
#define PCC3_LPI2C4_SWRST 7
|
||||
#define PCC3_LPI2C5_SWRST 8
|
||||
#define PCC3_LPUART4_SWRST 9
|
||||
#define PCC3_LPUART5_SWRST 10
|
||||
#define PCC3_LPSPI4_SWRST 11
|
||||
#define PCC3_LPSPI5_SWRST 12
|
||||
|
||||
/* PCC4 */
|
||||
#define PCC4_FLEXSPI2_SWRST 0
|
||||
#define PCC4_TPM6_SWRST 1
|
||||
#define PCC4_TPM7_SWRST 2
|
||||
#define PCC4_LPI2C6_SWRST 3
|
||||
#define PCC4_LPI2C7_SWRST 4
|
||||
#define PCC4_LPUART6_SWRST 5
|
||||
#define PCC4_LPUART7_SWRST 6
|
||||
#define PCC4_SAI4_SWRST 7
|
||||
#define PCC4_SAI5_SWRST 8
|
||||
#define PCC4_USDHC0_SWRST 9
|
||||
#define PCC4_USDHC1_SWRST 10
|
||||
#define PCC4_USDHC2_SWRST 11
|
||||
#define PCC4_USB0_SWRST 12
|
||||
#define PCC4_USB0_PHY_SWRST 13
|
||||
#define PCC4_USB1_SWRST 14
|
||||
#define PCC4_USB1_PHY_SWRST 15
|
||||
#define PCC4_ENET_SWRST 16
|
||||
|
||||
/* PCC5 */
|
||||
#define PCC5_TPM8_SWRST 0
|
||||
#define PCC5_SAI6_SWRST 1
|
||||
#define PCC5_SAI7_SWRST 2
|
||||
#define PCC5_SPDIF_SWRST 3
|
||||
#define PCC5_ISI_SWRST 4
|
||||
#define PCC5_CSI_REGS_SWRST 5
|
||||
#define PCC5_CSI_SWRST 6
|
||||
#define PCC5_DSI_SWRST 7
|
||||
#define PCC5_WDOG5_SWRST 8
|
||||
#define PCC5_EPDC_SWRST 9
|
||||
#define PCC5_PXP_SWRST 10
|
||||
#define PCC5_GPU2D_SWRST 11
|
||||
#define PCC5_GPU3D_SWRST 12
|
||||
#define PCC5_DC_NANO_SWRST 13
|
||||
|
||||
#endif /*DT_BINDING_RESET_IMX8ULP_H */
|
||||
Reference in New Issue
Block a user