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rockchip: px30: Add support for using UART3 as debug UART

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Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.

Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1).

Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
This commit is contained in:
Paul Kocialkowski
2019-11-28 15:27:52 +01:00
committed by Kever Yang
parent ec4fafdf1f
commit c541bfda2f
2 changed files with 96 additions and 0 deletions
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19
arch/arm/include/asm/arch-rockchip/cru_px30.h
View File

@@ -357,6 +357,25 @@ enum {
UART2_DIVNP5_SHIFT = 0,
UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
/* CRU_CLK_SEL40_CON */
UART3_PLL_SEL_SHIFT = 14,
UART3_PLL_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
UART3_PLL_SEL_GPLL = 0,
UART3_PLL_SEL_24M,
UART3_PLL_SEL_480M,
UART3_PLL_SEL_NPLL,
UART3_DIV_CON_SHIFT = 0,
UART3_DIV_CON_MASK = 0x1f << UART3_DIV_CON_SHIFT,
/* CRU_CLK_SEL41_CON */
UART3_CLK_SEL_SHIFT = 14,
UART3_CLK_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
UART3_CLK_SEL_UART3 = 0,
UART3_CLK_SEL_UART3_NP5,
UART3_CLK_SEL_UART3_FRAC,
UART3_DIVNP5_SHIFT = 0,
UART3_DIVNP5_MASK = 0x1f << UART3_DIVNP5_SHIFT,
/* CRU_CLK_SEL46_CON */
UART5_PLL_SEL_SHIFT = 14,
UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,